935311645557_技术文档

Freescale Semiconductor, Inc.

Data Sheet: Technical Data

KV31P100M100SF9

Rev. 7, 02/2016

Kinetis KV31F 128KB Flash

MKV31F128VLL10

MKV31F128VLH10

MKV31F128VLH10P

100 MHz ARM® Cortex®-M4 Based Microcontroller with FPU

The KV31 MCU family is a highly scalable member of the Kinetis

V series and provides a high-performance, cost-competitive,

motor-control solution. Built on the ARM^®Cortex^®-M4 core

running at 100 MHz, combined with floating point and DSP

capability, it delivers a highly capable platform enabling

customers to build a highly scalable solution portfolio.

Additional features include:

100 LQFP (LL)

14 x 14 x 1.4 Pitch 0.5 10 x 10 x 1.4 Pitch 0.5

mm mm

64 LQFP (LH)

• Dual 16-bit ADCs sampling at up to 1.2 MS/s in 12-bit

mode

• 12 channels of highly flexible motor-control timers (PWMs)

across three independent time bases

• Large RAM block enabling local execution of fast control

loops at full clock speed

• Enabled to support Kinetis Motor Suite (KMS), a bundled hardware and software solution that enables

rapid configuration of BLDC and PMSM motor drive systems

Performance

• 100 MHz ARM Cortex-M4 core with DSP instructions

Analog modules

• Two 16-bit SAR ADCs (1.2 MS/s in 12bit mode)

• One 12-bit DAC

delivering 1.25 Dhrystone MIPS per MHz

• Two analog comparators (CMP) with 6-bit DAC

• Accurate internal voltage reference

Memories and memory interfaces

• 128 KB of embedded flash and 24 KB of RAM

• Pre-programmed Kinetis flashloader for one-time, in-

system factory programming

Communication interfaces

• Two SPI modules

• Three UART modules and one low-power UART

• Two I2C: Support for up to 1 Mbps operation

System peripherals

• 4-channel DMA controller

• Independent External and Software Watchdog monitor Timers

• One 8-channel motor-control general-purpose/PWM

Clocks

• One crystal oscillator with two ranges: 32-40 kHz or

timer

• Two 2-channel motor-control general-purpose

timers with quadrature decoder functionality

3-32 MHz

• Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz

• Multi-purpose clock generator with FLL

Operating Characteristics

• Voltage range (including flash writes): 1.71 to 3.6 V

• Temperature range (ambient): -40 to 105°C

Security and integrity modules

• Hardware CRC module

• 128-bit unique identification (ID) number per chip

• Flash access control to protect proprietary software

Kinetis Motor Suite

• Supports Velocity and Position control of BLDC &

PMSM motors

Human-machine interface

• Up to 70 general-purpose I/O (GPIO)

• Implements Field Orient Control (FOC) using Back

EMF to improve motor efficiency

• Utilizes SpinTAC control theory that improves

overall system performance and reliability

Ordering Information

Part Number

Memory

Number of GPIOs

Flash (KB)

SRAM (KB)

MKV31F128VLL10

MKV31F128VLH10

MKV31F128VLH10P

128

120

24

70

46

Related Resources

Type

Description

Resource

Selector

Guide

The Freescale Solution Advisor is a web-based tool that features

interactive application wizards and a dynamic product selector

Product Selector

Product Brief The Product Brief contains concise overview/summary information to

enable quick evaluation of a device for design suitability.

KV30FKV31FPB

Reference

Manual

The Reference Manual contains a comprehensive description of the

structure and function (operation) of a device.

KV31P100M100SF9RM

KV31P100M100SF9

Data Sheet

The Data Sheet is this document. It includes electrical characteristics

and signal connections.

Chip Errata

The chip mask set Errata provides additional or corrective information for KINETIS_xN74M ¹

a particular device mask set.

KMS User

Guide

The KMS User Guide provides a comprehensive description of the

features and functions of the Kinetis Motor Suite solution.

Kinetis Motor Suite User’s Guide

(KMS100UG)²

KMS API

Reference

Manual

The KMS API reference manual provides a comprehensive description of Kinetis Motor Suite API

the API of the Kinetis Motor Suite function blocks.

Reference Manual

(KMS100RM)²

Package

drawing

Package dimensions are provided by part number:

• MKV31F128VLL10

Package drawing:

• 98ASS23308W

• 98ASS23234W

• MKV31F128VLH10

• MKV31F128VLH10P

1. To find the associated resource, go to freescale.com and perform a search using this term with the x replaced by the

revision of the device you are using.

2. To find the associated resource, go to freescale.com and perform a search using Document ID

Figure 1 shows the functional modules in the chip.

2

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

Freescale Semiconductor, Inc.

ARM^®Cortex™-M4

Core

System

Memories and Memory Interfaces

Clocks

Program

RAM

Frequency-

locked loop

flash

DMA (4 ch)

Debug

(24 KB)

(128 KB)

DSP

FPU

interfaces

Low-leakage

wakeup

Low/high

frequency

oscillators

Serial

programming

Interrupt

interface

(EzPort)

controller

Internal

and external

watchdogs

Internal

reference

clocks

Security

and Integrity

Communication Interfaces

Human-Machine

Interface (HMI)

Analog

Timers

I²C

x2

Timers

x1 (8ch)

x2 (2ch)

16-bit

SAR ADC x2

SPI

x2

CRC

Up to

70 GPIOs

Comparator

Programmable

delay block

Flash access

control

UART

x3

with 6-bit DAC

x2

Periodic

interrupt

timers

12-bit DAC

x1

LPUART

x1

High

16-bit

low-power

timer

performance

voltage ref

Figure 1. Functional block diagram

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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Freescale Semiconductor, Inc.

Table of Contents

1 Ratings....................................................................................5

3.6 Analog............................................................................. 31

3.6.1 ADC electrical specifications............................... 31

3.6.2 CMP and 6-bit DAC electrical specifications....... 36

3.6.3 12-bit DAC electrical characteristics....................38

3.6.4 Voltage reference electrical specifications.......... 41

3.7 Timers..............................................................................42

3.8 Communication interfaces............................................... 42

3.8.1 DSPI switching specifications (limited voltage

1.1 Thermal handling ratings................................................. 5

1.2 Moisture handling ratings................................................ 5

1.3 ESD handling ratings.......................................................5

1.4 Voltage and current operating ratings............................. 5

2 General................................................................................... 6

2.1 AC electrical characteristics.............................................6

2.2 Nonswitching electrical specifications..............................6

2.2.1 Voltage and current operating requirements....... 6

2.2.2 LVD and POR operating requirements................7

2.2.3 Voltage and current operating behaviors.............8

2.2.4 Power mode transition operating behaviors........ 9

2.2.5 Power consumption operating behaviors............ 10

2.2.6 EMC radiated emissions operating behaviors.....16

2.2.7 Designing with radiated emissions in mind..........17

2.2.8 Capacitance attributes.........................................17

2.3 Switching specifications...................................................17

2.3.1 Device clock specifications..................................17

2.3.2 General switching specifications......................... 18

2.4 Thermal specifications.....................................................18

2.4.1 Thermal operating requirements......................... 18

2.4.2 Thermal attributes................................................19

3 Peripheral operating requirements and behaviors.................. 20

3.1 Core modules.................................................................. 20

3.1.1 SWD electricals .................................................. 20

3.1.2 JTAG electricals.................................................. 21

3.2 System modules.............................................................. 24

3.3 Clock modules................................................................. 24

3.3.1 MCG specifications..............................................24

3.3.2 IRC48M specifications.........................................26

3.3.3 Oscillator electrical specifications........................27

3.4 Memories and memory interfaces................................... 29

3.4.1 Flash electrical specifications..............................29

3.4.2 EzPort switching specifications........................... 30

3.5 Security and integrity modules........................................ 31

range).................................................................. 43

3.8.2 DSPI switching specifications (full voltage

range).................................................................. 44

3.8.3 Inter-Integrated Circuit Interface (I2C) timing...... 46

3.8.4 UART switching specifications............................ 48

3.9 Kinetis Motor Suite.......................................................... 48

4 Dimensions............................................................................. 48

4.1 Obtaining package dimensions....................................... 48

5 Pinout......................................................................................49

5.1 KV31F Signal Multiplexing and Pin Assignments............49

5.2 Recommended connection for unused analog and

digital pins........................................................................53

5.3 KV31F Pinouts.................................................................54

6 Part identification.....................................................................57

6.1 Description.......................................................................57

6.2 Format............................................................................. 57

6.3 Fields............................................................................... 57

6.4 Example...........................................................................58

7 Terminology and guidelines.................................................... 58

7.1 Definitions........................................................................58

7.2 Examples.........................................................................58

7.3 Typical-value conditions.................................................. 59

7.4 Relationship between ratings and operating

requirements....................................................................59

7.5 Guidelines for ratings and operating requirements..........60

8 Revision History...................................................................... 60

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Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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Ratings

1 Ratings

1.1 Thermal handling ratings

Symbol

T_STG

Description

Min.

–55

—

Max.

150

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

1

2

T_SDR

260

°C

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD handling ratings

Symbol

V_HBM

Description

Min.

-2000

-500

Max.

+2000

+500

Unit

V

Notes

Electrostatic discharge voltage, human body model

1

2

V_CDM

Electrostatic discharge voltage, charged-device

model

V

I_LAT

Latch-up current at ambient temperature of 105°C

-100

+100

mA

3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.4 Voltage and current operating ratings

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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General

Symbol

Description

Min.

–0.3

Max.

3.8

Unit

V

V_DD

I_DD

Digital supply voltage

Digital supply current

—

145

mA

V

V_DIO

V_AIO

I_D

Digital input voltage

Analog¹

–0.3

V_DD+ 0.3

25

–0.3

V

Maximum current single pin limit (applies to all digital pins)

Analog supply voltage

–25

mA

V

V_DDA

V_DD– 0.3

V_DD+ 0.3

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

2 General

2.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

High

Low

V_IH

80%

50%

20%

Input Signal

Midpoint1

V_IL

Fall Time

Rise Time

The midpoint is V_IL+ (V_IH- V_IL) / 2

Figure 2. Input signal measurement reference

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

Symbol

Description

Min.

Max.

Unit

Notes

V_DD

Supply voltage

1.71

3.6

V

Table continues on the next page...

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Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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General

Notes

Table 1. Voltage and current operating requirements (continued)

Symbol

Description

Min.

1.71

Max.

3.6

0.1

—

Unit

V

V_DDA

Analog supply voltage

V_DD– V_DDAV_DD-to-V_DDAdifferential voltage

V_SS– V_SSAV_SS-to-V_SSAdifferential voltage

–0.1

V

–0.1

V

V_IH

Input high voltage

0.7 × V_DD

0.75 × V_DD

V

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

—

V

V_IL

Input low voltage

—

0.35 × V_DD

0.3 × V_DD

V

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

V_HYS

I_ICIO

Input hysteresis

0.06 × V_DD

-3

—

V

Analog and I/O pin DC injection current — single pin

• V_IN< V_SS-0.3V (Negative current injection)

1

mA

I_ICcont

Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents or sum of

positive injection currents of 16 contiguous pins

-25

—

mA

• Negative current injection

V_ODPU

V_RAM

Open drain pullup voltage level

V_DD

1.2

V_DD

—

V

2

V_DDvoltage required to retain RAM

1. All analog and I/O pins are internally clamped to V_SSthrough ESD protection diodes. If V_INis less than V_{IO_MIN}or

greater than V_{IO_MAX}, a current limiting resistor is required. The negative DC injection current limiting resistor is

calculated as R=(V_{IO_MIN}-V_IN)/|I_ICIO|.

2. Open drain outputs must be pulled to VDD.

2.2.2 LVD and POR operating requirements

Table 2. V_DDsupply LVD and POR operating requirements

Symbol Description

Min.

0.8

Typ.

1.1

Max.

1.5

Unit

V

Notes

V_POR

Falling VDD POR detect voltage

V_LVDH

Falling low-voltage detect threshold — high

range (LVDV=01)

2.48

2.56

2.64

V

Low-voltage warning thresholds — high range

• Level 1 falling (LVWV=00)

1

V_LVW1H

V_LVW2H

V_LVW3H

V_LVW4H

2.62

2.72

2.82

2.92

2.70

2.80

2.90

3.00

2.78

2.88

2.98

3.08

V

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

Table continues on the next page...

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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General

Table 2. V_DDsupply LVD and POR operating requirements (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_HYSH

Low-voltage inhibit reset/recover hysteresis —

high range

—

80

—

mV

V_LVDL

Falling low-voltage detect threshold — low

range (LVDV=00)

1.54

1.60

1.66

V

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV=00)

1

V_LVW1L

V_LVW2L

V_LVW3L

V_LVW4L

1.74

1.84

1.94

2.04

1.80

1.90

2.00

2.10

1.86

1.96

2.06

2.16

V

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

V_HYSL

Low-voltage inhibit reset/recover hysteresis —

low range

—

60

—

mV

V_BG

t_LPO

Bandgap voltage reference

0.97

900

1.00

1.03

V

Internal low power oscillator period — factory

trimmed

1000

1100

μs

1. Rising threshold is the sum of falling threshold and hysteresis voltage

2.2.3 Voltage and current operating behaviors

Table 3. Voltage and current operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_OHOutput high voltage — Normal drive pad except

RESET_B

2.7 V ≤ V_DD≤ 3.6 V, I_OH= -5 mA

1.71 V ≤ V_DD≤ 2.7 V, I_OH= -2.5 mA

V_DD– 0.5

—

V

1

V_OH

Output high voltage — High drive pad except

RESET_B

2.7 V ≤ V_DD≤ 3.6 V, I_OH= -20 mA

1.71 V ≤ V_DD≤ 2.7 V, I_OH= -10 mA

Output high current total for all ports

V_DD– 0.5

—

V

I_OHT

V_OL

100

mA

Output low voltage — Normal drive pad except

RESET_B

2.7 V ≤ V_DD≤ 3.6 V, I_OL= 5 mA

1.71 V ≤ V_DD≤ 2.7 V, I_OL= 2.5 mA

—

0.5

V

1

V_OL

Output low voltage — High drive pad except

RESET_B

2.7 V ≤ V_DD≤ 3.6 V, I_OL= 20 mA

1.71 V ≤ V_DD≤ 2.7 V, I_OL= 10 mA

Output low voltage — RESET_B

—

0.5

V

V_OL

Table continues on the next page...

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Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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General

Notes

Table 3. Voltage and current operating behaviors (continued)

Symbol Description

2.7 V ≤ V_DD≤ 3.6 V, I_OL= 3 mA

Min.

—

Typ.

—

Max.

0.5

Unit

V

1.71 V ≤ V_DD≤ 2.7 V, I_OL= 1.5 mA

Output low current total for all ports

—

0.5

V

I_OLT

I_IN

—

100

mA

Input leakage current (per pin) for full

temperature range

All pins other than high drive port pins

High drive port pins

—

0.002

0.004

—

0.5

1.0

μA

1, 2

2

I_IN

Input leakage current (total all pins) for full

temperature range

R_PU

R_PD

Internal pullup resistors

20

—

50

kΩ

3

4

Internal pulldown resistors

1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability

selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

2. Measured at VDD=3.6V

3. Measured at V_DDsupply voltage = V_DDmin and Vinput = V_SS

4. Measured at V_DDsupply voltage = V_DDmin and Vinput = V_DD

2.2.4 Power mode transition operating behaviors

All specifications except t_POR, and VLLSx→RUN recovery times in the following

table assume this clock configuration:

• CPU and system clocks = 72 MHz

• Bus clock = 36 MHz

• Flash clock = 24 MHz

• MCG mode: FEI

Table 4. Power mode transition operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

t_PORAfter a POR event, amount of time from the

—

300

μs

1

point V_DDreaches 1.71 V to execution of the

first instruction across the operating

temperature range of the chip.

• VLLS0 → RUN

• VLLS1 → RUN

• VLLS2 → RUN

—

135

75

μs

Table continues on the next page...

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General

Table 4. Power mode transition operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

• VLLS3 → RUN

—

75

6

μs

• LLS2 → RUN

• LLS3 → RUN

• VLPS → RUN

• STOP → RUN

—

μs

6

—

μs

—

5.7

μs

—

μs

1. Normal boot (FTFA_OPT[LPBOOT]=1)

2.2.5 Power consumption operating behaviors

The current parameters in the table below are derived from code executing a while(1)

loop from flash, unless otherwise noted.

The IDD typical values represent the statistical mean at 25°C, and the IDD maximum

values for RUN, WAIT, VLPR, and VLPW represent data collected at 125°C junction

temperature unless otherwise noted. The maximum values represent characterized

results equivalent to the mean plus three times the standard deviation (mean + 3 sigma).

Table 5. Power consumption operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_DDA

Analog supply current

—

See note

mA

1

I_{DD_HSRUN}High Speed Run mode current - all peripheral

clocks disabled, CoreMark benchmark code

executing from flash

@ 1.8V

@ 3.0V

—

19.51

20.24

mA

2, 3, 4

I_{DD_HSRUN}High Speed Run mode current - all peripheral

clocks disabled, code executing from flash

@ 1.8V

@ 3.0V

—

16.9

17.0

17.63

17.73

mA

5

6

I_{DD_HSRUN}High Speed Run mode current — all peripheral

clocks enabled, code executing from flash

@ 1.8V

@ 3.0V

—

22.8

22.9

23.53

23.63

mA

Table continues on the next page...

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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General

Table 5. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_RUN}Run mode current in Compute operation —

CoreMark benchmark code executing from flash

@ 1.8V

@ 3.0V

—

11.39

11.58

12.12

12.31

mA

2, 3, 7

I_{DD_RUN}Run mode current in Compute operation —

code executing from flash

@ 1.8V

@ 3.0V

—

10.90

11.90

12.23

mA

7

8

9

I_{DD_RUN}Run mode current — all peripheral clocks

disabled, code executing from flash

@ 1.8V

@ 3.0V

—

11.8

11.9

12.53

12.63

mA

I_{DD_RUN}Run mode current — all peripheral clocks

enabled, code executing from flash

@ 1.8V

—

15.5

16.23

mA

@ 3.0V

• @ 25°C

—

15.6

16.3

16.33

17.03

mA

• @ 70°C

• @ 85°C

• @ 105°C

I_{DD_RUN}Run mode current — Compute operation, code

executing from flash

@ 1.8V

—

10.9

11.63

mA

10

@ 3.0V

• @ 25°C

—

10.9

11.5

6.5

11.63

12.23

7.23

mA

• @ 70°C

• @ 85°C

• @ 105°C

I_{DD_WAIT}Wait mode high frequency current at 3.0 V — all

peripheral clocks disabled

8

I_{DD_WAIT}Wait mode reduced frequency current at 3.0 V

— all peripheral clocks disabled

—

3.9

4.63

mA

11

I_{DD_VLPR}Very-low-power run mode current in Compute

operation — CoreMark benchmark code

executing from flash

@ 1.8V

@ 3.0V

—

0.60

0.61

0.88

0.89

mA

2, 3, 12

I_{DD_VLPR}Very-low-power run mode current in Compute

operation, code executing from flash

Table continues on the next page...

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General

Table 5. Power consumption operating behaviors (continued)

Symbol Description

Min.

—

Typ.

0.48

0.54

Max.

0.76

0.82

Unit

mA

Notes

@ 1.8V

@ 3.0V

12

—

I_{DD_VLPR}Very-low-power run mode current at 3.0 V — all

peripheral clocks disabled

—

13

14

15

I_{DD_VLPR}Very-low-power run mode current at 3.0 V — all

peripheral clocks enabled

—

0.79

0.30

1.07

0.59

mA

I_{DD_VLPW}Very-low-power wait mode current at 3.0 V —

all peripheral clocks disabled

I_{DD_STOP}Stop mode current at 3.0 V

@ -40°C to 25°C

—

0.27

0.31

0.43

0.33

0.36

0.66

mA

@ 70°C

@ 85°C

@ 105°C

I_{DD_VLPS}Very-low-power stop mode current at 3.0 V

@ -40°C to 25°C

—

4.2

9.00

31.90

50.95

89.00

µA

@ 70°C

15.8

26.9

43.0

@ 85°C

@ 105°C

I_{DD_LLS3}Low leakage stop mode 3 current at 3.0 V

@ -40°C to 25°C

—

2.6

6.2

3.30

8.60

µA

@ 70°C

@ 85°C

9.6

12.30

26.00

@ 105°C

15.0

I_{DD_LLS2}Low leakage stop mode 2 current at 3.0 V

@ -40°C to 25°C

—

2.4

5.2

3.00

6.85

µA

@ 70°C

@ 85°C

7.9

9.95

@ 105°C

12.0

20.00

I_{DD_VLLS3}Very low-leakage stop mode 3 current at 3.0 V

@ -40°C to 25°C

—

1.8

4.3

2.10

5.70

µA

@ 70°C

@ 85°C

6.6

8.10

@ 105°C

10.0

17.00

I_{DD_VLLS2}Very low-leakage stop mode 2 current at 3.0 V

@ -40°C to 25°C

—

1.6

3.1

4.7

6.8

1.80

3.90

µA

@ 70°C

@ 85°C

7.00

@ 105°C

10.90

I_{DD_VLLS1}Very low-leakage stop mode 1 current at 3.0 V

@ -40°C to 25°C

—

0.70

0.90

µA

Table continues on the next page...

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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General

Notes

Table 5. Power consumption operating behaviors (continued)

Symbol Description

@ 70°C

Min.

—

Typ.

1.78

2.8

Max.

2.09

3.25

6.15

Unit

µA

@ 85°C

—

µA

@ 105°C

—

4.0

µA

I_{DD_VLLS0}Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit enabled

@ -40°C to 25°C

@ 70°C

—

0.40

1.38

2.40

3.6

0.49

1.49

2.70

5.65

µA

@ 85°C

@ 105°C

I_{DD_VLLS0}Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit disabled

@ -40°C to 25°C

@ 70°C

—

0.12

1.05

2.1

0.19

1.13

2.45

5.35

µA

@ 85°C

@ 105°C

3.3

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.

See each module's specification for its supply current.

2. Cache on and prefetch on, low compiler optimization.

3. Coremark benchmark compiled using IAR 7.2 withs optimization level low.

4. 100 MHz core and system clock, 50 MHz bus clock, and 25 MHz flash clock. MCG configured for FEE mode. All

peripheral clocks disabled.

5. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All

peripheral clocks disabled.

6. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All

peripheral clocks enabled.

7. 72 MHz core and system clock, 36 MHz bus clock, and 24 MHz flash clock. MCG configured for FEE mode. All

peripheral clocks disabled. Compute operation.

8. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. All

peripheral clocks disabled.

9. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. All

peripheral clocks enabled.

10. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. Compute

Operation.

11. 25MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode.

12. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. Compute Operation.

Code executing from flash.

13. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks

disabled. Code executing from flash.

14. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks

enabled but peripherals are not in active operation. Code executing from flash.

15. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks

disabled.

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General

Table 6. Low power mode peripheral adders—typical value

Symbol

Description

Temperature (°C)

Unit

-40

25

50

70

85

105

I_IREFSTEN4MHz

I_{IREFSTEN32KHz}

I_EREFSTEN4MHz

I_{EREFSTEN32KHz}

4 MHz internal reference clock (IRC)

adder. Measured by entering STOP or

VLPS mode with 4 MHz IRC enabled.

56

µA

32 kHz internal reference clock (IRC)

adder. Measured by entering STOP

mode with the 32 kHz IRC enabled.

52

µA

uA

External 4 MHz crystal clock adder.

Measured by entering STOP or VLPS

mode with the crystal enabled.

206

228

237

245

251

258

External 32 kHz crystal clock adder by

means of the OSC0_CR[EREFSTEN

and EREFSTEN] bits. Measured by

entering all modes with the crystal

enabled.

VLLS1

440

490

510

350

22

490

560

350

22

540

560

350

22

560

350

22

570

610

350

22

580

680

350

22

nA

VLLS3

LLS

VLPS

STOP

I_48MIRC

I_CMP

48 Mhz internal reference clock

µA

CMP peripheral adder measured by

placing the device in VLLS1 mode with

CMP enabled using the 6-bit DAC and a

single external input for compare.

Includes 6-bit DAC power consumption.

I_UART

UART peripheral adder measured by

placing the device in STOP or VLPS

mode with selected clock source waiting

for RX data at 115200 baud rate.

Includes selected clock source power

consumption.

MCGIRCLK (4 MHz internal reference

clock)

66

214

45

66

237

45

66

246

45

66

254

45

66

260

45

66

268

45

µA

>OSCERCLK (4 MHz external crystal)

I_BG

Bandgap adder when BGEN bit is set

and device is placed in VLPx, LLS, or

VLLSx mode.

µA

I_ADC

ADC peripheral adder combining the

measured values at V_DDand V_DDAby

placing the device in STOP or VLPS

mode. ADC is configured for low power

mode using the internal clock and

continuous conversions.

42

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Freescale Semiconductor, Inc.

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

General

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at

frequencies between 50 MHz and 100MHz.

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFA

Figure 3. Run mode supply current vs. core frequency

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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Freescale Semiconductor, Inc.

General

Figure 4. VLPR mode supply current vs. core frequency

2.2.6 EMC radiated emissions operating behaviors

Table 7. EMC radiated emissions operating behaviors for 64 LQFP package

Parame Conditions

ter

Clocks

Frequency range

Level

(Typ.)

Unit

Notes

V_EME

Device configuration, test FSYS = 100 MHz

150 kHz–50 MHz

50 MHz–150 MHz

150 MHz–500 MHz

500 MHz–1000 MHz

IEC level

13

24

23

7

dBuV

1, 2, 3

conditions and EM

testing per standard IEC

FBUS = 50 MHz

External crystal = 10 MHz

61967-2.

Supply voltages:

L

4

Temp = 25°C

1. Measurements were made per IEC 61967-2 while the device was running typical application code.

2. Measurements were performed on a similar 64LQFP device.

3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,

from among the measured orientations in each frequency range.

4. IEC Level Maximums: M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV, H ≤ 42dBmV .

16

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Freescale Semiconductor, Inc.

General

2.2.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.freescale.com.

2. Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 8. Capacitance attributes

Symbol

C_{IN_A}

Description

Min.

—

Max.

Unit

pF

Input capacitance: analog pins

Input capacitance: digital pins

7

C_{IN_D}

—

pF

2.3 Switching specifications

2.3.1 Device clock specifications

Table 9. Device clock specifications

Symbol

Description

Min.

Max.

Unit

Notes

High Speed run mode

f_SYS

f_BUS

System and core clock

Bus clock

—

100

50

MHz

Normal run mode (and High Speed run mode unless otherwise specified above)

f_SYS

f_BUS

f_FLASH

f_LPTMR

System and core clock

Bus clock

—

72

50

25

MHz

Flash clock

LPTMR clock

VLPR mode¹

f_SYS

f_BUS

System and core clock

Bus clock

—

4

MHz

f_FLASH

f_ERCLK

f_{LPTMR_pin}

Flash clock

1

External reference clock

LPTMR clock

16

25

16

f_{LPTMR_ERCLK}LPTMR external reference clock

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General

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

any other module.

2.3.2 General switching specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

and timers.

Table 10. General switching specifications

Symbol

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5

—

Bus clock

cycles

1, 2

External RESET and NMI pin interrupt pulse width —

Asynchronous path

100

50

—

ns

3

4

GPIO pin interrupt pulse width (digital glitch filter

disabled, passive filter disabled) — Asynchronous

path

ns

Mode select (EZP_CS) hold time after reset

deassertion

2

—

Bus clock

cycles

Port rise and fall time

• Slew disabled

5

—

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

• Slew enabled

10

5

ns

—

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

30

16

ns

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may

or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can

be recognized in that case.

2. The greater of synchronous and asynchronous timing must be met.

3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be

recognized.

4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be

recognized.

5. 25 pF load

2.4 Thermal specifications

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Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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General

Notes

2.4.1 Thermal operating requirements

Table 11. Thermal operating requirements

Symbol

T_J

Description

Min.

–40

Max.

125

Unit

°C

Die junction temperature

Ambient temperature

T_A

105

°C

1

1. Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not exceed maximum T_J. The simplest method to

determine T_Jis: T_J= T_A+ R_ΘJA× chip power dissipation.

2.4.2 Thermal attributes

Board type

Symbol

Description

100 LQFP

64 LQFP

Unit

Notes

Single-layer

(1s)

R_θJA

Thermal

63

69

51

57

44

33

°C/W

1

2

3

4

resistance,

junction to

ambient

(natural

convection)

Four-layer

(2s2p)

R_θJA

Thermal

50

53

44

36

resistance,

junction to

ambient

(natural

convection)

Single-layer

(1s)

R_θJMA

R_θJB

Thermal

resistance,

junction to

ambient (200

ft./min. air

speed)

Four-layer

(2s2p)

Thermal

resistance,

junction to

ambient (200

ft./min. air

speed)

—

Thermal

resistance,

junction to

board

—

R_θJC

Thermal

resistance,

junction to case

18

3

18

3

°C/W

5

6

Ψ_JT

Thermal

characterizatio

n parameter,

junction to

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Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Board type

Symbol

Description

100 LQFP

64 LQFP

Unit

Notes

package top

outside center

(natural

convection)

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air)with the single layer board horizontal. Board meets JESD51-9 specification.

2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental

Conditions—Forced Convection (Moving Air) with the board horizontal.

4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 SWD electricals

Table 12. SWD full voltage range electricals

Symbol

Description

Min.

Max.

Unit

Operating voltage

1.71

3.6

V

S1

SWD_CLK frequency of operation

• Serial wire debug

0

33

—

MHz

ns

S2

S3

SWD_CLK cycle period

SWD_CLK clock pulse width

• Serial wire debug

1/S1

15

—

ns

S4

S9

SWD_CLK rise and fall times

—

8

3

ns

SWD_DIO input data setup time to SWD_CLK rise

SWD_DIO input data hold time after SWD_CLK rise

SWD_CLK high to SWD_DIO data valid

SWD_CLK high to SWD_DIO high-Z

—

25

—

S10

S11

S12

1.4

—

5

20

Freescale Semiconductor, Inc.

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

Peripheral operating requirements and behaviors

S2

S3

SWD_CLK (input)

S4

Figure 5. Serial wire clock input timing

SWD_CLK

SWD_DIO

S9

S10

Input data valid

S11

Output data valid

S12

S11

Output data valid

Figure 6. Serial wire data timing

3.1.2 JTAG electricals

Table 13. JTAG limited voltage range electricals

Symbol

Description

Min.

Max.

Unit

V

Operating voltage

TCLK frequency of operation

• Boundary Scan

2.7

3.6

J1

MHz

0

10

20

• JTAG and CJTAG

J2

J3

TCLK cycle period

1/J1

—

ns

TCLK clock pulse width

50

—

Table continues on the next page...

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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Peripheral operating requirements and behaviors

Table 13. JTAG limited voltage range electricals (continued)

Symbol

Description

• Boundary Scan

Min.

Max.

Unit

25

—

ns

• JTAG and CJTAG

J4

J5

TCLK rise and fall times

—

20

1

3

ns

Boundary scan input data setup time to TCLK rise

Boundary scan input data hold time after TCLK rise

TCLK low to boundary scan output data valid

TCLK low to boundary scan output high-Z

TMS, TDI input data setup time to TCLK rise

TMS, TDI input data hold time after TCLK rise

TCLK low to TDO data valid

—

25

—

19

—

J6

J7

—

8

J8

J9

J10

J11

J12

J13

J14

1

—

100

8

TCLK low to TDO high-Z

TRST assert time

TRST setup time (negation) to TCLK high

Table 14. JTAG full voltage range electricals

Symbol

Description

Min.

Max.

Unit

Operating voltage

1.71

3.6

V

J1

TCLK frequency of operation

• Boundary Scan

MHz

0

10

15

• JTAG and CJTAG

J2

J3

TCLK cycle period

TCLK clock pulse width

• Boundary Scan

1/J1

—

ns

50

33

—

ns

• JTAG and CJTAG

J4

J5

TCLK rise and fall times

—

20

1.4

—

8

3

—

ns

Boundary scan input data setup time to TCLK rise

Boundary scan input data hold time after TCLK rise

TCLK low to boundary scan output data valid

TCLK low to boundary scan output high-Z

TMS, TDI input data setup time to TCLK rise

TMS, TDI input data hold time after TCLK rise

TCLK low to TDO data valid

J6

—

J7

27

—

J8

J9

J10

J11

J12

J13

J14

1.4

—

100

8

—

26.2

—

TCLK low to TDO high-Z

TRST assert time

TRST setup time (negation) to TCLK high

—

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Freescale Semiconductor, Inc.

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

Peripheral operating requirements and behaviors

J2

J3

TCLK (input)

J4

Figure 7. Test clock input timing

TCLK

J5

J6

Input data valid

Data inputs

J7

Output data valid

Data outputs

J8

J7

Output data valid

Figure 8. Boundary scan (JTAG) timing

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Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

TCLK

TDI/TMS

TDO

J9

J10

Input data valid

J11

Output data valid

J12

J11

TDO

Output data valid

TDO

Figure 9. Test Access Port timing

TCLK

TRST

J14

J13

Figure 10. TRST timing

3.2 System modules

There are no specifications necessary for the device's system modules.

3.3 Clock modules

24

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Peripheral operating requirements and behaviors

3.3.1 MCG specifications

Table 15. MCG specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

f_{ints_ft}

Δf_{ints_t}

f_{ints_t}

Internal reference frequency (slow clock) —

factory trimmed at nominal VDD and 25 °C

—

32.768

—

kHz

Total deviation of internal reference frequency

(slow clock) over voltage and temperature

—

31.25

—

+0.5/-0.7

—

2

39.0625

0.6

%

Internal reference frequency (slow clock) —

user trimmed

kHz

Δ_{fdco_res_t}Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using SCTRIM and SCFTRIM

0.3

%f_dco

1

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over voltage and temperature

—

+0.5/-0.7

0.3

2

%f_dco

1, 2

1

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over fixed voltage and temperature

range of 0–70°C

1.5

f_{intf_ft}

Internal reference frequency (fast clock) —

factory trimmed at nominal VDD and 25°C

—

4

—

5

MHz

Δf_{intf_ft}

Frequency deviation of internal reference clock

(fast clock) over temperature and voltage —

factory trimmed at nominal VDD and 25 °C

+1/-2

%f_{intf_ft}

f_{intf_t}

Internal reference frequency (fast clock) —

user trimmed at nominal VDD and 25 °C

3

—

5

MHz

kHz

f_{loc_low}

Loss of external clock minimum frequency —

RANGE = 00

(3/5) x

f_{ints_t}

—

f_{loc_high}Loss of external clock minimum frequency —

RANGE = 01, 10, or 11

(16/5) x

f_{ints_t}

FLL

f_{fll_ref}

f_dco

FLL reference frequency range

31.25

20

—

39.0625

25

kHz

DCO output

Low range (DRS=00)

20.97

MHz

3, 4

frequency range

640 × f_{fll_ref}

Mid range (DRS=01)

1280 × f_{fll_ref}

40

60

80

—

41.94

62.91

83.89

23.99

47.97

71.99

50

75

100

—

MHz

Mid-high range (DRS=10)

1920 × f_{fll_ref}

High range (DRS=11)

2560 × f_{fll_ref}

f_{dco_t_DMX3}DCO output

Low range (DRS=00)

732 × f_{fll_ref}

5, 6

frequency

2

Mid range (DRS=01)

1464 × f_{fll_ref}

—

Mid-high range (DRS=10)

—

Table continues on the next page...

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Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 15. MCG specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

2197 × f_{fll_ref}

High range (DRS=11)

2929 × f_{fll_ref}

—

95.98

—

MHz

J_{cyc_fll}

FLL period jitter

—

180

150

—

ps

—

• f_VCO= 48 MHz

• f_VCO= 98 MHz

t_{fll_acquire}FLL target frequency acquisition time

—

1

ms

7

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

mode).

2. 2.0 V <= VDD <= 3.6 V.

3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.

4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency

deviation (Δf_{dco_t}) over voltage and temperature should be considered.

5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.

6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

3.3.2 IRC48M specifications

Table 16. IRC48M specifications

Symbol

V_DD

Description

Min.

1.71

—

Typ.

—

Max.

3.6

Unit

V

Notes

Supply voltage

I_DD48M

f_irc48m

Supply current

400

48

500

—

μA

Internal reference frequency

—

MHz

%f_irc48m

Δf_{irc48m_ol_hv}Open loop total deviation of IRC48M frequency at

—

0.2

0.5

1

high voltage (VDD=1.89V-3.6V) over 0°C to 70°C

Δf_{irc48m_ol_hv}Open loop total deviation of IRC48M frequency at

—

0.4

0.5

1.0

1.5

%f_irc48m

high voltage (VDD=1.89V-3.6V) over full temperature

Δf_{irc48m_ol_lv}Open loop total deviation of IRC48M frequency at low

voltage (VDD=1.71V-1.89V) over full temperature

J_{cyc_irc48m}Period Jitter (RMS)

—

35

2

150

3

ps

μs

t_irc48mst

Startup time

2

1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard

deviation (mean 3 sigma).

2. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the

clock by one of the following settings:

• MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10 or MCG_C5[PLLCLKEN0]=1, or

• SIM_SOPT2[PLLFLLSEL]=11

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Peripheral operating requirements and behaviors

3.3.3 Oscillator electrical specifications

3.3.3.1 Oscillator DC electrical specifications

Table 17. Oscillator DC electrical specifications

Symbol Description

V_DDSupply voltage

Min.

Typ.

Max.

Unit

Notes

1.71

—

3.6

V

I_DDOSCSupply current — low-power mode (HGO=0)

1

• 32 kHz

—

500

200

300

950

1.2

—

nA

μA

mA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

• 24 MHz

• 32 MHz

1.5

I_DDOSCSupply current — high-gain mode (HGO=1)

1

• 32 kHz

—

25

400

500

2.5

3

—

μA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

μA

mA

• 24 MHz

• 32 MHz

4

C_x

C_y

R_F

EXTAL load capacitance

XTAL load capacitance

—

2, 3

2, 4

Feedback resistor — low-frequency, low-power

mode (HGO=0)

MΩ

kΩ

Feedback resistor — low-frequency, high-gain

mode (HGO=1)

—

10

—

Feedback resistor — high-frequency, low-

power mode (HGO=0)

Feedback resistor — high-frequency, high-gain

mode (HGO=1)

1

R_S

Series resistor — low-frequency, low-power

mode (HGO=0)

—

Series resistor — low-frequency, high-gain

mode (HGO=1)

200

—

kΩ

Series resistor — high-frequency, low-power

mode (HGO=0)

kΩ

Series resistor — high-frequency, high-gain

mode (HGO=1)

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 17. Oscillator DC electrical specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

—

0

—

kΩ

5

V_pp

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, low-power mode

(HGO=0)

—

0.6

V_DD

0.6

—

V

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, high-gain mode

(HGO=1)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, low-power mode

(HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, high-gain mode

(HGO=1)

V_DD

1. V_DD=3.3 V, Temperature =25 °C

2. See crystal or resonator manufacturer's recommendation

3. C_xand C_ycan be provided by using either integrated capacitors or external components.

4. When low-power mode is selected, R_Fis integrated and must not be attached externally.

5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

any other device.

3.3.3.2 Oscillator frequency specifications

Table 18. Oscillator frequency specifications

Symbol Description

f_{osc_lo}Oscillator crystal or resonator frequency — low-

frequency mode (MCG_C2[RANGE]=00)

Min.

Typ.

Max.

Unit

Notes

32

—

40

kHz

f_{osc_hi_1}Oscillator crystal or resonator frequency — high-

frequency mode (low range)

3

8

—

8

MHz

(MCG_C2[RANGE]=01)

f_{osc_hi_2}Oscillator crystal or resonator frequency — high

frequency mode (high range)

32

(MCG_C2[RANGE]=1x)

f_{ec_extal}Input clock frequency (external clock mode)

t_{dc_extal}Input clock duty cycle (external clock mode)

—

40

—

50

60

—

MHz

%

1, 2

3, 4

t_cst

Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0)

750

ms

Crystal startup time — 32 kHz low-frequency,

high-gain mode (HGO=1)

—

250

0.6

—

ms

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), low-power mode

(HGO=0)

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), high-gain mode

(HGO=1)

—

1

—

ms

1. Other frequency limits may apply when external clock is being used as a reference for the FLL

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Peripheral operating requirements and behaviors

2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

3. Proper PC board layout procedures must be followed to achieve specifications.

4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

register being set.

3.4 Memories and memory interfaces

3.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

3.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps

are active and do not include command overhead.

Table 19. NVM program/erase timing specifications

Symbol Description

Min.

—

Typ.

7.5

Max.

18

Unit

μs

Notes

t_hvpgm4Longword Program high-voltage time

t_hversscrSector Erase high-voltage time

—

1

—

13

113

904

ms

t_hversall

Erase All high-voltage time

—

104

1

1. Maximum time based on expectations at cycling end-of-life.

3.4.1.2 Flash timing specifications — commands

Table 20. Flash command timing specifications

Symbol Description

Min.

—

Typ.

—

Max.

60

Unit

μs

Notes

t_rd1sec2kRead 1s Section execution time (flash sector)

t_pgmchkProgram Check execution time

1

—

45

μs

t_rdrsrc

t_pgm4

t_ersscr

t_rd1all

t_rdonce

Read Resource execution time

Program Longword execution time

Erase Flash Sector execution time

Read 1s All Blocks execution time

Read Once execution time

—

30

μs

1

65

145

114

0.9

30

μs

—

2

14

ms

μs

—

1

—

1

t_pgmonceProgram Once execution time

100

140

—

μs

—

2

t_ersall

Erase All Blocks execution time

1150

30

ms

μs

t_vfykey

Verify Backdoor Access Key execution time

1

1. Assumes 25 MHz flash clock frequency.

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Peripheral operating requirements and behaviors

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3.4.1.3 Flash high voltage current behaviors

Table 21. Flash high voltage current behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

I_{DD_PGM}

Average current adder during high voltage

flash programming operation

—

2.5

6.0

mA

I_{DD_ERS}

Average current adder during high voltage

flash erase operation

—

1.5

4.0

mA

3.4.1.4 Reliability specifications

Table 22. NVM reliability specifications

Symbol Description

Min.

Program Flash

Typ.¹

Max.

Unit

Notes

t_nvmretp10kData retention after up to 10 K cycles

t_nvmretp1kData retention after up to 1 K cycles

n_nvmcycpCycling endurance

5

50

—

years

cycles

—

2

20

100

50 K

10 K

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a

constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in

Engineering Bulletin EB619.

2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ T_j≤ 125 °C.

3.4.2 EzPort switching specifications

Table 23. EzPort switching specifications

Num

Description

Min.

1.71

—

Max.

3.6

Unit

V

Operating voltage

EP1

EZP_CK frequency of operation (all commands except

READ)

f_SYS/2

MHz

EP1a

EP2

EP3

EP4

EP5

EP6

EP7

EP8

EP9

EZP_CK frequency of operation (READ command)

EZP_CS negation to next EZP_CS assertion

EZP_CS input valid to EZP_CK high (setup)

EZP_CK high to EZP_CS input invalid (hold)

EZP_D input valid to EZP_CK high (setup)

EZP_CK high to EZP_D input invalid (hold)

EZP_CK low to EZP_Q output valid

—

f_SYS/8

—

MHz

ns

2 x t_{EZP_CK}

5

—

ns

—

ns

2

—

ns

5

—

ns

—

0

25

—

ns

EZP_CK low to EZP_Q output invalid (hold)

EZP_CS negation to EZP_Q tri-state

ns

—

12

ns

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Peripheral operating requirements and behaviors

EZP_CK

EP2

EP3

EP4

EZP_CS

EP9

EP8

EP7

EZP_Q (output)

EZP_D (input)

EP5

EP6

Figure 11. EzPort Timing Diagram

3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

3.6 Analog

3.6.1 ADC electrical specifications

The 16-bit accuracy specifications listed in Table 24 and Table 25 are achievable on

the differential pins ADCx_DPx, ADCx_DMx.

All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy

specifications.

3.6.1.1 16-bit ADC operating conditions

Table 24. 16-bit ADC operating conditions

Symbol Description

V_DDASupply voltage

ΔV_DDASupply voltage

Conditions

Min.

1.71

-100

Typ.¹

Max.

3.6

Unit

V

Notes

Absolute

—

Delta to V_DD(V_DD– V_DDA

)

0

+100

mV

2

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 24. 16-bit ADC operating conditions (continued)

Symbol Description

Conditions

Min.

-100

1.13

Typ.¹

Max.

+100

V_DDA

Unit

mV

V

Notes

ΔV_SSA

Ground voltage Delta to V_SS(V_SS– V_SSA

)

0

2

V_REFH

ADC reference

voltage high

V_DDA

V_REFL

V_ADIN

ADC reference

voltage low

V_SSA

V

Input voltage

• 16-bit differential mode

VREFL

—

31/32 *

VREFH

• All other modes

• 16-bit mode

VREFH

C_ADIN

Input

capacitance

—

8

4

10

5

pF

• 8-bit / 10-bit / 12-bit

modes

R_ADIN

R_AS

Input series

resistance

—

2

5

kΩ

Analog source

resistance

(external)

13-bit / 12-bit modes

f_ADCK< 4 MHz

3

—

f_ADCK

C_rate

ADC conversion ≤ 13-bit mode

clock frequency

1.0

2.0

—

24.0

12.0

MHz

4

5

ADC conversion 16-bit mode

clock frequency

ADC conversion ≤ 13-bit modes

rate

No ADC hardware averaging

20

37

—

1200

461

Ksps

Continuous conversions

enabled, subsequent

conversion time

C_rate

ADC conversion 16-bit mode

5

rate

No ADC hardware averaging

Continuous conversions

enabled, subsequent

conversion time

1. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The

R_AS/C_AStime constant should be kept to < 1 ns.

4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

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Peripheral operating requirements and behaviors

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

ZADIN

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

ZAS

leakage

due to

input

ADC SAR

ENGINE

RAS

RADIN

protection

VADIN

CAS

VAS

RADIN

INPUT PIN

CADIN

Figure 12. ADC input impedance equivalency diagram

3.6.1.2 16-bit ADC electrical characteristics

Table 25. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Symbol Description

Conditions¹

Min.

0.215

1.2

Typ.²

Max.

1.7

3.9

6.1

7.3

9.5

Unit

Notes

I_{DDA_ADC}Supply current

—

mA

3

ADC asynchronous

clock source

• ADLPC = 1, ADHSC = 0

• ADLPC = 1, ADHSC = 1

• ADLPC = 0, ADHSC = 0

• ADLPC = 0, ADHSC = 1

2.4

4.0

5.2

6.2

MHz

t_ADACK= 1/

f_ADACK

2.4

f_ADACK

3.0

4.4

Sample Time

See Reference Manual chapter for sample times

TUE

DNL

Total unadjusted

error

• 12-bit modes

• <12-bit modes

—

4

6.8

2.1

LSB⁴

5

1.4

Differential non-

linearity

• 12-bit modes

• <12-bit modes

—

0.7

0.2

–1.1 to

+1.9

–0.3 to

0.5

INL

Integral non-linearity

• 12-bit modes

—

1.0

–2.7 to

+1.9

LSB⁴

5

Table continues on the next page...

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Table 25. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Symbol Description

Conditions¹

Min.

Typ.²

Max.

Unit

Notes

—

0.5

–0.7 to

+0.5

• <12-bit modes

5

E_FS

E_Q

Full-scale error

• 12-bit modes

• <12-bit modes

• 16-bit modes

• ≤13-bit modes

—

–4

–1.4

–1 to 0

—

–5.4

–1.8

—

LSB⁴

V_ADIN= V_DDA

Quantization error

0.5

ENOB Effective number of 16-bit differential mode

6

bits

12.8

11.9

14.5

13.8

—

bits

• Avg = 32

• Avg = 4

16-bit single-ended mode

• Avg = 32

12.2

11.4

13.9

13.1

—

bits

dB

• Avg = 4

Signal-to-noise plus See ENOB

SINAD

6.02 × ENOB + 1.76

distortion

THD

Total harmonic

distortion

16-bit differential mode

• Avg = 32

7

dB

—

-94

-85

—

16-bit single-ended mode

• Avg = 32

—

SFDR Spurious free

dynamic range

16-bit differential mode

• Avg = 32

—

dB

82

78

95

90

16-bit single-ended mode

• Avg = 32

E_IL

Input leakage error

I_In× R_AS

mV

I_In= leakage

current

(refer to the

MCU's

voltage and

current

operating

ratings)

Temp sensor slope Across the full temperature

range of the device

1.55

706

1.62

716

1.69

726

mV/°C

mV

8

V_TEMP25Temp sensor

voltage

25 °C

8

1. All accuracy numbers assume the ADC is calibrated with V_REFH= V_DDA

2. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

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Peripheral operating requirements and behaviors

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with

1 MHz ADC conversion clock speed.

4. 1 LSB = (V_REFH- V_REFL)/2^N

5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)

6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

8. ADC conversion clock < 3 MHz

Typical ADC 16-bit Differential ENOB vs ADC Clock

100Hz, 90% FS Sine Input

15.00

14.70

14.40

14.10

13.80

13.50

13.20

12.90

12.60

Hardware Averaging Disabled

Averaging of 4 samples

12.30

12.00

Averaging of 8 samples

Averaging of 32 samples

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 13. Typical ENOB vs. ADC_CLK for 16-bit differential mode

Typical ADC 16-bit Single-Ended ENOB vs ADC Clock

100Hz, 90% FS Sine Input

14.00

13.75

13.50

13.25

13.00

12.75

12.50

12.25

12.00

11.75

11.50

11.25

Averaging of 4 samples

Averaging of 32 samples

11.00

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 14. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

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Peripheral operating requirements and behaviors

3.6.2 CMP and 6-bit DAC electrical specifications

Table 26. Comparator and 6-bit DAC electrical specifications

Symbol

V_DD

Description

Min.

1.71

—

Typ.

—

Max.

3.6

Unit

V

Supply voltage

I_DDHS

I_DDLS

V_AIN

Supply current, High-speed mode (EN=1, PMODE=1)

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

—

200

20

μA

V

—

V_SS– 0.3

—

V_DD

20

V_AIO

Analog input offset voltage

Analog comparator hysteresis¹

• CR0[HYSTCTR] = 00

—

mV

V_H

—

5

—

mV

10

20

30

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

V_CMPOh

V_CMPOl

t_DHS

Output high

V_DD– 0.5

—

50

250

—

7

—

0.5

200

600

40

V

Output low

Propagation delay, high-speed mode (EN=1, PMODE=1)

Propagation delay, low-speed mode (EN=1, PMODE=0)

Analog comparator initialization delay²

6-bit DAC current adder (enabled)

6-bit DAC integral non-linearity

20

ns

t_DLS

80

ns

—

μs

I_DAC6b

INL

—

μA

LSB³

LSB

–0.5

–0.3

—

0.5

0.3

DNL

6-bit DAC differential non-linearity

1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD–0.6 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.

3. 1 LSB = V_reference/64

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Peripheral operating requirements and behaviors

0.08

0.07

0.06

0.05

0.04

0.03

HYSTCTR

Setting

00

01

10

11

0.02

0.01

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

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Peripheral operating requirements and behaviors

0.18

0.16

0.14

0.12

HYSTCTR

Setting

0.1

00

01

10

11

0.08

0.06

0.04

0.02

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 16. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

3.6.3 12-bit DAC electrical characteristics

3.6.3.1 12-bit DAC operating requirements

Table 27. 12-bit DAC operating requirements

Symbol

V_DDA

V_DACR

C_L

Desciption

Min.

1.71

1.13

—

Max.

3.6

100

1

Unit

V

Notes

Supply voltage

Reference voltage

Output load capacitance

Output load current

V

1

2

pF

mA

I_L

—

1. The DAC reference can be selected to be V_DDAor V_REFH

.

2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

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Peripheral operating requirements and behaviors

3.6.3.2 12-bit DAC operating behaviors

Table 28. 12-bit DAC operating behaviors

Symbol Description

Min.

Typ.

Max.

330

Unit

Notes

I_{DDA_DACL}Supply current — low-power mode

—

μA

P

I_{DDA_DACH}Supply current — high-speed mode

—

100

15

1200

200

30

μA

μs

P

t_DACLPFull-scale settling time (0x080 to 0xF7F) —

low-power mode

1

t_DACHPFull-scale settling time (0x080 to 0xF7F) —

high-power mode

t_CCDACLPCode-to-code settling time (0xBF8 to

0xC08) — low-power mode and high-

speed mode

0.7

1

V_dacoutlDAC output voltage range low — high-

speed mode, no load, DAC set to 0x000

—

100

mV

V_dacouthDAC output voltage range high — high-

speed mode, no load, DAC set to 0xFFF

V_DACR

−100

V_DACR

INL

DNL

Integral non-linearity error — high speed

mode

—

8

1

LSB

2

3

4

Differential non-linearity error — V_DACR> 2

V

Differential non-linearity error — V_DACR

VREF_OUT

=

V_OFFSETOffset error

E_GGain error

PSRR Power supply rejection ratio, V_DDA≥ 2.4 V

—

60

—

0.4

0.1

0.8

0.6

90

%FSR

dB

5

—

T_CO

T_GE

Rop

SR

Temperature coefficient offset voltage

Temperature coefficient gain error

Output resistance (load = 3 kΩ)

Slew rate -80h→ F7Fh→ 80h

3.7

—

μV/C

%FSR/C

Ω

6

0.000421

—

250

V/μs

• High power (SP_HP

)

1.2

1.7

—

• Low power (SP_LP

3dB bandwidth

)

0.05

0.12

BW

kHz

• High power (SP_HP

• Low power (SP_LP

)

550

40

—

)

1. Settling within 1 LSB

2. The INL is measured for 0 + 100 mV to V_DACR−100 mV

3. The DNL is measured for 0 + 100 mV to V_DACR−100 mV

4. The DNL is measured for 0 + 100 mV to V_DACR−100 mV with V_DDA> 2.4 V

5. Calculated by a best fit curve from V_SS+ 100 mV to V_DACR− 100 mV

6. V_DDA= 3.0 V, reference select set for V_DDA(DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC

set to 0x800, temperature range is across the full range of the device

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Peripheral operating requirements and behaviors

8

6

4

2

0

-2

-4

-6

-8

0

500

1000

1500

2000

2500

3000

3500

4000

Digital Code

Figure 17. Typical INL error vs. digital code

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Peripheral operating requirements and behaviors

1.499

1.4985

1.498

1.4975

1.497

1.4965

1.496

55

85

25

105

125

-40

Temperature °C

Figure 18. Offset at half scale vs. temperature

3.6.4 Voltage reference electrical specifications

Table 29. VREF full-range operating requirements

Symbol

V_DDA

T_A

Description

Supply voltage

Temperature

Min.

Max.

Unit

Notes

1.71

3.6

V

Operating temperature

range of the device

°C

C_L

Output load capacitance

100

nF

1, 2

1. C_Lmust be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external

reference.

2. The load capacitance should not exceed +/-25% of the nominal specified C_Lvalue over the operating temperature

range of the device.

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Peripheral operating requirements and behaviors

Table 30. VREF full-range operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_out

Voltage reference output with factory trim at

1.1920

1.1950

1.1980

V

1

nominal V_DDAand temperature=25°C

V_out

Voltage reference output with user trim at

nominal V_DDAand temperature=25°C

1.1945

1.1950

1.1955

V

1

V_step

V_tdrift

Voltage reference trim step

—

0.5

—

mV

1

Temperature drift (Vmax -Vmin across the full

temperature range)

15

I_bg

I_lp

Bandgap only current

—

80

360

1

µA

uA

mA

µV

Low-power buffer current

High-power buffer current

1

I_hp

ΔV_LOADLoad regulation

• current = 1.0 mA

1, 2

—

200

—

T_stup

Buffer startup time

—

100

35

µs

T_{chop_osc_st}Internal bandgap start-up delay with chop

ms

oscillator enabled

up

V_vdrift

Voltage drift (Vmax -Vmin across the full voltage

range)

—

2

—

mV

1

1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.

2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 31. VREF limited-range operating requirements

Symbol

Description

Min.

Max.

Unit

Notes

T_A

Temperature

0

70

°C

Table 32. VREF limited-range operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

V_tdrift

Temperature drift (V_max-V_minacross the limited

temperature range)

—

10

mV

3.7 Timers

See General switching specifications.

3.8 Communication interfaces

42

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

3.8.1 DSPI switching specifications (limited voltage range)

The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus

with master and slave operations. Many of the transfer attributes are programmable.

The tables below provide DSPI timing characteristics for classic SPI timing modes.

Refer to the SPI chapter of the Reference Manual for information on the modified

transfer formats used for communicating with slower peripheral devices.

Table 33. Master mode DSPI timing (limited voltage range)

Num

Description

Min.

2.7

Max.

3.6

25

Unit

V

Notes

Operating voltage

Frequency of operation

—

MHz

ns

DS1

DS2

DS3

DSPI_SCK output cycle time

DSPI_SCK output high/low time

DSPI_PCSn valid to DSPI_SCK delay

2 x t_BUS

—

(t_SCK/2) − 2 (t_SCK/2) + 2

ns

(t_BUSx 2) −

2

—

ns

1

2

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(t_BUSx 2) −

2

—

ns

DS5

DS6

DS7

DS8

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

—

-2

8.5

—

ns

16.2

0

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].

2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

DSPI_PCSn

DS1

DS3

DS2

DS4

DSPI_SCK

(CPOL=0)

DS8

DS7

Data

Last data

First data

DSPI_SIN

DS5

DS6

First data

Data

Last data

DSPI_SOUT

Figure 19. DSPI classic SPI timing — master mode

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 34. Slave mode DSPI timing (limited voltage range)

Num

Description

Min.

2.7

Max.

3.6

Unit

V

Notes

Operating voltage

Frequency of operation

—

12.5

—

MHz

ns

1

DS9

DSPI_SCK input cycle time

4 x t_BUS

DS10

DS11

DS12

DS13

DS14

DS15

DS16

DSPI_SCK input high/low time

(t_SCK/2) − 2 (t_SCK/2) + 2

ns

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

DSPI_SS active to DSPI_SOUT driven

DSPI_SS inactive to DSPI_SOUT not driven

—

0

21.4

—

ns

2.6

7

—

ns

—

ns

—

17

ns

1. The maximum operating frequency is measured with noncontinuous CS and SCK. When DSPI is configured with

continuous CS and SCK, the SPI clock must not be greater than 1/6 of the bus clock. For example, when the bus clock

is 60 MHz, the SPI clock must not be greater than 10 MHz.

DSPI_SS

DS10

DS9

DSPI_SCK

(CPOL=0)

DS15

DS12

DS16

DS11

First data

DS14

Last data

DSPI_SOUT

Data

DS13

First data

Last data

DSPI_SIN

Figure 20. DSPI classic SPI timing — slave mode

44

Freescale Semiconductor, Inc.

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

Peripheral operating requirements and behaviors

3.8.2 DSPI switching specifications (full voltage range)

The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus

with master and slave operations. Many of the transfer attributes are programmable.

The tables below provides DSPI timing characteristics for classic SPI timing modes.

Refer to the SPI chapter of the Reference Manual for information on the modified

transfer formats used for communicating with slower peripheral devices.

Table 35. Master mode DSPI timing (full voltage range)

Num

Description

Min.

1.71

Max.

3.6

Unit

V

Notes

Operating voltage

1

Frequency of operation

—

12.5

—

MHz

ns

DS1

DS2

DS3

DSPI_SCK output cycle time

DSPI_SCK output high/low time

DSPI_PCSn valid to DSPI_SCK delay

4 x t_BUS

(t_SCK/2) - 4 (t_SCK/2)+ 4

ns

(t_BUSx 2) −

4

—

ns

2

3

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(t_BUSx 2) −

4

—

ns

DS5

DS6

DS7

DS8

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

—

-4.5

24.6

0

10

—

ns

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].

3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

DSPI_PCSn

DS1

DS3

DS2

DS4

DSPI_SCK

(CPOL=0)

DS8

DS7

Data

Last data

First data

DSPI_SIN

DS5

DS6

First data

Data

Last data

DSPI_SOUT

Figure 21. DSPI classic SPI timing — master mode

Table 36. Slave mode DSPI timing (full voltage range)

Num

Description

Min.

Max.

Unit

Operating voltage

1.71

3.6

V

Table continues on the next page...

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

45

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 36. Slave mode DSPI timing (full voltage range) (continued)

Num

Description

Min.

Max.

Unit

MHz

ns

Frequency of operation

—

6.25

DS9

DSPI_SCK input cycle time

8 x t_BUS

—

DS10

DS11

DS12

DS13

DS14

DS15

DS16

DSPI_SCK input high/low time

(t_SCK/2) - 4

(t_SCK/2)+ 4

ns

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

DSPI_SS active to DSPI_SOUT driven

DSPI_SS inactive to DSPI_SOUT not driven

—

0

29.5

—

ns

3.2

7

—

ns

—

ns

—

25

ns

DSPI_SS

DS10

DS9

DSPI_SCK

(CPOL=0)

DS15

DS12

DS16

DS11

First data

DS14

Last data

DSPI_SOUT

Data

DS13

First data

Last data

DSPI_SIN

Figure 22. DSPI classic SPI timing — slave mode

3.8.3 Inter-Integrated Circuit Interface (I²C) timing

Table 37. I ²C timing

Characteristic

Symbol

Standard Mode

Minimum Maximum

100

Fast Mode

Unit

Minimum

Maximum

400¹

SCL Clock Frequency

f_SCL

0

kHz

µs

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated.

t_HD; STA

4

—

0.6

—

LOW period of the SCL clock

HIGH period of the SCL clock

t_LOW

t_HIGH

4.7

4

—

1.25

0.6

—

µs

Set-up time for a repeated START

condition

t_SU; STA

4.7

0.6

Data hold time for I²C bus devices

t_HD; DAT

0²

3.45³

0⁴

0.9²

µs

Table continues on the next page...

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

46

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 37. I ²C timing (continued)

Characteristic

Symbol

Standard Mode

Fast Mode

Unit

Minimum Maximum

Minimum

Maximum

Data set-up time

t_SU; DAT

250⁵

—

1000

300

—

100^{3, 6}

20 +0.1C_b

0.6

—

300

—

ns

µs

7

6

Rise time of SDA and SCL signals

Fall time of SDA and SCL signals

Set-up time for STOP condition

t_r

t_f

—

t_SU; STO

t_BUF

4

Bus free time between STOP and

START condition

4.7

—

1.3

—

Pulse width of spikes that must be

suppressed by the input filter

t_SP

N/A

0

50

ns

1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the

High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.

2. The master mode I²C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves

acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and

SCL lines.

3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.

4. Input signal Slew = 10 ns and Output Load = 50 pF

5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.

6. A Fast mode I²C bus device can be used in a Standard mode I2C bus system, but the requirement t_{SU; DAT}≥ 250 ns

must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If

such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t_rmax

+ t_{SU; DAT}= 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification) before the SCL line is

released.

7. C_b= total capacitance of the one bus line in pF.

Table 38. I ²C 1 Mbps timing

Characteristic

Symbol

f_SCL

Minimum

Maximum

Unit

MHz

µs

SCL Clock Frequency

0

1¹

Hold time (repeated) START condition. After this

period, the first clock pulse is generated.

t_HD; STA

0.26

—

LOW period of the SCL clock

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data hold time for I₂C bus devices

Data set-up time

t_LOW

t_HIGH

0.5

0.26

0

—

µs

ns

µs

t_SU; STA

t_HD; DAT

t_SU; DAT

t_r

—

50

—

, 2

Rise time of SDA and SCL signals

Fall time of SDA and SCL signals

Set-up time for STOP condition

20 +0.1C_b

0.26

120

—

2

t_f

t_SU; STO

t_BUF

Bus free time between STOP and START

condition

0.5

—

Pulse width of spikes that must be suppressed by

the input filter

t_SP

0

50

ns

1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins

across the full voltage range.

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

47

Freescale Semiconductor, Inc.

Dimensions

2. C_b= total capacitance of the one bus line in pF.

SDA

t_{SU; DAT}

t_f

t_r

t_BUF

t_f

t_r

t_{HD; STA}

t_SP

t_LOW

SCL

t_{SU; STA}

t_{SU; STO}

HD; STA

S

SR

P

S

t_{HD; DAT}

t_HIGH

Figure 23. Timing definition for devices on the I²C bus

3.8.4 UART switching specifications

See General switching specifications.

3.9 Kinetis Motor Suite

Kinetis Motor Suite is a bundled software solution that enables the rapid configuration

of motor drive systems, and accelerates development of the final motor drive

application.

Several members of the KV3x family are enabled with Kinetis motor suite. The enabled

devices can be identified within the orderable part numbers in this table. For more

information refer to Kinetis Motor Suite User's Guide (KMS100UG) and Kinetis Motor

Suite API Reference Manual (KMS100RM).

NOTE

To find the associated resource, go to freescale.com and

perform a search using Document ID.

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

48

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

Freescale Semiconductor, Inc.

Pinout

To find a package drawing, go to freescale.com and perform a keyword search for the

drawing’s document number:

If you want the drawing for this package

64-pin LQFP

Then use this document number

98ASS23234W

98ASS23308W

100-pin LQFP

5 Pinout

5.1 KV31F Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is

responsible for selecting which ALT functionality is available on each pin.

100

LQFP LQFP

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

I2C1_SDA

I2C1_SCL

ALT7

EzPort

1

2

3

4

5

6

7

1

PTE0/

CLKOUT32K

ADC1_SE4a ADC1_SE4a PTE0/

CLKOUT32K

SPI1_PCS1

SPI1_SOUT

SPI1_SCK

SPI1_SIN

UART1_TX

UART1_RX

2

PTE1/

LLWU_P0

ADC1_SE5a ADC1_SE5a PTE1/

LLWU_P0

SPI1_SIN

SPI1_SOUT

—

PTE2/

LLWU_P1

ADC1_SE6a ADC1_SE6a PTE2/

LLWU_P1

UART1_

CTS_b

PTE3

ADC1_SE7a ADC1_SE7a PTE3

UART1_

RTS_b

PTE4/

LLWU_P2

DISABLED

PTE4/

LLWU_P2

SPI1_PCS0

SPI1_PCS2

SPI1_PCS3

LPUART0_

TX

PTE5

PTE6

PTE5

PTE6

LPUART0_

RX

LPUART0_

CTS_b

8

9

3

4

5

VDD

VSS

VDD

VSS

10

PTE16

ADC0_SE4a ADC0_SE4a PTE16

ADC0_SE5a ADC0_SE5a PTE17

ADC0_SE6a ADC0_SE6a PTE18

ADC0_SE7a ADC0_SE7a PTE19

SPI0_PCS0

SPI0_SCK

SPI0_SOUT

SPI0_SIN

UART2_TX

UART2_RX

FTM_

CLKIN0

FTM0_FLT3

11

12

13

14

6

7

PTE17

FTM_

CLKIN1

LPTMR0_

ALT3

PTE18

UART2_

CTS_b

I2C0_SDA

I2C0_SCL

8

PTE19

UART2_

RTS_b

—

ADC0_DP1

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

49

Freescale Semiconductor, Inc.

Pinout

100

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

LQFP LQFP

15

16

—

ADC0_DM1

ADC1_DP1/

ADC0_DP2

ADC1_DP1/

ADC0_DP2

ADC1_DP1/

ADC0_DP2

17

18

19

20

21

—

9

ADC1_DM1/

ADC0_DM2

ADC1_DM1/

ADC0_DM2

ADC1_DM1/

ADC0_DM2

ADC0_DP0/

ADC1_DP3

ADC0_DP0/

ADC1_DP3

ADC0_DP0/

ADC1_DP3

10

11

12

ADC0_DM0/

ADC1_DM3

ADC0_DM0/

ADC1_DM3

ADC0_DM0/

ADC1_DM3

ADC1_DP0/

ADC0_DP3

ADC1_DP0/

ADC0_DP3

ADC1_DP0/

ADC0_DP3

ADC1_DM0/

ADC0_DM3

ADC1_DM0/

ADC0_DM3

ADC1_DM0/

ADC0_DM3

22

23

24

25

26

13

14

15

16

17

VDDA

VREFH

VREFL

VSSA

VDDA

VREFH

VREFL

VSSA

VDDA

VREFH

VREFL

VSSA

VREF_OUT/

CMP1_IN5/

CMP0_IN5/

VREF_OUT/

CMP1_IN5/

CMP0_IN5/

VREF_OUT/

CMP1_IN5/

CMP0_IN5/

ADC1_SE18 ADC1_SE18 ADC1_SE18

27

28

18

19

DAC0_OUT/

CMP1_IN3/

ADC0_SE23 ADC0_SE23 ADC0_SE23

CMP0_IN4/ CMP0_IN4/ CMP0_IN4/

ADC1_SE23 ADC1_SE23 ADC1_SE23

DAC0_OUT/

CMP1_IN3/

DAC0_OUT/

CMP1_IN3/

29

30

31

—

20

VSS

VDD

VSS

VDD

PTE24

ADC0_SE17 ADC0_SE17 PTE24

FTM0_CH0

FTM0_CH1

I2C0_SCL

I2C0_SDA

EWM_OUT_

b

32

33

21

—

PTE25

ADC0_SE18 ADC0_SE18 PTE25

EWM_IN

PTE26/

DISABLED

PTE26/

CLKOUT32K

34

22

PTA0

JTAG_TCLK/

SWD_CLK/

EZP_CLK

PTA0

UART0_

CTS_b

FTM0_CH5

EWM_IN

JTAG_TCLK/ EZP_CLK

SWD_CLK

35

36

23

24

PTA1

PTA2

JTAG_TDI/

EZP_DI

PTA1

PTA2

UART0_RX

UART0_TX

FTM0_CH6

FTM0_CH7

CMP0_OUT

CMP1_OUT

FTM2_QD_

PHA

FTM1_CH1

FTM1_CH0

JTAG_TDI

EZP_DI

JTAG_TDO/

TRACE_

SWO/

FTM2_QD_

PHB

JTAG_TDO/

TRACE_

SWO

EZP_DO

37

38

25

26

PTA3

JTAG_TMS/

SWD_DIO

PTA3

UART0_

RTS_b

FTM0_CH0

FTM0_CH1

FTM2_FLT0

EWM_OUT_

b

JTAG_TMS/

SWD_DIO

PTA4/

NMI_b/

PTA4/

FTM0_FLT3

NMI_b

EZP_CS_b

LLWU_P3

EZP_CS_b

LLWU_P3

50

Freescale Semiconductor, Inc.

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

Pinout

100

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

LQFP LQFP

39

27

PTA5

DISABLED

PTA5

FTM0_CH2

JTAG_

TRST_b

40

41

42

—

28

VDD

VSS

PTA12

DISABLED

PTA12

FTM1_CH0

FTM1_CH1

FTM1_QD_

PHA

43

29

PTA13/

LLWU_P4

DISABLED

PTA13/

LLWU_P4

FTM1_QD_

PHB

44

45

46

—

PTA14

PTA15

PTA16

DISABLED

PTA14

PTA15

PTA16

SPI0_PCS0

SPI0_SCK

SPI0_SOUT

UART0_TX

UART0_RX

UART0_

CTS_b

47

—

PTA17

ADC1_SE17 ADC1_SE17 PTA17

SPI0_SIN

UART0_

RTS_b

48

49

50

30

31

32

VDD

VSS

PTA18

EXTAL0

PTA18

PTA19

FTM0_FLT2

FTM1_FLT0

FTM_

CLKIN0

51

33

PTA19

XTAL0

FTM0_FLT0

FTM_

LPTMR0_

ALT1

CLKIN1

52

53

34

35

RESET_b

PTB0/

LLWU_P5

ADC0_SE8/

ADC1_SE8

ADC0_SE8/

ADC1_SE8

PTB0/

LLWU_P5

I2C0_SCL

I2C0_SDA

I2C0_SCL

I2C0_SDA

SPI1_PCS1

SPI1_PCS0

SPI1_SCK

FTM1_CH0

FTM1_CH1

FTM1_QD_

PHA

UART0_RX

UART0_TX

54

55

56

57

58

59

36

37

38

—

PTB1

PTB2

PTB3

PTB9

PTB10

PTB11

ADC0_SE9/

ADC1_SE9

ADC0_SE9/

ADC1_SE9

PTB1

FTM0_FLT2

FTM0_FLT1

EWM_IN

FTM1_QD_

PHB

ADC0_SE12 ADC0_SE12 PTB2

ADC0_SE13 ADC0_SE13 PTB3

UART0_

RTS_b

FTM0_FLT3

UART0_

CTS_b

FTM0_FLT0

DISABLED

PTB9

LPUART0_

CTS_b

ADC1_SE14 ADC1_SE14 PTB10

ADC1_SE15 ADC1_SE15 PTB11

LPUART0_

RX

FTM0_FLT1

FTM0_FLT2

LPUART0_

TX

60

61

62

—

39

VSS

VDD

PTB16

DISABLED

PTB16

PTB17

PTB18

PTB19

SPI1_SOUT

SPI1_SIN

UART0_RX

UART0_TX

FTM2_CH0

FTM2_CH1

FTM_

CLKIN0

EWM_IN

63

64

65

40

41

42

PTB17

PTB18

PTB19

DISABLED

FTM_

CLKIN1

EWM_OUT_

b

FTM2_QD_

PHA

FTM2_QD_

PHB

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

51

Freescale Semiconductor, Inc.

Pinout

100

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

LQFP LQFP

66

67

68

69

70

—

43

PTB20

PTB21

PTB22

PTB23

PTC0

DISABLED

PTB20

CMP0_OUT

CMP1_OUT

PTB21

PTB22

PTB23

SPI0_PCS5

ADC0_SE14 ADC0_SE14 PTC0

SPI0_PCS4

SPI0_PCS3

SPI0_PCS2

SPI0_PCS1

PDB0_

EXTRG

FTM0_FLT1

SPI0_PCS0

71

72

73

44

45

46

PTC1/

LLWU_P6

ADC0_SE15 ADC0_SE15 PTC1/

LLWU_P6

ADC0_SE4b/ ADC0_SE4b/ PTC2

UART1_

RTS_b

FTM0_CH0

FTM0_CH1

FTM0_CH2

LPUART0_

RTS_b

PTC2

UART1_

CTS_b

LPUART0_

CTS_b

CMP1_IN0

PTC3/

LLWU_P7

CMP1_IN1

PTC3/

LLWU_P7

UART1_RX

CLKOUT

LPUART0_

RX

74

75

76

47

48

49

VSS

VDD

VSS

VDD

PTC4/

LLWU_P8

DISABLED

PTC4/

LLWU_P8

SPI0_PCS0

SPI0_SCK

SPI0_SOUT

SPI0_SIN

UART1_TX

FTM0_CH3

CMP1_OUT

CMP0_OUT

LPUART0_

TX

77

78

50

51

PTC5/

LLWU_P9

DISABLED

CMP0_IN0

CMP0_IN1

PTC5/

LLWU_P9

LPTMR0_

ALT2

FTM0_CH2

I2C0_SCL

I2C0_SDA

PTC6/

LLWU_P10

CMP0_IN0

CMP0_IN1

PTC6/

LLWU_P10

PDB0_

EXTRG

79

80

52

53

PTC7

PTC8

PTC7

ADC1_SE4b/ ADC1_SE4b/ PTC8

CMP0_IN2 CMP0_IN2

81

54

PTC9

ADC1_SE5b/ ADC1_SE5b/ PTC9

CMP0_IN3 CMP0_IN3

FTM2_FLT0

82

83

55

56

PTC10

ADC1_SE6b ADC1_SE6b PTC10

I2C1_SCL

I2C1_SDA

PTC11/

ADC1_SE7b ADC1_SE7b PTC11/

LLWU_P11

PTC12

84

85

86

87

88

89

90

—

PTC12

PTC13

PTC14

PTC15

VSS

DISABLED

VSS

PTC13

PTC14

PTC15

VSS

VDD

PTC16

DISABLED

PTC16

PTC17

PTC18

LPUART0_

RX

91

92

93

94

—

57

58

PTC17

PTC18

DISABLED

LPUART0_

TX

LPUART0_

RTS_b

PTD0/

LLWU_P12

PTD0/

LLWU_P12

SPI0_PCS0

SPI0_SCK

UART2_

RTS_b

FTM0_CH0

FTM0_CH1

LPUART0_

RTS_b

PTD1

ADC0_SE5b ADC0_SE5b PTD1

UART2_

CTS_b

LPUART0_

CTS_b

52

Freescale Semiconductor, Inc.

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

Pinout

100

LQFP LQFP

64

Pin Name

Default

DISABLED

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

95

96

59

60

61

62

63

64

PTD2/

LLWU_P13

PTD2/

LLWU_P13

SPI0_SOUT

SPI0_SIN

UART2_RX

UART2_TX

FTM0_CH2

FTM0_CH3

FTM0_CH4

FTM0_CH5

FTM0_CH6

FTM0_CH7

LPUART0_

RX

I2C0_SCL

I2C0_SDA

SPI1_PCS0

PTD3

LPUART0_

TX

97

PTD4/

LLWU_P14

PTD4/

LLWU_P14

SPI0_PCS1

SPI0_PCS2

SPI0_PCS3

UART0_

RTS_b

EWM_IN

98

PTD5

ADC0_SE6b ADC0_SE6b PTD5

UART0_

CTS_b

EWM_OUT_ SPI1_SCK

b

99

PTD6/

LLWU_P15

ADC0_SE7b ADC0_SE7b PTD6/

UART0_RX

FTM0_FLT0

SPI1_SOUT

LLWU_P15

PTD7

100

PTD7

DISABLED

UART0_TX

FTM0_FLT1

SPI1_SIN

5.2 Recommended connection for unused analog and digital

pins

The following table shows the recommended connections for analog interface pins if

those analog interfaces are not used in the customer's application.

Table 39. Recommended connection for unused analog interfaces

Pin Type

Analog/non GPIO

GPIO/Analog

Short recommendation

Float

Detailed recommendation

Analog input - Float

PGAx/ADCx

ADCx/CMPx

VREF_OUT

DACx_OUT

RTC_WAKEUP_B

XTAL32

Float

Analog input - Float

Analog output - Float

Analog input - Float

EXTAL32

PTA18/EXTAL0

PTA19/XTAL0

PTx/ADCx

Analog input - Float

GPIO/Analog

Analog output - Float

Float (default is analog input)

GPIO/Analog

PTx/CMPx

GPIO/Digital

PTA0/JTAG_TCLK

Float (default is JTAG with

pulldown)

GPIO/Digital

PTA1/JTAG_TDI

PTA2/JTAG_TDO

PTA3/JTAG_TMS

PTA4/NMI_b

Float

Float (default is JTAG with

pullup)

Float (default is JTAG with

pullup)

Float (default is JTAG with

pullup)

10kΩ pullup or disable and

float

Pull high or disable in PCR &

FOPT and float

Table continues on the next page...

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Freescale Semiconductor, Inc.

Pinout

Table 39. Recommended connection for unused analog interfaces (continued)

Pin Type

Short recommendation

Float

Detailed recommendation

GPIO/Digital

VDDA

PTx

Float (default is disabled)

VDDA

Always connect to VDD

potential

Always connect to VDD

potential

VREFH

VREFL

VSSA

VREFH

VREFL

VSSA

Always connect to VDD

potential

Always connect to VDD

potential

Always connect to VSS

potential

Always connect to VSS

potential

Always connect to VSS

potential

Always connect to VSS

potential

5.3 KV31F Pinouts

The below figure shows the pinout diagram for the devices supported by this document.

Many signals may be multiplexed onto a single pin. To determine what signals can be

used on which pin, see the previous section.

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Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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Pinout

PTE0/CLKOUT32K

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VDD

VSS

PTE1/LLWU_P0

2

VDD

3

PTC3/LLWU_P7

PTC2

VSS

PTE16

4

5

PTC1/LLWU_P6

PTC0

PTE17

6

PTE18

7

PTB19

PTE19

8

PTB18

ADC0_DP0/ADC1_DP3

ADC0_DM0/ADC1_DM3

ADC1_DP0/ADC0_DP3

ADC1_DM0/ADC0_DM3

VDDA

9

PTB17

10

11

12

13

14

15

16

PTB16

PTB3

PTB2

PTB1

VREFH

PTB0/LLWU_P5

RESET_b

PTA19

VREFL

VSSA

Figure 24. KV31F 64 LQFP pinout diagram (top view)

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

55

Freescale Semiconductor, Inc.

Pinout

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PTE0/CLKOUT32K

VDD

2

PTE1/LLWU_P0

PTE2/LLWU_P1

PTE3

VSS

3

PTC3/LLWU_P7

PTC2

4

5

PTC1/LLWU_P6

PTC0

PTE4/LLWU_P2

PTE5

6

7

PTB23

PTB22

PTB21

PTB20

PTB19

PTB18

PTB17

PTB16

VDD

PTE6

8

VDD

9

VSS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PTE16

PTE17

PTE18

PTE19

ADC0_DP1

ADC0_DM1

ADC1_DP1/ADC0_DP2

ADC1_DM1/ADC0_DM2

ADC0_DP0/ADC1_DP3

ADC0_DM0/ADC1_DM3

ADC1_DP0/ADC0_DP3

ADC1_DM0/ADC0_DM3

VDDA

VSS

PTB11

PTB10

PTB9

PTB3

PTB2

PTB1

PTB0/LLWU_P5

RESET_b

PTA19

VREFH

VREFL

VSSA

Figure 25. KV31F 100 LQFP pinout diagram (top view)

56

Freescale Semiconductor, Inc.

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

Part identification

6 Part identification

6.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

6.2 Format

Part numbers for this device have the following format:

Q KV## A FFF R T PP CC S N

6.3 Fields

This table lists the possible values for each field in the part number (not all

combinations are valid):

Field

Description

Values

Q

Qualification status

• M = Fully qualified, general market flow

• P = Prequalification

KV##

A

Kinetis V Series

Key attribute

• KV3x: Cortex-M4 based MCU

• D = Cortex-M4 w/ DSP

• F = Cortex-M4 w/ DSP and FPU

FFF

Program flash memory size

• 64 = 64 KB

• 128 = 128 KB

• 256 = 256 KB

• 512 = 512 KB

R

Silicon revision

• (Blank) = Main

• A = Revision after main

T

Temperature range (°C)

Package identifier

• V = –40 to 105

• C = –40 to 85

PP

• FM = 32 QFN (5 mm x 5 mm)

• LF = 48 LQFP (7 mm x 7 mm)

• LH = 64 LQFP (10 mm x 10 mm)

• LL = 100 LQFP (14 mm x 14 mm)

• MC = 121 XFBGA (8 mm x 8 mm)

• DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)

CC

Maximum CPU frequency (MHz)

• 10 = 100 MHz

• 12 = 120 MHz

Table continues on the next page...

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

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Freescale Semiconductor, Inc.

Terminology and guidelines

Field

Description

Values

S

Software type

• P = KMS-PMSM and BLDC

• (Blank) = Not software enabled

N

Packaging type

• R = Tape and reel

• (Blank) = Trays

6.4 Example

This is an example part number:

MKV31F128VLL10P

7 Terminology and guidelines

7.1 Definitions

Key terms are defined in the following table:

Term

Definition

Rating

A minimum or maximum value of a technical characteristic that, if exceeded, may cause

permanent chip failure:

• Operating ratings apply during operation of the chip.

• Handling ratings apply when the chip is not powered.

NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic

begins to exceed one of its operating ratings.

Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during

operation to avoid incorrect operation and possibly decreasing the useful life of the chip

Operating behavior

A specified value or range of values for a technical characteristic that are guaranteed during

operation if you meet the operating requirements and any other specified conditions

Typical value

A specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior

• Is representative of that characteristic during operation when you meet the typical-value

conditions or other specified conditions

NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.

58

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Terminology and guidelines

7.2 Examples

Operating rating:

EXAMPLE

Operating requirement:

Operating behavior that includes a typical value:

EXAMPLE

7.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as

specified):

Symbol

Description

Ambient temperature

Supply voltage

Value

Unit

T_A

25

°C

V

V_DD

3.3

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Freescale Semiconductor, Inc.

Revision History

7.4 Relationship between ratings and operating requirements

Fatal range

Degraded operating range

Normal operating range

Degraded operating range

Fatal range

Expected permanent failure

- No permanent failure

- Correct operation

- No permanent failure

Expected permanent failure

- Possible decreased life

- Possible incorrect operation

- Possible decreased life

- Possible incorrect operation

–∞

∞

Operating (power on)

Fatal range

Handling range

Fatal range

Expected permanent failure

No permanent failure

Expected permanent failure

–∞

∞

Handling (power off)

7.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.

• During normal operation, don’t exceed any of the chip’s operating requirements.

• If you must exceed an operating requirement at times other than during normal

operation (for example, during power sequencing), limit the duration as much as

possible.

8 Revision History

The following table provides a revision history for this document.

Table 40. Revision History

Rev. No.

Date

Substantial Changes

7

02/2016

• Added Terminology and Guidelines section

• Updated the front matter section

• Added KMS related information in front matter

• Added Kinetis Motor Suite section

• Added "S" in Format and Part Identification table

Table continues on the next page...

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Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

Revision History

Table 40. Revision History (continued)

Rev. No.

Date

Substantial Changes

• Updated the Part Number Example

• Updated IRC48M specifications table

6

10/2015

• In "Power consumption operating behaviors" section, added "Low power mode

peripheral adders—typical value" table

• In "Thermal operating requirements" table, in footnote, corrected "T_J= T_A+ Θ_JA" to

"T_J= T_A+ R_ΘJA

"

• Updated "IRC48M specifications" table

• Updated "NVM program/erase timing specifications" table; updated values for t_hversall

(Erase All high-voltage time)

• In "Slave mode DSPI timing (limited voltage range)" table, added footnote regarding

maximum frequency of operation

• Added new section, "Recommended connections for unused analog and digital pins"

5

4/2015

• On page 1:

• Under "Communication interfaces," updated I²C bullet to indicate support for up

to 1 Mbps operation

• Under "Operating characteristics," specified that voltage range includes flash

writes

• In "Voltage and current operating requirements" table:

• Removed content related to positive injection

• Updated footnote 1 to say that all analog and I/O pins are internally clamped to

V_SSonly (not V_SSand V_DD)through ESD protection diodes.

• In"Power consumption operating behaviors" table:

• Added additional temperature data in power consumption table

• Added Max IDD values based on characterization results equivalent to mean +

3 sigma

• Updated "EMC radiated emissions operating behaviors" table

• In "Thermal operating requirements" table, added the following footnote for ambient

temperature: "Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not

exceed maximum T_J. The simplest method to determine T_Jis: T_J= T_A+ Θ_JAx chip

power dissipation"

• Updated "IRC48M Specifications":

• Updated maximum values for Δ_{firc48m_lv}and Δ_{firc48m_hv}(full temperature)

• Added specifications for Δ_{firc48m_hv}(-40°C to 85°C)

• In "I²C timing" table,

• Added the following footnote on maximum Fast mode value for SCL Clock

Frequency: "The maximum SCL Clock Frequency in Fast mode with maximum

bus loading can only be achieved when using the High drive pins across the full

voltage range and when using the Normal drive pins and VDD ≥ 2.7 V."

• Updated minimum Fast mode value for LOW period of the SCL clock to 1.25 µ

• Added "I²C 1 Mbps timing" table

• Specified that the figure, "KV31F 64 LQFP Pinout Diagram" is a top view

• Specified that the figure, "KV31F 100 LQFP Pinout Diagram" is a top view

• Removed Section 6, "Ordering parts."

4

7/2014

In "Power consumption operating behaviors table":

• Updated existing typical power measurements

• Added new typical power measurements for the following:

• IDD_HSRUN (High Speed Run mode current executing CoreMark code)

• IDD_RUNCO (Run mode current in Compute operation, executing CoreMark

code)

• IDD_RUN (Run mode current in Compute operation, executing while(1) loop)

Table continues on the next page...

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

61

Freescale Semiconductor, Inc.

Revision History

Table 40. Revision History (continued)

Rev. No.

Date

Substantial Changes

• IDD_VLPR (Very Low Power mode current executing CoreMark code)

• IDD_VLPR (Very Low Power Run mode current in Compute operation,

executing while(1) loop)

3

5/2014

• In "Voltage and current operating ratings" table, updated maximum digital supply

current

• Updated "Voltage and current operating behaviors" table

• Updated "Power mode transition operating behaviors" table

• Updated "Power consumption operating behaviors" table

• Updated "EMC radiated emissions operating behaviors for 64 LQFP package" table

• Updated "Thermal attributes" table

• Updated "MCG specifications" table

• Updated "IRC48M specifications" table

• Updated "16-bit ADC operating conditions" table

• Updated "Voltage reference electrical specifications" section

• Added "121-pin XFBGA part marking" table

• Added "64-pin MAPBGA part marking" table

2

1

4/2014

3/2014

• Updated "Voltage and current operating behaviors" table

• Updated "Thermal attributes" table

• Updated "IRC48M specifications" table

Initial public release

62

Kinetis KV31F 128KB Flash, Rev. 7, 02/2016

Freescale Semiconductor, Inc.


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