935313936557 [NXP]
RISC Microprocessor;
| 型号： | 935313936557 |
| 厂家： | 
NXP |
| 描述： | RISC Microprocessor 外围集成电路 |
| 文件： | 总46页 (文件大小：421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF52277
Rev. 8, 09/2009
MCF52277
LQFP–176
MAPBGA–196
15mm x 15mm
24 mm x 24 mm
MCF5227x ColdFire®
Microprocessor Data Sheet
Features
®
• Version 2 ColdFire Core with EMAC
• Up to 159 Dhrystone 2.1 MIPS @ 166.67 MHz
• 8 Kbytes configurable cache (instruction only, data only, or
split instruction/data)
• 128 Kbytes internal SRAM
• Support for booting from SPI-compatible flash, EEPROM,
and FRAM devices
• Crossbar switch technology (XBS) for concurrent access to
peripherals or RAM from multiple bus masters
• 16 channel DMA controller
• 16- or 32-bit SDR/DDR controller
• USB 2.0 On-the-Go controller
• Liquid crystal display controller with support up to
800 × 600 pixels
• ADC and touchscreen controller
• FlexCAN module
• 4 32-bit timers with DMA support
• DMA supported serial peripheral interface (DSPI)
• 3 UARTs
2
• I C bus interface
• Synchronous serial interface (SSI)
• Plus-width modulator (PWM)
• Real-time clock (RTC)
• Two programmable interrupt controllers (PIT)
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Table of Contents
1
2
3
MCF5227x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4
5.5 Oscillator and PLL Electrical Characteristics. . . . . . . . 19
5.6 ASP Electrical Characteristics. . . . . . . . . . . . . . . . . . . 20
5.7 External Interface Timing Specifications . . . . . . . . . . . 21
5.7.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7.2 SDRAM Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . 29
5.9 Reset and Configuration Override Timing . . . . . . . . . . 29
5.10 LCD Controller Timing Specifications . . . . . . . . . . . . . 30
5.11 USB On-The-Go Specifications. . . . . . . . . . . . . . . . . . 33
5.12 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 34
5.13 I2C Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 36
5.14 DMA Timer Timing Specifications . . . . . . . . . . . . . . . . 38
5.15 DSPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 38
5.16 SBF Timing Specifications. . . . . . . . . . . . . . . . . . . . . . 39
5.17 JTAG and Boundary Scan Timing Specifications . . . . 40
5.18 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 42
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . . .5
3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.3 ADC Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.4 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6
3.4.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .6
3.4.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .6
3.5 Power Consumption Specifications. . . . . . . . . . . . . . . . .7
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .9
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2 Pinout—176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.3 Pinout—196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .15
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .17
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .18
4
5
6
7
8
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
2
Freescale Semiconductor
MCF52277
JTAG
Oscillator
PLL
Version 2 ColdFire Core
8K
Configurable
Cache
Serial Boot
Facility
BDM
Hardware
Divide
EMAC
LCD
Controller
128K
SRAM
USB OTG
eDMA
Crossbar Switch (XBS)
Peripheral Bridge
DSPI
SDRAM
Controller
FlexBus
Touch
Screen
RTC
SSI
FlexCAN
I2C
GPIO
EPORT
INTC
4 DMA
Timers
PWM
2 PITs
3 UARTs
LEGEND
BDM
– Background debug module
LCD
– Liquid-crystal display
DSPI
eDMA
EMAC
EPORT
GPIO
I2C
– DMA serial peripheral interface
– Enhanced direct memory access
– Enchanced multiply-accumulate unit
– Edge port module
– General purpose input/output module
– Inter-intergrated circuit
PIT
– Programmable interrupt timer
– Phase-locked loop module
– Pulse-width modulator
– Real time clock
– Synchronous serial interface
– Universal asynchronous receiver/transmitter
PLL
PWM
RTC
SSI
UART
INTC
JTAG
– Interrupt controller
– Joint Test Action Group interface
USB OTG – Universal Serial Bus On-the-Go controller
Figure 1. MCF52277 Block Diagram
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
3
MCF5227x Family Comparison
1
MCF5227x Family Comparison
The following table compares the various device derivatives available within the MCF5227x family.
Table 1. MCF5227x Family Configurations
Module
MCF52274
MCF52277
ColdFire Version 2 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
•
•
Core (System) Clock
up to 120 MHz
up to 60 MHz
up to 114
up to 166.67 MHz
up to 83.33 MHz
up to 159
Peripheral and External Bus Clock
(Core clock ÷ 2)
Performance (Dhrystone/2.1 MIPS)
Static RAM (SRAM)
128 Kbytes
8 Kbytes
Configurable Cache
ASP Touchscreen Controller
LCD Controller
•
•
12-bit color
18-bit color
USB 2.0 On-the-Go
•
•
•
FlexBus External Interface
SDR/DDR SDRAM Controller
FlexCAN 2.0B communication module
Real Time Clock
•
•
•
•
•
•
•
Watchdog Timer
•
•
16-channel Direct Memory Access (DMA)
Interrupt Controllers (INTC)
Synchronous Serial Interface (SSI)
I2C
•
•
1
1
•
•
•
•
DSPI
•
•
UARTs
3
3
4
2
•
32-bit DMA Timers
4
Periodic Interrupt Timers (PIT)
PWM Module
2
•
Edge Port Module (EPORT)
General Purpose I/O Module (GPIO)
JTAG - IEEE® 1149.1 Test Access Port
Package
•
•
•
•
•
•
176 LQFP
196 MAPBGA
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
4
Freescale Semiconductor
Ordering Information
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part
Description
Package
Speed
Temperature
Number
MCF52274CLU120
MCF52277CVM160
MCF52274 RISC Microprocessor
MCF52277 RISC Microprocessor
176 LQFP
120 MHz
–40° to +85° C
–40° to +85° C
196 MAPBGA 166.67 MHz
3
Hardware Design Considerations
3.1
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog V pins. The filter shown in
DD
Figure 2 should be connected between the board V and the PLLV pins. The resistor and capacitors should be placed as
DD
DD
close to the dedicated PLLV pin as possible.
DD
10 Ω
Board IVDD
PLL VDD Pin
10 µF
0.1 µF
GND
Figure 2. System PLL V Power Filter
DD
3.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be
connected between the board EV and the USBV pin. The resistor and capacitors should be placed as close to the dedicated
DD
DD
USBV pin as possible.
DD
0 Ω
Board EVDD
USB VDD Pin
10 µF
0.1 µF
GND
Figure 3. USB V Power Filter
DD
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
5
Hardware Design Considerations
3.3
ADC Power Filtering
To minimize noise, an external filters is required for the ADCV power pin. The filter shown in Figure 4 should be connected
DD
between the board EV and the ADCV pin. The resistor and capacitors should be placed as close to the dedicated ADCV
DD
DD
DD
pin as possible.
0 Ω
Board EVDD
ADC VDD Pin
10 µF
0.1 µF
GND
Figure 4. ADC V Power Filter
DD
3.4
Supply Voltage Sequencing
The relationship between SDV and EV is non-critical during power-up and power-down sequences. Both SDV (2.5V
DD
DD
DD
or 3.3V) and EV are specified relative to IV
.
DD
DD
3.4.1
Power Up Sequence
If EV /SDV are powered up with IV at 0 V, then the sense circuits in the I/O pads will cause all pad output drivers
DD
DD
DD
connected to the EV /SDV to be in a high impedance state. There is no limit on how long after EV /SDV powers up
DD
DD
DD
DD
before IV must powered up. IV should not lead the EV , SDV or PLLV by more than 0.4 V during power ramp-up,
DD
DD
DD
DD
DD
or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than
500 us to avoid turning on the internal ESD protection clamp diodes.
3.4.2
Power Down Sequence
If IV /PLLV are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high
DD
DD
impedance state. There is no limit on how long after IV and PLLV power down before EV or SDV must power
DD
DD
DD
DD
down. IV should not lag EV , SDV , or PLLV going low by more than 0.4 V during power down or there will be
DD
DD
DD
DD
undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop IV /PLLV to 0 V.
DD
DD
2. Drop EV /SDV supplies.
DD
DD
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
6
Freescale Semiconductor
Hardware Design Considerations
3.5
Power Consumption Specifications
All application power consumption data is lab data measured on an M52277EVB running the Freescale Linux BSP.
1
Table 3. MCF52277 Application Power Consumption
Core
Freq.
Idle (LCD
image)
Idle (audio
image)
Button
Demo
Slideshow
Demo
MP3
Playback
USB FS
File Copy
Units
IVDD
EVDD
61.4
28.87
18.8
59.2
25.73
18.57
84.7
35.3
21.8
96.5
34.6
23.9
89.2
33.46
22.66
89.5
29.86
22.2
mA
160 MHz
SDVDD
Total Power
221.211
207.135
282.78
301.95
285.006
272.748
mW
1
All voltage rails at nominal values: IVDD = 1.5 V, EVDD = 3.3 V, and SDVDD = 1.8 V.
350
300
250
200
150
100
50
0
Idle (LCD Idle (Audio
image) Image)
Button
Demo
Slideshow
Demo
MP3
USB FS
Playback File Copy
Figure 5. Power Consumption in Various Applications
All current consumption data is lab data measured on a single device using an evaluation board. Table 4 shows the typical power
consumption in low-power modes. These current measurements are taken after executing a STOP instruction.
1,2
Table 4. Current Consumption in Low-Power Modes
System Frequency
4MHz
(LIMP
mode)
Mode
Voltage Supply
80MHz
64MHz
48MHz
32MHz
IVDD (mA)
Power (mW)
IVDD (mA)
75.1
112.65
61.9
62.7
94.05
52.8
49.2
73.80
42.0
36.6
54.90
31.7
3.5
5.25
2.9
RUN
WAIT
Power (mW)
92.85
79.20
63.00
47.55
4.35
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
7
Hardware Design Considerations
1,2
Table 4. Current Consumption in Low-Power Modes (continued)
System Frequency
4MHz
(LIMP
mode)
Mode
Voltage Supply
80MHz
64MHz
48MHz
32MHz
IVDD (mA)
Power (mW)
IVDD (mA)
57.0
85.50
16.1
24.15
15.9
23.85
1.8
48.8
73.20
15.1
22.65
14.9
22.35
1.8
38.9
58.35
13.4
20.10
13.2
19.80
1.8
29.7
44.55
12.5
18.75
12.4
18.60
1.8
2.7
4.05
1.3
DOZE
STOP 0
STOP 1
STOP 2
STOP 3
Power (mW)
IVDD (mA)
1.95
1.3
Power (mW)
IVDD (mA)
1.95
1.3
Power (mW)
IVDD (mA)
2.70
0.5
2.70
0.5
2.70
0.5
2.70
0.5
1.95
0.5
Power (mW)
0.75
0.75
0.75
0.75
0.75
1
2
All values are measured on an M52277EVB with nominal core voltage(IVDD = 1.5 V). Tests
performed at room temperature. All peripheral clocks on prior to entering low-power mode
Refer to the Power Management chapter in the MCF52277 Reference Manual for more information
on low-power modes.
120
100
RUN
80
WAIT
DOZE
60
40
20
0
STOP 0
STOP 1
STOP 2
STOP 3
80
64
48
32
4 (LIMP)
System Frequency (MHz)
Figure 6. IV Power Consumption in Low-Power Modes
DD
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
8
Freescale Semiconductor
Pin Assignments and Reset States
4
Pin Assignments and Reset States
4.1
Signal Multiplexing
The following table lists all the MCF5227x pins grouped by function. The direction column is the direction for the primary
function of the pin only. Refer to Section 4, “Pin Assignments and Reset States,” for package diagrams. For a more detailed
discussion of the MCF5227x signals, consult the MCF52277 Reference Manual (MCF52277RM).
NOTE
In this table and throughout this document a single signal within a group is designated
without square brackets (i.e., FB_A23), while designations for multiple signals within a
group use brackets (i.e., FB_A[23:21]) and is meant to include all signals within the two
bracketed numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Most pins that
are muxed with GPIO will default to their GPIO functionality. See Table 5 for a list of the
exceptions.
Table 5. Special-Case Default Signal Functionality
Pin
Default Signal
FB_BE/BWE[3:0]
FB_CS[3:0]
FB_OE
FB_BE/BWE[3:0]
FB_CS[3:0]
FB_OE
FB_TA
FB_TA
FB_R/W
FB_R/W
FB_TS
FB_TS
Table 6. MCF5227x Signal Information and Muxing
MCF52274
176 LQFP
MCF52277
196 MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
Reset
RESET
—
—
—
—
—
—
U
I
EVDD
EVDD
103
102
J11
RSTOUT
—
O
K11
Clock
EXTAL
XTAL
—
—
—
—
—
—
—
I
EVDD
EVDD
106
105
F14
G14
U3
O
Mode Selection
BOOTMOD[1:0]
—
—
—
—
I
EVDD
110, 109
G10, H10
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
9
Pin Assignments and Reset States
Table 6. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
MCF52277
196 MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
FlexBus
FB_A[23:22]
FB_A[21:16]
—
—
FB_CS[5:4]
—
—
—
—
—
O
O
SDVDD
143, 142
C11, D11
SDVDD 141–139, 137–135
A12, B12, C12,
B13, A13, A14
FB_A[15:14]
FB_A[13:11]
FB_A10
—
—
—
—
SD_BA[1:0]
SD_A[13:11]
—
—
—
—
—
—
—
O
O
O
O
SDVDD
SDVDD
SDVDD
SDVDD
131, 130
129–127
126
B14, C13
C14, D12, D13
D14
FB_A[9:0]
SD_A[9:0]
125–116
E11–E14,
F11–F13, G11,
G12, H11
FB_D[31:16]
FB_D[15:0]
—
—
SD_D[31:16]
FB_D[31:16]
—
—
I/O SDVDD
I/O SDVDD
30–37, 49–56
19–26, 60–67
J4, K1–K4, L1–L3,
M3, N3, P3,M4,
N4, P4, L5, M5
G1–G4, H1–H4,
M6, N6, P6, L7,
M7, N7, P7, L8
FB_CLK
FB_BE/BWE[3:0]
FB_CS[3:2]
FB_CS1
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
O
I
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
42
P1
J3, N5, J1, L6
B11, A11
D10
PBE[3:0]
PCS[3:2]
PCS1
SD_DQM[3:0]
—
—
—
—
—
U
29, 57, 27, 59
—
SD_CS1
—
—
144
145
69
FB_CS0
PCS0
C10
FB_OE
PFBCTL3
PFBCTL2
PFBCTL1
PFBCTL0
—
N8
FB_TA
—
115
68
H12
FB_R/W
—
—
—
O
O
M8
FB_TS
DACK0
15
F4
SDRAM Controller
SD_A10
SD_CAS
SD_CKE
SD_CLK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
O
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
46
47
L4
N2
17
F2
40
M1
SD_CLK
41
N1
SD_CS0
18
F1
SD_DQS[3:2]
SD_RAS
I/O SDVDD
SDVDD
28, 58
48
J2, P5
P2
O
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
10
Freescale Semiconductor
Pin Assignments and Reset States
Table 6. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
MCF52277
196 MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
SD_SDR_DQS
SD_WE
—
—
—
—
—
—
—
—
O
O
SDVDD
SDVDD
38
16
M2
F3
External Interrupts Port4
IRQ7
IRQ4
IRQ1
PIRQ7
PIRQ4
PIRQ1
—
—
—
I
I
I
EVDD
EVDD
EVDD
162
161
160
D7
C7
B7
5
DREQ0
DSPI_PCS4
USB_CLKIN
SSI_CLKIN
—
LCD Controller6
LCD_D[17:16]6
LCD_D[15:14]6
LCD_D13
PLCDDH[1:0]
PLCDDM[7:6]
PLCDDM5
PLCDDM4
PLCDDM[3:0]
PLCDDL7
LCD_D[11:10]
LCD_D[9:8]
CANTX
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
O
O
O
O
O
O
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
9, 8
7, 6
—
E3, E4
D1, D2
C1
LCD_D12
CANRX
—
C2
LCD_D[11:8]6
LCD_D[7:4]
PWM7
5–2
—
D3, C3, D4, B1
LCD_D7
B2
LCD_D6
PLCDDL6
PWM5
—
A1
LCD_D[5:2]6
PLCDDL[5:2]
PLCDDL1
LCD_D[3:0]
PWM3
175–172
—
A2, A3, B3, A4
LCD_D1
B4
C4
B5
LCD_D0
PLCDDL0
PWM1
—
LCD_ACD/
LCD_OE
PLCDCTL3
LCD_SPL_SPR
169
LCD_FLM/
LCD_VSYNC
PLCDCTL2
PLCDCTL1
PLCDCTL0
—
—
—
—
—
—
—
—
O
O
O
EVDD
EVDD
EVDD
10
11
E2
E1
A5
LCD_LP/
LCD_HSYNC
LCD_LSCLK
—
USB On-the-Go
—
170
USB_DM
USB_DP
—
—
—
—
—
—
O
O
USB
VDD
149
150
A9
—
USB
VDD
A10
Real Time Clock
RTC_EXTAL
RTC_XTAL
—
—
—
—
—
—
—
—
I
EVDD
EVDD
100
99
J14
O
K14
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
11
Pin Assignments and Reset States
Table 6. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
MCF52277
196 MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
Touchscreen Controller
ADC_IN[7:0]
ADC_REF
—
—
—
—
—
—
—
I
I
VDD_
ADC
82–85, 87–90
P12, N12, P13,
N13, P14, N14,
M13, M14
—
VDD_
ADC
86
M12
I2C
I2C_SCL
I2C_SDA
PI2C1
PI2C0
CANTX
CANRX
U2TXD
U2RXD
U
U
I/O
I/O
EVDD
EVDD
168
167
C5
D5
DSPI7
DSPI_PCS0/SS
DSPI_SIN
PDSPI3
PDSPI2
PDSPI1
PDSPI0
U2RTS
U2RXD
U2TXD
U2CTS
—
U
I/O
I
EVDD
EVDD
EVDD
EVDD
152
155
154
153
B9
D8
D9
C9
8
SBF_DI
SBF_D0
SBF_CK
DSPI_SOUT
DSPI_SCK
—
—
O
I/O
UARTs
U1CTS
U1RTS
U1TXD
U1RXD
U0CTS
U0RTS
U0TXD
U0RXD
PUART7
PUART6
PUART5
PUART4
PUART3
PUART2
PUART1
PUART0
SSI_BCLK
SSI_FS
LCD_CLS
—
—
—
—
—
—
—
—
I
O
O
I
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
156
157
159
158
97
C8
B8
LCD_PS
SSI_TXD
SSI_RXD
DT1OUT
DT1IN
—
A7
—
A8
USB_VBUS_EN
I
K12
J12
L12
K13
USB_VBUS_OC
O
O
I
98
CANTX
—
—
95
CANRX
96
DMA Timers
DT3IN
DT2IN/SBF_CS7
DT1IN
PTIMER3
PTIMER2
PTIMER1
PTIMER0
DT3OUT
DT2OUT
DT1OUT
DT0OUT
SSI_MCLK
DSPI_PCS2
—
—
—
—
I
I
I
I
EVDD
EVDD
EVDD
EVDD
163
164
165
166
D6
C6
B6
A6
LCD_CONTRAST
LCD_REV
DT0IN
BDM/JTAG9
PST[3:0]
—
—
—
—
—
—
—
—
O
O
EVDD
EVDD
—
—
L9, M9, N9, P9
DDATA[3:0]
L10, M10, N10,
P10
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
12
Freescale Semiconductor
Pin Assignments and Reset States
Table 6. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
MCF52277
196 MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
ALLPST
JTAG_EN
PSTCLK
DSI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D
O
I
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
76
79
74
78
81
80
77
—
K10
P8
TCLK
TDI
U
O
I
U
M11
L11
N11
P11
DSO
TDO
TMS
TRST
—
U
O
I
BKPT
DSCLK
U
I
Test
TEST
—
—
—
Power Supplies
—
D
I
EVDD
134
E10
IVDD
EVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
39, 75, 114, 138,
171
K5, F10, E5, J10
—
—
12, 72, 73, 94, 111, E6, E7, F5, F6, G5,
148, 176 H9, J9, K8, K9
SD_VDD
14, 43, 44, 70, 113, E8, E9, F9, G9, H5,
132, 146
J5, J6, K6, K7
VDD_OSC
VDD_PLL
VDD_USB
VDD_RTC
VDD_ADC
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
108
G13
H14
B10
J13
L13
104
151
101
91
1, 13, 45, 71, 93,
112, 133, 147
F7, F8, G6–G8,
H6–H8, J7, J8
VSS_OSC
VSS_ADC
—
—
—
—
—
—
—
—
—
—
—
—
107
92
H13
L14
1
2
3
4
5
6
7
Pull-ups are generally only enabled on pins with their primary function, except as noted.
Refers to pin’s primary function.
Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).
GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions.
Pull-up when DREQ controls the pin.
The 176 LQFP device only supports a 12-bit LCD data bus.
DSPI or SBF signal functionality is controlled by RESET. When asserted, these pins are configured for serial boot; when negated, the
pins are configured for DSPI.
8
Pull-up when the serial boot facility (SBF) controls the pin.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
13
Pin Assignments and Reset States
9
If JTAG_EN is asserted, these pins default to alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these
pins.
4.2
Pinout—176 LQFP
The pinout for the MCF52274 package is shown below.
VSS
1
SD_VDD
FB_A15
FB_A14
FB_A13
FB_A12
FB_A11
FB_A10
FB_A9
132
131
130
129
128
127
126
125
124
123
•
2
3
4
5
6
7
8
9
LCD_D8
LCD_D9
LCD_D10
LCD_D11
LCD_D14
LCD_D15
LCD_D16
LCD_D17
LCD_FLM/VSYNC
LCD_LP/HSYNC
EVDD
FB_A8
FB_A7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
122 FB_A6
FB_A5
FB_A4
FB_A3
FB_A2
FB_A1
FB_A0
FB_TA
IVDD
121
120
119
118
117
116
115
114
113
112
VSS
SD_VDD
FB_TS
SD_WE
SD_CKE
SD_CS0
FB_D15
FB_D14
FB_D13
FB_D12
FB_D11
FB_D10
FB_D9
SD_VDD
VSS
111 EVDD
110 BOOTMOD1
109 BOOTMOD0
108 VDD_OSC
107 VSS_OSC
106 EXTAL
FB_D8
FB_BE/BWE1
SD_DQS3
FB_BE/BWE3
FB_D31
105 XTAL
104 VDD_PLL
103 RESET
102 RSTOUT
101 VDD_RTC
100 RTC_EXTAL
99 RTC_XTAL
98 U0RTS
97 U0CTS
96 U0RXD
95 U0TXD
94 EVDD
FB_D30
FB_D29
FB_D28
FB_D27
FB_D26
FB_D25
FB_D24
SD_SDR_DQS
IVDD
SD_CLK
SD_CLK
FB_CLK
SD_VDD
SD_VDD 44
93 VSS
92 VSS_ADC
91 VDD_ADC
90 ADC_IN0
89 ADC_IN1
Figure 7. MCF52274 Pinout (176 LQFP)
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
14
Freescale Semiconductor
Electrical Characteristics
4.3
Pinout—196 MAPBGA
The pinout for the MCF52277 package is shown below.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LCD_
LSCLK
A
B
C
D
E
F
LCD_D6 LCD_D5 LCD_D4 LCD_D2
LCD_D8 LCD_D7 LCD_D3 LCD_D1
T0IN
U1TXD
U1RXD USB_DM USB_DP FB_CS2 FB_A21
FB_A17
FB_A16
A
B
C
D
E
F
LCD_
ACD/OE
DSPI_
PCS0
VDD_
USB
T1IN
T2IN
IRQ_1
IRQ_4
U1RTS
U1CTS
FB_CS3 FB_A20
FB_A18
FB_A14
FB_A11
FB_A7
FB_A15
FB_A13
FB_A10
FB_A6
EXTAL
XTAL
DSPI_
SCK
LCD_D13 LCD_D12 LCD_D10 LCD_D0 I2C_SCL
FB_CS0 FB_A23
FB_CS1 FB_A22
FB_A19
FB_A12
FB_A8
FB_A4
FB_A1
FB_TA
U0RTS
U0CTS
U0TXD
DSPI_
SOUT
LCD_D15 LCD_D14 LCD_D11 LCD_D9 I2C_SDA
LCD_LP/ LCD_FLM/
T3IN
IRQ_7 DSPI_SIN
LCD_D17 LCD_D16
IVDD
EVDD
EVDD
SDVDD
SDVDD
IVDD
EVDD
EVDD
VSS
EVDD
VSS
SDVDD
VSS
SDVDD
SDVDD
SDVDD
EVDD
EVDD
EVDD
PST3
TEST
IVDD
FB_A9
FB_A5
FB_A2
FB_A0
RESET
HSYNC
VSYNC
SD_CS0 SD_CKE
SD_WE
FB_D13
FB_D9
FB_TS
FB_D12
FB_D8
FB_A3
BOOT
MOD1
VDD_
OSC
G
H
J
FB_D15
FB_D11
FB_D14
FB_D10
SD_DQS3
FB_D29
FB_D25
VSS
VSS
G
H
J
BOOT
MOD0
VSS_
OSC
VDD_
PLL
VSS
VSS
VSS
FB_BE/
BWE1
FB_BE/
BWE3
VDD_
RTC
RTC_
EXTAL
FB_D31
FB_D27
SDVDD
SDVDD
VSS
VSS
IVDD
RTC_
XTAL
K
L
FB_D30
FB_D26
SD_CLK
FB_D28
SDVDD
FB_D4
FB_D3
FB_D2
EVDD
FB_D0
FB_R/W
FB_OE
JTAG_EN RSTOUT
U0RXD
K
L
FB_BE/
BWE0
VDD_
ADC
VSS_
ADC
FB_D24 SD_A10 FB_D17
DDATA3
DDATA2
DDATA1
TDO
TDI
SD_
SDR_DQS
ADC_
REF
M
N
P
FB_D23
FB_D20
FB_D19
FB_D16
FB_D7
FB_D6
PST2
ADC_IN1 ADC_IN0
M
N
P
FB_BE/
BWE2
SD_CLK SD_CAS FB_D22
FB_CLK SD_RAS FB_D21
PST1
TMS
ADC_IN6 ADC_IN4 ADC_IN2
ADC_IN7 ADC_IN5 ADC_IN3
SD_
DQS0
FB_D18
FB_D5
FB_D1
TCLK
PST0
DDATA0
TRST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 8. MCF52277 Pinout (196 MAPBGA)
5
Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF5227x microprocessor. This
section contains detailed information on DC/AC electrical characteristics and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not
be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will
be met. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
15
Electrical Characteristics
NOTE
The parameters specified in this MCU document supersede any values found in the module
specifications.
5.1
Maximum Ratings
1, 2
Table 7. Absolute Maximum Ratings
Characteristic
Symbol
Value
Unit
Core Supply Voltage
IVDD
EVDD
–0.5 to +2.0
–0.3 to +4.0
–0.3 to +4.0
–0.3 to +4.0
–0.3 to +2.0
–0.5 to +2.0
–0.3 to +3.6
25
V
V
CMOS Pad Supply Voltage
DDR/Memory Pad Supply Voltage
Oscillator Supply Voltage
PLL Supply Voltage
SDVDD
OSCVDD
PLLVDD
RTCVDD
VIN
V
V
V
RTC Supply Voltage
V
Digital Input Voltage 3
V
Instantaneous Maximum Current
ID
mA
Single pin limit (applies to all pins) 3, 4, 5
Operating Temperature Range (Packaged)
TA
(TL – TH)
–40 to +85
°C
°C
Storage Temperature Range
Tstg
–55 to +150
1
Functional operating conditions are given in Section 5.4, “DC Electrical Specifications.” Absolute maximum ratings
are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these
levels may affect device reliability or cause permanent damage to the device.
2
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is
advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages
to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic
voltage level (e.g., either VSS or EVDD).
3
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
4
5
All functional non-supply pins are internally clamped to VSS and EVDD
.
Power supply must maintain regulation within operating EVDD range during instantaneous and operating maximum
current conditions. If positive injection current (Vin > EVDD) is greater than IDD, the injection current may flow out of
EVDD and could result in external power supply going out of regulation. Insure external EVDD load will shunt current
greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power (ex; no
clock). Power supply must maintain regulation within operating EVDD range during instantaneous and operating
maximum current conditions.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
16
Freescale Semiconductor
Electrical Characteristics
5.2
Thermal Characteristics
Table 8. Thermal Characteristics
196
MAPBGA
176
Unit
Characteristic
Symbol
LQFP
Junction to ambient, natural convection Four layer board (2s2p)
θJA
θJMA
θJB
θJC
Ψjt
381,2
341,2
273
481,2
421,2
373
°C/W
°C/W
°C/W
°C/W
°C/W
oC
Junction to ambient (@200 ft/min)
Junction to board
Four layer board (2s2p)
Junction to case
174
144
Junction to top of package
Maximum operating junction temperature
41,5
31,5
Tj
105
105
1
θ
JA, θJMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
Freescale recommends the use of θJmA and power dissipation specifications in the system design to prevent device
junction temperatures from exceeding the rated specification. System designers should be aware that device
junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the
device junction temperature specification can be verified by physical measurement in the customer’s system using
the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.
2
3
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
4
5
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written in conformance with Psi-JT.
The average chip-junction temperature (T ) in °C can be obtained from:
J
TJ = TA + (PD × ΘJMA
)
Eqn. 1
Where:
TA
= Ambient Temperature, °C
QJMA
PD
= Package Thermal Resistance, Junction-to-Ambient, °C/W
= PINT + PI/O
PINT
PI/O
= IDD × IVDD, Watts - Chip Internal Power
= Power Dissipation on Input and Output Pins — User Determined
For most applications P < P
and can be ignored. An approximate relationship between P and T (if P is neglected) is:
D J I/O
I/O
INT
K
---------------------------------
PD
=
Eqn. 2
(TJ + 273°C)
Solving equations 1 and 2 for K gives:
K = PD × (TA × 273°C) + QJMA × P2D
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively
A
D
J
for any value of T .
A
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
17
Electrical Characteristics
5.3
ESD Protection
1,2
Table 9. ESD Protection Characteristics
Characteristic
ESD Target for Human Body Model
Symbol
Value
2000
Unit
HBM
V
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits.
2
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing is performed per
applicable device specification at room temperature followed by hot temperature, unless specified
otherwise in the device specification.
5.4
DC Electrical Specifications
Table 10. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Unit
Core Supply Voltage
IVDD
PLLVDD
RTCVDD
EVDD
1.4
1.4
1.4
3.0
1.6
1.6
1.6
3.6
V
V
V
V
V
PLL Supply Voltage
RTC Supply Voltage
CMOS Pad Supply Voltage
SDRAM and FlexBus Supply Voltage
SDVDD
Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
1.7
2.25
3.0
1.95
2.75
3.6
USB Supply Voltage
USBVDD
OSCVDD
EVIH
3.0
3.0
3.6
3.6
V
V
V
V
V
Oscillator Supply Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
2
EVDD + 0.3
0.8
EVIL
VSS – 0.3
EVDD – 0.4
CMOS Output High Voltage
IOH = –5.0 mA
EVOH
—
CMOS Output Low Voltage
EVOL
—
0.4
V
V
IOL = 5.0 mA
SDRAM and FlexBus Input High Voltage
SDVIH
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
1.35
1.7
2
SDVDD + 0.3
SDVDD + 0.3
SDVDD + 0.3
SDRAM and FlexBus Input Low Voltage
SDVIL
V
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
VSS – 0.3
0.45
0.8
0.8
VSS – 0.3
VSS – 0.3
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
18
Freescale Semiconductor
Electrical Characteristics
Table 10. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
SDRAM and FlexBus Output High Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
IOH = –5.0 mA for all modes
SDVOH
V
1.4
2.1
2.4
—
—
—
SDRAM and FlexBus Output Low Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
IOL = 5.0 mA for all modes
SDVOL
V
—
—
—
0.3
0.3
0.5
Input Leakage Current
Iin
–1.0
–10
1.0
μA
Vin = VDD or VSS, Input-only pins
Weak Internal Pull-Up Device Current, tested at VIL Max.1
IAPU
Cin
–130
μA
Input Capacitance 2
pF
All input-only pins
All input/output (three-state) pins
—
—
7
7
1
Refer to the signals section for pins having weak internal pull-up devices.
This parameter is characterized before qualification rather than 100% tested.
2
5.5
Oscillator and PLL Electrical Characteristics
Table 11. PLL Electrical Characteristics
Num
Characteristic
Symbol
Min
Max
Unit
1
PLL Reference Frequency Range
Crystal reference
fref_crystal
fref_ext
16
16
251
MHz
MHz
External reference
66.671
2
Core/system frequency
CLKOUT Frequency
fsys
fsys/2
512 Hz2
256 Hz2
166.67
83.33
MHz
MHz
3
4
Crystal Start-up Time3,4
tcst
—
10
ms
EXTAL Input High Voltage
Crystal Mode5
VIHEXT
VIHEXT
VXTAL + 0.4
EVDD/2 + 0.4
—
—
V
V
All other modes (External, Limp)
5
EXTAL Input Low Voltage
Crystal Mode5
VILEXT
VILEXT
—
—
VXTAL – 0.4
EVDD/2 – 0.4
V
V
All other modes (External, Limp)
7
8
PLL Lock Time 3,6
tlpll
tdc
—
40
1
50000
60
CLKIN
%
Duty cycle of reference3
9
XTAL Current
IXTAL
3
mA
pF
10
11
12
Total on-chip stray capacitance on XTAL
Total on-chip stray capacitance on EXTAL
Crystal capacitive load
CS_XTAL
CS_EXTAL
CL
—
—
1.5
1.5
pF
See crystal spec
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
19
Electrical Characteristics
Num
Table 11. PLL Electrical Characteristics (continued)
Characteristic
Symbol
Min
Max
Unit
13
Discrete load capacitance for XTAL
Discrete load capacitance for EXTAL
CL_XTAL
CL_EXTAL
—
2 × (CL –
CS_XTAL –
pF
CS_EXTAL
–
7
CS_PCB
)
14
15
17
Frequency un-LOCK Range
Frequency LOCK Range
fUL
–4.0
–2.0
4.0
% fsys
% fsys
fLCK
Cjitter
2.0
CLKOUT period jitter 4, 5, 8 measured at fsys max
Peak-to-peak jitter (Clock edge to clock edge)
Long-term jitter
—
—
10
TBD
% fsys/2
% fsys/2
19
VCO frequency (fvco = fref × PFDR)
fvco
350
540
MHz
1
2
3
Although these are the allowable frequency ranges, do not violate the VCO frequency range of the PLL. See the
MCF5227x Reference Manual for more details.
The minimum system frequency is the minimum input clock divided by the maximum low-power divider
(16 MHz ÷ 32,768). When the PLL is enabled, the minimum system frequency (fsys) is 37.5 MHz.
This parameter is guaranteed by characterization before qualification rather than 100% tested. Applies to external clock
reference only.
4
5
6
Proper PC board layout procedures must be followed to achieve specifications.
This parameter is guaranteed by design rather than 100% tested.
This specification is the PLL lock time only and does not include oscillator start-up time..
7
8
CS_PCB is the measured PCB stray capacitance on EXTAL and XTAL.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
5.6
ASP Electrical Characteristics
Table 12 lists the electrical specifications for the ASP module.
Table 12. ASP Electrical Characteristics
Characteristic
ASP Analog Supply Voltage
Symbol
Min
Typical
Max
Unit
VDDA
VADIN
3.0
0
—
—
700
1
3.6
VDDA
—
V
V
Input Voltage Range
Operating Current Consumption
Power-down Current Consumption
Resolution
IDDA_ON
IDDA_OFF
RES
—
—
—
—
—
—
2
uA
—
uA
—
—
±8
±2
—
—
12
bits
kS/s
lsb1
lsb1
MHz
V
Sampling rate
125
±24
±24
8
Integral Non-linearity
Differential Non-linearity
ADC Internal Clock Frequency
Conversion Range
INL
DNL
tAIC
RAD
0
VDDA
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
20
Freescale Semiconductor
Electrical Characteristics
Table 12. ASP Electrical Characteristics (continued)
Characteristic
Symbol
Min
Typical
Max
Unit
Conversion Time
Sample Time
tADC
15
—
32
tAIC
cycles
tADS
tAMS
3
—
—
20
3
tAIC
cycles
Multiplexer Settling Time
—
tAIC
cycles
Zero-scale Error
Full-scale Error
Input Capacitance
ZE
FE
—
—
—
±4
±320
—
±12
±370
34
lsb1
lsb1
pF
CAIN
1
A least significant bit (lsb) is a unit of voltage equal to the smallest resolution of the ADC. This unit of measure approximately
relates the error voltage to the observed error in conversion (code error), and is useful for systemic errors such as differential
non-linearity. A 2.56-V input on an ADC with ± 3 lsb of error could read between 0x1FD and 0x203. This unit is by far the most
common terminology and will be the preferred unit used for error representation.
A bit is a unit equal to the log (base2) of the error voltage normalized to the resolution of the ADC. An error of N bits
corresponds to 2N lsb of error. This measure is easily confused with lsb and is hard to extrapolate between integer values.
5.7
External Interface Timing Specifications
FlexBus
5.7.1
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up
to a maximum bus frequency of 66MHz. It can be directly connected to asynchronous or synchronous devices such as external
boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices a simple chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of
a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the Flexbus output
clock, FB_CLK. All other timing relationships can be derived from these values.
Table 13. FlexBus AC Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
Frequency of Operation
FB1 Clock Period (FB_CLK)
—
12.0
—
83.33
—
MHz
ns
fsys/2
tFBCK
tcyc
1
FB2 Address, Data, and Control Output Valid (FB_A[23:0], FB_D[31:0], tFBCHDCV
FB_CS[5:0], FB_R/W, FB_TS, FB_BE/BWE[3:0] and FB_OE)
7.0
ns
1, 2
FB3 Address, Data, and Control Output Hold (FB_A[23:0], FB_D[31:0], tFBCHDCI
FB_CS[5:0], FB_R/W, FB_TS, FB_BE/BWE[3:0], and FB_OE)
1
—
ns
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
21
Electrical Characteristics
Num
Table 13. FlexBus AC Timing Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
Notes
FB4 Data Input Setup
FB5 Data Input Hold
tDVFBCH
tDIFBCH
tCVFBCH
tCIFBCH
3.5
0
—
—
—
—
ns
ns
ns
ns
FB6 Transfer Acknowledge (TA) Input Setup
FB7 Transfer Acknowledge (TA) Input Hold
4
0
1
2
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2.2, “DDR SDRAM AC Timing
Specifications,” for SD_CS[3:0] timing.
The FlexBus supports programming an extension of the address hold. Please consult the device reference manual for more
information.
NOTE
The processor drives the data lines during the first clock cycle of the transfer with the full
32-bit address. This may be ignored by standard connected devices using non-multiplexed
address and data buses. However, some applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM controller. At
the end of the read and write bus cycles the address signals are indeterminate.
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB2
FB5
FB_D[31:X]
ADDR[31:X]
DATA
FB4
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB6
FB7
FB_TA
Figure 9. FlexBus Read Timing
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
22
Freescale Semiconductor
Electrical Characteristics
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB2
ADDR[31:X]
FB_D[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB6
FB7
FB_TA
Figure 10. Flexbus Write Timing
5.7.2
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard
SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.2.1
SDR SDRAM AC Timing Specifications
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus
clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller
is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to the
device for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during
read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
Table 14. SDR Timing Specifications
Num
Characteristic
Frequency of Operation
Symbol
Min
Max
Unit
Notes
1
60
12.0
0.45
0.45
—
83.33
16.67
0.55
MHz
ns
2
3
3
SD1 Clock Period
tSDCK
tSDCKH
SD2 Pulse Width High
SD3 Pulse Width Low
SD_CLK
SD_CLK
ns
tSDCKH
0.55
SD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Valid
tSDCHACV
0.5 × SD_CLK
+ 1.0
SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Hold
tSDCHACI
2.0
—
—
ns
4
5
SD6 SD_SDR_DQS Output Valid
tDQSOV
Self timed
ns
ns
SD7 SD_DQS[3:2] input setup relative to SD_CLK
tDQVSDCH
0.25 ×
0.40 × SD_CLK
SD_CLK
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
23
Electrical Characteristics
Num
Table 14. SDR Timing Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
Notes
6
SD8 SD_DQS[3:2] input hold relative to SD_CLK
tDQISDCH
Does not apply. 0.5×SD_CLK fixed
width.
7
SD9 Data (D[31:0]) Input Setup relative to SD_CLK (reference
only)
tDVSDCH
0.25 ×
SD_CLK
—
—
ns
SD10 Data Input Hold relative to SD_CLK (reference only)
tDISDCH
1.0
—
ns
ns
SD11 Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid tSDCHDMV
0.5 × SD_CLK
+ 2
SD12 Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold tSDCHDMI
1.5
—
ns
1
The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock.
Please see the PLL chapter of the device reference manual for more information on setting the SDRAM clock rate.
2
3
4
SD_CLK is one SDRAM clock in ns.
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD_SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle
variation from this guideline is expected. SD_SDR_DQS will only pulse during a read cycle and one pulse will occur for each
data beat.
5
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data
beat.
6
7
The SD_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
Since a read cycle in SDR mode still uses the DQS circuit within the device, it is critical that the data valid window be centered
1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup spec is
provided as guidance.
SD2
SD1
SD_CLK
SD3
SD5
SD_CSn
SD_RAS
SD_CAS
SD_WE
CMD
ROW
SD4
A[23:0]
SD_BA[1:0]
COL
SD11
SDDM
D[31:0]
SD12
WD2
WD1
WD3
WD4
Figure 11. SDR Write Timing
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
24
Freescale Semiconductor
Electrical Characteristics
SD2
SD1
SD_CLK
SD5
SD_CSn,
SD_RAS,
SD_CAS,
SD_WE
SD3
CMD
ROW
3/4 MCLK
Reference
SD4
A[23:0],
SD_BA[1:0]
COL
tDQS
SDDM
SD6
SD_SDR_DQS (Measured at Output Pin)
SD_DQS[3:2] (Measured at Input Pin)
Board Delay
SD8
SD7
Board Delay
Delayed
SD_CLK
SD9
D[31:0]
from
WD1
WD2
WD3
WD4
Memories
NOTE: Data driven from memories relative
to delayed memory clock.
SD10
Figure 12. SDR Read Timing
5.7.2.2
DDR SDRAM AC Timing Specifications
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive
data onto the memory bus. All timing numbers are relative to the two DQS byte lanes.
Table 15. DDR Timing Specifications
Num
Characteristic
Frequency of Operation
Symbol
Min
Max
Unit
Notes
1
tDDCK
tDDSK
60
12.0
0.45
0.45
—
83.33
16.67
0.55
MHz
ns
2
3
3
4
DD1 Clock Period
DD2 Pulse Width High
DD3 Pulse Width Low
tDDCKH
tDDCKL
tSDCHACV
SD_CLK
SD_CLK
ns
0.55
DD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid
0.5 × SD_CLK
+ 1.0
DD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
tSDCHACI
2.0
—
ns
DD6 Write Command to first DQS Latching Transition
tCMDVDQ
tDQDMV
—
1.25
—
SD_CLK
ns
5
6
DD7 Data and Data Mask Output Setup (DQ→DQS)
1.5
Relative to DQS (DDR Write Mode)
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
25
Electrical Characteristics
Num
Table 15. DDR Timing Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
Notes
7
DD8 Data and Data Mask Output Hold (DQS→DQ) Relative tDQDMI
1.0
—
ns
to DQS (DDR Write Mode)
8
9
DD9 Input Data Skew Relative to DQS (Input Setup)
DD10 Input Data Hold Relative to DQS
tDVDQ
tDIDQ
—
1
ns
ns
0.25 × SD_CLK
—
+ 0.5ns
DD11 DQS falling edge from SDCLK rising (output hold time) tDQLSDCH
0.5
—
ns
1
The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the
same frequency as the internal bus clock.
2
3
4
SD_CLK is one SDRAM clock in ns.
Pulse-width high plus pulse-width low cannot exceed minimum or maximum clock period.
Command output valid should be one-half the memory bus clock (SD_CLK) plus some minor adjustments for process,
temperature, and voltage variations.
5
This specification relates to the required input setup time of today’s DDR memories. The device’s output setup should be larger
than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_DATA[7:0] is relative MEM_DQS[0].
6
7
The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
will be valid for each subsequent DQS edge.
This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_DATA[7:0] is relative
MEM_DQS[0].
8
9
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system-level board skew (due to routing or other
factors).
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes
invalid.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
26
Freescale Semiconductor
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
SD_CSn, SD_WE,
SD_RAS, SD_CAS
CMD
DD4
A[13:0]
ROW
COL
DD11
SD_DQS[3:2]
SD_DM[3:2]
D[31:16]
DD6
DD7
WD1 WD2 WD3 WD4
DD8
Figure 13. DDR Write Timing
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
27
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
CL=2
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
ROW
DD4
CL=2.5
A[13:0]
COL
DD9
DQS Read
Postamble
DQS Read
Preamble
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
DD10
WD1 WD2 WD3 WD4
DQS Read
Preamble
DQS Read
Postamble
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
Figure 14. DDR Read Timing
Table 16. DDR Clock Crossover Specifications
Symbol
VMP
VOUT Clock output voltage level
Characteristic
Min
Max
Unit
Clock output mid-point voltage
1.05
–0.3
0.7
1.45
V
V
V
V
SD_VDD + 0.3
SD_VDD + 0.6
1.45
VID
VIX
Clock output differential voltage (peak to peak swing)
Clock crossing point voltage1
1.05
1
The clock crossover voltage is only guaranteed when using the highest drive strength option for the SDCLK[1:0] and
SDCLK[1:0] signals.
SD_CLK
VIX
VID
VMP
VIX
SD_CLK
Figure 15. SD_CLK and SD_CLK Crossover Timing
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
28
Freescale Semiconductor
Electrical Characteristics
5.8
General Purpose I/O Timing
1
Table 17. GPIO Timing
Num
Characteristic
Symbol
Min
Max
Unit
G1 FB_CLK High to GPIO Output Valid
G2 FB_CLK High to GPIO Output Invalid
G3 GPIO Input Valid to FB_CLK High
G4 FB_CLK High to GPIO Input Invalid
tCHPOV
tCHPOI
tPVCH
tCHPI
—
1.5
9
10
—
—
—
ns
ns
ns
ns
1.5
1
These general purpose specifications apply to the following signals: IRQn, all UART signals, FlexCAN signals, PWM
signals, DACKn and DREQn, and all signals configured as GPIO.
FB_CLK
G2
G1
GPIO Outputs
GPIO Inputs
G3
G4
Figure 16. GPIO Timing
5.9
Reset and Configuration Override Timing
Table 18. Reset and Configuration Override Timing
Num
Characteristic
Symbol
Min
Max
Unit
R1 RESET Input valid to FB_CLK High
tRVCH
tCHRI
9
1.5
5
—
—
—
10
—
—
—
1
ns
ns
R2 FB_CLK High to RESET Input invalid
R3 RESET Input valid Time 1
tRIVT
tCYC
ns
R4 FB_CLK High to RSTOUT Valid
tCHROV
tROVCV
tCOS
—
0
R5 RSTOUT valid to Config. Overrides valid
R6 Configuration Override Setup Time to RSTOUT invalid
R7 Configuration Override Hold Time after RSTOUT invalid
R8 RSTOUT invalid to Configuration Override High Impedance
ns
20
0
tCYC
ns
tCOH
tROICZ
—
tCYC
1
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to
the system. Thus, RESET must be held a minimum of 100 ns.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
29
Electrical Characteristics
FB_CLK
R1
R2
R3
RESET
R4
R4
RSTOUT
R8
R5
R6
R7
Configuration Overrides*:
(RCON, Override pins)
Figure 17. RESET and Configuration Override Timing
NOTE
Refer to the CCM chapter of the MCF52277 Reference Manual for more information.
5.10 LCD Controller Timing Specifications
This sections lists the timing specifications for the LCD Controller.
Table 19. LCD_LSCLK Timing
Num
Characteristic
Min
Max
Unit
T1
T2
T3
LCD_LSCLK Period
Pixel data setup time
Pixel data up time
25
11
11
2000
—
ns
ns
ns
—
Note: The pixel clock is equal to LCD_LSCLK / (PCD + 1). When it is in CSTN, TFT, or monochrome mode with
bus width = 1, LCD_LSCLK is equal to the pixel clock. When it is in monochrome with other bus width
settings, LCD_LSCLK is equal to the pixel clock divided by bus width. The polarity of LCD_LSCLK and
LCD_D signals can also be programmed.
T1
LCD_LSCLK
LCD_D[17:0]
T2
T3
Figure 18. LCD_LSCLK to LCD_D[17:0] timing diagram
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
30
Freescale Semiconductor
Electrical Characteristics
Non-display Region
Display Region
T3
T1
T4
LCD_VSYNC
LCD_HSYNC
LCD_OE
T2
Line Y
Line 1
Line Y
LCD_D[17:0]
T5
T6
XMAX
T7
LCD_HSYNC
LCD_LSCLK
LCD_OE
(1,1)
(1,2)
LCD_D[15:0]
(1,X)
Figure 19. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Table 20. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing
Num
Characteristic
Min
Value
Unit
T1 End of LCD_OE to beginning of LCD_VSYNC
T5 + T6 + T7 – 1
(VWAIT1 × T2) +
Ts
T5 + T6 + T7 – 1
T2 LCD_HSYNC period
—
T2
1
XMAX+T5+T6+T7
VWIDTH × T2
(VWAIT2 × T2)+1
HWIDTH + 1
Ts
Ts
Ts
Ts
Ts
Ts
T3 LCD_VSYNC pulse width
T4 End of LCD_VSYNC to beginning of LCD_OE
T5 LCD_HSYNC pulse width
1
T6 End of LCD_HSYNC to beginning to LCD_OE
T7 End of LCD_OE to beginning of LCD_HSYNC
3
HWAIT2 + 3
1
HWAIT1 + 1
Note: Ts is the LCD_LSCLK period. LCD_VSYNC, LCD_HSYNC, and LCD_OE can be programmed as active high or active
low. In Figure 19, all 3 signals are active low. LCD_LSCLK can be programmed to be deactivated during the
LCD_VSYNC pulse or the LCD_OE deasserted period. In Figure 19, LCD_LSCLK is always active.
Note: XMAX is defined in number of pixels in one line.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
31
Electrical Characteristics
XMAX
LCD_LSCLK
LCD_D
LCD_SPL_SPR
LCD_HSYNC
D2
D1
D320
D320
T1
T2
T3
T2
T4
T4
LCD_CLS
LCD_PS
T5
T6
T7
T7
LCD_REV
Figure 20. Sharp TFT Panel Timing
Table 21. Sharp TFT Panel Timing
Num
Characteristic
Min
Value
Unit
T1
T2
T3
T4
T5
T6
T7
LCD_SPL/LCD_SPR pulse width
—
1
1
Ts
Ts
Ts
Ts
Ts
Ts
Ts
End of LCD_D of line to beginning of LCD_HSYNC
End of LCD_HSYNC to beginning of LCD_D of line
LCD_CLS rise delay from end of LCD_D of line
LCD_CLS pulse width
HWAIT1+1
HWAIT2 + 4
4
3
CLS_RISE_DELAY+1
CLS_HI_WIDTH+1
PS_RISE_DELAY
1
LCD_PS rise delay from LCD_CLS negation
LCD_REV toggle delay from last LCD_D of line
0
1
REV_TOGGLE_DELAY+1
Note: Falling of LCD_SPL/LCD_SPR aligns with first LCD_D of line.
Note: Falling of LCD_PS aligns with rising edge of LCD_CLS.
Note: LCD_REV toggles in every LCD_HSYN period.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
32
Freescale Semiconductor
Electrical Characteristics
T1
T1
LCD_VSYNC
T3
T4
T2
T2
XMAX
LCD_HSYNC
LCD_LSCLK
Ts
LCD_D[15:0]
Figure 21. Non-TFT Mode Panel Timing
Table 22. Non-TFT Mode Panel Timing
Num
Characteristic
Min
Value
Unit
T1
T2
T3
T4
LCD_HSYNC to LCD_VSYNC delay
LCD_HSYNC pulse width
2
1
HWAIT2 + 2
HWIDTH + 1
0 ≤ T3 ≤ Ts
HWAIT1 + 1
Tpix
Tpix
—
LCD_VSYNC to LCD_LSCLK
LCD_LSCLK to LCD_HSYNC
—
1
Tpix
Note: Ts is the LCD_LSCLK period while Tpix is the pixel clock period. LCD_VSYNC, LCD_HSYNC, and
LCD_LSCLK can be programmed as active high or active low. In Figure 21, all these 3 signals are active
high. When it is in CSTN mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in
monochrome mode with bus width = 2, 4 and 8, T3 = 1, 2 and 4 Tpix respectively.
5.11 USB On-The-Go Specifications
The MCF5227x device is compliant with industry standard USB 2.0 specification.
Table 23. USB On-Chip Transceiver DC Characteristics
Characteristic
Condition Symbol
Min
Typ
Max
Unit
Input High
Input Low
Driven
VIH
VIL
2.0
—
—
—
—
0.8
00
V
V
Input Differential
(DP – DM)
VID
200
0.8
0.8
—
—
mV
V
Differential Common Mode Range
Single Ended Receive Threshold
Single Ended Receive Hysteresis
Output High
VCM
—
2.5
2.0
—
VSETHR
VSEHYS
VOH
—
V
400
—
mV
mV
V
Driven
Driven
0.0
2.8
1.3
300
2.0
2.0
Output Low
VOL
—
Differential Output Crossover
DP = DM
VCRS
—
V
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
33
Electrical Characteristics
Table 23. USB On-Chip Transceiver DC Characteristics (continued)
Characteristic
Condition Symbol
Min
Typ
Max
Unit
P side Impedance
Driven
Driven
ZP
ZM
6.25
6.25
—
8.25
8.25
0.17
50k
11.25
11.25
0.23
70k
Ω
Ω
Ω
Ω
M side Impedance
Impedance Matching P/M
Pulldown Resistance1
ZMatching
RPD
30k
1
The pulldown resistors are included to provide a method to keep DP and DM signals in a known quiescent state
if desired when the USB port is not being used or when the USB cable is not connected. These on-chip
resistors should not be used to provide the 15-kΩ host-mode pulldowns called for in Chapter 7 of the USB
Specification, Rev. 1.1 or Rev. 2.0.
Table 24. USB On-Chip Transceiver Full Speed AC Characteristics
Characteristic
Condition
Symbol
Min
Typ
Max
Unit
Rise Time
Fall Time
10–90%
90–10%
—
tLH
tHL
7
7
11
11
40
17.5
17.5
60
ns
ns
ps
tLH
-------
Rise/Fall Matching
20
Matching
tHL
tLH
Rise/Fall Matching, DP and DM
TIme Skew Between DP and DM
—
—
330
100
360
140
640
210
ps
ps
-------
Pad-to-Pad
tSKE
tHL
Table 25. USB On-Chip Transceiver Low Speed AC Characteristics
Characteristic
Condition
Symbol
Min
Typ
Max
Unit
Rise Time
Fall Time
10–90%
90–10%
tLH
tHL
75
75
80
—
—
—
300
300
125
ns
ns
%
tLH
-------
tHL
tLH
-------
Rise/Fall Matching
Matching
tHL
5.12 SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
1
Table 26. SSI Timing—Master Modes
Num
Characteristic
SSI_MCLK cycle time
Symbol
Min
Max
Unit
Notes
2
S1
S2
S3
S4
tMCLK 4 × 1/fSYS
45%
—
55%
—
ns
tMCLK
ns
SSI_MCLK pulse width high / low
SSI_BCLK cycle time
3
tBCLK 4 × 1/fSYS
45%
SSI_BCLK pulse width
55%
tBCLK
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
34
Freescale Semiconductor
Electrical Characteristics
1
Table 26. SSI Timing—Master Modes (continued)
Num
Characteristic
Symbol
Min
Max
Unit
Notes
S5
S6
S7
S8
S9
SSI_BCLK to SSI_FS output valid
—
0
10
—
10
—
—
—
ns
ns
ns
ns
ns
ns
SSI_BCLK to SSI_FS output invalid
SSI_BCLK to SSI_TXD valid
—
0
SSI_BCLK to SSI_TXD invalid / high impedence
SSI_RXD / SSI_FS input setup before SSI_BCLK
10
0
S10 SSI_RXD / SSI_FS input hold after SSI_BCLK
1
2
3
All timings specified with a capactive load of 25pF.
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK).
SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum
divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does not
exceed 4 x fSYS
.
1
Table 27. SSI Timing—Slave Modes
Characteristic Symbol
Num
Min
Max
Unit
Notes
S11 SSI_BCLK cycle time
tBCLK 4 × 1/fSYS
—
55%
—
ns
tBCLK
ns
S12 SSI_BCLK pulse width high / low
S13 SSI_FS input setup before SSI_BCLK
S14 SSI_FS input hold after SSI_BCLK
S15 SSI_BCLK to SSI_TXD / SSI_FS output valid
45%
10
2
—
ns
—
0
10
ns
S16 SSI_BCLK to SSI_TXD / SSI_FS output invalid / high
impedence
—
ns
S17 SSI_RXD setup before SSI_BCLK
S18 SSI_RXD hold after SSI_BCLK
10
2
—
—
ns
ns
1
All timings specified with a capactive load of 25 pF.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
35
Electrical Characteristics
S1
S2
S2
SSI_MCLK
(Output)
S3
SSI_BCLK
(Output)
S4
S4
S5
S6
SSI_FS
(Output)
S9
S10
SSI_FS
(Input)
S7
S8
S7
S8
SSI_TXD
SSI_RXD
S9
S10
Figure 22. SSI Timing—Master Modes
S11
SSI_BCLK
(Input)
S12
S12
S15
S16
SSI_FS
(Output)
S13
S14
SSI_FS
(Input)
S15
S16
S16
S15
SSI_TXD
SSI_RXD
S17
S18
Figure 23. SSI Timing—Slave Modes
2
5.13 I C Timing Specifications
2
Table 28 lists specifications for the I C input timing parameters shown in Figure 24.
2
Table 28. I C Input Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Unit
I1
I2
I3
I4
Start condition hold time
Clock low period
2
8
—
—
1
tcyc
tcyc
ms
ns
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
—
0
—
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
36
Freescale Semiconductor
Electrical Characteristics
Table 28. I C Input Timing Specifications between SCL and SDA (continued)
2
Num
Characteristic
Min
Max
Unit
I5
I6
I7
I8
I9
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
Clock high time
—
4
1
ms
tcyc
ns
—
—
—
—
Data setup time
0
Start condition setup time (for repeated start condition only)
Stop condition setup time
2
tcyc
tcyc
2
2
Table 29 lists specifications for the I C output timing parameters shown in Figure 24.
2
Table 29. I C Output Timing Specifications between SCL and SDA
Num
I11 Start condition hold time
I21 Clock low period
Characteristic
Min
Max
Unit
6
—
—
—
—
3
tcyc
tcyc
µs
10
—
7
I32 I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
I41 Data hold time
tcyc
ns
I53 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
I61 Clock high time
—
10
2
—
—
—
—
tcyc
tcyc
tcyc
tcyc
I71 Data setup time
I81 Start condition setup time (for repeated start condition only)
I91 Stop condition setup time
20
10
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 29. The I2C interface is designed
to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is
affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 29
are minimum values.
2
3
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
Specified at a nominal 50-pF load.
Figure 24 shows timing for the values in Table 29 and Table 28.
I5
I6
I2
I2C_SCL
I2C_SDA
I7
I8
I1
I9
I4
I3
2
Figure 24. I C Input/Output Timings
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
37
Electrical Characteristics
5.14 DMA Timer Timing Specifications
Table 30 lists timer module AC timings.
Table 30. Timer Module AC Timing Specifications
Characteristic Min
Num
Max
Unit
T1
T2
DT0IN / DT1IN / DT2IN / DT3IN cycle time
DT0IN / DT1IN / DT2IN / DT3IN pulse width
3
1
—
—
tCYC
tCYC
5.15 DSPI Timing Specifications
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with both master and slave operations. Many
of the transfer attributes are programmable. Table 31 provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the MCF52277 Reference Manual for information on the modified transfer formats used for
communicating with slower peripheral devices.
1
Table 31. DSPI Module AC Timing Specifications
Num
Characteristic
DSPI_SCK Cycle Time
DSPI_SCK Duty Cycle
Symbol
Min
Max
Unit
Notes
2
DS1
DS2
tSCK
—
4 x 1/fSYS
—
ns
ns
(tsck ÷ 2) – 2.0 (tsck ÷ 2) + 2.0
Master Mode
3
4
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_PCSn to DSPI_SCK delay
tCSC
tASC
—
(2 × 1/fSYS) – 2.0
—
—
5
ns
ns
ns
ns
ns
ns
DSPI_SCK to DSPI_PCSn delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
(2 × 1/fSYS) – 3.0
—
–5
9
—
—
—
—
—
—
0
Slave Mode
DS9
DSPI_SCK to DSPI_SOUT valid
—
—
—
—
—
—
—
0
4
ns
ns
ns
ns
ns
ns
DS10 DSPI_SCK to DSPI_SOUT invalid
DS11 DSPI_SIN to DSPI_SCK input setup
DS12 DSPI_SCK to DSPI_SIN input hold
DS13 DSPI_SS active to DSPI_SOUT driven
DS14 DSPI_SS inactive to DSPI_SOUT not driven
—
—
—
20
18
2
7
—
—
1
Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin on the
odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges.
2
3
4
When in master mode, the baud rate is programmable in DCTARn[PBR] and DCTARn[BR].
The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK].
The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
38
Freescale Semiconductor
Electrical Characteristics
DS3
DS4
DSPI_PCSn
DS1
DS2
DSPI_SCK
(DCTARn[CPOL] = 0)
DS2
DSPI_SCK
(DCTARn[CPOL] = 1)
DS7
DS8
DSPI_SIN
Last Data
First Data
Data
Data
DS6
DS5
DSPI_SOUT
First Data
Last Data
Figure 25. DSPI Classic SPI Timing—Master Mode
DSPI_SS
DS1
DSPI_SCK
DS2
(DCTARn[CPOL] = 0)
DS2
DSPI_SCK
(DCTARn[CPOL] = 1)
DS13
DS9
DS10
Data
DS14
First Data
DSPI_SOUT
DSPI_SIN
Last Data
DS11
DS12
Data
Last Data
First Data
Figure 26. DSPI Classic SPI Timing—Slave Mode
5.16 SBF Timing Specifications
The Serial Boot Facility (SBF) provides a means to read configuration information and system boot code from a broad array of
SPI-compatible EEPROMs, flashes, FRAMs, nVSRAMs, etc. Table 32 provides the AC timing specifications for the SBF.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
39
Electrical Characteristics
Num
Table 32. SBF AC Timing Specifications
Characteristic
Symbol
Min
Max
Unit
Notes
1
SB1
SB2
SB3
SB4
SB5
SB6
SB7
SB8
SBF_CK Cycle Time
SBF_CK High/Low Time
tSBFCK
—
30
—
—
—
—
12
—
—
—
ns
tSBFCK
ns
30%
SBF_CS to SBF_CK delay
SBF_CK to SBF_CS delay
SBF_CK to SBF_DO valid
SBF_CK to SBF_DO invalid
SBF_DI to SBF_SCK input setup
SBF_CK to SBF_DI input hold
—
tSBFCK – 2.0
—
tSBFCK – 2.0
ns
—
—
0
ns
—
ns
—
6
ns
—
0
ns
1
At reset, the SBF_CK cycle time is tREF × 67. The first byte of data read from the serial memory contains a divider
value that is used to set the SBF_CK cycle time for the duration of the serial boot process.
SB1
SB4
SB2
SB2
SBF_CK
SBF_CS
SB3
SB7 SB8
SBF_DI
Last Data
SB5
First Data
SB6
Data
Data
SBF_DO
First Data
Last Data
Figure 27. SBF Timing
5.17 JTAG and Boundary Scan Timing Specifications
Table 33. JTAG and Boundary Scan Timing
Num
Characteristic1
TCLK Frequency of Operation
Symbol
Min
Max
Unit
J1
J2
J3
J4
J5
J6
J7
J8
fJCYC
tJCYC
tJCW
DC
4
1/4
—
—
3
fsys/2
tCYC
ns
TCLK Cycle Period
TCLK Clock Pulse Width
26
0
TCLK Rise and Fall Times
tJCRF
tBSDST
tBSDHT
tBSDV
tBSDZ
ns
Boundary Scan Input Data Setup Time to TCLK Rise
Boundary Scan Input Data Hold Time after TCLK Rise
TCLK Low to Boundary Scan Output Data Valid
TCLK Low to Boundary Scan Output High Z
4
—
—
33
33
ns
26
0
ns
ns
0
ns
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
40
Freescale Semiconductor
Electrical Characteristics
Table 33. JTAG and Boundary Scan Timing (continued)
Num
Characteristic1
Symbol
Min
Max
Unit
J9
TMS, TDI Input Data Setup Time to TCLK Rise
tTAPBST
tTAPBHT
tTDODV
tTDODZ
tTRSTAT
tTRSTST
4
10
0
—
—
26
8
ns
ns
ns
ns
ns
ns
J10 TMS, TDI Input Data Hold Time after TCLK Rise
J11 TCLK Low to TDO Data Valid
J12 TCLK Low to TDO High Z
0
J13 TRST Assert Time
100
10
—
—
J14 TRST Setup Time (Negation) to TCLK High
1
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
J2
J3
J3
VIH
VIL
TCLK
(input)
J4
J4
Figure 28. Test Clock Input Timing
TCLK
VIL
VIH
J5
J6
Data Inputs
Input Data Valid
J7
J8
Data Outputs
Output Data Valid
Data Outputs
Data Outputs
J7
Output Data Valid
Figure 29. Boundary Scan (JTAG) Timing
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
41
Electrical Characteristics
TCLK
VIL
VIH
J9
Input Data Valid
J10
TDI
TMS
J11
TDO
Output Data Valid
J12
J11
TDO
TDO
Output Data Valid
Figure 30. Test Access Port Timing
TCLK
TRST
J14
J13
Figure 31. TRST Timing
5.18 Debug AC Timing Specifications
Table 34 lists specifications for the debug AC timing parameters shown in Figure 32.
Table 34. Debug AC Timing Specification
Num
Characteristic
PSTCLK cycle time
Min
Max
Units
D0
D1
D2
D3
D41
D5
D6
1
—
1.5
1
1
3.0
—
—
—
—
—
1/fSYS
ns
PSTCLK rising to PSTDDATA valid
PSTCLK rising to PSTDDATA invalid
DSI-to-DSCLK setup
ns
PSTCLK
PSTCLK
PSTCLK
PSTCLK
DSCLK-to-DSO hold
4
DSCLK cycle time
5
BKPT assertion time
1
1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative
to the rising edge of PSTCLK.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
42
Freescale Semiconductor
Package Information
D0
PSTCLK
D2
D1
PSTDDATA[7:0]
Figure 32. Real-Time Trace AC Timing
D5
DSCLK
DSI
D3
Current
D4
Next
DSO
Past
Current
Figure 33. BDM Serial Port AC Timing
6
Package Information
The latest package outline drawings are available on the product summary pages on our web site:
http://www.freescale.com/coldfire. The following table lists the case outline numbers per device. Use these numbers in the web
page’s keyword search engine to find the latest package outline drawings.
Table 35. Package Information
Device
Package Type
Mask Set
Revision
Case Outline Numbers
MCF52274
176 LQFP
All
All
1.1
98ASS23479W
98ASH98061A
98ARH98390A
M26H
MCF52277
196 MAPBGA
2M26H, 3M26H
1.2–1.3
7
Product Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution
Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire.
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
43
Revision History
8
Revision History
Table 36 summarizes revisions to this document.
f
Table 36. MCF52277 Data Sheet Revision History
Rev. No. Date of Release Summary of Changes
3
4
02/2008
05/2008
Initial public revision.
Corrected MCF52274 order number from MCF52274CAB120 to
MCF52274CLU120 in Table 2
5
07/2008
Corrected MCF52277CVM166 part number to MCF52277CVM160 in Table 2.
Although, this device has a maximum rated frequency of 166.67 MHz.
6
7
07/2008
02/2009
Added data to Section 3.5, “Power Consumption Specifications.”
Changed document type from Data Sheet: Advance Information to Data Sheet:
Technical Data and corresponding footnote on first page
Replaced tSYS with 1/fSYS throughout
Changed the following specs in Table 14 and Table 15:
• Minimum frequency of operation from TBD to 60MHz
• Maximum clock period from TBD to 16.67 ns
Added RTC and Oscillator Supply Voltage specs to Table 7 and Table 10
In Table 8:
• Updated thermal characteristics for the 196 MAPBGA package
• Added thermal characteristics for the 176 LQFP package that were TBD
In Table 11:
• Corrected maximum crystal reference frequency range from 66.67 to 25 MHz
• Added footnotes to maximum crystal and external reference frequency ranges
• Changed minimum core/system and CLKOUT frequencies from TBD to 512 and
256 Hz, respectively.
In Table 12:
• Added Typical column
• Removed Internal Reference Voltage spec as it isn’t necessary
• Moved Current Consumption specs from maximum column to typical column
• Added INL and DNL specs that were TBD, and changed the unit footnote
• Replaced Gain and Offset Error specs with Full-Scale and Zero-Scale Error
• Removed Input Leakage Current and Input Current specs as they aren’t
necessary
Removed Gain Calculations section as it isn’t necessary
8
09/2009
Iin Table 35, added case outline number for MCF52277 masks 2M26H and 3M26H
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
44
Freescale Semiconductor
Revision History
MCF5227x ColdFire® Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
45
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Document Number: MCF52277
Rev. 8
09/2009
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