935314156557_技术文档

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MCIMX35SR2AEC

Rev. 10, 06/2012

IMX35

Package Information

Plastic Package

Case 5284 17 x 17 mm, 0.8 mm Pitch

i.MX35 Applications

Processors for

Automotive Products

Ordering Information

See Table 1 on page 3 for ordering information.

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1 Introduction

The i.MX35 Auto Application Processor family is

designed for automotive infotainment and navigation

applications. These processors are AECQ100 Grade 3

qualified and rated for ambient operating temperatures

up to 85 °C.

2

Functional Description and Application Information. . . . . . 4

2.1. Application Processor Domain Overview. . . . . . . . . 5

2.2. Shared Domain Overview . . . . . . . . . . . . . . . . . . . . 6

2.3. Advanced Power Management Overview . . . . . . . . 6

2.4. ARM11 Microprocessor Core. . . . . . . . . . . . . . . . . . 6

2.5. Module Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3. Signal Descriptions: Special Function Related Pins . . . . 12

4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1. i.MX35 Chip-Level Conditions . . . . . . . . . . . . . . . . 13

4.2. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3. Supply Power-Up/Power-Down Requirements and

Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.4. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.5. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . 19

4.6. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . 20

4.7. I/O Pin DC Electrical Characteristics . . . . . . . . . . . 21

4.8. I/O Pin AC Electrical Characteristics . . . . . . . . . . . 24

4.9. Module-Level AC Electrical Specifications. . . . . . . 30

5. Package Information and Pinout . . . . . . . . . . . . . . . . . . 131

5.1. MAPBGA Production Package 1568-01, 17 × 17 mm,

0.8 Pitch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Based on an ARM11 microprocessor core running at up

to 532 MHz, the device offers the following features and

optimized system cost for the target applications.

•

Audio connectivity and telematics:

— Compressed audio playback from storage

devices (CD, USB, HDD or SD card)

— PlayFromDevice (1-wire and 2-wire

support) for portable media players

— iPod/iPhone control and playback

— High-speed CD ripping to USB, SD/MMC

or HDD for virtual CD changer

5.2. MAPBGA Signal Assignments. . . . . . . . . . . . . . . 133

6. Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . 145

7. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

— Audio processing for hands-free telephony:

Bluetooth, AEC/NS, and microphone beam

forming

— Speech recognition

•

A/V connectivity and navigation:

— Includes audio connectivity and telematics features

— Map display and route calculation

— QVGA video decode, WVGA video display

— Sophisticated graphical user interface

The i.MX35 processor takes advantage of the ARM1136JF-S™ core running at 532 MHz that is boosted

by a multilevel cache system, and features peripheral devices such as an autonomous image processing

unit, a vector floating point (VFP11) co-processor, and a RISC-based DMA controller.

The i.MX35 supports connections to various types of external memories, such as SDRAM, mobile DDR

and DDR2, SLC and MLC NAND Flash, NOR Flash and SRAM. The device can be connected to a variety

of external devices such as high-speed USB2.0 OTG, ATA, MMC/SDIO, and Compact Flash.

1.1

Features

The i.MX35 is designed for automotive infotainment video-enabled applications. It provides low-power

solutions for applications demanding high-performance multimedia and graphics.

The i.MX35 is based on the ARM1136 platform, which has the following features:

•

ARM1136JF-S processor, version r1p3

16-Kbyte L1 instruction cache

16-Kbyte L1 data cache

128-Kbyte L2 cache, version r0p4

128 Kbytes of internal SRAM

Vector floating point unit (VFP11)

To boost multimedia performance, the following hardware accelerators are integrated:

•

Image processing unit (IPU)

OpenVG 1.1 graphics processing unit (GPU) (not available for the MCIMX351)

The MCIMX35 provides the following interfaces to external devices (some of these interfaces are muxed

and not available simultaneously):

•

2 controller area network (CAN) interfaces

2 SDIO/MMC interfaces, 1 SDIO/CE-ATA interface (CE-ATA is not available for the MCIMX351)

32-bit mobile DDR, DDR2 (4-bank architecture), and SDRAM (up to 133 MHz)

2 configurable serial peripheral interfaces (CSPI) (up to 52 Mbps each)

Enhanced serial audio interface (ESAI)

2 synchronous serial interfaces (SSI)

Ethernet MAC 10/100 Mbps

1 USB 2.0 host with ULPI interface or internal full-speed PHY. Up to 480 Mbps if external HS

PHY is used.

•

1 USB 2.0 OTG (up to 480 Mbps) controller with internal high-speed OTG PHY

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•

Flash controller—MLC/SLC NAND and NOR

GPIO with interrupt capabilities

2

3 I C modules (up to 400 Kbytes each)

JTAG

Key pin port

Media local bus (MLB) interface

Asynchronous sample rate converter (ASRC)

1-Wire

Parallel camera sensor (4/8/10/16-bit data port for video color models: YCC, YUV, 30 Mpixels/s)

Parallel display (primary up to 24-bit, 1024 x 1024)

Parallel ATA (up to 66 Mbytes) (not available for the MCIMX351)

PWM

SPDIF transceiver

3 UART (up to 4.0 Mbps each)

1.2

Ordering Information

Table 1 provides the ordering information for the i.MX35 processors for automotive applications.

Table 1. Ordering Information

Operating

Temperature

Range (°C)

Signal Ball

Map

Locations

Silicon

Revision

Description

Part Number

Package¹

Speed

Ball Map

i.MX351

i.MX355

i.MX356

i.MX351

i.MX355

i.MX356

MCIMX351AVM4B

MCIMX351AVM5B

MCIMX355AVM4B

MCIMX355AVM5B

MCIMX356AVM4B

MCIMX356AVM5B

MCIMX351AJQ4C

MCIMX351AJQ5C

MCIMX355AJQ4C

MCIMX355AJQ5C

MCIMX356AJQ4C

MCIMX356AJQ5C

SCIMX356BVMB

2.0

2.1

2

5284

400 MHz

532 MHz²

400 MHz

532 MHz²

400 MHz

532 MHz²

400MHz

532MHz²

400MHz

532MHz²

400MHz

532MHz²

532MHz

–40 to 85

-40 to 85

Table 94

Table 95

Table 94

Table 96

Table 97

Table 96

1

2

Case 5284 is RoHS-compliant, lead-free, MSL = 3, 1.

532 MHz rated devices meet all specifications of 400 MHz rated devices. A 532 MHz device can be substituted in place of a

400 MHz device.

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The ball map for silicon revision 2.1 is different than the ballmap for silicon revision 2.0. The layout for

each revision is not compatible, so it is important that the correct ballmap be used to implement the layout.

See Section 5, “Package Information and Pinout.”

Table 2 shows the functional differences between the different parts in the i.MX35 family.

Table 2. Functional Differences in the i.MX35 Parts

Module

MCIMX351

MCIMX353

MCIMX355

MCIMX356

MCIMX357

I2C (3)

Yes

—

Yes

CSPI (2)

SSI/I2S (2)

ESAI

SPDIF I/O

USB HS Host

USB OTG

FlexCAN (2)

MLB

Ethernet

1-Wire

KPP

SDIO/MMC (2)

SDIO/Memory Stick

External Memory Controller (EMC)

JTAG

PATA

CE-ATA

—

Image Processing Unit (IPU) (inversion

and rotation, pre- and post-processing,

camera interface, blending, display

controller)

—

Open VG graphics acceleration (GPU)

—

Yes

—

Yes

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1.3

Block Diagram

Figure 1 is the i.MX35 simplified interface block diagram.

NOR

Flash/

PSRAM

External Graphics

Accelerator

LCD Display 1

LCD Display 2

DDR2/SDDR

RAM

NAND

Flash

Camera

Sensor

External Memory

Interface (EMI)

Image

Processing Unit

(IPU)

Smart

DMA

ARM11

Platform

ARM1136 Platform Peripherals

ARM1136JF-S

SSI

HS USBOTG

SPBA

VFP

L1 I/D cache

L2 cache

AVIC

HS USBOTGPHY

HS USBHost

FS USBPHY

AUDMUX

I2C(3)

UART(2)

CSPI

Peripherals

ESAI

GPU 2D

MSHC

MAX

SPDIF

SSI

AIPS (2)

ETM

eSDHC(3)

ASRC

CAN(2)

MLB

ECT

UART

CSPI

IOMUX

GPIO(3)

Internal

Memory

ATA

FEC

IIM

RTICv3

RNGC

SCC

EPIT

Timers

RTC

KPP

PWM

WDOG

GPT

OWIRE

3 FuseBox

Connectivity

Access

Audio/Power

Management

MMC/SDIO

or WLAN

Bluetooth

Keypad

JTAG

Figure 1. i.MX35 Simplified Interface Block Diagram

2 Functional Description and Application Information

The i.MX35 consists of the following major subsystems:

•

ARM1136 Platform—AP domain

SDMA Platform and EMI—Shared domain

2.1

Application Processor Domain Overview

The applications processor (AP) and its domain are responsible for running the operating system and

applications software, providing the user interface, and supplying access to integrated and external

peripherals. The AP domain is built around an ARM1136JF-S core with 16-Kbyte instruction and data L1

caches, an MMU, a 128-Kbyte L2 cache, a multiported crossbar switch, and advanced debug and trace

interfaces.

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The i.MX35 core is intended to operate at a maximum frequency of 532 MHz to support the required

multimedia use cases. Furthermore, an image processing unit (IPU) is integrated into the AP domain to

offload the ARM11 core from performing functions such as color space conversion, image rotation and

scaling, graphics overlay, and pre- and post-processing.

The functionality of AP Domain peripherals includes the user interface; the connectivity, display, security,

and memory interfaces; and 128 Kbytes of multipurpose SRAM.

2.2

Shared Domain Overview

The shared domain is composed of the shared peripherals, a smart DMA engine (SDMA) and a number of

miscellaneous modules. For maximum flexibility, some peripherals are directly accessible by the SDMA

engine.

The i.MX35 has a hierarchical memory architecture including L1 caches and a unified L2 cache. This

reduces the bandwidth demands for the external bus and external memory. The external memory

subsystem supports a flexible external memory system, including support for SDRAM (SDR, DDR2 and

mobile DDR) and NAND Flash.

2.3

Advanced Power Management Overview

To address the continuing need to reduce power consumption, the following techniques are incorporated

in the i.MX35:

•

Clock gating

Power gating

Power-optimized synthesis

Well biasing

The insertion of gating into the clock paths allows unused portions of the chip to be disabled. Because

static CMOS logic consumes only leakage power, significant power savings can be realized.

“Well biasing” is applying a voltage that is greater than V to the nwells, and one that is lower than V

DD

SS

to the pwells. The effect of applying this well back bias voltage reduces the subthreshold channel leakage.

For the 90-nm digital process, it is estimated that the subthreshold leakage is reduced by a factor of ten

over the nominal leakage. Additionally, the supply voltage for internal logic can be reduced from 1.4 V to

1.22 V.

2.4

ARM11 Microprocessor Core

The CPU of the i.MX35 is the ARM1136JF-S core, based on the ARM v6 architecture. This core supports

®

the ARM Thumb instruction sets, features Jazelle technology (which enables direct execution of Java

byte codes) and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit

registers.

The ARM1136JF-S processor core features are as follows:

™

•

Integer unit with integral EmbeddedICE logic

Eight-stage pipeline

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•

Branch prediction with return stack

Low-interrupt latency

Instruction and data memory management units (MMUs), managed using micro TLB structures

backed by a unified main TLB

•

Instruction and data L1 caches, including a non-blocking data cache with hit-under-miss

Virtually indexed/physically addressed L1 caches

64-bit interface to both L1 caches

Write buffer (bypassable)

™

High-speed Advanced Micro Bus Architecture (AMBA) L2 interface

Vector floating point co-processor (VFP) for 3D graphics and hardware acceleration of other

floating-point applications

™

•

ETM and JTAG-based debug support

Table 3 summarizes information about the i.MX35 core.

Table 3. i.MX35 Core

Core

Acronym

Core

Name

Integrated Memory

Features

Brief Description

ARM11 or

ARM1136

ARM1136 The ARM1136™ platform consists of the ARM1136JF-S core, the ETM

• 16-Kbyte

Platform

real-time debug modules, a 6 × 5 multi-layer AHB crossbar switch (MAX), and

instruction cache

• 16-Kbyte data

cache

• 128-Kbyte L2

cache

a vector floating processor (VFP).

The i.MX35 provides a high-performance ARM11 microprocessor core and

highly integrated system functions. The ARM Application Processor (AP) and

other subsystems address the needs of the personal, wireless, and portable

product market with integrated peripherals, advanced processor core, and

power management capabilities.

• 32-Kbyte ROM

• 128-Kbyte RAM

2.5

Module Inventory

Table 4 shows an alphabetical listing of the modules in the MCIMX35. For extended descriptions of the

modules, see the MCIMX35 reference manual.

Table 4. Digital and Analog Modules

Block

Mnemonic

Block Name

Domain¹

Subsystem

Brief Description

1-WIRE 1-Wire

interface

ARM

ARM1136

platform

1-Wire provides the communication line to a 1-Kbit add-only

memory. the interface can send or receive 1 bit at a time.

peripherals

ASRC

Asynchronous SDMA

sample rate

converter

Connectivity

peripherals

The ASRC is designed to convert the sampling rate of a signal

associated to an input clock into a signal associated to a different

output clock. It supports a concurrent sample rate conversion of

about –120 dB THD+N. The sample rate conversion of each

channel is associated to a pair of incoming and outgoing sampling

rates.

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Table 4. Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Domain¹

Subsystem

Brief Description

ATA

ATA module

SDMA

Connectivity

peripherals

The ATA block is an AT attachment host interface. Its main use is to

interface with IDE hard disk drives and ATAPI optical disk drives. It

interfaces with the ATA device over a number of ATA signals.

AUDMUX Digital audio

mux

ARM

Multimedia

peripherals

The AUDMUX is a programmable interconnect for voice, audio, and

synchronous data routing between host serial interfaces (SSIs) and

peripheral serial interfaces (audio codecs). The AUDMUX has two

sets of interfaces: internal ports to on-chip peripherals and external

ports to off-chip audio devices. Data is routed by configuring the

appropriate internal and external ports.

CAN(2)

CCM

CAN module

ARM

Connectivity

peripherals

The CAN protocol is primarily designed to be used as a vehicle

serial data bus running at 1 Mbps.

Clock control

module

Clocks

This block generates all clocks for the peripherals in the SDMA

platform. The CCM also manages ARM1136 platform low-power

modes (WAIT, STOP), disabling peripheral clocks appropriately for

power conservation, and provides alternate clock sources for the

ARM1136 and SDMA platforms.

CSPI(2) Configurable

serial

SDMA,

ARM

Connectivity

peripherals

This module is a serial interface equipped with data FIFOs; each

master/slave-configurable SPI module is capable of interfacing to

both serial port interface master and slave devices. The CSPI ready

(SPI_RDY) and slave select (SS) control signals enable fast data

communication with fewer software interrupts.

peripheral

interface

ECT

EMI

Embedded

cross trigger

SDMA,

ARM

Debug

ECT (embedded cross trigger) is an IP for real-time debug

purposes. It is a programmable matrix allowing several subsystems

to interact with each other. ECT receives signals required for

debugging purposes (from cores, peripherals, buses, external

inputs, and so on) and propagates them (propagation programmed

through software) to the different debug resources available within

the SoC.

External

memory

interface

SDMA

External

memory

interface

The EMI module provides access to external memory for the ARM

and other masters. It is composed of the following main

submodules:

M3IF—provides arbitration between multiple masters requesting

access to the external memory.

SDRAM CTRL—interfaces to mDDR, DDR2 (4-bank architecture

type), and SDR interfaces.

NANDFC—provides an interface to NAND Flash memories.

WEIM—interfaces to NOR Flash and PSRAM.

EPIT(2)

Enhanced

periodic

interrupt timer

ARM

Timer

peripherals

Each EPIT is a 32-bit “set-and-forget” timer that starts counting after

the EPIT is enabled by software. It is capable of providing precise

interrupts at regular intervals with minimal processor intervention. It

has a 12-bit prescaler to adjust the input clock frequency to the

required time setting for the interrupts, and the counter value can be

programmed on the fly.

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Table 4. Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Domain¹

Subsystem

Brief Description

ESAI

Enhanced

serial audio

interface

SDMA

ARM

Connectivity

peripherals

The enhanced serial audio interface (ESAI) provides a full-duplex

serial port for serial communication with a variety of serial devices,

including industry-standard codecs, SPDIF transceivers, and other

DSPs. The ESAI consists of independent transmitter and receiver

sections, each section with its own clock generator.

eSDHCv2 Enhanced

Connectivity

peripherals

The eSDHCv2 consists of four main modules: CE-ATA, MMC, SD

and SDIO. CE-ATA is a hard drive interface that is optimized for

embedded applications of storage. The MultiMediaCard (MMC) is a

universal, low-cost, data storage and communication media to

applications such as electronic toys, organizers, PDAs, and smart

phones. The secure digital (SD) card is an evolution of MMC and is

specifically designed to meet the security, capacity, performance,

and environment requirements inherent in emerging audio and

video consumer electronic devices. SD cards are categorized into

Memory and I/O. A memory card enables a copyright protection

mechanism that complies with the SDMI security standard. SDIO

cards provide high-speed data I/O (such as wireless LAN via SDIO

interface) with low power consumption.

(3)

secure digital

host controller

Note: CE-ATA is not available for the MCIMX351.

FEC

Ethernet

SDMA

Connectivity

peripherals

The Ethernet media access controller (MAC) is designed to support

both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external

transceiver interface and transceiver function are required to

complete the interface to the media

GPIO(3) General

purpose I/O

ARM

Pins

Used for general purpose input/output to external ICs. Each GPIO

module supports 32 bits of I/O.

modules

GPT

General

Timer

peripherals

Each GPT is a 32-bit free-running or set-and-forget mode timer with

a programmable prescaler and compare and capture registers. A

timer counter value can be captured using an external event and can

be configured to trigger a capture event on either the leading or

trailing edges of an input pulse. When the timer is configured to

operate in set-and-forget mode, it is capable of providing precise

interrupts at regular intervals with minimal processor intervention.

The counter has output compare logic to provide the status and

interrupt at comparison. This timer can be configured to run either

on an external clock or on an internal clock.

purpose timers

GPU2D

Graphics

processingunit

2Dv1

ARM

Multimedia

peripherals

This module accelerates OpenVG and GDI graphics.

Note: Not available for the MCIMX351.

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Table 4. Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Domain¹

Subsystem

Brief Description

I²C(3)

I²C module

ARM

ARM1136

platform

peripherals

Inter-integrated circuit (I²C) is an industry-standard, bidirectional

serial bus that provides a simple, efficient method of data exchange,

minimizing the interconnection between devices. I²C is suitable for

applications requiring occasional communications over a short

distance among many devices. The interface operates at up to

100 kbps with maximum bus loading and timing. The I²C system is

a true multiple-master bus, with arbitration and collision detection

that prevent data corruption if multiple devices attempt to control the

bus simultaneously. This feature supports complex applications with

multiprocessor control and can be used for rapid testing and

alignment of end products through external connections to an

assembly-line computer.

IIM

IC

ARM

Security

modules

The IIM provides the primary user-visible mechanism for interfacing

with on-chip fuse elements. Among the uses for the fuses are

unique chip identifiers, mask revision numbers, cryptographic keys,

and various control signals requiring a fixed value.

identification

module

IOMUX

External

signals and pin

multiplexing

Pins

Each I/O multiplexer provides a flexible, scalable multiplexing

solution with the following features:

• Up to eight output sources multiplexed per pin

• Up to four destinations for each input pin

• Unselected input paths held at constant levels for reduced power

consumption

IPUv1

Image

processing unit

ARM

Multimedia

peripherals

The IPU supports video and graphics processing functions. It also

provides the interface for image sensors and displays. The IPU

performs the following main functions:

• Preprocessing of data from the sensor or from the external

system memory

• Postprocessing of data from the external system memory

• Post-filtering of data from the system memory with support of the

MPEG-4 (both deblocking and deringing) and H.264 post-filtering

algorithms

• Displaying video and graphics on a synchronous (dumb or

memory-less) display

• Displaying video and graphics on an asynchronous (smart)

display

• Transferring data between IPU sub-modules and to/from the

system memory with flexible pixel reformatting

KPP

MLB

Keypin port

ARM

Connectivity

peripherals

Can be used for either keypin matrix scanning or general purpose

I/O.

Media local

bus

ARM

Connectivity

peripherals

The MLB is designed to interface to an automotive MOST ring.

OSCAUD OSC audio

reference

Analog

Clock

The OSCAUDIO oscillator provides a stable frequency reference for

the PLLs. This oscillator is designed to work in conjunction with an

external 24.576-MHz crystal.

oscillator

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Table 4. Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Domain¹

Subsystem

Brief Description

OSC24M OSC24M

24-MHz

Analog

SDMA

Clock

The signal from the external 24-MHz crystal is the source of the

CLK24M signal fed into USB PHY as the reference clock and to the

real time clock (RTC).

reference

oscillator

MPLL

PPLL

Digital

phase-locked

loops

Clocks

DPLLs are used to generate the clocks:

MCU PLL (MPLL)—programmable

Peripheral PLL (PPLL)—programmable

PWM

RTC

Pulse-width

modulator

ARM

ARM1136

platform

peripherals

The pulse-width modulator (PWM) is optimized to generate sound

from stored sample audio images; it can also generate tones.

Real-time

clock

ARM

Clocks

Provides the ARM1136 platform with a clock function (days, hours,

minutes, seconds) and includes alarm, sampling timer, and minute

stopwatch capabilities.

SDMA

Smart DMA

engine

SDMA

System

controls

The SDMA provides DMA capabilities inside the processor. It is a

shared module that implements 32 DMA channels and has an

interface to connect to the ARM1136 platform subsystem, EMI

interface, and the peripherals.

SJC

Secure JTAG

controller

ARM

Pins

The secure JTAG controller (SJC) provides debug and test control

with maximum security.

SPBA

SDMA

peripheral bus

arbiter

SDMA

System

controls

The SPBA controls access to the SDMA peripherals. It supports

shared peripheral ownership and access rights to an owned

peripheral.

S/PDIF

SSI(2)

Serial audio

interface

SDMA

SDMA,

Connectivity

peripherals

Sony/Philips digital transceiver interface

Synchronous

serial interface ARM(2)

Connectivity

peripherals

The SSI is a full-duplex serial port that allows the processor

connected to it to communicate with a variety of serial protocols,

including the Freescale Semiconductor SPI standard and the I²C

sound (I²S) bus standard. The SSIs interface to the AUDMUX for

flexible audio routing.

UART(3) Universal

ARM

Connectivity

Each UART provides serial communication capability with external

devices through an RS-232 cable using the standard RS-232

non-return-to-zero (NRZ) encoding format. Each module transmits

and receives characters containing either 7 or 8 bits

(program-selectable). Each UART can also provide low-speed IrDA

compatibility through the use of external circuitry that converts

infrared signals to electrical signals (for reception) or transforms

electrical signals to signals that drive an infrared LED (for

transmission).

asynchronous (UART1,2) peripherals

receiver/trans

mitters

SDMA

(UART3)

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Table 4. Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Domain¹

Subsystem

Brief Description

USBOH High-speed

USB on-the-go

SDMA

ARM

Connectivity

peripherals

The USB module provides high performance USB on-the-go (OTG)

functionality (up to 480 Mbps), compliant with the USB 2.0

specification, the OTG supplement, and the ULPI 1.0 low pin count

specification. The module has DMA capabilities handling data

transfer between internal buffers and system memory.

WDOG

Watchdog

modules

Timer

peripherals

Each module protects against system failures by providing a method

of escaping from unexpected events or programming errors. Once

activated, the timer must be serviced by software on a periodic

basis. If servicing does not take place, the watchdog times out and

then either asserts a system reset signal or an interrupt request

signal, depending on the software configuration.

1

ARM = ARM1136 platform, SDMA = SDMA platform

3 Signal Descriptions: Special Function Related Pins

Some special functional requirements are supported in the device. The details about these special functions

and the corresponding pin names are listed in Table 5.

Table 5. Special Function Related Pins

Function Name

Pin Name

Mux Mode

Detailed Description

External ARM Clock

EXT_ARMCLK

I2C1_CLK

ALT0

ALT6

ALT4

ALT2

External clock input for ARM clock.

External peripheral clock source.

External Peripheral Clock

External 32-kHz Clock

CAPTURE

External clock input of 32 kHz, used when the internal

24M Oscillator is powered off, which could be

configured either from CAPTURE or CSPI1_SS1.

CSPI1_SS1

Clock Out

CLKO

ALT0

Clock-out pin from CCM, clock source is controllable

and can also be used for debug.

Power Ready

GPIO1_0

TX1

ALT1

ALT6

PMIC power-ready signal, which can be configured

either from GPIO1_0 or TX1.

Tamper Detect

GPIO1_1

Tamper-detect logic is used to issue a security

violation. This logic is activated if the tamper-detect

input is asserted. Tamper-detect logic is enabled by the

bit of IOMUXC_GPRA[2]. After enabling the logic, it is

impossible to disable it until the next reset.

i.MX35 Applications Processors for Automotive Products, Rev. 10

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4 Electrical Characteristics

The following sections provide the device-level and module-level electrical characteristics for the i.MX35

processor.

4.1

i.MX35 Chip-Level Conditions

This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference

to the individual tables and sections.

Table 6. i.MX35 Chip-Level Conditions

Characteristics

Table/Location

Absolute Maximum Ratings

i.MX35 Operating Ranges

Interface Frequency

Table 7 on page 13

Table 8 on page 14

Table 9 on page 15

CAUTION

Stresses beyond those listed in Table 7 may cause permanent damage to the

device. These are stress ratings only. Functional operation of the device at

these or any other conditions beyond those indicated in Table 8 is not

implied. Exposure to absolute-maximum-rated conditions for extended

periods may affect device reliability.

Table 7. Absolute Maximum Ratings

Parameter

Symbol

Min.

Max.

Units

1

Supply voltage (core)

Supply voltage (I/O)

Input voltage range

Storage temperature

ESD damage immunity:

VDD_max

NVCC_max

V_Imax

–0.5

–40

1.47

3.6

V

3.6

V

T_storage

V_esd

125

^oC

V

Human Body Model (HBM)

Charge Device Model (CDM)

—

2000²

500³

1

VDD is also known as QVCC.

2

3

HBM ESD classification level according to the AEC-Q100-002 standard

Corner pins max. 750 V

i.MX35 Applications Processors for Automotive Products, Rev. 10

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13

4.1.1

i.MX35 Operating Ranges

Table 8 provides the recommended operating ranges. The term NVCC in this section refers to the

associated supply rail of an input or output.

Table 8. i.MX35 Operating Ranges

Parameter

Symbol

Min.

Typical

Max.

Units

Core Operating Voltage

0 < fARM < 400 MHz

V_DD

1.22

—

1.47

V

Core Operating Voltage

0 < fARM < 532 MHz

1.33

—

1.47

V

State Retention Voltage

EMI¹

1

—

3.6

3.43

3.6

1.65

3.6

85

V

^oC

NVCC_EMI1,2,3

NVCC_CRM

NVCC_NANDF

NVCC_ATA

1.7

WTDG, Timer, CCM, CSPI1

NANDF

1.75

3.17

—

ATA, USB generic

eSDHC1

—

NVCC_SDIO

NVCC_CSI

—

CSI, SDIO2

—

JTAG

NVCC_JTAG

NVCC_LCDC

NVCC_MISC

NVCC_MLB²

PHY1_VDDA

—

LCDC, TTM, I2C1

I2Sx2,ESAI, I2C2, UART2, UART1, FEC

MLB

—

USB OTG PHY

USB HOST PHY

OSC24M

3.3

—

USBPHY1_VDDA_BIAS 3.17

USBPHY1_UPLLVDD

PHY2_VDD

OSC24M_VDD

OSC_AUDIO_VDD

MVDD

3.17

3.0

1.4

3.0

–40

OSC_AUDIO

MPLL

PPLL

PVDD

—

Fusebox program supply voltage

Operating ambient temperature range

Junction temperature range

FUSE_VDD³

3.6

—

TA

TJ

—

105

1

2

3

EMI I/O interface power supply should be set up according to external memory. For example, if using SDRAM then

NVCC_EMI1,2,3 should all be set at 3.3 V (typ.). If using MDDR or DDR2, NVC_EMI1,2,3 must be set at 1.8 V (typ.).

MLB interface I/O pads can be programmed to function as GPIO by setting NVCC_MLB to 1.8 or 3.3 V, but if used as MLB

pads, NVCC_MLB must be set to 2.5 V in order to be compliant with external MOST devices. NVCC_MLB may be left floating.

The Fusebox read supply is connected to supply of the full speed USB PHY. FUSE_VDD is only used for programming. It is

recommended that FUSE_VDD be connected to ground when not being used for programming. FUSE_VDD should be

supplied by following the power up sequence given in Section 4.3.1, “Powering Up.”

i.MX35 Applications Processors for Automotive Products, Rev. 10

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4.1.2

Interface Frequency Limits

Table 9 provides information on interface frequency limits.

Table 9. Interface Frequency

ID

Parameter

JTAG TCK Frequency

Symbol

f_JTAG

Min.

DC

Typ.

Max.

Units

1

5

10

MHz

4.2

Power Modes

Table 10 provides descriptions of the power modes of the i.MX35 processor.

Table 10. i.MX35 Power Modes

QVCC (ARM/L2

Peripheral)

OSC24M_VDD

OSC_AUDO_VDD

MVDD/PVDD

Power

Mode

Description

Typ.

Max.

Typ.

Max.

Typ.

Max.

Wait

VDD1,2,3,4 = 1.1 V (min.)

ARM is in wait for interrupt mode.

MAX is active.

L2 cache is kept powered.

MCU PLL is on (400 MHz)

PER PLL is off (can be configured)

(default: 300 MHz)

16 mA

170 mA

7.2 mA

14 mA

1.2 mA

3 mA

Module clocks are gated off (can be

configured by CGR register).

OSC 24M is ON.

OSC audio is off (can be configured).

RNGC internal osc is off.

Doze

VDD1,2,3,4 = 1.1 V (min.)

ARM is in wait for interrupt mode.

MAX is halted.

L2 cache is kept powered.

L2 cache control logic off.

AWB enabled.

MCU PLL is on(400 MHz)

12.4 mA 105 mA

7.2 mA

14 mA

1.2 mA

3 mA

PER PLL is off (can be configured).

(300 Mhz).

Module clocks are gated off (can be

configured by CGR register).

OSC 24M is ON.

OSC audio is off (can be configured)

RNGC internal osc is off

i.MX35 Applications Processors for Automotive Products, Rev. 10

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15

Table 10. i.MX35 Power Modes (continued)

QVCC (ARM/L2

OSC24M_VDD

OSC_AUDO_VDD

MVDD/PVDD

Power

Mode

Peripheral)

Description

Typ.

Max.

Typ.

Max.

Typ.

Max.

Stop

VDD1,2,3,4 = 1.1 V (min.)

ARM is in wait for interrupt mode.

MAX is halted

L2 cache is kept powered.

L2 cache control logic off.

AWB enabled.

1.1 mA

77 mA

400 µA

2.2 mA

1.2 mA

2.2 mA

MCU PLL is off.

PER PLL is off.

All clocks are gated off.

OSC 24 MHz is on

OSC audio is off

RNGC internal osc is off

Static

VDD1,2,3,4 = 1.1 V (min.)

ARM is in wait for interrupt mode.

MAX is halted

L2 cache is kept powered.

L2 cache control logic off.

AWB enabled.

820 µA

72 mA

50 µA

1.7 mA

24 µA

35 µA

MCU PLL is off.

PER PLL is off.

All clocks are gated off.

OSC 24MHz is on

OSC audio is off

RNGC internal osc is off

Note: Typical column: TA = 25 °C

Note: Maximum column: TA = 85 °C

4.3

Supply Power-Up/Power-Down Requirements and Restrictions

This section provides power-up and power-down sequence guidelines for the i.MX35 processor.

CAUTION

Any i.MX35 board design must comply with the power-up and power-down

sequence guidelines as described in this section to guarantee reliable

operation of the device. Any deviation from these sequences can result in

irreversible damage to the i.MX35 processor (worst-case scenario).

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NOTE

Deviation from these sequences may also result in one or more of the

following:

•

Excessive current during power-up phase

Prevent the device from booting

Programming of unprogrammed fuses

4.3.1

Powering Up

The power-up sequence should be completed as follows:

1. Assert Power on Reset (POR).

2. Turn on digital logic domain and IO power supply: VDDn, NVCCx

3. Wait until VDDn and NVCCx power supplies are stable + 32 μs.

4. Turn on all other power supplies: PHY1_VDDA, USBPHY1_VDDA_BIAS, PHY2_VDD,

USBPHY1_UPLLVDD, OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD, FUSEVDD.

(Always FUSE_VDD should be connected to ground, except when eFuses are to be

programmed.)

5. Wait until PHY1_VDDA, USBPHY1_VDDA_BIAS, PHY2_VDD, USBPHY1_UPLLVDD,

OSC24M_VDD, OSC_AUDIO_VDD, MVDD, PVDD, (FUSEVDD, optional). Power supplies

are stable + 100 μs.

6. Deassert the POR signal.

i.MX35 Applications Processors for Automotive Products, Rev. 10

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17

Figure 2 shows the power-up sequence and timing.

Figure 2. i.MX35 Power-Up Sequence and Timing

4.3.2

Powering Down

The power-up sequence in reverse order is recommended for powering down. However, all power supplies

can be shut down at the same time.

4.4

Reset Timing

There are two ways of resetting the i.MX35 using external pins:

•

Power On Reset (using the POR_B pin)

System Reset (using the RESET_IN_B pin)

4.4.1

Power On Reset

POR_B is normally connected to a power management integrated circuit (PMIC). The PMIC asserts

POR_B while the power supplies are turned on and negates POR_B after the power up sequence is

finished. See Figure 2.

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Assuming the i.MX35 chip is already fully powered; it is still possible to reset all of the modules to their

default reset by asserting POR_B for at least 4 CKIL cycles and later de-asserting POR_B. This method

of resetting the i.MX35 can also be supported by tying the POR_B and RESET_IN_B pins together.

POR_B

At least 4 CKIL cycles

CKIL

Figure 3. Timing Between POR_B and CKIL for Complete Reset of i.MX35

4.4.2

System Reset

System reset can be achieved by asserting RESET_IN_B for at least 4 CKIL cycles and later negating

RESET_IN_B. The following modules are not reset upon system reset: RTC, PLLs, CCM, and IIM.

POR_B pin must be deasserted all the time.

RESET_IN_B

At least 4 CKIL cycles

CKIL

Figure 4. Timing Between RESET_IN_B and CKIL for i.MX35 System Reboot

4.5

Power Characteristics

The table shows values representing maximum current numbers for the i.MX35 under worst case voltage

and temperature conditions. These values are derived from the i.MX35 with core clock speeds up to

532 MHz. Common supplies have been bundled according to the i.MX35 power-up sequence

requirements. Peak numbers are provided for system designers so that the i.MX35 power supply

requirements will be satisfied during startup and transient conditions. Freescale recommends that system

current measurements be taken with customer-specific use-cases to reflect normal operating conditions in

the end system.

i.MX35 Applications Processors for Automotive Products, Rev. 10

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19

Table 11. Power Consumption

Power Supply

Voltage (V)

Max Current (mA)

QVCC

1.47

1.65

1.9

400

20

MVDD, PVDD

NVCC_EMI1, NVCC_EMI2, NVCC_EMI3, NVCC_LCDC, NVCC_NFC

FUSE_VDD¹

90

62

3.6

NVCC_MISC, NVCC_CSI, NVCC_SDIO, NVCC_CRM, NVCC_ATA, NVCC_MLB,

NVCC_JTAG

3.6

60

OSC24M_VDD, OSC_AUDIO_VDD, PHY1_VDDA, PHY2_VDD,

USBPHY1_UPLLVDD, USBPHY1_VDDA_BIAS

3.6

25

1

This rail is connected to ground; it only needs a voltage if eFuses are to be programmed. FUSE_VDD should be supplied by

following the power up sequence given in Section 4.3.1, “Powering Up.”

The method for obtaining max current is as follows:

1. Measure worst case power consumption on individual rails using directed test on i.MX35.

2. Correlate worst case power consumption power measurements with worst case power

consumption simulations.

3. Combine common voltage rails based on power supply sequencing requirements

4. Guard band worst case numbers for temperature and process variation. Guard band is based on

process data and correlated with actual data measured on i.MX35.

5. The sum of individual rails is greater than real world power consumption, as a real system does

not typically maximize power consumption on all peripherals simultaneously.

4.6

Thermal Characteristics

The thermal resistance characteristics for the device are given in Table 12. These values were measured

under the following conditions:

•

Two-layer substrate

Substrate solder mask thickness: 0.025 mm

Substrate metal thicknesses: 0.016 mm

Substrate core thickness: 0.200 mm

Core via I.D: 0.168 mm, Core via plating 0.016 mm.

Full array map design, but nearly all balls under die are power or ground.

Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K

Mold compound: k = 0.9 W/m K

Table 12. Thermal Resistance Data

Rating

Condition

Symbol

Value

Unit

Junction to ambient¹natural convection

Single layer board (1s)

Four layer board (2s2p)

R_eJA

53

30

ºC/W

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Table 12. Thermal Resistance Data (continued)

Condition

Rating

Symbol

Value

Unit

Junction to ambient¹(at 200 ft/min)

Junction to boards²

Single layer board (1s)

R_eJMA

R_eJB

44

27

19

10

2

ºC/W

Four layer board (2s2p)

—

Junction to case (top)³

R_eJCtop

Ψ_JT

Junction to package top⁴

Natural convection

1

2

3

4

Junction-to-ambient thermal resistance determined per JEDC JESD51-3 and JESD51-6. Thermal test board meets JEDEC

specification for this package.

Junction-to-board thermal resistance determined per JEDC JESD51-8. Thermal test board meets JEDEC specification for this

package.

Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used

for the case temperature. Reported value includes the thermal resistance of the interface layer.

Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, this thermal characterization parameter is written

as Psi-JT.

4.7

I/O Pin DC Electrical Characteristics

I/O pins are of two types: GPIO and DDR. DDR pins can be configured in three different drive strength

modes: mobile DDR, SDRAM, and DDR2. The SDRAM and mobile DDR modes can be further

customized at three drive strength levels: normal, high, and max.

Table 13 shows currents for the different DDR pin drive strength modes.

Table 13. DDR Pin Drive Strength Mode Current Levels

Drive Mode

Normal

High

Max.

Mobile DDR (1.8 V)

SDRAM (1.8 V)

SDRAM (3.3 V)

DDR2 (1.8 V)

3.6 mA

—

7.2 mA

—

10.8 mA

6.5 mA

12 mA

4 mA

—

8 mA

—

13.4 mA

i.MX35 Applications Processors for Automotive Products, Rev. 10

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21

Table 14 shows the DC electrical characteristics for GPIO, DDR2, mobile DDR, and SDRAM pins. The

term NVCC refers to the power supply voltage that feeds the I/O of the module in question. For example,

NVCC for the SD/MMC interface refers to NVCC_SDIO.

Table 14. I/O Pin DC Electrical Characteristics

DC Electrical Characteristics Symbol

Test Condition

Min.

Typ.

Max.

Unit

GPIO High-level output voltage

Low-level output voltage

Voh

Vol

Ioh

Ioh = –1 mA

Ioh = specified drive

NVCC – 0.15

0.8 × NVCC

—

V

Iol = 1 mA

Iol = specified drive

—

0.15

0.2 × NVCC

V

High-level output current for

slow mode

(Voh = 0.8 × NVCC)

Standard drive

High drive

Max. drive

–2.0

–4.0

–8.0

—

mA

High-level output current

for fast mode

(Voh = 0.8 × NVCC)

Ioh

Iol

Standard drive

High drive

Max. drive

–4.0

–6.0

–8.0

—

mA

V

Low-level output current

for slow mode

(Voh = 0.2 × NVCC)

Standard drive

High drive

Max. drive

2.0

4.0

8.0

—

Low-level output current

for fast mode

(Voh = 0.2 × NVCC)

Iol

Standard drive

High drive

Max. drive

4.0

6.0

8.0

—

High-level DC Input

Voltage with 1.8 V,

3.3 V NVCC (for digital

cells in input mode)

VIH

—

0.7 × NVCC

NVCC

Low-level DC Input

Voltage with 1.8 V,

3.3 V NVCC (for digital

cells in input mode

VIL

—

–0.3 V

—

0.3 × NVCC

V

Input Hysteresis

VHYS

OVDD = 3.3 V

OVDD = 1.8 V

410

330

—

mV

Schmitt trigger VT+

Schmitt trigger VT–

VT+

VT–

Rpu

—

0.5 × NVCC

—

22

V

—

0.5 × NVCC

Pull-up resistor

Vi = 0

—

kΩ

(22 kΩ PU)

Pull-up resistor

(47 kΩ PU)

Rpu

Vi = 0

—

47

—

kΩ

Pull-up resistor

100

(100 kΩ PU)

Pull-down resistor (100 kΩ PD)

Rpd

Vi = NVCC

—

100

—

kΩ

External resistance to pull

keeper up when enabled

Rkpu

Ipu > 620 μA

@ min Vddio = 3.0 V

4.8

External resistance to pull

keeper down when enabled

Rkpd

Ipu > 510 μA

@min Vddio = 3.0 V

—

5.9

kΩ

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Table 14. I/O Pin DC Electrical Characteristics (continued)

DC Electrical Characteristics Symbol

Test Condition

Min.

Typ.

Max.

Unit

DDR2 High-level output voltage

Low-level output voltage

Output min. source current

Output min. sink current

DC input logic high

Voh

Vol

—

NVCC – 0.28

—

V

0.28

Ioh

–13.4

13.4

—

mA

V

Iol

VIH(dc)

NVCC ÷ 2 +

NVCC + 0.3

0.125

DC input logic low

VIL(dc)

Vin(dc)

—

–0.3 V

–0.3

—

NVCC ÷ 2 –

V

0.125

DC input signal voltage

(for differential signal)

NVCC + 0.3

NVCC + 0.6

DC differential input voltage

Termination voltage

Vid(dc)

Vtt

—

0.25

V

NVCC ÷ 2 – NV NVCC ÷ 2 +

0.04

—

CC

÷ 2

0.04

Input current (no

pull-up/down)

IIN

—

1

μA

V

Tri-state I/O supply current

Icc – N

VCC

—

1

Mobile High-level output voltage

DDR

—

IOH = –1mA

IOH = specified drive

NVCC – 0.08

0.8 × NVCC

—

Low-level output voltage

IOL = 1mA

IOL = specified drive

—

0.08

0.2 × NVCC

V

High-level output current

(Voh = 0.8 × NVCCV)

Standard drive

High drive

–3.6

–7.2

—

mA

Max. drive

–10.8

Low-level output current

(Vol = 0.2 × NVCCV)

—

Standard Drive

High Drive

3.6

7.2

—

mA

Max. Drive

10.8

High-Level DC CMOS

input voltage

VIH

VIL

—

0.7 × NVCC

—

NVCC + 0.3

0.2 × NVCC

100

V

Low-Level DC CMOS

input voltage

–0.3

Differential receiver VTH+

Differential receiver VTH–

VTH+

VTH–

IIN

—

–100

—

mV

μA

Input current (no

pull-up/down)

VI = 0

VI = NVCC

1

Tri-state I/O supply current

Icc – N

VCC

VI = NVCC or 0

—

μA

i.MX35 Applications Processors for Automotive Products, Rev. 10

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23

Table 14. I/O Pin DC Electrical Characteristics (continued)

DC Electrical Characteristics Symbol

Test Condition

Min.

Typ.

Max.

Unit

SDR High-level output voltage

Voh

Vol

Ioh

Iol

loh = 5.7 mA

Max. drive

—

OVDD – 0.28

—

0.4

—

V

(1.8 V)

Low-level output voltage

—

5.7

7.3

1.4

–0.3

—

High-level output current

Low-level output current

High-level DC Input Voltage

Low-level DC Input Voltage

mA

V

—

VIH

VIL

IIN

1.98

0.8

—

V

Input current (no

pull-up/down)

VI = 0

VI=NVCC

150

80

μA

Tri-state I/O supply current

Icc

(NVCC)

VI = OVDD or 0

VI = VDD or 0

—

1180

1220

—

μA

V

Tri-state core supply current

Icc

(NVCC)

SDR High-level output voltage

(3.3 V)

Voh

Ioh=specified drive

(Ioh = –4, –8, –12,

–16 mA)

2.4

Low-level output voltage

High-level output current

Vol

Ioh

Ioh=specified drive (Ioh = 4,

8, 12, 16 mA)

—

0.4

—

V

Standard drive

High drive

–4.0

–8.0

mA

Max. drive

–12.0

Low-level output current

Iol

Standard drive

High drive

4.0

8.0

—

mA

Max. drive

12.0

High-level DC Input Voltage

Low-level DC Input Voltage

VIH

VIL

IIN

—

2.0

–0.3V

—

3.6

0.8

1

V

Input current (no

pull-up/down)

VI = 0

μA

VI = NVCC

Tri-state I/O supply current

Icc

VI = NVCC or 0

—

1

μA

(NVCC)

4.8

I/O Pin AC Electrical Characteristics

Figure 5 shows the load circuit for output pins.

From Output

Under Test

Test Point

CL

CL includes package, probe and jig capacitance

Figure 5. Load Circuit for Output Pin

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Freescale Semiconductor

Figure 6 shows the output pin transition time waveform.

NVCC

0V

80%

20%

80%

20%

Output (at pin)

PA1

Figure 6. Output Pin Transition Time Waveform

4.8.1

AC Electrical Test Parameter Definitions

AC electrical characteristics in Table 16 through Table 21 are not applicable for the output open drain

pull-down driver.

The dI/dt parameters are measured with the following methodology:

•

The zero voltage source is connected between pin and load capacitance.

The current (through this source) derivative is calculated during output transitions.

Table 15. AC Requirements of I/O Pins

Parameter

Symbol

VIH(ac)

VIL(ac)

Min.

NVCC ÷ 2 + 0.25

–0.3

Max.

Units

AC input logic high

AC input logic low

NVCC + 0.3

V

NVCC ÷ 2 – 0.25

V

Table 16. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode

[NVCC = 3.0 V–3.6 V]

Test

Condition

Min.

Rise/Fall

Max.

Rise/Fall

Parameter

Symbol

Typ. Rise/Fall

Units

Duty cycle

Fduty

tps

—

40

—

60

%

Output pin slew rate (max. drive)

25 pF

50 pF

0.79/1.12

0.49/0.73

1.30/1.77

0.84/1.23

2.02/2.58

1.19/1.58

V/ns

Output pin slew rate (high drive)

tps

tdit

25 pF

50 pF

0.48/0.72

0.27/0.42

0.76/1.10

0.41/0.62

1.17/1.56

0.63/0.86

V/ns

Output pin slew rate (standard

drive)

25 pF

50 pF

0.25/0.40

0.14/0.21

0.40/0.59

0.21/0.32

0.60/0.83

0.32/0.44

Output pin di/dt (max. drive)

25 pF

50 pF

15

16

36

38

76

80

mA/ns

Output pin di/dt (high drive)

25 pF

50 pF

8

9

20

21

45

47

Output pin di/dt (standard

drive)

25 pF

50 pF

4

10

22

23

i.MX35 Applications Processors for Automotive Products, Rev. 10

Freescale Semiconductor

25

Table 17. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode

[NVCC = 1.65 V–1.95 V]

Min.

Rise/Fall

Max.

Rise/Fall

Parameter

Symbol Test Condition

Typ.

Units

Duty cycle

Fduty

tps

—

40

—

60

%

Output pin slew rate (max. drive)

Output pin slew rate (high drive)

Output pin slew rate (standard drive)

Output pin di/dt (max. drive)

25 pF

50 pF

0.30/0.42

0.20/0.29

0.54/0.73

0.35/0.50

0.91/1.20

0.60/0.80

V/ns

tps

tdit

25 pF

50 pF

0.19/0.28

0.12/0.18

0.34/0.49

0.58/0/79

0.36/0.49

V/ns

25 pF

50 pF

0.12/0.18

0.07/0.11

0.20/0.30

0.11/0.17

0.34/0.47

0.20/0.27

25 pF

50 pF

7

21

22

56

58

mA/ns

Output pin di/dt (high drive)

25 pF

50 pF

5

14

15

38

40

Output pin di/dt (standard

drive)

25 pF

50 pF

2

7

18

19

Table 18. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode for

[NVCC = 3.0 V–3.6 V]

Min.

rise/fall

Max.

Rise/Fall

Parameter

Symbol Test Condition

Typ.

Units

Duty cycle

Fduty

tps

—

40

—

60

%

Output pin slew rate (max. drive)

Output pin slew rate (high drive)

Output pin slew rate (standard drive)

Output pin di/dt (max. drive)

25 pF

50 pF

0.96/1.40

0.54/0.83

1.54/2.10

0.85/1.24

2.30/3.00

1.26/1.70

V/ns

tps

tdit

25 pF

50 pF

0.76/1.10

0.41/0.64

1.19/1.71

0.63/0.95

1.78/2.39

0.95/1.30

V/ns

25 pF

50 pF

0.52/0.78

0.28/0.44

0.80/1.19

0.43/0.64

1.20/1.60

0.63/0.87

25 pF

50 pF

46

49

108

113

250

262

mA/ns

Output pin di/dt (high drive)

25 pF

50 pF

35

37

82

86

197

207

Output pin di/dt (standard

drive)

25 pF

50 pF

22

23

52

55

116

121

i.MX35 Applications Processors for Automotive Products, Rev. 10

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Freescale Semiconductor

Table 19. AC Electrical Characteristics, GPIO Pins in Fast Slew Rate Mode

[NVCC = 1.65 V–1.95 V]

Min.

Rise/Fall

Max.

Rise/Fall

Parameter

Symbol Test Condition

Typ.

Units

Duty cycle

Fduty

tps

—

40

—

60

%

Output pin slew rate (max. drive)

Output pin slew rate (high drive)

Output pin slew rate (standard drive)

Output pin di/dt (max. drive)

25 pF

50 pF

0.40/0.57

0.25/0.36

0.72/0.97

0.43/0.61

1.2/1.5

0.72/0.95

V/ns

tps

tdit

25 pF

50 pF

0.38/0.48

0.20/0.30

0.59/0.81

0.34/0.50

0.98/1.27

0.56/0.72

V/ns

25 pF

50 pF

0.23/0.32

0.13/0.20

0.40/0.55

0.23/0.34

0.66/0.87

0.38/0.52

25 pF

50 pF

7

43

46

112

118

mA/ns

Output pin di/dt (high drive)

25 pF

50 pF

11

12

31

33

81

85

Output pin di/dt (standard

drive)

25 pF

50 pF

9

10

27

28

71

74

Table 20. AC Electrical Characteristics of GPIO Pins in Slow Slew Rate Mode

[NVCC = 2.25 V–2.75 V]

Min.

Rise/Fall

Max.

Rise/Fall

Parameter

Symbol Test Condition

Typ.

Units

Duty cycle

Fduty

tps

—

40

—

60

%

Output pin slew rate (max. drive)

Output pin slew rate (high drive)

Output pin slew rate (standard drive)

25 pF

40 pF

50 pF

0.63/0.85

0.52/0.67

0.41/0.59

1.10/1.40

0.90/1.10

0.73/0.99

1.86/2.20

1.53/1.73

1.20/1.50

V/ns

tps

25 pF

40 pF

50 pF

0.40/0.58

0.33/0.43

0.25/0.37

0.71/0.98

0.56/0.70

0.43/0.60

1.16/1.40

0.93/1.07

0.68/0.90

V/ns

25 pF

40 pF

50 pF

0.24/0.36

0.19/0.25

0.13/0.21

0.41/0.59

0.32/0.35

0.23/0.33

0.66/0.87

0.51/0.59

0.36/0.48

Output pin di/dt (max. drive)

Output pin di/dt (high drive)

tdit

25 pF

50 pF

22

23

62

65

148

151

mA/ns

25 pF

50 pF

15

16

42

44

102

107

Output pin di/dt (standard

drive)

25 pF

50 pF

7

8

21

22

52

54

i.MX35 Applications Processors for Automotive Products, Rev. 10

Freescale Semiconductor

27

Table 21. AC Electrical Characteristics of GPIO Pins in Fast Slew Rate Mode

[NVCC = 2.25 V–2.75 V]

Test

Min.

Max.

Rise/Fall

Parameter

Symbol

Typ.

Units Notes

Condition Rise/Fall

Duty cycle

Fduty

tps

—

40

—

60

%

—

2

Output pin slew rate (max. drive)

Output pin slew rate (high drive)

Output pin slew rate (standard drive)

25 pF

40 pF

50 pF

0.84/1.10 1.45/1.80 2.40/2.80 V/ns

0.68/0.83 1.14/1.34 1.88/2.06

0.58/0.72 0.86/1.10 1.40/1.70

tps

25 pF

40 pF

50 pF

0.69/0.96 1.18/1.50 1.90/2.30 V/ns

0.55/0.69 0.92/1.10 1.49/1.67

0.40/0.59 0.67/0.95 1.10/1.30

25 pF

40 pF

50 pF

0.24/0.36 0.80/1.00 1.30/1.60 V/ns

0.37/0.47 0.62/0.76 1.00/1.14

0.13/0.21 0.45/0.65 0.70/0.95

Output pin di/dt (max. drive)

Output pin di/dt (high drive)

tdit

25 pF

50 pF

46

49

124

131

310

324

mA/ns

3

25 pF

50 pF

33

35

89

94

290

304

Output pin di/dt (standard

drive)

25 pF

50 pF

28

29

75

79

188

198

4.8.2

AC Electrical Characteristics for DDR Pins (DDR2, Mobile DDR, and

SDRAM Modes)

Table 22. AC Electrical Characteristics of DDR Type IO Pins in DDR2 Mode

Min.

Rise/Fall

Max.

Rise/Fall

Parameter

Symbol

Test Condition

Typ.

Units

Duty cycle

Fduty

—

45

—

50

55

—

%

Clock frequency

f

133

MHz

V/ns

Output pin slew rate

tps

25 pF

50 pF

0.86/0.98

0.46/054

1.35/1.5

0.72/0.81

2.15/2.19

1.12/1.16

Output pin di/dt

tdit

25 pF

50 pF

65

70

157

167

373

396

mA/ns

Table 23. AC Requirements of DDR2 Pins

Parameter¹

Symbol

VIH(ac)

VIL(ac)

Vox(ac)

Min.

Max.

Units

AC input logic high

AC input logic low

NVCC ÷ 2 + 0.25

–0.3

NVCC + 0.3

V

NVCC ÷ 2 – 0.25

NVCC ÷ 2 + 0.125

AC differential cross point voltage for output²

NVCC ÷ 2 – 0.125

1

The Jedec SSTL_18 specification (JESD8-15a) for an SSTL interface for class II operation supersedes any specification in this

document.

i.MX35 Applications Processors for Automotive Products, Rev. 10

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Freescale Semiconductor

2

The typical value of Vox(ac) is expected to be about 0.5 × NVCC and Vox(ac) is expected to track variation in NVCC. Vox(ac)

indicates the voltage at which the differential output signal must cross. Cload = 25 pF.

Table 24. AC Electrical Characteristics of DDR Type IO Pins in mDDR Mode

Min.

Rise/Fall

Max.

Rise/Fall

Parameter

Symbol

Test Condition

Typ.

Units

Duty cycle

Fduty

—

45

—

50

55

—

%

Clock frequency

f

133

MHz

V/ns

Output pin slew rate (max. drive)

tps

25 pF

50 pF

0.80/0.92

0.43/0.50

1.35/1.50

0.72/0.81

2.23/2.27

1.66/1.68

Output pin slew rate (high drive)

Output pin slew rate (standard drive)

Output pin di/dt (max. drive)

tps

tdit

25 pF

50 pF

0.37/0.43

0.19/0.23

0.62/0.70

0.33/0.37

1.03/1.05

0.75/0.77

V/ns

25 pF

50 pF

0.18/0.22

0.10/0.12

0.31/0.35

0.16/0.18

0.51/0.53

0.38/0.39

25 pF

50 pF

64

69

171

183

407

432

mA/ns

Output pin di/dt (high drive)

25 pF

50 pF

37

39

100

106

232

246

Output pin di/dt (standard drive)

25 pF

50 pF

18

20

50

52

116

123

Table 25. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode

Min.

Rise/Fall

Min. Clock

Frequency

Max.

Rise/Fall

Parameter

Clock frequency

Symbol

Test Condition

Units

f

—

125

—

MHz

V/ns

Output pin slew rate (max. drive)

Output pin slew rate (high drive)

Output pin slew rate (standard drive)

Output pin di/dt (max. drive)

tps

25 pF

50 pF

1.11/1.20

0.97/0.65

1.74/1.75

0.92/0.94

2.42/2.46

1.39/1.30

tps

tdit

25 pF

50 pF

0.76/0.80

0.40/0.43

1.16/1.19

0.61/0.63

1.76/1.66

0.93/0.87

V/ns

25 pF

50 pF

0.38/0.41

0.20/0.22

0.59/0.60

0.31/0.32

0.89/0.82

0.47/0.43

25 pF

50 pF

89

94

198

209

398

421

mA/ns

Output pin di/dt (high drive)

25 pF

50 pF

59

62

132

139

265

279

Output pin di/dt (standard drive)

25 pF

50 pF

29

31

65

69

132

139

i.MX35 Applications Processors for Automotive Products, Rev. 10

Freescale Semiconductor

29

Table 26. AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive (1.8 V)

Min.

Rise/Fall

Max.

Rise/Fall

Parameter

Clock frequency

Symbol

Test Condition

Typ.

Units

f

—

125

—

MHz

V/ns

Output pin slew rate (max. drive)¹

tps

25 pF

50 pF

2.83/2.68

1.59/1.49

1.84/1.85

1.03/1.05

1.21/1.40

0.70/0.75

Output pin di/dt (max. drive)²

didt

25 pF

50 pF

89

95

202

213

435

456

mA/ns

Input pin transition times³

trfi

tpi

1.0 pF

0.07/0.08

0.35/1.17

1.18/1.99

0.11/0.12

0.63/1.53

1.45/2.35

0.16/0.20

1.16/2.04

1.97/2.85

ns

Input pin propagation delay, 50%–50%

Input pin propagation delay, 40%–60%

1

Min. condition for tps: wcs model, 1.1 V, IO 1.65 V, and 105 °C. tps is measured between VIL to VIH for rising edge and between

VIH to VIL for falling edge.

2

3

Max. condition for tdit: bcs model, 1.3 V, IO 1.95 V, and –40 °C.

Max. condition for tpi and trfi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Min. condition for tpi and trfi: bcs model, 1.3 V, IO 1.95 V

and –40 °C. Input transition time from pad is 5 ns (20%–80%).

4.9

Module-Level AC Electrical Specifications

This section contains the AC electrical information (including timing specifications) for the modules of

the i.MX35. The modules are listed in alphabetical order.

4.9.1

AUDMUX Electrical Specifications

The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between

internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is hence governed by the SSI module. See the electrical specification for SSI.

4.9.2

CSPI AC Electrical Specifications

The i.MX35 provides two CSPI modules. CSPI ports are multiplexed in the i.MX35 with other pins. See

the “External Signals and Multiplexing” chapter of the reference manual for more details.

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Freescale Semiconductor

Figure 7 and Figure 8 depict the master mode and slave mode timings of the CSPI, and Table 27 lists the

timing parameters.

SPI_RDY

CS11

SSn[3:0]

CS2

CS6

CS1

CS3

CS5

CS3

CS4

SCLK

MOSI

MISO

CS2

CS7 CS8

CS9

CS10

Figure 7. CSPI Master Mode Timing Diagram

SSn[3:0]

CS1

CS5

CS3

CS2

CS6

CS4

SCLK

CS3

CS2

CS9

CS7

CS10

MISO

MOSI

CS8

Figure 8. CSPI Slave Mode Timing Diagram

Table 27. CSPI Interface Timing Parameters

ID

Parameter

Symbol

Min.

Max.

Units

CS1

CS2

CS3

CS4

CS5

CS6

CS7

CS8

CS9

SCLK cycle time

t_clk

t_SW

60

30

—

30

5

—

7.6

—

ns

SCLK high or low time

SCLK rise or fall

t_RISE/FALL

t_CSLH

t_SCS

SSn[3:0] pulse width

SSn[3:0] lead time (CS setup time)

SSn[3:0] lag time (CS hold time)

MOSI setup time

t_HCS

t_Smosi

t_Hmosi

t_Smiso

MOSI hold time

5

MISO setup time

5

i.MX35 Applications Processors for Automotive Products, Rev. 10

Freescale Semiconductor

31

Table 27. CSPI Interface Timing Parameters (continued)

ID

Parameter

Symbol

Min.

Max.

Units

CS10

CS11

MISO hold time

t_Hmiso

t_SDRY

5

—

ns

SPI_RDY setup time

4.9.3

DPLL Electrical Specifications

There are three PLLs inside the i.MX35, all based on the same PLL design. The reference clock for these

PLLs is normally generated from an external 24-MHz crystal connected to an internal oscillator via

EXTAL24M and XTAL24 pins. It is also possible to connect an external 24-MHz clock directly to

EXTAL24M, bypassing the internal oscillator.

DPLL specifications are listed in Table 28.

Table 28. DPLL Specifications

Parameter

Reference clock frequency

Min. Typ. Max. Unit

Comments

10

—

24 100

MHz

Max. allowed reference clock phase noise

—

0.03 2 Tdck¹Fmodulation < 50 kHz

0.01

0.15

50 kHz < Fmodulation 300 Hz

Fmodulation > 300 KHz

Frequency lock time (FOL mode or non-integer MF)

Phase lock time

—

80

μs

—

100

Max. allowed PL voltage ripple

150

100

150

mV

Fmodulation < 50 kHz

50 kHz < Fmodulation 300 Hz

Fmodulation > 300 KHz

1

There are two PLL are used in the i.MX35, MPLL and PPLL. Both are based on same DPLL design.

If crystals are used instead of external oscillators, they should meed the following specifications:

Table 29. Clock Input Tolerance

Parameters

OSC24M

OSC_AUDIO

Normal Frequency

Frequency Tolerance

ESR

24 MHz

30 ppm

<80 Ω

25.576 MHz

20 ppm (high quality)

<80 Ω

Load Capacitance

Shunt capacitance

Level of drive

8 pF-12 pF

<7 pF

8 pF-12 pF

<7 pF

>150 μW

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Freescale Semiconductor

4.9.4

Embedded Trace Macrocell (ETM) Electrical Specifications

ETM is an ARM protocol. The timing specifications in this section are given as a guide for a test point

access (TPA) that supports TRACECLK frequencies up to 133 MHz.

Figure 9 depicts the TRACECLK timings of ETM, and Table 30 lists the timing parameters.

Figure 9. ETM TRACECLK Timing Diagram

Table 30. ETM TRACECLK Timing Parameters

ID

Parameter

Min.

Max.

Unit

T_cyc

T_wl

Clock period

Frequency dependent

—

3

ns

Low pulse width

High pulse width

2

T_wh

T

Clock and data rise time

Clock and data fall time

—

r

T_f

3

Figure 10 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and

Table 31 lists the timing parameters.

Figure 10. Trace Data Timing Diagram

Table 31. ETM Trace Data Timing Parameters

ID

Parameter

Min.

Max.

Unit

T_s

T_h

Data setup

Data hold

2

1

—

ns

4.9.4.1

Half-Rate Clocking Mode

When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and falling

edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 10. The same

T and T parameters from Table 31 still apply with respect to the falling edge of the TRACECLK signal.

s

h

i.MX35 Applications Processors for Automotive Products, Rev. 10

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33

4.9.5

EMI Electrical Specifications

This section provides electrical parametrics and timing for the EMI module.

4.9.5.1 NAND Flash Controller Interface (NFC)

The i.MX35 NFC supports normal timing mode, using two flash clock cycles for one access of RE and

WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 11, Figure 12,

Figure 13, and Figure 14 depict the relative timing requirements among different signals of the NFC at

module level for normal mode. Table 32 lists the timing parameters.

NFCLE

NF2

NF1

NF3

NF4

NFCE

NF5

NFWE

NFALE

NF6

NF7

NF8

NF9

Command

NFIO[7:0]

Figure 11. Command Latch Cycle Timing DIagram

NFCLE

NFCE

NF1

NF4

NF3

NF10

NF11

NF5

NF8

NFWE

NFALE

NF7

NF9

NF6

NFIO[7:0]

Address

Figure 12. Address Latch Cycle Timing DIagram

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Freescale Semiconductor

NFCLE

NFCE

NF1

NF3

NF10

NF11

NF5

NF8

NFWE

NFALE

NF7

NF6

NF9

NFIO[15:0]

Data to NF

Figure 13. Write Data Latch Cycle Timing DIagram

NFCLE

NFCE

NF14

NF15

NF13

NFRE

NFRB

NF17

NF16

NF12

NFIO[15:0]

Data from NF

Figure 14. Read Data Latch Cycle Timing DIagram

1

Table 32. NFC Timing Parameters

Example Timing for

Timing

^{NFC Clock}≈ 33 MHz

T = NFC Clock Cycle²

ID

Parameter

Symbol

Unit

T = 30 ns

Min.

Max.

Min.

Max.

NF1 NFCLE setup time

NF2 NFCLE hold time

NF3 NFCE setup time

NF4 NFCE hold time

tCLS

tCLH

tCS

T – 4.0 ns

T – 5.0 ns

T – 2.0 ns

T – 1.0 ns

—

26

25

28

29

—

ns

tCH

i.MX35 Applications Processors for Automotive Products, Rev. 10

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35

1

Table 32. NFC Timing Parameters (continued)

Example Timing for

NFC Clock ≈ 33 MHz

T = 30 ns

Timing

T = NFC Clock Cycle²

Symbol

ID

Parameter

Unit

Min.

T – 1.0 ns

Max.

Min.

Max.

NF5 NF_WP pulse width

NF6 NFALE setup time

NF7 NFALE hold time

NF8 Data setup time

tWP

tALS

tALH

tDS

29

ns

T – 4.0 ns

T – 4.5 ns

T – 2.0 ns

T – 5.0 ns

—

26

25.5

28

—

NF9 Data hold time

tDH

25

NF10 Write cycle time

NF11 NFWE hold time

NF12 Ready to NFRE low

NF13 NFRE pulse width

NF14 READ cycle time

NF15 NFRE high hold time

NF16 Data setup on READ

NF17 Data hold on READ

tWC

tWH

tRR

2T – 3.0 ns

T – 5.0 ns

57

25

6T

—

180

44

54.5

11

9

—

tRP

1.5T – 1.0 ns

2T – 5.5 ns

tRC

tREH

tDSR

tDHR

0.5T – 4.0 ns

N/A

0

1

2

The flash clock maximum frequency is 50 MHz.

Subject to DPLL jitter specification listed in Table 28, "DPLL Specifications," on page 32.

NOTE

High is defined as 80% of signal value and low is defined as 20% of signal

value.

Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is

approximately 33 MHz (30 ns). All timings are listed according to this NFC

clock frequency (multiples of NFC clock phases), except NF16 and NF17,

which are not NFC clock related.

4.9.5.2

Wireless External Interface Module (WEIM)

All WEIM output control signals may be asserted and deasserted by internal clocks related to the BCLK

rising edge or falling edge according to the corresponding assertion or negation control fields. The address

always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed

mode according to control register configuration. Output data begins related to BCLK rising edge except

in muxed mode where both rising and falling edge may be used according to control register configuration.

i.MX35 Applications Processors for Automotive Products, Rev. 10

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Freescale Semiconductor

Input data, ECB and DTACK all captured according to BCLK rising edge time. Figure 15 depicts the

timing of the WEIM module, and Table 33 lists the timing parameters.

WEIM Output Timing

WE2

WE3

WE1

BCLK

...

WE4

WE6

WE8

WE5

WE7

WE9

Address

CSx_B

RW_B

OE_B

WE10

WE12

WE11

WE13

EBy_B

LBA_B

WE14

WE16

WE15

WE17

Output Data

WEIM Input Timing

BCLK

WE18

Input Data

ECB_B

WE20

WE24

WE22

WE26

DTACK_B

WE27

Figure 15. WEIM Bus Timing Diagram

i.MX35 Applications Processors for Automotive Products, Rev. 10

Freescale Semiconductor

37

1

Table 33. WEIM Bus Timing Parameters

Parameter

ID

Min.

Max.

Unit

WE1

WE2

BCLK cycle time²

14.5

7

—

21

25

19

5

ns

BCLK low-level width²

BCLK high-level width²

WE3

7

WE4

Address valid to Clock rise/fall

Clock rise/fall to address invalid

Clock rise/fall to CSx_B valid

Clock rise/fall to CSx_B invalid

Clock rise/fall to RW_B valid

Clock rise/fall to RW_B invalid

Clock rise/fall to OE_B valid

Clock rise/fall to OE_B invalid

Clock rise/fall to EBy_B valid

Clock rise/fall to EBy_B invalid

Clock rise/fall to LBA_B valid

Clock rise/fall to LBA_B invalid

Clock rise/fall to Output Data valid

Clock rise to Output Data invalid

Input Data Valid to Clock rise³

15

22

15

3.6

8

WE5

WE6

WE7

WE8

12

8

WE9

3

WE10

WE11

WE12

WE13

WE14

WE15

WE16

WE17

WE18

WE19

7

12

5.5

11.5

10

20

1

3.8

6

17.5

0

5

10

2.5

—

0

1

Input Data Valid to Clock rise, FCE=0 (in the case there is ECB_B asserted

during access)

(BCLK/2)

+ 3.01

WE19

Input Data Valid to Clock rise, FCE=0 (in the case there is NO ECB_B

asserted during access)

6.9

—

ns

WE20

WE22

WE24

WE26

WE27

Clock rise to Input Data invalid³

ECB_B setup time³

1

5

—

ns

ECB_B hold time³

0

DTACK_B setup time

DTACK_B hold time

5.4

–3.2

1

2

“High” is defined as 80% of signal value, and “low” is defined as 20% of signal value.

BCLK parameters are measured from the 50% point. For example, “high” is defined as 50% of signal value and “low” is defined

as 50% of signal value.

3

Parameters W18, W20, W22, and W24 are tested when FCE=1. i.MX35 does not support FCE=0.

NOTE

Test conditions: load capacitance, 25 pF. Recommended drive strength for

all controls, address, and BCLK is set to maximum drive.

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Freescale Semiconductor

Recommended drive strength for all controls, address and BCLK is set to

maximum drive.

Figure 16 through Figure 21 depict some examples of basic WEIM accesses to external memory devices

with the timing parameters mentioned in Table 33 for specific control parameter settings.

BCLK

WE5

WE4

WE6

V1

Next Address

WE7

Last Valid Address

ADDR

CS[x]

RW

WE14

WE15

LBA

WE10

WE12

WE11

OE

WE13

EB[y]

WE20, WE21

V1

WE18, WE 19

DATA

BCLK

Figure 16. Synchronous Memory Timing Diagram for Read Access—WSC = 1

WE5

WE4

Last Valid Address

ADDR

CS[x]

Next Address

V1

WE6

WE8

WE7

WE9

RW

LBA

OE

WE14

WE15

WE13

WE12

WE16

EB[y]

DATA

WE17

V1

Figure 17. Synchronous Memory Timing Diagram for Write Access—

WSC = 1, EBWA = 1, EBWN = 1, LBN = 1

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39

BCLK

WE4

Last Valid Addr

WE6

WE5

Address V1

Address V2

ADDR

CS[x]

WE7

RW

WE14

WE10

WE15

LBA

WE11

WE13

OE

WE12

EB[y]

WE24, WE25

ECB

WE22, WE23

WE20, WE21

WE22, WE23

WE20, WE21

V1

V2

Halfword

V1+2

V2+2

Halfword

DATA

Halfword Halfword

WE18, WE19

Figure 18. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses—

WSC = 2, SYNC = 1, DOL = 0

BCLK

WE5

WE7

WE9

WE4

ADDR

Last Valid Addr

Address V1

WE6

CS[x]

WE8

RW

WE15

WE14

LBA

OE

WE13

WE12

EB[y]

WE24, WE25

WE22, WE23

ECB

WE17

WE16

V1+4 V1+8 V1+12

V1

DATA

WE16

Figure 19. Synchronous Memory TIming Diagram for Burst Write Access—

BCS = 1, WSC = 4, SYNC = 1, DOL = 0, PSR = 1

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BCLK

WE4

WE5

WE17

WE7

WE9

ADDR/

M_DATA

Last Valid Addr

Write Data

Address V1

WE16

WE6

CS[x]

RW

WE8

Write

WE14

WE15

LBA

OE

WE12

WE13

EB[y]

Figure 20. Muxed A/D Mode Timing Diagram for Synchronous Write Access—

WSC = 7, LBA = 1, LBN = 1, LAH = 1

BCLK

WE4

Last Valid Addr

WE6

WE5

WE20, WE21

Read Data

ADDR/

M_DATA

Address V1

WE18, WE19

CS[x]

WE7

RW

WE14

WE15

LBA

WE10

WE11

WE13

OE

WE12

EB[y]

Figure 21. Muxed A/D Mode Timing Diagram for Synchronous Read Access—

WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7

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41

Figure 22 through Figure 26, and Table 34 help to determine timing parameters relative chip select (CS)

state for asynchronous and DTACK WEIM accesses with corresponding WEIM bit fields and the timing

parameters mentioned above.

CS[x]

WE31

WE32

ADDR

Last Valid Address

Next Address

Address V1

RW

LBA

OE

WE39

WE35

WE37

WE40

WE36

WE38

EB[y]

DATA

WE44

V1

WE43

Figure 22. Asynchronous Memory Read Access

CS[x]

MAXDI

D(V1)

WE31

Addr. V1

WE32A

ADDR/

M_DATA

WE44

WE

WE40

WE39

WE35A

WE37

LBA

WE36

WE38

OE

BE[y]

MAXCO

Figure 23. Asynchronous A/D muxed Read Access (RWSC = 5)

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CS[x]

WE31

Last Valid Address

WE32

WE34

WE40

ADDR

Next Address

Address V1

WE33

RW

LBA

OE

WE39

WE45

WE41

WE46

BE[y]

DATA

WE42

D(V1)

Figure 24. Asynchronous Memory Write Access

CS[x]

WE41

WE31

D(V1)

Addr. V1

WE32A

ADDR/

M_DATA

WE42

WE33

WE39

WE34

RW

WE40A

LBA

OE

WE45

WE46

BE[y]

WE42

Figure 25. Asynchronous A/D Mux Write Access

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43

CS[x]

WE31

WE32

ADDR

Last Valid Address

Next Address

Address V1

RW

LBA

OE

WE39

WE35

WE37

WE40

WE36

WE38

EB[y]

DATA

WE44

V1

WE43

WE48

DATA

WE47

Figure 26. DTACK Read Access

Table 34. WEIM Asynchronous Timing Parameters Relative Chip Select Table

Determination By

Synchronous Measured

Parameters¹

Max

Ref No.

Parameter

Min

(If 133 MHz is

supported by SoC)

Unit

WE31

CS[x] valid to Address valid

WE4 – WE6 – CSA²

WE7 – WE5 – CSN³

—

3 – CSA

3 – CSN

—

ns

WE32 Address invalid to CS[x] invalid

WE32A( CS[x] valid to address invalid WE4 – WE7 + (LBN + LBA + 1 –3+ (LBN + LBA +

muxed

A/D

– CSA²)

1 – CSA)

WE33

WE34

WE35

CS[x] valid to WE valid

WE invalid to CS[x] invalid

CS[x] valid to OE valid

WE8 – WE6 + (WEA – CSA)

WE7 – WE9 + (WEN – CSN)

WE10 – WE6 + (OEA – CSA)

—

3 + (WEA – CSA)

3 – (WEN_CSN)

3 + (OEA – CSA)

ns

WE35A

(muxed

A/D)

WE10 – WE6 + (OEA + RLBN

+ RLBA + ADH + 1 – CSA)

–3 + (OEA +

RLBN + RLBA +

ADH + 1 – CSA)

3 + (OEA + RLBN +

RLBA + ADH + 1 –

CSA)

WE36

OE invalid to CS[x] invalid

WE7 – WE11 + (OEN – CSN)

—

3 – (OEN – CSN)

ns

WE37 CS[x] valid to BE[y] valid (read WE12 – WE6 + (RBEA – CSA)

access)

3 + (RBEA⁴– CSA)

WE38

BE[y] invalid to CS[x] invalid WE7 – WE13 + (RBEN – CSN)

(read access)

—

3 – (RBEN⁵– CSN)

ns

WE39

WE40

CS[x] valid to LBA valid

WE14 – WE6 + (LBA – CSA)

WE7 – WE15 – CSN

—

3 + (LBA – CSA)

3 – CSN

ns

LBA invalid to CS[x] invalid

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Table 34. WEIM Asynchronous Timing Parameters Relative Chip Select Table (continued)

Determination By

Synchronous Measured

Parameters¹

Max

Ref No.

Parameter

Min

(If 133 MHz is

supported by SoC)

Unit

WE40A

(muxed

A/D)

CS[x] valid to LBA invalid

WE14 – WE6 + (LBN + LBA + 1 –3+ (LBN + LBA + 3 + (LBN + LBA + 1 –

ns

– CSA)

1 – CSA)

CSA)

WE41 CS[x] valid to Output Data valid

WE16 – WE6 – WCSA

—

3 – WCSA

ns

WE41A CS[x] valid to Output Data valid

(muxed

A/D)

WE16 – WE6 + (WLBN +

WLBA + ADH + 1 – WCSA)

3 + (WLBN + WLBA +

ADH + 1 – WCSA)

WE42

Output Data invalid to CS[x]

Invalid

WE17 – WE7 – CSN

—

3 – CSN

—

ns

WE43

Input Data valid to CS[x] invalid MAXCO – MAXCSO + MAXDI

MAXCO^{6 –}

MAXCSO⁷+

MAXDI⁸

WE44

WE45

WE46

WE47

CS[x] invalid to Input Data

invalid

0

—

ns

CS[x] valid to BE[y] valid (write WE12 – WE6 + (WBEA – CSA)

access)

—

3 + (WBEA – CSA)

–3 + (WBEN – CSN)

—

BE[y] invalid to CS[x] invalid WE7 – WE13 + (WBEN – CSN)

(write access)

DTACK valid to CS[x] invalid MAXCO – MAXCSO + MAXDTI

MAXCO⁶–

MAXCSO⁷+

MAXDTI⁹

WE48

CS[x] Invalid to DTACK invalid

0

—

ns

1

2

3

4

5

6

7

8

9

For the value of parameters WE4–WE21, see column BCD = 0 in Table 33.

CS Assertion. This bit field determines when the CS signal is asserted during read/write cycles.

CS Negation. This bit field determines when the CS signal is negated during read/write cycles.

BE Assertion. This bit field determines when the BE signal is asserted during read cycles.

BE Negation. This bit field determines when the BE signal is negated during read cycles.

Output maximum delay from internal driving ADDR/control FFs to chip outputs.

Output maximum delay from CS[x] internal driving FFs to CS[x] out.

DATA maximum delay from chip input data to its internal FF.

DTACK maximum delay from chip dtack input to its internal FF.

Note: All configuration parameters (CSA, CSN, WBEA, WBEN, LBA, LBN, OEN, OEA, RBEA, and RBEN) are in cycle units.

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45

4.9.5.3

ESDCTL Electrical Specifications

Figure 27 through Figure 35 depict the timings pertaining to the ESDCTL module, which interfaces with

mobile DDR or SDR SDRAM. Table 35 through Table 45 list the timing parameters.

SD1

SDCLK

SD2

SD3

SD4

CS

RAS

CAS

SD5

SD4

SD5

SD4

SD5

WE

ADDR

DQ

SD6

SD7

ROW/BA

COL/BA

SD8

SD10

SD9

Data

SD4

DQM

Note: CKE is high during the read/write cycle.

Figure 27. SDRAM Read Cycle Timing Diagram

Table 35. DDR/SDR SDRAM Read Cycle Timing Parameters

SD5

ID

Parameter

Symbol

Min.

Max.

Unit

SD1

SD2

SD3

SD4

SD5

SD6

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

tCH

tCL

3.4

7.0

2.0

1.8

2.0

4.1

—

ns

tCK

CS, RAS, CAS, WE, DQM, CKE setup time

CS, RAS, CAS, WE, DQM, CKE hold time

Address setup time

tCMS

tCMH

tAS

—

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Table 35. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)

ID

Parameter

Symbol

Min.

Max.

Unit

SD7

SD8

Address hold time

SDRAM access time

Data out hold time¹

tAH

tAC

tOH

tRC

1.8

—

6.47

—

ns

SD9

1.2

10

ns

SD10

Active to read/write command period

—

clock

1

Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see

Table 44 and Table 45.

NOTE

SDR SDRAM CLK parameters are measured from the 50% point—that is,

high is defined as 50% of signal value and low is defined as 50% of signal

value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.

The timing parameters are similar to the ones used in SDRAM data

sheets—that is, Table 35 indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the

parameters are measured at maximum memory frequency.

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47

SD1

SDCLK

SD2

SD4

SD3

CS

SD5

RAS

CAS

SD4

SD5

SD4

WE

SD5

SD7

SD6

BA

ADDR

ROW / BA

COL/BA

DATA

SD13

SD14

DQ

DQM

Figure 28. SDR SDRAM Write Cycle Timing Diagram

Table 36. SDR SDRAM Write Timing Parameters

ID

Parameter

Symbol

Min.

Max.

Unit

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD13

SD14

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

CS, RAS, CAS, WE, DQM, CKE setup time

CS, RAS, CAS, WE, DQM, CKE hold time

Address setup time

tCH

tCL

0.45

7.0

2.4

1.4

2.4

1.4

2.4

1.4

0.55

—

ns

tCK

tCMS

tCMH

tAS

—

Address hold time

tAH

—

Data setup time

tDS

—

Data hold time

tDH

—

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NOTE

Test conditions are: pin voltage 1.7 V–1.95 V, capacitance 15 pF for all pins

(both DDR and non-DDR pins), drive strength is high (7.2 mA). “High” is

defined as 80% of signal value and “low” is defined as 20% of signal value.

SDR SDRAM CLK parameters are measured from the 50% point—that is,

“high” is defined as 50% of signal value, and “low” is defined as 50% of

signal value. tCH + tCL will not exceed 7.5 ns for 133 MHz. DDR SDRAM

CLK parameters are measured at the crossing point of SDCLK and SDCLK

(inverted clock).

The timing parameters are similar to the ones used in SDRAM data sheets.

Table 36 indicates SDRAM requirements. All output signals are driven by

the ESDCTL at the negative edge of SDCLK, and the parameters are

measured at maximum memory frequency.

SD1

SDCLK

SD2

SD3

CS

RAS

CAS

SD11

SD10

WE

SD7

SD6

BA

ADDR

ROW/BA

Figure 29. SDRAM Refresh Timing Diagram

Table 37. SDRAM Refresh Timing Parameters

ID

Parameter

Symbol

Min.

Max.

Unit

SD1

SD2

SD3

SD6

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

Address setup time

tCH

tCL

tCK

tAS

3.4

7.5

1.8

4.1

—

ns

—

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49

Table 37. SDRAM Refresh Timing Parameters (continued)

ID

Parameter

Symbol

Min.

Max.

Unit

SD7

SD10

SD11

Address hold time

tAH

tRP

tRC

1.8

1

—

4

ns

Precharge cycle period¹

clock

Auto precharge command period¹

2

20

1

SD10 and SD11 are determined by SDRAM controller register settings.

NOTE

SDR SDRAM CLK parameters are measured from the 50% point—that is,

“high” is defined as 50% of signal value and “low” is defined as 50% of

signal value.

The timing parameters are similar to the ones used in SDRAM data sheets.

Table 37 indicates SDRAM requirements. All output signals are driven by

the ESDCTL at the negative edge of SDCLK, and the parameters are

measured at maximum memory frequency.

SDCLK

CS

RAS

CAS

WE

ADDR

CKE

BA

SD16

Don’t care

Figure 30. SDRAM Self-Refresh Cycle Timing Diagram

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NOTE

The clock will continue to run unless both CKEs are low. Then the clock will

be stopped in low state.

Table 38. SDRAM Self-Refresh Cycle Timing Parameters

ID

Parameter

CKE output delay time

Symbol

Min.

Max.

Unit

SD16

tCKS

1.8

—

ns

DDR1

DDR3

SDCLK

DDR2

DDR4

CS

DDR5

DDR4

RAS

CAS

DDR5

DDR4

DDR5

WE

CKE

DDR4

DDR6

DDR7

ADDR

ROW/BA

COL/BA

Figure 31. DDR2 SDRAM Basic Timing Parameters

Table 39. DDR2 SDRAM Timing Parameter Table

DDR2-400

ID

PARAMETER

Symbol

Unit

Min

Max

DDR1 SDRAM clock high-level width

DDR2 SDRAM clock low-level width

DDR3 SDRAM clock cycle time

tCH

tCL

tCK

0.45

7.0

0.55

8.0

tCK

ns

1

DDR4 CS, RAS, CAS, CKE, WE setup time

tIS

1.5

—

ns

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51

Table 39. DDR2 SDRAM Timing Parameter Table

DDR2-400

Min

ID

PARAMETER

Symbol

Unit

Max

1

DDR5 CS, RAS, CAS, CKE, WE hold time

DDR6 Address output setup time

DDR7 Address output hold time

tIH

1.25

1.5

—

ns

1

tIS

1

tIH

1.5

NOTE

These values are for command/address slew rate of 1 V/ns and SDCLK,

SDCLK_B differential slew rate of 2 V/ns. For different values, use the

derating table.

Table 40. Derating Values for DDR2–400, DDR2–533

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SDCLK

SDCLK_B

DDR21

DDR20

DDR22

DDR23

DDR18

DDR19

DQS (output)

DDR18

Data

DDR17

Data

DM

Data

DQ (output)

DM

DQM (output)

DDR17

DDR18

Figure 32. DDR2 SDRAM Write Cycle Timing Diagram

Table 41. DDR2 SDRAM Write Cycle Parameters

DDR2-400

ID

PARAMETER

Symbol

Unit

Min

Max

DDR17 DQ and DQM setup time to DQS (single-ended strobe)

DDR18 DQ and DQM hold time to DQS (single-ended strobe)

DDR19 Write cycle DQS falling edge to SDCLK output setup time.

DDR20 Write cycle DQS falling edge to SDCLK output hold time.

DDR21 DQS latching rising transitions to associated clock edges

DDR22 DQS high level width

tDS1(base)

tDH1(base)

tDSS

0.5

—

ns

0.2

—

tCK

tDSH

0.2

—

tDQSS

–0.25

0.35

0.25

—

tDQSH

tDQSL

DDR23 DQS low level width

—

NOTE

These values are for DQ/DM slew rate of 1 V/ns and DQS slew rate of

1 V/ns. For different values use the derating table.

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Table 42. DDR Single-ended Slew Rate

NOTE

SDR SDRAM CLK parameters are measured from the 50% point—that is,

“high” is defined as 50% of signal value and “low” is defined as 50% of

signal value. DDR SDRAM CLK parameters are measured at the crossing

point of SDCLK and SDCLK (inverted clock).

Test conditions are: Capacitance 15 pF for DDR PADS. Recommended

drive strength is Medium for SDCLK and High for Address and controls.

SDCLK

SDCLK_B

DDR26

DQS (input)

DDR25

DDR24

DATA

DQ (input)

Figure 33. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram

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Table 43. DDR2 SDRAM Read Cycle Parameter Table

DDR2-400

Min

ID

PARAMETER

Symbol

Unit

Max

DDR24

DQS – DQ Skew (defines the Data valid window in

read cycles related to DQS).

tDQSQ

—

0.35

ns

DDR25

DDR26

DQS DQ in HOLD time from DQS¹

tQH

2.925

–0.5

—

ns

DQS output access time from SDCLK posedge

tDQSCK

0.5

¹The value was calculated for an SDCLK frequency of 133 MHz by the formula tQH = tHP – tQHS = min (tCL,tCH) – tQHS =

0.45 × tCK – tQHS = 0.45 × 7.5 – 0.45 = 2.925 ns.

NOTE

SDRAM CLK and DQS-related parameters are measured from the 50%

point—that is, “high” is defined as 50% of signal value and “low” is defined

as 50% of signal value. DDR SDRAM CLK parameters are measured at the

crossing point of SDCLK and SDCLK (inverted clock).

Test conditions are: Capacitance 15 pF for DDR PADS. Recommended

drive strength is Medium for SDCLK and High for Address and controls.

SDCLK

SD20

SD19

DQS (output)

DQ (output)

SD18

Data

SD17

Data

SD17

SD18

Data

DM

Data

DM

Data

DM

DQM (output)

DM

SD17

SD18

Figure 34. Mobile DDR SDRAM Write Cycle Timing Diagram

Table 44. Mobile DDR SDRAM Write Cycle Timing Parameters

1

ID

Parameter

Symbol

Min.

Max.

Unit

SD17 DQ and DQM setup time to DQS

SD18 DQ and DQM hold time to DQS

tDS

tDH

0.95

1.8

—

ns

SD19 Write cycle DQS falling edge to SDCLK output delay time.

SD20 Write cycle DQS falling edge to SDCLK output hold time.

tDSS

tDSH

1.8

1

Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.

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NOTE

SDRAM CLK and DQS-related parameters are measured from the 50%

point—that is, “high” is defined as 50% of signal value and “low” is defined

as 50% of signal value.

The timing parameters are similar to the ones used in SDRAM data sheets.

Table 44 indicates SDRAM requirements. All output signals are driven by

the ESDCTL at the negative edge of SDCLK, and the parameters are

measured at maximum memory frequency.

SDCLK

SD23

DQS (input)

DQ (input)

SD22

SD21

Data

Figure 35. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram

Table 45. Mobile DDR SDRAM Read Cycle Timing Parameters

ID

Parameter

Symbol Min. Max. Unit

SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS).

SD22 DQS DQ HOLD time from DQS

tDQSQ

tQH

—

2.3

—

0.85 ns

—

ns

SD23 DQS output access time from SDCLK posedge

tDQSCK

6.7

NOTE

SDRAM CLK and DQS-related parameters are measured from the 50%

point—that is, “high” is defined as 50% of signal value, and “low” is defined

as 50% of signal value.

The timing parameters are similar to the ones used in SDRAM data sheets.

Table 45 indicates SDRAM requirements. All output signals are driven by

the ESDCTL at the negative edge of SDCLK, and the parameters are

measured at maximum memory frequency.

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4.9.6

Enhanced Serial Audio Interface (ESAI) Timing Specifications

The ESAI consists of independent transmitter and receiver sections, each section with its own clock

generator. Table 46 shows the interface timing values. The number field in the table refers to timing signals

found in Figure 36 and Figure 37.

Table 46. Enhanced Serial Audio Interface Timing

No.

Characteristics^1,2

Symbol Expression²Min. Max. Condition³Unit

62 Clock cycle⁴

t_SSICC

4 × T

30.0

—

i ck

ns

c

63 Clock high period

ns

—

2 × T − 9.0

6

—

• For internal clock

c

• For external clock

2 × T

15

c

64 Clock low period

• For internal clock

ns

—

2 × T − 9.0

6

—

c

• For external clock

2 × T

15

c

65 SCKR rising edge to FSR out (bl) high

—

17.0

7.0

x ck

i ck a

ns

66 SCKR rising edge to FSR out (bl) low

67 SCKR rising edge to FSR out (wr) high⁵

68 SCKR rising edge to FSR out (wr) low⁵

69 SCKR rising edge to FSR out (wl) high

70 SCKR rising edge to FSR out (wl) low

—

17.0

7.0

x ck

i ck a

—

19.0

9.0

x ck

i ck a

—

19.0

9.0

x ck

i ck a

—

16.0

6.0

x ck

i ck a

—

17.0

7.0

x ck

i ck a

71 Data in setup time before SCKR (SCK in synchronous

mode) falling edge

—

12.0

19.0

—

x ck

i ck

72 Data in hold time after SCKR falling edge

73 FSR input (bl, wr) high before SCKR falling edge⁵

74 FSR input (wl) high before SCKR falling edge

75 FSR input hold time after SCKR falling edge

78 SCKT rising edge to FST out (bl) high

—

3.5

9.0

—

x ck

i ck

—

2.0

12.0

—

x ck

i ck a

—

2.0

12.0

—

x ck

i ck a

—

2.5

8.5

—

x ck

i ck a

—

18.0

8.0

x ck

i ck

79 SCKT rising edge to FST out (bl) low

—

20.0

10.0

x ck

i ck

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Table 46. Enhanced Serial Audio Interface Timing (continued)

Characteristics^1,2Symbol Expression²Min. Max. Condition³Unit

No.

80 SCKT rising edge to FST out (wr) high⁵

81 SCKT rising edge to FST out (wr) low⁵

82 SCKT rising edge to FST out (wl) high

83 SCKT rising edge to FST out (wl) low

—

20.0

10.0

x ck

i ck

ns

—

22.0

12.0

x ck

i ck

—

19.0

9.0

x ck

i ck

—

20.0

10.0

x ck

i ck

84 SCKT rising edge to data out enable from high

impedance

—

22.0

17.0

x ck

i ck

86 SCKT rising edge to data out valid

—

18.0

13.0

x ck

i ck

87 SCKT rising edge to data out high impedance ⁶⁷

89 FST input (bl, wr) setup time before SCKT falling edge⁵

90 FST input (wl) setup time before SCKT falling edge

91 FST input hold time after SCKT falling edge

—

21.0

16.0

x ck

i ck

—

2.0

18.0

—

x ck

i ck

—

2.0

18.0

—

x ck

i ck

—

4.0

5.0

—

x ck

i ck

1

i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that SCKT and SCKR are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that SCKT and SCKR are the same clock)

2

3

bl = bit length

wl = word length

wr = word length relative

SCKT(SCKT pin) = transmit clock

SCKR(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

4

5

For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync

signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the

second-to-last bit clock of the first word in the frame.

6

Periodically sampled and not 100% tested.

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62

63

64

SCKT

(Input/Output)

78

79

FST (Bit)

Out

82

83

FST (Word)

Out

86

84

86

87

First Bit

Last Bit

Data Out

89

91

FST (Bit) In

91

90

FST (Word) In

Figure 36. ESAI Transmitter Timing

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62

63

64

SCKR

(Input/Output)

65

66

FSR (Bit)

Out

69

70

FSR (Word)

Out

72

71

Data In

Last Bit

First Bit

75

73

FSR (Bit)

In

74

75

FSR (Word)

In

Figure 37. ESAI Receiver Timing

4.9.7

eSDHCv2 AC Electrical Specifications

Figure 38 depicts the timing of eSDHCv2, and Table 47 lists the eSDHCv2 timing characteristics. The

following definitions apply to values and signals described in Table 47:

•

LS: low-speed mode. Low-speed card can tolerate a clock up to 400 kHz.

FS: full-speed mode. For a full-speed MMC card, the card clock can reach 20 MHz; a full-speed

SD/SDIO card can reach 25 MHz.

•

HS: high-speed mode. For a high-speed MMC card, the card clock can reach 52 MHz; SD/SDIO

can reach 50 MHz.

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SD4

SD2

SD5

SD1

SDHCx_CLK

SD3

SDHCx_CMD

SDHCx_DAT_0

SDHCx_DAT_1

SD6

output from eSDHCv2 to card

output from card to eSDHCv2

SDHCx_DAT_7

SD7

SD8

SDHCx_CMD

SDHCx_DAT_0

SDHCx_DAT_1

SDHCx_DAT_7

Figure 38. eSDHCv2 Timing

Table 47. eSDHCv2 Interface Timing Specification

ID

Card Input Clock

Parameter

Symbols Min. Max. Unit

1

SD1 Clock frequency (Low Speed)

Clock frequency (SD/SDIO Full Speed/High Speed)

Clock frequency (MMC Full Speed/High Speed)

Clock frequency (Identification Mode)

SD2 Clock Low time

f_PP

0

400 kHz

25/50 MHz

20/52 MHz

2

3

f_OD

t_WL

100 400 kHz

7

—

3

ns

SD3 Clock high time

t_WH

t_TLH

t_THL

SD4 Clock rise time

—

SD5 Clock fall time

3

eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)

SD6 eSDHC output delay

t_OD

–3

3

ns

eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)

SD7 eSDHC input setup time

t_ISU

5

—

ns

4

SD8 eSDHC input hold time

t_IH

2.5

1

In low-speed mode, the card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

2

3

4

In normal-speed mode for the SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0–50 MHz.

In normal-speed mode for MMC card, clock frequency can be any value between 0 and 20 MHz. In high-speed mode, clock

frequency can be any value between 0–52 MHz.

To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

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4.9.8

Fast Ethernet Controller (FEC) AC Electrical Specifications

This section describes the electrical information of the FEC module. The FEC is designed to support both

10- and 100-Mbps Ethernet networks. An external transceiver interface and transceiver function are

required to complete the interface to the media. The FEC supports the 10/100 Mbps Media Independent

Interface (MII) using a total of 18 pins. The 10-Mbps 7-wire interface that is restricted to a 10-Mbps data

rate uses seven of the MII pins for connection to an external Ethernet transceiver.

4.9.8.1

FEC AC Timing

This section describes the AC timing specifications of the FEC. The MII signals are compatible with

transceivers operating at a voltage of 3.3 V.

4.9.8.2

MII Receive Signal Timing

The MII receive timing signals consist of FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and

FEC_RX_CLK. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of

25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency

must exceed twice the FEC_RX_CLK frequency. Table 48 lists MII receive channel timings.

Table 48. MII Receive Signal Timing

Num.

Characteristic¹

Min.

Max.

Unit

M1

M2

M3

M4

FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup

FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold

FEC_RX_CLK pulse width high

5

—

ns

5

ns

35%

65%

FEC_RX_CLK period

FEC_RX_CLK pulse width low

¹FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing when in 10 Mbps 7-wire interface mode.

Figure 39 shows the MII receive signal timings listed in Table 48.

M3

FEC_RX_CLK (input)

M4

FEC_RXD[3:0] (inputs)

FEC_RX_DV

FEC_RX_ER

M1

M2

Figure 39. MII Receive Signal Timing Diagram

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4.9.8.3

MII Transmit Signal Timing

The transmitter timing signals consist of FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and

FEC_TX_CLK. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of

25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency

must exceed twice the FEC_TX_CLK frequency. Table 49 lists MII transmit channel timings.

Table 49. MII Transmit Signal Timing

Num

Characteristic¹

Min.

Max.

Unit

M5

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER

invalid

5

—

ns

M6

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER

valid

—

20

ns

M7

M8

FEC_TX_CLK pulse width high

FEC_TX_CLK pulse width low

35%

65%

FEC_TX_CLK period

¹FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing when in 10 Mbps 7-wire interface mode.

Figure 40 shows the MII transmit signal timings listed in Table 49.

M7

FEC_TX_CLK (input)

M5

M8

FEC_TXD[3:0] (outputs)

FEC_TX_EN

FEC_TX_ER

M6

Figure 40. MII Transmit Signal Timing Diagram

4.9.8.4

MII Asynchronous Inputs Signal Timing

The MII asynchronous timing signals are FEC_CRS and FEC_COL. Table 50 lists MII asynchronous

inputs signal timing.

Table 50. MII Asynch Inputs Signal Timing

Num

Characteristic

Min.

Max.

Unit

M9¹

FEC_CRS to FEC_COL minimum pulse width

1.5

—

FEC_TX_CLK period

¹FEC_COL has the same timing in 10 Mbit 7-wire interface mode.

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Figure 41 shows MII asynchronous input timings listed in Table 50.

FEC_CRS, FEC_COL

M9

Figure 41. MII Asynch Inputs Timing Diagram

4.9.8.5

MII Serial Management Channel Timing

Serial management channel timing is accomplished using FEC_MDIO and FEC_MDC. The FEC

functions correctly with a maximum MDC frequency of 2.5 MHz. Table 51 lists MII serial management

channel timings.

The MDC frequency should be equal to or less than 2.5 MHz to be compliant with the IEEE 802.3 MII

specification. However the FEC can function correctly with a maximum MDC frequency of 15 MHz.

Table 51. MII Transmit Signal Timing

Num

Characteristic

Min.

Max.

Units

M10

FEC_MDC falling edge to FEC_MDIO output invalid (minimum

propagation delay)

0

—

ns

M11

FEC_MDC falling edge to FEC_MDIO output valid (max.

propagation delay)

—

5

ns

M12

M13

M14

M15

FEC_MDIO (input) to FEC_MDC rising edge setup

FEC_MDIO (input) to FEC_MDC rising edge hold

FEC_MDC pulse width high

18

0

—

ns

40%

60%

FEC_MDC period

FEC_MDC pulse width low

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Figure 42 shows MII serial management channel timings listed in Table 51.

M14

M15

FEC_MDC (output)

M10

FEC_MDIO (output)

M11

FEC_MDIO (input)

M12

M13

Figure 42. MII Serial Management Channel Timing Diagram

4.9.9

FIR Electrical Specifications

®

FIR implements asynchronous infrared protocols (FIR, MIR) defined by IrDA (Infrared Data

®

Association). Refer to the IrDA website for details on FIR and MIR protocols.

4.9.10 FlexCAN Module AC Electrical Specifications

The electrical characteristics are related to the CAN transceiver outside the chip. The i.MX35 has two

CAN modules available for systems design. Tx and Rx ports for both modules are multiplexed with other

I/O pins. Refer to the IOMUX chapter of the MCIMX35 Multimedia Applications Processor Reference

Manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN,

respectively.

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4.9.11 I²C AC Electrical Specifications

2

This section describes the electrical characteristics of the I C module.

2

4.9.11.1 I C Module Timing

2

Figure 43 depicts the timing of the I C module. Table 52 lists the I C module timing parameters.

IC11

IC9

IC10

I2DAT

I2CLK

IC7

IC4

IC2

IC3

IC8

IC10

IC6

IC11

STOP

START

IC5

IC1

2

Figure 43. I C Bus Timing Diagram

2

Table 52. I C Module Timing Parameters

Standard Mode

Fast Mode

Min.

ID

Parameter

Unit

Min.

Max.

IC1 I2CLK cycle time

10

4.0

0¹

—

2.5

0.6

0¹

—

μs

ns

μs

ns

pF

IC2 Hold time (repeated) START condition

IC3 Set-up time for STOP condition

IC4 Data hold time

—

3.45²

0.9²

IC5 HIGH Period of I2CLK Clock

4.0

4.7

250

4.7

—

0.6

1.3

0.6

100³

1.3

—

IC6 LOW Period of the I2CLK Clock

IC7 Set-up time for a repeated START condition

IC8 Data set-up time

—

IC9 Bus free time between a STOP and START condition

IC10 Rise time of both I2DAT and I2CLK signals

IC11 Fall time of both I2DAT and I2CLK signals

IC12 Capacitive load for each bus line (C_b)

—

1000

300

400

300

400

—

1

A device must internally provide a hold time of at least 300 ns for the I2DAT signal in order to bridge the undefined region of

the falling edge of I2CLK.

2

3

The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal.

A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement of set-up time (ID IC7) of

250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal.

If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line

max_rise_time (ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I²C-bus

specification) before the I2CLK line is released.

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4.9.12 IPU—Sensor Interfaces

This section contains a list of supported camera sensors, a functional description, and the electrical

characteristics.

4.9.12.1 Supported Camera Sensors

Table 53 lists the known supported camera sensors at the time of publication.

1

Table 53. Supported Camera Sensors

Vendor

Model

Conexant

Agilant

CX11646, CX20490², CX20450²

HDCP–2010, ADCS–1021², ADCS–1021²

TC90A70

Toshiba

ICMedia

iMagic

ICM202A, ICM102²

IM8801

Transchip

Fujitsu

TC5600, TC5600J, TC5640, TC5700, TC6000

MB86S02A

Micron

MI-SOC–0133

Matsushita

STMicro

OmniVision

Sharp

MN39980

W6411, W6500, W6501², W6600², W6552², STV0974²

OV7620, OV6630, OV2640

LZ0P3714 (CCD)

Motorola

MC30300 (Python)², SCM20014², SCM20114², SCM22114², SCM20027²

LM9618²

National Semiconductor

1

Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only

camera suppliers.

2

These sensors have not been validated at the time of publication.

4.9.12.2 Functional Description

There are three timing modes supported by the IPU.

4.9.12.2.1

Pseudo BT.656 Video Mode

Smart camera sensors, which typically include image processing capability, support video mode transfer

operations. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC

signals. The timing syntax is defined by the BT.656 standard.

This operation mode follows the recommendations of the ITU BT.656 specifications. The only control

signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream.

An active line starts with a SAV code and ends with an EAV code. In some cases, digital blanking is

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inserted in between EAV and SAV code. The CSI decodes and filters out the timing coding from the data

stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.

4.9.12.2.2

Gated Clock Mode

The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See

Figure 44.

Active Line

Start of Frame

nth frame

n+1th frame

SENSB_VSYNC

SENSB_HSYNC

SENSB_PIX_CLK

invalid

SENSB_DATA[9:0]

1st byte

Figure 44. Gated Clock Mode Timing Diagram

A frame starts with a rising edge on SENSB_VSYNC (all the timing corresponds to straight polarity of the

corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. The pixel clock

is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.

SENSB_HSYNC goes to low at the end of the line. Pixel clocks then become invalid and the CSI stops

receiving data from the stream. For the next line, the SENSB_HSYNC timing repeats. For the next frame,

the SENSB_VSYNC timing repeats.

4.9.12.2.3

Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.9.12.2.2, “Gated Clock Mode”),

except for the SENSB_HSYNC signal, which is not used. See Figure 45. All incoming pixel clocks are

valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states

low) until valid data is going to be transmitted over the bus.

Start of Frame

nth frame

n+1th frame

SENSB_VSYNC

SENSB_PIX_CLK

invalid

SENSB_DATA[7:0]

1st byte

Figure 45. Non-Gated Clock Mode Timing Diagram

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The timing described in Figure 45 is that of a Motorola sensor. Some other sensors may have slightly

different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;

active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.

4.9.12.3 Electrical Characteristics

Figure 46 depicts the sensor interface timing, and Table 54 lists the timing parameters.

1/IP1

SENSB_MCLK

(Sensor Input)

SENSB_PIX_CLK

(Sensor Output)

1/IP4

IP2

IP3

SENSB_DATA,

SENSB_VSYNC,

SENSB_HSYNC

Figure 46. Sensor Interface Timing Diagram

Table 54. Sensor Interface Timing Parameters

ID

Parameter

Symbol

Min.

Max.

Units

IP1

IP2

IP3

IP4

Sensor input clock frequency

Data and control setup time

Fmck

Tsu

0.01

5

133

—

MHz

ns

Data and control holdup time

Thd

3

—

ns

Sensor output (pixel) clock frequency

Fpck

0.01

133

MHz

4.9.13 IPU—Display Interfaces

This section describes the following types of display interfaces:

•

Section 4.9.13.1, “Synchronous Interfaces”

Section 4.9.13.2, “Interface to Sharp HR-TFT Panels”

Section 4.9.13.3, “Synchronous Interface to Dual-Port Smart Displays”

Section 4.9.13.4, “Asynchronous Interfaces”

Section 4.9.13.5, “Serial Interfaces, Functional Description”

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4.9.13.1 Synchronous Interfaces

This section discusses the interfaces to active matrix TFT LCD panels, Sharp HR-TFT, and dual-port smart

displays.

4.9.13.1.4

Interface to Active Matrix TFT LCD Panels, Functional Description

Figure 47 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,

signals are shown with negative polarity. The sequence of events for active matrix interface timing is as

follows:

•

DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is

selected). In active mode, DISPB_D3_CLK runs continuously.

•

DISPB_D3_HSYNC causes the panel to start a new line.

DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one

HSYNC pulse.

•

DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the

data to be shifted to the display. When disabled, the data is invalid and the trace is off.

DISPB_D3_VSYNC

DISPB_D3_HSYNC

LINE 1

LINE 2

LINE 3

LINE 4

LINE n – 1 LINE n

DISPB_D3_HSYNC

DISPB_D3_DRDY

1

2

3

m – 1

m

DISPB_D3_CLK

DISPB_D3_DATA

Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels

4.9.13.1.5

Interface to Active Matrix TFT LCD Panels, Electrical Characteristics

Figure 48 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and

the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity

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of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC

and DISPB_D3_DRDY signals.

IP7

IP6

IP9

IP10

IP8

IP5

Start of line

DISPB_D3_CLK

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_DATA

Figure 48. TFT Panels Timing Diagram—Horizontal Sync Pulse

Figure 49 depicts the vertical timing (timing of one frame). All figure parameters shown are

programmable.

End of frame

Start of frame

IP13

DISPB_D3_VSYNC

DISPB_D3_HSYNC

DISPB_D3_DRDY

IP15

IP11

IP14

IP12

Figure 49. TFT Panels Timing Diagram—Vertical Sync Pulse

Table 55 shows timing parameters of signals presented in Figure 48 and Figure 49.

Table 55. Synchronous Display Interface Timing Parameters—Pixel Level

ID

Parameter

Symbol

Value

Units

IP5

IP6

IP7

IP8

Display interface clock period

Display pixel clock period

Screen width

Tdicp

Tdpcp

Tsw

Tdicp¹

ns

(DISP3_IF_CLK_CNT_D + 1) × Tdicp

(SCREEN_WIDTH + 1) × Tdpcp

(H_SYNC_WIDTH + 1) × Tdpcp

HSYNC width

Thsw

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Table 55. Synchronous Display Interface Timing Parameters—Pixel Level (continued)

ID

Parameter

Symbol

Value

Units

IP9

Horizontal blank interval 1

Horizontal blank interval 2

HSYNC delay

Thbi1

Thbi2

Thsd

Tsh

BGXP × Tdpcp

ns

IP10

IP11

IP12

IP13

(SCREEN_WIDTH – BGXP – FW) × Tdpcp

H_SYNC_DELAY × Tdpcp

Screen height

(SCREEN_HEIGHT + 1) × Tsw

VSYNC width

Tvsw

if V_SYNC_WIDTH_L = 0 than

(V_SYNC_WIDTH + 1) × Tdpcp

else

(V_SYNC_WIDTH + 1) × Tsw

IP14

IP15

Vertical blank interval 1

Vertical blank interval 2

Tvbi1

Tvbi2

BGYP × Tsw

ns

(SCREEN_HEIGHT – BGYP – FH) × Tsw

1

Display interface clock period immediate value

Display interface clock period average value.

DISP3_IF_CLK_PER_WR

-----------------------------------------------------------------

⋅

Tdicp = T

HSP_CLK

HSP_CLK_PERIOD

Figure 50 depicts the synchronous display interface timing for access level, and Table 56 lists the timing

parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the

DI_DISP3_TIME_CONF Register.

IP20

DISPB_D3_VSYNC

DISPB_D3_HSYNC

DISPB_D3_DRDY

other controls

DISPB_D3_CLK

IP18

IP16

IP17

IP19

DISPB_DATA

Figure 50. Synchronous Display Interface Timing Diagram—Access Level

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Table 56. Synchronous Display Interface Timing Parameters—Access Level

ID

Parameter

Symbol

Min.

Typ.¹

Max.

Units

IP16 Display interface clock low time

IP17 Display interface clock high time

Tckl

Tdicd – Tdicu – 1.5

Tdicd²– Tdicu³

Tdicd – Tdicu + 1.5

ns

Tckh Tdicp – Tdicd +

Tdicu – 1.5

Tdicp – Tdicd +

Tdicu

Tdicp – Tdicd +

Tdicu + 1.5

IP18 Data setup time

IP19 Data holdup time

Tdsu Tdicd – 3.5

Tdicu

—

ns

Tdhd Tdicp – Tdicd – 3.5

Tcsu Tdicd – 3.5

Tdicp – Tdicu

Tdicu

IP20 Control signals setup time to

display interface clock

1

The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be device specific.

2

Display interface clock down time

1

2

2 ⋅ DISP3_IF_CLK_DOWN_WR

--

--------------------------------------------------------------------------------

⋅ ceil

Tdicd =

T

HSP_CLK

HSP_CLK_PERIOD

3

Display interface clock up time

1

2

2 ⋅ DISP3_IF_CLK_UP_WR

---------------------------------------------------------------------

⋅ ceil

--

Tdicu =

T

HSP_CLK

HSP_CLK_PERIOD

where CEIL(X) rounds the elements of X to the nearest integers toward infinity.

4.9.13.2 Interface to Sharp HR-TFT Panels

Figure 51 depicts the Sharp HR-TFT panel interface timing, and Table 57 lists the timing parameters. The

CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,

REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and

SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to

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Section 4.9.13.1.5, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.” The timing

images correspond to straight polarity of the Sharp signals.

Horizontal timing

DISPB_D3_CLK

D1 D2

D320

DISPB_D3_DATA

DISPB_D3_SPL

IP21

1 DISPB_D3_CLK period

DISPB_D3_HSYNC

IP23

IP22

DISPB_D3_CLS

DISPB_D3_PS

IP24

IP25

IP26

DISPB_D3_REV

Example is drawn with FW + 1 = 320 pixel/line, FH + 1 = 240 lines.

SPL pulse width is fixed and aligned to the first data of the line.

REV toggles every HSYNC period.

Figure 51. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level

Table 57. Sharp Synchronous Display Interface Timing Parameters—Pixel Level

ID

Parameter

SPL rise time

Symbol

Value

Units

IP21

IP22

IP23

IP24

IP25

IP26

Tsplr

Tclsr

Tclsf

Tpsf

Tpsr

Trev

(BGXP – 1) × Tdpcp

ns

CLS rise time

CLS_RISE_DELAY × Tdpcp

CLS_FALL_DELAY × Tdpcp

PS_FALL_DELAY × Tdpcp

PS_RISE_DELAY × Tdpcp

REV_TOGGLE_DELAY × Tdpcp

CLS fall time

CLS rise and PS fall time

PS rise time

REV toggle time

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4.9.13.3 Synchronous Interface to Dual-Port Smart Displays

Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are

identical to parameters of the synchronous interface. See Section 4.9.13.1.5, “Interface to Active Matrix

TFT LCD Panels, Electrical Characteristics.”

4.9.13.3.6

Interface to a TV Encoder—Functional Description

The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits

D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 52 depicts the

interface timing.

•

The frequency of the clock DISPB_D3_CLK is 27 MHz.

The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low.

The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal. It

remains low for a single clock cycle.

•

The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC

signal. It remains low for at least one clock cycle.

— At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC

and DISPB_D3_HSYNC coincide.

— At a transition to an even field (of the same frame), they do not coincide.

•

The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC

signal being high.

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DISPB_D3_CLK

DISPB_D3_HSYNC

DISPB_D3_VSYNC

DISPB_D3_DRDY

DISPB_DATA

Cb

Y

Cr

Y

3

Cb

Y

Cr

Pixel Data Timing

523

524

525

1

2

4

5

6

10

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Even Field

262 263

Odd Field

268 269

261

264

265

266

267

273

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Even Field

Odd Field

Line and Field Timing - NTSC

621

622

623

624

625

1

2

3

4

23

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Even Field

Odd Field

315

308

309

310

311

312

313

314

316

336

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Even Field

Odd Field

Line and Field Timing - PAL

Figure 52. TV Encoder Interface Timing Diagram

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4.9.13.3.7

Interface to a TV Encoder, Electrical Characteristics

The timing characteristics of the TV encoder interface are identical to the synchronous display

characteristics. See Section 4.9.13.1.5, “Interface to Active Matrix TFT LCD Panels, Electrical

Characteristics.”

4.9.13.4 Asynchronous Interfaces

This section discusses the asynchronous parallel and serial interfaces.

4.9.13.4.8

Parallel Interfaces, Functional Description

The IPU supports the following asynchronous parallel interfaces:

•

System 80 interface

— Type 1 (sampling with the chip select signal) with and without byte enable signals.

— Type 2 (sampling with the read and write signals) with and without byte enable signals.

System 68k interface

— Type 1 (sampling with the chip select signal) with or without byte enable signals.

— Type 2 (sampling with the read and write signals) with or without byte enable signals.

For each of four system interfaces, there are three burst modes:

1. Burst mode without a separate clock—The burst length is defined by the corresponding parameters

of the IDMAC (when data is transferred from the system memory) or by the HBURST signal (when

the MCU directly accesses the display via the slave AHB bus). For system 80 and system 68k type

1 interfaces, data is sampled by the CS signal and other control signals change only when transfer

direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals

(system 80) or by the ENABLE signal (system 68k), and the CS signal stays active during the

whole burst.

2. Burst mode with the separate clock DISPB_BCLK—In this mode, data is sampled with the

DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are

changed simultaneously with data when the bus state (read, write or wait) is altered. The CS

signals and other controls move to non-active state after burst has been completed.

3. Single access mode—In this mode, slave AHB and DMA burst are broken to single accesses. The

data is sampled with CS or other controls according to the interface type as described above. All

controls (including CS) become non-active for one display interface clock after each access. This

mode corresponds to the ATI single access mode.

Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 53,

Figure 54, Figure 55, and Figure 56. These timing images correspond to active-low DISPB_Dn_CS,

DISPB_Dn_WR and DISPB_Dn_RD signals.

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Additionally, the IPU allows a programmable pause between two bursts. The pause is defined in the

HSP_CLK cycles. It allows the prevention of timing violation between two sequential bursts or two

accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by CS signal

DISPB_BCLK

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 53. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram

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DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by WR/RD signals

DISPB_BCLK

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 54. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram

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DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Burst access mode with sampling by CS signal

DISPB_BCLK

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 55. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram

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DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Burst access mode with sampling by ENABLE signal

DISPB_BCLK

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 56. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram

Display read operation can be performed with wait states when each read access takes up to 4 display

interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the

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DI_DISPn_TIME_CONF_3 registers (n = 0,1,2). Figure 57 shows the timing of the parallel interface with

read wait states.

WRITE OPERATION

DISP0_RD_WAIT_ST=00

READ OPERATION

DISPB_D#_CS

DISPB_RD

DISPB_WR

DISPB_PAR_RS

DISPB_DATA

DISP0_RD_WAIT_ST=01

DISPB_D#_CS

DISPB_RD

DISPB_WR

DISPB_PAR_RS

DISPB_DATA

DISP0_RD_WAIT_ST=10

DISPB_D#_CS

DISPB_RD

DISPB_WR

DISPB_PAR_RS

DISPB_DATA

Figure 57. Parallel Interface Timing Diagram—Read Wait States

4.9.13.4.9

Parallel Interfaces, Electrical Characteristics

Figure 58, Figure 60, Figure 59, and Figure 61 depict timing of asynchronous parallel interfaces based on

the system 80 and system 68k interfaces. Table 58 lists the timing parameters at display access level. All

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timing images are based on active low control signals (signal polarity is controlled via the

DI_DISP_SIG_POL register).

IP28, IP27

DISPB_PAR_RS

DISPB_RD (READ_L)

DISPB_DATA[17]

(READ_H)

IP35, IP33

IP36, IP34

IP32, IP30

DISPB_D#_CS

DISPB_WR (WRITE_L)

DISPB_DATA[16]

(WRITE_H)

IP31, IP29

read point

Read Data

IP38

IP37

DISPB_DATA

(Input)

IP40

IP39

DISPB_DATA

(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 58. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram

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IP28, IP27

DISPB_PAR_RS

DISPB_D#_CS

IP35, IP33

IP36, IP34

DISPB_RD (READ_L)

DISPB_DATA[17]

(READ_H)

DISPB_WR (WRITE_L)

DISPB_DATA[16]

(WRITE_H)

IP31, IP29

IP32, IP30

read point

IP38

IP37

DISPB_DATA

(Input)

Read Data

IP39

IP40

DISPB_DATA

(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 59. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram

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IP28, IP27

DISPB_PAR_RS

DISPB_RD (ENABLE_L)

DISPB_DATA[17]

(ENABLE_H)

IP35,IP33

IP36, IP34

DISPB_D#_CS

DISPB_WR

(READ/WRITE)

IP31, IP29

IP32, IP30

read point

IP38

IP37

DISPB_DATA

(Input)

Read Data

IP39

IP40

DISPB_DATA

(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 60. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram

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IP28, IP27

DISPB_PAR_RS

DISPB_D#_CS

IP35,IP33

IP36, IP34

DISPB_RD (ENABLE_L)

DISPB_DATA[17]

(ENABLE_H)

DISPB_WR

(READ/WRITE)

IP32, IP30

IP31, IP29

read point

IP38

IP37

DISPB_DATA

(Input)

Read Data

IP39

IP40

DISPB_DATA

(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 61. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram

Table 58. Asynchronous Parallel Interface Timing Parameters—Access Level

ID

Parameter

Symbol

Min.

Typ.¹

Tdicpr²

Tdicpw³

Max.

Tdicpr + 1.5

Tdicpw + 1.5

Units

IP27 Read system cycle time

IP28 Write system cycle time

IP29 Read low pulse width

IP30 Read high pulse width

Tcycr Tdicpr – 1.5

Tcycw Tdicpw – 1.5

ns

Trl

Tdicdr – Tdicur – 1.5

Tdicdr⁴– Tdicur⁵Tdicdr – Tdicur + 1.5

Trh

Tdicpr – Tdicdr +

Tdicur – 1.5

Tdicpr – Tdicdr + Tdicpr – Tdicdr + Tdicur

Tdicur

+ 1.5

IP31 Write low pulse width

IP32 Write high pulse width

Twl

Tdicdw – Tdicuw

– 1.5

Tdicdw⁶–

Tdicuw⁷

Tdicdw – Tdicuw + 1.5

ns

Twh

Tdicpw – Tdicdw +

Tdicuw – 1.5

Tdicpw – Tdicdw Tdicpw – Tdicdw +

+ Tdicuw

Tdicuw + 1.5

IP33 Controls setup time for read

IP34 Controls hold time for read

Tdcsr Tdicur – 1.5

Tdicur

—

ns

Tdchr Tdicpr – Tdicdr – 1.5

Tdicpr – Tdicdr

—

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Table 58. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)

ID

Parameter

Symbol

Min.

Typ.¹

Tdicuw

Max.

Units

IP35 Controls setup time for write

IP36 Controls hold time for write

IP37 Slave device data delay⁸

Tdcsw Tdicuw – 1.5

—

ns

Tdchw Tdicpw – Tdicdw – 1.5

Tdicpw – Tdicdw

—

Tracc

0

Tdrp⁹– Tlbd¹⁰– Tdicur – ns

1.5

IP38 Slave device data hold time⁸

Troh

Tdrp – Tlbd – Tdicdr

+ 1.5

—

Tdicpr – Tdicdr – 1.5

ns

IP39 Write data setup time

IP40 Write data hold time

IP41 Read period²

Tds

Tdh

Tdicdw – 1.5

Tdicdw

Tdicpw – Tdicdw

Tdicpr

—

ns

Tdicpw – Tdicdw – 1.5

Tdicpr Tdicpr – 1.5

Tdicpw Tdicpw – 1.5

Tdicdr Tdicdr – 1.5

Tdicur Tdicur – 1.5

Tdicdw Tdicdw – 1.5

Tdicuw Tdicuw – 1.5

Tdrp Tdrp – 1.5

Tdicpr + 1.5

Tdicpw + 1.5

Tdicdr + 1.5

Tdicur + 1.5

Tdicdw + 1.5

Tdicuw + 1.5

Tdrp + 1.5

IP42 Write period³

Tdicpw

Tdicdr

IP43 Read down time⁴

IP44 Read up time⁵

IP45 Write down time⁶

IP46 Write up time⁷

Tdicur

Tdicdw

Tdicuw

Tdrp

IP47 Read time point⁹

¹The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be device-specific.

2

Display interface clock period value for read:

DISP#_IF_CLK_PER_RD

HSP_CLK_PERIOD

----------------------------------------------------------------

⋅ ceil

Tdicpr = T

HSP_CLK

3

Display interface clock period value for write:

DISP#_IF_CLK_PER_WR

HSP_CLK_PERIOD

-----------------------------------------------------------------

⋅ ceil

Tdicpw = T

HSP_CLK

4

Display interface clock down time for read:

1

2

2 ⋅ DISP#_IF_CLK_DOWN_RD

--

-------------------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicdr =

T

HSP_CLK_PERIOD

5

6

7

Display interface clock up time for read:

1

2

2 ⋅ DISP#_IF_CLK_UP_RD

--

--------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicur =

T

HSP_CLK_PERIOD

Display interface clock down time for write:

1

2

2 ⋅ DISP#_IF_CLK_DOWN_WR

--

--------------------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicdw =

T

HSP_CLK_PERIOD

Display interface clock up time for write:

1

2

2 ⋅ DISP#_IF_CLK_UP_WR

--

---------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicuw =

T

HSP_CLK_PERIOD

8

This parameter is a requirement to the display connected to the IPU

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9

Data read point

DISP#_READ_EN

HSP_CLK_PERIOD

--------------------------------------------------

⋅ ceil

Tdrp = T

HSP_CLK

¹⁰Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a

device – level output delay, board delays, a device – level input delay, an IPU input delay. This value is device specific.

The following parameters are programmed via the DI_DISP#_TIME_CONF_1,

DI_DISP#_TIME_CONF_2, and DI_HSP_CLK_PER registers:

•

DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD

HSP_CLK_PERIOD

DISP#_IF_CLK_DOWN_WR

DISP#_IF_CLK_UP_WR

DISP#_IF_CLK_DOWN_RD

DISP#_IF_CLK_UP_RD

DISP#_READ_EN

4.9.13.5 Serial Interfaces, Functional Description

The IPU supports the following types of asynchronous serial interfaces:

•

3-wire (with bidirectional data line)

4-wire (with separate data input and output lines)

5-wire type 1 (with sampling RS by the serial clock)

5-wire type 2 (with sampling RS by the chip select signal)

Figure 62 depicts timing of the 3-wire serial interface. The timing images correspond to active-low

DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal.

For this interface, a bidirectional data line is used outside the device. The IPU still uses separate input and

output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux connects the

internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal

provided by the IPU.

Each data transfer can be preceded by an optional preamble with programmable length and contents. The

preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is

programmable. The RW bit can be disabled. The following data can consist of one word or of a whole

burst. The interface parameters are controlled by the DI_SER_DISPn_CONF registers (n = 1, 2).

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1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

RW

RS

D7

D6

D5

D4

D3

D2

D1

D0

Input or output data

Preamble

Figure 62. 3-Wire Serial Interface Timing Diagram

Figure 63 depicts timing of the 4-wire serial interface. For this interface, there are separate input and output

data lines both inside and outside the device.

Write

1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

RW

RS

D7

D6

D5

D4

D3

D2

D1

D0

Preamble

Output data

DISPB_SD_D

(Input)

Read

1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

RW

RS

Preamble

DISPB_SD_D

(Input)

D7

D6

D5

D4

D3

D2

D1

D0

Input data

Figure 63. 4-Wire Serial Interface Timing Diagram

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Figure 64 depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is

added. When a burst is transmitted within a single active chip select interval, the RS can be changed at

boundaries of words.

Write

1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

RW

D7

D6

D5

D4

D3

D2

D1

D0

(Output)

Preamble

Output data

DISPB_SD_D

(Input)

DISPB_SER_RS

Read

1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

RW

Preamble

DISPB_SD_D

(Input)

D7

D6

D5

D4

D3

D2

D1

D0

Input data

DISPB_SER_RS

Figure 64. 5-Wire Serial Interface (Type 1) Timing Diagram

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Figure 65 depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is

added. When a burst is transmitted within a single active chip select interval, the RS can be changed at

boundaries of words.

Write

1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

RW

D7

D6

D5

D4

D3

D2

D1

D0

Output data

Preamble

DISPB_SD_D

(Input)

1 display IF

clock cycle

DISPB_SER_RS

Read

1 display IF

clock cycle

1 display IF

clock cycle

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

RW

Preamble

DISPB_SD_D

(Input)

D7

D6

D5

D4

D3

D2

D1

D0

Input data

1 display IF

clock cycle

DISPB_SER_RS

Figure 65. 5-Wire Serial Interface (Type 2) Timing Diagram

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4.9.13.5.10 Serial Interfaces, Electrical Characteristics

Figure 66 depicts timing of the serial interface. Table 59 lists the timing parameters at display access level.

IP49, IP48

DISPB_SER_RS

IP56,IP54

IP57, IP55

DISPB_SD_D_CLK

IP51, IP53

IP50, IP52

read point

IP59

IP58

DISPB_DATA

(Input)

Read Data

IP60

IP61

DISPB_DATA

(Output)

IP67,IP65

IP47

IP64, IP66

IP62, IP63

Figure 66. Asynchronous Serial Interface Timing Diagram

Table 59. Asynchronous Serial Interface Timing Parameters—Access Level

Typ.¹

Tdicpr²

Tdicpw³

ID

Parameter

Symbol

Min.

Max.

Tdicpr + 1.5

Tdicpw + 1.5

Units

IP48 Read system cycle time

IP49 Write system cycle time

IP50 Read clock low pulse width

IP51 Read clock high pulse width

Tcycr Tdicpr – 1.5

Tcycw Tdicpw – 1.5

ns

Trl

Tdicdr – Tdicur – 1.5

Tdicdr⁴– Tdicur⁵Tdicdr – Tdicur + 1.5

Trh

Tdicpr – Tdicdr + Tdicur Tdicpr – Tdicdr + Tdicpr – Tdicdr + Tdicur

– 1.5

Tdicur

+ 1.5

IP52 Write clock low pulse width

IP53 Write clock high pulse width

IP54 Controls setup time for read

Twl

Tdicdw – Tdicuw – 1.5

Tdicdw⁶–

Tdicuw⁷

Tdicdw – Tdicuw + 1.5

ns

Twh

Tdicpw – Tdicdw +

Tdicuw – 1.5

Tdicpw – Tdicdw Tdicpw – Tdicdw +

+ Tdicuw

Tdicuw + 1.5

Tdcsr Tdicur – 1.5

Tdicur

—

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Table 59. Asynchronous Serial Interface Timing Parameters—Access Level (continued)

ID

IP55 Controls hold time for read

IP56 Controls setup time for write Tdcsw Tdicuw – 1.5

Parameter

Symbol

Min.

Typ.¹

Max.

Units

Tdchr Tdicpr – Tdicdr – 1.5

Tdicpr – Tdicdr

Tdicuw

—

ns

IP57 Controls hold time for write

IP58 Slave device data delay⁸

Tdchw Tdicpw – Tdicdw – 1.5

Tdicpw – Tdicdw

—

Tracc

0

Tdrp⁹– Tlbd¹⁰– Tdicur

– 1.5

IP59 Slave device data hold time⁸

Troh

Tdrp – Tlbd – Tdicdr

+ 1.5

—

Tdicpr – Tdicdr – 1.5

ns

IP60 Write data setup time

IP61 Write data hold time

IP62 Read period²

Tds

Tdh

Tdicdw – 1.5

Tdicdw

Tdicpw – Tdicdw

Tdicpr

—

ns

Tdicpw – Tdicdw – 1.5

Tdicpr Tdicpr – 1.5

Tdicpw Tdicpw – 1.5

Tdicdr Tdicdr – 1.5

Tdicur Tdicur – 1.5

Tdicdw Tdicdw – 1.5

Tdicuw Tdicuw – 1.5

Tdrp Tdrp – 1.5

Tdicpr + 1.5

Tdicpw + 1.5

Tdicdr + 1.5

Tdicur + 1.5

Tdicdw + 1.5

Tdicuw + 1.5

Tdrp + 1.5

IP63 Write period³

Tdicpw

Tdicdr

IP64 Read down time⁴

IP65 Read up time⁵

IP66 Write down time⁶

IP67 Write up time⁷

Tdicur

Tdicdw

Tdicuw

Tdrp

IP68 Read time point⁹

1

The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be device specific.

2

Display interface clock period value for read:

DISP#_IF_CLK_PER_RD

HSP_CLK_PERIOD

----------------------------------------------------------------

⋅ ceil

Tdicpr = T

HSP_CLK

3

4

5

6

7

8

Display interface clock period value for write:

DISP#_IF_CLK_PER_WR

HSP_CLK_PERIOD

-----------------------------------------------------------------

⋅ ceil

Tdicpw = T

HSP_CLK

Display interface clock down time for read:

1

2

2 ⋅ DISP#_IF_CLK_DOWN_RD

--

-------------------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicdr =

T

HSP_CLK_PERIOD

Display interface clock up time for read:

1

2

2 ⋅ DISP#_IF_CLK_UP_RD

--

--------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicur =

T

HSP_CLK_PERIOD

Display interface clock down time for write:

1

2

2 ⋅ DISP#_IF_CLK_DOWN_WR

--

--------------------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicdw =

T

HSP_CLK_PERIOD

Display interface clock up time for write:

1

2

2 ⋅ DISP#_IF_CLK_UP_WR

--

---------------------------------------------------------------------

⋅ ceil

HSP_CLK

Tdicuw =

T

HSP_CLK_PERIOD

This parameter is a requirement to the display connected to the IPU.

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9

Data read point:

DISP#_READ_EN

HSP_CLK_PERIOD

--------------------------------------------------

⋅ ceil

Tdrp = T

HSP_CLK

¹⁰Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a

device-level output delay, board delays, a device-level input delay, and an IPU input delay. This value is device specific.

The following parameters are programmed via the DI_DISP#_TIME_CONF_1,

DI_DISP#_TIME_CONF_2, and DI_HSP_CLK_PER registers:

•

DISP#_IF_CLK_PER_WR

DISP#_IF_CLK_PER_RD

HSP_CLK_PERIOD

DISP#_IF_CLK_DOWN_WR

DISP#_IF_CLK_UP_WR

DISP#_IF_CLK_DOWN_RD

DISP#_IF_CLK_UP_RD

DISP#_READ_EN

4.9.14 Memory Stick Host Controller (MSHC)

Figure 67, Figure 68, and Figure 69 depict the MSHC timings, and Table 60 and Table 61 list the timing

parameters.

tSCLKc

tSCLKwh

tSCLKwl

MSHC_SCLK

tSCLKr

tSCLKf

Figure 67. MSHC_CLK Timing Diagram

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tSCLKc

MSHC_SCLK

MSHC_BS

tBSsu

tBSh

tDsu

tDh

MSHC_DATA

(Output)

tDd

MSHC_DATA

(Intput)

Figure 68. Transfer Operation Timing Diagram (Serial)

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tSCLKc

MSHC_SCLK

MSHC_BS

tBSsu

tBSh

tDsu

tDh

MSHC_DATA

(Output)

tDd

MSHC_DATA

(Input)

Figure 69. Transfer Operation Timing Diagram (Parallel)

NOTE

The memory stick host controller is designed to meet the timing

requirements per Sony's Memory Stick Pro Format Specifications. Tables in

this section detail the specifications’ requirements for parallel and serial

modes, and not the i.MX35 timing.

1

Table 60. Serial Interface Timing Parameters

Standards

Signal

Parameter

Symbol

Unit

Min.

Max.

MSHC_SCLK

Cycle

H pulse length

L pulse length

Rise time

tSCLKc

tSCLKwh

tSCLKwl

tSCLKr

tSCLKf

tBSsu

50

15

—

5

—

10

—

ns

Fall time

MSHC_BS

Setup time

Hold time

tBSh

5

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1

Table 60. Serial Interface Timing Parameters (continued)

Standards

Signal

Parameter

Symbol

Unit

Min.

Max.

MSHC_DATA

Setup time

Hold time

tDsu

tDh

5

—

15

ns

Output delay time

tDd

—

1

Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See NVCC

restrictions described in Table 61.

1

Table 61. Parallel Interface Timing Parameters

Standards

Signal

Parameter

Symbol

Unit

Min.

Max.

MSHC_SCLK

Cycle

H pulse length

L pulse length

Rise time

tSCLKc

tSCLKwh

tSCLKwl

tSCLKr

tSCLKf

tBSsu

tBSh

25

5

—

10

—

15

ns

5

—

8

Fall time

MSHC_BS

Setup time

Hold time

1

MSHC_DATA

Setup time

Hold time

tDsu

8

tDh

1

Output delay time

tDd

—

1

Timing is guaranteed for NVCC from 2.7 V through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See the NVCC

restrictions described in Table 8.

4.9.15 MediaLB Controller Electrical Specifications

This section describes the electrical information of the MediaLB Controller module.

Table 62. MLB 256/512 Fs Timing Parameters

Parameter

Symbol

Min

Typ

Max

Units

Comment

MLBCLK operating frequency¹

f_mck

11.264

MHz

Min: 256 × Fs at 44.0 kHz

Typ: 256 × Fs at 48.0 kHz

Typ: 512 × Fs at 48.0 kHz

Max: 512 × Fs at 48.1 kHz

Max: 512 × Fs PLL unlocked

12.288

24.576

24.6272

25.600

MLBCLK rise time

t_mckr

—

3

ns

V_ILTO V_IH

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Table 62. MLB 256/512 Fs Timing Parameters (continued)

Parameter

MLB fall time

Symbol

Min

Typ

Max

Units

Comment

t_mckf

t_mckc

—

3

ns

V_IHTO V_IL

MLBCLK cycle time

—

81

40

—

256 × Fs

512 × Fs

MLBCLK low time

t_mckl

31.5

30

37

35.5

—

ns

256 × Fs

256 × Fs PLL unlocked

14.5

14

17

16.5

—

512 × Fs

512 × Fs PLL unlocked

MLBCLK high time

t_mckh

31.5

30

38

36.5

—

256 × Fs

256 × Fs PLL unlocked

14.5

14

17

16.5

—

512 × Fs

512 × Fs PLL unlocked

MLBCLK pulse width variation

t_mpwv

t_dsmcf

—

1

—

2

ns pp

ns

Note²

MLBSIG/MLBDAT input valid to

MLBCLK falling

—

MLBSIG/MLBDAT input hold

from MLBCLK low

t_dhmcf

t_mcfdz

t_mdzh

0

4

—

t_mckl

—

ns

—

MLBSIG/MLBDAT output high

impedance from MLBCLK low

Bus Hold Time

Note³

1

2

The MLB controller can shut off MLBCLK to place MediaLB in a low-power state.

Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other

edge, measured in ns peak-to-peak (pp)

3

The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this

time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.

Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing parameters

specified from the valid voltage threshold as listed below unless otherwise noted.

Table 63. MLB Device 1024Fs Timing Parameters

Parameter

Symbol

Min

Typ

Max

Units

Comment

MLBCLK Operating

Frequency¹

f_mck

45.056

MHz

Min: 1024 × Fs at 44.0 kHz

Typ: 1024 × Fs at 48.0 kHz

Max: 1024 × Fs at 48.1 kHz

Max: 1024 × Fs PLL unlocked

49.152

49.2544

51.200

MLBCLK rise time

MLB fall time

t_mckr

t_mckf

t_mckc

t_mckl

—

1

ns

V_ILTO V_IH

V_IHTO V_IL

—

MLBCLK cycle time

MLBCLK low time

20.3

—

6.5

6.1

7.7

7.3

PLL unlocked

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Table 63. MLB Device 1024Fs Timing Parameters (continued)

Parameter

Symbol

Min

Typ

Max

Units

Comment

MLBCLK high time

t_mckh

9.7

9.3

10.6

10.2

—

ns

PLL unlocked

MLBCLK pulse width variation

t_mpwv

t_dsmcf

—

1

—

0.7

—

ns pp

ns

Note²

—

MLBSIG/MLBDAT input valid

to MLBCLK falling

MLBSIG/MLBDAT input hold

from MLBCLK low

t_dhmcf

t_mcfdz

t_mdzh

0

2

—

t_mckl

—

ns

—

MLBSIG/MLBDAT output high

impedance from MLBCLK low

Bus Hold Time

Note³

1

2

The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state.

Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge,

measured in ns peak-to-peak (pp)

3

The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this

time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.

4.9.16 1-Wire Timing Specifications

Figure 70 depicts the RPP timing, and Table 64 lists the RPP timing parameters.

1-WIRE Tx

DS2502 Tx

“Presence Pulse”

“Reset Pulse”

OW2

1-Wire bus

(BATT_LINE)

OW3

OW1

OW4

Figure 70. Reset and Presence Pulses (RPP) Timing Diagram

Table 64. RPP Sequence Delay Comparisons Timing Parameters

ID

OW1

Parameters

Symbol

Min.

480

Typ.

Max.

Units

Reset time low

t_RSTL

t_PDH

t_PDL

511

—

60

µs

OW2

OW3

OW4

Presence detect high

Presence detect low

Reset time high

15

60

—

240

—

t_RSTH

480

512

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Figure 71 depicts write 0 sequence timing, and Table 65 lists the timing parameters.

OW6

1-Wire bus

(BATT_LINE)

OW5

Figure 71. Write 0 Sequence Timing Diagram

Table 65. WR0 Sequence Timing Parameters

ID

Parameter

Symbol

Min.

Typ.

Max.

Units

OW5

OW6

Write 0 low time

Transmission time slot

t_{WR0_low}

t_SLOT

60

100

117

120

µs

OW5

Figure 72 shows write 1 sequence timing, and Figure 73 depicts the read sequence timing. Table 66 lists

the timing parameters.

OW8

1-Wire bus

(BATT_LINE)

OW7

Figure 72. Write 1 Sequence Timing Diagram

OW8

1-Wire bus

(BATT_LINE)

OW7

OW9

Figure 73. Read Sequence Timing Diagram

Table 66. WR1/RD Timing Parameters

ID

Parameter

Write 1/read low time

Symbol

Min.

Typ.

Max.

Units

OW7

OW8

OW9

t_LOW1

t_SLOT

1

5

15

120

45

µs

Transmission time slot

Release time

60

15

117

—

t_RELEASE

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4.9.17 Parallel ATA Module AC Electrical Specifications

The parallel ATA module can work on PIO/multiword DMA/ultra-DMA transfer modes (not available for

the MCIMX351). Each transfer mode has a different data transfer rate, Ultra DMA mode 4 data transfer

rate is up to 100 MBps.

The parallel ATA module interface consists of a total of 29 pins. Some pins have different functions in

different transfer modes. There are various requirements for timing relationships among the function pins,

in compliance with the ATA/ATAPI-6 specification, and these requirements are configurable by the ATA

module registers.

4.9.17.1 General Timing Requirements

Table 67 and Figure 74 define the AC characteristics of the interface signals on all data transfer modes.

Table 67. AC Characteristics of All Interface Signals

ID

Parameter

Symbol

Min.

Max.

Unit

1

SI1 Rising edge slew rate for any signal on the ATA interface¹

SI2 Falling edge slew rate for any signal on the ATA interface¹

SI3 Host interface signal capacitance at the host connector

S_rise

—

1.25

20

V/ns

pF

1

S_fall

C_host

1

SRISE and SFALL meet this requirement when measured at the sender’s connector from 10–90% of full signal amplitude with

all capacitive loads from 15 pF through 40 pF, where all signals have the same capacitive load value.

ATA Interface Signals

SI2

SI1

Figure 74. ATA Interface Signals Timing Diagram

4.9.17.2 ATA Electrical Specifications (ATA Bus, Bus Buffers)

This section discusses ATA parameters. For a detailed description, refer to the ATA-6 specification.

Level shifters are required for 3.3-V or 5.0-V compatibility on the ATA interface.

The use of bus buffers introduces delays on the bus and introduces skew between signal lines. These factors

make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. Use of bus

buffers is not recommended if fast UDMA mode is required.

The ATA specification imposes a slew rate limit on the ATA bus. According to this limit, any signal driven

on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Few vendors of bus buffers

specify the slew rate of the outgoing signals.

When bus buffers are used the ata_data bus buffer is bidirectional, and uses the direction control signal

ata_buffer_en. When ata_buffer_en is asserted, the bus should drive from host to device. When

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101

ata_buffer_en is negated, the bus drives from device to host. Steering of the signal is such that contention

on the host and device tri-state buses is always avoided.

4.9.17.3 Timing Parameters

Table 68 shows the parameters used in the timing equations. These parameters depend on the

implementation of the ATA interface on silicon, the bus buffer used, the cable delay, and the cable skew.

Table 68. ATA Timing Parameters

Value/

Name

Description

Contributing Factor¹

T

Bus clock period (ipg_clk_ata)

Peripheral clock

frequency

ti_ds Set-up time ata_data to ata_iordy edge (UDMA-in only)

15 ns

10 ns

7 ns

5 ns

4 ns

UDMA0

UDMA1

UDMA2, UDMA3

UDMA4

UDMA5

ti_dh Hold time ata_iordy edge to ata_data (UDMA-in only)

5.0 ns

4.6 ns

UDMA0, UDMA1, UDMA2, UDMA3, UDMA4

UDMA5

tco

tsu

Propagation delay bus clock L-to-H to

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,

ata_buffer_en

12.0 ns

Set-up time ata_data to bus clock L-to-H

8.5 ns

2.5 ns

7 ns

tsui Set-up time ata_iordy to bus clock H-to-L

thi Hold time ata_iordy to bus clock H to L

tskew1 Maximum difference in propagation delay bus clock L-to-H to any of following signals

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data

(write), ata_buffer_en

tskew2 Maximum difference in buffer propagation delay for any of following signals

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data

(write), ata_buffer_en

Transceiver

tskew3 Maximum difference in buffer propagation delay for any of following signals ata_iordy,

ata_data (read)

tbuf Maximum buffer propagation delay

Transceiver

Cable

tcable1 Cable propagation delay for ata_data

tcable2 Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack

tskew4 Maximum difference in cable propagation delay between ata_iordy and ata_data (read)

Cable

tskew5 Maximum difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack)

and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)

Cable

tskew6 Maximum difference in cable propagation delay without accounting for ground bounce

Cable

1

Values provided where applicable.

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4.9.17.4 PIO Mode Timing

Figure 75 shows timing for PIO read, and Table 69 lists the timing parameters for PIO read.

Figure 75. PIO Read Timing Diagram

Table 69. PIO Read Timing Parameters

ATA

Parameter

Parameter from

Figure 75

Controlling

Variable

Value

t1

t2

t9

t5

t1

t2r

t9

t1 (min.) = time_1 × T – (tskew1 + tskew2 + tskew5)

t2 min.) = time_2r × T – (tskew1 + tskew2 + tskew5)

t9 (min.) = time_9 × T – (tskew1 + tskew2 + tskew6)

t5 (min.) = tco + tsu + tbuf + tbuf + tcable1 + tcable2

time_1

time_2r

time_3

t5

If not met, increase

time_2

t6

tA

trd

t6

tA

0

—

tA (min.) = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2 × tbuf)

time_ax

trd1

trd1 (max.) = (–trd) + (tskew3 + tskew4)

time_pio_rdx

trd1 (min.) = (time_pio_rdx – 0.5) × T – (tsu + thi)

(time_pio_rdx – 0.5) × T > tsu + thi + tskew3 + tskew4

t0

—

t0 (min.) = (time_1 + time_2 + time_9) × T

time_1, time_2r, time_9

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Figure 76 shows timing for PIO write, and Table 70 lists the timing parameters for PIO write.

Figure 76. PIO Write Timing Diagram

Table 70. PIO Write Timing Parameters

Parameter

ATA

Parameter

Controlling

Variable

from

Value

Figure 76

t1

t2

t9

t3

t1

t2w

t9

t1 (min.) = time_1 × T – (tskew1 + tskew2 + tskew5)

t2 (min.) = time_2w × T – (tskew1 + tskew2 + tskew5)

t9 (min.) = time_9 × T – (tskew1 + tskew2 + tskew6)

t3 (min.) = (time_2w – time_on) × T – (tskew1 + tskew2 +tskew5)

time_1

time_2w

time_9

—

If not met, increase

time_2w

t4

tA

t0

t4

tA

—

t4 (min.) = time_4 × T – tskew1

time_4

tA = (1.5 + time_ax) × T – (tco + tsui + tcable2 + tcable2 + 2*tbuf)

t0(min.) = (time_1 + time_2 + time_9) × T

time_ax

time_1, time_2r,

time_9

—

Avoid bus contention when switching buffer on by making ton long enough.

Avoid bus contention when switching buffer off by making toff long enough.

—

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Figure 77 shows timing for MDMA read, and Figure 78 shows timing for MDMA write. Table 71 lists the

timing parameters for MDMA read and write.

Figure 77. MDMA Read Timing Diagram

Figure 78. MDMA Write Timing Diagram

Table 71. MDMA Read and Write Timing Parameters

Parameter

ATA

Parameter

from

Figure 77,

Figure 78

Controlling

Variable

Value

tm, ti

tm

td, td1

tk

tm (min.) = ti (min.) = time_m × T – (tskew1 + tskew2 + tskew5)

td1.(min.) = td (min.) = time_d × T – (tskew1 + tskew2 + tskew6)

tk.(min.) = time_k × T – (tskew1 + tskew2 + tskew6)

t0 (min.) = (time_d + time_k) × T

time_m

time_d

td

tk

time_k

t0

—

time_d, time_k

time_d

tg(read)

tgr

tgr (min. – read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2

tgr.(min. – drive) = td – te(drive)

tf(read)

tg(write)

tf(write)

tL

tfr

—

tfr (min. – drive) = 0

—

time_d

tg (min. – write) = time_d × T – (tskew1 + tskew2 + tskew5)

tf (min. – write) = time_k × T – (tskew1 + tskew2 + tskew6)

tL (max.) = (time_d + time_k–2) × T – (tsu + tco + 2 × tbuf + 2 × tcable2)

time_k

time_d, time_k

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Table 71. MDMA Read and Write Timing Parameters (continued)

Parameter

ATA

Parameter

from

Figure 77,

Figure 78

Controlling

Variable

Value

tn, tj

—

tkjn

tn = tj = tkjn = (max.(time_k,. time_jn) × T – (tskew1 + tskew2 + tskew6)

time_jn

—

ton

toff

ton = time_on × T – tskew1

toff = time_off × T – tskew1

4.9.17.5 UDMA-In Timing

Figure 79 shows timing when the UDMA-in transfer starts, Figure 80 shows timing when the UDMA-in

host terminates transfer, Figure 81 shows timing when the UDMA-in device terminates transfer, and

Table 72 lists the timing parameters for the UDMA-in burst.

Figure 79. UDMA-In Transfer Starts Timing Diagram

Figure 80. UDMA-In Host Terminates Transfer Timing Diagram

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Figure 81. UDMA-In Device Terminates Transfer Timing Diagram

Table 72. UDMA-In Burst Timing Parameters

Parameters

from

ATA

Parameter

Figure 79,

Figure 80,

Figure 81

Description

Controlling Variable

tack

tenv

tack

tenv

tack (min.) = (time_ack × T) – (tskew1 + tskew2)

time_ack

time_env

tenv (min.) = (time_env × T) – (tskew1 + tskew2)

tenv (max.) = (time_env × T) + (tskew1 + tskew2)

tds

tdh

tds1

tdh1

tc1

tds – (tskew3) – ti_ds > 0

tskew3, ti_ds, ti_dh

should be low enough

tdh – (tskew3) – ti_dh > 0

tcyc

trp

(tcyc – tskew > T

T big enough

time_rp

trp

trp (min.) = time_rp × T – (tskew1 + tskew2 + tskew6)

(time_rp × T) – (tco + tsu + 3T + 2 × tbuf + 2 × tcable2) > trfs (drive)

tmli1 (min.) = (time_mlix + 0.4) × T

tzah (min.) = (time_zah + 0.4) × T

—

tx1¹

tmli1

tzah

tdzfs

tcvh

time_rp

tmli

tzah

tdzfs

tcvh

—

time_mlix

time_zah

time_dzfs

time_cvh

—

tdzfs = (time_dzfs × T) – (tskew1 + tskew2)

tcvh = (time_cvh × T) – (tskew1 + tskew2)

ton

toff

ton = time_on × T – tskew1

toff = time_off × T – tskew1

1

There is a special timing requirement in the ATA host that requires the internal DIOW to go high three clocks after the last active

edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.

2. Make ton and toff large enough to avoid bus contention.

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4.9.17.6 UDMA-Out Timing

Figure 82 shows timing when the UDMA-out transfer starts, Figure 83 shows timing when the UDMA-out

host terminates transfer, Figure 84 shows timing when the UDMA-out device terminates transfer, and

Table 73 lists the timing parameters for the UDMA-out burst.

Figure 82. UDMA-Out Transfer Starts Timing Diagram

Figure 83. UDMA-Out Host Terminates Transfer Timing Diagram

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Figure 84. UDMA-Out Device Terminates Transfer Timing Diagram

Table 73. UDMA-Out Burst Timing Parameters

Parameter

from

ATA

Parameter

Controlling

Variable

Figure 82,

Figure 83,

Figure 84

Value

tack

tenv

tack

tenv

tack (min.) = (time_ack × T) – (tskew1 + tskew2)

time_ack

time_env

tenv (min.) = (time_env × T) – (tskew1 + tskew2)

tenv (max.) = (time_env × T) + (tskew1 + tskew2)

tdvs

tdvh

tcyc

t2cyc

trfs1

—

tdvs

tdvh

tcyc

—

tdvs = (time_dvs ×T) – (tskew1 + tskew2)

tdvs = (time_dvh × T) – (tskew1 + tskew2)

tcyc = time_cyc × T – (tskew1 + tskew2)

t2cyc = time_cyc × 2 × T

time_dvs

time_dvh

time_cyc

—

trfs

trfs = 1.6 × T + tsui + tco + tbuf + tbuf

tdzfs = time_dzfs × T – (tskew1)

tss = time_ss × T – (tskew1 + tskew2)

tdzfs_mli = max. (time_dzfs, time_mli) × T – (tskew1 + tskew2)

tli1 > 0

tdzfs

tss

time_dzfs

time_ss

—

tss

tmli

tli

tdzfs_mli

tli1

—

tli

tli2

tli2 > 0

—

tli

tli3

tli3 > 0

—

tcvh

—

tcvh

tcvh = (time_cvh × T) – (tskew1 + tskew2)

time_cvh

—

ton

toff

ton = time_on × T – tskew1

toff = time_off × T – tskew1

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4.9.18 Parallel Interface (ULPI) Timing

Electrical and timing specifications of the parallel interface are presented in the subsequent sections.

Table 74. Signal Definitions—Parallel Interface

Name

Direction

Signal Description

USB_Clk

Interface clock. All interface signals are synchronous to the clock.

In

I/O

In

USB_Data[7:0]

USB_Dir

Bidirectional data bus, driven low by the link during idle. Bus ownership is determined by Dir.

Direction. Control the direction of the data bus.

USB_Stp

Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus.

Next. The PHY asserts this signal to throttle the data.

Out

In

USB_Nxt

USB_Clk

US15

US16

USB_Stp

US15

US16

USB_Data

US17

USB_Dir/Nxt

Figure 85. USB Transmit/Receive Waveform in Parallel Mode

Table 75. USB Timing Specification in VP_VM Unidirectional Mode

Conditions /

Reference Signal

ID

Parameter

Min.

Max.

Unit

US15 USB_TXOE_B

US16 USB_DAT_VP

US17 USB_SE0_VM

—

6.0

0.0

9.0

ns

10 pF

4.9.19 PWM Electrical Specifications

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

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pin. The modulated signal of the module is observed at this pin. It can be viewed as a clock signal whose

period and duty cycle can be varied with different settings of the PWM. The smallest period is two ipg_clk

periods with duty cycle of 50 percent.

4.9.20 SJC Electrical Specifications

This section details the electrical characteristics for the SJC module. Figure 86 depicts the SJC test clock

input timing. Figure 87 depicts the SJC boundary scan timing, Figure 88 depicts the SJC test access port,

Figure 89 depicts the SJC TRST timing, and Table 76 lists the SJC timing parameters.

SJ1

SJ2

VM

SJ2

VM

TCK

(Input)

VIH

VIL

SJ3

Figure 86. Test Clock Input Timing Diagram

TCK

(Input)

VIH

SJ5

Input Data Valid

VIL

SJ4

Data

Inputs

SJ6

Data

Outputs

Output Data Valid

SJ7

SJ6

Data

Outputs

Data

Outputs

Output Data Valid

Figure 87. Boundary Scan (JTAG) Timing Diagram

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TCK

(Input)

VIH

VIL

SJ8

Input Data Valid

SJ9

TDI

TMS

(Input)

SJ10

SJ11

SJ10

TDO

Output Data Valid

(Output)

TDO

(Output)

TDO

(Output)

Output Data Valid

Figure 88. Test Access Port Timing Diagram

TCK

(Input)

SJ13

TRST

(Input)

SJ12

Figure 89. TRST Timing Diagram

Table 76. SJC Timing Parameters

Parameter

All Frequencies

ID

Unit

Min.

Max.

SJ1 TCK cycle time

100¹

40

—

3

ns

2

SJ2 TCK clock pulse width measured at V_M

SJ3 TCK rise and fall times

SJ4 Boundary scan input data set-up time

SJ5 Boundary scan input data hold time

SJ6 TCK low to output data valid

SJ7 TCK low to output high impedance

SJ8 TMS, TDI data set-up time

10

50

—

50

—

44

—

10

50

—

SJ9 TMS, TDI data hold time

SJ10 TCK low to TDO data valid

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Table 76. SJC Timing Parameters (continued)

Parameter

All Frequencies

Min. Max.

44

ID

Unit

SJ11 TCK low to TDO high impedance

SJ12 TRST assert time

—

ns

100

40

—

SJ13 TRST set-up time to TCK low

1

2

On cases where SDMA TAP is put in the chain, the max. TCK frequency is limited by max. ratio of 1:8 of SDMA core frequency

to TCK limitation. This implies max. frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.

V_M= mid point voltage

4.9.21 SPDIF Timing

SPDIF data is sent using bi-phase marking code. When encoding, the SPDIF data signal is modulated by

a clock that is twice the bit rate of the data signal.

Figure 90 shows SPDIF timing parameters, including the timing of the modulating Rx clock (SRCK) for

SPDIF in Rx mode and the timing of the modulating Tx clock (STCLK). for SPDIF in Tx mode.

Table 77. SPDIF Timing Parameters

Timing Parameter Range

Parameters

Symbol

Units

Min.

Max.

SPDIFIN Skew: asynchronous inputs, no specs apply

SPDIFOUT output (Load = 50 pf)

—

0.7

ns

—

1.5

24.2

31.3

• Skew

• Transition rising

• Transition falling

SPDIFOUT1 output (Load = 30 pf)

—

1.5

13.6

18.0

ns

• Skew

• Transition rising

• Transition falling

Modulating Rx clock (SRCK) period

SRCK high period

srckp

srckph

srckpl

stclkp

stclkph

stclkpl

40.0

16.0

40.0

16.0

—

ns

SRCK low period

Modulating Tx clock (STCLK) period

STCLK high period

STCLK low period

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srckp

srckpl

V_M

srckph

V_M

SRCK

(Output)

Figure 90. SRCK Timing

stclkp

stclkpl

V_M

stclkph

V_M

STCLK

(Input)

Figure 91. STCLK Timing

4.9.22 SSI Electrical Specifications

This section describes electrical characteristics of the SSI.

NOTE

•

All of the timing for the SSI is given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables

and in the figures.

•

All timing is on AUDMUX signals when SSI is being used for data

transfer.

“Tx” and “Rx” refer to the transmit and receive sections of the SSI,

respectively.

For internal frame sync operations using the external clock, the FS

timing will be the same as that of Tx Data (for example, during AC97

mode of operation).

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4.9.22.1 SSI Transmitter Timing with Internal Clock

Figure 92 depicts the SSI transmitter timing with internal clock, and Table 78 lists the timing parameters.

SS1

SS5

SS4

SS3

SS2

AD1_TXC

(Output)

SS8

SS6

AD1_TXFS (bl)

(Output)

SS10

SS12

AD1_TXFS (wl)

(Output)

SS14

SS17

SS15

SS16

SS18

AD1_TXD

(Output)

SS43

SS42

SS19

AD1_RXD

(Input)

Note: SRXD Input in Synchronous mode only

SS1

SS3

SS5

SS4

SS2

DAM1_T_CLK

(Output)

SS8

SS6

DAM1_T_FS (bl)

(Output)

SS10

SS12

DAM1_T_FS (wl)

(Output)

SS14

SS17

SS15

SS18

SS16

DAM1_TXD

(Output)

SS43

SS42

SS19

DAM1_RXD

(Input)

Note: SRXD Input in Synchronous mode only

Figure 92. SSI Transmitter with Internal Clock Timing Diagram

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Table 78. SSI Transmitter with Internal Clock Timing Parameters

ID

Parameter

Min.

Max.

Unit

Internal Clock Operation

SS1

SS2

(Tx/Rx) CK clock period

81.4

36.0

—

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Tx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

(Tx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

(Tx/Rx) Internal FS rise time

(Tx/Rx) Internal FS fall time

SS3

6

SS4

36.0

—

SS5

6

SS6

—

15.0

6

SS8

—

SS10

SS12

SS14

SS15

SS16

SS17

SS18

SS19

—

6

(Tx) CK high to STXD valid from high impedance

(Tx) CK high to STXD high/low

—

15.0

6

—

(Tx) CK high to STXD high impedance

STXD rise/fall time

—

Synchronous Internal Clock Operation

SS42

SS43

SS52

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

Loading

10.0

0

—

25

ns

pF

—

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4.9.22.2 SSI Receiver Timing with Internal Clock

Figure 93 depicts the SSI receiver timing with internal clock. Table 79 lists the timing parameters shown

in Figure 93.

SS1

SS3

SS5

SS4

SS2

AD1_TXC

(Output)

SS9

SS7

AD1_TXFS (bl)

(Output)

SS11

SS13

AD1_TXFS (wl)

(Output)

SS20

SS21

AD1_RXD

(Input)

SS51

SS50

SS47

SS49

SS3

SS48

AD1_RXC

(Output)

SS1

SS7

SS5

SS4

SS2

DAM1_T_CLK

(Output)

SS9

DAM1_T_FS (bl)

(Output)

SS11

SS13

DAM1_T_FS (wl)

(Output)

SS20

SS21

DAM1_RXD

(Input)

SS47

SS51

SS50

SS49

SS48

DAM1_R_CLK

(Output)

Figure 93. SSI Receiver with Internal Clock Timing Diagram

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Table 79. SSI Receiver with Internal Clock Timing Parameters

ID

Parameter

Internal Clock Operation

Min.

Max.

Unit

SS1

SS2

(Tx/Rx) CK clock period

81.4

36.0

—

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Rx) CK high to FS (bl) high

(Rx) CK high to FS (bl) low

(Rx) CK high to FS (wl) high

(Rx) CK high to FS (wl) low

SS3

6

SS4

36.0

—

SS5

6

SS7

—

15.0

—

SS9

—

SS11

SS13

SS20

SS21

—

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

10.0

0

—

Oversampling Clock Operation

SS47

SS48

SS49

SS50

SS51

Oversampling clock period

Oversampling clock high period

Oversampling clock rise time

Oversampling clock low period

Oversampling clock fall time

15.04

6

—

3

ns

—

6

—

3

—

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4.9.22.3 SSI Transmitter Timing with External Clock

Figure 94 depicts the SSI transmitter timing with external clock, and Table 80 lists the timing parameters.

SS22

SS23

SS25

SS26

SS24

AD1_TXC

(Input)

SS27

SS29

AD1_TXFS (bl)

(Input)

SS33

SS31

AD1_TXFS (wl)

(Input)

SS39

SS37

SS38

AD1_TXD

(Output)

SS45

SS44

AD1_RXD

(Input)

SS46

Note: SRXD Input in Synchronous mode only

SS22

SS26

SS25

SS24

SS23

DAM1_T_CLK

(Input)

SS29

SS27

DAM1_T_FS (bl)

(Input)

SS33

SS31

DAM1_T_FS (wl)

(Input)

SS39

SS37

SS38

DAM1_TXD

(Output)

SS45

SS44

DAM1_RXD

(Input)

SS46

Note: SRXD Input in Synchronous mode only

Figure 94. SSI Transmitter with External Clock Timing Diagram

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Table 80. SSI Transmitter with External Clock Timing Parameters

ID

Parameter

External Clock Operation

Min.

Max.

Unit

SS22

SS23

SS24

SS25

SS26

SS27

SS29

SS31

SS33

SS37

SS38

SS39

(Tx/Rx) CK clock period

81.4

36.0

—

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Tx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

(Tx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

6.0

—

36.0

—

6.0

15.0

—

–10.0

10.0

–10.0

10.0

—

15.0

—

(Tx) CK high to STXD valid from high impedance

(Tx) CK high to STXD high/low

15.0

—

(Tx) CK high to STXD high impedance

—

Synchronous External Clock Operation

SS44

SS45

SS46

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

SRXD rise/fall time

10.0

2.0

—

ns

6.0

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4.9.22.4 SSI Receiver Timing with External Clock

Figure 95 depicts the SSI receiver timing with external clock, and Table 81 lists the timing parameters.

SS22

SS26

SS25

SS24

SS23

AD1_TXC

(Input)

SS30

SS28

AD1_TXFS (bl)

(Input)

SS32

SS35

SS34

AD1_TXFS (wl)

(Input)

SS41

SS36

SS40

AD1_RXD

(Input)

SS22

SS24

SS26

SS25

SS23

DAM1_T_CLK

(Input)

SS30

SS28

DAM1_T_FS (bl)

(Input)

SS32

SS35

SS34

DAM1_T_FS (wl)

(Input)

SS41

SS36

SS40

DAM1_RXD

(Input)

Figure 95. SSI Receiver with External Clock Timing Diagram

Table 81. SSI Receiver with External Clock Timing Parameters

ID

Parameter

External Clock Operation

Min.

Max.

Unit

SS22

SS23

SS24

(Tx/Rx) CK clock period

81.4

36.0

—

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

6.0

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Table 81. SSI Receiver with External Clock Timing Parameters (continued)

ID

Parameter

Min.

Max.

Unit

SS25

SS26

SS28

SS30

SS32

SS34

SS35

SS36

SS40

SS41

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Rx) CK high to FS (bl) high

(Rx) CK high to FS (bl) low

(Rx) CK high to FS (wl) high

(Rx) CK high to FS (wl) low

(Tx/Rx) External FS rise time

(Tx/Rx) External FS fall time

36.0

—

6.0

15.0

—

ns

–10.0

10.0

–10.0

10.0

—

15.0

—

6.0

—

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

10.0

2.0

—

4.9.23 UART Electrical

This section describes the electrical information of the UART module.

4.9.23.1 UART RS-232 Serial Mode Timing

The following subsections give the UART transmit and receive timings in RS-232 serial mode.

4.9.23.1.11 UART Transmitter

Figure 96 depicts the transmit timing of UART in RS-232 serial mode, with 8 data bit/1 stop bit format.

Table 82 lists the UART RS-232 serial mode transmit timing characteristics.

Possible

UA1

Bit 3

Parity

Bit

Start

Bit

TXD

(output)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 4

Bit 5

Bit 6

Par Bit

UA1

Figure 96. UART RS-232 Serial Mode Transmit Timing Diagram

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Table 82. RS-232 Serial Mode Transmit Timing Parameters

ID

Parameter

Transmit Bit Time

Symbol

Min.

Max.

Units

1

UA1

t_Tbit

1/F_{baud_rate}

–

1/F_{baud_rate}

+

—

2

T

ref_clk

1

2

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

_{ref_clk}: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

T

4.9.23.1.12 UART Receiver

Figure 97 depicts the RS-232 serial mode receive timing, with 8 data bit/1 stop bit format. Table 83 lists

serial mode receive timing characteristics.

Possible

UA2

Parity

Bit

UA2

Bit 3

Bit

Start

Bit

RXD

(input)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 4

Bit 5

Bit 6

Par Bit

UA2

Figure 97. UART RS-232 Serial Mode Receive Timing Diagram

Table 83. RS-232 Serial Mode Receive Timing Parameters

ID

Parameter

Symbol

Min.

Max.

Units

Receive Bit Time¹

t_Rbit

1/F_{baud_rate}

–

1/F_{baud_rate}+

—

2

UA2

1/(16 × F_{baud_rate}

)

1/(16 × F_{baud_rate})

1

2

The UART receiver can tolerate 1/(16 × F_{baud_rate}) tolerance in each bit. But accumulation tolerance in one frame must not

exceed 3/(16 × F_{baud_rate}).

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency) ÷ 16.

4.9.23.2 UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode.

4.9.23.2.13 UART IrDA Mode Transmitter

Figure 98 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 84 lists

the transmit timing characteristics.

UA4

UA3

TXD

(output)

Start

Bit

STOP

BIT

Bit 0

Bit 1

Possible

Parity

Bit

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 98. UART IrDA Mode Transmit Timing Diagram

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Table 84. IrDA Mode Transmit Timing Parameters

ID

Parameter

Symbol

Min.

Max.

Units

1

UA3

Transmit bit time in IrDA mode

t_TIRbit

1/F_{baud_rate}

–

1/F_{baud_rate}+ T

—

ref_clk

2

T

ref_clk

UA4

Transmit IR pulse duration

t_TIRpulse(3/16) × (1/F_{baud_rate}) (3/16) × (1/F_{baud_rate}

– T + T

)

—

ref_clk

1

2

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

_{ref_clk}: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

T

4.9.23.2.14 UART IrDA Mode Receiver

Figure 99 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 85 lists the

receive timing characteristics.

UA6

UA5

RXD

(input)

Start

Bit

STOP

BIT

Bit 0

Bit 1

Possible

Parity

Bit

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Figure 99. UART IrDA Mode Receive Timing Diagram

Table 85. IrDA Mode Receive Timing Parameters

ID

Parameter

Symbol

Min.

Max.

Units

Receive bit time¹in IrDA mode

t_RIRbit

1/F_{baud_rate}

–

1/F_{baud_rate}

1/(16 × F_{baud_rate})

+

—

2

UA5

1/(16 × F_{baud_rate}

)

UA6

Receive IR pulse duration

t_RIRpulse

1.41 us

(5/16) × (1/F_{baud_rate}

)

—

1

2

The UART receiver can tolerate 1/(16 × F_{baud_rate}) tolerance in each bit. But accumulation tolerance in one frame must not

exceed 3/(16 × F_{baud_rate}).

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency) ÷ 16.

4.9.24 USB Electrical Specifications

In order to support four different serial interfaces, the USB serial transceiver can be configured to operate

in one of four modes:

•

DAT_SE0 bidirectional, 3-wire mode

DAT_SE0 unidirectional, 6-wire mode

VP_VM bidirectional, 4-wire mode

VP_VM unidirectional, 6-wire mode

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4.9.24.1 DAT_SE0 Bidirectional Mode

Table 86 defines the signals for DAT_SE0 bidirectional mode. Figure 100 and Figure 101 show the

transmit and receive waveforms respectively.

Table 86. Signal Definitions—DAT_SE0 Bidirectional Mode

Name

Direction

Signal Description

Out

USB_TXOE_B

Transmit enable, active low

Out

In

Tx data when USB_TXOE_B is low

Differential Rx data when USB_TXOE_B is high

USB_DAT_VP

USB_SE0_VM

Out

In

SE0 drive when USB_TXOE_B is low

SE0 Rx indicator when USB_TXOE_B is high

Transmit

US3

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US1

US4

US2

Figure 100. USB Transmit Waveform in DAT_SE0 Bidirectional Mode

Receive

USB_TXOE_B

USB_DAT_VP

US7

US8

USB_SE0_VM

Figure 101. USB Receive Waveform in DAT_SE0 Bidirectional Mode

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Table 87 describes the port timing specification in DAT_SE0 bidirectional mode.

Table 87. Port Timing Specification in DAT_SE0 Bidirectional Mode

No.

Parameter

Signal Name

Direction

Min. Max. Unit

Conditions/Reference Signal

US1 Tx rise/fall time

US2 Tx rise/fall time

US3 Tx rise/fall time

US4 Tx duty cycle

US7 Rx rise/fall time

US8 Rx rise/fall time

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Out

In

—

5.0

ns

%

50 pF

—

5.0

49.0

—

51.0

3.0

ns

35 pF

In

—

3.0

4.9.24.2 DAT_SE0 Unidirectional Mode

Table 88 defines the signals for DAT_SE0 unidirectional mode. Figure 102 and Figure 103 show the

transmit and receive waveforms respectively.

Table 88. Signal Definitions—DAT_SE0 Unidirectional Mode

Name

Direction

Signal Description

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

Out

In

Transmit enable, active low

Tx data when USB_TXOE_B is low

SE0 drive when USB_TXOE_B is low

Buffered data on DP when USB_TXOE_B is high

Buffered data on DM when USB_TXOE_B is high

Differential Rx data when USB_TXOE_B is high

USB_VM1

In

USB_RCV

In

Transmit

US11

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US9

US10

US12

Figure 102. USB Transmit Waveform in DAT_SE0 Unidirectional Mode

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Receive

USB_TXOE_B

USB_VP1

USB_RCV

US15/US17

US16

USB_VM1

Figure 103. USB Receive Waveform in DAT_SE0 Unidirectional Mode

Table 89 describes the port timing specification in DAT_SE0 unidirectional mode.

Table 89. USB Port Timing Specification in DAT_SE0 Unidirectional Mode

Signal

Source

Condition/

Reference Signal

No.

Parameter

Signal Name

Min.

Max.

Unit

US9

Tx rise/fall time

Tx duty cycle

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_VP1

Out

In

—

5.0

51.0

3.0

ns

%

50 pF

—

US10

US11

US12

US15

US16

US17

—

49.0

—

Rx rise/fall time

ns

35 pF

USB_VM1

In

—

USB_RCV

In

—

4.9.24.3 VP_VM Bidirectional Mode

Table 90 defines the signals for VP_VM bidirectional mode. Figure 104 and Figure 105 show the transmit

and receive waveforms respectively.

Table 90. Signal Definitions—VP_VM Bidirectional Mode

Name

USB_TXOE_B

Direction

Signal Description

Out

Transmit enable, active low

USB_DAT_VP

USB_SE0_VM

USB_RCV

Out (Tx)

In (Rx)

Tx VP data when USB_TXOE_B is low

Rx VP data when USB_TXOE_B is high

Out (Tx)

In (Rx)

Tx VM data when USB_TXOE_B low

Rx VM data when USB_TXOE_B high

In

Differential Rx data

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Transmit

US20

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US18

US21

US19

US22

Figure 104. USB Transmit Waveform in VP_VM Bidirectional Mode

Receive

US26

USB_DAT_VP

USB_SE0_VM

USB_RCV

US27

US28

US29

Figure 105. USB Receive Waveform in VP_VM Bidirectional Mode

Table 91 describes the port timing specification in VP_VM bidirectional mode.

Table 91. USB Port Timing Specification in VP_VM Bidirectional Mode

Condition/

Reference Signal

No.

Parameter

Signal Name

USB_DAT_VP

Direction

Min.

Max.

Unit

US18

US19

US20

US21

US22

US26

US27

Tx rise/fall time

Tx duty cycle

Tx overlap

Out

In

—

5.0

ns

%

50 pF

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_DAT_VP

USB_SE0_VM

—

5.0

50 pF

49.0

–3.0

—

51.0

+3.0

3.0

—

ns

USB_DAT_VP

35 pF

Rx rise/fall time

In

—

3.0

35 pF

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Table 91. USB Port Timing Specification in VP_VM Bidirectional Mode (continued)

Condition/

Reference Signal

No.

Parameter

Signal Name

Direction

Min.

Max.

Unit

US28

US29

Rx skew

USB_DAT_VP

USB_RCV

In

–4.0

–6.0

+4.0

+2.0

ns

USB_SE0_VM

USB_DAT_VP

4.9.24.4 VP_VM Unidirectional Mode

Table 92 defines the signals for VP_VM unidirectional mode. Figure 106 and Figure 107 show the

transmit and receive waveforms respectively.

Table 92. Signal Definitions—VP_VM Unidirectional Mode

Name

Direction

Signal Description

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

Out

In

Transmit enable, active low

Tx VP data when USB_TXOE_B is low

Tx VM data when USB_TXOE_B is low

Rx VP data when USB_TXOE_B is high

Rx VM data when USB_TXOE_B is high

Differential Rx data

USB_VM1

In

USB_RCV

In

Transmit

US32

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US30

US33

US31

US34

Figure 106. USB Transmit Waveform in VP_VM Unidirectional Mode

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129

Receive

USB_TXOE_B

USB_VP1

US38

USB_VM1

USB_RCV

US40

US39

US41

Figure 107. USB Receive Waveform in VP_VM Unidirectional Mode

Table 93 describes the port timing specification in VP_VM unidirectional mode.

Table 93. USB Timing Specification in VP_VM Unidirectional Mode

No.

Parameter

Signal

Direction

Out

In

Min. Max. Unit

Conditions/Reference Signal

Tx rise/fall time

USB_DAT_VP

US30

US31

US32

US33

US34

US38

US39

US40

US41

—

5.0

ns

%

50 pF

Tx rise/fall time

Tx duty cycle

Tx overlap

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

—

5.0

50 pF

49.0

–3.0

—

51.0

+3.0

3.0

—

ns

USB_DAT_VP

35 pF

Rx rise/fall time

Rx skew

USB_VM1

In

—

3.0

35 pF

USB_VP1

In

–4.0

–6.0

+4.0

+2.0

USB_VM1

USB_VP1

Rx skew

USB_RCV

In

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5 Package Information and Pinout

This section includes the following:

•

Mechanical package drawing

Pin/contact assignment information

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131

5.1

MAPBGA Production Package 1568-01, 17 × 17 mm, 0.8 Pitch

See Figure 108 for the package drawing and dimensions of the production package.

Figure 108. Production Package: Mechanical Drawing

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5.2

MAPBGA Signal Assignments

Table 94 and Table 95 list MAPBGA signals, alphabetized by signal name, for silicon revisions 2.0 and

2.1, respectively. Table 96 and Table 97 show the signal assignment on the i.MX35 ball map for silicon

revisions 2.0 and 2.1, respectively. The ball map for silicon revision 2.1 is different than the ballmap for

silicon revision 2.0. The layout for each revision is not compatible, so it is important that the correct

ballmap be used to implement the layout.

Table 94. Silicon Revision 2.0 Signal Ball Map Locations

Signal ID

Ball Location

Signal ID

Ball Location

A0

A5

D7

F15

D5

F6

ATA_DATA7¹

ATA_DATA8¹

ATA_DATA9¹

ATA_DIOR¹

ATA_DIOW¹

ATA_DMACK¹

ATA_DMARQ¹

ATA_INTRQ¹

ATA_IORDY¹

ATA_RESET_B¹

BCLK

Y3

U4

A1

A10

W3

A11

Y6

A12

W6

A13

A14

B3

V6

D14

D15

D13

D12

E11

D11

E7

T3

A15

V2

A16

U6

A17

T6

A18

E14

W10

U9

A19

BOOT_MODE0

BOOT_MODE1

CAPTURE

CAS

A2

A20

D10

E10

D9

E9

V12

E16

Y10

T10

V10

T12

L16

F17

E19

B20

C19

E18

F19

V16

T15

W16

V15

U14

Y16

U15

W17

V14

W15

Y15

A21

A22

CLK_MODE0

CLK_MODE1

CLKO

A23

A24

D8

E8

A25

COMPARE

CONTRAST¹

CS0

A3

C6

D6

B5

A4

A5

CS1

A6

C5

A4

CS2

A7

CS3

A8

B4

CS4

A9

A3

CS5

ATA_BUFF_EN¹

ATA_CS0¹

ATA_CS1¹

ATA_DA0¹

ATA_DA1¹

ATA_DA2¹

ATA_DATA0¹

ATA_DATA1¹

ATA_DATA10¹

ATA_DATA11¹

ATA_DATA12¹

T5

CSI_D10¹

CSI_D11¹

CSI_D12¹

CSI_D13¹

CSI_D14¹

CSI_D15¹

CSI_D8¹

V7

T7

R4

V1

R5

Y5

W5

V3

CSI_D9¹

CSI_HSYNC¹

CSI_MCLK¹

CSI_PIXCLK¹

Y2

U3

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Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)

Signal ID

Ball Location

Signal ID

Ball Location

ATA_DATA13¹

ATA_DATA14¹

ATA_DATA15¹

ATA_DATA2¹

ATA_DATA3

ATA_DATA4

ATA_DATA5

ATA_DATA6

CTS2

W2

W1

T4

CSI_VSYNC¹

CSPI1_MISO

CSPI1_MOSI

CSPI1_SCLK

CSPI1_SPI_RDY

CSPI1_SS0

CSPI1_SS1

CTS1

T14

V9

W9

W8

T8

V5

U5

Y4

Y8

W4

V4

U8

R3

G5

FEC_TDATA0

FEC_TDATA1

FEC_TDATA2

FEC_TDATA3

FEC_TX_CLK

FEC_TX_EN

FEC_TX_ERR

FSR

P5

D0

A2

M4

D1

D4

M5

D10

D2

L6

D11

E6

P4

D12

E3

T1

D13

F5

N4

D14

D1

K5

D15

E2

FST

J1

D2

B2

FUSE_VDD

FUSE_VSS

GPIO1_0

GPIO1_1

GPIO2_0

GPIO3_0

HCKR

P13

M11

T11

Y11

U11

V11

K2

D3

E5

D3_CLS¹

D3_DRDY¹

D3_FPSHIFT¹

D3_HSYNC¹

D3_REV¹

D3_SPL¹

D3_VSYNC¹

D4

L17

L20

L15

L18

M17

M18

M19

C3

HCKT

J5

I2C1_CLK

I2C1_DAT

I2C2_CLK

I2C2_DAT

LBA

M20

N17

L3

D5

B1

D6

D3

M1

D7

C2

D20

F20

G18

H20

J18

J16

J19

J17

J20

K14

K19

K18

K20

G17

K16

K17

K15

D8

C1

LD0¹

D9

E4

LD1¹

DE_B

W19

B19

D17

D16

C18

F18

F16

D19

V8

LD10¹

DQM0

LD11¹

DQM1

LD12¹

DQM2

LD13¹

DQM3

LD14¹

EB0

LD15¹

EB1

LD16¹

ECB

LD17¹

EXT_ARMCLK

EXTAL_AUDIO

EXTAL24M

FEC_COL

FEC_CRS

FEC_MDC

LD18¹

W20

T20

P3

LD19¹

LD2¹

LD20¹

N5

LD21¹

R1

LD22¹

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Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)

Signal ID

Ball Location

Signal ID

Ball Location

FEC_MDIO

FEC_RDATA0

FEC_RDATA1

FEC_RDATA2

FEC_RDATA3

FEC_RX_CLK

FEC_RX_DV

FEC_RX_ERR

MA10

P1

P2

LD23¹

LD3¹

L19

G16

G19

H16

H18

G20

H17

H19

G12

F13

F14

G14

P16

H14

J14

L14

M14

K6

N2

LD4¹

M3

N1

LD5¹

LD6¹

R2

LD7¹

T2

LD8¹

N3

LD9¹

C4

NVCC_EMI2

NVCC_EMI3

NVCC_JTAG

NVCC_LCDC

NVCC_MISC

NVCC_MLB

NVCC_NFC

NVCC_SDIO

OE

MGND

N11

W13

Y13

W12

P11

G3

MLB_CLK

MLB_DAT

MLB_SIG

MVDD

NF_CE0

NFALE

F2

NFCLE

E1

NFRB

F3

NFRE_B

F1

K7

NFWE_B

G2

L8

NFWP_B

F4

R10

G6

NGND_ATA

NGND_CRM

NGND_CSI

NGND_EMI1

NGND_EMI2

NGND_EMI3

NGND_JTAG

NGND_LCDC

NGND_MISC

NGND_MLB

NGND_NFC

NGND_SDIO

NVCC_ATA

NVCC_CRM

NVCC_CSI

M9

P9

H6

L10

L11

N10

H8

H7

P14

E20

V20

U19

T19

T18

M12

M15

N20

N16

P20

R13

P12

W11

Y9

OSC_AUDIO_VDD

OSC_AUDIO_VSS

OSC24M_VDD

OSC24M_VSS

PGND

H10

J10

J11

J12

K12

M13

K11

L12

M7

K8

PHY1_VDDA

PHY1_VSSA

PHY2_VDD

PHY2_VSS

POR_B

M10

K9

POWER_FAIL

PVDD

N12

N6

N13

E15

U10

U18

U1

RAS

P6

RESET_IN_B

RTCK

P7

P8

RTS1

R9

RTS2

G1

R11

RW

C20

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Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)

Signal ID

Ball Location

Signal ID

Ball Location

NVCC_EMI1

SD1_CLK

SD1_CMD

SD1_DATA0

SD1_DATA1

SD1_DATA2

SD1_DATA3

SD10

G7

G8

RXD1

RXD2

U2

H3

G9

SCK4

L4

H9

SCK5

L5

F10

G10

F11

G11

V18

Y19

R14

U16

W18

V17

A15

B15

C13

B14

A14

B13

C12

C11

A12

B12

B18

W14

U13

V13

T13

Y14

U12

B11

A11

C10

B10

A9

SCKR

K3

SCKT

J4

SD0

C17

A19

E12

E13

B17

A13

A10

C7

SD1

SDCLK

SDCLK_B

SDQS0

SDQS1

SDQS2

SDQS3

SDWE

G15

U17

L1

SD11

SJC_MOD

SRXD4

SD12

SD13

SRXD5

K4

SD14

STXD4

M2

K1

SD15

STXD5

SD16

STXFS4

L2

SD17

STXFS5

J6

SD18

TCK

R17

P15

R15

Y7

SD19

TDI

SD2

TDO

SD2_CLK

SD2_CMD

SD2_DATA0

SD2_DATA1

SD2_DATA2

SD2_DATA3

SD20

TEST_MODE

TMS

R16

T16

M16

G4

TRSTB

TTM_PIN

TX0

TX1

H1

TX2_RX3

TX3_RX2

TX4_RX1

TX5_RX0

TXD1

H5

SD21

J2

SD22

H4

SD23

J3

SD24

R6

SD25

C9

TXD2

H2

SD26

B9

USBOTG_OC

USBOTG_PWR

USBPHY1_DM

USBPHY1_DP

USBPHY1_RREF

USBPHY1_UID

USBPHY1_UPLLGND

USBPHY1_UPLLVDD

U7

SD27

A8

W7

N19

P19

R19

N18

N14

N15

P17

SD28

B8

SD29

C8

SD3

C16

A7

SD30

SD31

B7

SD4

A18

C15

SD5

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Table 94. Silicon Revision 2.0 Signal Ball Map Locations (continued)

Signal ID

Ball Location

Signal ID

Ball Location

SD6

SD7

A17

B16

C14

A16

A6

USBPHY1_VBUS

P18

R20

R18

Y17

Y18

M6

USBPHY1_VDDA_BIAS

SD8

USBPHY1_VSSA_BIAS

SD9

USBPHY2_DM

USBPHY2_DP

VDD

SDBA0

SDBA1

SDCKE0

SDCKE1

VDD

B6

D18

E17

L7

VDD

F7

VDD

J7

VSS

L9

VDD

N7

VSS

N9

VDD

R7

VSS

K10

P10

H11

H12

H13

J13

K13

L13

T17

A20

Y20

T9

VDD

F8

VSS

VDD

R8

VSS

VDD

F9

VSS

VDD

F12

R12

G13

H15

J15

A1

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

Y1

VSS

J8

VSTBY

WDOG_RST

XTAL_AUDIO

XTAL24M

VSS

M8

N8

Y12

V19

U20

VSS

J9

1

Not available for the MCIMX351.

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Table 95. Silicon Revision 2.1 Signal Ball Map Locations

Signal ID

Ball Location

Signal ID

Ball Location

A0

A1

A5

D7

F15

D5

F6

ATA_DATA7

ATA_DATA8

ATA_DATA9

ATA_DIOR

ATA_DIOW

ATA_DMACK

ATA_DMARQ

ATA_INTRQ

ATA_IORDY

ATA_RESET_B

SDQS0

Y3

U4

A10

W3

Y6

A11

A12

W6

V6

A13

B3

A14

D14

D15

D13

D12

E11

D11

E7

T3

A15

V2

A16

U6

A18

T6

SDQS1

A19

E14

W10

U9

BOOT_MODE0

BOOT_MODE1

CAPTURE

RAS

A2

A21

D10

E10

D9

E9

V12

E16

Y10

T10

V10

T12

L16

F17

E19

B20

C19

E18

F19

V16

T15

W16

V15

U14

Y16

U15

W17

V14

W15

Y15

T14

V9

SDQS2

A22

CLK_MODE0

CLK_MODE1

CLKO

SDQS3

A24

D8

E8

A25

COMPARE

CONTRAST

CS0

A3

C6

D6

B5

A4

A5

CS1

A6

C5

A4

CS2

A7

CS3

A8

B4

CS4

A9

A3

CS5

ATA_BUFF_EN¹

ATA_CS0

ATA_CS1

ATA_DA0

ATA_DA1

ATA_DA2

ATA_DATA0

ATA_DATA1

ATA_DATA10

ATA_DATA11

ATA_DATA12

ATA_DATA13

ATA_DATA14

ATA_DATA15

ATA_DATA2

ATA_DATA3

ATA_DATA4

ATA_DATA5

ATA_DATA6

T5

CSI_D10

V7

CSI_D11

T7

CSI_D12

R4

V1

CSI_D13

CSI_D14

R5

Y5

CSI_D15

CSI_D8

W5

V3

CSI_D9

CSI_HSYNC

CSI_MCLK

CSI_PIXCLK

CSI_VSYNC

CSPI1_MISO

CSPI1_MOSI

CSPI1_SCLK

CSPI1_SPI_RDY

CSPI1_SS0

CSPI1_SS1

CTS1

Y2

U3

W2

W1

T4

W9

W8

T8

V5

U5

Y4

Y8

W4

V4

U8

R3

i.MX35 Applications Processors for Automotive Products, Rev. 10

138

Freescale Semiconductor

Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)

Signal ID

Ball Location

Signal ID

Ball Location

CTS2

D0

G5

A2

FEC_TDATA0

FEC_TDATA1

FEC_TDATA2

FEC_TDATA3

FEC_TX_CLK

FEC_TX_EN

FEC_TX_ERR

FSR

P5

M4

D1

D4

M5

D10

D2

L6

D11

E6

P4

D12

E3

T1

D13

F5

N4

D14

D1

K5

D15

E2

FST

J1

D2

B2

FUSE_VDD

FUSE_VSS

GPIO1_0

GPIO1_1

GPIO2_0

GPIO3_0

HCKR

P13

M11

T11

Y11

U11

V11

K2

D3

E5

D3_CLS

D3_DRDY

D3_FPSHIFT

D3_HSYNC

D3_REV

D3_SPL

D3_VSYNC

D4

L17

L20

L15

L18

M17

M18

M19

C3

HCKT

J5

I2C1_CLK

I2C1_DAT

I2C2_CLK

I2C2_DAT

LBA

M20

N17

L3

D5

B1

D6

D3

M1

D7

C2

D20

F20

G18

H20

J18

J16

J19

J17

J20

K14

K19

K18

K20

G17

K16

K17

K15

L19

G16

G19

H16

H18

G20

H17

H19

D8

C1

LD0

D9

E4

LD1

DE_B

W19

B19

D17

D16

C18

F18

F16

D19

V8

LD10

DQM0

LD11

SDCKE1

DQM2

LD12

LD13

DQM3

LD14

EB0

LD15

EB1

LD16

ECB

LD17

EXT_ARMCLK

EXTAL_AUDIO

EXTAL24M

FEC_COL

FEC_CRS

FEC_MDC

FEC_MDIO

FEC_RDATA0

FEC_RDATA1

FEC_RDATA2

FEC_RDATA3

FEC_RX_CLK

FEC_RX_DV

FEC_RX_ERR

LD18

W20

T20

P3

LD19

LD2

LD20

N5

LD21

R1

LD22

P1

LD23

P2

LD3

N2

LD4

M3

N1

LD5

LD6

R2

LD7

T2

LD8

N3

LD9

i.MX35 Applications Processors for Automotive Products, Rev. 10

Freescale Semiconductor

139

Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)

Signal ID

Ball Location

Signal ID

Ball Location

MA10

C4

N11

W13

Y13

W12

P11

G3

NVCC_EMI2

VSS

G12

F13

F14

G14

P16

H14

J14

L14

M14

K6

MGND

MLB_CLK

MLB_DAT

NVCC_EMI3

NVCC_JTAG

NVCC_LCDC

NVCC_MISC

NVCC_MLB

NVCC_NFC

NVCC_SDIO

OE

MLB_SIG

MVDD

NF_CE0

NFALE

F2

NFCLE

E1

NFRB

F3

NFRE_B

F1

K7

NFWE_B

G2

L8

NFWP_B

F4

R10

G6

NGND_ATA

NGND_CRM

NGND_CSI

NGND_EMI1

NVCC_EMI1

NGND_EMI1

NGND_EMI2

NGND_EMI3

NGND_JTAG

NGND_LCDC

NGND_MISC

NGND_MLB

NGND_NFC

NGND_SDIO

NVCC_ATA

NVCC_CRM

NVCC_CSI

NVCC_EMI1

NGND_EMI1

NVCC_EMI1

M9

P9

H6

L10

L11

N10

H8

H7

P14

E20

V20

U19

T19

T18

M12

M15

N20

N16

P20

R13

P12

W11

Y9

OSC_AUDIO_VDD

OSC_AUDIO_VSS

OSC24M_VDD

OSC24M_VSS

PGND

H10

J10

J11

J12

K12

M13

K11

L12

M7

PHY1_VDDA

PHY1_VSSA

PHY2_VDD

PHY2_VSS

POR_B

K8

M10

K9

POWER_FAIL

PVDD

N12

N6

N13

E15

U10

U18

U1

BCLK

P6

RESET_IN_B

RTCK

P7

P8

RTS1

R9

RTS2

G1

R11

G7

RW

C20

U2

RXD1

G8

RXD2

H3

G9

SCK4

L4

H9

SCK5

L5

F10

G10

F11

G11

SCKR

K3

SCKT

J4

DQM1

C17

A19

SD1

i.MX35 Applications Processors for Automotive Products, Rev. 10

140

Freescale Semiconductor

Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)

Signal ID

Ball Location

Signal ID

Ball Location

SD1_CLK

SD1_CMD

SD1_DATA0

SD1_DATA1

SD1_DATA2

SD1_DATA3

SD10

V18

Y19

R14

U16

W18

V17

A15

B15

C13

B14

A14

B13

C12

C11

A12

B12

B18

W14

U13

V13

T13

Y14

U12

B11

A11

C10

B10

A9

SDCLK

SDCLK_B

SD0

E12

E13

B17

A13

A10

C7

SD15

SD23

A23

SDWE

G15

U17

L1

SD11

SJC_MOD

SRXD4

A17

SD13

SRXD5

K4

SD14

STXD4

M2

SD12

STXD5

K1

SD16

STXFS4

L2

SD17

STXFS5

J6

SD18

TCK

R17

P15

R15

Y7

SD19

TDI

SD2

TDO

SD2_CLK

SD2_CMD

SD2_DATA0

SD2_DATA1

SD2_DATA2

SD2_DATA3

SD20

TEST_MODE

TMS

R16

T16

M16

G4

TRSTB

TTM_PIN

TX0

TX1

H1

TX2_RX3

TX3_RX2

TX4_RX1

TX5_RX0

TXD1

H5

SD21

J2

A20

H4

SD22

J3

SD24

R6

SD25

C9

TXD2

H2

SD26

B9

USBOTG_OC

USBOTG_PWR

USBPHY1_DM

USBPHY1_DP

USBPHY1_RREF

USBPHY1_UID

USBPHY1_UPLLGND

USBPHY1_UPLLVDD

USBPHY1_VBUS

USBPHY1_VDDA_BIAS

USBPHY1_VSSA_BIAS

USBPHY2_DM

USBPHY2_DP

VDD

U7

SD27

A8

W7

N19

P19

R19

N18

N14

N15

P17

P18

R20

R18

Y17

Y18

M6

SD28

B8

SD29

C8

SD3

C16

A7

SD30

SD31

B7

SD4

A18

C15

A17

B16

C14

A16

A6

SD5

SD6

SD7

SD8

SD9

SDBA0

SDBA1

SDCKE0

CAS

B6

D18

E17

VDD

F7

VDD

J7

i.MX35 Applications Processors for Automotive Products, Rev. 10

Freescale Semiconductor

141

Table 95. Silicon Revision 2.1 Signal Ball Map Locations (continued)

Signal ID

Ball Location

Signal ID

Ball Location

VDD

VSS

L7

N7

R7

F8

VSS

L9

N9

VSS

K10

P10

H11

H12

H13

J13

K13

L13

T17

A20

Y20

T9

VSS

R8

F9

VSS

F12

R12

G13

H15

J15

A1

NVCC_EMI2

VSS

Y1

VSS

J8

VSTBY

WDOG_RST

XTAL_AUDIO

XTAL24M

M8

N8

J9

Y12

V19

U20

1

Not available for the MCIMX351.

i.MX35 Applications Processors for Automotive Products, Rev. 10

142

Freescale Semiconductor

1

Table 96. Silicon Revision 2.0 Ball Map—17 x 17, 0.8 mm Pitch

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A

B

C

D

E

VSS

D0

A9

A7

A0

SDB SD3 SD2 SD2 SDQ SD2 SD1 SDQ SD1 SD1 SD9 SD6 SD4 SD1 VSS

A0 S2 S1

A

B

C

D

E

0

7

4

1

8

4

0

D5

D8

D2

D7

A13

D4

A8

A5

A6

SDB SD3 SD2 SD2 SD2 SD2 SD1 SD1 SD1 SD1 SD7 SDQ SD2 DQM CS2

A1

1

8

6

3

0

9

5

3

1

S0

0

MA1

0

A3

SDQ SD2 SD2 SD2 SD1 SD1 SD1 SD8 SD5 SD3 SD0 DQM CS3 RW

S3

A1

9

5

2

7

6

2

3

D14 D10

D6

D1

A11

D3

A4

A24

A22

A20

A19

A17

A16

A14

A15 DQM DQM SDC ECB LBA

2

1

KE0

NFC D15 D12

LE

D9

D11

A2

A25

A23

A21

A18 SDC SDC BCL RAS CAS SDC CS4 CS1

OE

LK

LK_

B

K

KE1

F

G

H

J

NFR NFA NFR NFW D13 A12 VDD VDD VDD NVC NVC VDD NVC NVC A10 EB1 CS0 EB0 CS5 LD0

E_B LE P_B C_E C_E C_E C_E

MI1 MI1 MI2 MI2

F

G

H

J

B

RTS NFW NF_ TX0 CTS NVC NVC NVC NVC NVC NVC NVC VDD NVC SDW LD3 LD2 LD1 LD4 LD7

2

E_B CE0

2

C_N C_E C_E C_E C_E C_E C_E

FC MI1 MI1 MI1

MI1 MI1 MI2

C_E

MI3

E

TX1 TXD RXD TX4_ TX2_ NVC NVC NGN NVC NGN VSS VSS VSS NVC VDD LD5 LD8 LD6 LD9 LD10

2

RX1 RX3 C_N C_N D_E C_E D_E

C_L

CDC

FC FC MI1 MI1 MI1

FST TX3_ TX5_ SCK HCK STX VDD VSS VSS NGN NGN NGN VSS NVC VDD LD12 LD14 LD11 LD13 LD15

RX2 RX0

T

FS5

D_E D_E D_E

MI1 MI2 MI3

C_L

CDC

K

L

STX HCK SCK SRX FSR NVC NVC NGN NGN VSS NGN NGN VSS LD16 LD22 LD20 LD21 LD18 LD17 LD19

K

L

D5

R

D5

C_MI C_MI D_MI D_N

SC

SC SC FC

D_L D_E

CDC MI3

SRX STX I2C2 SCK SCK FEC VDD NVC VSS NGN NGN NGN VSS NVC D3_ CON D3_ D3_ LD23 D3_

D4

FS4 _CL

4

5

_TD

C_MI

D_A D_C D_L

C_L FPS TRA CLS HSY

DRD

K

ATA3

SC

TA RM CDC

CDC HIFT ST NC

Y

M

N

I2C2 STX FEC FEC FEC VDD NGN VSS NGN NGN FUS PGN NGN NVC PHY TTM D3_ D3_ D3_ I2C1

M

N

_DAT D4

_RD _TD _TD

ATA2 ATA1 ATA2

D_MI

SC

D_A D_M E_V

TA LB SS

D

D_JT C_L 1_V _PIN REV SPL VSY _CL

AG CDC DDA

NC

K

FEC FEC FEC FEC FEC NVC VDD VSS VSS NGN MGN NGN PVD USB USB PHY I2C1 USB USB PHY

_RD _RD _RX _TX_ _CR C_A

D_C

SI

D

D_S

DIO

D

PHY PHY 1_V _DAT PHY PHY 1_V

ATA3 ATA1 _ER ERR

R

S

TA

1_U 1_U SSA

PLL PLLV

1_UI 1_D DDA

D

M

GND DD

P

R

FEC FEC FEC FEC FEC NVC NVC NVC NGN VSS MVD PHY FUS NVC TDI NVC USB USB USB PHY

_MDI _RD _CO _TX_ _TD C_A C_A C_A D_A 2_V E_V C_S C_JT PHY PHY PHY 1_V

ATA0 CLK ATA0 TA TA TA TA SS DD DIO AG 1_U 1_V 1_D SSA

P

R

D

O

L

PLLV BUS

DD

P

FEC FEC CTS ATA_ ATA_ TXD VDD VDD NVC NVC NVC VDD PHY SD1 TDO TMS TCK USB USB USB

_MD _RX

1

DA0 DA2

1

C_C C_M C_C

RM LB SI

2_V _DAT

DD A0

PHY PHY PHY

1_V 1_R 1_V

SSA REF DDA

C

_CL

K

_BIA

S

_BIA

S

T

FEC FEC ATA_ ATA_ ATA_ ATA_ ATA_ CSPI VST CLK GPI COM SD2 CSI_ CSI_ TRS VSS OSC OSC EXT

_TX_ _RX DMA DATA BUF RES CS1 1_S BY _MO O1_ PAR _DAT VSY D11

TB 24M 24M AL24

DE1

A1 NC _VS _VD

T

EN

_DV

RQ

15

F_E ET_

PI_R

DY

0

E

M

N

B

S

D

U

RTS RXD ATA_ ATA_ ATA_ ATA_ USB CSPI BOO RES GPI SD2 SD2 CSI_ CSI_ SD1 SJC RTC OSC XTAL

U

1

DATA DATA DATA IOR OTG 1_S T_M ET_I O2_ _DAT _CM D14

D8 _DAT _MO

K

_AU 24M

12

8

3

DY

_OC

S1

ODE N_B

1

0

A3

D

A1

D

DIO_

VSS

i.MX35 Applications Processors for Automotive Products, Rev. 10

Freescale Semiconductor

143

1

Table 96. Silicon Revision 2.0 Ball Map—17 x 17, 0.8 mm Pitch (continued)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

V

W

Y

ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ EXT CSPI CLK GPI CAP SD2 CSI_ CSI_ CSI_ SD1 SD1 XTAL OSC

V

W

Y

DA1 INTR DATA DATA DATA DMA CS0 _AR 1_MI

O3_ TUR _DAT HSY D13 D10 _DAT _CL _AU _AU

O

Q

10

6

2

CK

MCL

K

SO

0

E

A0

NC

A3

K

DIO DIO_

VDD

ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ USB CSPI CSPI BOO POR MLB MLB SD2 CSI_ CSI_ CSI_ SD1 DE_ EXT

DATA DATA DATA DATA DATA DIO OTG 1_S 1_M T_M

14 13

_PW CLK OSI ODE

_B

_SIG _CL _CL MCL D12

D9 _DAT

A2

B

AL_

AUDI

O

9

5

1

W

K

R

0

VSS ATA_ ATA_ ATA_ ATA_ ATA_ TES CSPI POW CLK GPI

DATA DATA DATA DATA DIO T_M 1_S ER_ _MO O1_ OG_ _DAT _DAT PIXC D15 PHY PHY _CM

11

ODE S0 FAIL DE0

RST A2 LK 2_D 2_D

WD MLB SD2 CSI_ CSI_ USB USB SD1 VSS

7

4

0

R

1

D

M

P

1

See Table 95 for pins unavailable in the MCIMX351 SoC.

Table 97. Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A

B

GND

D0

A9

A7

A0

SDB SD30 SD27 SD24 SD23 SD21 SD18 SD15 SD14 SD10 SD9 SD6 SD4 SD1 GND

A0

A

B

C

D

E

F

D5

D8

D2

D7

A13

D4

A8

A5

A6

SDB SD31 SD28 SD26 SD22 SD20 SD19 SD12 SD13 SD11 SD7 SD0 SD2 DQM CS2

A1

0

C

D

E

F

MA1

0

A3

A23 SD29 SD25 A20 SD17 SD16 A17

SD8 SD5 SD3 DQM DQM CS3

RW

1

3

D14

D10

D6

D1

A11

D3

A4

A1

A2

A24

A22

A21

A19

A18

A16

A14

A15 DQM SDC SDC ECB LBA

KE1 KE0

2

NFC D15

LE

D12

D9

D11

A25 SDQ SDQ SDQ SDC SDC SDQ BCL RAS CAS CS4 CS1

S3 S2 S1 LK LK_B S0

OE

K

NFR NFAL NFR NFW D13

E_B P_B

A12 VDD VDD VDD GND NVC VDD NVC GND A10

EB1 CS0 EB0 CS5 LD0

E

B

7

C_E

MI1

7

C_E

MI2

G

H

J

RTS NFW NF_

E_B CE0

TX0 CTS NVC NVC NVC NVC NVC NVC NVC VDD NVC SDW LD3

LD2

LD8

LD1

LD6

LD4

LD7

G

H

J

2

C_N C_E C_E C_E C_E C_E C_E

FC MI1 MI1 MI1 MI1 MI1 MI2

6

C_E

MI3

E

TX1 TXD RXD TX4_ TX2_ NVC NVC GND NVC NVC GND GND NVC NVC VDD LD5

LD9 LD10

2

RX1 RX3 C_N C_N

C_E C_E

MI1 MI1

C_E C_L

MI2 CDC

5

FC FC

FST TX3_ TX5_ SCK HCK STX VDD GND GND GND GND GND GND NVC VDD LD12 LD14 LD11 LD13 LD15

RX2 RX0

T

FS5

1

C_L

5

CDC

K

L

STX HCK SCK SRX FSR NVC NVC GND GND GND GND GND GND LD16 LD22 LD20 LD21 LD18 LD17 LD19

D5 D5 C_MI C_MI

SC SC

K

L

R

SRX STX I2C2 SCK SCK FEC VDD NVC GND GND GND GND GND NVC D3_F CON D3_

D3_ LD23 D3_

D4

FS4 _CLK

4

5

_TDA

TA3

2

C_MI

SC

C_L PSHI TRA CLS HSY

CDC FT ST NC

DRD

Y

M

N

I2C2 STX FEC FEC FEC VDD GND GND GND GND FUS PGN GND NVC PHY TTM D3_ D3_S D3_V I2C1

M

N

_DAT

D4

_RD _TDA _TDA

ATA2 TA1 TA2

2

E_V

SS

D

C_L 1_VD _PAD REV

CDC DA

PL

SYN _CLK

C

FEC FEC FEC FEC FEC NVC VDD GND GND GND MGN GND PVD USB USB PHY I2C1 USB USB PHY

_RD _RD _RX_ _TX_ _CR C_AT PHY PHY 1_VS _DAT PHY PHY 1_VD

ATA3 ATA1 ERR ERR

3

D

S

A

1_UP 1_UP SA

LLG LLVD

1_UI 1_D

DA

D

M

ND

D

i.MX35 Applications Processors for Automotive Products, Rev. 10

144

Freescale Semiconductor

Table 97. Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch (continued)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

P

R

FEC FEC FEC FEC FEC NVC NVC NVC GND GND MVD PHY FUS NVC

_MDI _RD _CO _TX_ _TDA C_AT C_AT C_AT 2_VS E_V C_S

ATA0 CLK TA0 DD DIO

TDI

NVC USB USB USB PHY

C_JT PHY PHY PHY 1_VS

AG 1_UP 1_VB 1_DP SA

P

R

D

O

L

A

S

LLVD

D

US

FEC FEC CTS ATA_ ATA_ TXD VDD VDD NVC NVC NVC VDD PHY SD1_ TDO TMS TCK USB USB USB

_MD _RX_

1

DA0 DA2

1

3

C_C C_M C_C

RM LB SI

4

2_VD DATA

PHY PHY PHY

1_VS 1_R 1_VD

SA_ REF DA_

C

CLK

D

0

BIAS

T

U

V

FEC FEC ATA_ ATA_ ATA_ ATA_ ATA_ CSPI VST CLK_ GPIO COM SD2_ CSI_ CSI_ TRS GND OSC OSC EXTA

T

U

V

_TX_ _RX_ DMA DATA BUF RES CS1 1_SP BY

MOD 1_0

E1

PAR DATA VSY D11

NC

TB

24M_ 24M_ L24M

VSS VDD

EN

DV

RQ

15

F_E ET_B

N

I_RD

Y

E

1

RTS RXD ATA_ ATA_ ATA_ ATA_ USB CSPI BOO RES GPIO SD2_ SD2_ CSI_ CSI_ SD1_ SJC_ RTC OSC XTAL

1

DATA DATA DATA IORD OTG 1_SS T_M ET_I 2_0 DATA CMD D14

D8

DATA MOD

1

K

_AU 24M

DIO_

12

8

3

Y

_OC

1

ODE N_B

3

1

VSS

ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ EXT_ CSPI CLK GPIO CAP SD2_ CSI_ CSI_ CSI_ SD1_ SD1_ XTAL OSC

DA1 INTR DATA DATA DATA DMA CS0 ARM 1_MI

3_0 TUR DATA HSY D13 D10 DATA CLK _AU _AU

10 CK

CLK SO

NC

O

Q

6

2

E

0

3

DIO DIO_

VDD

W

Y

ATA_ ATA_ ATA_ ATA_ ATA_ ATA_ USB CSPI CSPI BOO POR MLB MLB SD2_ CSI_ CSI_ CSI_ SD1_ DE_ EXTA

W

Y

DATA DATA DATA DATA DATA DIO OTG 1_SC 1_M T_M

_B

_SIG _CLK CLK MCL D12

K

D9

DATA

2

B

L_AU

DIO

14

13

9

5

1

W

_PW

R

LK

OSI ODE

0

GND ATA_ ATA_ ATA_ ATA_ ATA_ TES CSPI POW CLK_ GPIO WDO MLB SD2_ CSI_ CSI_ USB USB SD1_ GND

DATA DATA DATA DATA DIOR T_M 1_SS ER_ MOD 1_1 G_R _DAT DATA PIXC D15 PHY PHY CMD

11

7

4

0

ODE

0

FAIL

E0

ST

2

LK

2_D 2_DP

M

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

6 Product Documentation

All related product documentation for the i.MX35 processor is located at http://www.freescale.com/imx.

i.MX35 Applications Processors for Automotive Products, Rev. 10

Freescale Semiconductor

145

7 Revision History

Table 98 shows the revision history of this document. Note: There were no revisions of this document

between revision 1 and revision 4 or between revision 6 and revision 7.

Table 98. i.MX35 Data Sheet Revision History

Revision

Number

Date

Substantive Change(s)

10

06/2012

• In Table 2, "Functional Differences in the i.MX35 Parts," on page 4, added two columns for part

numbers MCIMX353 and MCIMX357.

• Added Table 29, "Clock Input Tolerance," on page 32 in Section 4.9.3, “DPLL Electrical

Specifications.”

• Updated Table 39, "DDR2 SDRAM Timing Parameter Table," on page 51 for DDR2-400 values.

• Updated Table 41, "DDR2 SDRAM Write Cycle Parameters," on page 53 for DDR2-400 values.

• Added Table 15, "AC Requirements of I/O Pins," on page 25.

• Updated WE4 parameter in Table 33, "WEIM Bus Timing Parameters," on page 38.

9

8

6

08/2010

04/2010

• Updated Table 32, “NFC Timing Parameters.”

• Updated Table 33, “WEIM Bus Timing Parameters.”

• Updated Table 1, “Ordering Information.”

• Updated Table 14, “I/O Pin DC Electrical Characteristics.”

10/21/2009 • Added information for silicon rev. 2.1

• Updated Table 1, “Ordering Information.”

• Added Table 95, “Silicon Revision 2.1 Signal Ball Map Locations.”

• Added Table 97, “Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch.”

5

4

08/06/2009 • Filled in TBDs in Table 14.

• Revised Figure 15 and Table 33 by removing FCE = 0 and FCE = 1. Added footnote 3 to the table.

• Added Table 26, “AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive

(1.8 V).”

04/30/2009 Note: There were no revisions of this document between revision 1 and revision 4.

• In Section 4.3.1, “Powering Up,” reverse positions of steps 5 and 6.

• Updated values in Table 10, “i.MX35 Power Modes.”

• Added Section 4.4, “Reset Timing.”

• In Section 4.8.2, “AC Electrical Characteristics for DDR Pins (DDR2, Mobile DDR, and SDRAM

Modes),” removed Slow Slew rate tables, relabeled Table 24, “AC Electrical Characteristics of DDR

Type IO Pins in mDDR Mode,” and Table 25, “AC Electrical Characteristics of DDR Type IO Pins in

SDRAM Mode,” to exclude mention of slew rate.

• In Section 4.9.5.2, “Wireless External Interface Module (WEIM),” modified Figure 16, “Synchronous

Memory Timing Diagram for Read Access—WSC = 1,” through Figure 21, “Muxed A/D Mode Timing

Diagram for Synchronous Read Access— WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7.”

• In Section 4.9.6, “Enhanced Serial Audio Interface (ESAI) Timing Specifications,” modified

Figure 36, “ESAI Transmitter Timing,” and Figure 37, “ESAI Receiver Timing,” to remove extraneous

signals. Removed a note from Figure 36, “ESAI Transmitter Timing.”

1

0

12/2008

• Updated Section 4.3.1, “Powering Up.”

• Section 4.7, “Module-Level AC Electrical Specifications”: Updated NFC, SDRAM and mDDR

SDRAM timing. Inserted DDR2 SDRAM timing.

10/2008 Initial public release

i.MX35 Applications Processors for Automotive Products, Rev. 10

146

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Document Number: MCIMX35SR2AEC

Rev. 10

06/2012


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