935314766557 [NXP]
Microcontroller;
| 型号： | 935314766557 |
| 厂家： | 
NXP |
| 描述： | Microcontroller 微控制器 外围集成电路 |
| 文件： | 总65页 (文件大小：1248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number MCF51QU128
Rev. 5, 03/2015
Freescale Semiconductor
Data Sheet: Technical Data
MCF51QU128
MCF51QU128
Supports the MCF51QU128VLH,
MCF51QU128VHS, MCF51QU64VLF,
MCF51QU64VHS, MCF51QU32VHS,
MCF51QU32VFM
Features
• Security and integrity
– Hardware CRC module to support fast cyclic
redundancy checks
– 128-bit unique identification (ID) number per chip
• Operating characteristics
– Voltage range: 1.71 V to 3.6 V
– Flash write voltage range: 1.71 V to 3.6 V
– Temperature range (ambient): -40°C to 105°C
• Analog
– 12-bit SAR ADC
– 12-bit DAC
– Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
– Voltage reference (VREF)
• Core
– Up to 50 MHz V1 ColdFire CPU
– Dhrystone 2.1 performance: 1.10 DMIPS per MHz
when executing from internal RAM, 0.99 DMIPS
per MHz when executing from flash memory
• Timers
• System
– Programmable delay block (PDB)
– Motor control/general purpose/PWM timers (FTM)
– 16-bit low-power timers (LPTMRs)
– 16-bit modulo timer (MTIM)
– DMA controller with four programmable channels
– Integrated ColdFire DEBUG_Rev_B+ interface with
single-wire BDM connection
• Power management
– Carrier modulator transmitter (CMT)
– 10 low power modes to provide power optimization
based on application requirements
– Low-leakage wakeup unit (LLWU)
– Voltage regulator (VREG)
• Communication interfaces
– UARTs with Smart Card support and FIFO
– SPI modules, one with FIFO
– Inter-Integrated Circuit (I2C) modules
• Clocks
• Human-machine interface
– Crystal oscillators (two, each with range options): 1
kHz to 32 kHz (low), 1 MHz to 8 MHz (medium), 8
MHz to 32 MHz (high)
– Up to 48 EGPIO pins
– Up to 16 rapid general purpose I/O (RGPIO) pins
– Low-power hardware touch sensor interface (TSI)
– Interrupt request pin (IRQ)
– Multipurpose clock generator (MCG)
• Memories and memory interfaces
– Flash memory, FlexNVM, FlexRAM, and RAM
– Serial programming interface (EzPort)
– Mini-FlexBus external bus interface
© 2010–2015 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts.......................................................................................3
5.4 Thermal specifications.................................................................20
5.4.1 Thermal operating requirements.................................... 20
5.4.2 Thermal attributes.......................................................... 20
6 Peripheral operating requirements and behaviors................................ 21
6.1 Core modules............................................................................... 21
6.1.1 Debug specifications...................................................... 21
6.2 System modules........................................................................... 21
6.2.1 VREG electrical specifications...................................... 21
6.3 Clock modules............................................................................. 22
6.3.1 MCG specifications........................................................22
6.3.2 Oscillator electrical specifications................................. 24
6.4 Memories and memory interfaces................................................26
6.4.1 Flash electrical specifications........................................ 26
6.4.2 EzPort Switching Specifications....................................29
6.4.3 Mini-Flexbus Switching Specifications......................... 30
6.5 Security and integrity modules.................................................... 33
6.6 Analog..........................................................................................34
6.6.1 ADC electrical specifications.........................................34
6.6.2 CMP and 6-bit DAC electrical specifications................37
6.6.3 12-bit DAC electrical characteristics............................. 39
6.6.4 Voltage reference electrical specifications.....................42
6.7 Timers.......................................................................................... 43
6.8 Communication interfaces........................................................... 44
6.8.1 SPI switching specifications.......................................... 44
6.9 Human-machine interfaces (HMI)...............................................47
6.9.1 TSI electrical specifications........................................... 47
7 Dimensions...........................................................................................48
7.1 Obtaining package dimensions.................................................... 48
8 Pinout................................................................................................... 49
8.1 Signal Multiplexing and Pin Assignments...................................49
8.2 Pinout diagrams........................................................................... 51
8.3 Module-by-module signals.......................................................... 55
9 Revision History...................................................................................64
1.1 Determining valid orderable parts............................................... 3
2 Part identification................................................................................. 3
2.1 Description...................................................................................3
2.2 Format..........................................................................................3
2.3 Fields............................................................................................3
2.4 Example....................................................................................... 4
3 Terminology and guidelines.................................................................4
3.1 Definition: Operating requirement...............................................4
3.2 Definition: Operating behavior....................................................4
3.3 Definition: Attribute.................................................................... 5
3.4 Definition: Rating........................................................................ 5
3.5 Result of exceeding a rating.........................................................6
3.6 Relationship between ratings and operating requirements.......... 6
3.7 Guidelines for ratings and operating requirements......................6
3.8 Definition: Typical value.............................................................7
4 Ratings..................................................................................................8
4.1 Thermal handling ratings.............................................................8
4.2 Moisture handling ratings............................................................ 8
4.3 ESD handling ratings...................................................................8
4.4 Voltage and current operating ratings..........................................8
5 General................................................................................................. 9
5.1 Typical Value Conditions............................................................ 9
5.2 Nonswitching electrical specifications........................................ 9
5.2.1 Voltage and Current Operating Requirements...............9
5.2.2 LVD and POR operating requirements..........................10
5.2.3 Voltage and current operating behaviors....................... 11
5.2.4 Power mode transition operating behaviors...................12
5.2.5 Power consumption operating behaviors....................... 12
5.2.6 EMC radiated emissions operating behaviors................16
5.2.7 Designing with radiated emissions in mind................... 17
5.2.8 Capacitance attributes.................................................... 17
5.3 Switching electrical specifications...............................................17
5.3.1 General Switching Specifications.................................. 18
MCF51QU128, Rev. 5, 03/2015
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Freescale Semiconductor, Inc.
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device:
1. Go to www.freescale.com.
2. Perform a part number search for the following partial device numbers: PCF51QU
and MCF51QU.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q CCCC DD MMM T PP
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Qualification status
Values
Q
• M = Fully qualified, general market
flow
• P = Prequalification
CCCC
DD
Core code
CF51 = ColdFire V1
JF, JU, QF, QH, QM, QU
• 32 = 32 KB
Device number
Memory size (program flash memory)1
MMM
Table continues on the next page...
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Terminology and guidelines
Field
Description
Values
• 64 = 64 KB
• 128 = 128 KB
V = –40 to 105
T
Temperature range, ambient (°C)
Package identifier
PP
• FM = 32 QFN (5 mm x 5 mm)
• HS = 44 Laminate QFN (5 mm x 5
mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
1. All parts also have FlexNVM, FlexRAM, and RAM.
2.4 Example
This is an example part number:
MCF51QU128VLH
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
3.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values
for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
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Terminology and guidelines
3.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
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Terminology and guidelines
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
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Terminology and guidelines
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
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Ratings
4 Ratings
4.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
260
245
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
Solder temperature, leaded
1
2
TSDR
°C
—
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
VHBM
VCDM
ILAT
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 105°C
1
2
3
V
-100
+100
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
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General
Unit
Symbol
VDD
IDD
Description
Min.
–0.3
—
Max.
3.8
Digital supply voltage
V
mA
V
Digital supply current
120
VDIO
VAIO
ID
Digital input voltage (except RESET, EXTAL, and XTAL)
Analog, RESET, EXTAL, and XTAL input voltage
–0.3
–0.3
–25
VDD + 0.3
VDD + 0.3
25
V
Instantaneous maximum current single pin limit (applies to all
port pins)
mA
VDDA
Analog supply voltage
Regulator input
VDD – 0.3
–0.3
VDD + 0.3
6.0
V
V
VREGIN
5 General
5.1 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
5.2 Nonswitching electrical specifications
5.2.1 Voltage and Current Operating Requirements
Table 1. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
Max.
3.6
3.6
0.1
0.1
—
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
1.71
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
V
–0.1
V
VIH
Input high voltage
0.7 × VDD
0.75 × VDD
V
1
2
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
V
VIL
Input low voltage
—
0.35 × VDD
V
Table continues on the next page...
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Nonswitching electrical specifications
Table 1. Voltage and current operating requirements (continued)
Symbol
Description
• 2.7 V ≤ VDD ≤ 3.6 V
Min.
Max.
Unit
Notes
—
0.3 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
IIC
DC injection current — single pin
• VIN > VDD
0
0
2
mA
mA
3
–0.2
• VIN < VSS
DC injection current — total MCU limit, includes sum of
all stressed pins
• VIN > VDD
0
0
25
–5
mA
mA
3
• VIN < VSS
VRAM
VDD voltage required to retain RAM
1.2
—
V
1. The device always interprets an input as a 1 when the input is greater than or equal to VIH (min.) and less than or equal to
VIH (max.), regardless of whether input hysteresis is turned on.
2. The device always interprets an input as a 0 when the input is less than or equal to VIL (max.) and greater than or equal to
VIL (min.), regardless of whether input hysteresis is turned on.
3. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified.
To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp
voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during
instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the
injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external
VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not
consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall
power consumption).
5.2.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
Falling low-voltage detect threshold — low range
(LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
1
VLVW1L
1.74
1.80
1.86
V
Table continues on the next page...
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Nonswitching electrical specifications
Table 2. LVD and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VLVW2L
VLVW3L
VLVW4L
• Level 1 falling (LVWV=00)
1.84
1.90
1.96
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
1.94
2.04
2.00
2.10
2.06
2.16
V
V
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
Internal low power oscillator period
factory trimmed
0.97
900
1.00
1.03
V
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
5.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = - 9 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
VOL
Output high current total for all ports
Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3 mA
—
100
mA
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6 mA
—
—
0.5
0.5
V
V
IOLT
IIN
Output low current total for all ports
Input leakage current (per pin)
• @ full temperature range
• @ 25 °C
—
100
mA
—
—
1.0
0.1
μA
μA
1
IOZ
IOZ
Hi-Z (off-state) leakage current (per pin)
Total Hi-Z (off-state) leakage current (all input pins)
Internal pullup resistors
—
—
22
22
1
4
μA
μA
kΩ
kΩ
RPU
RPD
50
50
2
3
Internal pulldown resistors
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Nonswitching electrical specifications
1. Tested by ganged leakage method
2. Measured at Vinput = VSS
3. Measured at Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx-RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 50 MHz
• Bus clock (and flash and Mini-FlexBus clocks) = 25 MHz
Table 4. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
—
300 1.71
V/(VDD slew
rate)
μs
1
• 1.71 V/(VDD slew rate) ≤ 300 μs
• 1.71 V/(VDD slew rate) > 300 μs
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
1, 2
1, 2
1, 2
2
—
—
—
—
—
—
132
92
μs
μs
μs
μs
μs
μs
92
7.5
5.5
5.5
• VLPS → RUN
• STOP → RUN
2
2
1. Normal boot (FTFL_FOPT[LPBOOT] is 1)
2. The wakeup time includes the execution time for a small amount of firmware used to produce a GPIO clear event. Wakeup
time is measured from the falling edge of the external wakeup event to the falling edge of a GPIO clear performed by
software.
5.2.5 Power consumption operating behaviors
Table 5. Power consumption operating behaviors
Symbol
IDDA
Description
Min.
Typ.
Max.
Unit
Notes
Analog supply current
—
—
See note
mA
1
2
IDD_RUN
Run mode current — all peripheral clocks
disabled, code executing from RAM
—
—
13
13
—
mA
mA
16
• @ 1.8 V
• @ 3.0 V
Table continues on the next page...
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Nonswitching electrical specifications
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_RUN
Run mode current — all peripheral clocks
disabled, code executing from flash memory with
page buffering disabled
2
—
—
14.3
14.5
—
mA
mA
17.9
• @ 1.8 V
• @ 3.0 V
IDD_RUN
Run mode current — all peripheral clocks
enabled, code executing from RAM, exercising
flash memory
3
4
—
—
20
20
23.5
25
mA
mA
• @ 1.8 V
• @ 3.0 V
IDD_WAIT
IDD_STOP
Wait mode current at 3.0 V — all peripheral
clocks disabled
—
5.8
6.8
mA
Stop mode current at 3.0 V
• @ –40 to 25 °C
—
—
0.34
0.90
0.41
1.8
mA
mA
• @ 105 °C
IDD_VLPR
IDD_VLPR
Very low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
—
—
0.63
0.78
0.15
1.32
1.46
0.62
mA
mA
5
6
Very low-power run mode current at 3.0 V — all
peripheral clocks enabled
IDD_VLPW
IDD_VLPS
Very low-power wait mode current at 3.0 V
mA
μA
7
8
Very low-power stop mode current at 3.0 V
• @ –40 to 25 °C
—
—
19
45
145
312
• @ 105 °C
IDD_LLS
IDD_VLLS3
IDD_VLLS2
IDD_VLLS1
IDD_RTC
Low leakage stop mode current at 3.0 V
• @ –40 to 25 °C
8,9,10
8,9,10
8,9
—
—
3.0
4.8
μA
μA
53.3
157
• @ 105 °C
Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25 °C
—
—
1.8
3.3
μA
μA
39.2
115
• @ 105 °C
Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25 °C
—
—
1.6
2.8
65
μA
μA
22.2
• @ 105 °C
Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25 °C
8,9
—
—
1.4
2.6
50
μA
μA
17.6
• @ 105 °C
Average current adder for real-time clock function
• @ –40 to 25 °C
11
—
0.7
—
μA
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Nonswitching electrical specifications
1. The analog supply current is the sum of the active current for each of the analog modules on the device. See each
module's specification for its supply current.
2. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks disabled.
3. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, but
peripherals are not in active operation.
4. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode.
5. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing from flash memory.
6. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks enabled, but
peripherals are not in active operation. Code executing from flash memory.
7. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks disabled.
8. OSC clocks disabled.
9. All pads disabled.
10. Data reflects devices with 32 KB of RAM. For devices with 16 KB of RAM, power consumption is reduced by 500 nA. For
devices with 8 KB of RAM, power consumption is reduced by 750 nA.
11. RTC function current includes LPTMR with OSC enabled with 32.768 kHz crystal at 3.0 V
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode, except for 50 MHz core (FEI mode)
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL
• For the ALLON curve, all peripheral clocks are enabled, but peripherals are not in
active operation
• Voltage Regulator disabled
• No GPIOs toggled
• Code execution from flash memory with cache enabled
MCF51QU128, Rev. 5, 03/2015
14
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Figure 1. Run mode supply current vs. core frequency
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
15
Nonswitching electrical specifications
Figure 2. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 6. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
20
19
17
16
L
dBμV
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
—
2, 3
MCF51QU128, Rev. 5, 03/2015
16
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and
Definitions, and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated
Emissions—TEM Cell and Wideband TEM Cell Method.
2. VDD = 3 V, TA = 25 °C, fOSC = 32 kHz (crystal), fBUS = 24 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated
Emissions—TEM Cell and Wideband TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 7. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
5.3 Switching electrical specifications
Table 8. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
50
25
25
25
MHz
MHz
MHz
MHz
FB_CLK Mini-FlexBus clock
1
fLPTMR
LPTMR clock
VLPR mode
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
2
1
MHz
MHz
MHz
MHz
FB_CLK Mini-FlexBus clock
fLPTMR
LPTMR clock2
1
1
25
1. When the Mini-FlexBus is enabled, its clock frequency is always the same as the bus clock frequency.
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
17
Nonswitching electrical specifications
2. A maximum frequency of 25 MHz for the LPTMR in VLPR mode is possible when the LPTMR is configured for pulse
counting mode and is driven externally via the LPTMR_ALT1, LPTMR_ALT2, or LPTMR_ALT3 pin.
5.3.1 General Switching Specifications
These general purpose specifications apply to all signals configured for EGPIO, MTIM,
CMT, PDB, IRQ, and I2C signals. The conditions are 50 pf load, VDD = 1.71 V to 3.6 V,
and full temperature range. The GPIO are set for high drive, no slew rate control, and no
input filter, digital or analog, unless otherwise specified.
Table 9. EGPIO General Control Timing
Symbol
G1
Description
Min.
Max.
Unit
Bus clock from CLK_OUT pin high to GPIO output valid
—
1
32
—
ns
ns
G2
Bus clock from CLK_OUT pin high to GPIO output invalid
(output hold)
G3
G4
GPIO input valid to bus clock high
28
—
—
4
ns
ns
Bus clock from CLK_OUT pin high to GPIO input invalid
GPIO pin interrupt pulse width (digital glitch filter disabled)
Synchronous path1
1.5
—
Bus
clock
cycles
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter enabled)
100
50
—
—
ns
ns
ns
Asynchronous path2
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter disabled)
Asynchronous path2
External reset pulse width (digital glitch filter disabled)
Mode select (MS) hold time after reset deassertion
100
2
—
—
Bus
clock
cycles
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
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Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Bus clock
G1
G2
Data outputs
Data inputs
G3
G4
Figure 3. EGPIO timing diagram
The following general purpose specifications apply to all signals configured for RGPIO,
FTM, and UART. The conditions are 25 pf load, VDD = 3.6 V to 1.71 V, and full
temperature range. The GPIO are set for high drive, no slew rate control, and no input
filter, digital or analog, unless otherwise specified.
Table 10. RGPIO General Control Timing
Symbol
R1
Description
Min.
Max.
Unit
CPUCLK from CLK_OUT pin high to GPIO output valid
—
1
16
—
ns
ns
R2
CPUCLK from CLK_OUT pin high to GPIO output invalid
(output hold)
R3
R4
GPIO input valid to bus clock high
17
—
—
2
ns
ns
CPUCLK from CLK_OUT pin high to GPIO input invalid
Bus clock
R1
R2
Data outputs
R3
R4
Data inputs
Figure 4. RGPIO timing diagram
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
19
Thermal specifications
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
115
Unit
°C
Die junction temperature
Ambient temperature
TA
105
°C
5.4.2 Thermal attributes
Board type Symbol
Description
64 LQFP 48 LQFP
44
32 QFN Unit Notes
Laminate
QFN
Single-layer RθJA
(1s)
Thermal resistance, junction to
ambient (natural convection)
73
79
55
66
48
34
108
98
33
81
28
13
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
2
Four-layer
(2s2p)
RθJA
Thermal resistance, junction to
ambient (natural convection)
54
61
48
37
69
91
63
44
Single-layer RθJMA
(1s)
Thermal resistance, junction to
ambient (200 ft./min. air speed)
Four-layer
(2s2p)
RθJMA
Thermal resistance, junction to
ambient (200 ft./min. air speed)
—
RθJB
Thermal resistance, junction to
board
—
—
RθJC
Thermal resistance, junction to case 20
20
31
2.2
6.0
°C/W
°C/W
3
4
ΨJT
Thermal characterization parameter, 5.0
junction to package top outside
center (natural convection)
4.0
6.0
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions
—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air).
MCF51QU128, Rev. 5, 03/2015
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug specifications
Table 12. Background debug mode (BDM) timing
Number
Symbol
tMSSU
Description
Min.
Max.
Unit
1
2
BKGD/MS setup time after issuing background
debug force reset to enter user mode or BDM
500
—
—
ns
µs
tMSH
BKGD/MS hold time after issuing background
debug force reset to enter user mode or BDM1
100
1. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after
VDD rises above VLVD
.
6.2 System modules
6.2.1 VREG electrical specifications
Table 13. VREG electrical specifications
Symbol Description
Min.
2.7
—
Typ.1
Max.
5.5
Unit
V
Notes
VREGIN Input supply voltage
—
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
120
186
μA
Quiescent current — Standby mode, load current
equal zero
—
1.1
10
μA
Quiescent current — Shutdown mode
—
—
650
—
—
4
nA
μA
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
3.6
3.6
V
V
• Standby mode
2.1
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
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21
Clock modules
Table 13. VREG electrical specifications (continued)
Symbol Description
Min.
Typ.1
Max.
Unit
Notes
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.1
—
3.6
V
2
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Short circuit current
—
290
—
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
6.3 Clock modules
6.3.1 MCG specifications
Table 14. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed
31.25
—
—
38.214
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
%fdco
1
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
0.2
0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
10
—
%fdco
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
1.0
4.5
fintf_ft
fintf_t
floc_low
floc_high
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3
3.3
—
—
—
4
5
MHz
MHz
kHz
kHz
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
ffll_ref
FLL reference frequency range
31.25
—
39.0625
kHz
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
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Clock modules
Table 14. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20
20.97
25
MHz
2, 3
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
4, 5
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
—
180
150
—
—
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
6
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
100
—
MHz
µA
PLL operating current
7
7
1060
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 48)
=
=
Ipll
PLL operating current
—
600
—
—
µA
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
PLL period jitter (RMS)
• fvco = 48 MHz
2.0
4.0
MHz
Jcyc_pll
8
8
—
—
120
50
—
—
ps
ps
• fvco = 100 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 48 MHz
—
—
1350
600
—
—
ps
ps
• fvco = 100 MHz
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
1.49
4.47
—
—
—
—
2.98
5.97
150 × 10-6
+ 1075(1/
%
%
s
tpll_lock
9
fpll_ref
)
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23
Clock modules
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
6.3.2.1 Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
—
500
200
200
300
950
1.2
—
—
—
—
—
—
—
nA
μA
μA
μA
μA
mA
mA
• 1 MHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high-gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
—
25
300
400
500
2.5
3
—
—
—
—
—
—
—
μA
μA
• 1 MHz
• 4 MHz
μA
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
2, 3
2, 3
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
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Freescale Semiconductor, Inc.
Clock modules
Table 15. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
RF Feedback resistor — low-frequency, low-power
—
—
—
MΩ
2, 4
mode (HGO=0)
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
MΩ
MΩ
MΩ
kΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain mode
(HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
• 1 MHz resonator
• 2 MHz resonator
• 4 MHz resonator
• 8 MHz resonator
• 16 MHz resonator
• 20 MHz resonator
• 32 MHz resonator
—
—
—
—
—
—
—
—
6.6
3.3
0
—
—
—
—
—
—
—
—
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
V
0
0
0
0
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx and Cy can be provided by using either integrated capacitors or external components.
4. When low-power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other device.
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
25
Memories and memory interfaces
6.3.2.2 Oscillator frequency specifications
Table 16. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high-
frequency mode (low range)
1
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal
tdc_extal
tcst
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1, 2
3, 4
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
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Freescale Semiconductor, Inc.
Memories and memory interfaces
Table 17. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
13
Max.
18
Unit
μs
Notes
thvpgm4
Longword Program high-voltage time
—
1
thversscr Sector Erase high-voltage time
thversblk32k Erase Block high-voltage time for 32 KB
thversblk128k Erase Block high-voltage time for 128 KB
—
113
452
1808
ms
ms
ms
—
52
1
—
208
1
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash timing specifications — commands
Table 18. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
1
trd1blk32k
• 32 KB data flash
—
—
—
—
0.5
1.7
ms
ms
trd1blk128k
• 128 KB program flash
trd1sec1k Read 1s Section execution time (flash sector)
—
—
—
—
—
—
—
65
60
45
μs
μs
μs
μs
1
1
tpgmchk
trdrsrc
Program Check execution time
Read Resource execution time
Program Longword execution time
Erase Flash Block execution time
• 32 KB data flash
30
1
tpgm4
145
—
2
tersblk32k
—
—
55
465
ms
ms
tersblk128k
• 128 KB program flash
220
1850
tersscr
Erase Flash Sector execution time
Program Section execution time
• 512 bytes flash
—
14
114
ms
2
—
tpgmsec512
tpgmsec1k
—
—
4.7
9.3
—
—
ms
ms
• 1 KB flash
trd1all
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
—
1.8
25
ms
μs
μs
ms
μs
1
1
trdonce
tpgmonce Program Once execution time
65
275
—
—
—
2
tersall
Erase All Blocks execution time
2350
30
tvfykey
Verify Backdoor Access Key execution time
Program Partition for EEPROM execution time
• 32 KB FlexNVM
1
—
tpgmpart32k
—
70
—
ms
Set FlexRAM Function execution time:
• Control Code 0xFF
—
tsetramff
tsetram8k
tsetram32k
—
—
—
50
0.3
0.7
—
μs
ms
ms
• 8 KB EEPROM backup
• 32 KB EEPROM backup
0.5
1.0
Byte-write to FlexRAM for EEPROM operation
Table continues on the next page...
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Memories and memory interfaces
Table 18. Flash command timing specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
teewr8bers Byte-write to erased FlexRAM location execution
time
—
175
260
μs
3
Byte-write to FlexRAM execution time:
—
teewr8b8k
teewr8b16k
teewr8b32k
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
—
—
—
340
385
475
1700
1800
2000
μs
μs
μs
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
—
175
260
μs
—
—
Word-write to FlexRAM execution time:
teewr16b8k
teewr16b16k
teewr16b32k
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
—
—
—
340
385
475
1700
1800
2000
μs
μs
μs
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
360
540
μs
—
—
Longword-write to FlexRAM execution time:
teewr32b8k
teewr32b16k
teewr32b32k
• 8 KB EEPROM backup
• 16 KB EEPROM backup
• 32 KB EEPROM backup
—
—
—
545
630
810
1950
2050
2250
μs
μs
μs
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3 Flash high voltage current behaviors
Table 19. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
6.4.1.4 Reliability specifications
Table 20. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
Table continues on the next page...
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Memories and memory interfaces
Table 20. NVM reliability specifications (continued)
Symbol Description
Min.
5
Typ.1
Max.
—
Unit
years
years
years
cycles
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
tnvmretp100 Data retention after up to 100 cycles
nnvmcycp Cycling endurance
50
2
2
2
3
20
100
100
50 K
—
15
—
10 K
—
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
tnvmretd100 Data retention after up to 100 cycles
nnvmcycd Cycling endurance
5
50
—
—
—
—
years
years
years
cycles
2
2
2
3
20
100
100
50 K
15
10 K
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
tnvmretee1 Data retention up to 1% of write endurance
5
50
—
—
—
years
years
years
2
2
2
4
20
15
100
100
Write endurance
nnvmwree16
35 K
315 K
1.27 M
10 M
175 K
1.6 M
6.4 M
50 M
—
—
—
—
—
writes
writes
writes
writes
writes
• EEPROM backup to FlexRAM ratio = 16
nnvmwree128
• EEPROM backup to FlexRAM ratio = 128
nnvmwree512
• EEPROM backup to FlexRAM ratio = 512
nnvmwree4k
• EEPROM backup to FlexRAM ratio = 4096
nnvmwree8k
20 M
100 M
• EEPROM backup to FlexRAM ratio = 8192
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology.
3. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
4. Write endurance represents the number of writes to each FlexRAM location at –40 °C ≤Tj ≤ 125 °C influenced by the
cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup. Minimum and typical
values assume all byte-writes to FlexRAM.
6.4.2 EzPort Switching Specifications
All timing is shown with respect to a maximum pin load of 50 pF and input signal
transitions of 3 ns.
Table 21. EzPort switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
Unit
V
Operating voltage
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
Table continues on the next page...
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Memories and memory interfaces
Table 21. EzPort switching specifications (continued)
Num
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
Description
Min.
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
2 x tEZP_CK
15
0.0
15
0.0
—
—
—
—
—
25
—
0.0
—
12
EZP_CK
EP2
EP3
EP4
EZP_CS
EP9
EP8
EP7
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 5. EzPort Timing Diagram
6.4.3 Mini-Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
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Memories and memory interfaces
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Mini-Flexbus output clock (FB_CLK). All other timing relationships
can be derived from these values.
Table 22. Flexbus switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
25
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
MHz
ns
FB1
FB2
FB3
FB4
FB5
40
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
—
20
ns
1
1
2
2
1
—
ns
20
—
ns
10
—
ns
1. Specification is valid for all FB_AD[31:0], FB_CSn, FB_OE, FB_R/W, and FB_TS.
2. Specification is valid for all FB_AD[31:0].
Note
The following diagrams refer to signal names that may not be
included on your particular device. Ignore these extraneous
signals.
Also, ignore the AA=0 portions of the diagrams because this
setting is not supported in the Mini-FlexBus.
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Memories and memory interfaces
FB1
FB_CLK
FB3
FB5
FB_A[Y]
Address
FB4
FB2
Address
Data
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 6. Mini-FlexBus read timing diagram
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Memories and memory interfaces
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB2
FB3
Address
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 7. Mini-FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
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Analog
6.6 Analog
6.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
6.6.1.1 12-bit ADC operating conditions
Table 23. 12-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Ground voltage
Absolute
—
—
2
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
Delta to VSS (VSS – VSSA
)
0
2
ADC reference
voltage high
VDDA
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
CADIN
Input voltage
VREFL
—
—
4
VREFH
5
V
—
—
Input capacitance
• 8-bit / 10-bit / 12-bit
modes
pF
RADIN
RAS
Input series
resistance
—
2
5
kΩ
—
3
Analog source
resistance
(external)
12-bit modes
fADCK < 4 MHz
—
—
—
5
kΩ
fADCK
Crate
ADC conversion ≤ 12-bit mode
clock frequency
1.0
18.0
MHz
4
ADC conversion ≤ 12-bit modes
rate
—
No ADC hardware averaging
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
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Analog
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 8. ADC input impedance equivalency diagram
6.6.1.2 12-bit ADC electrical characteristics
Table 24. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
7.3
6.1
9.5
Unit
mA
Notes
IDDA_ADC Supply current
—
3
ADC
asynchronous
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
MHz
MHz
MHz
MHz
tADACK =
1/fADACK
3.0
clock source
fADACK
2.4
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
• 12-bit modes
• <12-bit modes
—
—
—
—
0.7
0.2
1.0
0.5
–1.1 to
+1.9
–0.3 to 0.5
INL
Integral non-
linearity
–2.7 to
+1.9
LSB4
5
–0.7 to
+0.5
Table continues on the next page...
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35
Analog
Table 24. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
—
Typ.2
Max.
–5.4
–1.8
0.5
Unit
Notes
EFS
Full-scale error
• 12-bit modes
• <12-bit modes
• 12-bit modes
–4
LSB4
VADIN
VDDA
=
5
—
–1.4
—
EQ
EIL
Quantization
error
—
LSB4
mV
Input leakage
error
IIn × RAS
IIn =
leakage
current
(refer to
the MCU's
voltage
and current
operating
ratings)
Temp sensor
slope
–40°C to 25°C
25 to 105°C
25 °C
1.695
1.713
716
mV/°C
mV
6
VTEMP25 Temp sensor
voltage
6
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. ADC conversion clock < 3 MHz
Typical ADC 12-bit Single Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
11.9
11.8
11.7
11.6
11.5
11.4
11.3
11.2
11.1
11
10.9
10.8
10.7
10.6
10.5
10.4
10.3
Hardware Averaging Disabled
Averaging of 8 samples
10.2
10.1
10
Averaging of 32 samples
0
2
4
6
8
10
12
14
16
18
20
22
ADC Clock Frequency (MHz)
Figure 9. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode
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Analog
6.6.2 CMP and 6-bit DAC electrical specifications
Table 25. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
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Analog
0.08
0.07
0.06
0.05
0.04
0.03
HYSTCTR
Setting
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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12-bit DAC electrical characteristics
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 26. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
1.71
1.13
—
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
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39
12-bit DAC electrical characteristics
6.6.3.2 12-bit DAC operating behaviors
Table 27. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
450
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
—
100
15
0.7
—
1000
200
30
μA
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
μs
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
1
μs
Vdacoutl DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
100
VDACR
8
mV
mV
LSB
LSB
LSB
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
—
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
—
2
3
4
Differential non-linearity error — VDACR > 2
V
—
1
Differential non-linearity error — VDACR
VREF_OUT
=
—
1
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
• High power (SPHP
• Low power (SPLP
)
1.2
1.7
—
—
)
0.05
0.12
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to
0x800, temperature range is across the full range of the device
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12-bit DAC electrical characteristics
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 12. Typical INL error vs. digital code
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41
12-bit DAC electrical characteristics
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
-40
55
85
25
105
125
Temperature °C
Figure 13. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 28. VREF full-range operating requirements
Symbol
VDDA
CL
Description
Min.
Max.
Unit
Notes
Supply voltage
1.71
3.6
V
—
1
Output load capacitance
100
nF
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
Table 29. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1965
1.2
1.2027
V
nominal VDDA and temperature=25C
Vout
Voltage reference output — factory trim
1.144
—
1.266
V
Table continues on the next page...
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12-bit DAC electrical characteristics
Table 29. VREF full-range operating behaviors (continued)
Symbol Description
Min.
1.198
—
Typ.
—
Max.
1.202
—
Unit
V
Notes
Vout
Vstep
Vtdrift
Voltage reference output — user trim
Voltage reference trim step
0.5
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
80
Ibg
Ihp
Bandgap only current
—
—
—
—
80
1
µA
mA
mV
High-power buffer current
ΔVLOAD Load regulation
• current = + 1.0 mA
1
—
—
2
5
—
—
• current = - 1.0 mA
Tstup
Buffer startup time
—
—
—
2
100
—
µs
—
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
mV
1. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 30. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
—
Table 31. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
—
6.7 Timers
See General Switching Specifications.
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
43
Communication interfaces
6.8 Communication interfaces
6.8.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. See the SPI chapter of the
chip's Reference Manual for information about the modified transfer formats used for
communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 70% VDD, unless noted, as well as
input signal transitions of 3 ns and a 50 pF maximum load on all SPI pins. All timing
assumes slew rate control is disabled and high drive strength is enabled for SPI output
pins.
Table 32. SPI master mode timing
Num.
Symbol Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
fBUS/2048
fBUS/2
Hz
fBUS is the
bus clock
as defined
in Table 8.
2
tSPSCK
SPSCK period
2 x tBUS 2048 x tBUS
ns
tBUS = 1/
fBUS
3
4
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
—
—
—
—
—
5
tWSPSCK Clock (SPSCK) high or low time
tBUS - 30 1024 x tBUS
6
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
21
0
—
—
ns
7
ns
8
tv
—
0
25
ns
9
tHO
tRI
—
ns
10
—
tBUS - 25
ns
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
MCF51QU128, Rev. 5, 03/2015
44
Freescale Semiconductor, Inc.
Communication interfaces
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI master mode timing (CPHA=0)
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 15. SPI master mode timing (CPHA=1)
Table 33. SPI slave mode timing
Num.
Symbol Description
Min.
Max.
fBUS/4
Unit
Comment
1
fop
Frequency of operation
0
Hz
fBUS is the
bus clock
as defined
in Table 8.
2
tSPSCK
SPSCK period
4 x tBUS
—
ns
tBUS = 1/
fBUS
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
45
Communication interfaces
Table 33. SPI slave mode timing (continued)
Num.
Symbol Description
Min.
Max.
Unit
tBUS
tBUS
ns
Comment
3
4
5
6
7
8
tLead
tLag
Enable lead time
Enable lag time
1
—
—
—
—
—
—
—
1
tBUS - 30
19.5
0
tWSPSCK Clock (SPSCK) high or low time
—
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
—
ns
—
ns
—
tBUS
ns
Time to
data active
from high-
impedance
state
9
tdis
Slave MISO disable time
—
tBUS
ns
Hold time
to high-
impedance
state
10
11
12
tv
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
—
0
27
—
ns
ns
ns
—
—
—
tHO
tRI
—
tBUS - 25
tFI
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 16. SPI slave mode timing (CPHA=0)
MCF51QU128, Rev. 5, 03/2015
46
Freescale Semiconductor, Inc.
Human-machine interfaces (HMI)
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
NOTE: Not defined
Figure 17. SPI slave mode timing (CPHA=1)
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 34. TSI electrical specifications
Symbol Description
VDDTSI Operating voltage
CELE Target electrode capacitance range
Min.
1.71
1
Typ.
—
Max.
3.6
Unit
V
Notes
20
500
14
pF
1
2
3
fREFmax Reference oscillator frequency
fELEmax Electrode oscillator frequency
—
5.5
0.5
1
MHz
MHz
pF
—
4.0
CREF
VDELTA
IREF
Internal reference capacitor
Oscillator delta voltage
0.5
100
1.2
600
760
mV
μA
4
Reference oscillator current source base current
• 1uA setting (REFCHRG=0)
3 , 5
—
—
1.133
36
1.5
50
• 32uA setting (REFCHRG=31)
IELE
Electrode oscillator current source base current
• 1uA setting (EXTCHRG=0)
μA
3 , 6
—
—
1.133
36
1.5
50
• 32uA setting (EXTCHRG=31)
Pres5
Electrode capacitance measurement precision
—
8.3333
8.3333
8.3333
12.5
—
38400
38400
38400
—
fF/count
fF/count
fF/count
fF/count
bits
7
8
Pres20 Electrode capacitance measurement precision
Pres100 Electrode capacitance measurement precision
MaxSens Maximum sensitivity
—
—
9
0.003
—
10
Res
Resolution
16
TCon20
Response time @ 20 pF
8
15
25
μs
11
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
47
Dimensions
Table 34. TSI electrical specifications (continued)
Symbol Description
Min.
—
Typ.
55
Max.
—
Unit
μA
Notes
ITSI_RUN Current added in run mode
ITSI_LP
Low power mode current adder
—
1.3
2.5
μA
12
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. CAPTRM=7, DELVOL=7, and fixed external capacitance of 20 pF.
3. CAPTRM=0, DELVOL=2, and fixed external capacitance of 20 pF.
4. CAPTRM=0, EXTCHRG=9, and fixed external capacitance of 20 pF.
5. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
6. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
7. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
8. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
10. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes, it is equal to (Cref
* Iext)/( Iref * PS * NSCN). Sensitivity depends on the configuration used. The typical value listed is based on the following
configuration: Iext = 5 μA, EXTCHRG = 4, PS = 128, NSCN = 2, Iref = 16 μA, REFCHRG = 15, Cref = 1.0 pF. The minimum
sensitivity describes the smallest possible capacitance that can be measured by a single count (this is the best sensitivity
but is described as a minimum because it’s the smallest number). The minimum sensitivity parameter is based on the
following configuration: Iext = 1 μA, EXTCHRG = 0, PS = 128, NSCN = 32, Iref = 32 μA, REFCHRG = 31, Cref= 0.5 pF
11. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, DELVOL = 2, EXTCHRG = 15.
12. CAPTRM=7, DELVOL=2, REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and
fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.freescale.com and perform a keyword search for
the drawing’s document number:
If you want the drawing for this package
32-pin QFN
Then use this document number
98ARE10566D
44-pin Laminate QFN
48-pin LQFP
98ASA00239D
98ASH00962A
98ASS23234W
64-pin LQFP
MCF51QU128, Rev. 5, 03/2015
48
Freescale Semiconductor, Inc.
Pinout
8 Pinout
8.1 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Mux Control module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
• On PTB0, EZP_MS_b is active only during reset. Refer to
the detailed boot description.
• PTC1 is open drain.
64-
pin
48-
pin
44-
pin
32-
pin
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
—
—
—
EP
Exposed Pad Exposed die
attach pad.
Connection to
VSS is
recommende
d.
—
—
EP
—
VSS
Exposed die
attach pads
are
connected
internally to
VSS. External
connection to
VSS is
recommende
d.
1
2
3
4
5
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
VDD
VDD
VSS
VSS
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
PTC6
UART0_TX
UART0_RX
I2C0_SCL
I2C0_SDA
I2C1_SDA
RGPIO6
RGPIO7
RGPIO8
SPI1_MOSI
SPI1_MISO
SPI1_SCLK
FBa_AD11
FBa_AD12
FBa_AD13
PTC7
PTD0
UART0_
CTS_b
6
2
—
—
Disabled
Disabled
PTD1
UART0_
RTS_b
I2C1_SCL
RGPIO9
SPI1_SS
SPI0_SS
FBa_AD14
7
8
3
4
5
6
7
1
2
3
4
5
1
2
3
4
5
Disabled
Disabled
Disabled
Disabled
ADC0_SE2
Disabled
Disabled
Disabled
Disabled
ADC0_SE2
PTA0
PTA1
PTA2
PTA3
PTA4
I2C2_SCL
I2C2_SDA
FTM1_CH0
FTM1_CH1
FTM1_CH2
FTM1_CH3
FTM1_CH4
FBa_AD15
FBa_AD16
9
UART1_TX
UART1_RX
SPI1_SS
10
11
SPI1_SCLK
SPI1_MISO
EZP_CLK
EZP_DI
UART1_
CTS_b
I2C2_SCL
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
49
Pinout
64-
pin
48-
pin
44-
pin
32-
pin
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
12
8
6
6
ADC0_SE3
ADC0_SE3
PTA5
UART1_
RTS_b
I2C2_SDA
FTM1_CH5
SPI1_MOSI
CLKOUT
EZP_DO
13
14
15
16
17
18
19
20
21
22
23
24
25
9
7
7
VDDA
VDDA
10
11
12
13
14
15
16
17
18
19
20
21
8
—
—
—
8
VREFH
VREFH
9
VREF_OUT
VREFL
VREF_OUT
VREFL
10
11
12
13
14
15
16
17
18
19
VSSA
VSSA
9
DAC0_OUT
ADC0_SE0
ADC0_SE1
VREGIN
VOUT33
VSS
DAC0_OUT
ADC0_SE0
ADC0_SE1
VREGIN
VOUT33
VSS
10
11
12
13
14
—
15
VDD
VDD
ADC0_SE8/
TSI0_CH0
ADC0_SE8/
TSI0_CH0
PTA6
PTD2
LPTMR_
ALT1
FTM_FLT1
FTM0_CH0
FTM0_CH1
FBa_D7
FBa_D6
FBa_AD17
26
27
28
29
30
31
32
33
—
22
—
—
23
24
—
—
—
20
—
—
21
22
—
—
—
—
—
—
16
—
—
—
ADC0_SE9/
TSI0_CH1
ADC0_SE9/
TSI0_CH1
FTM0_QD_
PHA
RGPIO10
RGPIO11
RGPIO12
RGPIO13
ADC0_SE10/ ADC0_SE10/ PTD3
TSI0_CH2 TSI0_CH2
FTM0_QD_
PHB
FBa_AD0
FBa_D7
FBa_D6
FBa_D5
FBa_D4
FBa_D3
FBa_D2
FBa_D1
ADC0_SE11/ ADC0_SE11/ PTD4
TSI0_CH3 TSI0_CH3
ADC0_SE12/ ADC0_SE12/ PTD5
TSI0_CH4 TSI0_CH4
ADC0_SE13/ ADC0_SE13/ PTA7
TSI0_CH5 TSI0_CH5
UART0_TX
UART0_RX
FTM0_QD_
PHA
ADC0_SE14/ ADC0_SE14/ PTD6
TSI0_CH6 TSI0_CH6
RGPIO14
I2C3_SCL
I2C3_SDA
ADC0_SE15/ ADC0_SE15/ PTD7
TSI0_CH7
UART0_
CTS_b
RGPIO15
TSI0_CH7
TSI0_CH8
TSI0_CH8
PTE0
UART0_
RTS_b
34
35
—
—
—
TSI0_CH9
TSI0_CH9
Disabled
PTE1
PTB0
SPI0_SS
FTM_FLT0
FTM_FLT2
25
23
17
IRQ/
EZP_MS_b
I2C0_SCL
I2C0_SDA
IRQ/
EZP_MS_b
EZP_CS_b
36
26
24
18
TSI0_CH10
TSI0_CH10
PTB1
SPI0_SCLK
LPTMR_
ALT2
FTM0_QD_
PHB
FB_CLKOUT
37
38
—
—
—
—
—
—
TSI0_CH11
TSI0_CH11
PTE2
I2C3_SCL
I2C3_SDA
FBa_D0
ADC0_SE16/ ADC0_SE16/ PTE3
TSI0_CH12 TSI0_CH12
SPI0_MOSI
SPI0_MISO
SPI0_MOSI
FBa_OE_b
39
40
41
27
28
29
25
26
—
19
20
—
ADC0_SE17/ ADC0_SE17/ PTB2
TSI0_CH13 TSI0_CH13
FBa_CS0_b
FBa_ALE
FBa_AD1
ADC0_SE18/ ADC0_SE18/ PTB3
TSI0_CH14 TSI0_CH14
FBa_CS1_b
ADC0_SE19/ ADC0_SE19/ PTE4
TSI0_CH15 TSI0_CH15
UART0_
RTS_b
LPTMR_
ALT3
SPI1_SS
MCF51QU128, Rev. 5, 03/2015
50
Freescale Semiconductor, Inc.
Pinout
64-
pin
48-
pin
44-
pin
32-
pin
Default
ALT0
ALT1
ALT2
ALT3
I2C1_SCL
I2C1_SDA
ALT4
ALT5
ALT6
ALT7
EzPort
42
30
—
—
ADC0_SE20
ADC0_SE20
PTE5
UART0_
CTS_b
SPI1_SCLK
FBa_AD2
43
44
—
—
—
—
ADC0_SE21
ADC0_SE22
ADC0_SE21
ADC0_SE22
PTE6
PTE7
UART0_RX
UART0_TX
SPI1_MISO
SPI1_MOSI
FBa_AD3
FBa_AD4
31
27
PDB0_
EXTRG
FBa_RW_b
45
32
28
21
BKGD/
MS
Disabled
PTB4
BKGD/
MS
46
47
48
49
50
51
52
53
54
55
56
57
33
34
35
36
37
38
39
—
—
—
40
41
29
30
31
32
33
34
35
—
—
—
36
37
22
23
24
25
26
27
28
—
—
—
—
29
XTAL2
XTAL2
PTB5
PTB6
EXTAL2
VDD
EXTAL2
VDD
VSS
VSS
EXTAL1
XTAL1
EXTAL1
XTAL1
PTB7
PTC0
PTC1
PTF0
PTF1
PTF2
PTF3
PTC2
I2C1_SDA
I2C1_SCL
TMR_CLKIN1
TMR_CLKIN0 RGPIO0
RESET_b
CMP0_IN0
Disabled
CMP0_IN1
CMP0_IN2
CMP0_IN3
Disabled
CMP0_IN0
Disabled
CMP0_IN1
CMP0_IN2
CMP0_IN3
RESET_b
SPI0_SS
FBa_AD5
FBa_AD6
FBa_AD7
FBa_AD8
FBa_AD18
SPI0_SCLK
SPI0_MISO
SPI0_MOSI
CMP0_OUT
RGPIO1
RGPIO2
UART1_
RTS_b
SPI1_SS
58
42
38
—
Disabled
Disabled
PTF4
UART1_
CTS_b
SPI1_SCLK
FBa_D3
FBa_AD19
59
60
61
43
44
45
39
40
41
—
—
—
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
PTF5
PTF6
PTF7
UART1_RX
UART1_TX
SPI1_MISO
SPI1_MOSI
FBa_D2
FBa_D1
FBa_D0
FBa_RW_b
FBa_AD9
UART0_
RTS_b
SPI0_SS
FBa_AD10
62
63
64
46
47
48
42
43
44
30
31
32
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
PTC3
PTC4
PTC5
UART0_
CTS_b
RGPIO3
RGPIO4
RGPIO5
SPI0_SCLK
SPI0_MISO
SPI0_MOSI
CLKOUT
UART0_RX
PDB0_
EXTRG
UART0_TX
CMT_IRO
8.2 Pinout diagrams
The following diagrams show pinouts for the 64-pin, 48-pin, 44-pin, and 32-pin
packages. These diagrams are representations for ease of reference. See the package
drawings for mechanical details.
For each pin, the diagrams show the default function or (when disabled is the default) the
ALT1 signal for a GPIO function. However, many signals may be multiplexed onto a
single pin.
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
51
Pinout
VDD
VSS
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
2
EXTAL2
PTC6
3
XTAL2
PTC7
4
BKGD/MS
PTD0
5
ADC0_SE22
PTD1
6
ADC0_SE21
PTA0
7
ADC0_SE20
PTA1
8
ADC0_SE19/TSI0_CH15
ADC0_SE18/TSI0_CH14
ADC0_SE17/TSI0_CH13
ADC0_SE16/TSI0_CH12
TSI0_CH11
PTA2
9
PTA3
10
11
12
13
14
15
16
ADC0_SE2
ADC0_SE3
VDDA
TSI0_CH10
VREFH
VREF_OUT
VREFL
IRQ/EZP_MS_b
TSI0_CH9
TSI0_CH8
Figure 18. 64-pin LQFP
MCF51QU128, Rev. 5, 03/2015
52
Freescale Semiconductor, Inc.
Pinout
VSS
36
35
34
33
32
31
30
29
28
27
26
25
PTD0
PTD1
1
2
VDD
EXTAL2
PTA0
3
XTAL2
PTA1
4
BKGD/MS
PTA2
5
ADC0_SE22
ADC0_SE20
ADC0_SE19/TSI0_CH15
ADC0_SE18/TSI0_CH14
ADC0_SE17/TSI0_CH13
TSI0_CH10
PTA3
6
ADC0_SE2
ADC0_SE3
VDDA
7
8
9
VREFH
VREF_OUT
VREFL
10
11
12
IRQ/EZP_MS_b
Figure 19. 48-pin LQFP
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
53
Pinout
PTA0
PTA1
1
3
5
7
9
33 EXTAL1
2
4
32
30
28
26
24
VSS
PTA2
31 VDD
PTA3
EXTAL2
ADC0_SE2
ADC0_SE3
VDDA
29 XTAL2
EXPOSED
PADS
6
BKGD/MS
27 ADC0_SE22
ADC0_SE18/TSI0_CH14
25 ADC0_SE17/TSI0_CH13
TSI0_CH10
VREFH
8
VREF_OUT
VREFL
10
VSSA 11
23 IRQ/EZP_MS_b
Figure 20. 44-pin Laminate QFN
MCF51QU128, Rev. 5, 03/2015
54
Freescale Semiconductor, Inc.
Pinout
VDD
PTA0
PTA1
24
23
22
21
20
19
1
2
3
4
5
6
7
8
EXTAL2
XTAL2
PTA2
BKGD/MS
PTA3
EXPOSED
PAD
ADC0_SE18/TSI0_CH14
ADC0_SE17/TSI0_CH13
TSI0_CH10
ADC0_SE2
ADC0_SE3
VDDA
18
17
VSSA
IRQ/EZP_MS_b
Figure 21. 32-pin QFN
8.3 Module-by-module signals
NOTE
• On PTB0, EZP_MS_b is active only during reset. Refer to
the detailed boot description.
• PTC1 is open drain.
Table 35. Module signals by GPIO port and pin
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
Power and ground
1
VDD
VDD
24
20
18
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
55
Pinout
Table 35. Module signals by GPIO port and pin (continued)
64-pin
48
48-pin
44-pin
32-pin
Port
Module signal(s)
35
31
24
VDD
VSS
VSS
VSS
2
23
19
36
17
32
14
25
49
System
45
12
62
10
11
12
35
32
8
28
6
21
6
PTB4
PTA5
PTC3
PTA3
PTA4
PTA5
PTB0
BKGD/MS
CLKOUT
CLKOUT
EZP_CLK
EZP_DI
46
6
42
4
30
4
7
5
5
8
6
6
EZP_DO
25
23
17
IRQ/EZP_MS_b,
EZP_CS_b
52
39
35
28
PTC1
RESET_b
OSC
50
47
51
46
37
34
38
33
33
30
34
29
26
23
27
22
PTB7
PTB6
PTC0
PTB5
EXTAL1
EXTAL2
XTAL1
XTAL2
LLWU
4
PTC7
PTD1
PTA5
PTA7
PTD7
PTB0
PTB1
PTB2
PTE7
PTB4
PTF2
PTF3
PTC2
PTF5
PTC3
PTC4
LLWU_P0
LLWU_P1
LLWU_P2
LLWU_P3
LLWU_P4
LLWU_P5
LLWU_P6
LLWU_P7
LLWU_P8
LLWU_P9
LLWU_P10
LLWU_P11
LLWU_P12
LLWU_P13
LLWU_P14
LLWU_P15
6
2
8
12
30
32
35
36
39
44
45
55
56
57
59
62
63
6
6
23
21
16
25
26
27
31
32
23
24
25
27
28
17
18
19
21
29
40
41
43
46
47
36
37
39
42
43
30
31
RGPIO
51
56
57
38
40
41
34
36
37
27
PTC0
PTF3
PTC2
RGPIO0
RGPIO1
RGPIO2
29
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
56
Freescale Semiconductor, Inc.
Pinout
Table 35. Module signals by GPIO port and pin (continued)
64-pin
62
63
64
3
48-pin
46
44-pin
42
32-pin
30
Port
PTC3
PTC4
PTC5
PTC6
PTC7
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
Module signal(s)
RGPIO3
47
43
31
RGPIO4
48
44
32
RGPIO5
RGPIO6
4
RGPIO7
5
1
2
RGPIO8
6
RGPIO9
26
27
28
29
31
32
RGPIO10
RGPIO11
RGPIO12
RGPIO13
RGPIO14
RGPIO15
22
24
20
22
LPTMR
25
36
41
21
26
29
19
24
15
18
PTA6
PTB1
PTE4
LPTMR_ALT1
LPTMR_ALT2
LPTMR_ALT3
LPTMR-TOD
50
47
25
36
41
51
46
37
34
21
26
29
38
33
33
30
19
24
26
23
15
18
PTB7
PTB6
PTA6
PTB1
PTE4
PTC0
PTB5
EXTAL1
EXTAL2
LPTMR_ALT1
LPTMR_ALT2
LPTMR_ALT3
XTAL1
34
29
27
22
XTAL2
PTA
7
3
4
1
2
1
2
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
PTA7
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
PTA7
8
9
5
3
3
10
11
12
25
30
6
4
4
7
5
5
8
6
6
21
23
19
21
15
16
PTB
35
36
39
40
25
26
27
28
23
24
25
26
17
18
19
20
PTB0
PTB1
PTB2
PTB3
PTB0
PTB1
PTB2
PTB3
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
57
Pinout
Table 35. Module signals by GPIO port and pin (continued)
64-pin
45
48-pin
32
44-pin
28
32-pin
21
Port
PTB4
PTB5
PTB6
PTB7
Module signal(s)
PTB4
46
33
29
22
PTB5
47
34
30
23
PTB6
50
37
33
26
PTB7
PTC
PTD
PTE
PTF
51
52
57
62
63
64
3
38
39
41
46
47
48
34
35
37
42
43
44
27
28
29
30
31
32
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
4
5
1
2
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
6
26
27
28
29
31
32
22
24
20
22
33
34
38
39
41
42
43
44
PTE0
PTE1
PTE3
PTB2
PTE4
PTE5
PTE6
PTE7
PTE0
PTE1
PTE2
PTE3
PTE4
PTE5
PTE6
PTE7
27
29
30
25
27
19
31
53
54
55
56
58
59
60
PTF0
PTF1
PTF2
PTF3
PTF4
PTF5
PTF6
PTF0
PTF1
PTF2
PTF3
PTF4
PTF5
PTF6
40
42
43
44
36
38
39
40
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
58
Freescale Semiconductor, Inc.
Pinout
Table 35. Module signals by GPIO port and pin (continued)
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
61
45
41
PTF7
PTF7
5 V VREG
ADC0
22
21
18
17
16
15
13
12
VOUT33
VREGIN
11
12
25
26
27
28
29
30
31
32
38
39
40
41
42
43
44
13
14
16
17
7
8
5
6
5
6
PTA4
PTA5
PTA6
PTD2
PTD3
PTD4
PTD5
PTA7
PTD6
PTD7
PTE3
PTB2
PTB3
PTE4
PTE5
PTE6
PTE7
ADC0_SE2
ADC0_SE3
ADC0_SE8
ADC0_SE9
ADC0_SE10
ADC0_SE11
ADC0_SE12
ADC0_SE13
ADC0_SE14
ADC0_SE15
ADC0_SE16
ADC0_SE17
ADC0_SE18
ADC0_SE19
ADC0_SE20
ADC0_SE21
ADC0_SE22
VDDA
21
19
15
22
20
23
24
21
22
16
27
28
29
30
25
26
19
20
31
9
27
7
7
10
12
13
8
VREFH
10
11
VREFL
8
9
VSSA
DAC0
VREF
CMP0
18
15
14
11
12
9
DAC0_OUT
VREF_OUT
53
55
56
57
54
PTF0
PTF2
PTF3
PTC2
PTF1
CMP0_IN0
CMP0_IN1
CMP0_IN2
CMP0_IN3
CMP0_OUT
40
41
36
37
29
32
CMT
TSI0
64
48
44
PTC5
CMT_IRO
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
59
Pinout
Table 35. Module signals by GPIO port and pin (continued)
64-pin
25
26
27
28
29
30
31
32
33
34
36
37
38
39
40
41
48-pin
44-pin
32-pin
Port
PTA6
PTD2
PTD3
PTD4
PTD5
PTA7
PTD6
PTD7
PTE0
PTE1
PTB1
PTE2
PTE3
PTB2
PTB3
PTE4
Module signal(s)
TSI0_CH0
TSI0_CH1
TSI0_CH2
TSI0_CH3
TSI0_CH4
TSI0_CH5
TSI0_CH6
TSI0_CH7
TSI0_CH8
TSI0_CH9
TSI0_CH10
TSI0_CH11
TSI0_CH12
TSI0_CH13
TSI0_CH14
TSI0_CH15
21
19
15
22
20
23
24
21
22
16
18
26
24
27
28
29
25
26
19
20
PDB0
FTM0
44
63
31
47
27
43
PTE7
PTC4
PDB0_EXTRG
PDB0_EXTRG
31
34
25
36
PTE1
PTA6
PTB1
FTM_FLT0
FTM_FLT1
21
26
19
24
15
18
FTM_FLT2 /
FTM0_QD_PHB
26
27
PTD2
PTD3
FTM0_CH0/
FTM0_QD_PHA
22
20
FTM0_CH1 /
FTM0_QD_PHB
30
51
50
23
38
37
21
34
33
16
27
26
PTA7
PTC0
PTB7
FTM0_QD_PHA
TMR_CLKIN0
TMR_CLKIN1
FTM1
34
25
36
7
PTE1
PTA6
PTB1
PTA0
PTA1
PTA2
PTA3
PTA4
FTM_FLT0
FTM_FLT1
FTM_FLT2
FTM1_CH0
FTM1_CH1
FTM1_CH2
FTM1_CH3
FTM1_CH4
21
26
3
19
24
1
15
18
1
8
4
2
2
9
5
3
3
10
11
6
4
4
7
5
5
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
60
Freescale Semiconductor, Inc.
Pinout
Table 35. Module signals by GPIO port and pin (continued)
64-pin
12
48-pin
8
44-pin
6
32-pin
6
Port
PTA5
PTC0
PTB7
Module signal(s)
FTM1_CH5
51
38
34
27
TMR_CLKIN0
TMR_CLKIN1
50
37
33
26
MTIM
51
50
38
37
34
33
27
26
PTC0
PTB7
TMR_CLKIN0
TMR_CLKIN1
Mini-FlexBus
36
27
41
42
43
44
53
54
55
56
60
61
3
26
22
29
30
24
20
18
PTB1
PTD3
PTE4
PTE5
PTE6
PTE7
PTF0
PTF1
PTF2
PTF3
PTF6
PTF7
PTC6
PTC7
PTD0
PTD1
PTA0
PTA1
PTA6
PTC2
PTF4
PTB3
PTB2
PTE2
PTE1
PTE0
PTD7
PTD6
PTA7
PTD5
PTD4
PTE3
FB_CLKOUT
FBa_AD0
FBa_AD1
FBa_AD2
FBa_AD3
FBa_AD4
FBa_AD5
FBa_AD6
FBa_AD7
FBa_AD8
FBa_AD9
FBa_AD10
FBa_AD11
FBa_AD12
FBa_AD13
FBa_AD14
FBa_AD15
FBa_AD16
FBa_AD17
FBa_AD18
FBa_AD19
FBa_ALE
FBa_CS0_b
FBa_D0
31
27
40
44
45
36
40
41
4
5
1
2
6
7
3
1
1
2
8
4
2
25
57
58
40
39
37
34
33
32
31
30
29
28
38
21
41
42
28
27
19
37
38
26
25
15
29
20
19
FBa_D1
FBa_D2
FBa_D3
24
23
22
21
FBa_D4
16
FBa_D5
FBa_D6
FBa_D7
FBa_OE_b
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
61
Pinout
Table 35. Module signals by GPIO port and pin (continued)
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
59
43
39
PTF5
FBa_RW_b
DATA_BUS
8
4
2
2
PTA1
PTB2
PTF7
PTF6
PTF5
PTF4
PTD6
PTA7
PTD3
PTA6
PTE7
FBa_AD16
FBa_CS0_b
FBa_D0
39
61
60
59
58
31
30
27
25
44
27
45
44
43
42
24
23
22
21
31
25
41
40
39
38
22
21
20
19
27
19
FBa_D1
FBa_D2
FBa_D3
FBa_D4
16
15
FBa_D5
FBa_D6
FBa_D7
FBa_RW_b
I2C0 and I2C1
3
PTC6
PTB0
PTC7
PTB1
PTD1
PTE5
PTC0
PTD0
PTE6
PTB7
I2C0_SCL
I2C0_SCL
I2C0_SDA
I2C0_SDA
I2C1_SCL
I2C1_SCL
I2C1_SCL
I2C1_SDA
I2C1_SDA
I2C1_SDA
35
4
25
23
24
17
18
36
6
26
2
42
51
5
30
38
1
34
33
27
26
43
50
37
I2C2 and I2C3
7
3
7
4
8
1
5
2
6
1
5
2
6
PTA0
PTA4
PTA1
PTA5
PTD7
PTE2
PTE0
PTE3
I2C2_SCL
I2C2_SCL
I2C2_SDA
I2C2_SDA
I2C3_SCL
I2C3_SCL
I2C3_SDA
I2C3_SDA
11
8
12
32
37
33
38
SPI0
39
55
63
38
40
27
47
28
25
43
26
19
31
20
PTB2
PTF2
PTC4
PTE3
PTB3
SPI0_MISO
SPI0_MISO
SPI0_MISO
SPI0_MOSI
SPI0_MOSI
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
62
Freescale Semiconductor, Inc.
Pinout
Table 35. Module signals by GPIO port and pin (continued)
64-pin
56
48-pin
40
44-pin
36
32-pin
Port
PTF3
PTC5
PTB1
PTF1
PTC3
PTA0
PTE1
PTF0
PTF7
Module signal(s)
SPI0_MOSI
SPI0_MOSI
SPI0_SCLK
SPI0_SCLK
SPI0_SCLK
SPI0_SS
64
48
44
32
18
36
26
24
54
62
46
3
42
1
30
1
7
34
SPI0_SS
53
SPI0_SS
61
45
41
SPI0_SS
SPI1
4
PTC7
PTA4
PTE6
PTF5
PTC6
PTA5
PTE7
PTF6
PTD0
PTA3
PTE5
PTF4
PTD1
PTA2
PTE4
PTC2
SPI1_MISO
SPI1_MISO
SPI1_MISO
SPI1_MISO
SPI1_MOSI
SPI1_MOSI
SPI1_MOSI
SPI1_MOSI
SPI1_SCLK
SPI1_SCLK
SPI1_SCLK
SPI1_SCLK
SPI1_SS
11
43
59
3
7
5
5
6
4
43
39
12
44
60
5
8
31
44
1
6
27
40
10
42
58
6
6
4
38
3
30
42
2
9
5
3
SPI1_SS
41
57
29
41
SPI1_SS
37
29
SPI1_SS
UART0
5
1
PTD0
PTD7
PTE5
PTC3
PTD1
PTE0
PTE4
PTF7
PTC7
PTD6
PTE6
PTC4
UART0_CTS_b
UART0_CTS_b
UART0_CTS_b
UART0_CTS_b
UART0_RTS_b
UART0_RTS_b
UART0_RTS_b
UART0_RTS_b
UART0_RX
32
42
62
6
30
46
2
42
30
33
41
61
4
29
45
41
22
43
31
43
63
24
47
UART0_RX
UART0_RX
31
UART0_RX
Table continues on the next page...
MCF51QU128, Rev. 5, 03/2015
Freescale Semiconductor, Inc.
63
Revision History
Table 35. Module signals by GPIO port and pin (continued)
64-pin
3
48-pin
44-pin
32-pin
Port
PTC6
PTA7
PTE7
PTC5
Module signal(s)
UART0_TX
30
23
31
48
21
27
44
16
UART0_TX
44
UART0_TX
64
32
UART0_TX
UART1
11
58
12
57
10
59
9
7
42
8
5
38
6
5
PTA4
PTF4
PTA5
PTC2
PTA3
PTF5
PTA2
PTF6
UART1_CTS_b
UART1_CTS_b
UART1_RTS_b
UART1_RTS_b
UART1_RX
6
29
4
41
6
37
4
43
5
39
3
UART1_RX
3
UART1_TX
60
44
40
UART1_TX
9 Revision History
The following table summarizes content changes since the previous release of this
document.
Table 36. Revision History
Rev. No.
Date
Substantial Changes
5
03/2015
• Updated the value and description in Power mode transition operating behaviors
• Updated the maximum value of ffll_ref in MCG specs
• 12-bit ADC characteristics: Updated the values of temperature sensor slope for -40°C to 25°C
and 25°C to 105°C
• Updated the minimum and typical values of Vout in VREF full-range operating behaviors
• Updated the maximum internal reference frequency and maximum FLL reference frequency
range in MCG specifications
• Updated the values of Temperature sensor voltage in 12-bit ADC characteristics
• Removed the temperature parameter from VREF full-range operating requirements table
• Removed Write endurance to FlexRAM for EEPROM section
• Removed ADC calculator tool footnote from ADC operating conditions
MCF51QU128, Rev. 5, 03/2015
64
Freescale Semiconductor, Inc.
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Document Number MCF51QU128
Revision 5, 03/2015
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