935314884557 [NXP]
RISC Microcontroller;
| 型号： | 935314884557 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 外围集成电路 |
| 文件： | 总37页 (文件大小：844K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number MKE02P64M20SF0
Rev. 6, 01/2019
NXP Semiconductors
Data Sheet: Technical Data
MKE02P64M20SF0
KE02 Sub-Family Data Sheet
Supports the following:
MKE02Z16VLC2(R),
MKE02Z32VLC2(R),
MKE02Z64VLC2(R),
MKE02Z16VLD2(R),
MKE02Z32VLD2(R),
MKE02Z64VLD2(R),
MKE02Z32VLH2(R),
MKE02Z64VLH2(R),
MKE02Z32VQH2(R), and
MKE02Z64VQH2(R)
Key features
• System peripherals
– Power management module (PMC) with three power
modes: Run, Wait, Stop
– Low-voltage detection (LVD) with reset or interrupt,
selectable trip points
– Watchdog with independent clock source (WDOG)
– Programmable cyclic redundancy check module
(CRC)
– Serial wire debug interface (SWD)
– Bit manipulation engine (BME)
• Operating characteristics
– Voltage range: 2.7 to 5.5 V
– Flash write voltage range: 2.7 to 5.5 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 20 MHz Arm® Cortex-M0+ core
– Single cycle 32-bit x 32-bit multiplier
– Single cycle I/O access port
• Memories and memory interfaces
– Up to 64 KB flash
• Security and integrity modules
– 64-bit unique identification (ID) number per chip
– Up to 256 B EEPROM
– Up to 4 KB RAM
• Human-machine interface
– Up to 57 general-purpose input/output (GPIO)
– Two up to 8-bit keyboard interrupt modules (KBI)
– External interrupt (IRQ)
• Clocks
– Oscillator (OSC) - supports 32.768 kHz crystal or 4
MHz to 20 MHz crystal or ceramic resonator; choice
of low power or high gain oscillators
– Internal clock source (ICS) - internal FLL with
internal or external reference, 31.25 kHz pre-
trimmed internal reference for 16 MHz system clock
(able to be trimmed for up to 20 MHz system clock)
– Internal 1 kHz low-power oscillator (LPO)
• Analog modules
– One up to 16-channel 12-bit SAR ADC, operation in
Stop mode, optional hardware trigger (ADC)
– Two analog comparators containing a 6-bit DAC
and programmable reference input (ACMP)
• Timers
– One 6-channel FlexTimer/PWM (FTM)
– Two 2-channel FlexTimer/PWM (FTM)
– One 2-channel periodic interrupt timer (PIT)
– One real-time clock (RTC)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Communication interfaces
– Two SPI modules (SPI)
– Up to three UART modules (UART)
– One I2C module (I2C)
• Package options
– 64-pin QFP/LQFP
– 44-pin LQFP
– 32-pin LQFP
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
2
NXP Semiconductors
Table of Contents
1 Ordering parts.......................................................................................4
5.2.2 FTM module timing....................................................... 17
5.3 Thermal specifications.................................................................18
5.3.1 Thermal operating requirements.................................... 18
5.3.2 Thermal characteristics.................................................. 18
6 Peripheral operating requirements and behaviors................................ 20
6.1 Core modules............................................................................... 20
6.1.1 SWD electricals .............................................................20
6.2 External oscillator (OSC) and ICS characteristics.......................21
6.3 NVM specifications..................................................................... 23
6.4 Analog..........................................................................................24
6.4.1 ADC characteristics....................................................... 24
6.4.2 Analog comparator (ACMP) electricals.........................27
6.5 Communication interfaces........................................................... 27
6.5.1 SPI switching specifications.......................................... 27
7 Dimensions...........................................................................................31
7.1 Obtaining package dimensions.................................................... 31
8 Pinout................................................................................................... 32
8.1 Signal multiplexing and pin assignments.................................... 32
8.2 Device pin assignment.................................................................34
9 Revision history....................................................................................35
1.1 Determining valid orderable parts............................................... 4
2 Part identification................................................................................. 4
2.1 Description...................................................................................4
2.2 Format..........................................................................................4
2.3 Fields............................................................................................4
2.4 Example....................................................................................... 5
3 Parameter classification........................................................................5
4 Ratings..................................................................................................6
4.1 Thermal handling ratings.............................................................6
4.2 Moisture handling ratings............................................................ 6
4.3 ESD handling ratings...................................................................6
4.4 Voltage and current operating ratings..........................................7
5 General................................................................................................. 7
5.1 Nonswitching electrical specifications........................................ 7
5.1.1 DC characteristics.......................................................... 7
5.1.2 Supply current characteristics........................................ 14
5.1.3 EMC performance..........................................................15
5.2 Switching specifications.............................................................. 16
5.2.1 Control timing................................................................ 16
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
3
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: KE02Z.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q KE## A FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KE##
A
Kinetis family
Key attribute
• KE02
• Z = M0+ core
FFF
Program flash memory size
• 16 = 16 KB
• 32 = 32 KB
• 64 = 64 KB
R
Silicon revision
• (Blank) = Main
• A = Revision after main
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
4
NXP Semiconductors
Parameter classification
Values
Field
T
Description
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• LC = 32 LQFP (7 mm x 7 mm)
• LD = 44 LQFP (10 mm x 10 mm)
• QH = 64 QFP (14 mm x 14 mm)
• LH = 64 LQFP (10 mm x 10 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 2 = 20 MHz
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MKE02Z64VQH2
3 Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods.
To give the customer a better understanding, the following classification is used and the
parameters are tagged accordingly in the tables where appropriate:
Table 1. Parameter classifications
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant sample size
across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices under
typical conditions unless otherwise noted. All values shown in the typical column are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the
parameter tables where appropriate.
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
5
Ratings
4 Ratings
4.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
VHBM
VCDM
ILAT
Description
Min.
–6000
–500
–100
Max.
+6000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 125°C
1
2
3
V
+100
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78D, IC Latch-up Test.
• Test was performed at 125 °C case temperature (Class II).
• I/O pins pass 100 mA I-test with IDD current limit at 800 mA.
• I/O pins pass +60/-100 mA I-test with IDD current limit at 1000 mA.
• Supply groups pass 1.5 Vccmax
.
• RESET pin was only tested with negative I-test due to product conditioning requirement.
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
6
NXP Semiconductors
General
4.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in the following table may
affect device reliability or cause permanent damage to the device. For functional
operating conditions, refer to the remaining tables in this document.
This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate
logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor
associated with the pin is enabled.
Table 2. Voltage and current operating ratings
Symbol
VDD
Description
Min.
–0.3
—
Max.
Unit
V
Digital supply voltage
6.0
IDD
Maximum current into VDD
Input voltage except true open drain pins
Input voltage of true open drain pins
120
VDD + 0.31
mA
V
VIN
–0.3
–0.3
–25
6
V
ID
Instantaneous maximum current single pin limit (applies to all
port pins)
25
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
1. Maximum rating of VDD also applies to VIN.
5 General
5.1 Nonswitching electrical specifications
5.1.1 DC characteristics
This section includes information about power supply requirements and I/O pin
characteristics.
Table 3. DC characteristics
Symbol
C
Descriptions
Operating voltage2
Table continues on the next page...
Min
Typical1
Max
Unit
—
—
—
2.7
—
5.5
V
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
7
Nonswitching electrical specifications
Table 3. DC characteristics (continued)
Symbol
C
P
Descriptions
Min
Typical1
Max
—
Unit
V
VOH
Output All I/O pins, except PTA2 5 V, Iload = –5 mA
VDD – 0.8
VDD – 0.8
—
—
high
voltage
and PTA3, standard-
drive strength
C
3 V, Iload = –2.5 mA
—
V
P
C
D
High current drive pins, 5 V, Iload = –20 mA
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
V
V
high-drive strength3
3 V, Iload = –10 mA
IOHT
Output Max total IOH for all ports
5 V
3 V
–100
–60
mA
high
current
—
VOL
P
C
P
C
D
Output
low
voltage
All I/O pins, standard-
drive strength
5 V, Iload = 5 mA
3 V, Iload = 2.5 mA
5 V, Iload =20 mA
3 V, Iload = 10 mA
5 V
—
—
—
—
—
—
—
—
—
—
—
—
0.8
0.8
0.8
0.8
100
60
V
V
High current drive pins,
high-drive strength3
V
V
IOLT
VIH
VIL
Output Max total IOL for all ports
low
current
mA
3 V
P
P
Input
high
voltage
All digital inputs
All digital inputs
4.5≤VDD<5.5 V
2.7≤VDD<4.5 V
0.65 × VDD
0.70 × VDD
—
—
—
—
V
V
Input low
voltage
4.5≤VDD<5.5 V
2.7≤VDD<4.5 V
—
—
—
—
—
—
0.35 ×
VDD
0.30 ×
VDD
Vhys
C
P
C
Input
hysteresi
s
All digital inputs
0.06 × VDD
—
mV
µA
µA
|IIn|
Input
Per pin (pins in high
VIN = VDD or VSS
VIN = VDD or VSS
—
—
0.1
—
1
leakage impedance input mode)
current
|IINTOT
|
Total
Pins in high impedance
input mode
2
leakage
combine
d for all
port pins
RPU
P
Pullup
resistors
All digital inputs, when
enabled (all I/O pins
other than PTA2 and
PTA3)
—
—
30.0
30.0
—
—
50.0
60.0
kΩ
4
RPU
P
D
Pullup
resistors
PTA2 and PTA3 pins
kΩ
IIC
DC
Single pin limit
VIN < VSS, VIN
VDD
>
-2
-5
—
—
2
mA
injection
Total MCU limit, includes
sum of all stressed pins
25
current5,
6, 7
CIn
C
C
Input capacitance, all pins
RAM retention voltage
—
—
—
—
—
7
pF
V
VRAM
2.0
—
1. Typical values are measured at 25 °C. Characterized, not tested.
2. Max power supply ramp rate is 500 V/ms.
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
8
NXP Semiconductors
Nonswitching electrical specifications
3. Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 support high current output.
4. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured
externally on the pin.
5. All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD. PTA2 and PTA3 are true
open drain I/O pins that are internally clamped to VSS
.
6. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger value.
7. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than
maximum injection current when the MCU is not consuming power, such as when no system clock is present, or clock rate
is very low (which would reduce overall power consumption).
Table 4. LVD and POR specification
Symbol
VPOR
C
D
C
Description
Min
1.5
4.2
Typ
1.75
4.3
Max
2.0
Unit
V
POR re-arm voltage1
VLVDH
Falling low-voltage detect
threshold—high range (LVDV
= 1)2
4.4
V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
VHYSH
C
C
C
C
C
C
Falling low- Level 1 falling
4.3
4.5
4.6
4.7
—
4.4
4.5
4.5
4.6
4.7
4.8
—
V
V
voltage
warning
threshold—
high range
(LVWV = 00)
Level 2 falling
(LVWV = 01)
Level 3 falling
(LVWV = 10)
4.6
V
Level 4 falling
(LVWV = 11)
4.7
V
High range low-voltage
detect/warning hysteresis
100
2.61
mV
V
VLVDL
Falling low-voltage detect
threshold—low range (LVDV
= 0)
2.56
2.66
VLVW1L
VLVW2L
VLVW3L
VLVW4L
VHYSDL
VHYSWL
VBG
C
C
C
C
C
C
P
Falling low- Level 1 falling
2.62
2.72
2.82
2.92
—
2.7
2.8
2.9
3.0
40
2.78
2.88
2.98
3.08
—
V
V
voltage
warning
threshold—
low range
(LVWV = 00)
Level 2 falling
(LVWV = 01)
Level 3 falling
(LVWV = 10)
V
Level 4 falling
(LVWV = 11)
V
Low range low-voltage detect
hysteresis
mV
mV
V
Low range low-voltage
warning hysteresis
Buffered bandgap output 3
—
80
—
1.14
1.16
1.18
1. Maximum is highest voltage that POR is guaranteed.
2. Rising thresholds are falling threshold + hysteresis.
3. voltage Factory trimmed at VDD = 5.0 V, Temp = 25 °C
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
9
Nonswitching electrical specifications
VDD-VOH(V)
IOH(mA)
Figure 1. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 5 V)
VDD-VOH(V)
IOH(mA)
Figure 2. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 3 V)
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
10
NXP Semiconductors
Nonswitching electrical specifications
VDD-VOH(V)
IOH(mA)
Figure 3. Typical VDD-VOH Vs. IOH (high drive strength) (VDD = 5 V)
VDD-VOH(V)
IOH(mA)
Figure 4. Typical VDD-VOH Vs. IOH (high drive strength) (VDD = 3 V)
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
11
Nonswitching electrical specifications
VOL(V)
IOL(mA)
Figure 5. Typical VOL Vs. IOL (standard drive strength) (VDD = 5 V)
VOL(V)
IOL(mA)
Figure 6. Typical VOL Vs. IOL (standard drive strength) (VDD = 3 V)
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
12
NXP Semiconductors
Nonswitching electrical specifications
VOL(V)
IOL(mA)
Figure 7. Typical VOL Vs. IOL (high drive strength) (VDD = 5 V)
VOL(V)
IOL(mA)
Figure 8. Typical VOL Vs. IOL (high drive strength) (VDD = 3 V)
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
13
Nonswitching electrical specifications
5.1.2 Supply current characteristics
This section includes information about power supply current in various operating modes.
Table 5. Supply current characteristics
C
Parameter
Symbol
Core/Bus
Freq
VDD (V)
Typical1
Max2
Unit
Temp
C
C
Run supply current FEI
mode, all modules clocks
enabled; run from flash
RIDD
20/20 MHz
10/10 MHz
1/1 MHz
5
6.7
4.5
1.5
6.6
4.4
1.45
5.3
3.7
1.5
5.3
3.7
1.4
9
—
—
mA
–40 to 105 °C
—
C
C
20/20 MHz
10/10 MHz
1/1 MHz
3
5
3
5
3
5
3
5
3
—
—
—
C
C
Run supply current FEI
mode, all modules clocks
disabled; run from flash
RIDD
RIDD
RIDD
WIDD
SIDD
20/20 MHz
10/10 MHz
1/1 MHz
—
mA
mA
mA
mA
µA
–40 to 105 °C
–40 to 105 °C
–40 to 105 °C
–40 to 105 °C
—
—
C
C
20/20 MHz
10/10 MHz
1/1 MHz
—
—
—
P
C
Run supply current FBE
mode, all modules clocks
enabled; run from RAM
20/20 MHz
10/10 MHz
1/1 MHz
14.8
—
5.2
1.45
8.8
5.1
1.4
8
—
P
C
20/20 MHz
10/10 MHz
1/1 MHz
11.8
—
—
P
C
Run supply current FBE
mode, all modules clocks
disabled; run from RAM
20/20 MHz
10/10 MHz
1/1 MHz
12.3
—
4.4
1.35
7.8
4.2
1.3
5.5
3.5
1.4
5.4
3.4
1.4
2
—
P
C
20/20 MHz
10/10 MHz
1/1 MHz
9.2
—
—
P
C
Wait mode current FEI
mode, all modules clocks
enabled
20/20 MHz
20/10 MHz
1/1 MHz
—
—
—
C
20/20 MHz
10/10 MHz
1/1 MHz
—
—
—
P
P
Stop mode supply current
no clocks active (except 1
kHz LPO clock)3
—
5
3
85
80
–40 to 105 °C
–40 to 105 °C
—
1.9
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
14
NXP Semiconductors
Nonswitching electrical specifications
Table 5. Supply current characteristics (continued)
C
Parameter
Symbol
Core/Bus
Freq
VDD (V)
Typical1
Max2
Unit
Temp
C
ADC adder to Stop
ADLPC = 1
—
—
5
86 (64-, 44-
pin
packages)
—
µA
–40 to 105 °C
ADLSMP = 1
ADCO = 1
42 (32-pin
package)
C
3
82 (64-, 44-
pin
packages)
—
MODE = 10B
ADICLK = 11B
41 (32-pin
package)
C
C
C
C
ACMP adder to Stop
LVD adder to stop4
—
—
—
—
5
3
5
3
12
12
—
—
—
—
µA
µA
–40 to 105 °C
–40 to 105 °C
128
124
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. The Max current is observed at high temperature of 105 °C.
3. RTC adder causes IDD to increase typically by less than 1 µA; RTC clock source is 1 kHz LPO clock.
4. LVD is periodically woken up from Stop by 5% duty cycle. The period is equal to or less than 2 ms.
5.1.3 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components as well as MCU software
operation play a significant role in EMC performance. The system designer must consult
the following applications notes, available on nxp.com for advice and guidance
specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-Based
Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
15
Switching specifications
5.1.3.1 EMC radiated emissions operating behaviors
Table 6. EMC radiated emissions operating behaviors for 64-pin QFP package
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
14
15
3
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
4
VRE_IEC
M
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
2. VDD = 5.0 V, TA = 25 °C, fOSC = 10 MHz (crystal), fBUS = 20 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2 Switching specifications
5.2.1 Control timing
Table 7. Control timing
Num
C
D
P
P
D
Rating
System and core clock
Bus frequency (tcyc = 1/fBus
Symbol
fSys
Min
DC
Typical1
Max
20
Unit
MHz
MHz
KHz
ns
1
2
3
4
—
—
)
fBus
DC
20
Internal low power oscillator frequency
External reset pulse width2
fLPO
0.67
1.5 ×
tcyc
1.0
—
1.25
—
textrst
5
6
D
D
Reset low drive
trstdrv
tILIH
34 × tcyc
100
—
—
—
—
ns
ns
IRQ pulse width
Asynchronous
path2
D
D
Synchronous path3
tIHIL
tILIH
1.5 × tcyc
100
—
—
—
—
ns
ns
7
8
Keyboard interrupt pulse
width
Asynchronous
path2
D
C
C
Synchronous path
—
tIHIL
tRise
tFall
1.5 × tcyc
—
10.2
9.5
—
—
—
ns
ns
ns
Port rise and fall time -
Normal drive strength
(load = 50 pF)4
—
—
C
C
Port rise and fall time -
high drive strength (load =
50 pF)4
—
tRise
tFall
—
—
5.4
4.6
—
—
ns
ns
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16
NXP Semiconductors
Switching specifications
1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.
3. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
4. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C.
textrst
RESET_b pin
Figure 9. Reset timing
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 10. KBIPx timing
5.2.2 FTM module timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the
fastest clock that can be used as the optional external source to the timer counter. These
synchronizers operate from the current bus rate clock.
Table 8. FTM input timing
C
Function
Symbol
Min
Max
Unit
D
External clock
frequency
fTCLK
0
fBus/4
Hz
D
D
D
D
External clock
period
tTCLK
tclkh
4
—
—
—
—
tcyc
tcyc
tcyc
tcyc
External clock high
time
1.5
1.5
1.5
External clock low
time
tclkl
Input capture pulse
width
tICPW
tTCLK
tclkh
TCLK
tclkl
Figure 11. Timer external clock
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
17
Thermal specifications
tICPW
FTMCHn
FTMCHn
tICPW
Figure 12. Timer input capture pulse
5.3 Thermal specifications
5.3.1 Thermal operating requirements
Table 9. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
105
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + θJA x chip power dissipation
5.3.2 Thermal characteristics
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-
determined rather than being controlled by the MCU design. To take PI/O into account in
power calculations, determine the difference between actual pin voltage and VSS or VDD
and multiply by the pin current for each I/O pin. Except in cases of unusually high pin
current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
Table 10. Thermal attributes
Board type
Symbol
Description
64
64 QFP
44
32
Unit
Notes
LQFP
LQFP
LQFP
Single-layer (1S)
RθJA
Thermal resistance, junction
to ambient (natural
convection)
71
61
75
86
°C/W
1, 2
Four-layer (2s2p)
RθJA
Thermal resistance, junction
to ambient (natural
convection)
53
47
53
57
°C/W
1, 3
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
18
NXP Semiconductors
Thermal specifications
Table 10. Thermal attributes (continued)
Board type
Symbol
Description
64
64 QFP
44
32
Unit
Notes
LQFP
LQFP
LQFP
Single-layer (1S)
RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
59
50
62
72
°C/W
1, 3
Four-layer (2s2p)
RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
46
41
47
51
°C/W
1, 3
—
—
—
RθJB
RθJC
ΨJT
Thermal resistance, junction
to board
35
20
5
32
23
8
34
20
5
33
24
6
°C/W
°C/W
°C/W
4
5
6
Thermal resistance, junction
to case
Thermal characterization
parameter, junction to
package top outside center
(natural convection)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization.
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts - chip internal power
PI/O = Power dissipation on input and output pins - user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship
between PD and TJ (if PI/O is neglected) is:
PD = K ÷ (TJ + 273 °C)
Solving the equations above for K gives:
K = PD × (TA + 273 °C) + θJA × (PD)2
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
19
Peripheral operating requirements and behaviors
where K is a constant pertaining to the particular part. K can be determined by measuring
PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can
be obtained by solving the above equations iteratively for any value of TA.
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 SWD electricals
Table 11. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
5.5
V
J1
SWD_CLK frequency of operation
• Serial wire debug
0
20
—
MHz
ns
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
3
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
35
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 13. Serial wire clock input timing
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
20
NXP Semiconductors
Peripheral operating requirements and behaviors
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
J12
J11
Output data valid
Figure 14. Serial wire data timing
6.2 External oscillator (OSC) and ICS characteristics
Table 12. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)
Num
C
C
C
Characteristic
Low range (RANGE = 0)
High range (RANGE = 1)
Symbol
Min
31.25
4
Typical1
32.768
—
Max
39.0625
20
Unit
kHz
1
Crystal or
resonator
frequency
flo
fhi
MHz
2
3
D
D
Load capacitors
C1, C2
RF
See Note2
—
Feedback
resistor
Low Frequency, Low-Power
Mode3
—
—
—
—
—
—
—
—
MΩ
MΩ
MΩ
MΩ
Low Frequency, High-Gain
Mode
10
1
High Frequency, Low-
Power Mode
High Frequency, High-Gain
Mode
1
2
4
5
D
D
Series resistor -
Low Frequency
Low-Power Mode 3
High-Gain Mode
Low-Power Mode3
RS
—
—
—
0
200
0
—
—
—
kΩ
kΩ
kΩ
2
Series resistor -
High Frequency
RS
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KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
21
Peripheral operating requirements and behaviors
Table 12. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)
(continued)
Num
C
D
D
D
Characteristic
4 MHz
Symbol
Min
—
Typical1
Max
—
Unit
kΩ
Series resistor -
High
0
0
0
8 MHz
—
—
kΩ
Frequency,
High-Gain Mode
16 MHz
—
—
kΩ
6
C
C
C
C
Crystal start-up
time low range
= 32.768 kHz
crystal; High
range = 20 MHz
crystal4,5
Low range, low power
Low range, high gain
High range, low power
High range, high gain
tCSTL
—
—
—
—
1000
800
3
—
—
—
—
ms
ms
ms
ms
tCSTH
1.5
7
8
T
P
Internal reference start-up time
tIRST
fint_t
—
20
—
50
µs
Internal reference clock (IRC) frequency trim
range
31.25
39.0625
kHz
9
P
Internal
T = 25 °C, VDD = 5 V
fint_ft
—
31.25
—
kHz
reference clock
frequency,
factory trimmed,
10
11
P
P
DCO output
frequency range
FLL reference = fint_t, flo,
or fhi/RDIV
fdco
16
—
—
20
MHz
%
Factory trimmed
internal
T = 25 °C, VDD = 5 V
Δfint_ft
-0.5
0.5
oscillator
accuracy6
12
13
C
C
Deviation of IRC Over temperature range
Δfint_t
Δfint_t
-1
—
—
0.5
0.5
%
%
over
from -40 °C to 105°C
temperature
when trimmed
at T = 25 °C,
VDD = 5 V
Over temperature range
from 0 °C to 105°C
-0.5
Frequency
accuracy of
DCO output
using factory
trim value
Over temperature range
from -40 °C to 105°C
Δfdco_ft
Δfdco_ft
-1.5
-1
—
—
1
1
Over temperature range
from 0 °C to 105°C
14
15
C
C
FLL acquisition time4,7
tAcquire
CJitter
—
—
—
2
ms
Long term jitter of DCO output clock
(averaged over 2 ms interval)8
0.02
0.2
%fdco
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. See crystal or resonator manufacturer's recommendation.
3. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =
0.
4. This parameter is characterized and not tested on each device.
5. Proper PC board layout procedures must be followed to achieve specifications.
6. The accuracy is for factory trimmed deviation when performing trim process in NXP, however, the reflow process may
cause an extra 0.5% drift at the room temperature.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
22
NXP Semiconductors
Peripheral operating requirements and behaviors
8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
OSC
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 15. Typical crystal or resonator circuit
6.3 NVM specifications
This section provides details about program/erase times and program/erase endurance for
the flash and EEPROM memories.
Table 13. Flash and EEPROM characteristics
C
Characteristic
Symbol
Min1
Typical2
Max3
Unit4
D
Supply voltage for program/erase –40
°C to 105 °C
Vprog/erase
2.7
—
5.5
V
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Supply voltage for read operation
NVM Bus frequency
VRead
fNVMBUS
fNVMOP
tVFYALL
tRD1BLK
tRD1BLK
tRD1SEC
tDRD1SEC
tRDONCE
tPGM2
2.7
1
—
—
5.5
25
V
MHz
MHz
tcyc
tcyc
tcyc
tcyc
tcyc
tcyc
ms
ms
ms
ms
ms
ms
NVM Operating frequency
Erase Verify All Blocks
Erase Verify Flash Block
Erase Verify EEPROM Block
Erase Verify Flash Section
Erase Verify EEPROM Section
Read Once
0.8
—
1
1.05
17338
16913
810
—
—
—
—
—
—
—
484
—
—
555
—
—
450
Program Flash (2 word)
Program Flash (4 word)
Program Once
0.12
0.20
0.20
0.10
0.17
0.25
0.12
0.21
0.21
0.10
0.18
0.26
0.29
0.46
0.21
0.27
0.43
0.60
tPGM4
tPGMONCE
tDPGM1
tDPGM2
tDPGM3
Program EEPROM (1 Byte)
Program EEPROM (2 Byte)
Program EEPROM (3 Byte)
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KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
23
Peripheral operating requirements and behaviors
Table 13. Flash and EEPROM characteristics
(continued)
C
D
D
D
D
D
D
D
D
C
Characteristic
Symbol
tDPGM4
tERSALL
tERSBLK
tERSPG
Min1
0.32
96.01
95.98
19.10
4.81
96.01
—
Typical2
Max3
0.77
Unit4
ms
Program EEPROM (4 Byte)
Erase All Blocks
0.33
100.78
100.75
20.05
5.05
101.49
101.44
20.08
20.57
101.48
464
ms
Erase Flash Block
ms
Erase Flash Sector
ms
Erase EEPROM Sector
Unsecure Flash
tDERSPG
tUNSECU
tVFYKEY
tMLOADU
nFLPE
ms
100.78
—
ms
Verify Backdoor Access Key
Set User Margin Level
tcyc
—
—
407
tcyc
FLASH Program/erase endurance TL to
TH = -40 °C to 105 °C
10 k
100 k
—
Cycles
C
C
EEPROM Program/erase endurance TL
to TH = -40 °C to 105 °C
nFLPE
tD_ret
50 k
15
500 k
100
—
—
Cycles
years
Data retention at an average junction
temperature of TJavg = 85°C after up to
10,000 program/erase cycles
1. Minimum times are based on maximum fNVMOP and maximum fNVMBUS
2. Typical times are based on typical fNVMOP and maximum fNVMBUS
3. Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
4. tcyc = 1 / fNVMBUS
Program and erase operations do not require any special power sources other than the
normal VDD supply. For more detailed information about program/erase operations, see
the Flash Memory Module section in the reference manual.
6.4 Analog
6.4.1 ADC characteristics
Table 14. 5 V 12-bit ADC operating conditions
Characteri
stic
Conditions
Symbol
Min
Typ1
Max
Unit
Comment
Reference
potential
• Low
• High
VREFL
VREFH
VDDA
VSSA
VDDA
2.7
—
—
—
0
VSSA
VDDA
5.5
V
—
Supply
voltage
Absolute
V
—
—
—
Delta to VDD (VDD-VDDA
Delta to VSS (VSS-VSSA
)
ΔVDDA
ΔVSSA
-100
-100
+100
+100
mV
mV
Ground
voltage
)
0
Input
VADIN
VREFL
—
VREFH
V
—
voltage
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KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
24
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 14. 5 V 12-bit ADC operating conditions (continued)
Characteri
stic
Conditions
Symbol
CADIN
RADIN
RAS
Min
Typ1
4.5
3
Max
5.5
5
Unit
Comment
Input
capacitance
—
pF
—
—
Input
resistance
—
kΩ
Analog
source
resistance
12-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
kΩ
External to
MCU
—
—
—
—
2
5
•
•
10-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
—
—
—
—
—
—
5
•
•
10
10
8-bit mode
(all valid fADCK
)
ADC
conversion
clock
High speed (ADLPC=0)
Low power (ADLPC=1)
fADCK
0.4
0.4
—
—
8.0
4.0
MHz
—
frequency
1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
SIMPLIFIED
INPUT PIN EQUIVALENT
z ADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
R AS
R ADIN
protection
v ADIN
C AS
v AS
R ADIN
R ADIN
R ADIN
INPUT PIN
INPUT PIN
INPUT PIN
C ADIN
Figure 16. ADC input impedance equivalency diagram
Table 15. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Characteristic
Conditions
C
Symbol
Min
Typ1
Max
Unit
Supply current
T
IDDA
—
133
—
µA
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KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
25
Peripheral operating requirements and behaviors
Table 15. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Characteristic
Conditions
C
Symbol
Min
Typ1
Max
Unit
ADLPC = 1
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 1
ADLSMP = 0
ADCO = 1
T
IDDA
—
218
—
µA
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
T
T
IDDA
—
—
327
582
—
µA
µA
Supply current
ADLPC = 0
ADLSMP = 0
ADCO = 1
IDDA
990
Supply current
Stop, reset, module
off
T
P
IDDA
—
2
0.011
3.3
2
1
5
µA
ADC asynchronous High speed (ADLPC
clock source
fADACK
MHz
= 0)
Low power (ADLPC
= 1)
1.25
—
3.3
—
—
—
—
Conversion time
(including sample
time)
Short sample
(ADLSMP = 0)
T
T
tADC
20
ADCK
cycles
Long sample
(ADLSMP = 1)
—
40
Sample time
Short sample
(ADLSMP = 0)
tADS
—
3.5
23.5
ADCK
cycles
Long sample
—
(ADLSMP = 1)
Total unadjusted
Error2
12-bit mode3
10-bit mode
8-bit mode
T
P
T
T
P
T
T
T
T
C
P
T
ETUE
DNL
INL
—
—
—
—
—
—
—
—
—
—
—
—
3.6
1.5
—
LSB4
LSB4
LSB4
LSB4
2.0
1.0
—
0.7
Differential Non-
Liniarity
12-bit mode
10-bit mode5
8-bit mode5
1.0
0.25
0.15
1.0
0.5
0.25
—
Integral Non-Linearity 12-bit mode3
10-bit mode
0.3
0.5
0.25
—
8-bit mode
0.15
2.0
Zero-scale error6
12-bit mode
10-bit mode
8-bit mode
EZS
0.25
0.65
1.0
1.0
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 15. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Characteristic
Conditions
12-bit mode
10-bit mode
8-bit mode
C
T
Symbol
Min
—
Typ1
Max
—
Unit
Full-scale error7
EFS
2.5
LSB4
T
—
0.5
1.0
1.0
0.5
T
—
0.5
Quantization error
≤12 bit modes
D
D
D
EQ
EIL
m
—
—
LSB4
mV
Input leakage error8 all modes
Temp sensor slope -40 °C–25 °C
25 °C–125 °C
Temp sensor voltage 25 °C
IIn * RAS
3.266
3.638
1.396
—
—
—
—
—
—
mV/°C
D
VTEMP25
V
1. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. Includes quantization
3. This parameter is valid for the temperature range of 25 °C to 50 °C.
4. 1 LSB = (VREFH - VREFL)/2N
5. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes
6. VADIN = VSSA
7. VADIN = VDDA
8. IIn = leakage current (refer to DC characteristics)
6.4.2 Analog comparator (ACMP) electricals
Table 16. Comparator electrical specifications
C
D
T
Characteristic
Supply voltage
Symbol
VDDA
IDDA
VAIN
VAIO
VH
Min
2.7
Typical
—
Max
5.5
20
Unit
V
Supply current (Operation mode)
Analog input voltage
—
10
µA
V
D
P
C
C
T
VSS - 0.3
—
—
VDDA
40
Analog input offset voltage
Analog comparator hysteresis (HYST=0)
Analog comparator hysteresis (HYST=1)
Supply current (Off mode)
Propagation Delay
—
mV
mV
mV
nA
µs
—
15
20
VH
—
20
30
IDDAOFF
tD
—
60
—
C
—
0.4
1
6.5 Communication interfaces
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
27
Peripheral operating requirements and behaviors
6.5.1 SPI switching specifications
The serial peripheral interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. See the SPI chapter of the
chip's reference manual for information about the modified transfer formats used for
communicating with slower peripheral devices. All timing is shown with respect to 20%
VDD and 80% VDD, unless noted, and 25 pF load on all SPI pins. All timing assumes
high-drive strength is enabled for SPI output pins.
Table 17. SPI master mode timing
Nu
m.
Symbol Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
fBus/2048
fBus/2
Hz
fBus is the bus
clock
2
3
tSPSCK
tLead
tLag
SPSCK period
Enable lead time
Enable lag time
2 x tBus
2048 x tBus
ns
tSPSCK
tSPSCK
ns
tBus = 1/fBus
1/2
—
—
—
—
—
—
—
—
—
4
1/2
—
5
tWSPSCK Clock (SPSCK) high or low time
tBus – 30
1024 x tBus
6
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
8
8
—
—
ns
7
ns
8
tv
—
20
—
25
ns
9
tHO
tRI
—
ns
10
tBus – 25
ns
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
28
NXP Semiconductors
Peripheral operating requirements and behaviors
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. SPI master mode timing (CPHA=0)
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI master mode timing (CPHA=1)
Table 18. SPI slave mode timing
Nu
m.
Symbol
Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
0
fBus/4
Hz
fBus is the bus clock as
defined in Control timing.
2
3
tSPSCK
tLead
SPSCK period
4 x tBus
1
—
—
ns
tBus = 1/fBus
—
Enable lead time
tBus
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
29
Peripheral operating requirements and behaviors
Table 18. SPI slave mode timing (continued)
Nu
m.
Symbol
Description
Min.
Max.
Unit
Comment
4
5
6
7
8
tLag
Enable lag time
1
tBus - 30
15
—
—
tBus
ns
ns
ns
ns
—
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
—
25
—
—
tBus
Time to data active from
high-impedance state
9
tdis
Slave MISO disable time
—
tBus
ns
Hold time to high-
impedance state
10
11
12
tv
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
—
0
25
—
ns
ns
ns
—
—
—
tHO
tRI
—
tBus - 25
tFI
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
SS
(INPUT)
2
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
12
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 19. SPI slave mode timing (CPHA = 0)
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
30
NXP Semiconductors
Dimensions
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
NOTE: Not defined
Figure 20. SPI slave mode timing (CPHA=1)
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
Then use this document number
98ASH70029A
32-pin LQFP
44-pin LQFP
64-pin QFP
64-pin LQFP
98ASS23225W
98ASB42844B
98ASS23234W
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
31
Pinout
8 Pinout
8.1 Signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
Table 19. Pin availability by package pin-count
Pin Number
44-LQFP
Lowest Priority <-- --> Highest
64-QFP/
LQFP
32-LQFP
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
1
1
2
1
2
PTD11
PTD01
PTH7
PTH6
PTE7
PTH2
—
KBI1_P1
FTM2_CH3
SPI1_MOSI
—
2
KBI1_P0
FTM2_CH2
SPI1_SCK
—
—
3
—
—
3
—
—
—
—
3
—
—
—
4
—
—
FTM2_CLK
BUSOUT
—
—
—
5
—
—
FTM1_CH1
FTM1_CH0
VDD
6
4
—
—
7
5
—
—
8
6
4
—
—
—
VDDA
VREFH2
VREFL
VSS3
9
7
5
—
—
—
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
8
6
—
—
—
VSSA
9
7
PTB7
PTB6
—
—
I2C0_SCL
I2C0_SDA
—
—
EXTAL
XTAL
10
11
—
—
—
—
12
13
14
15
16
17
18
19
20
—
8
—
—
—
—
—
—
—
9
—
—
—
VSS
PTH11
PTH01
PTE6
PTE5
PTB51
PTB41
PTC3
PTC2
PTD7
PTD6
PTD5
PTC1
PTC0
PTF7
FTM2_CH1
FTM2_CH0
—
—
—
—
—
—
—
—
—
—
—
—
—
FTM2_CH5
FTM2_CH4
FTM2_CH3
FTM2_CH2
KBI1_P7
KBI1_P6
KBI1_P5
—
SPI0_PCS0
SPI0_MISO
—
ACMP1_OUT
—
10
11
12
—
—
—
13
14
—
NMI
—
—
—
—
—
—
—
—
ACMP1_IN2
ADC0_SE11
ADC0_SE10
—
—
UART2_TX
UART2_RX
—
—
—
FTM2_CH1
FTM2_CH0
—
ADC0_SE9
ADC0_SE8
ADC0_SE15
—
—
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
32
NXP Semiconductors
Pinout
Table 19. Pin availability by package pin-count (continued)
Pin Number
Lowest Priority <-- --> Highest
64-QFP/
LQFP
44-LQFP
32-LQFP
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
—
—
—
21
22
23
24
—
—
25
26
—
27
28
—
—
29
30
31
32
33
34
35
36
37
—
38
—
—
—
—
39
40
41
42
43
44
—
—
—
15
16
17
18
—
—
19
20
—
—
—
—
—
—
21
22
23
24
25
26
27
28
—
—
—
—
—
—
—
—
29
30
31
32
PTF6
PTF5
PTF4
PTB3
PTB2
PTB1
PTB0
PTF3
PTF2
PTA7
PTA6
PTE4
—
—
—
—
—
ADC0_SE14
—
—
ADC0_SE13
—
—
—
ADC0_SE12
KBI0_P7
SPI0_MOSI
SPI0_SCK
UART0_TX
UART0_RX
—
FTM0_CH1
ADC0_SE7
KBI0_P6
FTM0_CH0
ADC0_SE6
KBI0_P5
—
ADC0_SE5
KBI0_P4
—
ADC0_SE4
—
—
—
—
—
—
—
—
FTM2_FLT2
FTM2_FLT1
—
ACMP1_IN1
ADC0_SE3
—
ACMP1_IN0
ADC0_SE2
—
—
—
—
—
—
VSS
—
—
—
—
—
VDD
PTF1
PTF0
PTD4
PTD3
PTD2
PTA34
PTA24
PTA1
PTA0
PTC7
PTC6
PTE3
PTE2
PTG3
PTG2
PTG1
PTG0
PTE11
PTE01
PTC5
PTC4
PTA5
PTA4
—
—
—
—
—
—
—
KBI1_P4
KBI1_P3
KBI1_P2
KBI0_P3
KBI0_P2
KBI0_P1
KBI0_P0
—
—
—
—
SPI1_PCS0
SPI1_MISO
UART0_TX
UART0_RX
FTM0_CH1
FTM0_CH0
UART1_TX
UART1_RX
SPI0_PCS0
SPI0_MISO
—
—
—
—
—
I2C0_SCL
—
I2C0_SDA
—
ACMP0_IN1
ADC0_SE1
ACMP0_IN0
ADC0_SE0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SPI0_MOSI
SPI0_SCK
FTM1_CH1
FTM1_CH0
FTM0_CLK
ACMP0_OUT
—
—
—
FTM1_CLK
—
—
—
RTCO
SWD_CLK
RESET
SWD_DIO
RTCO
IRQ
ACMP0_IN2
—
—
—
1. This is a high-current drive pin when operated as output.
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
33
Pinout
2. VREFH and VDDA are internally connected.
3. VSSA and VSS are internally connected.
4. This is a true open-drain pin when operated as output.
Note
When an alternative function is first enabled, it is possible to
get a spurious edge to the module. User software must clear any
associated flags before interrupts are enabled. Table 19
illustrates the priority if multiple modules are enabled. The
highest priority module will have control over the pin. Selecting
a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority
module. Disable all modules that share a pin before enabling
another module.
8.2 Device pin assignment
2
2
1
1
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTA2
PTA3
PTD1
PTD0
PTH7
PTH6
3
PTD2
PTD3
PTD4
PTF0
PTF1
VDD
4
PTE7
5
6
PTH2
VDD
7
8
VDDA/VREFH
VREFL
9
VSS
VSSA/VSS
10
11
12
13
14
15
16
PTE4
PTA6
PTA7
PTF2
PTF3
PTB0
PTB1
PTB7
PTB6
VSS
1
PTH1
1
PTH0
PTE6
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
Figure 21. 64-pin QFP/LQFP packages
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
34
NXP Semiconductors
Revision history
2
1
1
33
32
31
30
29
28
27
26
25
24
23
1
2
PTA2
PTD1
PTD0
PTA32
PTD2
PTD3
PTD4
VDD
3
PTE7
4
PTH2
5
VDD
VDDA/VREFH
6
7
VREFL
VSS
VSSA/VSS
8
PTA6
PTA7
PTB0
PTB1
9
PTB7
PTB6
10
11
VSS
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
Figure 22. 44-pin LQFP package
1
2
PTD1
PTD0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PTA2
1
PTA32
PTD2
PTD3
PTA6
PTA7
PTB0
PTB1
VDD
VDDA/VREFH
VREFL
VSSA/VSS
PTB7
PTB6
1. High source/sink current pins
2. True open drain pins
Figure 23. 32-pin LQFP package
9 Revision history
The following table provides a revision history for this document.
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
NXP Semiconductors
35
Revision history
Table 20. Revision history
Rev. No.
Date
Substantial Changes
3
4
07/2013
10/2014
Initial public release.
• Updated all the VDDAD to VDDA, VSSAD to VSSA
• Updated the features of OSC, ICS, UART, KBI and ADC in the front
page
• Updated ILAT and VCDM in the ESD handling ratings
• Added VIN and removed VDIO, VAIO in the Voltage and current
operating ratings
• Updated DC characteristics
• Added the item of ACMP adder to Stop and a note to the Max. in
Supply current characteristics
• Added EMC radiated emissions operating behaviors
• Added fSys and a note to tIHIL in the Control timing
• Added a new section of Thermal operating requirements
• Updated J1, J10 and J11 in the SWD electricals
• Updated External oscillator (OSC) and ICS characteristics
• Added reference potential and a note to the ETUE and EZS in ADC
characteristics
• Updated SPI switching specifications
5
6
07/2016
01/2019
• Updated the Typical value of ETUE in 12-bit mode and added a note
to the 12-bit mode of ETUE and INL in the ADC characteristics.
• Added a footnote of "Max power suppply ramp rate is 500 V/ms." to
Operating voltage in the DC characteristics.
• Added a footnote to the Δfint_ft in the External oscillator (OSC) and
ICS characteristics
KE02 Sub-Family Data Sheet, Rev. 6, 01/2019
36
NXP Semiconductors
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Document Number MKE02P64M20SF0
Revision 6, 01/2019
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