935316435557 [NXP]
RISC Microcontroller;
| 型号： | 935316435557 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 时钟 微控制器 外围集成电路 |
| 文件： | 总77页 (文件大小：1085K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number SAC57D54H
Rev. 7, 05/2017
NXP Semiconductors
Data Sheet: Technical Data
SAC57D54H
SAC57D54H
Features
• Debug functionality
– Run-time debug control of cores and visibility of
system resources using the Debug Access Port
(DAP)
– IEEE 1149.1/ IEEE 1149.7 System JTAG Controller
(SJTAG)
– Program and Data Trace support (16-bit data width)
implemented by the ARM Trace Port Interface Unit
(TPIU) Trace capture
• ARM™ Cortex-A5, 32-bit CPU
– Supports ARMv7- ISA
– 32 KB Instruction cache, 32 KB Data cache
– NEON SIMD Media Processing Engine
– FPU supporting double precision floating point
operations
– Memory Management Unit
– GIC Interrupt Controller
– Up to 320 MHz
• Timer
– Four 8-channel Flextimer modules (FTM)
– Two 4 channel System Timer Module (STM)
– Three Software WatchDog Timers (SWT)
– One 8 channel Periodic Interrupt Timer (PIT)
– Autonomous Real Time Counter (RTC)
• ARM™ Cortex-M4, 32-bit CPU
– Supports ARMv7 - ISA
– 16 KB Instruction cache, 16 KB Data cache
– 64 KB Tightly-Coupled Memory (TCM)
– Single Precision FPU
– NVIC Interrupts Controller
• Analog
– 1.25 DMIPS per MHz integer performance
– Up to 160 MHz
– 1 x 24 channel, 12-bit analog-to-digital converter
(ADC)
– 2 analog comparators (CMP)
• I/O Processor
– ARM™ Cortex-M0+, 32-bit CPU
– Intelligent Stepper Motor Drive
• Security
– Cryptographic Services Engine (CSE)
• Memory subsystem
• Safety
– System Memory Protection Unit
– 4 MB on-chip flash supported with the flash
controller
– 1 MB on-chip SRAM with ECC
– 1.3 MB on-chip Graphics SRAM with FlexECC
– ISO26262 ASIL-B compliance
– Password and Device Security (PASS) supporting
advanced censorship and life-cycle management
– One Fault Collection and Control Unit (FCCU) to
collect faults and issue interrupts
• Supports wake-up from low power modes via the
WKPU controller
• Multiple operating modes
– Includes enhanced low power operation
• On-chip voltage regulator
• Memory interfaces
– External 3.3 V input supply
– 2 x Dual QuadSPI Serial flash controllers
– Supports SDR and DDR serial flash
– Support for 3.3 V Hyperflash (Spansion)
– DRAM controller supporting SDR and DDR2
– Option for direct, external supply of core voltage
– Low Voltage Detect (LVD) and High Voltage
Detect (HVD) on various supplies and regulators
• Clock interfaces
– 8-40 MHz external crystal (FXOSC)
– 16 MHz IRC (FIRC)
– 128 kHz IRC (SIRC)
– 32 kHz external crystal (SXOSC)
– Clock Monitor Unit (CMU)
– Frequency modulated phase-locked loop (FMPLL)
– Real Time Counter (RTC)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Graphics interfaces
– Vivante GC355 GPU supporting OpenVG 1.1
– 2 x 2D-ACE Display Controllers (with inline Head-Up-Display warping)
– Digital RGB, TCON_0 (RSDS), TCON_1 and OpenLDI/LVDS output options
– Digital Video Input (VIU4)
– RLE Decoder for memory-memory decompression
– 40x4 segment LCD driver, reconfigurable as 38x6 or 36x8
• Cluster peripherals
– Sound Generator Module (SGM)
– 6 Stepper Motor Drivers with Stepper Stall Detect
• Communication
– Ethernet 10/100 + AVB (ENET)
– MLB50
– FlexCAN x 3
– DSPI x 5
– LINFlexD x 3 (1 x Master/Slave, 2 x Master only)
– I2C x 2
• eDMA controller with multiple transfer request sources using DMAMUX
• Boot Assist Flash (BAF) supports internal flash programming
SAC57D54H, Rev. 7, 05/2017
2
NXP Semiconductors
Table of Contents
1
2
3
Block diagram.................................................................................... 5
6.2.2 Slow Oscillator (SXOSC) electrical specifications ..32
6.2.3 Fast internal RC Oscillator (FIRC) electrical
Family comparison.............................................................................6
Ordering parts.....................................................................................8
3.1 Determining valid orderable parts ..........................................8
3.2 Ordering information ..............................................................8
General............................................................................................... 9
4.1 Absolute maximum ratings..................................................... 9
4.2 Recommended operating conditions....................................... 10
4.3 Voltage regulator electrical specifications.............................. 11
4.3.1 Decoupling capacitor values......................................12
4.4 Voltage monitor electrical specifications................................13
4.5 Power consumption.................................................................14
4.6 Electrostatic discharge (ESD) specifications.......................... 15
4.7 Electromagnetic Compatibility (EMC) specifications............ 16
I/O parameters....................................................................................16
5.1 AC specifications @ 3.3 V range............................................16
5.2 DC electrical specifications @ 3.3 V range............................ 17
5.3 AC specifications @ 5 V range...............................................17
5.4 DC electrical specifications @ 5 V range............................... 18
5.5 DDR2 pads IO specifications..................................................19
5.5.1 DDR2 pads AC specifications @ 1.8V
specifications............................................................. 32
6.2.4 Slow internal RC oscillator (SIRC) electrical
specifications ............................................................ 32
4
6.2.5 PLL electrical specifications .................................... 33
6.3 Memory interfaces...................................................................34
6.3.1 Flash memory specifications..................................... 34
6.3.1.1
6.3.1.2
6.3.1.3
Flash memory program and erase
specifications......................................... 34
Flash memory Array Integrity and
Margin Read specifications................... 35
Flash memory module life
specifications......................................... 36
Data retention vs program/erase cycles. 36
Flash memory AC timing
5
6.3.1.4
6.3.1.5
specifications......................................... 37
Flash read wait state and address
6.3.1.6
pipeline control settings ........................38
6.3.2 QuadSPI AC specifications....................................... 38
6.3.2.1
6.3.2.2
6.3.2.3
SDR mode..............................................39
DDR mode.............................................40
HyperFlash mode...................................42
VDDE_DDR..............................................................19
5.5.2 SSTL_18 Class II 1.8 V DDR2 DC specifications....20
5.6 SMC pads IO specifications....................................................21
5.6.1 SMC 5V pads IO specifications................................ 21
6.3.3 SDR AC specifications..............................................43
6.3.3.1 SDR DC specifications..........................45
5.6.1.1
5.6.1.2
SMC 5V pads IO DC specifications......21
SMC 5V pads IO AC specifications......22
6.3.4 DDR2 SDRAM AC specifications............................45
6.4 Communication modules.........................................................48
6.4.1 SPI electrical specifications.......................................48
6.4.2 Ethernet AC specifications........................................54
6.4.3 MediaLB (MLB) electrical specifications.................55
5.6.2 SMC 3.3 V pads IO specifications............................ 22
5.6.2.1
5.6.2.2
SMC 3.3 V pads IO DC specifications..22
SMC 3.3 V pads IO AC specifications..22
5.7 RSDS pads electrical specifications........................................23
5.8 LVDS pads electrical specifications....................................... 25
5.9 Functional reset pad electrical specifications..........................26
5.10 PORST electrical specifications..............................................26
Peripheral operating requirements and behaviors..............................27
6.1 Analog modules.......................................................................27
6.1.1 ADC electrical specifications....................................27
6.1.2 Analog Comparator (CMP) electrical specifications 29
6.2 Clocks and PLL interfaces modules........................................30
6.2.1 Fast Oscillator (FXOSC) electrical specifications.... 30
6.4.3.1
MLB 3-wire interface DC
specifications......................................... 55
MLB 3-wire interface electrical
6.4.3.2
specifications......................................... 56
6
6.5 Display modules......................................................................58
6.5.1 LCD driver electrical specifications..........................58
6.5.2 2D-ACE electrical specifications.............................. 58
6.5.2.1
Interface to TFT LCD Panels (2D-
ACE)......................................................58
SAC57D54H, Rev. 7, 05/2017
NXP Semiconductors
3
6.5.2.2
6.5.2.3
Interface to TFT LCD Panels—pixel
level timings...........................................59
Interface to TFT LCD panels—access
level........................................................61
6.7.1 JTAG interface timing ..............................................65
6.7.2 Debug trace timing specifications............................. 67
6.7.3 Wakeup Unit (WKPU) AC specifications.................68
6.7.4 External interrupt timing (IRQ pin)...........................68
Thermal attributes.............................................................................. 69
7.1 Thermal attributes................................................................... 69
Dimensions.........................................................................................71
8.1 Obtaining package dimensions ...............................................71
Pinouts................................................................................................71
9.1 Package pinouts and signal descriptions................................. 71
6.5.3 Video input unit (VIU4) electrical specifications..... 62
6.5.4 TCON electrical specifications..................................63
7
8
9
6.5.4.1
6.5.4.2
TCON RSDS electrical specifications...63
TCON TTL electrical specifications......63
6.6 Motor control modules............................................................64
6.6.1 Stepper Stall Detect (SSD) specifications................. 64
6.7 Debug specifications............................................................... 65
10 Revision History.................................................................................71
SAC57D54H, Rev. 7, 05/2017
4
NXP Semiconductors
Block diagram
1 Block diagram
RGB
LVDS
RSDS / RGB
System Modules
NVIC
RSDS
TCON_0
OpenLDI/LVDS
LDB
ARM
Cortex A5
GC355
GPU
TCON_1
ARM
Cortex M4
GIC
NEON
FPU
OpenVG 1.1
Tiny UI
I/O Ctrl
FPU
Reset Ctrl
2D-ACE
HUD Warping
32KB L1 32KB L1
D-Cache I-Cache
2D-ACE
16KB L1 16KB L1
D-Cache I-Cache
64KB
TCM
INT Router
Temp Sensor
MBIST
Code
System
64 64
64
64
64
32
64
32
32
64
64
64
64
64
Clocking
4-40MHz/32KHz
XOSC
System Bus
Memory Protection
16MHz/128KHz
IRC
AHB 64
AHB 64
AHB 64
AXI 64
AHB 64
AXI 64 AHB 64
AHB
AHB
AHB 64
AHB 64
AHB 64
AHB 64
64
64
Pixel
Converter
PLLs
Clock Monitor
Port Splitter
Boot ROM
DRAM Controller
16/32-bit
Flash memory BIU
512kB
System
SRAM (ECC)
512kB
System
SRAM (ECC)
1.3MB
GRAM
2 - 4MB
Flash memory (ECC)
Power
SDR
(FlexECC)
LVD / HVD
DDR2
EE Emulation
OTP
Low Power Ctrl
AIPS
Debug
SJTAG
Interrupt
Router
TPIU
IOP
ARM
4k and 2k ETBs
CortexM0+
Peripheral
Interrupts
32k SRAM
(ECC)
Figure 1. High level block diagram
SAC57D54H, Rev. 7, 05/2017
NXP Semiconductors
5
Family comparison
320MHz Domain
ARM
160MHz Domain
Cortex A5
NEON
FPU
ARM
Cortex M4
GC355
OpenVG GPU
32KB L1 32KB L1
D-Cache I-Cache
FPU
16KB L1 16KB L1
D-Cache I-Cache
64KB
TCM
64
64
Code
System
64
64
64
64
64
64
64
RDC - 8 domain, 1MDAC per master, 2x MDAC per CPU.,
64
32
64
AHB 64
M7
AHB 64
M5
64
64
M0
M1
M3
M4
M2
M10
M12
M16
M8 M9
M11
QoS301
M13
M15
M14
AMBA AXBS
S0
S7
S5
S6
S3
S4
S14
S15
S16
S1
S8 S9 S10 S11
S12
S13
S17
SDAC5 [0..3] (AXI)
S2
SDCAC1 [0..15] (AHB)
SDAC0 [0..15] (AHB)
SDAC2 [0..3] (AXI)
Port Splitter
AHB 64
AXI 64
Pixel
AHB 64
AHB 64
SDAC3 [0..7] (AHB)
SDAC4 [0..7] (AXI)
Converter
Boot ROM
AHB
64
AHB
64
AHB
64
AHB
64
AHB
64
AHB
64
1.3MB
GRAM
(FlexECC)
Flash Memory
BIU
Priority Manager
512kB
System
SRAM (ECC)
512kB
System
SRAM (ECC)
AIPS 0
PDAC
AIPS 1
PDAC
4MB
DRAM Controller
16/32-bit
Flash memory (ECC)
SDR & DDR2
EE Emulation
Secure Flash
memory
OTP
ARM
Cortex M0+
AXBS
32kB
SRAM (ECC)
I/O Processor
Figure 2. Detailed block diagram
2 Family comparison
The table below provides a summary of the different members of the SAC57D5xx Low/
Mid-Line Instrument Cluster family and their features. Note that not all features are
available simultaneously on all packages.
Table 1. Feature sets
Product Features
SAC57D54H
SAC57D53M
SAC57D52L
Cores
Cortex-A5 (320 MHz,
Yes
Yes
Yes
32 KB/32 KB L1
Caches, FPU, MMU,
NEON)
Cortex-M4 (160 MHz,
16 KB/16 KB L1
Caches, FPU)
Yes
Yes
Yes
Table continues on the next page...
SAC57D54H, Rev. 7, 05/2017
6
NXP Semiconductors
Family comparison
Table 1. Feature sets (continued)
Product Features
SAC57D54H
SAC57D53M
SAC57D52L
Cortex - M0+ I/O
Yes
Yes
Yes
Processor (IOP) (80
MHz)
Internal Memory
ECC Flash Memory
Graphics SRAM1
4 MB
1.3 MB
3 MB
1.3 MB
2 MB
1.3 MB
System SRAM (ECC)
IOP local SRAM (ECC)
Dual DDR QuadSPI
2 x 512 KB
32 KB
2 x 512 KB
32 KB
2 x 512 KB
32 KB
External Memory
Interfaces
2 x Dual DDR QuadSPI 2 x Dual DDR QuadSPI 2 x Dual DDR QuadSPI
16 bit SDR DRAM
(160MHz)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
32-Bit DDR2 DRAM
(320MHz)2
-
System and General
Purpose
Memory / Peripheral
Protection (xDRC -
Extended Resource
Domain Controller)
Yes
Security (CSE)
eDMA
Yes
16ch x 2
x2
Yes
16ch x 2
x2
Yes
16ch x 2
x2
Graphics/Video/Display/
Audio
2D-ACE
HUD Warping Engine
TCON_0/RSDS
TCON_1
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
OpenLDI/LVDS
GPU
Yes
Yes
GC355 : OpenVG 1.1 / GC355 : OpenVG 1.1 / GC355 : OpenVG 1.1 /
TinyUI
TinyUI
TinyUI
Video Input Unit
Sound Generator
Segment LCD
FlexCAN
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
System Connectivity
x3
x3
x3
I2C
x2
x2
x2
LINFlexD
x3
x3
x3
SPI
x5
x5
x5
MLB50
Yes
Yes
Yes
10/100 Ethernet + AVB
SMC/SSD
12 Bit ADC
Analog Comparator
PIT
Yes
Yes
Yes
Analog Connectivity
Timer/PWM
x6
x6
x6
Yes
Yes
Yes
2 x 8ch
8ch
2 x 8ch
8ch
2 x 8ch
8ch
SWT
3
3
3
ARTC
Yes
Yes
Yes
FlexTimer
LQFP
4 x 8ch
208 LQFP
4 x 8ch
208 LQFP
4 x 8ch
208 LQFP
Package Options
Table continues on the next page...
SAC57D54H, Rev. 7, 05/2017
NXP Semiconductors
7
Ordering parts
Table 1. Feature sets (continued)
Product Features
SAC57D54H
SAC57D53M
516 MAPBGA
SAC57D52L
BGA
516 MAPBGA
-
1. GRAM can be reconfigured as ECC RAM
2. DDR2 interface only available in BGA package option
3 Ordering parts
3.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web.
1. To determine the orderable part numbers for this device, go to www.nxp.com and
perform a part number search for the following device number: SAC57D5xx.
3.2 Ordering information
SAC57D54H, Rev. 7, 05/2017
8
NXP Semiconductors
General
4 General
4.1 Absolute maximum ratings
NOTE
Functional operating conditions appear in the DC electrical
characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maximum values is not
guaranteed.
Stress beyond the listed maximum values may affect device
reliability or cause permanent damage to the device.
Table 2. Absolute maximum ratings
Symbol 1
Parameter
Conditions
Min
Max
Unit
VDDE_A, VDDE_B
VDDE_SDR
,
Input/output supply voltage2
—
–0.3
3.6
V
VDD_LP_DEC
VDDA
VDDEH_ADC
VSSA
Decoupling pin for low power regulators3
ADC supply voltage
—
–0.32
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
1.32
6.0
V
V
V
V
V
V
V
V
V
V
—
ADC I/O supply voltage
ADC supply ground
—
6.0
—
0.3
4
VDDA_REF
ADC supply voltage
—
6.0
VDDM_SMD
SMD supply voltage
—
6.0
VSSM_SMD
SMD supply ground
—
0.3
5
VDDE_DDR
DDR2 DRAM supply voltage
DDR I/O Reference Voltage
Core logic supply voltage
—
—
2.3
DDR_VREF
VDD12
1.15
1.32
—
VINA
Voltage on ADC analog pin with respect to
VSSA
Relative to
VDDE_A
VDDE_B
VDDE_SDR
VDDE_ADC + 0.3
VDDE_A + 0.3
VDDE_x + 0.3
V
V
V
,
,
Voltage on Analog comparator pin (CMP)
with respect to VSS
–0.3
–0.3
VIN
Voltage on any digital pin with respect to
Relative to
ground (VSS
)
VDDE_A
VDDE_B
,
,
VDDE_SDR
IINJPAD
IINJSUM
Injected input current on any pin during
overload condition
Always
–5
5
mA
mA
Absolute sum of all injected input currents
during overload condition
—
–50
50
Tramp
Ta 6
Supply ramp rate
—
—
—
0.5 V / min
–40
100 V/ms
105
—
°C
°C
Ambient temperature
Storage temperature
TSTG
–55
165
SAC57D54H, Rev. 7, 05/2017
NXP Semiconductors
9
General
1. All parameters are with reference to Vss unless otherwise specified.
2. A crossover current of up to 2 mA may be experienced if VDD12 is ramped up before VDDE_A supply. This current is only an
electrical crossover but has no functional implications, and should be removed when VDDE_A ramps up to its functional
operating range.
3. Not available for input voltage, only for decoupling internal regulators.
4. VDDA_REF is only available on the 516 BGA package.
5. DDR_VREF is expected to be equal to 0.5 × VDDE_DDR and to track VDDE_DDR DC variations as measured at the device
pins. Ensure VDD_LV supply ramps up before VDDE_DDR. In Standby mode, it should be ensured that VDDE_DDR supply
should be cut off.
6. Tj=125°C. Assumes Ta=105°C. Assumes maximum θJA of 2s2p board. See Thermal attributes section for details.
4.2 Recommended operating conditions
The following table describes the operating conditions for the device, and for which all
specifications in the data sheet are valid, except where explicitly noted. The device
operating conditions must not be exceeded in order to guarantee proper operation and
reliability. The ranges in this table are design targets and actual data may vary in the
given range.
For normal device operations, VDDE_A, VDDA, VDDA_REF, VDDEH_ADC and VDD12
supplies must be within operating range corresponding to the range mentioned in
following tables. This is required even if some of the features are not used. If using the
ADC to convert SSD channels then VDDA should always be >= VDDM_SMC
.
VDD12 should be supplied externally. VDDA_REF, the supply port to 516 BGA is shorted to
VDDA inside lower pin packages. Stepper Stall Detect module (SSD) should only be
operated in the 4.5 V to 5.5 V range and so cannot be used if VDDM_SMD is in 3.3 V
range.
Table 3. Recommended operating conditions
Symbol 1
Parameter
Conditions
Min2
Max
Unit
VDDE_A
Input/output supply voltage
—
3.15
3.6
V
3
VDDE_B
3
VDDE_SDR
VSSA
ADC supply ground, relative to
VSS
—
-0.1
0.1
V
VDDA
ADC supply voltage
ADC I/O supply voltage
ADC reference voltage
SMD supply voltage
VDDA,VDDA_REF and VDDEH_ADC
should be within +/-25 mV of
each other
3.15
3.15
3.15
3.15
1.7
5.5
5.5
5.5
5.5
1.9
V
V
V
V
V
V
VDDEH_ADC
VDDA_REF
VDDM_SMD
VDDE_DDR
DDR_VREF
—
—
—
DDR2 supply voltage
DDR I/O Reference Voltage
VDDE_DDR
(min)/2
VDDE_DDR
(max)/2
4
VDD12
Core logic supply voltage
—
1.20
1.32
V
Table continues on the next page...
SAC57D54H, Rev. 7, 05/2017
10
NXP Semiconductors
General
Table 3. Recommended operating conditions (continued)
Symbol 1
Parameter
Conditions
Min2
Max
Unit
VSSEH_ADC
ADC supply ground, relative to
VSS
—
-0.3
0.3
V
IINJPAD
Injected input current on any
pin during overload condition
—
-3.0
–40
3.0
mA
°C
5
Ta
Ambient temperature under
bias
105
1. All parameters are with reference to Vss, unless otherwise specified.
2. Device will be functional (and electrical specifications as per various datasheet parameters will be guaranteed) until one of
the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset.
3. VDDE_A, VDDE_B and VDDE_SDR are all independent supplies and can each be set to 3.3 V. However, care must be taken
over LCD inputs that operate across the IO segments.
4. Only applicable when supplying from external source. VDD12 supply pins should never be grounded (through a small
impedance). If not driven, these should only be left floating.
5. Tj=125°C. Assumes Ta=105°C. Assumes maximum θJA of 2s2p board. See Thermal attributes section for details.
4.3 Voltage regulator electrical specifications
The voltage regulator is composed of the following blocks:
• Connect an external 1.25 V nominal directly
• Low voltage detector - low threshold (LVD_HV_A) for VDDE_A supply
• Low voltage detector (LVD_FLASH) for 3.3 V flash supply
• Various low voltage detectors (LVD_LV_x) for digital core supply (VDD12)
• High voltage detector (HVD_LV) for digital core supply (VDD12
)
• Power on Reset (POR_LV) for 1.25 V digital core supply (VDD12
• Power on Reset (POR_HV) for VDDE_A
)
SAC57D54H, Rev. 7, 05/2017
NXP Semiconductors
11
General
VDD_LP_DEC
ULPREG
CULPREG
Vss
V DD12
Vss
DEVICE
Figure 3. Voltage regulator capacitance connection
Table 4. Voltage regulator electrical specifications
Symbol
Culp_reg
Parameter
Conditions
Min
Typ1
Max
Unit
External decoupling / stability
Min, max values shall be
0.8
1
1.4
µF
capacitor for internal low power granted with respect to
regulator
tolerance, voltage, temperature,
and aging variations
Combined ESR of external
capacitor
—
0.001
—
0.1
Ohm
1. Typical values will vary over temperature, voltage, tolerance, drift, but total variation must not exceed minimum and
maximum values.
4.3.1 Decoupling capacitor values
Following are the requirements for supply decoupling on various power domains:
• For VDDE_A, VDDE_B, VDDE_SDR, VDDM_SMD, VDDE_DDR, VDDA
VDDEH_ADC,VDDA_REF, DDR_VREF supplies:
,
• 0.1 μF close to each VDD/VSS pin pair.
• 1 μF on each side of the chip for each supply domain.
• 10 μF near for each power supply source (except for VDDM_SMD pins where a
higher capacitance value may be needed depending upon motor characteristics).
SAC57D54H, Rev. 7, 05/2017
12
NXP Semiconductors
General
• For VDD12, 0.1 μF close to each VDD/VSS pin pair is required.
4.4 Voltage monitor electrical specifications
Table 5. Voltage monitor electrical specifications
Symbol
Parameter
State Conditions
Configuration
Threshold
Typ Max
Unit
Power Mask Reset Type
Min
Up 1
Untrimmed Yes
Opt
VPOR_LV
LV supply
power on reset
detector
Fall
No
Destructive 0.9300 0.9790 1.0280
V
V
V
V
Trimmed
Untrimmed
Trimmed
-
-
-
Rise
0.9800 1.0290 1.0780
-
-
-
VHVD_LV_cold
LV supply high Fall
voltage
Untrimmed No
Trimmed
Yes
No
Functional
Disabled at Start
1.3250 1.3450 1.3750
Disabled at Start
V
monitoring,
detecting at the
device pin
Rise
Untrimmed
Trimmed
1.3450 1.3650 1.3950
V
V
V
V
V
VLVD_LV_PD2_hot LV supply low Fall
Untrimmed Yes
Trimmed
Destructive 1.0800 1.1200 1.1600
1.1250 1.1425 1.1600
voltage
monitoring,
Rise
Untrimmed
Trimmed
1.1000 1.1400 1.1800
detecting in the
PD2 core (hot)
area
1.1450 1.1625 1.1800
VLVD_LV_PD0_hot LV supply low Fall
Untrimmed Yes
Trimmed
No
Destructive 1.0800 1.1200 1.1600
1.1140 1.1370 1.1600
V
V
V
V
voltage
monitoring,
Rise
Untrimmed
Trimmed
1.1000 1.1400 1.1800
detecting in the
PD0 core (hot)
area
1.1340 1.1570 1.1800
VPOR_HV
HV supply
power on reset
detector
Fall
Untrimmed Yes
Trimmed
No
Destructive 2.7000 2.8500 3.0000
V
V
V
V
V
V
V
V
-
-
-
Rise
Untrimmed
Trimmed
2.7500 2.9000 3.0500
-
-
-
VLVD_IO_A_LO
HV IO_A supply Fall
low voltage
monitoring - low
Untrimmed Yes
Trimmed
No
Destructive 2.7500 2.9230 3.0950
2.9780 3.0260 3.0750
Rise
Untrimmed
Trimmed
2.7800 2.9530 3.1250
range
3.0080 3.0690 3.1300
VLVD_LV_PD2_COL LV supply low Fall
Untrimmed No
Trimmed
Yes
Functional
Disabled at Start
voltage
D
1.1400 1.1550 1.1750
Disabled at Start
V
V
monitoring,
detecting at the
device pin
Rise
Untrimmed
Trimmed
1.1600 1.1750 1.1950
1. All monitors that are active at power up will gate the power up recovery and prevent exit from POWERUP phase until the
minimum level is crossed. These monitors can in some cases be masked during normal device operation, but when active
will always generate a destructive reset.
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NXP Semiconductors
13
General
4.5 Power consumption
The following table shows the power consumption for the device in the various modes of
operation.
Table 6. Power consumption
Mode
Configuration
Typ
Max
Unit
RUN Mode
CA5 320 MHz, CM4
160 MHz, DDR2 320
MHz, Dual Display (516
BGA)
800
1500
mA
RUN Mode
CA5 320 MHz, CM4
160 MHz, SDR 160
MHz, Single Display
(208 QFP)
600
1200
mA
STOP Mode
Cores halted, device
fully powered.
240
700
mA
μA
STANDBY Mode1, 2
ARTC/32 KHz + 32 KB
SRAM powered
50 (25 °C)
500 (55 °C)
1500 (85 °C)
2000 (105 °C)
45 (25 °C)
70 (25 °C)
900 (55 °C)
2500 (85 °C)
4000 (105 °C)
65 (25 °C)
ARTC/32 KHz + 8 KB
SRAM powered
μA
500 (55 °C)
1500 (85 °C)
2000 (105 °C)
900 (55 °C)
2500 (85 °C)
4000 (105 °C)
1. Weak pull functionality provided in I/O pads must be used to configure I/Os in a known state (that does not cause
contention with external connection on the pin) to avoid floating input to cause crow-bar currents and hence increased
leakage during low power modes.
2. During STANDBY modes, it is recommended to keep VDDE_A, VDDEH_ADC, VDDAand VDDA_REF powered to their respective
functional levels to obtain best power performance of the device. All other supplies are recommended be kept unpowered
in these low power modes.
The following diagrams show the supply configuration of the device.
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14
NXP Semiconductors
General
Figure 4. Supply configuration
4.6 Electrostatic discharge (ESD) specifications
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
NOTE
A device will be defined as a failure if after exposure to ESD
pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing
shall be performed per applicable device specification at room
temperature followed by hot temperature, unless specified
otherwise in the device specification.
Table 7. ESD ratings
Symbol
Parameter
Electrostatic discharge
(Human Body Model)
Conditions1
Class
Max value2
Unit
VESD(HBM)
TA = 25 °C
H1C
2000
V
conforming to AEC-
Q100-002
VESD(CDM)
Electrostatic discharge
TA = 25 °C
C3A
500
V
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NXP Semiconductors
15
I/O parameters
Symbol
Table 7. ESD ratings
Parameter
Conditions1
Class
Max value2
Unit
(Charged Device Model)
conforming to AEC-
Q100-011
750 (corners)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. Data based on characterization results, not tested in production.
4.7 Electromagnetic Compatibility (EMC) specifications
EMC measurements to IC-level IEC standards are available from NXP on request.
5 I/O parameters
5.1 AC specifications @ 3.3 V range
Table 8. Functional Pad AC Specifications @ 3.3 V range
Symbol
Rise/Fall Edge (ns)
Drive Load (pF)
Drive/Slew Rate Select
MSB, LSB
Min
Max
pad_sr_hv
(output)
1.75/1.5
3.25/3
12/12
25
50
11 (Recommended setting)
0.8/0.8
3.5/2.5
0.6/0.8
1/1
200
25
3.75/3.5
7/6.5
10
50
7.7/5
25/21
200
50
4/3.5
25/25
01
001
NA
6.3/6.2
6.8/6
30/30
200
50
40/40
11/11
51/51
200
0.5
pad_i_hv/pad_sr_hv
0.5/0.5
(input)2
pad_fc_hv
0.6/0.6
1.5/1.5
2.4/2.4
1.5/1.5
1.85/1.85
36/45
30
50
20
10
50
11
(output)
0.6/0.6
0.6/0.6
12/11
10
01
00
1. Slew rate control modes
2. Input slope = 2 ns
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16
NXP Semiconductors
I/O parameters
5.2 DC electrical specifications @ 3.3 V range
Table 9. DC electrical specifications @ 3.3 V range
Symbol
Parameter
Value
Unit
Min
3.15
Max
3.63
Vdde
Vih
I/O Supply Voltage
V
V
CMOS Input Buffer High Voltage (with
hysteresis disabled)
0.55 x Vdde
Vdde + 0.3
Vil
CMOS Input Buffer Low Voltage (with
hysteresis disabled)
Vss − 0.3
0.65 x Vdde
Vss − 0.3
0.40 x Vdde
Vdde + 0.3
0.35 x Vdde
V
V
V
Vih_hys
Vil_hys
CMOS Input Buffer High Voltage (with
hysteresis enabled)
CMOS Input Buffer Low Voltage (with
hysteresis enabled)
Vhys
CMOS Input Buffer Hysteresis
0.1 x Vdde
25
V
Pull_Ioh_vil_hys
Weak Pullup Current measured when
pad = 0.35 x Vdde
80
80
µA
Pull_Ioh_vih_hys
Iinact_d
Weak Pulldown Current measured when
pad = 0.65 x Vdde
25
µA
µA
Digital Pad Input Leakage Current (weak
pull inactive)
−2.5
2.5
Voh
Vol
Output High Voltage1
Output Low Voltage2
0.8 x Vdde
—
V
V
V
V
V
V
V
V
—
0.2 x Vdde
Vih_ttl
Vil_ttl
TTL High Level Input Voltage
TTL Low Level Input Voltage
TTL Input Hysteresis Voltage
Automotive High Level Input Voltage
Automotive Low Level Input Voltage
Automotive Input Hysteresis Voltage
1.8
0.6
Vhyst_ttl
Vih_auto
0.25
0.75 x Vdde
−0.3
Vdde + 0.3
3
Vil_auto
0.35 ✕ Vdde
Vhyst_auto
0.11 x Vdde
1. Measured when pad is sourcing 2 mA.
2. Measured when pad is sinking 2 mA.
3. Auto levels are applicable to the ‘input only' channels (CH0-7) of the ADC pins
5.3 AC specifications @ 5 V range
Table 10. Functional pad AC specifications @ 5 V range
Symbol
Rise/Fall Edge (ns)
Min Max
Drive Load (pF)
Drive/Slew Rate Select
MSB, LSB
pad_sr_hv
(output)
1.2/1.2
2.5/2
25
50
11 (Recommended setting)
Table continues on the next page...
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NXP Semiconductors
17
I/O parameters
Table 10. Functional pad AC specifications @ 5 V range (continued)
Symbol
Rise/Fall Edge (ns)
Min Max
Drive Load (pF)
Drive/Slew Rate Select
MSB, LSB
8/8
3/2
200
25
10
5/4
50
18/16
13/13
24/24
24/24
50/50
1.8/1.7
6.6/6.1
2.7/2.5
10.3/9.3
5.6/4.8
21/19
41/41
151/151
200
50
01
001
11
10
01
00
200
50
200
50
pad_fc_hv
(output)
200
50
200
50
200
50
200
1. Slew rate control modes
5.4 DC electrical specifications @ 5 V range
Table 11. DC electrical specifications @ 5 V range
Symbol
Parameter
Value
Unit
Min
4.5
Max
5.5
Vdde
Vih
I/O Supply Voltage
V
V
CMOS Input Buffer High Voltage (with hysteresis
disabled)
0.55 × Vdde
Vdde + 0.3
Vil
CMOS Input Buffer Low Voltage (with hysteresis
disabled)
Vss − 0.3
0.65 × Vdde
Vss − 0.3
0.40 × Vdde
Vdde + 0.3
0.35 × Vdde
V
V
V
Vih_hys
Vil_hys
Vhys
CMOS Input Buffer High Voltage (with hysteresis
enabled)
CMOS Input Buffer Low Voltage (with hysteresis
enabled)
CMOS Input Buffer Hysteresis
0.1 × Vdde
40
V
Pull_Ioh_vil_h ys Weak Pullup Current measured when pad = 0.35 x Vdde
(Vil_hys)
120
120
2.5
µA
Pull_Ioh_vih_hys Weak Pulldown Current measured when pad = 0.65 x
Vdde (Vih_hys)
40
µA
µA
Iinact_d
Digital Pad Input Leakage Current (weak pull inactive)
−2.5
Table continues on the next page...
SAC57D54H, Rev. 7, 05/2017
18
NXP Semiconductors
I/O parameters
Table 11. DC electrical specifications @ 5 V range (continued)
Symbol
Parameter
Value
Unit
Min
0.8 x Vdde
—
Max
Voh
Vol
Output High Voltage1
Output Low Voltage2
—
V
0.2 x Vdde
V
V
V
V
V
V
V
Vih_ttl
Vil_ttl
TTL High Level Input Voltage
2.0
TTL Low Level Input Voltage
0.8
Vhyst_ttl
Vih_auto
TTL Input Hysteresis Voltage
0.3
3.8
Automotive High Level Input Voltage
Automotive Low Level Input Voltage
Automotive Input Hysteresis Voltage
Vdde + 0.3
2.2
3
Vil_auto
−0.3
0.5
3
Vhyst_auto
Automotive Levels with Expanded VDDE Range: 4 V - 5.5 V
3
Vih_auto
Automotive High Level Input Voltage
0.7 × Vdde
−0.3
Vdde + 0.3
V
V
V
3
Vil_auto
Automotive Low Level Input Voltage
Automotive Input Hysteresis Voltage
0.47 × Vdde
3
Vhyst_auto
0.11 × Vdde
1. Measured when pad is sourcing 2 mA.
2. Measured when pad is sinking 2 mA.
3. Auto levels are applicable to the ‘input only' channels (CH0-7) of the ADC pins
5.5 DDR2 pads IO specifications
5.5.1 DDR2 pads AC specifications @ 1.8V VDDE_DDR
Table 12. DDR2 pads AC electrical specifications at 1.8 V VDDE_DDR
Name
Rise/Fall Edge (V/ns)
Drive Load (pF)
Drive Strength
Select (Refer
SIUL_MSCR[SRE]
description in the
device reference
manual)
Min
Max
—
Half/Full
Half
Half
Full
pad_dq_18
pad_acc_18
1
1
1
1
1
1
1
1
5
20
5
—
—
—
20
5
Full
—
Half
Half
Full
—
20
5
—
—
20
Full
Table continues on the next page...
SAC57D54H, Rev. 7, 05/2017
NXP Semiconductors
19
I/O parameters
Table 12. DDR2 pads AC electrical specifications at 1.8 V VDDE_DDR (continued)
Name
Rise/Fall Edge (V/ns)
Drive Load (pF)
Drive Strength
Select (Refer
SIUL_MSCR[SRE]
description in the
device reference
manual)
Min
Max
—
Half/Full
Half
pad_clk_18
1
1
1
1
5
20
5
—
Half
—
Full
—
20
Full
5.5.2 SSTL_18 Class II 1.8 V DDR2 DC specifications
Table 13. SSTL_18 Class II 1.8 V DDR2 DC specifications
Symbol
VDDE_DDR
VDD12
DDR_REF
Vih(dc)
Vil(dc)
Parameter
Conditio
n
Min
1.7
Typ
1.8
Max
1.9
Uni
t
Notes
SpecI
D
DDR 1.8 V I/O
Supply voltage
—
V
JESD8-15
A
A5.14
A5.15
A5.16
A5.18
A5.19
A5.20
A5.21
A5.22
A5.23
A5.24
A5.25
Core Supply
Voltage
—
1.20
1.26
1.32
V
I/O Reference
Voltage
—
0.49 x VDDE_DDR 0.50 x VDDE_DDR
0.51 x
VDDE_DDR
V
DC Input Logic
High
—
DDR_VREF +
0.125
—
—
—
—
—
—
—
—
V
JESD8-15
A
DC Input Logic
Low
—
DDR_VREF −
0.125
V
JESD8-15
A
Vih(ac)
Vil(ac)
AC Input Logic
High
—
DDR_VREF +
0.25
—
V
JESD8-15
A
AC Input Logic
Low
—
—
DDR_VREF −
0.25
V
JESD8-15
A
Iin
Pad input
Leakage Current
—
—
-50
VDDE_DDR − 0.28
—
50
μA
V
—
—
—
Voh
Output High
Voltage Level
—
Vol
Output Low
Voltage Level
—
0.28
—
V
Ioh(dc)
Output min
source dc current
Vout = Voh
−12.86
mA JESD8-15
A VDDE_DDR
= 1.7V Voh
= 1.42V
Iol(dc)
Output min sink
dc current
Vout= Vol
12.86
—
—
mA JESD8-15
A VDDE_DDR
= 1.7 V Vol
= 0.28 V
A5.26
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NXP Semiconductors
SMC pads IO specifications
Table 14. Current-draw Characteristics for DDR_VREF
Symbol
Parameter
Min
Max
Unit
DDR_VREF Current-draw characteristics for DDR_VREF
-
5
mA
5.6 SMC pads IO specifications
5.6.1 SMC 5V pads IO specifications
NOTE
In Table 15, Table 16, "VDDE" is the VDDM_SMD supply
5.6.1.1 SMC 5V pads IO DC specifications
Table 15. SMC 5V IO DC specifications(4.5V<vdde<5.5V)
Symbol
Vil
Characteristic
Low level input voltage
High level input voltage
Schmitt trigger hysteresis
Min
−0.3
Typ
Max
Unit
0.35 × vdde
vdde + 0.3
V
V
Vih
0.65 × vdde
0.1 × vdde
−130
Vhyst
Ipu
V
Internal pull up device current
(Vin=Vil)
μA
Ipu
Ipd
Ipd
Internal pull up device current
(Vin=Vih)
−10
130
μA
μA
μA
Internal pull down device current
(Vin=Vil)
10
Internal pull down device current
(Vin=Vih)
Iin
Input leakage current (ipp_pue=0)
−2.5
2.5
μA
V
Vol
Low level output voltage (Iol=+20
mA)
0.32
Voh
High level output voltage (Ioh=-20
mA)
vdde − 0.32
V
V
Vsum
Vsum ( | Vol | + | Voh | ) (Iol=+40
mA and Ioh=-40 mA)
1.0
50
Voh delta / Vol Delta Voh across one motor
−50
mV
delta
Rdsonh
Rdsonl
segment and Delta Vol across one
motor segment
Pad drive active high impedance
(test load Ioh = 30 mA)
4
13
9
Ω
Ω
Pad drive active low impedance
(test load Iol = 30 mA)
2.75
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NXP Semiconductors
21
SMC pads IO specifications
5.6.1.2 SMC 5V pads IO AC specifications
Table 16. SMC 5V IO functional pad AC specifications (4.5V<vdde<5.5V)
Name
Symbol
Symbol
Rise/Fall Edge (ns)
Drive Load
(pF)
Drive/Slew
Rate Select
Min
Max
0.5/0.5
ipp_sre_lv
CMOS input
0.5
NA
5.6.2 SMC 3.3 V pads IO specifications
NOTE
In Table 17, Table 18, the "VDDE" refers to the VDDM_SMD
supply.
5.6.2.1 SMC 3.3 V pads IO DC specifications
Table 17. SMC 3.3 V pads IO DC specifications (3.0V<vdde<3.6V)
Symbol
Vil
Characteristic
Low level input voltage
High level input voltage
Schmitt trigger hysteresis
Min
-0.3
Typ
Max
Unit
V
0.35 × vdde
vdde + 0.3
Vih
0.65 × vdde
0.1 × vdde
-130
V
Vhyst
Ipu
V
Internal pull up device current
(Vin=Vil)
μA
Ipu
Ipd
Ipd
Internal pull up device current
(Vin=Vih)
-10
μA
μA
μA
Internal pull down device current
(Vin=Vil)
10
Internal pull down device current
(Vin=Vih)
130
Iin
Input leakage current (ipp_pue=0)
-2.5
+2.5
μA
V
Vol
Low level output voltage (Iol=+10
mA)
0.32
Voh
High level output voltage (Ioh=-10
mA)
vdde − 0.32
V
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NXP Semiconductors
SMC pads IO specifications
5.6.2.2 SMC 3.3 V pads IO AC specifications
Table 18. SMC 3.3 V functional pads IO DC specifications (3.0V<vdde<3.6V)
Name
Symbol
Symbol
Rise/Fall Edge (ns)
Drive Load
(pF)
Drive/Slew
Rate Select
Min
Max
0.5/0.5
ipp_sre_lv
CMOS input
0.5
NA
5.7 RSDS pads electrical specifications
Table 19. RSDS pads electrical specifications
Symbol
Parameter
Min
Typ
Max
Unit
Supply Voltages
1
Vdde
3
3.3
-
V
RSDS_Tx
Normal mode (Vdde
)
-
3
1
-
-
mA
µA
Power down mode
-
RSDS reference
Normal mode
-
400
0.1
-
-
μA
µA
Power down mode
-
Data rate
Data Frequency
50
50
MHz
Driver specs
Vod
Vos
Differential o/p voltage
100
-
200
1.2
400
-
mV
V
Common mode voltage
(VOS)
tR/tF
Rise/Fall time
-
500
6
-
-
-
ps
µs
µs
Startup Time (RSDS_ref)
Startup time (RSDSTx)
-
-
6
Termination
Termination Resistance
-
100
100
-
ohm
ohm
Trans. Line (differential Zo)
95
105
Skew
2
tskew
Skew between different
RSDS lines
-
382
-
ps
1. vdde is the VDDE_B supply
2. This value is derived from simulation assuming default register setting of all 1’s for skew. There are 8 programmable bits to
provide 256 different skew numbers with various combinations of these bits. See the TCON chapter of the device
Reference Manual for details. All "0" combination of 8 bits is not valid.
SAC57D54H, Rev. 7, 05/2017
NXP Semiconductors
23
SMC pads IO specifications
Pad_p
pad_n
pad_n
80%
80%
Crossover point
Differential
DataLines
20%
20%
pad_p
Fall
Time
(tf)
Rise
Time
(tr)
Figure 5. Rise/Fall transition
Pad_p
Crossover point
Vos
Valid outputs
Differential
outputs
pad_n
Enabletime
(tdz)
ipp_obe
Figure 6. Enable time
SAC57D54H, Rev. 7, 05/2017
24
NXP Semiconductors
SMC pads IO specifications
Figure 7. Rise/Fall transition of differential output
5.8 LVDS pads electrical specifications
Table 20. LVDS pads electrical specifications
Symbol
Parameter
Min
Typ
Max
Unit
Supply Voltages
, 1
V DDE
3
3.3
-
V
Current consumption
LVDS Tx
Normal mode
—
—
—
5
—
—
—
mA
mA
µA
1
(VDDE
)
Switching currents
Power down mode
1.5 (during output
transition)
1
LVDS Reference
Normal mode
—
—
400
0.1
—
—
µA
µA
Power down mode
Data Rate
Data Frequency
—
—
560
Mbps
Driver specs
Vod
Vos
tr/tf
Differential o/p
voltage 2
247
—
—
454
mV
V
Common mode
1.125
1.375
voltage (VOS
)
Rise/Fall time 3
—
—
—
5
800
—
ps
µs
Startup Time
(lvds_ref)
Startup time
(lvds_Tx)
—
5
—
µs
Table continues on the next page...
SAC57D54H, Rev. 7, 05/2017
NXP Semiconductors
25
SMC pads IO specifications
Table 20. LVDS pads electrical specifications (continued)
Termination
Termination
Resistance
—
100 1%
—
Ω
Ω
Trans. Line
95
100
105
(differential Zo)
1. VDDE is the VDDE_B supply.
2. The limit applies to the default drive current.
3. Rise/fall time is assumed to be measured with 20%-80% levels.
5.9 Functional reset pad electrical specifications
The device implements a dedicated bidirectional RESET pin.
Table 21. Functional reset pad electrical specifications
Symbol
Parameter
Conditions
Value
Unit
Min
2.0
Typ
—
Max
VIH
Input high level TTL (Schmitt Trigger)
Input low level TTL (Schmitt Trigger)
Input hysteresis TTL (Schmitt Trigger)
—
—
—
—
VDDE_A+0.4 V
VIL
–0.4
300
—
—
0.65
—
V
VHYS
—
mV
V
VDD_POR
Minimum supply for strong pull-down
activation
—
1.2
IOL_R
Strong pull-down current
Device under power-on reset
VDDE_A=VDD_POR
VOL = 0.35 x VDDE_A
—
0.2
—
—
mA
WFRST
RESET input filtered pulse
—
—
—
—
500
—
ns
ns
µA
WNFRST
RESET input not filtered pulse
Weak pull-up current absolute value
—
2000
23
|IWPU
|
RESET pin VIN = VDD
82
5.10 PORST electrical specifications
Table 22. PORST electrical specifications
Symbol
Parameter
Value
Unit
Min
—
Typ
Max
WFPORST
WNFPORST
VIH
PORST input filtered pulse
PORST input not filtered pulse
Input high level
—
200
—
ns
ns
1000
—
—
0.65 x VDDE_A
0.35 x VDDE_A
—
V
V
VIL
Input low level
—
—
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NXP Semiconductors
Peripheral operating requirements and behaviors
6 Peripheral operating requirements and behaviors
6.1 Analog modules
6.1.1 ADC electrical specifications
The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-
Digital Converter.
Offset Error OSE Gain Error GE
4095
4094
4093
4092
4091
4090
(2)
1 LSB ideal =(VrefH-VrefL)/ 4096 =
3.3V/ 4096 = 0.806 mV
Total Unadjusted Error
TUE = +/- 6 LSB = +/- 4.84mV
code out7
(1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
(5)
4
3
(4)
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal
)
Offset Error OSE
Figure 8. ADC characteristics and error definitions
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27
Analog modules
6.1.1.1 Input impedance and ADC accuracy
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
V
DD_IO
Channel
Sampling
Selection
Source
Filter
Current Limiter
R
R
R
R
R
S
F
L
SW1
AD
C
V
C
C
P1
C
S
A
F
P2
R
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
S
F
F
L
R
C
R
R
R
C
C
SW1
AD
P
Pin Capacitance (two contributions, C and C
Sampling Capacitance
)
P1
P2
S
Figure 9. Input equivalent circuit
Table 23. ADC conversion characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fCK
ADC Clock frequency (depends on —
ADC configuration) (The duty cycle
depends on AD_CK1 frequency)
15.2
80
80
MHz
fs
Sampling frequency
Sample time2
80 MHz
—
—
1
MHz
ns
tsample
80 MHz@ 100 ohm source
impedance
250
800
—
tconv
Conversion time3
80 MHz
80 MHz
700
1.54
—
—
—
—
ns
µs
ttotal_conv
Total Conversion time tsample +
tconv (for standard and extended
channels)
Total Conversion time tsample
tconv (for precision channels)
+
1
—
—
CS
ADC input sampling capacitance
ADC input pin capacitance 1
ADC input pin capacitance 2
—
—
—
—
—
—
—
3
5
pF
pF
pF
kΩ
Ω
5
CP1
—
—
—
—
—
—
5
5
CP2
—
0.8
0.3
875
825
5
RSW1
Internal resistance of analog
source
VREF range = 4.5 to 5.5 V
VREF range = 3.15 to 3.6 V
—
5
RAD
Internal resistance of analog
source
Ω
ADC Analog Pad Max leakage
(pad going to one
125°C
—
—
—
250
5
nA
Max positive/negative injection
–5
mA
ADC)
Table continues on the next page...
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NXP Semiconductors
Analog modules
Table 23. ADC conversion characteristics (continued)
Symbol
Parameter
Conditions
ADC (12-bit mode)
Min
Typ
Max
Unit
INL
DNL
OFS
GNE
Integral non-linearity
—
—
—
—
–2
–1
–6
–4
–6
—
—
—
—
2
1
LSB
LSB
LSB
LSB
LSB
LSB
μs
Differential non-linearity
Offset error
—
6
Gain error
—
4
TUEprecision channels Total unadjusted error for precision Without current injection
+/- 4
+/- 5
—
6
channels
With current injection
—
<1
Trecovery
Differential non-linearity
—
ADC (10-bit mode)6
INL
DNL
OFS
GNE
Integral non-linearity
Differential non-linearity
Offset error
—
—
—
—
–1
–0.7
–4
—
—
1
0.7
4
LSB
LSB
LSB
LSB
LSB
LSB
μs
—
Gain error
–4
—
4
TUEprecision channels Total unadjusted error for precision Without current injection
–5
+/- 3
+/- 4
—
5
channels
With current injection
—
—
<1
Trecovery
Differential non-linearity
—
—
1. The internally generated clock (known as AD_clk or ADCK) could be same as the peripheral clock or half of the peripheral
clock based on register configuration in the ADC.
2. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the
sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample
clock tsample depend on programming.
3. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to
load the result register with the conversion result.
4. Apart from tsample and tconv, few cycles are used up in ADC digital interface and hence the overall throughput from the
ADC is lower.
5. See Figure 2.
6. Measurements taken with same ADC accuracy settings as for 12bit. ADC data is read from CDR with last 2-LSBs ignored.
6.1.2 Analog Comparator (CMP) electrical specifications
Table 24. Comparator and 6-bit DAC electrical specifications
Symbol
IDDHS
IDDLS
VAIN
Description
Min.
—
Typ.
—
Max.
250
Unit
μA
μA
V
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
Analog input offset voltage 1
Analog comparator hysteresis 2
• CR0[HYSTCTR] = 00
—
5
11
VSS
-42
—
VDDE_A
42
VAIO
—
mV
VH
—
—
—
1
25
50
70
mV
mV
mV
20
40
• CR0[HYSTCTR] = 01
Table continues on the next page...
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29
Clocks and PLL interfaces modules
Table 24. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
• CR0[HYSTCTR] = 10
Min.
Typ.
Max.
Unit
—
60
105
mV
• CR0[HYSTCTR] = 11
tDHS
tDLS
Propagation Delay, High Speed Mode (Full Swing) 1, 3
Propagation Delay, Low power Mode (Full Swing) 1, 3
—
—
—
—
5
250
14
ns
μs
μs
Analog comparator initialization delay, High speed
mode4
4
Analog comparator initialization delay, Low speed
mode 4
—
100
μs
IDAC6b
6-bit DAC current adder (when enabled)
3.3V Reference Voltage
—
–1
6
9
1
μA
LSB5
INL
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
—
—
DNL
–0.8
0.8
LSB
1. Measured with hysteresis mode of 00
2. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_HV_A-0.6V
3. Full swing = VIH, VIL
4. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
5. 1 LSB = Vreference/64
6.2 Clocks and PLL interfaces modules
6.2.1 Fast Oscillator (FXOSC) electrical specifications
This device provides a driver for oscillator in pierce configuration with amplitude
control. Controlling the amplitude allows a more sinusoidal oscillation, reducing in this
way the EMI. Other benefits arises by reducing the power consumption. This Loop
Controlled Pierce (LCP mode) requires good practices to reduce the stray capacitance of
traces between crystal and MCU.
An operation in Full Swing Pierce (FSP mode), implemented by an inverter is also
available in case of parasitic capacitances and cannot be reduced by using crystal with
high equivalent series resistance. For this mode, a special care needs to be taken
regarding the serial resistance used to avoid the crystal overdrive.
Other two modes called External (EXT Wave) and disable (OFF mode) are provided. For
EXT Wave, the drive is disabled and an external source of clock within CMOS level
based in analog oscillator supply can be used. When OFF, EXTAL is pulled down by 240
Kohms resistor and the feedback resistor remains active connecting XTAL through
EXTAL by 1M resistor.
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NXP Semiconductors
Clocks and PLL interfaces modules
Figure 10. Oscillator connections scheme
Table 25. Fast Oscillator electrical characteristics
Symbol
fXOSCHS
Parameter
Mode
Conditions
Min
Typ
Max
Unit
Oscillator
frequency
FSP/LCP
8
40
MHz
TXOSCHSSU
Startup time
FSP/LCP
8-40 MHz
8 MHz
1
ms
Supply current FSP
2.2
2.2
3.2
141
252
518
1.84
mA
16 MHz
40 MHz
8 MHz
LCP
µA
16 MHz
40 MHz
VIH
VIL
Input High
level CMOS
Schmitt trigger
EXT Wave
Oscillator
supply=3.3
V
V
Input low level EXT Wave
CMOS
Oscillator
supply=3.3
1.48
Schmitt trigger
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31
Clocks and PLL interfaces modules
6.2.2 Slow Oscillator (SXOSC) electrical specifications
Table 26. Slow Oscillator (SXOSC) electrical
specifications
Symbol
fosc_lo
Parameter
Condition
Min
Typ
Max
Unit
Oscillator crystal
or resonator
frequency
32
40
2
kHz
tcst
Crystal Start-up
Time 1
s
Vpp
Peak-to-Peak
0.52
V
XTAL Amplitude
1. Proper PC board layout procedures must be followed to achieve specifications.
2. RF is integrated and may not be attached externally.
6.2.3 Fast internal RC Oscillator (FIRC) electrical specifications
Table 27. Fast internal RC Oscillator electrical specifications
Symbol
Parameter
Conditions
Value
Typ
16
Unit
Min
Max
FTarget
Tstartup
TSTJIT
TLTJIT
IVDDHV
IRC target frequency
—
—
—
—
1.51
1.5
0.2
75
MHz
µs
Startup time
—
Cycle to cycle jitter
Long term jitter
—
—
—
—
%
—
%
Current consumption on 3.3 V power
supply
After Tstartup
After Tstartup
—
µA
IVDDLV
Current consumption on 1.2 V power
supply
—
—
25
µA
1. The start-up time is generally 16 clock cycles of FIRC untrimmed clock.
6.2.4 Slow internal RC oscillator (SIRC) electrical specifications
Table 28. Slow internal RC oscillator electrical specifications
Symbol
Parameter
Condition
Calibrated
Min
Typ
Max
Unit
Fosc
Oscillator
frequency
119
128
136.5
600
kHz
Temperature
dependence
ppm/C
Table continues on the next page...
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NXP Semiconductors
Clocks and PLL interfaces modules
Table 28. Slow internal RC oscillator electrical specifications
(continued)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Supply
18
%/V
dependence
Supply current
Clock running
Clock stopped
2.75
200
µA
nA
6.2.5 PLL electrical specifications
Table 29. PLL electrical specifications
Parameter
Input Frequency
Min
Typ
Max
Unit
MHz
Comments
8
40
VCO Frequency Range
Duty Cycle at pllclkout
600
48%
1280
52%
MHz
This specification is guaranteed
at PLL IP boundary
Period Jitter
TIE
See Table 30
See Table 30
ps
NON SSCG mode
at 960 M Integrated over 1MHz
offset not valid in SSCG mode
Modulation Depth (Center Spread) +/- 0.25%
Modulation Frequency
+/- 3.0%
32
KHz
µs
Lock Time
60
Calibration mode
Table 30. Jitter calculation
Type of jitter
Jitter due to
Supply
Jitter due to
Jitter due to
Fractional Mode
JSSCG (ps) 3
1 Sigma
Total Period Jitter (ps)
Fractional Mode
Random
Jitter JRJ
(ps) 4
2
Noise (ps)
(ps) JSDM
1
JSN
Period Jitter
60 ps
3% of pllclkout1,2
Modulation depth
0.1% of
+/-(JSN+JSDM+JSSCG+N[4]
pllclkout1, 2
×JRJ)
Long Term Jitter
(Integer Mode)
40
+/-(N x JRJ
)
)
Long Term jitter
100
+/-(N x JRJ
(Fractional Mode)
1. This jitter component is due to self noise generated due to bond wire inductances on different PLL supplies. The jitter value
is valid for inductor value of 5nH or less each on avdd, avss, dvdd, dvss.
2. This jitter component is added when the PLL is working in the fractional mode.
3. This jitter component is added when the PLL is working in the Spread Spectrum Mode. Else it is 0.
4. The value of N is dependent on the accuracy requirement of the application. See Percentage of sample exceeding
specified value of jitter table
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33
Memory interfaces
Table 31. Percentage of sample exceeding specified value of jitter
N
Percentage of samples exceeding specified value of jitter
(%)
1
2
3
4
5
6
7
31.73
4.55
0.27
6.30 × 1e-03
5.63 × 1e-05
2.00 × 1e-07
2.82 × 1e-10
6.3 Memory interfaces
6.3.1 Flash memory specifications
NOTE
Flash specs defined in this section at 150°C are also valid for
the maximum temperature specifications of the device.
6.3.1.1 Flash memory program and erase specifications
NOTE
All timing, voltage, and current numbers specified in this
section are defined for a single embedded flash memory within
an SoC, and represent average currents for given supplies and
operations.
Table 32 shows the estimated Program/Erase times.
Table 32. Flash memory program and erase specifications
Symbol
Characteristic1
Typ2
Factory
Field Update
Unit
Programming3, 4
Initial
Max
Initial
Max, Full
Temp
Typical
End of
Life5
Lifetime Max6
20°C ≤TA -40°C ≤TJ -40°C ≤TJ ≤ 1,000 ≤ 250,000
≤30°C ≤150°C ≤150°C cycles cycles
tdwpgm
tppgm
Doubleword (64 bits) program time 43
100 150 55 500
200 300 108 500
μs
μs
Page (256 bits) program time
73
Table continues on the next page...
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Memory interfaces
Table 32. Flash memory program and erase specifications (continued)
Symbol
Characteristic1
Typ2
Factory
Field Update
Unit
Programming3, 4
Initial
Max
Initial
Max, Full
Temp
Typical
End of
Life5
Lifetime Max6
20°C ≤TA -40°C ≤TJ -40°C ≤TJ ≤ 1,000 ≤ 250,000
≤30°C
≤150°C
≤150°C
cycles
cycles
tqppgm
Quad-page (1024 bits) program
time
268
800
1,200
396
2,000
μs
t16kers
16 KB Block erase time
16 KB Block program time
32 KB Block erase time
32 KB Block program time
64 KB Block erase time
64 KB Block program time
256 KB Block erase time
256 KB Block program time
168
34
290
45
320
50
250
40
1,000
1,000
1,200
1,200
1,600
1,600
4,000
4,000
ms
ms
ms
ms
ms
ms
ms
ms
t16kpgm
t32kers
t32kpgm
t64kers
217
69
360
100
490
180
1,520
720
390
110
590
210
2,030
880
310
90
315
138
884
552
420
170
1,080
650
t64kpgm
t256kers
t256kpgm
—
—
1. Program times are actual hardware programming times and do not include software overhead. Block program times
assume quad-page programming.
2. Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
3. Conditions: ≤ 150 cycles, nominal voltage.
4. Plant Programing times provide guidance for timeout limits used in the factory.
5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.
6. Conditions: -40°C ≤ TJ ≤ 150°C, full spec voltage.
6.3.1.2 Flash memory Array Integrity and Margin Read specifications
Table 33. Flash memory Array Integrity and Margin Read specifications
Symbol
Characteristic
Min
Typical
Max1
Units
2
tai16kseq
Array Integrity time for sequential sequence on 16 KB block.
—
—
512 x
Tperiod x
Nread
—
—
—
—
tai32kseq
Array Integrity time for sequential sequence on 32 KB block.
Array Integrity time for sequential sequence on 64 KB block.
Array Integrity time for sequential sequence on 256 KB block.
—
—
—
—
—
—
1024 x
Tperiod x
Nread
tai64kseq
2048 x
Tperiod x
Nread
8192 x
Tperiod x
Nread
tai256kseq
tmr16kseq
tmr32kseq
Margin Read time for sequential sequence on 16 KB block.
Margin Read time for sequential sequence on 32 KB block.
73.81
—
—
110.7
192.6
μs
μs
128.43
Table continues on the next page...
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35
Memory interfaces
Table 33. Flash memory Array Integrity and Margin Read specifications (continued)
Symbol
Characteristic
Min
Typical
Max1
Units
2
tmr64kseq
Margin Read time for sequential sequence on 64 KB block.
Margin Read time for sequential sequence on 256 KB block.
237.65
893.01
—
—
356.5
μs
μs
tmr256kseq
1,339.5
1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The
equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and
Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires
6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the
address pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
6.3.1.3 Flash memory module life specifications
Table 34. Flash memory module life specifications
Symbol
Characteristic
Conditions
Min
Typical
Units
P/E
Array P/E
cycles
Number of program/erase cycles per block
for 16 KB, 32 KB and 64 KB blocks.1
—
—
250,000
—
cycles
Number of program/erase cycles per block
for 256 KB blocks.2
1,000
250,000
P/E
cycles
Data
retention
Minimum data retention.
Blocks with 0 - 1,000 P/E 50
cycles.
—
—
—
Years
Years
Years
Blocks with 100,000 P/E
cycles.
20
Blocks with 250,000 P/E
cycles.
10
1. Program and erase supported across standard temperature specs.
2. Program and erase supported across standard temperature specs.
6.3.1.4 Data retention vs program/erase cycles
Graphically, Data Retention versus Program/Erase Cycles can be represented by the
following figure. The spec window represents qualified limits. The extrapolated dotted
line demonstrates technology capability, however is beyond the qualification limits.
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NXP Semiconductors
Memory interfaces
6.3.1.5 Flash memory AC timing specifications
Table 35. Flash memory AC timing specifications
Symbol
Characteristic
Min
Typical
Max
Units
tpsus
Time from setting the MCR-PSUS bit until MCR-DONE bit is set
to a 1.
—
9.4
11.5
μs
plus four
system
clock
plus four
system
clock
periods
periods
tesus
Time from setting the MCR-ESUS bit until MCR-DONE bit is set
to a 1.
—
16
20.8
μs
plus four
system
clock
plus four
system
clock
periods
periods
tres
Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low.
—
—
—
—
—
16
100
ns
ns
μs
tdone
tdones
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared.
5
Time from 1 to 0 transition on the MCR-EHV bit aborting a
program/erase until the MCR-DONE bit is set to a 1.
20.8
plus four
system
clock
plus four
system
clock
periods
periods
tdrcv
Time to recover once exiting low power mode.
16
—
45
μs
Table continues on the next page...
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37
Memory interfaces
Table 35. Flash memory AC timing specifications (continued)
Symbol
Characteristic
Min
Typical
Max
Units
plus seven
system
clock
plus seven
system
clock
periods.
periods
taistart
Time from 0 to 1 transition of UT0-AIE initiating a Margin Read
or Array Integrity until the UT0-AID bit is cleared. This time also
applies to the resuming from a suspend or breakpoint by
clearing AISUS or clearing NAIBP
—
—
—
5
ns
ns
taistop
Time from 1 to 0 transition of UT0-AIE initiating an Array
Integrity abort until the UT0-AID bit is set. This time also applies
to the UT0-AISUS to UT0-AID setting in the event of a Array
Integrity suspend request.
—
80
plus fifteen
system
clock
periods
tmrstop
Time from 1 to 0 transition of UT0-AIE initiating a Margin Read
abort until the UT0-AID bit is set. This time also applies to the
UT0-AISUS to UT0-AID setting in the event of a Margin Read
suspend request.
10.36
—
20.42
μs
plus four
system
clock
plus four
system
clock
periods
periods
6.3.1.6 Flash read wait state and address pipeline control settings
The following table describes the recommended RWSC and APC settings at various
operating frequencies based on specified intrinsic flash access times of the flash module
controller array at 150 °C.
Table 36. Flash read wait state and address pipeline control guidelines
Flash Frequency
RWSC setting
APC setting
0 MHz < fFLASH ≤ 33 MHz
33 MHz < fFLASH ≤ 100 MHz
100 MHz < fFLASH ≤ 133 MHz
133 MHz < fFLASH ≤ 167 MHz
167 MHz < fFLASH ≤ 200 MHz
0
2
3
4
5
0
1
1
1
2
6.3.2 QuadSPI AC specifications
• Measurements are with a load of 35 pF on output pins. Input slew: 1ns, DSE[1:0]=11
• QuadSPI input timing is with 15pF load on flash output
The following table lists various QuadSPI modes and their corresponding configurations.
These DDR configurations are applicable when used without learning. Please see the
device reference manual for register and bit descriptions.
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Table 37. QuadSPI read/write settings
QuadSPI Modes
QuadSPI_MCR[D QuadSPI_MCR[D QuadSPI_MCR
QuadSPI_SOCCR QuadSPI_FLSH
DR_EN]
QS_EN]
[SCLKCFG]
[SOCCFG]
CR[TDH]
SDR
Internal DQS 0
1
07h
002F_002Fh
00
mode
mode
DDR
4x Sampling
mode
1
0
1
1
Don't care
03h
Don't care
10
10
10
mode
(without
learning
)
Internal DQS 1
mode
002F_002Fh
0000_0000h
HyperFlash
mode
1
02h
6.3.2.1 SDR mode
1
2
3
Clock
Tck
SCK
Tcsh
Tcss
CS
Tih
Tis
Data in
Figure 11. QuadSPI input timing (SDR mode) diagram
NOTE
• A negative time indicates the actual capture edge inside the
device is earlier than clock appearing at pad.
• All board delays need to be added appropriately
• Input hold time being negative does not have any
implication or max achievable frequency
Table 38. QuadSPI input timing (SDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tis
Setup time for incoming data
Hold time for incoming data
SCK clock frequency
5.5
1.5
-
-
ns
Tih
-
ns
FSCK
80
MHz
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Memory interfaces
NOTE
For SDR mode, QuadSPI_MCR[DQS_EN] must be set as '1'.
The delay chain settings for this mode is mentioned Table 37.
1
2
3
Clock
SCK
CS
Tck
Tcsh
Tcss
Toh
Tov
Data out
Figure 12. QuadSPI output timing (SDR mode) diagram
Table 39. QuadSPI output timing (SDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tov
Output Data Valid
Output Data Hold
SCK clock period
-
2.8
ns
Toh
Tck
-1.5
-
-
ns
80
-
MHz
ns
Tcss
Tcsh
Chip select output setup time
Chip select output hold time
1
-1
-
ns
6.3.2.2 DDR mode
1
2
3
Clock
Tck
SCK
CS
Tih
Tis
Data in
Figure 13. QuadSPI input timing (DDR mode) diagram
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Memory interfaces
Table 40. QuadSPI input timing (DDR mode) specifications without learning (valid across
PVT)
Symbol
Parameter
Value
Max
Unit
Configuration
Min
Tis
Setup time for incoming 5.5
data
—
ns
Tih
Hold time for incoming 1.5
data
—
ns
FSCK
SCK Clock Frequency
—
45 (Internal DQS)
35 (4x sampling)
MHz
Refer Table 37
—
QSPI_SMPR[DDRS
MP]=1
Table 41. QuadSPI input timing (DDR mode) specifications with learning
Symbol
Parameter
Value
Unit
Note
Min
Max
FSCK
SCK Clock Frequency
—
80 (Internal DQS) 1
66 (4x sampling)
MHz Flash data valid window must be >
3.5 ns
—
Flash data valid window must be >
3.5 ns, Flash max access time must
be < = 6.5 ns
1. Multiple (dynamic) calibration across voltage/temperature on board required.
1
2
3
Clock
SCK
CS
Tck
Tcss
Tcsh
Tov
Toh
Data out
Figure 14. QuadSPI output timing (DDR mode) diagram
Table 42. QuadSPI output timing (DDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tov
Toh
Tcss
Output Data Valid
Output Data Hold
-
4.5
ns
ns
ns
1.5
1
-
-
Chip select output setup time
Table continues on the next page...
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Table 42. QuadSPI output timing (DDR mode) specifications (continued)
Symbol
Parameter
Value
Unit
Min
Max
Tcsh
Chip select output hold time
-1
-
ns
6.3.2.3 HyperFlash mode
NOTE
In HyperFlash mode, the read/write maximum frequency is 90
MHz.
RDS
TsMIN
ThMIN
DI[7:0]
Figure 15. QuadSPI input timing (Hyperflash mode) diagram
Table 43. QuadSPI input timing (Hyperflash mode) specifications
Symbol
Parameter
Value
Unit
Configurations
Min
Max
Tis
Tih
Setup time for incoming data
Hold time for incoming data
2
2
-
-
ns
ns
Refer Table 37
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CK
CK 2
TclkSKMAX
TclkSKMIN
THO
TDVO
Output Invalid Data
Figure 16. QuadSPI output timing (Hyperflash mode) diagram
Table 44. QuadSPI output timing (Hyperflash mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
TDVO
THO
Output Data Valid
Output Data Hold
-
3
-
ns
ns
ns
ns
1.3
-
TclkSKMAX
TclkSKMIN
CK to CK2 skew max
CK to CK2 skew min
T/4 + 0.5
-
T/4 - 0.5
6.3.3 SDR AC specifications
For details on read timings with and without the external capacitor and capacitance value,
refer the "Chip-specific MDDRC information" section of the device Reference Manual.
For SDRAM operating frequencies above 80 MHz the SDR_A12 pin cannot be used for
the SDRAM address. At higher operating frequencies this pin requires an external
capacitor connected with VSS to adjust the read timing.
Round trip delay (consisting of board trace delay of SDCK and DQ(READ)) should not
be more than 450 ps.
NOTE
1. All transitions measured at mid-supply (VDDE_SDR/2).
2. Data signal which are driven from ATE are given a swing
of 20%/80% of full signal swing.
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3. The DQS Config Offset Count register
(MDDRC_DQS_CFG) would need to be programmed with
value 0x0000_16h in the initialization code when operating
SDR at 160 MHz.
4. The SRE settings for SDR_CLK pad going to the external
memory should be 2'b11 (as noted in the "Section 15.3.2.1
Recommended settings for SRE pads" in the Reference
Manual). SRE settings for loopback clock A12 has been
reduced to 2'b01 in CZ to help with EMC improvement.
Table 45. SDR @ 160 MHz AC timing specification
ID
—
Symbol
tSDCK
tQVS
tQH
Parameter
Min
—
Typ
6.25
—
Max
Unit
ns
Clock Period
—
DD1
DD21
DD3
DD4
—
Data output Valid (Write transaction)
Data output Hold (Write transaction)
Data Input Setup (Read transaction)
Data input Hold (Read transaction)
CK HIGH pulse width
—
(0.5 × tSDCK) + 1.125
—
ns
1.5
-0.6
3.1
0.43
0.43
—
—
ns
tIS
—
ns
tIH
—
—
0.57
0.57
—
ns
tCH
—
tCK
tCK
ohms
—
tCL
CK LOW pulse width
—
—
—
Series termination (Data/CLK/
Address/Command)
50
—
—
Trans. line impedance (Zo)
—
50
—
ohms
1. Applies to command and address buses also.
Table 46. SDR @ 80 MHz AC timing specification
ID
—
Symbol
tSDCK
Parameter
Clock Period
Min
—
Typ
12.5
—
Max
—
Unit
ns
DD1
tQVS
Data output Valid (Write
transaction)
—
(0.5 × tSDCK) + 1.25
ns
DD21
DD3
tQH
tIS
Data output Hold (Write
transaction)
3.0
2.2
—
—
—
ns
ns
Data Input Setup (Read
transaction)
DD4
—
tIH
tCH
tCL
—
Data input Hold (Read transaction)
CK HIGH pulse width
2.0
0.43
0.43
—
—
—
—
50
—
0.57
0.57
—
ns
tCK
—
CK LOW pulse width
tCK
—
Series termination (Data/CLK/
Address/Command)
ohms
—
—
Trans. line impedance (Zo)
—
50
—
ohms
1. Applies to command and address buses also.
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Figure 17. SDR (@ 160 MHz and @ 80 MHz) AC read and write timings
6.3.3.1 SDR DC specifications
The SDR DC specifications are same as pad_fc_hv specs described in this document.
6.3.4 DDR2 SDRAM AC specifications
NOTE
DDR2-800 (-25E speed grade) is the lowest speed grade
supported. If self-refresh mechanism needs to be supported, an
external pull-down resistance needs to be connected to the DDR
CKE pin.
NOTE
Specified values in the table are at recommended operating
conditions with VDDE_DDR of 1.8 5.5%
Table 47. DDR2 SDRAM timing specifications1, 2, 3, 4, 5
ID
Symbol
Parameter
Min
Typ
Max
Unit
MHz
—
—
F
Frequency of operation
(Clock Period)
—
—
—
320
VIX-AC
MCK AC differential
crosspoint voltage
0.5 × VDDE_DDR
0.175
—
0.5 × VDDE_DDR + 0.175 V
DD1
DD2
DD3
DD4
tDDR_CLK
tDDR_CLKH
tDDR_CLKL
tCMS
Clock period
High pulse width6
3.125
0.47
0.47
—
—
—
—
—
ns
tCK
0.53
0.53
—
Low pulse width
tCK
ns
Address/Command
Output Setup
0.5 × tDDR_CLK–0.75
0.5 × tDDR_CLK–0.75
-0.18 × tDDR_CLK
DD5
DD6
tCMH
Address/Command
Output Hold
—
—
—
ns
ns
tDQSS
First DQS latching
transition to associated
clock edge
0.18 × tDDR_CLK
Table continues on the next page...
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Memory interfaces
Table 47. DDR2 SDRAM timing specifications1, 2, 3, 4, 5 (continued)
ID
Symbol
Parameter
Min
Typ
Max
Unit
DD7
tOS
Data and Data Mask
Output Setup relative to
tDDR_CLK/4 − 0.4
—
—
ns
ns
ns
DQS (DDR Write Mode)
8, 9
DD8
tOH
Data and Data Mask
Output Hold relative to
tDDR_CLK/4 − 0.4
—
—
DQS (DDR Write Mode)
7, 10
DD9
—
tIS
—
Input Data Skew relative
to DQS11
—
0.24
—
Parallel termination
address lines
—
50
Ohms
—
—
—
—
Differential clock lines
—
—
100
50
—
—
Ohms
Ohms
Trans. Line (differential
Zo)
1. VDDE_DDR value is 1.8 V for DDR2 mode
2. CZ at -40 to 125 °C.
3. Measured with clock pin loaded with differential 100 ohm termination resistor.
4. All transitions measured at mid-supply (VDDE_DDR/2).
5. Measured with all outputs except the clock loaded with 50 ohm termination resistor to VDDE_DDR/2.
6. Pulse width high + pulse width low cannot exceed minimum and maximum clock period.
7. The losses for IO and package are 190 ps and are already included in the 400 ps budget taken by the device.
8. This specification relates to the required input setup time of DDR memories. The chip output setup should be larger than
the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation. DDR_DQ[31:24]
is relative to DDR_DQS[3]; DDR_DQ[23:16] is relative to DDR_DQS[2], DDR_DQ[15:8] is relative to DDR_DQS[1] and
DDR_DQ[7:0] is relative to DDR_DQS[0].
9. The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
are valid for each subsequent DQS edge.
10. This specification relates to the required hold time of DDR memories. DDR_DQ[31:24] is relative to DDR_DQS[3];
DDR_DQ[23:16] is relative to DDR_DQS[2], DDR_DQ[15:8] is relative to DDR_DQS[1] and DDR_DQ[7:0] is relative to
DDR_DQS[0].
11. Data input skew is derived from each DDR_DQS clock edge. It begins with a DDR_DQS transition and ends when the last
data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to
routing or other factors).
Figure 18 shows the DDR2 SDRAM write timing.
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DD1
DD2
DDR_CLK
DDR_CLK
DD4
DD3
DD5
,
DDR_CSn
DDR_WE
CMD
DDR_CAS
DDR_RAS ,
DDR_A[15:0]
ROW
COL
DDR_DQS
DD7
WD1 WD2 WD3 WD4
DD7
DDR_D[31:0]
DQS
DD6
DQ, DM(out)
tDS
tDH
Figure 18. DDR2 write timing
Figure 19 shows the DDR2 SDRAM read timing.
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DD1
DD2
DDR_CLK
DD3
DDR_CLK
CL= 4
DD5
DDR_CSn::, DDR_WE
DDR_RAS, DDR_CAS
CMD
ROW
DD4
CL= 5
COL
DDR_A[15:0]
DDR_DQS
DQS Read
Preamble
DD9
DQS Read
Postamble
DDR_D[7:0]
RD1 RD2 RD3 RD4
DQS Read
Postamble
DQS Read
Preamble
DDR_DQS
DDR_D[7:0]
RD1 RD2 RD3 RD4
Figure 19. DDR2 read timing
6.4 Communication modules
6.4.1 SPI electrical specifications
Table 48. SPI electrical specifications
No
1
Symbol
tSCK
Parameter
Conditions
High Speed Mode
low Speed mode
Unit
ns
Min
25
Max
—
Min
50
Max
—
SPI cycle time Master (MTFE = 0)
Slave (MTFE = 0)
40
—
60
—
2
tCSC
PCS to SCK
delay
—
16
—
—
—
ns
3
4
5
tASC
tSDC
tA
After SCK delay
SCK duty cycle
—
—
16
tSCK/2 - 1
—
—
tSCK/2 + 1
40
—
—
—
—
—
—
ns
ns
ns
Slave access SS active to SOUT
time valid
6
7
tDIS
Slave SOUT SS inactive to SOUT
—
25
—
—
—
—
—
ns
ns
disable time
High-Z or invalid
tPCSC
PCSx to PCSS
time
—
13
Table continues on the next page...
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Table 48. SPI electrical specifications (continued)
No
Symbol
Parameter
Conditions
High Speed Mode
low Speed mode
Unit
Min
Max
Min
Max
8
9
tPASC
tSUI
PCSS to PCSx
time
—
13
—
—
—
ns
ns
Data setup time Master (MTFE = 0)
NA
4
—
—
—
20
4
—
—
—
for inputs
Slave
Master (MTFE = 1,
CPHA = 0)
15
8
Master (MTFE = 1,
CPHA = 1)
15
—
20
—
10
11
12
tHI
tSUO
tHO
Data hold time Master (MTFE = 0)
NA
4
—
—
—
–2
4
111
—
—
—
ns
ns
ns
for inputs
Slave
Master (MTFE = 1,
CPHA = 0)
0
Master (MTFE = 1,
CPHA = 1)
0
—
-2
—
Data valid (after Master (MTFE = 0)
—
—
—
NA
15
7
—
—
—
7
SCK edge)
Slave
23
19.51
Master (MTFE = 1,
CPHA = 0)
Master (MTFE = 1,
CPHA = 1)
—
7
—
7
Data hold time Master (MTFE = 0)
for outputs
NA
—
–2
—
Slave
2
—
—
2
101
—
—
Master (MTFE = 1,
CPHA = 0)
-2
Master (MTFE = 1,
CPHA = 1)
–2
—
–2
—
1. SMPL_PTR should be set to 1
NOTE
Restriction for high speed modes:
• Maximum of one SPI will support 40 MHz Master mode
SCK
• 4 SPIs will support 20 MHz master SCK frequency.
• Maximum of one SPI will support 25 MHz Slave SCK
frequency.
• SIN(GPIO_20, PB[4]), DATAOUT(GPIO_19, PB[3]),
SCK(GPIO_27, PB[11]) groups support high frequency
mode.
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NOTE
For numbers shown in the following figures, see Table 48
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
Last Data
SIN
First Data
Data
Data
12
11
First Data
Last Data
SOUT
Figure 20. SPI classic SPI timing — master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
Data
First Data
Last Data
SIN
12
11
SOUT
Last Data
First Data
Figure 21. SPI classic SPI timing — master, CPHA = 1
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3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
11
12
Data
6
First Data
Last Data
SOUT
SIN
9
10
Data
Last Data
First Data
Figure 22. SPI classic SPI timing — slave, CPHA = 0
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Figure 23. SPI classic SPI timing — slave, CPHA = 1
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3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
10
SIN
First Data
12
Last Data
Last Data
Data
11
SOUT
First Data
Data
Figure 24. SPI modified transfer format timing — master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Figure 25. SPI modified transfer format timing — master, CPHA = 1
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3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Figure 26. SPI modified transfer format timing – slave, CPHA = 0
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Figure 27. SPI modified transfer format timing — slave, CPHA = 1
8
7
PCSS
PCSx
Figure 28. SPI PCS strobe (PCSS) timing
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6.4.2 Ethernet AC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.4.2.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 49. MII signal switching specifications
Symbol
—
Description
Min.
—
Max.
25
Unit
MHz
RXCLK frequency
RXCLK pulse width high
MII1
35%
65%
RXCLK
period
RXCLK
period
ns
MII2
RXCLK pulse width low
35%
65%
MII3
MII4
—
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
TXCLK frequency
5
5
—
—
ns
—
25
MHz
MII5
TXCLK pulse width high
35%
65%
TXCLK
period
TXCLK
period
ns
MII6
TXCLK pulse width low
35%
65%
MII7
MII8
TXCLK to TXD[3:0], TXEN, TXER invalid
TXCLK to TXD[3:0], TXEN, TXER valid
2
—
—
25
ns
MII6
MII5
MII7
TXCLK (input)
MII8
Valid data
TXD[n:0]
TXEN
Valid data
Valid data
TXER
Figure 29. RMII/MII transmit signal timing diagram
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MediaLB (MLB) electrical specifications
MII2
MII3
MII1
MII4
RXCLK (input)
RXD[n:0]
RXDV
Valid data
Valid data
Valid data
RXER
Figure 30. RMII/MII receive signal timing diagram
6.4.2.2 RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range of
transceiver devices.
Table 50. RMII signal switching specifications
Symbol
—
Description
Min.
—
Max.
50
Unit
EXTAL frequency (RMII input clock RMII_CLK)
RMII_CLK pulse width high
MHz
RMII1
35%
65%
RMII_CLK
period
RMII2
RMII_CLK pulse width low
35%
65%
RMII_CLK
period
RMII3
RMII4
RMII7
RMII8
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
RMII_CLK to TXD[1:0], TXEN invalid
4
2
—
—
—
15
ns
ns
ns
ns
4
RMII_CLK to TXD[1:0], TXEN valid
—
6.4.3 MediaLB (MLB) electrical specifications
6.4.3.1 MLB 3-wire interface DC specifications
The section lists the MLB 3-wire interface electrical specifications.
Table 51. MediaLB 3-wire interface DC specifications
Parameter
Maximum input voltage
Low level input threshold
Symbol
Test Conditions
Min
Max
Unit
—
—
—
—
3.6
0.7
V
V
VIL
—
Table continues on the next page...
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MediaLB (MLB) electrical specifications
Table 51. MediaLB 3-wire interface DC specifications (continued)
Parameter
Symbol
Test Conditions
See Note1
Min
1.8
Max
Unit
High level input threshold
Low level output threshold
High level output threshold
Input leakage current
VIH
—
V
V
V
VOL
VOH
IOL = –6 mA
IOH = –6 mA
0 < Vin < VDD
—
0.4
—
2.0
—
10
μA
IL
1. Higher VIH thresholds can be used; however, the risks associated with less noise margin in the system must be evaluated
and assumed by the customer.
6.4.3.2 MLB 3-wire interface electrical specifications
This section describes the timing electrical information of the MLB module.
Figure 31. MediaLB 3-wire Timing
Ground = 0.0 V; Load Capacitance = 60 pF, input transition= 1 ns ; MediaLB speed =
256/512 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold
as listed below; unless otherwise noted.
Table 52. MLB 3-wire 256/512 Fs Timing Parameters
Symbol
Parameter
Min
Max
25.6
Unit
MHz
Comment
fmck
MLBCLK operating frequency
11.264
256xFs at 44.0 kHz,
512xFs at 50.0 kHz
tmck
r
f
MLBCLK rise time
MLBCLK fall time
−
−
1
1
ns
ns
V
IL to VIH
tmck
V
IH to VIL
Table continues on the next page...
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MediaLB (MLB) electrical specifications
Table 52. MLB 3-wire 256/512 Fs Timing Parameters (continued)
Symbol
Parameter
MLBCLK low time1
Min
Max
Unit
Comment
256xFs
tmck
l
30
14
30
14
3
−
−
−
−
−
ns
ns
512xFs
256xFs
512xFs
−
tmck
h
MLBCLK high time
tdsmcf
tdhmcf
tmcfdz
MLBSIG/MLBDAT receiver input setup to
MLBCLK falling
ns
ns
ns
MLBSIG/MLBDAT receiver input hold from
MLBCLK low
2
−
−
MLBSIG/MLBDAT output valid from
MLBCLK low2
0
0
2
16
256xFs
512xFs3
−
12.5
−
tmdzh
Bus output hold from MLBCLK low
ns
1. MLBCLK low/high time includes the pluse width variation.
2. The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final
driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the
maximum load capacitance listed.
3. Only 1 pair of MLB pads support 512 Fs:
PK[11] - MLB Signal Output
PK[12] - MLB Data Output
PK[13] - MLB clock input
Ground = 0.0 V; Load Capacitance = 40 pF, input transition= 1 ns; MediaLB speed =
1024 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold as
listed below; unless otherwise noted.
Table 53. MLB 3-wire 1024 Fs Timing Parameters
Symbol
Parameter
Min
Max
Unit
MHz
Comment
1024 x fs at 44.0 kHz
1024 x fs at 50.0 kHz
VIL to VIH
fmck
MLBCLK Operating Frequency1
45.056
−
−
51.2
1
fmckr
fmckf
tmckl
tmckh
tdsmcf
MLBCLK rise time
MLBCLK fall time
MLBCLK low time
MLBCLK high time
−
ns
ns
ns
ns
ns
−
1
VIH to VIL
6.1
9.3
3
−
−
MLBSIG/MLBDAT receiver input setup
to MLBCLK falling
−
tdhmcf
tmcfdz
tmdzh
MLBSIG/MLBDAT receiver input hold
from MLBCLK low
2
−
2
−
ns
ns
ns
MLBSIG/MLBDAT output valid from
MLBCLK low
16
−
Bus Hold from MLBCLK low
1. The controller can shut off MLBCLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a
runt pulse can occur on MLBCLK.
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57
Display modules
6.5 Display modules
6.5.1 LCD driver electrical specifications
NOTE
When using the LCD segment display module in the 208LQFP
package options the VDDE_B and VDDE_SDR supply pins should
be shorted together if LCD signal pins are used in both I/O
supply domains.
Table 54. LCD driver specifications
Symbol
Parameter
Value1
Typ
-
Unit
Min
Max
ZBP/FP
IBP/FP
LCD output impedance (BP[n-1:0],
FP[m-1:0]) for output levels VLCD, VSS
-
10
kΩ
µA
LCD output current (BP[n-1:0],
FP[m-1:0]) for outputs charge/discharge
voltage levels VLCD2/3, VLCD1/2,
VLCD1/3) 2,3
-
-
2-180
-
Offset
Offset of outputs with capacitive load
-
50 4
mV
1. VDD = 5.0 V 10%, TA = –40 to 105 °C, unless otherwise specified.
2. Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.
3. With PWR = 0-3, BSTEN = 0-1, BSTAO = 0-1.
4. 50 mV offset is only guaranteed across temperature with BSTEN=1 / BSTAO=1 up to 85oC.
6.5.2 2D-ACE electrical specifications
6.5.2.1 Interface to TFT LCD Panels (2D-ACE)
The following figure depicts the LCD interface timing for a generic active matrix color
TFT panel. In this figure signals are shown with positive polarity. The sequence of events
for active matrix interface timing is:
• PCLK latches data into the panel on its positive edge (when positive polarity is
selected). In active mode, PCLK runs continuously. This signal frequency could be
from 5 to 80 MHz depending on the panel type.
• HSYNC causes the panel to start a new line. It always encompasses at least one
PCLK pulse.
• VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
• DE acts like an output enable signal to the LCD panel. This output enables the data
to be shifted onto the display. When disabled, the data is invalid and the trace is off.
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2D-ACE electrical specifications
VSYNC
HSYNC
LINE 1 LINE 2
LINE 3
LINE 4
LINE n-1 LINE n
HSYNC
DE
1
2
3
m-1
m
PCLK
LD[23:0]
Figure 32. TFT LCD interface timing
6.5.2.2 Interface to TFT LCD Panels—pixel level timings
The following figure depicts depicts the horizontal timing (timing of one line), including
both the horizontal sync pulse and data. All parameters shown in the diagram are
programmable. This timing diagram corresponds to positive polarity of the PCLK signal
(meaning the data and sync signals change on the rising edge) and active-high polarity of
the HSYNC, VSYNC and DE signals. The user can select the polarity of the HSYNC and
VSYNC signals via the SYN_POL register, whether active-high or active-low. The
default is active-high. The DE signal is always active-high.
Pixel clock inversion and a flexible programmable pixel clock delay are also supported.
They are programmed via the DCU Clock Confide Register (DCCR) in the system clock
module.
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register.
The PW_H, BP_H and FP_H parameters are programmed via the HSYN PARA register.
The PW_V, BP_V and FP_V parameters are programmed via the VSYN_PARA register.
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2D-ACE electrical specifications
tHSP
tFPH
tPWH
tBPH
tSW
Start of line
tPCP
PCLK
Invalid Data
Invalid Data
2
3
1
DELTA_X
LD[23:0]
HSYNC
DE
Figure 33. Horizontal sync pulse
tVSP
tSH
tFPV
tBPV
tPWV
Start of Frame
HSYNC
tHCP
LD[23:0]
(Line Data)
2
DELTA_Y
1
Invalid Data
3
Invalid Data
VSYNC
DE
Figure 34. Vertical sync timing
Table 55. TFT LCD interface timing parameters—horizontal and vertical
Symbol
tPCP
Parameter
Display pixel clock period
Value
Unit
12.5
ns
ns
ns
ns
ns
ns
ns
tPWH
tBPH
tFPH
tSW
HSYNC pulse width
HSYNC back porch width
HSYNC front porch width
Screen width
PW_H × tPCP
BP_H × tPCP
FP_H × tPCP
DELTA_X × tPCP
tHSP
tPWV
HSYNC (line) period
VSYNC pulse width
(PW_H + BP_H + FP_H + DELTA_X ) × tPCP
PWV × tHSP
Table continues on the next page...
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NXP Semiconductors
2D-ACE electrical specifications
Table 55. TFT LCD interface timing parameters—horizontal and vertical (continued)
Symbol
tBPV
tFPV
tSH
Parameter
VSYNC back porch width
Value
Unit
BP_V × tHSP
ns
ns
ns
ns
VSYNC front porch width
Screen height
FP_V × tHSP
DELTA_Y × tHSP
tVSP
VSYNC (frame) period
(PW_V + BP_V + FP_V + DELTA_Y ) × tHSP
6.5.2.3 Interface to TFT LCD panels—access level
1
2
3
4
5
6
7
8
9
10
Pixel Clock
Data Bus
tHO
tDV
Valid Data
Figure 35. Display timing diagram
Table 56. Interface to TFT LCD panels—access level
Symbol
Parameter
Min
Max
Unit
Tpix
TDV
Pixel clock frequency
-
-
80
MHz
ns
Data valid after pixel
clock for Data/Hysnc/
Vsync/DE
4.5
THO
Output hold time for
data and control bits
0
-
-
ns
ns
Tskew
Relative skew between
data bits
3
NOTE
The timing diagram is on the assumption that timing path
between this device and external display is full cycle.
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2D-ACE electrical specifications
6.5.3 Video input unit (VIU4) electrical specifications
Clock
fPIX_CLK
tDHD
tDSU
Data
/HSYNC/VSYNC/FID/FE
Figure 36. VIU4 timing diagram
Table 57. VIU4 timing parameters
Symbol
Parameter
VIU4 pixel clock frequency
Min
Typ
Max
Unit
MHz
fPIX_CK
tDSU
—
4
—
—
—
53
—
—
VIU4 data setup time
VIU4 data hold time
ns
ns
tDHD
1
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TCON electrical specifications
6.5.4 TCON electrical specifications
6.5.4.1 TCON RSDS electrical specifications
1
2
3
4
5
6
7
8
9
10
PixelClock
Pixel Data
TCON
Clock In
TCON Divided
Clock Out
(50 MHz)
Pixel Data Out
TOV
TOV
TOH
TOH
Figure 37. TCON RSDS timing diagram
Table 58. TCON RSDS timing parameters
Symbol
Parameter
Value
Unit
Min
Max
TOV
TOH
Output data valid time
Output data hold time
2
2
-
-
ns
ns
6.5.4.2 TCON TTL electrical specifications
1
2
3
4
5
6
7
8
9
10
Pixel Clock
Data Bus and
Timing Signals
t
HO
t
DV
Valid Data
Figure 38. TCON TTL timing diagram
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Motor control modules
Table 59. TCON TTL timing parameters
Symbol
Tpix
Parameter
Min
Max
80
Unit
MHz
ns
Pixel clock frequency
-
-
TDV
Data valid after pixel clock for data and timing
signals
5.5
THO
Output hold time for data and control bits
Relative skew between data bits
0
-
-
ns
ns
Tskew
3
6.6 Motor control modules
6.6.1 Stepper Stall Detect (SSD) specifications
Table 60. SSD electrical specifications
Symbol
Parameter
Value1
Unit
Min
Typ
Max
VVREF
IVREF
RIN
Reference voltage
(IVREF = 0)
VDDM/2 – 0.03
VDDM/22
VDDM/22 + 0.03
V
mA
MΩ
V
Reference voltage
output current
1.85
0.8
—
1.0
—
—
1.2
Input resistance
(against VDDM/2)
VIN
Input common
mode range
VSSM
VDDM
SSDCONST
SSDOFFSET
SSD constant 3
0.539
–53
0.574
—
0.610
45
—
SSD offset
counts
(unipolar, Nsample
1024)
=
SSD offset (bipolar,
Nsample = 1024)
-40
-5
—
—
40
5
SSD offset (bipolar
with offset cellation,
Nsample = 1024)
fSSDSMP
SSD cmpout
sample rate
0.5
—
2.0
MHz
1. VDDM_SMD = 5.0 V 10%, Tj = –40 to +125 °C.
2. VDDM is the voltage level of VDDM_SMD supply
3. If offset cancellation is enable, OFFCNC must equal 0b01 and the integration window must be greater than or equal to 2
ms. The integration window = fSSDSMP x Nsample.
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Debug specifications
6.7 Debug specifications
6.7.1 JTAG interface timing
Table 61. JTAG pin AC electrical characteristics 1
#
1
Symbol
tJCYC
Characteristic
Min
62.5
40
—
Max
Unit
ns
%
TCK Cycle Time
—
60
3
2
tJDC
TCK Clock Pulse Width
TCK Rise and Fall Times (40% - 70%)
3
tTCKRISE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
tTMSS, tTDIS TMS, TDI Data Setup Time
tTMSH, tTDIH TMS, TDI Data Hold Time
5
—
5
5
—
6
tTDOV
tTDOI
TCK Low to TDO Data Valid
TCK Low to TDO Data Invalid
TCK Low to TDO High Impedance
JCOMP Assertion Time
—
20
—
7
0
8
tTDOHZ
tJCMPPW
tJCMPS
tBSDV
—
15
—
9
100
40
—
10
11
12
JCOMP Setup Time to TCK Low
TCK Falling Edge to Output Valid
—
600
600
tBSDVZ
TCK Falling Edge to Output Valid out of High
Impedance
—
13
14
15
tBSDHZ
tBSDST
tBSDHT
TCK Falling Edge to Output High Impedance
Boundary Scan Input Valid to TCK Rising Edge
TCK Rising Edge to Boundary Scan Input Invalid
—
15
15
600
—
ns
ns
ns
—
1. These specifications apply to JTAG boundary scan only.
TCK
2
3
3
2
1
Figure 39. JTAG test clock input timing
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Debug specifications
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 40. JTAG test access port timing
TCK
10
JCOMP
9
Figure 41. JTAG JCOMP timing
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Debug specifications
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 42. JTAG boundary scan timing
6.7.2 Debug trace timing specifications
Table 62. Debug trace operating behaviors
Symbol
Tcyc
Twl
Description
Min.
Max.
Unit
MHz
ns
Clock period
40
Low pulse width
High pulse width
Data output valid
Data output hold
2
—
—
—
—
Twh
2
ns
tDV
7.5
0.5
ns
tHO
ns
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Debug specifications
TRACECLK
T
r
T
f
T
T
wh
wl
T
cyc
Figure 43. TRACE_CLKOUT specifications
traceoutput clock
traceoutput data
t
HO
t
DV
Figure 44. Trace data specifications
6.7.3 Wakeup Unit (WKPU) AC specifications
Table 63. WKPU glitch filter specifications
No.
1
Symbol
WF
Parameter
Min
—
Typ
—
Max
20
Unit
ns
Pulse width that is rejected
Pulse width that is passed
2
WNF
400
—
—
ns
6.7.4 External interrupt timing (IRQ pin)
Table 64. External interrupt timing specifications
No.
1
Symbol
tIPWL
Parameter
Conditions
Min
3
Max
Unit
tCYC
tCYC
tCYC
IRQ pulse width low
IRQ pulse width high
IRQ edge to edge time
—
—
—
—
—
—
2
tIPWH
3
3
tICYC
6
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Thermal attributes
These values applies when IRQ pins are configured for rising edge or falling edge events,
but not both.
IRQ
1
2
3
Figure 45. External interrupt timing
7 Thermal attributes
7.1 Thermal attributes
Board type
Symbol
Description
208LQFP
Unit
Notes
Single-layer (1s)
RθJA
Thermal
19.1
16.4
12.4
12.4
°C/W
°C/W
°C/W
°C/W
1,2
resistance, junction
to ambient (natural
convection)
Four-layer (2s2p)
Single-layer (1s)
Four-layer (2s2p)
RθJA
Thermal
1,2,3
1,3
resistance, junction
to ambient (natural
convection)
RθJMA
Thermal
resistance, junction
to ambient (200 ft./
min. air speed)
RθJMA
Thermal
1,3
resistance, junction
to ambient (200 ft./
min. air speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal
resistance, junction
to board
7.4
5.3
0.2
°C/W
°C/W
°C/W
4
5
6
Thermal
resistance, junction
to case
Thermal
characterization
parameter, junction
to package top
Table continues on the next page...
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Thermal attributes
Board type
Symbol
Description
208LQFP
Unit
Notes
—
ΨJB
Thermal
characterization
0.3
°C/W
7
parameter, junction
to package bottom
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package. With provided Theta-JB, Max junction temperature must be 125
degreeC.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction
temperature per JEDEC JESD51-12.
Board type
Symbol
Description
516MAPBGA
Unit
Notes
Single-layer (1s)
RθJA
Thermal
23.2
°C/W
°C/W
°C/W
°C/W
1,2
resistance, junction
to ambient (natural
convection)
Four-layer (2s2p)
Single-layer (1s)
Four-layer (2s2p)
RθJA
Thermal
16.2
15.9
12.2
1,2,3
1,3
resistance, junction
to ambient (natural
convection)
RθJMA
Thermal
resistance, junction
to ambient (200 ft./
min. air speed)
RθJMA
Thermal
1,3
resistance, junction
to ambient (200 ft./
min. air speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal
resistance, junction
to board
7.0
3.7
0.1
°C/W
°C/W
°C/W
4
5
6
Thermal
resistance, junction
to case
Thermal
characterization
parameter, junction
to package top
—
ΨJB
Thermal
2.7
°C/W
7
characterization
parameter, junction
to package bottom
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Dimensions
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package. With provided Theta-JB, Max junction temperature must be 125
degreeC.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction
temperature per JEDEC JESD51-12.
8 Dimensions
8.1 Obtaining package dimensions
Package dimensions are provided in package drawing.
To find a package drawing, go to http://www.nxp.com and perform a keyword search for
the drawing’s document number:
Package
208 LQFP
Body Size
Pitch
0.5 mm
1.0 mm
NXP Document Number
98ASA00649D
28 mm x 28 mm
27 mm x 27 mm
516 MAPBGA
98ASA00623D
9 Pinouts
9.1 Package pinouts and signal descriptions
For package pinouts and signal descriptions, refer to the Reference Manual.
10 Revision History
The following table provides a revision history for this document.
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Revision History
Table 65. Revision History
Rev. No.
Date
Substantial Changes
7
18 May
2017
• In Figure 1, corrected ENET module connectivity (was '32-bit AHB' now 'two instances of 64-bit
AXI'), removed '1.2 V regulator' from the Power sub-block.
• In Ordering information section,
• removed 1M Flash part, Qualification Level 'M' and Core Configuration 4 (M4, M0+)
• clarified temperature as Ta
• In Power consumption table, removed IOP modes related content and removed footnote in tcst
"There could be 10% variation based on the characterization".
• In Voltage regulator electrical specifications,
,
• removed references to LPREG
• renamed 'Recommended decoupling capacitor values' section heading to Decoupling
capacitor values
• updated 'recommendations' to 'requirements' in the first sentence
• In Voltage monitor electrical specifications, removed VLVD_LV_PD1_hot
.
• In Slow Oscillator (SXOSC) electrical specifications, removed the footnote in Stop Mode max
value, "This parameter is characterized before qualification rather than 100% tested"
• In Table 45, updated DD3 as -0.6 ns and DD4 as 3.1 ns.
• In Interface to TFT LCD Panels—pixel level timings swapped the figure titles for 'Vertical sync
pulse' and 'Horizontal sync timing' figures. Updated the second instance of HSYNC with VSYNC
in the 'Horizontal sync timing' figure.
• In Figure 36, added HSYNC, VSYNC, FID and FE signals.
6
22 Nov
2016
• In Voltage monitor electrical specifications table, updated VLVD_IO_A_LO fall trimmed values 'Typ'
and 'Max' to 3.0260 V and 3.0750 V respectively.
• In Recommended operating conditions table,
• removed the phrase, "Design may experience up to 30 mA.........additional current.
• In Flash memory program and erase specifications changed symbols for specifications:
• Quad-page (1024 bits) program time: Changed symbol from tqppgn to tqppgm
• 16 KB Block program time: Changed symbol from t16kpgn to t16kpgm
• In Flash memory AC timing specifications for tpsus
:
• Changed Typical from 7 µs plus four system clock periods to 9.4 µs plus four system clock
periods
• Changed Max from 9.1 µs plus four system clock periods to 11.5 µs plus four system clock
periods
5
05 May
2016
• Updated part number from MAC57D5xx to SAC57D5xx throughout the document.
• Changed the term 'Freescale' to 'NXP':
• In Determining valid orderable parts : web link address changed to NXP
• In Electromagnetic Compatibility (EMC) specifications : changed Freescale to NXP.
• Removed CAN-FD references from:
• system connectivity row of Table 1,
• communication bullet in "Features".
• In the feature list, removed the phrase 'using external ballast transistor' from 'External 3.3 V input
supply'.
• Removed reference to 176 LQFP package from the following sections:
• Table 1
• Ordering information
• LCD driver electrical specifications
• Thermal attributes
• Obtaining package dimensions
• In Recommended operating conditions,
• removed phrase, "....and internal regulator cannot be used if peak application demand is
more than 800 mA".
• added a phrase, 'Design may experience up to 30 mA.........additional current'.
• In Voltage regulator electrical specifications,
Table continues on the next page...
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Revision History
Table 65. Revision History (continued)
Rev. No.
Date
Substantial Changes
• removed VRC_CTL and all connection to FPREG, RC_BALLAST and HDD_HV_BALLAST
related content in the Voltage regulator capacitance connection figure and Voltage regulator
electrical specifications table,
• removed VDD_HV_BALLAST options section,
• updated Decoupling capacitor values.
• In Table 5,
• removed 'VLVD_FLASH' and 'VLVD_FLASH during low power mode using LPBG as reference'
parameters.
• updated VHVD_LV_cold fall trimmed typical value.
• In Power consumption section,
• updated Table 6 for standby current specs for 25oC,
• removed VDDE_B supply name from footnote 5,
• removed figure, "3.3 V Vreg Supply, External Ballast. DDR2, Mixed 3.3 V / 5 V IO",
• renamed Figure 4 title from '1.2 V External Supply, DDR2, Mixed 3.3 V / 5 V IO' to 'Supply
configuration', removed VRC_CTL block from the figure.
• In Table 11, added Vol and Voh specs.
• In Table 13 updated Ioh(dc) and Iol(dc) minimum values.
• In Table 17, removed 'Vsum', 'Voh delta / Vol delta', 'Rdsonh' and 'Rdsonl' parameters.
• Removed the column for 'Prop. Delay' parameter from the following tables:
• Table 8
• Table 10
• Table 12
• Table 16
• Table 18
• Removed reference to 5V Typ and 5.5V max in Table 19 and Table 20.
• In Table 24,
• updated min and max values for 'INL' parameter.
• removed '5V Reference Voltage' row in IDAC6b parameter.
• In Table 28,
• updated 'Temp Dependence' value as 600 ppm/C,
• updated 'Supply Dependence' as 18%V,
• updated 'Oscillator Frequency' as 119 KHz (min) and 136.5 KHz (max),
• added 'Supply Current (Run)' as 2.75 uA and 'Supply Current (Stop)' as 200 nA.
• In Table 27, updated TSTJIT value to '1.5%' and TLTJIT value to '0.2%'
• In Table 29 updated Modulation Depth (Center Spread), max value updated to +/- 3.0%.
• In SDR AC specifications,
• added note, 'All transitions measured at mid-supply ..........with EMC improvement'.
• added footnotes for DD1 and DD2 specs of Table 45 and Table 46 that these parameters
also apply to command and address buses.
• In Table 47, updated DD2 and DD3 values and unit.
• In Table 54, in footnote 4, added phrase '..up to 85oC'.
• In Table 55 updated 'Display pixel clock period' (tPCP) value to 12.5 ns.
• In Table 60, updated the values for all parameters of SSDOFFSET and added footnote 3.
4
17 Jun
2015
• In "Recommended operating conditions", removed phrase, "VDDE_A (4.5 V to 5.5 V) configuration
is only supported in 176 LQFP".
• In "LVDS pads electrical specifications",
• Vdde parameter, updated foonote, from "VDDE is the VDDE_OLDI supply" to "VDDE is the
VDDE_B supply"
• "Differential o/p voltage" parameter, added foonote, "The limit applies to the default drive
current".
• "Rise/Fall time" parameter, added footnote, "Rise/fall time is assumed to be measured with
20%-80% levels".
• In "Analog Comparator (CMP) electrical specifications", updated min VAIO from -35 mV to -42 mV
and max VAIO from 35 mV to 42 mV.
• Editorial changes in "Memory Interfaces" section.
Table continues on the next page...
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Revision History
Table 65. Revision History (continued)
Rev. No.
Date
Substantial Changes
• In "QuadSPI electrical specifications",
• updated table title from "QuadSPI delay chain read/write settings" to "QuadSPI read/write
settings" and revised the content.
• revised notes in the "SDR mode" section.
• "QuadSPI input timing (SDR mode)" diagram, renamed SFCK to SCK
• "QuadSPI output timing (SDR mode)" diagram, renamed SFCK to SCK
• "QuadSPI input timing (SDR mode) specifications" table, added "FSCK" parameter
• removed notes in the "DDR mode" section.
• added new table, "QuadSPI input timing (DDR mode) specifications with learning".
• "QuadSPI output timing (DDR mode) specifications" table, removed "Tck ".
• "QuadSPI output timing (Hyperflash mode) specifications" table, renamed "TdvMAX" to "TDVO
".
• In "SDR AC specifications",
• SDR @ 160 MHz AC timing specification table, moved value of tSDCK from Min to Typ
• SDR @ 80 MHz AC timing specification table, moved value of tSDCK from Min to Typ
• In "DDR2 SDRAM AC specifications", added a note, "If self-refresh mechanism needs to be
supported, an external pull-down resistance needs to be connected to the DDR CKE pin".
• Revised "TCON RSDS timing diagram"
• In "TCON RSDS timing parameters" table, updated TDS to TOV and updated TH to TOH
.
3
13 March
2015
• Updated High Level Block Diagram
• Updated Family Comparison table
• In Absolute maximum ratings table
• Removed Vss and Tj spec. Added footnote, "Tj=125°C. Assumes Ta=105°C. Assumes
maximum θJA of 2s2p board. See Thermal attributes section for details." Updated
description of VINA spec.
• Removed VDD_HV_FLA parameter.
• In Recommended operating conditions section, added the following paragraph: The following
table describes .... in the given range.
• In Recommended operating conditions (VDDE_x = 3.3 V)
• removed the footnote "This supply should be shorted on board with VSSA.VDDA_REF Min
voltage changed to 3.15V from -3.15V
• Recommended operating conditions (VDDE_x = 5 V) table:
• Clarified parameter description for several paramters
• Removed Vss
• VSSEH_ADC: Updated min to -0.1 and max to 0.1V.
• Added footnote: All parameters are with reference to Vss, unless otherwise
specified.
• Added Tj condition in the footnote.
• Added a footnote in VDD12 pin description in Recommended operating
conditions (VDDE_x = 3.3 V) table: VDD_LV supply pins should never be
grounded (through a small impedance). If these are not driven, they should only
be left floating.
• In Voltage regulator electrical specifications section,
• Changed the text "Supports up to 800 mA load internal generation of the 3.3 V flash supply
when device connected in 5 V applications" into following bullet:
• Supports up to 800mA current (on VDD12 supply) when using external NPN ballast
transistor for generating core supply
• Updated Voltage regulator capacitance connection figure to remove Flash voltage
regulator, VDD_HV_FLA and CFLASH_REG
• In block description, changed low range to low threshold and high range to high threshold.
In Voltage regulator electrical specifications table, added Combined ESR of external
capacitor parameter for Clp/ulp_reg. Added a foonote in the Cflash_reg
• Added VDD_HV_BALLAST options section
Table continues on the next page...
SAC57D54H, Rev. 7, 05/2017
74
NXP Semiconductors
Revision History
Table 65. Revision History (continued)
Rev. No.
Date
Substantial Changes
In Voltage monitor electrical specifications table,
• Updated parameter description to remove the term internal/external from LV supply.
• Removed VLVD_IO_A_HI parameter, added parameter description for "VLVD_FLASH
during low power mode using LPBG as reference", in footnote 3, renamed VDD_HV_FLA to
flash HV supply.
In Power consumption table,
• removed reference to "5 V Vreg Supply, External Ballast, 5 V only IO" figure, updated 3.3 V
Vreg Supply, External Ballast. DDR2, Mixed 3.3 V / 5 V IO figure and 1.2 V External Supply,
DDR2, Mixed 3.3 V / 5 V IO figure.
3
13 March
• In DC electrical specifications @ 3.3 V Range,
(continue 2015
d)
• Updated Pull_Ioh with Pull_Ioh_vil_hys data and its values, updated Pull_Iol with
Pull_Iol_vil_hys data and its values
• In DC electrical specifications @ 5 V Range,
• Updated Pull_Ioh with Pull_Ioh_vil_hys data and its values, updated Pull_Iol with
Pull_Iol_vil_hys data and its values
• In DDR2 pads AC electrical specifications at 1.8V VDDE_DDR,added reference to
SIUL_MSCR[SRE] in the Drive Strength Select cell.
• In RSDS pads electrical specifications, updated Data rate TYP and MAX to 50 MHz, added
Tskew value
• In LVDS pads electrical specifications, updated Rise/Fall time specification for open LDI LVDS
pads from 1.5 ns to 800 ps.
• In ADC conversion characteristics (for 12-bit) table,
• renamed TUEIS1WINJ to TUE for precision channels
• added parameter name as Trecovery for STOP mode to Run mode recovery time
• added parameter - ADC Analog Pad
• aded Total unadjusted error with current injection
• removed footnote in "Conditions" column
• Revised the whole section "Comparator and 6-bit DAC electrical specifications table"
• In Fast Oscillator electrical characteristics table, removed FOSC VIH/VIL Min and Max spec and
replaced with TYP specs: VIH as 1.84V, VIL as 1.48V .
• In Fast internal RC Oscillator electrical specifications table, removed FUntrimmed spec
• In Slow internal RC oscillator electrical specifications table, removed Foscu spec.
• Revised PLL electrical specifications table
• Revised the whole section "Flash Read Wait State and Address Pipeline Control Guidelines"
• In LCD driver electrical specifications, added offset, IBP/FP, ZBP/FP
• In 208LQFP and 516BGA thermal attribute tables, for RθJB updated footnote to add, "With
provided Theta-JB, Max junction temperature must be 125 degreeC".
3
13 March
• Revised Voltage monitor electrical specifications
(continue 2015
d)
• Revised Voltage regulator electrical specifications
• Revised Power consumption specifications
• Revised SSD electrical specifications
• Updated SAR-ADC electrical specifications by providing values for both 12-bit and 10-bit modes
• Revised QuadSPI, VIU and TCON specifications
• Updated Debug trace operating behaviors
• Renamed VDD_0P9_DDR to DDR_VREF throughout the document
2
20 May
2014
• Updated device part number to MAC57D54H
• "Feature list", updated Program and Data Trace support from "32-bit" to "16-bit"
Table continues on the next page...
SAC57D54H, Rev. 7, 05/2017
NXP Semiconductors
75
Revision History
Table 65. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Updated block diagram, added detailed block diagram.
• Revised "Feature Sets" table.
• Removed parameter classifications throughout the document.
• Revised "Ordering information" section.
• Removed "Key electrical parameter" section.
• Revised "Absolute maximum ratings" table.
• In the "Recommended operating conditions (VDDE_x = 3.3 V)", revised note, added VDDA_REF,
updated footnote with VDD_HV_FLA.
• In the "Recommended operating conditions (VDDE_x = 3.3 V)", revised note, added VDDA_REF,
updated footnote with VDD_HV_FLA.
• Added Voltage monitor electrical specifications
2
20 May
• In the "Voltage regulator electrical specifications", renamed VDD_PMC to VDDE_A, removed
CHV_VDD_A, CHV_ADC, CHV_ADR, added a new section, "Recommended decoupling capacitor
value".
(continue 2014
d)
• In the "Voltage monitor electrical specifications", updated VLVD_FLASH configuration and threshold.
• In the "Power consumption" table, updated Target Typ and Target Max for IOP Run Mode, IOP
Stop Mode, Standby Mode. Added footnote for Standby Mode parameter.
• Added note below Figure 6.
• Revised "Electromagnetic Compatibility (EMC) specifications".
• In the "Functional Pad AC Specifications @ 3.3 V Range table", added recommended settings,
removed asymmetry drive load, added footnote: "Auto levels are applicable only to the ADC pins"
• In the "DC electrical specifications @ 3.3 V Range table", removed footnote showing ramp rate.
• In the "Functional Pad AC Specifications @ 5 V Range table", added recommended settings,
removed asymmetry drive load.
• In the "DDR2 pads AC electrical specifications at 1.8 V VDDE_DDR table",updated Prop. Delay
(ns) L>H/ H>L.
• In the "SSTL_18 Class II 1.8 V DDR2 DC specifications table", updated VDD12, removed
JESD8-15 A notes from VDD0P9_DDR
.
• In the "SMC 5 V IO DC specifications", added Rdsonh, Rdsonl
.
• In the "SMC 5V pads IO AC specifications", updated pad_smc_io _hv values.
• In the "SMC 3.3 V pads IO DC specifications", added Rdsonh, Rdsonl
• In the "SMC 3.3 V functional pads IO DC specifications", updated pad_smc_io _hv values.
1
30 Jan
2014
• Updated family comparison table
• Updated Ordering information
• Updated Absolute Maximum Ratings and Recommended Operating Conditions tables
• Updated Power consumption table
• Revised parameter classifications in several tables
• Updated Main oscillator electrical characteristics table
• Added DDR2 Read timing figure in the DDR2 SDRAM AC specifications section and revised the
parameter values
• Updated QuadSPI Input timing (RPC mode) table
SAC57D54H, Rev. 7, 05/2017
76
NXP Semiconductors
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Document Number SAC57D54H
Revision 7, 05/2017
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