935318386557 [NXP]
Microcontroller;
| 型号： | 935318386557 |
| 厂家： | 
NXP |
| 描述： | Microcontroller 时钟 微控制器 外围集成电路 |
| 文件： | 总37页 (文件大小：564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC9S08PT60
Rev. 3, 4/2012
Freescale Semiconductor
Data Sheet: Technical Data
MC9S08PT60
MC9S08PT60 Series
Support: MC9S08PT60 and
MC9S08PT32
Features
Development support
•
•
8-Bit S08 central processor unit (CPU)
– Up to 20 MHz bus at 2.7 V to 5.5 V across
temperature range of -40 °C to 105 °C
– Supporting up to 40 interrupt/reset sources
– Supporting up to four-level nested interrupt
– On-chip memory
– Single-wire background debug interface
– Breakpoint capability to allow three breakpoints
setting during in-circuit debugging
– On-chip in-circuit emulator (ICE) debug module
containing two comparators and nine trigger modes
•
Peripherals
– Up to 60 KB flash read/program/erase over full
operating voltage and temperature
– Up to 256 byte EEPROM; 2-byte erase sector;
program and erase while executing flash
– Up to 4096 byte random-access memory (RAM)
– Flash and RAM access protection
– ACMP - one analog comparator with both positive
and negative inputs; separately selectable interrupt
on rising and falling comparator output; filtering
– ADC - 16-channel, 12-bit resolution; 2.5 µs
conversion time; data buffers with optional
watermark; automatic compare function; internal
bandgap reference channel; operation in stop mode;
optional hardware trigger
Power-saving modes
– One low-power stop mode; reduced power wait
mode
– Peripheral clock enable register can disable clocks to
unused modules, reducing currents; allows clocks to
remain enabled to specific peripherals in stop3 mode
•
•
– CRC - programmable cyclic redundancy check
module
– FTM - three flex timer modulators modules
including one 6-channel and two 2-channel ones;
16-bit counter; each channel can be configured for
input capture, output compare, edge- or center-
aligned PWM mode
– IIC - One inter-integrated circuit module; up to 400
kbps; multi-master operation; programmable slave
address; supporting broadcast mode and 10-bit
addressing
Clocks
– Oscillator (XOSC) - loop-controlled Pierce
oscillator; crystal or ceramic resonator range of
31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz
– Internal clock source (ICS) - containing a frequency-
locked-loop (FLL) controlled by internal or external
reference; precision trimming of internal reference
allowing 1% deviation across temperature range of 0
°C to 70 °C and 2% deviation across temperature
range of -40 °C to 105 °C; up to 20 MHz
– MTIM - Two modulo timers with 8-bit prescaler and
overflow interrupt
– RTC - 16-bit real timer counter (RTC)
– SCI - three serial communication interface (SCI/
UART) modules optional 13-bit break; full duplex
non-return to zero (NRZ); LIN extension support
– SPI - one 8-bit and one 16-bit serial peripheral
interface (SPI) modules; full-duplex or single-wire
bidirectional; master or slave mode
– TSI - supporting up to 16 external electrodes;
configurable software or hardware scan trigger; fully
support freescale touch sensing software library;
capability to wake MCU from stop3 mode
System protection
•
– Watchdog with independent clock source
– Low-voltage detection with reset or interrupt;
selectable trip points
– Illegal opcode detection with reset
– Illegal address detection with reset
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2011–2012 Freescale Semiconductor, Inc.
Input/Output
•
•
– 57 GPIOs including one output-only pin
– Two 8-bit keyboard interrupt modules (KBI)
– Two true open-drain output pins
– Eight, ultra-high current sink pins supporting 20 mA source/sink current
Package options
– 64-pin LQFP; 64-pin QFP
– 48-pin LQFP
– 44-pin LQFP
– 32-pin LQFP
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
2
Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................4
5.2.2 Debug trace timing specifications.........................15
5.2.3 FTM module timing...............................................16
5.3 Thermal specifications.......................................................17
5.3.1 Thermal characteristics.........................................17
6 Peripheral operating requirements and behaviors....................18
6.1 External oscillator (XOSC) and ICS characteristics...........18
6.2 NVM specifications............................................................20
6.3 Analog...............................................................................21
6.3.1 ADC characteristics...............................................21
6.3.2 Analog comparator (ACMP) electricals.................25
6.4 Communication interfaces.................................................25
6.4.1 SPI switching specifications..................................25
6.5 Human-machine interfaces (HMI)......................................28
6.5.1 TSI electrical specifications...................................28
7 Dimensions...............................................................................29
7.1 Obtaining package dimensions.........................................29
8 Pinout........................................................................................29
8.1 Signal multiplexing and pin assignments...........................29
8.2 Device pin assignment......................................................33
9 Revision history.........................................................................36
1.1 Determining valid orderable parts......................................4
2 Part identification......................................................................4
2.1 Description.........................................................................4
2.2 Format...............................................................................4
2.3 Fields.................................................................................4
2.4 Example............................................................................5
3 Parameter Classification...........................................................5
4 Ratings......................................................................................5
4.1 Thermal handling ratings...................................................5
4.2 Moisture handling ratings..................................................6
4.3 ESD handling ratings.........................................................6
4.4 Voltage and current operating ratings...............................6
5 General.....................................................................................7
5.1 Nonswitching electrical specifications...............................7
5.1.1 DC characteristics.................................................7
5.1.2 Supply current characteristics...............................12
5.1.3 EMC performance.................................................13
5.2 Switching specifications.....................................................14
5.2.1 Control timing........................................................14
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
3
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to http://www.freescale.com and perform a part number
search for the following device numbers: PT60 and PT32.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
MC 9 S08 PT AA B CC
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
• MC = fully qualified, general market flow
• 9 = flash based
MC
9
Qualification status
Memory
S08
PT
AA
Core
• S08 = 8-bit CPU
Device family
• PT
Approximate flash size in KB
• 60 = 60 KB
• 32 = 32 KB
B
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
Table continues on the next page...
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
4
Freescale Semiconductor, Inc.
Parameter Classification
Field
Description
Values
• QH = 64-pin QFP
CC
Package designator
• LH = 64-pin LQFP
• LF = 48-pin LQFP
• LD = 44-pin LQFP
• LC = 32-pin LQFP
2.4 Example
This is an example part number:
MC9S08PT60VQH
3 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods.
To give the customer a better understanding, the following classification is used and the
parameters are tagged accordingly in the tables where appropriate:
Table 1. Parameter Classifications
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant sample size
across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices under
typical conditions unless otherwise noted. All values shown in the typical column are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the
parameter tables where appropriate.
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
5
Ratings
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-4000
+4000
V
1
VCDM
ILAT
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 105°C
-500
-100
+500
+100
V
2
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in below table may affect
device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this document.
This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate
logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor
associated with the pin is enabled.
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
–0.3
5.8
V
IDD
Maximum current into VDD
—
120
mA
Table continues on the next page...
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
6
Freescale Semiconductor, Inc.
General
Unit
Symbol
Description
Min.
Max.
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
VDD + 0.3
V
V
Analog1, RESET, EXTAL, and XTAL input voltage
VAIO
ID
–0.3
–25
VDD + 0.3
25
Instantaneous maximum current single pin limit (applies to all
port pins)
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 Nonswitching electrical specifications
5.1.1 DC characteristics
This section includes information about power supply requirements and I/O pin
characteristics.
Table 2. DC characteristics
Typical1
Symbol
—
C
—
P
Descriptions
Operating voltage
Output high All I/O pins, low-drive 5 V, Iload
Min
2.7
Max
5.5
—
Unit
V
—
—
—
VOH
=
=
=
=
VDD - 1.5
V
voltage
strength
-2 mA
C
P
C
D
3 V, Iload
-0.6 mA
VDD - 0.8
VDD - 1.5
VDD - 0.8
—
—
—
—
—
—
V
V
High current drive
pins, high-drive
strength2
5 V, Iload
-20 mA
3 V, Iload
-6 mA
V
IOHT
Output high
current
Max total IOH for all
ports
5 V
3 V
—
—
—
—
—
—
-100
-60
mA
VOL
P
C
P
C
Output low All I/O pins, low-drive 5 V, Iload
=
=
1.5
V
V
V
V
voltage
strength
2 mA
3 V, Iload
0.6 mA
—
—
—
—
—
—
0.8
1.5
0.8
High current drive
pins, high-drive
strength2
5 V, Iload
=20 mA
3 V, Iload
6 mA
=
Table continues on the next page...
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
7
Nonswitching electrical specifications
Table 2. DC characteristics (continued)
Typical1
Symbol
C
Descriptions
Min
Max
Unit
IOLT
D
Output low
current
Max total IOL for all
ports
5 V
—
—
—
—
—
100
mA
3 V
60
VIH
VIL
P
P
Input high
voltage
All digital inputs
All digital inputs
All digital inputs
VDD>4.1V
VDD>2.7V
VDD>4.1V
VDD>2.7V
—
0.70 × VDD
0.85 × VDD
—
—
—
V
V
—
—
—
—
Input low
voltage
0.35 × VDD
0.30 × VDD
—
—
Vhys
|IIn|
C
P
Input
hysteresis
0.06 × VDD
mV
µA
Input leakage
current
All input only pins
(per pin)
VIN = VDD
or VSS
—
—
0.1
0.1
1
1
|IOZ
|
P
C
P
Hi-Z (off-
state)
leakage
current
All input/output (per
pin)
VIN = VDD
or VSS
µA
µA
kΩ
|IOZTOT
|
Total leakage All input only and I/O VIN = VDD
—
—
—
2
combined for
all inputs and
Hi-Z pins
or VSS
RPU
Pullup
resistors
All digital inputs,
when enabled (all I/O
pins other than
PTA5/IRQ/TCLK/
RESET
—
17.5
52.5
3
P
D
Pullup
resistors
PTA5/IRQ/TCLK/
RESET
—
17.5
—
52.5
kΩ
RPU
IIC
DC injection
current4, 5, 6
Single pin limit
VIN < VSS
VIN > VDD
,
-0.2
-5
—
—
0.2
5
mA
Total MCU limit,
includes sum of all
stressed pins
CIn
C
C
Input capacitance, all pins
RAM retention voltage
—
—
—
—
—
8
pF
V
VRAM
2.0
—
1. Typical values are measured at 25 °C. Characterized, not tested.
2. Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 support ultra high current output.
3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured
externally on the pin.
4. All functional non-supply pins, except for PTA5, are internally clamped to VSS and VDD
.
5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the large one.
6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than
maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is
very low (which would reduce overall power consumption).
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
8
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Table 3. LVD and POR Specification
Symbol
C
Description
Min
Typ
Max
Unit
POR re-arm voltage1
VPOR
D
1.5
1.75
2.0
V
VLVDH
C
Falling low-voltage detect threshold - high
range (LVDV = 1)2
4.2
4.3
4.4
V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
VHYSH
C
C
C
C
C
Falling low-
voltage warning
threshold - high
range
Level 1 falling (LVWV = 00)
Level 2 falling (LVWV = 01)
Level 3 falling (LVWV = 10)
Level 4 falling (LVWV = 11)
4.3
4.5
4.6
4.7
—
4.4
4.5
4.6
4.7
100
4.5
4.6
4.7
4.8
—
V
V
V
V
High range low-voltage detect/warning
hysteresis
mV
VLVDL
C
Falling low-voltage detect threshold - low range
(LVDV = 0)
2.56
2.61
2.66
V
VLVDW1L
VLVDW2L
VLVDW3L
VLVDW4L
VHYSDL
VHYSWL
VBG
C
C
C
C
C
C
P
Falling low-
voltage warning
threshold - low
range
Level 1 falling (LVWV = 00)
Level 2 falling (LVWV = 01)
Level 3 falling (LVWV = 10)
Level 4 falling (LVWV = 11)
2.62
2.72
2.82
2.92
—
2.7
2.8
2.9
3.0
40
2.78
2.88
2.98
3.08
—
V
V
V
V
Low range low-voltage detect hysteresis
Low range low-voltage warning hysteresis
Buffered bandgap output 3
mV
mV
V
—
80
—
1.14
1.16
1.18
1. Maximum is highest voltage that POR is guaranteed.
2. Rising thresholds are falling threshold + hysteresis.
3. voltage Factory trimmed at VDD = 5.0 V, Temp = 25 °C
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
9
Nonswitching electrical specifications
0.7
0.6
0.5
VDD=3V
VDD=5V
0.4
VDD-VOH(V)
0.3
0.2
0.1
0
1
2
3
4
5
6
IOH(mA)
Figure 1. Typical IOH Vs. VDD-VOH
0.8
0.7
0.6
0.5
VDD=3V
VDD=5V
VDD-VOH(V)
0.4
0.3
0.2
0.1
0
5
10
15
20
25
IOH(mA)
Figure 2. Typical IOH Vs. VDD-VOH (High current drive)
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
10
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
0.6
0.5
0.4
0.3
0.2
0.1
0
VDD=3V
VDD=5V
VOL(V)
1
2
3
4
5
6
IOL(mA)
Figure 3. Typical IOL Vs. VOL
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VDD=3V
VDD=5V
VOL(V)
5
10
15
IOL(mA)
20
25
Figure 4. Typical IOL Vs. VOL (High current drive)
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
11
Nonswitching electrical specifications
5.1.2 Supply current characteristics
This section includes information about power supply current in various operating modes.
Table 4. Supply current characteristics
Typical1
12.6
7.2
2.4
9.6
6.1
2.1
10.5
6.2
2.3
7.4
5.0
2.0
12.1
6.5
1.8
9.1
5.5
1.5
9.8
5.4
1.6
6.9
4.4
1.4
7.8
4.5
1.3
5.1
3.5
1.2
Num
C
C
C
Parameter
Symbol Bus Freq
VDD (V)
Max
—
Unit
Temp
1
Run supply current FEI
mode, all modules on;
run from flash
RIDD
RIDD
RIDD
RIDD
WIDD
20 MHz
10 MHz
1 MHz
5
mA -40 to 105 °C
mA -40 to 105 °C
mA -40 to 105 °C
mA -40 to 105 °C
mA -40 to 105 °C
—
—
C
C
20 MHz
10 MHz
1 MHz
3
5
3
5
3
5
3
5
3
—
—
—
2
3
4
5
C
C
Run supply current FEI
mode, all modules off &
gated; run from flash
20 MHz
10 MHz
1 MHz
—
—
—
C
C
20 MHz
10 MHz
1 MHz
—
—
—
P
C
Run supply current FBE
mode, all modules on;
run from RAM
20 MHz
10 MHz
1 MHz
14.8
—
—
P
C
20 MHz
10 MHz
1 MHz
11.8
—
—
P
C
Run supply current FBE
mode, all modules off &
gated; run from RAM
20 MHz
10 MHz
1 MHz
12.3
—
—
P
C
20 MHz
10 MHz
1 MHz
9.2
—
—
C
C
Wait mode current FEI
mode, all modules on
20 MHz
10 MHz
1 MHz
—
—
—
C
20 MHz
10 MHz
1 MHz
—
—
—
Table continues on the next page...
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
12
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Table 4. Supply current characteristics (continued)
Typical1
Num
C
C
C
Parameter
Symbol Bus Freq
VDD (V)
Max
—
Unit
Temp
6
Stop3 mode supply
current no clocks active
(except 1kHz LPO
clock)2, 3
S3IDD
—
—
5
3
3.8
3
µA
-40 to 105 °C
-40 to 105 °C
—
7
8
9
C
C
ADC adder to stop3
ADLPC = 1
—
—
—
—
5
3
44
40
—
—
µA
µA
µA
-40 to 105 °C
-40 to 105 °C
-40 to 105 °C
ADLSMP = 1
ADCO = 1
MODE = 10B
ADICLK = 11B
TSI adder to stop34
PS = 010B
C
C
—
5
3
111
110
—
—
NSCN =0x0F
EXTCHRG = 0
REFCHRG = 0
DVOLT = 01B
LVD adder to stop35
C
C
—
5
3
130
125
—
—
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. RTC adder cause <1uA IDD increase typically, RTC clock source is 1kHz LPO clock.
3. ACMP adder cause <1uA IDD increase typically.
4. The current varies with TSI configuration and capacity of touch electrode. Please refer to TSI electrical specifications.
5. LVD is periodically woken up from stop3 by 5% duty cycle. The period is equal to or less than 2 ms.
5.1.3 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependant on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should
consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and
AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
13
Switching specifications
5.2 Switching specifications
5.2.1 Control timing
Table 5. Control timing
Typical1
Num
C
P
P
D
Rating
Symbol
fBus
Min
DC
Max
20
Unit
MHz
KHz
ns
1
2
3
Bus frequency (tcyc = 1/fBus
)
—
Internal low power oscillator frequency
External reset pulse width2
fLPO
0.67
1.0
—
1.25
—
textrst
1.5 ×
tSelf_reset
4
5
D
D
Reset low drive
trstdrv
34 × tcyc
500
—
—
—
—
ns
ns
BKGD/MS setup time after issuing background
debug force reset to enter user or BDM modes
tMSSU
6
7
D
D
BKGD/MS hold time after issuing background
debug force reset to enter user or BDM modes3
tMSH
100
100
—
—
—
—
ns
ns
IRQ pulse width
Asynchronous
path2
tILIH
Synchronous path4
D
D
tIHIL
tILIH
1.5 × tcyc
100
—
—
—
—
ns
ns
8
9
Keyboard interrupt pulse
width
Asynchronous
path2
D
C
C
Synchronous path
—
tIHIL
tRise
tFall
1.5 × tcyc
—
10.2
9.5
—
—
—
ns
ns
ns
Port rise and fall time -
Normal drive strength
(HDRVE_PTXx = 0) (load
= 50 pF)5
—
—
C
C
Port rise and fall time -
Extreme high drive
strength (HDRVE_PTXx =
1) (load = 50 pF)5
—
tRise
tFall
—
—
5.4
4.6
—
—
ns
ns
1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of tMSH after
VDD rises above VLVD
.
4. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C.
textrst
RESET PIN
Figure 5. Reset timing
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
14
Freescale Semiconductor, Inc.
Switching specifications
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 6. IRQ/KBIPx timing
5.2.2 Debug trace timing specifications
Table 6. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
tcyc
Clock period
Frequency dependent
MHz
twl
twh
tr
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
ns
ns
ns
ns
ns
ns
—
—
3
tf
3
ts
—
—
th
Data hold
2
Figure 7. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 8. Trace data specifications
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
15
Switching specifications
5.2.3 FTM module timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the
fastest clock that can be used as the optional external source to the timer counter. These
synchronizers operate from the current bus rate clock.
Table 7. FTM input timing
No.
C
Function
Symbol
Min
Max
Unit
1
D
External clock
frequency
fTCLK
0
fBus/4
Hz
2
3
4
5
D
D
D
D
External clock
period
tTCLK
4
—
—
—
—
tcyc
tcyc
tcyc
tcyc
External clock
high time
tclkh
1.5
1.5
1.5
External clock
low time
tclkl
Input capture
pulse width
tICPW
tTCLK
tclkh
TCLK
tclkl
Figure 9. Timer external clock
tICPW
FTMCHn
FTMCHn
tICPW
Figure 10. Timer input capture pulse
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
16
Freescale Semiconductor, Inc.
Thermal specifications
5.3 Thermal specifications
5.3.1 Thermal characteristics
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-
determined rather than being controlled by the MCU design. To take PI/O into account in
power calculations, determine the difference between actual pin voltage and VSS or VDD
and multiply by the pin current for each I/O pin. Except in cases of unusually high pin
current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
Table 8. Thermal characteristics
Rating
Symbol
Value
Unit
Operating temperature range
(packaged)
TA
-40 to 105
°C
Junction temperature range
TJ
-40 to 150
°C
Thermal resistance single-layer board
64-pin LQFP
64-pin QFP
48-pin LQFP
44-pin LQFP
32-pin LQFP
θJA
θJA
θJA
θJA
θJA
71
61
81
75
86
°C/W
°C/W
°C/W
°C/W
°C/W
Thermal resistance four-layer board
64-pin LQFP
64-pin QFP
48-pin LQFP
44-pin LQFP
32-pin LQFP
θJA
θJA
θJA
θJA
θJA
53
47
57
53
57
°C/W
°C/W
°C/W
°C/W
°C/W
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Where:
TA = Ambient temperature, °C
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
17
Peripheral operating requirements and behaviors
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts - chip internal power
PI/O = Power dissipation on input and output pins - user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship
between PD and TJ (if PI/O is neglected) is:
PD = K ÷ (TJ + 273 °C)
Solving the equations above for K gives:
K = PD × (TA + 273 °C) + θJA × (PD)2
where K is a constant pertaining to the particular part. K can be determined by measuring
PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can
be obtained by solving the above equations iteratively for any value of TA.
6 Peripheral operating requirements and behaviors
6.1 External oscillator (XOSC) and ICS characteristics
Table 9. XOSC and ICS specifications (temperature range = -40 to 105 °C ambient)
Typical1
Num
C
C
C
Characteristic
Low range (RANGE = 0)
Symbol
Min
32
4
Max
40
Unit
kHz
1
Oscillator
crystal or
resonator
flo
fhi
—
High range (RANGE = 1)
FEE or FBE mode2
—
20
MHz
C
C
D
High range (RANGE = 1),
high gain (HGO = 1),
FBELP mode
fhi
4
4
—
20
20
MHz
MHz
High range (RANGE = 1),
low power (HGO = 0),
FBELP mode
fhi
—
See Note3
2
Load capacitors
C1, C2
Table continues on the next page...
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
18
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 9. XOSC and ICS specifications (temperature range = -40 to 105 °C ambient)
(continued)
Typical1
Num
C
Characteristic
Symbol
Min
Max
Unit
3
D
Feedback
resistor
Low Frequency, Low-
RF
—
—
—
MΩ
Power Mode4
Low Frequency, High-Gain
Mode
—
—
—
10
1
—
—
—
MΩ
MΩ
MΩ
High Frequency, Low-
Power Mode
High Frequency, High-Gain
Mode
1
Low-Power Mode 4
High-Gain Mode
Low-Power Mode4
4
5
D
D
Series resistor -
Low Frequency
RS
RS
—
—
—
—
200
—
—
—
—
kΩ
kΩ
kΩ
Series resistor -
High Frequency
D
D
D
D
D
C
C
C
C
Series resistor -
High
Frequency,
High-Gain
Mode
1 MHz
2 MHz
—
—
—
—
—
—
—
—
—
6.6
3.3
0
—
—
—
—
—
—
—
—
—
kΩ
kΩ
kΩ
kΩ
kΩ
ms
ms
ms
ms
4 MHz
8 MHz
0
16 MHz
0
6
Crystal start-up
time Low range
= 32.768 KHz
crystal; High
range = 20
MHz crystal5, 6
Low range, low power
Low range, high power
High range, low power
High range, high power
tCSTL
1000
800
3
tCSTH
1.5
7
8
T
D
D
Internal reference start-up time
tIRST
fextal
—
0.03125
0
20
—
—
50
5
µs
FEE or FBE mode2
FBELP mode
Square wave
input clock
frequency
MHz
MHz
20
9
P
Average internal reference frequency -
trimmed
fint_t
—
32.768
—
kHz
10
11
P
P
DCO output frequency range - trimmed
fdco_t
16
—
—
—
20
MHz
Total deviation
of DCO output
from trimmed
frequency5
Over full voltage and
temperature range
Δfdco_t
2.0
%fdco
C
Over fixed voltage and
temperature range of 0 to
70 °C
1.0
FLL acquisition time5, 7
12
13
C
C
tAcquire
CJitter
—
—
—
2
ms
Long term jitter of DCO output clock
(averaged over 2 ms interval)8
0.02
0.2
%fdco
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25
kHz to 39.0625 kHz.
3. See crystal or resonator manufacturer's recommendation.
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
19
Peripheral operating requirements and behaviors
4. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =
0.
5. This parameter is characterized and not tested on each device.
6. Proper PC board layout procedures must be followed to achieve specifications.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed,
DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
XOSC
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 11. Typical crystal or resonator circuit
6.2 NVM specifications
This section provides details about program/erase times and program-erase endurance for
the flash and EEPROM memories.
Table 10. Flash characteristics
Min1
Typical2
Max3
Unit4
C
Characteristic
Symbol
D
Supply voltage for program/erase -40
°C to 105 °C
Vprog/erase
2.7
—
5.5
V
D
D
D
D
D
D
D
D
Supply voltage for read operation
NVM Bus frequency
VRead
fNVMBUS
fNVMOP
tVFYALL
tRD1BLK
tRD1BLK
tRD1SEC
tDRD1SEC
2.7
1
—
—
5.5
25
V
MHz
MHz
tcyc
NVM Operating frequency
Erase Verify All Blocks
0.8
—
—
1.05
17030
16977
843
—
Erase Verify Flash Block
Erase Verify EEPROM Block
Erase Verify Flash Section
Erase Verify EEPROM Section
—
—
tcyc
—
—
tcyc
—
—
517
tcyc
0.10
0.10
0.11
ms
Table continues on the next page...
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
20
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 10. Flash characteristics (continued)
Min1
Typical2
Max3
Unit4
C
D
D
D
D
D
D
D
D
D
D
D
D
D
C
Characteristic
Read Once
Symbol
tRDONCE
tPGM2
—
—
455
tcyc
Program Flash (2 word)
Program Flash (4 word)
Program Once
0.12
0.20
0.20
0.02
0.17
96.01
95.98
19.10
4.81
96.01
—
0.12
0.21
0.14
0.24
ms
ms
tPGM4
tPGMONCE
tDPGM1
tDPGM2
tERSALL
tERSBLK
tERSPG
tDERSPG
tUNSECU
tVFYKEY
tMLOADU
nFLPE
0.21
0.24
ms
Program EEPROM (1 Byte)
Program EEPROM (2 Byte)
Erase All Blocks
0.02
0.02
ms
0.18
0.20
ms
100.78
100.75
20.05
5.05
125.80
125.76
25.05
6.30
ms
Erase Flash Block
ms
Erase Flash Sector
Erase EEPROM Sector
Unsecure Flash
ms
ms
100.78
—
125.80
469
ms
Verify Backdoor Access Key
Set User Margin Level
tcyc
tcyc
Cycles
—
—
442
FLASH Program/erase endurance TL to
TH = -40 °C to 105 °C
10 k
100 k
—
C
C
EEPROM Program/erase endurance TL
to TH = -40 °C to 105 °C
nFLPE
50 k
15
500 k
100
—
—
Cycles
years
Data retention at an average junction
temperature of TJavg = 85°C after up to
10,000 program/erase cycles
tD_ret
1. Minimun times are based on maxmum fNVMOP and maximum fNVMBUS
2. Typical times are based on typical fNVMOP and maximum fNVMBUS
3. Maximum times are based on minimum fNVMOP and maximum fNVMBUS
4. tcyc = 1 / fNVMBUS
Program and erase operations do not require any special power sources other than the
normal VDD supply. For more detailed information about program/erase operations, see
the Memory section.
6.3 Analog
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
6.3.1 ADC characteristics
Table 11. 5 V 12-bit ADC operating conditions
Typ1
Characteristic
Conditions
Symb
VDDA
Min
2.7
Max
5.5
Unit
V
Comment
Supply voltage
Absolute
—
—
ΔVDDA
-100
0
0
+100
mV
Delta to VDD (VDD-VDDAD
)
3
Ground voltage
Input voltage
ΔVSSA
VADIN
CADIN
-100
VREFL
—
+100
VREFH
5.5
mV
V
Delta to VSS (VSS-VSSA
)
—
4.5
—
—
Input
pF
capacitance
Input resistance
RADIN
RAS
—
3
5
kΩ
—
Analog source
resistance
12-bit mode
kΩ External to MCU
fADCK > 4 MHz
fADCK < 4 MHz
—
—
—
—
2
5
10-bit mode
fADCK > 4MHz
fADCK < 4MHz
—
—
—
—
—
—
5
10
10
8-bit mode
(all valid fADCK
)
ADC conversion High Speed (ADLPC=0)
fADCK
0.4
0.4
—
—
8.0
4.0
MHz
—
clock frequency
Low Power (ADLPC=1)
1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
zADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
Z
AS
leakage
due to
input
ADC SAR
ENGINE
R AS
R ADIN
protection
vADIN
C AS
vAS
R ADIN
R ADIN
R ADIN
INPUT PIN
INPUT PIN
INPUT PIN
C ADIN
Figure 12. ADC input impedance equivalency diagram
Table 12. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA
)
Typ1
Characteristic
Supply current
ADLPC = 1
Conditions
C
Symb
Min
Max
Unit
Comment
T
IDDA
—
133
—
µA
—
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 1
T
T
T
T
IDDA
—
—
—
—
218
327
—
—
µA
µA
µA
µA
—
—
—
ADLSMP = 0
ADCO = 1
Supply current
ADLPC = 0
IDDA
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 0
IDDAD
582
990
ADLSMP = 0
ADCO = 1
Supply current
Stop, reset,
module off
IDDA
0.011
1
Table continues on the next page...
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
Table 12. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Typ1
Characteristic
Conditions
C
Symb
Min
Max
Unit
Comment
tADACK
1/fADACK
ADC
asynchronous
clock source
High speed
(ADLPC = 0)
P
fADACK
2
3.3
5
MHz
=
Low power
(ADLPC = 1)
1.25
—
2
20
3.3
—
—
—
—
Conversion time Short sample
(including sample (ADLSMP = 0)
time)
T
T
tADC
ADCK
cycles
—
Long sample
(ADLSMP = 1)
—
40
Sample time
Short sample
(ADLSMP = 0)
tADS
—
3.5
23.5
ADCK
cycles
Long sample
—
(ADLSMP = 1)
LSB2
LSB2
Total unadjusted 12-bit mode
T
P
P
T
P
P
T
T
T
C
P
P
T
T
T
D
ETUE
DNL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.0
1.5
—
Includes
quantization
Error
10-bit mode
2.0
1.0
—
8-bit mode
0.7
Differential Non- 12-bit mode
1.0
—
—
Liniarity
10-bit mode3
0.25
0.15
1.0
0.5
0.25
—
8-bit mode3
LSB2
LSB2
LSB2
Integral Non-
Linearity
12-bit mode
10-bit mode
8-bit mode
INL
EZS
EFS
0.3
0.5
0.25
—
0.15
2.0
Zero-scale error 12-bit mode
10-bit mode
VADIN
=
=
0.25
0.65
2.5
1.0
1.0
—
VSSA
8-bit mode
Full-scale error
12-bit mode
10-bit mode
8-bit mode
VADIN
0.5
1.0
1.0
0.5
VDDA
0.5
LSB2
mV
Quantization
error
≤12 bit modes
EQ
EIL
—
—
Input leakage
error
all modes
D
IIn * RAS
IIn = leakage
current (refer to
DC
characteristics)
Temp sensor
slope
-40°C– 25°C
25°C– 125°C
25°C
D
D
m
—
—
—
3.266
3.638
1.396
—
—
—
mV/°C
V
Temp sensor
voltage
VTEMP25
1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
1 LSB = (VREFH - VREFL)/2N
2.
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes
6.3.2 Analog comparator (ACMP) electricals
Table 13. Comparator electrical specifications
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
Supply voltage
VDDA
2.7
—
5.5
V
T
D
P
C
C
T
Supply current (Operation mode)
Analog input voltage
IDDA
VAIN
VAIO
VH
—
10
—
20
VDDA
40
µA
V
VSS - 0.3
Analog input offset voltage
—
—
—
—
—
—
mV
mV
mV
nA
µs
Analog comparator hysteresis (HYST=0)
Analog comparator hysteresis (HYST=1)
Supply current (Off mode)
15
20
60
0.4
20
VH
30
IDDAOFF
tD
—
C
Propagation Delay
1
6.4 Communication interfaces
6.4.1 SPI switching specifications
The serial peripheral interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of
the chip's reference manual for information about the modified transfer formats used for
communicating with slower peripheral devices. All timing is shown with respect to 20%
VDD and 70% VDD, unless noted, and 100 pF load on all SPI pins. All timing assumes
slew rate control is disabled and high drive strength is enabled for SPI output pins.
Table 14. SPI master mode timing
Nu
m.
Symbol Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
fBus/2048
fBus/2
Hz
fBus is the bus
clock
2
3
4
5
tSPSCK
tLead
SPSCK period
2 x tBus
1/2
2048 x tBus
ns
tBus = 1/fBus
Enable lead time
—
—
tSPSCK
tSPSCK
ns
—
—
—
tLag
Enable lag time
1/2
tWSPSCK
Clock (SPSCK) high or low time
tBus - 30
1024 x tBus
Table continues on the next page...
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
Table 14. SPI master mode timing (continued)
Nu
m.
Symbol Description
Min.
Max.
Unit
Comment
6
7
tSU
tHI
Data setup time (inputs)
15
0
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
8
tv
—
0
25
9
tHO
tRI
—
10
—
tBus - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
5
=
(CPOL 0)
(OUTPUT)
5
SPSCK
(CPOL 1)
=
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
LSB OUT
MSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 13. SPI master mode timing (CPHA=0)
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL 0)
=
(OUTPUT)
5
5
SPSCK
(CPOL 1)
=
(OUTPUT)
6
7
MISO
(INPUT)
2
MSB IN
BIT 6 . . . 1
LSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
MASTER MSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI master mode timing (CPHA=1)
Table 15. SPI slave mode timing
Nu
m.
Symbol
Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
0
fBus/4
Hz
fBus is the bus clock as
defined in .
2
3
4
5
6
7
8
tSPSCK
tLead
tLag
SPSCK period
4 x tBus
—
—
ns
tBus
tBus
ns
tBus = 1/fBus
Enable lead time
1
1
—
—
—
—
—
Enable lag time
—
tWSPSCK
tSU
Clock (SPSCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Slave access time
tBus - 30
15
—
—
ns
tHI
25
—
ns
ta
—
tBus
ns
Time to data active from
high-impedance state
9
tdis
Slave MISO disable time
—
tBus
ns
Hold time to high-
impedance state
10
11
12
tv
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
—
0
25
—
ns
ns
ns
—
—
—
tHO
tRI
—
tBus - 25
tFI
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL 0)
=
(INPUT)
5
5
3
SPSCK
=
(CPOL 1)
(INPUT)
9
8
10
11
11
MISO
(OUTPUT)
see
SEE
BIT 6 . . . 1
SLAVE LSB OUT
SLAVE MSB
7
note
NOTE
6
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE: Not defined!
Figure 15. SPI slave mode timing (CPHA = 0)
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
=
(CPOL 0)
(INPUT)
5
5
SPSCK
=
(CPOL 1)
(INPUT)
11
9
10
SLAVE MSB OUT
MISO
(OUTPUT)
see
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
note
8
6
7
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE: Not defined!
Figure 16. SPI slave mode timing (CPHA=1)
6.5 Human-machine interfaces (HMI)
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
28
Freescale Semiconductor, Inc.
Dimensions
6.5.1 TSI electrical specifications
Table 16. TSI electrical specifications
Symbol
TSI_RUNF
TSI_RUNV
Description
Min.
—
Type
100
—
Max
—
Unit
µA
Fixed power consumption in run mode
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
128
µA
TSI_EN
TSI_DIS
Power consumption in enable mode
Power consumption in disable mode
TSI analog enable time
—
—
100
1.2
66
—
—
µA
µA
µs
pF
V
TSI_TEN
—
—
TSI_CREF
TSI_DVOLT
TSI reference capacitor
—
1.0
—
—
Voltage variation of VP & VM around nominal
values
0.19
1.03
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
32-pin LQFP
Then use this document number
98ASH70029A
44-pin LQFP
98ASS23225W
48-pin LQFP
98ASH00962A
64-pin QFP
98ASB42844B
64-pin LQFP
98ASS23234W
8 Pinout
8.1 Signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
29
Pinout
Table 17. Pin availability by package pin-count
Pin Number
Lowest Priority <-- --> Highest
64-LQFP
64-QFP
1
48-LQFP 44-LQFP 32-LQFP
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
PTD11
PTD01
PTH7
PTH6
PTE7
PTH2
—
1
1
1
2
KBI1P1
FTM2CH3
FTM2CH2
—
MOSI1
SPSCK1
—
—
—
2
2
2
KBI1P0
3
—
—
3
—
—
3
—
—
—
—
3
—
—
4
—
—
—
—
5
—
TCLK2
BUSOUT
—
—
—
6
4
4
—
—
—
7
5
5
—
—
VDD
VREFH
VREFL
VSS
EXTAL
XTAL
VSS
—
8
6
6
4
—
—
—
VDDA
VSSA
—
9
7
7
5
—
—
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
8
8
6
—
—
—
9
9
7
PTB7
PTB6
—
—
—
SCL
—
10
11
—
—
12
13
14
15
16
17
18
19
20
21
22
—
—
—
—
23
24
10
11
—
—
—
—
12
13
14
15
16
17
18
19
20
—
—
—
—
21
22
8
SDA
—
—
—
—
—
—
—
9
—
—
PTH11
PTH01
PTE6
PTE5
PTB51
PTB41
PTC3
PTC2
PTD7
PTD6
PTD5
PTC1
PTC0
PTF7
PTF6
PTF5
PTF4
PTB3
PTB2
—
FTM2CH1
FTM2CH0
—
—
—
—
—
—
—
—
—
—
—
—
FTM2CH5
FTM2CH4
FTM2CH3
FTM2CH2
KBI1P7
KBI1P6
KBI1P5
—
SS0
—
—
10
11
12
—
—
—
13
14
—
—
—
—
15
16
MISO0
—
—
—
ADP11
ADP10
—
—
—
—
TXD2
RXD2
—
—
—
—
—
—
FTM2CH1
FTM2CH0
—
ADP9
ADP8
ADP15
ADP14
ADP13
ADP12
ADP7
ADP6
TSI7
TSI6
—
—
—
—
—
—
—
—
—
—
—
—
KBI0P7
KBI0P6
MOSI0
SPSCK0
TSI5
TSI4
Table continues on the next page...
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
30
Freescale Semiconductor, Inc.
Pinout
Table 17. Pin availability by package pin-count (continued)
Pin Number
Lowest Priority <-- --> Highest
64-LQFP
48-LQFP 44-LQFP 32-LQFP
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
64-QFP
33
25
26
—
—
27
28
29
30
31
—
—
32
33
34
35
36
37
38
39
40
41
42
—
—
—
—
43
44
45
46
47
48
23
24
—
—
25
26
—
27
28
—
—
29
30
31
32
33
34
35
36
37
—
38
—
—
—
—
39
40
41
42
43
44
17
18
—
—
19
20
—
—
—
—
—
—
21
22
23
24
25
26
27
28
—
—
—
—
—
—
—
—
29
30
31
32
PTB1
PTB0
PTF3
PTF2
PTA7
PTA6
PTE4
—
KBI0P5
TXD0
RXD0
—
ADP5
ADP4
—
TSI3
TSI2
TSI15
TSI14
TSI1
TSI0
—
34
KBI0P4
35
—
36
—
—
—
37
FTM2FAULT2
—
ADP3
ADP2
—
38
FTM2FAULT1
—
39
—
—
—
40
—
—
VSS
VDD
TSI13
TSI12
—
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
—
—
—
—
PTF1
PTF0
PTD4
PTD3
PTD2
PTA32
PTA22
PTA1
PTA0
PTC7
PTC6
PTE3
PTE2
PTG3
PTG2
PTG1
PTG0
PTE11
PTE01
PTC5
PTC4
PTA5
PTA4
—
—
—
—
—
—
KBI1P4
KBI1P3
KBI1P2
KBI0P3
KBI0P2
KBI0P1
KBI0P0
—
—
—
SS1
—
TSI11
TSI10
—
MISO1
TXD0
RXD0
FTM0CH1
FTM0CH0
TxD1
RxD1
SS0
—
SCL
SDA
ACMP1
ACMP0
—
—
ADP1
ADP0
TSI9
TSI8
—
—
—
—
—
—
MISO0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MOSI0
SPSCK0
FTM1CH1
FTM1CH0
TCLK0
ACMPO
—
—
—
TCLK1
—
—
—
—
—
RTCO
—
—
IRQ
—
RESET
MS
BKGD
1. This is a high current drive pin when operated as output.
2. This is a true open-drain pin when operated as output.
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
31
Pinout
Note
When an alternative function is first enabled, it is possible to
get a spurious edge to the module. User software must clear any
associated flags before interrupts are enabled. The table above
illustrates the priority if multiple modules are enabled. The
highest priority module will have control over the pin. Selecting
a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority
module. Disable all modules that share a pin before enabling
another module.
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
32
Freescale Semiconductor, Inc.
Pinout
8.2 Device pin assignment
2
1
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTA2/KBI0P2/RxD0/SDA
PTD1/KBI1P1/FTM2CH3/MOSI1
PTD0/KBI1P0/FTM2CH2/SPSCK1
1
2
PTA3/KBI0P3/TxD0/SCL
PTH7
PTH6
3
PTD2/KBI1P2/MISO1/TSI10
PTD3/KBI1P3/SS1/TSI11
PTD4/KBI1P4
4
PTE7/TCLK2
PTH2/BUSOUT
5
6
PTF0/TSI12
V
7
PTF1/TSI13
DD
8
V
DD
V
DDA /V
REFH
9
V
SS
V
SSA /V
REFL
V
10
11
12
13
14
15
16
PTE4
SS
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTA6/FTM2FAULT1/ADP2/TSI0
PTA7/FTM2FAULT2/ADP3/TSI1
PTF2/TSI14
V
SS
1
PTF3/TSI15
PTH1/FTM2CH1
1
PTB0/KBI0P4/RxD0/ADP4/TSI2
PTB1/KBI0P5/TxD0/ADP5/TSI3
PTH0/FTM2CH0
PTE6
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
Figure 17. MC9S08PT60 64-pin QFP and LQFP package
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
33
Pinout
1
1
2
1
2
36
35
PTD1/KBI1P1/FTM2CH3/MOSI1
PTD0/KBI1P0/FTM2CH2/SPSCK1
PTA2/KBI0P2/RxD0/SDA
2
PTA3/KBI0P3/TxD0/SCL
3
PTE7/TCLK2
34 PTD2/KBI1P2/MISO1/TSI10
33
PTD3/KBI1P3/SS1/TSI11
32 PTD4/KBI1P4
4
PTH2/BUSOUT
5
V
DD
REFH
SSA /V
6
31
30
V
DD
V
SS
V
DDA /V
7
V
REFL
8
29 PTE4
V
SS
9
28 PTA6/FTM2FAULT1/ADP2/TSI0
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
10
11
12
PTA7/FTM2FAULT2/ADP3/TSI1
27
V
26 PTB0/KBI0P4/RxD0/ADP4/TSI2
25 PTB1/KBI0P5/TxD0/ADP5/TSI3
SS
PTE6
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
Figure 18. MC9S08PT60 48-pin LQFP package
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
34
Freescale Semiconductor, Inc.
Pinout
2
1
1
33
32
31
30
29
28
27
26
25
24
23
1
2
PTA2/KBI0P2/RxD0/SDA
PTD1/KBI1P1/FTM2CH3/MOSI1
PTD0/KBI1P0/FTM2CH2/SPSCK1
PTA3/KBI0P3/TxD0/SCL2
PTD2/KBI1P2/MISO1/TSI10
PTD3/KBI1P3/SS1/TSI11
PTD4/KBI1P4
3
PTE7/TCLK2
4
PTH2/BUSOUT
5
V
DD
REFH
SSA /V
6
V
V
V
DDA /V
DD
7
V
SS
REFL
8
PTA6/FTM2FAULT1/ADP2/TSI0
PTA7/FTM2FAULT2/ADP3/TSI1
PTB0/KBI0P4/RxD0/ADP4/TSI2
PTB1/KBI0P5/TxD0/ADP5/TSI3
V
SS
9
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
10
11
V
SS
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
Figure 19. MC9S08PT60 44-pin LQFP package
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
35
Revision history
1
1
2
PTD1/KBI1P1/FTM2CH3/MOSI1
PTD0/KBI1P0/FTM2CH2/SPSCK1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PTA2/KBI0P2/RxD0/SDA
PTA3/KBI0P3/TxD0/SCL2
V
PTD2/KBI1P2/MISO1/TSI10
PTD3/KBI1P3/SS1/TSI11
DD
V
DDA /V
REFH
PTA6/FTM2FAULT1/ADP2/TSI0
PTA7/FTM2FAULT2/ADP3/TSI1
PTB0/KBI0P4/RxD0/ADP4/TSI2
PTB1/KBI0P5/TxD0/ADP5/TSI3
V
SSA /V
REFL
V
SS
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
1. High source/sink current pins
2. True open drain pins
Figure 20. MC9S08PT60 32-pin LQFP package
9 Revision history
The following table provides a revision history for this document.
Table 18. Revision history
Rev. No.
Date
Substantial Changes
1
2
10/2011
11/2011
Initial public revision.
• Updated some TBDs
• Updated LVD and POR data
• Updated ADC data
• Updated SPI data
• Updated TSI data.
3
4/2012
• Finished all the TBDs
• Updated package information
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
36
Freescale Semiconductor, Inc.
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