935318733528_技术文档

NXP Semiconductors

Data Sheet: Technical Data

Document Number: MPC5607B

Rev. 9, 11/2017

MPC5607B

MPC5607B Microcontroller

Data Sheet

144 LQFP (20 mm x 20 mm)

208 MAPBGA (17 mm x 17 mm)

100 LQFP (14 mm x 14mm)

LQFP176 (24 mm x 24 mm)

Features

•

Up to 10 serial communication interface (LINFlex)

modules

Up to 6 enhanced full CAN (FlexCAN) modules with

configurable buffers

•

Single issue, 32-bit CPU core complex (e200z0h)

—

Compliant with the Power Architecture^®technology

embedded category

1 inter-integrated circuit (I²C) interface module

Up to 149 configurable general purpose pins supporting

input and output operations (package dependent)

Real-Time Counter (RTC)

Clock source from internal 128 kHz or 16 MHz oscillator

supporting autonomous wakeup with 1 ms resolution with

maximum timeout of 2 seconds

Optional support for RTC with clock source from external

32 kHz crystal oscillator, supporting wakeup with 1 sec

resolution and maximum timeout of 1 hour

Up to 8 periodic interrupt timers (PIT) with 32-bit counter

resolution

Nexus development interface (NDI) per IEEE-ISTO

5001-2003 Class Two Plus

Device/board boundary scan testing supported per Joint

Test Action Group (JTAG) of IEEE (IEEE 1149.1)

On-chip voltage regulator (VREG) for regulation of

input supply for all internal levels

—

Enhanced instruction set allowing variable length

encoding (VLE) for code size footprint reduction.

With the optional encoding of mixed 16-bit and

32-bit instructions, it is possible to achieve

significant code size footprint reduction.

•

Up to 1.5 MB on-chip code flash memory supported with

the flash memory controller

64 (4 × 16) KB on-chip data flash memory with ECC

Up to 96 KB on-chip SRAM

Memory protection unit (MPU) with 8 region descriptors

and 32-byte region granularity on certain family members

(Refer to Table 1 for details.)

Interrupt controller (INTC) capable of handling 204

selectable-priority interrupt sources

Frequency modulated phase-locked loop (FMPLL)

Crossbar switch architecture for concurrent access to

peripherals, Flash, or RAM from multiple bus masters

16-channel eDMA controller with multiple transfer

request sources using DMA multiplexer

•

Boot assist module (BAM) supports internal Flash

programming via a serial link (CAN or SCI)

Timer supports I/O channels providing a range of 16-bit

input capture, output compare, and pulse width

modulation functions (eMIOS)

•

2 analog-to-digital converters (ADC): one 10-bit and one

12-bit

Cross Trigger Unit to enable synchronization of ADC

conversions with a timer event from the eMIOS or PIT

Up to 6 serial peripheral interface (DSPI) modules

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Table of Contents

1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

4.9.1 Program/erase characteristics . . . . . . . . . . . . . 63

4.9.2 Flash power supply DC characteristics . . . . . . 64

4.9.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 65

4.10 Electromagnetic compatibility (EMC) characteristics. . 65

4.10.1 Designing hardened software to avoid noise

problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .8

3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2

3

3.2

. . . . . . . . . . . . Pad configuration during reset phases11

3.3 Pad configuration during standby mode exit . . . . . . . . .12

3.4 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.5 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.6 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.7 Functional port pins . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.8 Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .35

4.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

4.2.1 NVUSRO[PAD3V5V] field description . . . . . . . .35

4.2.2 NVUSRO[OSCILLATOR_MARGIN] field description

36

4.2.3 NVUSRO[WATCHDOG_EN] field description . .36

4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .36

4.4 Recommended operating conditions . . . . . . . . . . . . . .37

4.5 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .40

4.5.1 External ballast resistor recommendations . . . .40

4.5.2 Package thermal characteristics . . . . . . . . . . . .40

4.5.3 Power considerations. . . . . . . . . . . . . . . . . . . . .41

4.6 I/O pad electrical characteristics. . . . . . . . . . . . . . . . . .42

4.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .42

4.6.2 I/O input DC characteristics. . . . . . . . . . . . . . . .42

4.6.3 I/O output DC characteristics. . . . . . . . . . . . . . .43

4.6.4 Output pin transition times. . . . . . . . . . . . . . . . .46

4.6.5 I/O pad current specification . . . . . . . . . . . . . . .47

4.6.6 RESET electrical characteristics . . . . . . . . . . . .54

4.7 Power management electrical characteristics. . . . . . . .57

4.7.1 Voltage regulator electrical characteristics . . . .57

4.7.2 Low voltage detector electrical characteristics .59

4.8 Power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . .61

4.9 Flash memory electrical characteristics . . . . . . . . . . . .63

4.10.2 Electromagnetic interference (EMI) . . . . . . . . . 66

4.10.3 Absolute maximum ratings (electrical sensitivity)66

4.11 Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.12 Slow external crystal oscillator (32 kHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.13 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 72

4.14 Fast internal RC oscillator (16 MHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.15 Slow internal RC oscillator (128 kHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.16 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 75

4.16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.16.2 Input impedance and ADC accuracy . . . . . . . . 76

4.16.3 ADC electrical characteristics . . . . . . . . . . . . . 81

4.17 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.17.1 Current consumption . . . . . . . . . . . . . . . . . . . . 86

4.17.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 88

4.17.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . 94

4.17.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 95

Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 97

5.1.1 176 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.1.2 144 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.1.3 100 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.1.4 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . 105

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4

5

6

7

MPC5607B Microcontroller Data Sheet, Rev. 9

2

NXP Semiconductors

Introduction

1

Introduction

This document describes the features of the family and options available within the family members, and highlights important

electrical and physical characteristics of the device.

1.1

Description

This family of 32-bit system-on-chip (SoC) microcontrollers is the latest achievement in integrated automotive application

controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body

electronics applications within the vehicle.

The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the

Power Architecture technology and only implements the VLE (variable-length encoding) APU (Auxiliary Processor Unit),

providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for

low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and

is supported with software drivers, operating systems and configuration code to assist with users implementations.

1

Table 1. MPC5607B family comparison

Feature

MPC5605B

MPC5606B

e200z0h

Up to 64 MHz

1 MB

^{64 (4}× 16) KB

80 KB

MPC5607B

CPU

Execution speed²

Code flash memory

Data flash memory

SRAM

768 KB

64 KB

1.5 MB

96 KB

MPU

8-entry

16 ch

Yes

eDMA

10-bit ADC

dedicated³

shared with 12-bit ADC

12-bit ADC

7 ch

15 ch

29 ch

15 ch

19 ch

Yes

29 ch

dedicated⁴

shared with 10-bit ADC

Total timer I/O⁵eMIOS

5 ch

19 ch

37 ch,

16-bit

64 ch, 16-bit

Counter / OPWM / ICOC⁶

10 ch

7 ch

O(I)PWM / OPWFMB /

OPWMCB / ICOC⁷

O(I)PWM / ICOC⁸

OPWM / ICOC⁹

SCI (LINFlex)

SPI (DSPI)

7 ch

13 ch

4

14 ch

33 ch

8

10

3

5

6

5

6

1

6

CAN (FlexCAN)

I²C

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

3

Block diagram

1

Table 1. MPC5607B family comparison (continued)

Feature

MPC5605B

MPC5606B

Yes

MPC5607B

32 KHz oscillator

GPIO¹⁰

77

121

149

121

149

Debug

JTAG

N2+

Package

100

LQFP

144

LQFP

176

LQFP

144

LQFP

176

LQFP

176

LQFP

208 MAP

BGA¹¹

1

2

3

4

5

6

Feature set dependent on selected peripheral multiplexing; table shows example

Based on 125 °C ambient operating temperature

Not shared with 12-bit ADC, but possibly shared with other alternate functions

Not shared with 10-bit ADC, but possibly shared with other alternate functions

See the eMIOS section of the chip reference manual for information on the channel configuration and functions.

Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output

Compare.

7

8

9

Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output

Compare.

Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and

Pulse width measurement.

Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare.

¹⁰Maximum I/O count based on multiplexing with peripherals

¹¹208 MAPBGA available only as development package for Nexus2+

2

Block diagram

Figure 1 shows a top-level block diagram of the MPC5607B.

MPC5607B Microcontroller Data Sheet, Rev. 9

4

NXP Semiconductors

Block diagram

SRAM

96 KB

Data Flash

64 KB

Code Flash

1.5 MB

eDMA

JTAG

JTAG Port

Nexus Port

(Master)

Instructions

SRAM

Flash

Controller

e200z0h

Nexus 2+

(Master)

Nexus

Controller

Data

NMI

(Slave)

(Master)

(Slave)

SIUL

Voltage

Regulator

Interrupt

request with

wakeup

functionality

Interrupt requests

from peripheral

blocks

(Slave)

NMI

MPU

Registers

INTC

WKPU

BAM

Clocks

CMU

FMPLL

RTC

MC_RGM MC_CGM MC_ME MC_PCU

SSCM

STM

PIT

SWT

ECSM

Peripheral Bridge

SIUL

64 ch

eMIOS

10 ×

LINFlex

6 ×

DSPI

6 ×

FlexCAN

19 ch 10-bit/12-bit 29 ch 10-bit

ADC ADC

2

CTU

I C

Reset Control

Interrupt

Request

External

Interrupt

Request

5 ch 12-bit

ADC

IMUX

GPIO &

Pad Control

. . .

I/O

Legend:

ADC

BAM

Analog-to-Digital Converter

Boot Assist Module

MC_CGM Clock Generation Module

MC_ME Mode Entry Module

CMU

CTU

Clock Monitor Unit

Cross Triggering Unit

MC_PCU Power Control Unit

MC_RGM Reset Generation Module

DSPI

ECSM

eDMA

eMIOS

Flash

Deserial Serial Peripheral Interface

Error Correction Status Module

Enhanced Direct Memory Access

Enhanced Modular Input Output System

Flash memory

MPU

NMI

PIT

Memory Protection Unit

Non-Maskable Interrupt

Periodic Interrupt Timer

Real-Time Clock

System Integration Unit Lite

Static Random-Access Memory

System Status Configuration Module

System Timer Module

Software Watchdog Timer

Voltage regulator

Wakeup Unit

Crossbar switch

RTC

SIUL

SRAM

SSCM

STM

SWT

VREG

WKPU

XBAR

FlexCAN Controller Area Network

FMPLL

GPIO

Frequency-Modulated Phase-Locked Loop

General-purpose input/output

Inter-Integrated Circuit bus

Internal Multiplexer

Interrupt Controller

JTAG controller

2

I C

IMUX

INTC

JTAG

LINFlex

Serial Communication Interface (LIN support)

Figure 1. MPC5607B block diagram

Table 2 summarizes the functions of the blocks present on the MPC5607B.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

5

Block diagram

Table 2. MPC5607B series block summary

Function

Block

Analog-to-digital converter (ADC) Converts analog voltages to digital values

Boot assist module (BAM)

A block of read-only memory containing VLE code which is executed according

to the boot mode of the device

Clock generation module

(MC_CGM)

Provides logic and control required for the generation of system and peripheral

clocks

Clock monitor unit (CMU)

Cross triggering unit (CTU)

Monitors clock source (internal and external) integrity

Enables synchronization of ADC conversions with a timer event from the eMIOS

or from the PIT

Crossbar switch (XBAR)

Supports simultaneous connections between two master ports and three slave

ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus

width.

Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices

(DSPI)

Enhanced direct memory access Performs complex data transfers with minimal intervention from a host processor

(eDMA)

via “n” programmable channels

Enhanced modular input output

system (eMIOS)

Provides the functionality to generate or measure events

Error correction status module

(ECSM)

Provides a myriad of miscellaneous control functions for the device including

program-visible information about configuration and revision levels, a reset status

register, wakeup control for exiting sleep modes, and optional features such as

information on memory errors reported by error-correcting codes

Flash memory

Provides non-volatile storage for program code, constants and variables

FlexCAN (controller area network) Supports the standard CAN communications protocol

Frequency-modulated

Generates high-speed system clocks and supports programmable frequency

phase-locked loop (FMPLL)

modulation

Inter-integrated circuit (I²C) bus

Two-wire bidirectional serial bus that provides a simple and efficient method of

data exchange between devices

Internal multiplexer (IMUX) SIU

subblock

Allows flexible mapping of peripheral interface on the different pins of the device

Interrupt controller (INTC)

JTAG controller (JTAGC)

Provides priority-based preemptive scheduling of interrupt requests

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

LINFlex controller

Manages a high number of LIN (Local Interconnect Network protocol) messages

efficiently with a minimum of CPU load

Memory protection unit (MPU)

Mode entry module (MC_ME)

Provides hardware access control for all memory references generated in a

device

Provides a mechanism for controlling the device operational mode and

modetransition sequences in all functional states; also manages the power

control unit, reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

Non-maskable interrupt (NMI)

Handles external events that must produce an immediate response, such as

power down detection

MPC5607B Microcontroller Data Sheet, Rev. 9

6

NXP Semiconductors

Block diagram

Table 2. MPC5607B series block summary (continued)

Function

Block

Periodic interrupt timer (PIT)

Power control unit (MC_PCU)

Produces periodic interrupts and triggers

Reduces the overall power consumption by disconnecting parts of the device

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

Real-time counter (RTC)

A free running counter used for time keeping applications, the RTC can be

configured to generate an interrupt at a predefined interval independent of the

mode of operation (run mode or low-power mode)

Reset generation module

(MC_RGM)

Centralizes reset sources and manages the device reset sequence of the device

Static random-access memory

(SRAM)

Provides storage for program code, constants, and variables

System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits

of bidirectional, general-purpose input and output signals and supports up to 32

external interrupts with trigger event configuration

System status and configuration Provides system configuration and status data (such as memory size and status,

module (SSCM)

device mode and security status), device identification data, debug status port

enable and selection, and bus and peripheral abort enable/disable

System timer module (STM)

Provides a set of output compare events to support AUTOSAR (Automotive Open

System Architecture) and operating system tasks

Software watchdog timer (SWT) Provides protection from runaway code

Wakeup unit (WKPU) The wakeup unit supports up to 27 external sources that can generate interrupts

or wakeup events, of which 1 can cause non-maskable interrupt requests or

wakeup events.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

7

Package pinouts and signal descriptions

3

Package pinouts and signal descriptions

3.1

Package pinouts

The available LQFP pinouts and the ballmap are provided in the following figures. For pin signal descriptions, please see

Table 5.

Figure 2 shows the MPC5607B in the 176 LQFP package.

PB[3]

PC[9]

PC[14]

PC[15]

PJ[4]

VDD_HV

VSS_HV

PH[15]

PH[13]

PH[14]

PI[6]

PI[7]

PG[5]

PG[4]

PG[3]

PG[2]

PA[2]

PE[0]

PA[1]

PE[1]

PE[8]

PE[9]

PE[10]

1

2

3

4

5

6

7

8

PA[11]

PA[10]

PA[9]

PA[8]

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

PA[7]

PE[13]

PF[14]

PF[15]

VDD_HV

VSS_HV

PG[0]

PG[1]

PH[3]

PH[2]

PH[1]

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

PH[0]

PG[12]

PG[13]

PA[3]

PI[13]

PI[12]

PI[11]

PI[10]

PI[9]

PI[8]

PB[15]

PD[15]

PB[14]

PD[14]

PB[13]

PD[13]

PB[12]

PD[12]

VDD_HV_ADC1

VSS_HV_ADC1

PB[11]

PD[11]

PD[10]

PD[9]

176 LQFP

Top view

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PG[9]

PG[8]

PC[11]

PC[10]

PG[7]

PG[6]

PB[0]

PB[1]

PF[9]

PF[8]

PF[12]

98

97

96

95

94

93

92

91

PB[7]

PB[6]

PB[5]

VDD_HV_ADC0

VSS_HV_ADC0

90

89

PC[6]

Figure 2. 176 LQFP pin configuration

MPC5607B Microcontroller Data Sheet, Rev. 9

8

NXP Semiconductors

Package pinouts and signal descriptions

Figure 3 shows the MPC5607B in the 144 LQFP package.

PB[3]

PC[9]

PC[14]

PC[15]

PG[5]

PG[4]

PG[3]

PG[2]

PA[2]

PE[0]

PA[1]

PE[1]

PE[8]

PE[9]

PE[10]

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PG[9]

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

PA[11]

PA[10]

PA[9]

PA[8]

PA[7]

PE[13]

PF[14]

PF[15]

VDD_HV

VSS_HV

PG[0]

PG[1]

PH[3]

PH[2]

PH[1]

PH[0]

PG[12]

PG[13]

PA[3]

PB[15]

PD[15]

PB[14]

PD[14]

PB[13]

PD[13]

PB[12]

VDD_HV_ADC1

VSS_HV_ADC1

PD[11]

PD[10]

PD[9]

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

144 LQFP

Top view

PG[8]

PC[11]

PC[10]

PG[7]

PG[6]

PB[0]

PB[1]

PF[9]

PF[8]

PF[12]

PC[6]

PB[7]

PB[6]

PB[5]

VDD_HV_ADC0

VSS_HV_ADC0

Figure 3. 144 LQFP pin configuration

Figure 4 shows the MPC5607B in the 100 LQFP package.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

9

Package pinouts and signal descriptions

PB[3]

PC[9]

PC[14]

PC[15]

PA[2]

PE[0]

PA[1]

PE[1]

PE[8]

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PA[11]

PA[10]

PA[9]

PA[8]

PA[7]

VDD_HV

VSS_HV

PA[3]

PB[15]

PD[15]

PB[14]

PD[14]

PB[13]

PD[13]

9

PE[9]

PE[10]

PA[0]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

100 LQFP

Top view

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PC[11]

PC[10]

PB[0]

PB[12]

VDD_HV_ADC1

VSS_HV_ADC1

PD[11]

PD[10]

PD[9]

PB[7]

PB[6]

PB[5]

VDD_HV_ADC0

VSS_HV_ADC0

PB[1]

PC[6]

Figure 4. 100 LQFP pin configuration

Figure 5 shows the MPC5607B in the 208 MAPBGA package.

MPC5607B Microcontroller Data Sheet, Rev. 9

10

NXP Semiconductors

Package pinouts and signal descriptions

1

PC[8]

PC[9]

PC[14]

PH[14]

PG[4]

PE[0]

PE[9]

VSS_HV

RESET

EVTI

2

3

4

5

6

7

8

9

10

PI[1]

PI[2]

PI[3]

NC

11

12

13

PE[15]

PG[15]

PE[14]

PG[10]

PG[1]

14

15

NC

16

NC

PC[13]

PB[2]

VDD_HV

PI[6]

PH[15]

PH[13]

PB[3]

PC[15]

PG[3]

PA[1]

PJ[4]

PC[12]

PE[7]

PI[7]

PG[2]

PE[1]

PA[0]

NC

PH[8]

PE[6]

PH[7]

PH[6]

PH[4]

PH[5]

PE[5]

PE[4]

PC[5]

PC[4]

PE[3]

PE[2]

PC[0]

PH[9]

VSS_LV

PI[0]

PC[2]

PC[3]

PA[5]

PA[6]

PI[4]

PH[11]

PG[14]

PE[12]

PF[14]

PG[0]

PH[1]

A

B

C

D

E

F

A

B

C

D

E

F

PH[10]

PC[1]

PG[11]

PI[5]

PA[11]

PA[9]

PE[13]

PA[10]

PA[8]

PA[7]

VDD_LV VDD_HV

PH[12]

PG[5]

PA[2]

PF[15] VDD_HV

PH[0]

PH[3]

PI[13]

MDO0

PI[10]

PA[3]

PH[2]

MSEO

MDO1

PI[11]

PG[13]

PB[14]

PB[12]

PD[11]

PB[7]

PB[5]

PB[4]

16

PE[8]

PE[10]

VSS_HV VSS_HV VSS_HV VSS_HV

VDD_HV

MDO3

PI[8]

PI[12]

MDO2

PI[9]

G

H

J

G

H

J

PE[11] VDD_HV

VSS_LV

NC

VDD_HV

_ADC1

VDD_BV VDD_LV

PG[12]

PD[15]

PD[13]

PD[10]

K

L

K

L

PG[9]

PG[7]

PB[1]

PF[8]

PF[12]

NC

PG[8]

PG[6]

PF[9]

PJ[3]

PC[6]

NC

PC[10]

PB[0]

PC[7]

PF[10]

NC

EVTO

PC[11]

VDD_HV

PJ[2]

PB[15]

PB[13]

PB[11]

PD[3]

PD[4]

PD[5]

13

PD[14]

PD[12]

PD[9]

PB[6]

M

N

P

R

T

M

N

P

R

T

VSS_HV

_ADC1

PJ[0]

PJ[1]

PA[4]

VSS_LV

VDD_LV

PA[13]

PA[12]

7

EXTAL VDD_HV

PF[0]

PF[1]

PF[3]

PF[2]

10

PF[4]

PF[5]

PF[7]

PF[6]

11

VDD_HV

_ADC0

PA[14]

XTAL

PI[14]

PI[15]

8

PB[10]

PD[0]

PD[2]

PD[1]

12

VSS_HV

_ADC0

PF[11] VDD_HV PA[15]

XTAL32

PD[7]

PD[6]

EXTAL

32

MCKO

NC

PF[13]

PD[8]

1

2

3

4

5

6

9

14

15

NC

NOTE: The 208 MAPBGA is available only as development package for Nexus 2+.

= Not connected

Figure 5. 208 MAPBGA configuration

3.2

Pad configuration during reset phases

All pads have a fixed configuration under reset.

During the power-up phase, all pads are forced to tristate.

After power-up phase, all pads are tristate with the following exceptions:

•

PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash.

PA[8], PC[0] and PH[9:10] are in input weak pull-up when out of reset.

RESET pad is driven low by the device till 40 FIRC clock cycles after phase2 completion.

Minimum phase3 duration is 40 FIRC cycles.

•

Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

11

Package pinouts and signal descriptions

3.3

Pad configuration during standby mode exit

Pad configuration (input buffer enable, pull enable) for low-power wakeup pads is controlled by both the

1

SIUL and WKPU modules. During standby exit, all low power pads PA[0,1,2,4,15], PB[1,3,8,9,10] ,

2

3

PC[7,9,11], PD[0,1], PE[0,9,11], PF[9,11,13] , PG[3,5,7,9] , PI[1,3] are configured according to their

respective configuration done in the WKPU module. All other pads will have the same configuration as

expected after a reset.

The TDO pad has been moved into the STANDBY domain in order to allow low-power debug

handshaking in STANDBY mode. However, no pull-resistor is active on the TDO pad while in STANDBY

mode. At this time the pad is configured as an input. When no debugger is connected the TDO pad is

floating causing additional current consumption.

To avoid the extra consumption TDO must be connected. An external pull-up resistor in the range of

47–100 kOhms should be added between the TDO pin and VDD. Only if the TDO pin is used as an

application pin and a pull-up cannot be used should a pull-down resistor with the same value be used

instead between the TDO pin and GND.

3.4

Voltage supply pins

Voltage supply pins are used to provide power to the device. Three dedicated VDD_LV/VSS_LV supply

pairs are used for 1.2 V regulator stabilization.

Table 3. Voltage supply pin descriptions

Pin number

Port pin

Function

100 LQFP

144 LQFP

176 LQFP 208 MAPBGA

VDD_HV

Digital supply voltage

15, 37, 70, 84 19, 51, 100, 6, 27, 59, 85, C2, D9, E16,

123

124, 151

G13, H3, N4,

N9, R5

VSS_HV

Digital ground

14, 16, 35, 69, 18, 20, 49, 99, 7, 26, 28, 57, G7, G8, G9,

83

122

86, 123, 150 G10, H7, H8,

H9, H10, J7,

J8, J9, J10,

K7, K8, K9,

K10

VDD_LV

VSS_LV

VDD_BV

1.2 V decoupling pins. Decoupling

capacitor must be connected

between these pins and the nearest

V_{SS_LV}pin.¹

19, 32, 85

18, 33, 86

20

23, 46, 124

22, 47, 125

24

31, 54, 152

30, 55, 153

32

D8, K4, P7

C8, J2, N7

K3

1.2 V decoupling pins. Decoupling

capacitor must be connected

between these pins and the nearest

V_{DD_LV}pin.¹

Internal regulator supply voltage

1. PB[8, 9] ports have wakeup functionality in all modes except STANDBY.

2. PF[9,11,13], PG[3,5,7,9], PI[1,3] are not available in the 100-pin LQFP.

3. PI[1,3] are not available in the 144-pin LQFP.

MPC5607B Microcontroller Data Sheet, Rev. 9

12

NXP Semiconductors

Package pinouts and signal descriptions

Table 3. Voltage supply pin descriptions (continued)

Pin number

Port pin

Function

100 LQFP

144 LQFP

176 LQFP 208 MAPBGA

VSS_HV_ADC0 Reference ground and analog ground

for the A/D converter 0 (10-bit)

51

73

74

81

82

89

90

98

99

R15

P14

N12

K13

VDD_HV_ADC0 Reference voltage and analog supply

for the A/D converter 0 (10-bit)

52

59

60

VSS_HV_ADC1 Reference ground and analog ground

for the A/D converter 1 (12-bit)

VDD_HV_ADC1 Reference voltage and analog supply

for the A/D converter 1 (12-bit)

1

A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable

voltage (see the recommended operating conditions in the device data sheet).

3.5

Pad types

In the device the following types of pads are available for system pins and functional port pins:

1

S = Slow

1 2

M = Medium

F = Fast

1 2

1

I = Input only with analog feature

J = Input/Output (‘S’ pad) with analog feature

X = Oscillator

3.6

System pins

The system pins are listed in Table 4.

Table 4. System pin descriptions

Pin number

208

MAP

RESET

configuration

Port pin

Function

100

144

176

LQFP

BGA

1

RESET BidirectionalresetwithSchmitt-Trigger I/O

characteristics and noise filter.

M

Input weak

pull-up after

RGM PHASE2

and 40 FIRC

cycles

17

21

29

J1

1. See the I/O pad electrical characteristics in the chip data sheet for details.

2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium. The only

exception is PC[1] which is in medium configuration by default (see the PCR.SRC description in the chip reference manual, Pad

Configuration Registers (PCR0–PCR148)).

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

13

Package pinouts and signal descriptions

Table 4. System pin descriptions (continued)

Pin number

208

MAP

RESET

configuration

Port pin

Function

100

144

176

LQFP

BGA

1

EXTAL Analog output of the oscillator

amplifier circuit, when the oscillator is

not in bypass mode.

I/O

X

Tristate

36

50

58

N8

P8

Analog input for the clock generator

when the oscillator is in bypass mode.

XTAL Analog input of the oscillator amplifier

circuit. Needs to be grounded if

I

34

48

56

oscillator bypass mode is used.

1

208 MAPBGA available only as development package for Nexus2+

3.7

Functional port pins

The functional port pins are listed in Table 5.

Table 5. Functional port pin descriptions

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

Port A

SIUL I/O

PA[0]

PA[1]

PA[2]

PCR[0] AF0

GPIO[0]

E0UC[0]

CLKOUT

E0UC[13]

WKPU[19]⁵

M

S

Tristate

12

7

16

11

9

24

19

17

G4

F3

F2

AF1

AF2

AF3

—

eMIOS_0 I/O

MC_CGM

eMIOS_0 I/O

O

WKPU

I

PCR[1] AF0

GPIO[1]

E0UC[1]

NMI⁶

SIUL

I/O

AF1

AF2

AF3

—

eMIOS_0 I/O

WKPU

—

WKPU

I

—

I

—

WKPU[2]⁵

PCR[2] AF0

GPIO[2]

E0UC[2]

—

SIUL

I/O

5

AF1

AF2

AF3

—

eMIOS_0 I/O

—

ADC_0

WKPU

—

O

I

MA[2]

WKPU[3]⁵

MPC5607B Microcontroller Data Sheet, Rev. 9

14

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PA[3]

PCR[3] AF0

GPIO[3]

E0UC[3]

LIN5TX

CS4_1

EIRQ[0]

ADC1_S[0]

SIUL

eMIOS_0 I/O

LINFlex_5

DSPI_1

SIUL

I/O

J

Tristate

68

29

90

43

114

51

K15

N6

AF1

AF2

AF3

—

O

I

—

ADC_1

I

PA[4]

PCR[4] AF0

GPIO[4]

E0UC[4]

—

CS0_1

LIN5RX

WKPU[9]⁵

SIUL

eMIOS_0 I/O

I/O

S

AF1

AF2

AF3

—

I/O

I

DSPI_1

LINFlex_5

WKPU

—

I

PA[5]

PA[6]

PCR[5] AF0

AF1

GPIO[5]

E0UC[5]

LIN4TX

—

SIUL

eMIOS_0 I/O

LINFlex_4

—

I/O

M

S

Tristate

79

80

118

119

146

147

C11

D11

AF2

AF3

O

—

PCR[6] AF0

GPIO[6]

E0UC[6]

—

CS1_1

EIRQ[1]

LIN4RX

SIUL

eMIOS_0 I/O

—

DSPI_1

SIUL

I/O

AF1

AF2

AF3

—

O

I

—

LINFlex_4

I

PA[7]

PA[8]

PCR[7] AF0

GPIO[7]

E0UC[7]

LIN3TX

—

EIRQ[2]

ADC1_S[1]

SIUL

eMIOS_0 I/O

LINFlex_3

—

SIUL

ADC_1

I/O

J

Tristate

71

72

104

105

128

129

D16

C16

AF1

AF2

AF3

—

O

—

I

—

I

PCR[8] AF0

GPIO[8]

E0UC[8]

E0UC[14]

—

EIRQ[3]

ABS[0]

LIN3RX

SIUL

eMIOS_0 I/O

—

SIUL

BAM

I/O

S

Input,

weak

pull-up

AF1

AF2

AF3

—

I

N/A⁷

—

LINFlex_3

PA[9]

PCR[9] AF0

AF1

GPIO[9]

E0UC[9]

—

CS2_1

FAB

SIUL

eMIOS_0 I/O

—

DSPI_1

BAM

I/O

S

Pull-

down

73

106

130

C15

AF2

—

O

I

AF3

N/A⁷

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

15

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PA[10] PCR[10] AF0

GPIO[10]

E0UC[10]

SDA

LIN2TX

ADC1_S[2]

SIUL

I/O

J

Tristate

74

75

107

108

131

132

B16

B15

AF1

AF2

AF3

—

eMIOS_0 I/O

I²C_0

LINFlex_2

ADC_1

I/O

O

I

PA[11] PCR[11] AF0

GPIO[11]

E0UC[11]

SCL

SIUL

I/O

AF1

AF2

AF3

—

eMIOS_0 I/O

I²C_0

—

I/O

—

I

—

EIRQ[16]

LIN2RX

ADC1_S[3]

SIUL

LINFlex_2

ADC_1

PA[12] PCR[12] AF0

GPIO[12]

—

E0UC[28]

CS3_1

EIRQ[17]

SIN_0

SIUL

—

eMIOS_0 I/O

DSPI_1

SIUL

DSPI_0

I/O

—

S

Tristate

31

45

53

T7

AF1

AF2

AF3

—

O

I

—

PA[13] PCR[13] AF0

GPIO[13]

SOUT_0

E0UC[29]

—

SIUL

DSPI_0

eMIOS_0 I/O

I/O

O

M

Tristate

30

28

44

42

52

50

R7

P6

AF1

AF2

AF3

—

PA[14] PCR[14] AF0

GPIO[14]

SCK_0

CS0_0

E0UC[0]

EIRQ[4]

SIUL

DSPI_0

eMIOS_0 I/O

SIUL

I/O

AF1

AF2

AF3

—

I

PA[15] PCR[15] AF0

GPIO[15]

CS0_0

SCK_0

SIUL

DSPI_0

eMIOS_0 I/O

WKPU

I/O

M

Tristate

27

23

40

31

48

39

R6

N3

AF1

AF2

AF3

—

E0UC[1]

WKPU[10]⁵

I

Port B

PB[0]

PCR[16] AF0

GPIO[16]

CAN0TX

E0UC[30]

LIN0TX

SIUL

FlexCAN_0

eMIOS_0 I/O

LINFlex_0

I/O

O

AF1

AF2

AF3

O

MPC5607B Microcontroller Data Sheet, Rev. 9

16

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PB[1]

PCR[17] AF0

GPIO[17]

—

SIUL

—

eMIOS_0 I/O

—

WKPU

I/O

—

S

Tristate

24

32

40

N1

AF1

AF2

AF3

—

E0UC[31]

—

WKPU[4]⁵

CAN0RX

LIN0RX

I

FlexCAN_0

LINFlex_0

PB[2]

PB[3]

PCR[18] AF0

GPIO[18]

LIN0TX

SDA

SIUL

LINFlex_0

I²C_0

I/O

O

I/O

M

S

Tristate

100

1

144

1

176

1

B2

C3

AF1

AF2

AF3

E0UC[30]

eMIOS_0 I/O

PCR[19] AF0

GPIO[19]

E0UC[31]

SCL

SIUL I/O

AF1

AF2

AF3

—

eMIOS_0 I/O

I²C_0

—

I/O

—

I

—

WKPU[11]⁵

LIN0RX

WKPU

LINFlex_0

—

I

PB[4]

PB[5]

PB[6]

PCR[20] AF0

—

I

Tristate

50

53

54

72

75

76

88

91

92

T16

R16

P15

AF1

AF2

AF3

—

ADC0_P[0]

ADC1_P[0]

GPIO[20]

ADC_0

ADC_1

SIUL

I

PCR[21] AF0

—

I

AF1

AF2

AF3

—

ADC0_P[1]

ADC1_P[1]

GPIO[21]

ADC_0

ADC_1

SIUL

I

PCR[22] AF0

—

I

AF1

AF2

AF3

—

ADC0_P[2]

ADC1_P[2]

GPIO[22]

ADC_0

ADC_1

SIUL

I

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

17

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PB[7]

PCR[23] AF0

—

I

Tristate

55

39

77

53

93

61

P16

AF1

AF2

AF3

—

ADC0_P[3]

ADC1_P[3]

GPIO[23]

ADC_0

ADC_1

SIUL

I

PB[8]

PCR[24] AF0

GPIO[24]

SIUL

—

I

—

R9

AF1

AF2

AF3

—

I⁹

I

—

OSC32K_XTAL⁸OSC32K

WKPU[25]⁵

ADC0_S[0]

ADC1_S[4]

WKPU

ADC_0

ADC_1

—

I

PB[9]

PCR[25] AF0

GPIO[25]

SIUL

—

I

—

38

52

60

T9

AF1

AF2

AF3

—

I⁹

I

—

OSC32K_EXTAL⁸OSC32K

WKPU[26]⁵

ADC0_S[1]

ADC1_S[5]

WKPU

ADC_0

ADC_1

—

I

PB[10] PCR[26] AF0

GPIO[26]

—

SIUL

—

I/O

—

I

J

Tristate

40

54

62

P9

AF1

AF2

AF3

—

WKPU[8]⁵

ADC0_S[2]

ADC1_S[6]

WKPU

ADC_0

ADC_1

I

PB[11] PCR[27] AF0

GPIO[27]

E0UC[3]

—

CS0_0

ADC0_S[3]

SIUL

eMIOS_0 I/O

—

DSPI_0

ADC_0

I/O

J

Tristate

—

97

N13

M16

AF1

AF2

AF3

—

I/O

I

PB[12] PCR[28] AF0

GPIO[28]

E0UC[4]

—

CS1_0

ADC0_X[0]

SIUL

eMIOS_0 I/O

—

DSPI_0

ADC_0

I/O

61

83

101

AF1

AF2

AF3

—

O

I

MPC5607B Microcontroller Data Sheet, Rev. 9

18

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PB[13] PCR[29] AF0

GPIO[29]

E0UC[5]

—

CS2_0

ADC0_X[1]

SIUL

eMIOS_0 I/O

—

DSPI_0

ADC_0

I/O

J

Tristate

63

65

67

85

87

89

103

105

107

M13

L16

L13

AF1

AF2

AF3

—

O

I

PB[14] PCR[30] AF0

GPIO[30]

E0UC[6]

—

CS3_0

ADC0_X[2]

SIUL

eMIOS_0 I/O

—

DSPI_0

ADC_0

I/O

AF1

AF2

AF3

—

O

I

PB[15] PCR[31] AF0

GPIO[31]

E0UC[7]

—

CS4_0

ADC0_X[3]

SIUL

eMIOS_0 I/O

—

DSPI_0

ADC_0

I/O

AF1

AF2

AF3

—

O

I

Port C

PC[0]¹⁰PCR[32] AF0

GPIO[32]

SIUL

—

JTAGC

—

I/O

—

I

M

Input,

weak

pull-up

87

82

78

126

121

117

154

149

145

A8

C9

AF1

AF2

AF3

—

TDI

—

PC[1]¹⁰PCR[33] AF0

GPIO[33]

—

TDO

—

SIUL

—

JTAGC

—

I/O F¹¹Tristate

—

O

AF1

AF2

AF3

—

PC[2]

PC[3]

PCR[34] AF0

GPIO[34]

SCK_1

CAN4TX

DEBUG[0]

EIRQ[5]

SIUL

DSPI_1

FlexCAN_4

SSCM

I/O

O

I

M

S

Tristate

A11

AF1

AF2

AF3

—

SIUL

PCR[35] AF0

GPIO[35]

CS0_1

MA[0]

DEBUG[1]

EIRQ[6]

CAN1RX

CAN4RX

SIUL

DSPI_1

ADC_0

SSCM

SIUL

I/O

O

I

77

92

116

131

144

159

B11

AF1

AF2

AF3

—

FlexCAN_1

FlexCAN_4

I

PC[4]

PCR[36] AF0

GPIO[36]

E1UC[31]

—

DEBUG[2]

EIRQ[18]

SIN_1

SIUL

eMIOS_1 I/O

—

SSCM

SIUL

I/O

M

Tristate

B7

AF1

AF2

AF3

—

O

I

DSPI_1

FlexCAN_3

CAN3RX

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

19

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PC[5]

PCR[37] AF0

GPIO[37]

SOUT_1

CAN3TX

DEBUG[3]

EIRQ[7]

SIUL

DSPI_1

FlexCAN_3

SSCM

I/O

O

I

M

Tristate

91

130

158

A7

AF1

AF2

AF3

—

SIUL

PC[6]

PC[7]

PCR[38] AF0

GPIO[38]

LIN1TX

E1UC[28]

DEBUG[4]

SIUL

LINFlex_1

eMIOS_1 I/O

SSCM

I/O

O

S

Tristate

25

26

36

37

44

45

R2

P3

AF1

AF2

AF3

O

PCR[39] AF0

GPIO[39]

—

SIUL

—

eMIOS_1 I/O

SSCM

LINFlex_1

WKPU

I/O

—

AF1

AF2

AF3

—

E1UC[29]

DEBUG[5]

LIN1RX

O

I

—

WKPU[12]⁵

PC[8]

PC[9]

PCR[40] AF0

GPIO[40]

LIN2TX

E0UC[3]

DEBUG[6]

SIUL

LINFlex_2

eMIOS_0 I/O

SSCM

I/O

O

S

Tristate

99

2

143

2

175

2

A1

B1

AF1

AF2

AF3

O

PCR[41] AF0

GPIO[41]

—

E0UC[7]

DEBUG[7]

WKPU[13]⁵

LIN2RX

SIUL

—

eMIOS_0 I/O

SSCM

WKPU

LINFlex_2

I/O

—

AF1

AF2

AF3

—

O

I

—

PC[10] PCR[42] AF0

GPIO[42]

CAN1TX

CAN4TX

MA[1]

SIUL

I/O

O

M

S

Tristate

22

21

28

27

36

35

M3

M4

AF1

AF2

AF3

FlexCAN_1

FlexCAN_4

ADC_0

O

PC[11] PCR[43] AF0

GPIO[43]

—

SIUL

—

I/O

—

O

I

AF1

AF2

AF3

—

MA[2]

ADC_0

WKPU

FlexCAN_1

FlexCAN_4

WKPU[5]⁵

CAN1RX

CAN4RX

I

PC[12] PCR[44] AF0

GPIO[44]

E0UC[12]

—

SIUL

eMIOS_0 I/O

—

SIUL

DSPI_2

I/O

M

Tristate

97

141

173

B4

AF1

AF2

AF3

—

I

—

EIRQ[19]

SIN_2

—

I

MPC5607B Microcontroller Data Sheet, Rev. 9

20

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PC[13] PCR[45] AF0

GPIO[45]

E0UC[13]

SOUT_2

—

SIUL

eMIOS_0 I/O

DSPI_2

—

I/O

S

Tristate

98

3

142

3

174

3

A2

C1

AF1

AF2

AF3

O

—

PC[14] PCR[46] AF0

GPIO[46]

E0UC[14]

SCK_2

—

SIUL

eMIOS_0 I/O

DSPI_2

—

SIUL

I/O

AF1

AF2

AF3

—

I/O

—

I

EIRQ[8]

PC[15] PCR[47] AF0

GPIO[47]

E0UC[15]

CS0_2

—

SIUL

eMIOS_0 I/O

DSPI_2

—

SIUL

I/O

M

Tristate

4

D3

AF1

AF2

AF3

—

I/O

—

I

EIRQ[20]

Port D

PD[0]

PD[1]

PCR[48] AF0

GPIO[48]

—

SIUL

—

I

—

I

41

63

77

P12

AF1

AF2

AF3

—

WKPU[27]⁵

ADC0_P[4]

ADC1_P[4]

WKPU

ADC_0

ADC_1

I

PCR[49] AF0

GPIO[49]

—

SIUL

—

I

—

I

Tristate

42

64

78

T12

AF1

AF2

AF3

—

WKPU[28]⁵

ADC0_P[5]

ADC1_P[5]

WKPU

ADC_0

ADC_1

I

PD[2]

PD[3]

PCR[50] AF0

GPIO[50]

SIUL

—

ADC_0

ADC_1

I

—

I

Tristate

43

44

65

66

79

80

R12

P13

AF1

AF2

AF3

—

ADC0_P[6]

ADC1_P[6]

—

I

PCR[51] AF0

GPIO[51]

SIUL

—

ADC_0

ADC_1

I

—

I

AF1

AF2

AF3

—

ADC0_P[7]

ADC1_P[7]

—

I

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

21

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PD[4]

PCR[52] AF0

GPIO[52]

SIUL

—

ADC_0

ADC_1

I

—

I

Tristate

45

46

47

48

49

56

57

67

68

69

70

71

78

79

81

82

83

84

87

94

95

R13

T13

T14

R14

T15

N15

N14

AF1

AF2

AF3

—

ADC0_P[8]

ADC1_P[8]

—

I

PD[5]

PD[6]

PD[7]

PD[8]

PD[9]

PCR[53] AF0

GPIO[53]

SIUL

—

ADC_0

ADC_1

I

—

I

AF1

AF2

AF3

—

ADC0_P[9]

ADC1_P[9]

—

I

PCR[54] AF0

GPIO[54]

SIUL

—

ADC_0

ADC_1

I

—

I

AF1

AF2

AF3

—

ADC0_P[10]

ADC1_P[10]

—

I

PCR[55] AF0

GPIO[55]

SIUL

—

ADC_0

ADC_1

I

—

I

AF1

AF2

AF3

—

ADC0_P[11]

ADC1_P[11]

—

I

PCR[56] AF0

GPIO[56]

SIUL

—

ADC_0

ADC_1

I

—

I

AF1

AF2

AF3

—

ADC0_P[12]

ADC1_P[12]

—

I

PCR[57] AF0

GPIO[57]

SIUL

—

ADC_0

ADC_1

I

—

I

AF1

AF2

AF3

—

ADC0_P[13]

ADC1_P[13]

—

I

PD[10] PCR[58] AF0

GPIO[58]

SIUL

—

ADC_0

ADC_1

I

—

I

AF1

AF2

AF3

—

ADC0_P[14]

ADC1_P[14]

—

I

MPC5607B Microcontroller Data Sheet, Rev. 9

22

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PD[11] PCR[59] AF0

GPIO[59]

SIUL

—

ADC_0

ADC_1

I

—

I

Tristate

58

80

96

N16

AF1

AF2

AF3

—

ADC0_P[15]

ADC1_P[15]

—

I

PD[12] PCR[60] AF0

GPIO[60]

CS5_0

E0UC[24]

—

SIUL

DSPI_0

eMIOS_0 I/O

—

ADC_0

I/O

O

J

Tristate

—

62

64

66

—

84

86

88

100

102

104

106

M15

M14

L15

L14

AF1

AF2

AF3

—

I

ADC0_S[4]

PD[13] PCR[61] AF0

GPIO[61]

CS0_1

E0UC[25]

—

SIUL

DSPI_1

eMIOS_0 I/O

—

ADC_0

I/O

AF1

AF2

AF3

—

I

ADC0_S[5]

PD[14] PCR[62] AF0

GPIO[62]

CS1_1

E0UC[26]

—

SIUL

DSPI_1

eMIOS_0 I/O

—

ADC_0

I/O

O

AF1

AF2

AF3

—

I

ADC0_S[6]

PD[15] PCR[63] AF0

GPIO[63]

CS2_1

E0UC[27]

—

SIUL

DSPI_1

eMIOS_0 I/O

—

ADC_0

I/O

O

AF1

AF2

AF3

—

I

ADC0_S[7]

Port E

PE[0]

PCR[64] AF0

GPIO[64]

E0UC[16]

—

SIUL

eMIOS_0 I/O

I/O

S

Tristate

6

10

18

F1

AF1

AF2

AF3

—

I

—

WKPU[6]⁵

CAN5RX

WKPU

FlexCAN_5

—

I

PE[1]

PE[2]

PCR[65] AF0

GPIO[65]

E0UC[17]

CAN5TX

—

SIUL

eMIOS_0 I/O

FlexCAN_5

—

I/O

M

Tristate

8

12

20

F4

D7

AF1

AF2

AF3

O

—

PCR[66] AF0

GPIO[66]

E0UC[18]

—

SIUL

eMIOS_0 I/O

—

SIUL

DSPI_1

I/O

89

128

156

AF1

AF2

AF3

—

I

—

EIRQ[21]

SIN_1

—

I

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

23

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PE[3]

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PCR[67] AF0

GPIO[67]

E0UC[19]

SOUT_1

—

SIUL

eMIOS_0 I/O

DSPI_1

—

I/O

M

Tristate

90

93

129

132

157

160

C7

D6

AF1

AF2

AF3

O

—

PE[4]

PCR[68] AF0

GPIO[68]

E0UC[20]

SCK_1

—

SIUL

eMIOS_0 I/O

DSPI_1

—

SIUL

I/O

AF1

AF2

AF3

—

I/O

—

I

EIRQ[9]

PE[5]

PE[6]

PCR[69] AF0

GPIO[69]

E0UC[21]

CS0_1

SIUL

eMIOS_0 I/O

DSPI_1

ADC_0

I/O

M

Tristate

94

95

133

139

161

167

C6

B5

AF1

AF2

AF3

I/O

O

MA[2]

PCR[70] AF0

GPIO[70]

E0UC[22]

CS3_0

MA[1]

EIRQ[22]

SIUL

eMIOS_0 I/O

DSPI_0

ADC_0

SIUL

I/O

AF1

AF2

AF3

—

O

I

PE[7]

PCR[71] AF0

GPIO[71]

E0UC[23]

CS2_0

MA[0]

EIRQ[23]

SIUL

eMIOS_0 I/O

DSPI_0

ADC_0

SIUL

I/O

M

Tristate

96

140

168

C4

AF1

AF2

AF3

—

O

I

PE[8]

PE[9]

PCR[72] AF0

GPIO[72]

CAN2TX

E0UC[22]

CAN3TX

SIUL

FlexCAN_2

eMIOS_0 I/O

FlexCAN_3

I/O

O

M

S

Tristate

9

13

14

21

22

G2

G1

AF1

AF2

AF3

O

PCR[73] AF0

GPIO[73]

—

SIUL

—

eMIOS_0 I/O

—

WKPU

I/O

—

10

AF1

AF2

AF3

—

E0UC[23]

—

WKPU[7]⁵

CAN2RX

CAN3RX

I

FlexCAN_2

FlexCAN_3

PE[10] PCR[74] AF0

GPIO[74]

LIN3TX

CS3_1

E1UC[30]

EIRQ[10]

SIUL

LINFlex_3

DSPI_1

eMIOS_1 I/O

SIUL

I/O

O

S

Tristate

11

15

23

G3

AF1

AF2

AF3

—

I

MPC5607B Microcontroller Data Sheet, Rev. 9

24

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PE[11] PCR[75] AF0

GPIO[75]

E0UC[24]

CS4_1

SIUL

eMIOS_0 I/O

DSPI_1

—

LINFlex_3

WKPU

I/O

S

J

Tristate

13

76

17

25

H2

AF1

AF2

AF3

—

O

—

I

—

LIN3RX

—

WKPU[14]⁵

I

PE[12] PCR[76] AF0

GPIO[76]

—

SIUL

—

eMIOS_1 I/O

—

SIUL

I/O

—

109

133

C14

AF1

AF2

AF3

—

E1UC[19]¹²

—

EIRQ[11]

SIN_2

ADC1_S[7]

I

DSPI_2

ADC_1

PE[13] PCR[77] AF0

GPIO[77]

SOUT_2

E1UC[20]

—

SIUL

DSPI_2

eMIOS_1 I/O

I/O

O

S

Tristate

—

103

112

127

136

D15

C13

AF1

AF2

AF3

—

PE[14] PCR[78] AF0

GPIO[78]

SCK_2

E1UC[21]

—

SIUL

DSPI_2

eMIOS_1 I/O

—

SIUL

I/O

AF1

AF2

AF3

—

I

EIRQ[12]

PE[15] PCR[79] AF0

GPIO[79]

CS0_2

E1UC[22]

—

SIUL

DSPI_2

eMIOS_1 I/O

I/O

M

Tristate

—

113

137

A13

AF1

AF2

AF3

—

Port F

PF[0]

PF[1]

PF[2]

PCR[80] AF0

GPIO[80]

E0UC[10]

CS3_1

SIUL

eMIOS_0 I/O

DSPI_1

—

ADC_0

I/O

J

Tristate

—

55

56

57

63

64

65

N10

P10

T10

AF1

AF2

AF3

—

O

—

I

—

ADC0_S[8]

PCR[81] AF0

GPIO[81]

E0UC[11]

CS4_1

SIUL

eMIOS_0 I/O

DSPI_1

—

ADC_0

I/O

AF1

AF2

AF3

—

O

—

I

—

ADC0_S[9]

PCR[82] AF0

GPIO[82]

E0UC[12]

CS0_2

SIUL

eMIOS_0 I/O

DSPI_2

—

ADC_0

I/O

AF1

AF2

AF3

—

I/O

—

I

—

ADC0_S[10]

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

25

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PF[3]

PCR[83] AF0

GPIO[83]

E0UC[13]

CS1_2

SIUL

eMIOS_0 I/O

DSPI_2

—

ADC_0

I/O

J

Tristate

—

58

59

60

61

62

66

67

68

69

70

R10

N11

P11

T11

R11

AF1

AF2

AF3

—

O

—

I

—

ADC0_S[11]

PF[4]

PF[5]

PF[6]

PF[7]

PCR[84] AF0

GPIO[84]

E0UC[14]

CS2_2

SIUL

eMIOS_0 I/O

DSPI_2

—

ADC_0

I/O

AF1

AF2

AF3

—

O

—

I

—

ADC0_S[12]

PCR[85] AF0

GPIO[85]

E0UC[22]

CS3_2

SIUL

eMIOS_0 I/O

DSPI_2

—

ADC_0

I/O

AF1

AF2

AF3

—

O

—

I

—

ADC0_S[13]

PCR[86] AF0

GPIO[86]

E0UC[23]

CS1_1

SIUL

eMIOS_0 I/O

DSPI_1

—

ADC_0

I/O

AF1

AF2

AF3

—

O

—

I

—

ADC0_S[14]

PCR[87] AF0

GPIO[87]

—

CS2_1

—

SIUL

—

DSPI_1

—

I/O

—

O

—

I

AF1

AF2

AF3

—

ADC0_S[15]

ADC_0

PF[8]

PF[9]

PCR[88] AF0

GPIO[88]

CAN3TX

CS4_0

SIUL

FlexCAN_3

DSPI_0

I/O

O

M

S

Tristate

—

34

33

42

41

P1

N2

AF1

AF2

AF3

CAN2TX

FlexCAN_2

O

PCR[89] AF0

GPIO[89]

E1UC[1]

CS5_0

SIUL

eMIOS_1 I/O

DSPI_0

—

WKPU

I/O

AF1

AF2

AF3

—

O

—

I

—

WKPU[22]⁵

CAN2RX

CAN3RX

FlexCAN_2

FlexCAN_3

PF[10] PCR[90] AF0

GPIO[90]

CS1_0

LIN4TX

E1UC[2]

SIUL

DSPI_0

LINFlex_4

I/O

O

M

Tristate

—

38

46

R3

AF1

AF2

AF3

eMIOS_1 I/O

MPC5607B Microcontroller Data Sheet, Rev. 9

26

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PF[11] PCR[91] AF0

GPIO[91]

CS2_0

SIUL

DSPI_0

eMIOS_1 I/O

—

WKPU

LINFlex_4

I/O

O

S

Tristate

—

39

47

R4

AF1

AF2

AF3

—

E1UC[3]

—

I

WKPU[15]⁵

LIN4RX

—

PF[12] PCR[92] AF0

GPIO[92]

E1UC[25]

LIN5TX

—

SIUL

eMIOS_1 I/O

LINFlex_5

—

I/O

M

S

Tristate

—

35

41

43

49

R1

T6

AF1

AF2

AF3

O

—

PF[13] PCR[93] AF0

GPIO[93]

E1UC[26]

—

SIUL

eMIOS_1 I/O

I/O

AF1

AF2

AF3

—

I

—

WKPU[16]⁵

LIN5RX

WKPU

LINFlex_5

—

I

PF[14] PCR[94] AF0

GPIO[94]

CAN4TX

E1UC[27]

CAN1TX

SIUL

FlexCAN_4

eMIOS_1 I/O

FlexCAN_1

I/O

O

M

S

Tristate

—

102

101

126

125

D14

E15

AF1

AF2

AF3

O

PF[15] PCR[95] AF0

GPIO[95]

E1UC[4]

—

SIUL

eMIOS_1 I/O

—

SIUL

I/O

AF1

AF2

AF3

—

I

—

EIRQ[13]

CAN1RX

CAN4RX

FlexCAN_1

FlexCAN_4

Port G

PG[0] PCR[96] AF0

GPIO[96]

CAN5TX

E1UC[23]

—

SIUL

FlexCAN_5

eMIOS_1 I/O

I/O

O

M

S

Tristate

—

98

97

122

121

E14

E13

AF1

AF2

AF3

—

PG[1] PCR[97] AF0

GPIO[97]

—

E1UC[24]

—

EIRQ[14]

CAN5RX

SIUL

—

eMIOS_1 I/O

—

SIUL

I/O

—

AF1

AF2

AF3

—

I

—

FlexCAN_5

PG[2] PCR[98] AF0

GPIO[98]

E1UC[11]

SOUT_3

—

SIUL

eMIOS_1 I/O

DSPI_3

—

I/O

M

Tristate

—

8

16

E4

AF1

AF2

AF3

O

—

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

27

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PG[3] PCR[99] AF0

GPIO[99]

E1UC[12]

CS0_3

SIUL

eMIOS_1 I/O

DSPI_3

—

WKPU

I/O

S

Tristate

—

7

15

E3

AF1

AF2

AF3

—

I/O

—

I

—

WKPU[17]⁵

PG[4] PCR[100] AF0

GPIO[100]

E1UC[13]

SCK_3

—

SIUL

eMIOS_1 I/O

DSPI_3

—

I/O

M

S

Tristate

—

6

5

14

13

E1

E2

AF1

AF2

AF3

I/O

—

PG[5] PCR[101] AF0

GPIO[101]

E1UC[14]

—

SIUL

eMIOS_1 I/O

—

WKPU

DSPI_3

I/O

AF1

AF2

AF3

—

I

—

WKPU[18]⁵

SIN_3

—

I

PG[6] PCR[102] AF0

GPIO[102]

E1UC[15]

LIN6TX

—

SIUL

eMIOS_1 I/O

LINFlex_6

—

I/O

M

S

Tristate

—

30

29

38

37

M2

M1

AF1

AF2

AF3

O

—

PG[7] PCR[103] AF0

GPIO[103]

E1UC[16]

E1UC[30]

—

SIUL

eMIOS_1 I/O

—

WKPU

I/O

AF1

AF2

AF3

—

I

WKPU[20]⁵

LIN6RX

—

LINFlex_6

PG[8] PCR[104] AF0

GPIO[104]

E1UC[17]

LIN7TX

CS0_2

EIRQ[15]

SIUL

eMIOS_1 I/O

LINFlex_7

DSPI_2

SIUL

I/O

S

Tristate

—

26

25

34

33

L2

L1

AF1

AF2

AF3

—

O

I/O

I

PG[9] PCR[105] AF0

GPIO[105]

E1UC[18]

—

SIUL

eMIOS_1 I/O

—

DSPI_2

WKPU

I/O

AF1

AF2

AF3

—

I/O

I

SCK_2

WKPU[21]⁵

LIN7RX

—

LINFlex_7

I

PG[10] PCR[106] AF0

GPIO[106]

E0UC[24]

E1UC[31]

—

SIUL

eMIOS_0 I/O

eMIOS_1 I/O

—

DSPI_4

I/O

S

Tristate

—

114

138

D13

AF1

AF2

AF3

—

I

SIN_4

MPC5607B Microcontroller Data Sheet, Rev. 9

28

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PG[11] PCR[107] AF0

GPIO[107]

E0UC[25]

CS0_4

—

SIUL

eMIOS_0 I/O

DSPI_4

—

I/O

M

S

Tristate

—

115

92

139

116

115

134

135

B12

K14

K16

B14

B13

AF1

AF2

AF3

I/O

—

PG[12] PCR[108] AF0

GPIO[108]

E0UC[26]

SOUT_4

—

SIUL

eMIOS_0 I/O

DSPI_4

—

I/O

AF1

AF2

AF3

O

—

PG[13] PCR[109] AF0

GPIO[109]

E0UC[27]

SCK_4

—

SIUL

eMIOS_0 I/O

DSPI_4

—

I/O

91

AF1

AF2

AF3

I/O

—

PG[14] PCR[110] AF0

GPIO[110]

E1UC[0]

LIN8TX

—

SIUL

eMIOS_1 I/O

LINFlex_8

—

I/O

110

111

AF1

AF2

AF3

O

—

PG[15] PCR[111] AF0

GPIO[111]

E1UC[1]

—

LIN8RX

SIUL

eMIOS_1 I/O

I/O

M

AF1

AF2

AF3

—

I

LINFlex_8

Port H

PH[0] PCR[112] AF0

GPIO[112]

E1UC[2]

—

SIN_1

SIUL

eMIOS_1 I/O

—

DSPI_1

I/O

M

Tristate

—

93

117

F13

AF1

AF2

AF3

—

I

PH[1] PCR[113] AF0

GPIO[113]

E1UC[3]

SOUT_1

—

SIUL

eMIOS_1 I/O

DSPI_1

—

I/O

M

Tristate

—

94

95

96

118

119

120

F14

F16

F15

AF1

AF2

AF3

O

—

PH[2] PCR[114] AF0

GPIO[114]

E1UC[4]

SCK_1

—

SIUL

eMIOS_1 I/O

DSPI_1

—

I/O

AF1

AF2

AF3

I/O

—

PH[3] PCR[115] AF0

GPIO[115]

E1UC[5]

CS0_1

—

SIUL

eMIOS_1 I/O

DSPI_1

—

I/O

AF1

AF2

AF3

I/O

—

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

29

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PH[4] PCR[116] AF0

GPIO[116]

E1UC[6]

—

SIUL

eMIOS_1 I/O

I/O

M

S

Tristate

—

88

81

—

134

135

136

137

138

127

120

—

162

163

164

165

166

155

148

140

141

9

A6

B6

AF1

AF2

AF3

—

PH[5] PCR[117] AF0

GPIO[117]

E1UC[7]

—

SIUL

eMIOS_1 I/O

I/O

AF1

AF2

AF3

—

PH[6] PCR[118] AF0

GPIO[118]

E1UC[8]

—

SIUL

eMIOS_1 I/O

—

ADC_0

I/O

M

S

D5

C5

A5

AF1

AF2

AF3

—

O

MA[2]

PH[7] PCR[119] AF0

GPIO[119]

E1UC[9]

CS3_2

SIUL

eMIOS_1 I/O

DSPI_2

ADC_0

I/O

AF1

AF2

AF3

O

MA[1]

PH[8] PCR[120] AF0

GPIO[120]

E1UC[10]

CS2_2

SIUL

eMIOS_1 I/O

DSPI_2

ADC_0

I/O

AF1

AF2

AF3

O

MA[0]

PH[9]¹⁰PCR[121] AF0

GPIO[121]

SIUL

—

JTAGC

—

I/O

—

I

Input,

weak

pull-up

B8

AF1

AF2

AF3

—

TCK

—

PH[10]¹⁰PCR[122] AF0

GPIO[122]

SIUL

—

JTAGC

—

I/O

—

I

M

Input,

weak

pull-up

B9

AF1

AF2

AF3

—

TMS

—

PH[11] PCR[123] AF0

GPIO[123]

SOUT_3

CS0_4

SIUL

DSPI_3

DSPI_4

I/O

O

I/O

Tristate

A14

D12

B3

AF1

AF2

AF3

E1UC[5]

eMIOS_1 I/O

PH[12] PCR[124] AF0

GPIO[124]

SCK_3

CS1_4

SIUL

DSPI_3

DSPI_4

I/O

O

—

AF1

AF2

AF3

E1UC[25]

eMIOS_1 I/O

PH[13] PCR[125] AF0

GPIO[125]

SOUT_4

CS0_3

SIUL

DSPI_4

DSPI_3

I/O

O

I/O

—

AF1

AF2

AF3

E1UC[26]

eMIOS_1 I/O

MPC5607B Microcontroller Data Sheet, Rev. 9

30

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PH[14] PCR[126] AF0

GPIO[126]

SCK_4

CS1_3

SIUL

DSPI_4

DSPI_3

I/O

O

M

Tristate

—

10

8

D1

A3

AF1

AF2

AF3

E1UC[27]

eMIOS_1 I/O

PH[15] PCR[127] AF0

GPIO[127]

SOUT_5

—

SIUL

DSPI_5

—

I/O

O

—

AF1

AF2

AF3

E1UC[17]

eMIOS_1 I/O

Port I

PI[0] PCR[128] AF0

GPIO[128]

E0UC[28]

LIN8TX

—

SIUL

eMIOS_0 I/O

LINFlex_8

—

I/O

S

Tristate

—

172

171

A9

AF1

AF2

AF3

O

—

PI[1] PCR[129] AF0

GPIO[129]

E0UC[29]

—

SIUL

eMIOS_0 I/O

I/O

A10

AF1

AF2

AF3

—

I

—

WKPU[24]⁵

LIN8RX

WKPU

LINFlex_8

—

I

PI[2] PCR[130] AF0

GPIO[130]

E0UC[30]

LIN9TX

—

SIUL

eMIOS_0 I/O

LINFlex_9

—

I/O

S

Tristate

—

170

169

B10

C10

AF1

AF2

AF3

O

—

PI[3] PCR[131] AF0

GPIO[131]

E0UC[31]

—

SIUL

eMIOS_0 I/O

I/O

AF1

AF2

AF3

—

I

—

WKPU[23]⁵

LIN9RX

WKPU

LINFlex_9

—

I

PI[4] PCR[132] AF0

GPIO[132]

E1UC[28]

SOUT_4

—

SIUL

eMIOS_1 I/O

DSPI_4

—

I/O

S

Tristate

—

143

142

11

A12

C12

D2

AF1

AF2

AF3

O

—

PI[5] PCR[133] AF0

GPIO[133]

E1UC[29]

SCK_4

—

SIUL

eMIOS_1 I/O

DSPI_4

—

I/O

AF1

AF2

AF3

I/O

—

PI[6] PCR[134] AF0

GPIO[134]

E1UC[30]

CS0_4

—

SIUL

eMIOS_1 I/O

DSPI_4

—

I/O

AF1

AF2

AF3

I/O

—

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

31

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PI[7] PCR[135] AF0

GPIO[135]

E1UC[31]

CS1_4

—

SIUL

eMIOS_1 I/O

DSPI_4

—

I/O

S

J

Tristate

—

12

D3

AF1

AF2

AF3

O

—

PI[8] PCR[136] AF0

GPIO[136]

SIUL

—

ADC_0

I/O

—

I

108

J13

AF1

AF2

AF3

—

ADC0_S[16]

PI[9] PCR[137] AF0

GPIO[137]

SIUL

—

ADC_0

I/O

—

I

J

Tristate

—

109

110

111

J14

J15

J16

AF1

AF2

AF3

—

ADC0_S[17]

PI[10] PCR[138] AF0

GPIO[138]

SIUL

—

ADC_0

I/O

—

I

AF1

AF2

AF3

—

ADC0_S[18]

PI[11] PCR[139] AF0

GPIO[139]

SIUL

—

ADC_0

DSPI_3

I/O

—

I

AF1

AF2

AF3

—

ADC0_S[19]

SIN_3

—

I

PI[12] PCR[140] AF0

GPIO[140]

CS0_3

—

SIUL

DSPI_3

—

ADC_0

I/O

—

I

J

Tristate

—

112

113

76

G14

G15

R8

AF1

AF2

AF3

—

ADC0_S[20]

PI[13] PCR[141] AF0

GPIO[141]

CS1_3

—

SIUL

DSPI_3

—

ADC_0

I/O

O

—

I

AF1

AF2

AF3

—

ADC0_S[21]

PI[14] PCR[142] AF0

GPIO[142]

SIUL

—

ADC_0

DSPI_4

I/O

—

I

AF1

AF2

AF3

—

ADC0_S[22]

SIN_4

—

I

MPC5607B Microcontroller Data Sheet, Rev. 9

32

NXP Semiconductors

Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

208

MAP

Port pin

PCR

Function

Peripheral

100

144

176

LQFP LQFP LQFP

BGA

4

PI[15] PCR[143] AF0

GPIO[143]

CS0_4

—

SIUL

DSPI_4

—

ADC_0

I/O

—

I

J

Tristate

—

75

T8

AF1

AF2

AF3

—

ADC0_S[23]

Port J

PJ[0] PCR[144] AF0

GPIO[144]

CS1_4

—

SIUL

DSPI_4

—

ADC_0

I/O

O

—

I

J

Tristate

—

74

73

N5

P5

AF1

AF2

AF3

—

ADC0_S[24]

PJ[1] PCR[145] AF0

GPIO[145]

SIUL

—

——

ADC_0

DSPI_5

I/O

—

I

AF1

AF2

AF3

—

ADC0_S[25]

SIN_5

—

I

PJ[2] PCR[146] AF0

GPIO[146]

CS0_5

—

SIUL

DSPI_5

—

ADC_0

I/O

—

I

J

Tristate

—

72

71

5

P4

P2

A4

AF1

AF2

AF3

—

ADC0_S[26]

PJ[3] PCR[147] AF0

GPIO[147]

CS1_5

—

SIUL

DSPI_5

—

ADC_0

I/O

O

—

I

AF1

AF2

AF3

—

ADC0_S[27]

PJ[4] PCR[148] AF0

GPIO[148]

SCK_5

E1UC[18]

—

SIUL

DSPI_5

eMIOS_1 I/O

I/O

M

AF1

AF2

AF3

—

1

2

Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module.

PCR.PA = 00 → AF0; PCR.PA = 01 → AF1; PCR.PA = 10 → AF2; PCR.PA = 11 → AF2. This is intended to

select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of

the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is

reported as “—”.

Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by

setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.

3

4

5

6

The RESET configuration applies during and after reset.

208 MAPBGA available only as development package for Nexus2+

All WKPU pins also support external interrupt capability. See the WKPU chapter for further details.

NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

33

Electrical characteristics

7

“Not applicable” because these functions are available only while the device is booting. Refer to the BAM

information for details.

8

9

Value of PCR.IBE bit must be 0

This wakeup input cannot be used to exit STANDBY mode.

¹⁰Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.

PC[0:1] are available as JTAG pins (TDI and TDO respectively).

PH[9:10] are available as JTAG pins (TCK and TMS respectively).

It is up to the user to configure these pins as GPIO when needed.

¹¹PC[1] is a fast/medium pad but is in medium configuration by default. This pad is in Alternate Function 2 mode after

reset which has TDO functionality. The reset value of PCR.OBE is ‘1’, but this setting has no impact as long as this

pad stays in AF2 mode. After configuring this pad as GPIO (PCR.PA = 0), output buffer is enabled as reset value

of PCR.OBE = 1.

¹²Not available in 100 LQFP package

3.8

Nexus 2+ pins

In the 208 MAPBGA package, eight additional debug pins are available (see Table 6).

Table 6. Nexus 2+ pin descriptions

Pin number

I/O

direction

Function

after reset

Port pin

Function

Pad type

100

144

208 MAP

BGA¹

LQFP

MCKO

MDO0

MDO1

MDO2

MDO3

EVTI

Message clock out

Message data out 0

Message data out 1

Message data out 2

Message data out 3

Event in

O

I

F

—

T4

H15

H16

H14

H13

K1

M

—

Pull-up

—

EVTO

MSEO

Event out

O

L4

Message start/end out

—

G16

1

208 MAPBGA available only as development package for Nexus2+

4

Electrical characteristics

This section contains electrical characteristics of the device as well as temperature and power

considerations.

This product contains devices to protect the inputs against damage due to high static voltages. However,

it is advisable to take precautions to avoid application of any voltage higher than the specified maximum

rated voltages.

To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This

DD

SS

could be done by the internal pull-up and pull-down, which is provided by the product for most general

purpose pins.

MPC5607B Microcontroller Data Sheet, Rev. 9

34

NXP Semiconductors

Electrical characteristics

The parameters listed in the following tables represent the characteristics of the device and its demands on

the system.

In the tables where the device logic provides signals with their respective timing characteristics, the

symbol “CC” for Controller Characteristics is included in the Symbol column.

In the tables where the external system must provide signals with their respective timing characteristics to

the device, the symbol “SR” for System Requirement is included in the Symbol column.

4.1

Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the

customer a better understanding, the classifications listed in Table 7 are used and the parameters are tagged

accordingly in the tables where appropriate.

Table 7. Parameter classifications

Classification tag

Tag description

P

C

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically

relevant sample size across process variations.

T

Those parameters are achieved by design characterization on a small sample size from typical

devices under typical conditions unless otherwise noted. All values shown in the typical column

are within this category.

D

Those parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled “C” in the parameter tables where

appropriate.

4.2

NVUSRO register

Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the device configuration, namely electrical

parameters such as high voltage supply and oscillator margin, as well as digital functionality (watchdog enable/disable after

reset).

For a detailed description of the NVUSRO register, please refer to the device reference manual.

4.2.1

NVUSRO[PAD3V5V] field description

The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 8 shows how NVUSRO[PAD3V5V] controls

the device configuration.

1

Table 8. PAD3V5V field description

Value²

Description

0

1

High voltage supply is 5.0 V

High voltage supply is 3.3 V

1

See the device reference manual for more information on the NVUSRO register.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

35

Electrical characteristics

2

Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

4.2.2

NVUSRO[OSCILLATOR_MARGIN] field description

The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value.

Table 9 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.

1

Table 9. OSCILLATOR_MARGIN field description

Value²

Description

0

1

Low consumption configuration (4 MHz/8 MHz)

High margin configuration (4 MHz/16 MHz)

1

2

See the device reference manual for more information on the NVUSRO register.

Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

4.2.3

NVUSRO[WATCHDOG_EN] field description

The watchdog enable/disable configuration after reset is dependent on the WATCHDOG_EN bit value.

Table 10 shows how NVUSRO[WATCHDOG_EN] controls the device configuration.

Table 10. WATCHDOG_EN field description

Value¹

Description

0

1

Disable after reset

Enable after reset

1

Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

4.3

Absolute maximum ratings

Table 11. Absolute maximum ratings

Value

Symbol

Parameter

Conditions

Unit

Min

Max

V_SS

V_DD

SR Digital ground on VSS_HV pins

—

0

V

SR Voltage on VDD_HV pins with respect to

–0.3

6.0

ground (V_SS

)

V_{SS_LV}SR Voltage on VSS_LV (low voltage digital supply)

—

V

_SS– 0.1 V_SS+ 0.1

V

pins with respect to ground (V_SS

)

V_{DD_BV}SR Voltage on VDD_BV (regulator supply) pin with

—

Relative to V_DD

—

–0.3

6.0

respect to ground (V_SS

)

V_DD+ 0.3

V_{SS_ADC}SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1

(ADC reference) pins with respect to ground

V_SS– 0.1 V_SS+ 0.1

V

(V_SS

)

V_{DD_ADC}SR Voltage on VDD_HV_ADC0, VDD_HV_ADC1

(ADC reference) pins with respect to ground

—

–0.3

6.0

Relative to V_DD

V_DD− 0.3 V_DD+ 0.3

(V_SS

)

MPC5607B Microcontroller Data Sheet, Rev. 9

36

NXP Semiconductors

Electrical characteristics

Table 11. Absolute maximum ratings (continued)

Value

Unit

Symbol

Parameter

Conditions

Min

Max

V_IN

SR Voltage on any GPIO pin with respect to

—

Relative to V_DD

—

–0.3

—

6.0

V_DD+ 0.3

10

V

ground (V_SS

)

I_INJPADSR Injected input current on any pin during

overload condition

–10

mA

I_INJSUMSR Absolute sum of all injected input currents

during overload condition

—

–50

—

50

70

I_AVGSEGSR Sum of all the static I/O current within a supply V_DD= 5.0 V 10ꢀ,

mA

°C

segment

PAD3V5V = 0

V_DD= 3.3 V 10ꢀ,

—

64

PAD3V5V = 1

T_STORAGESR Storage temperature

—

–55

150

NOTE

Stresses exceeding the recommended absolute maximum ratings may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification are not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability. During overload conditions (V > V or

IN

DD

V

< V ), the voltage on pins with respect to ground (V ) must not exceed the

IN

SS SS

recommended values.

4.4

Recommended operating conditions

Table 12. Recommended operating conditions (3.3 V)

Value

Symbol

Parameter

Conditions

Unit

Min

Max

V_SS

SR Digital ground on VSS_HV pins

—

0

V

1

V_DD

SR Voltage on VDD_HV pins with respect to

3.0

3.6

ground (V_SS

)

2

V_{SS_LV}

SR Voltage on VSS_LV (low voltage digital

supply) pins with respect to ground (V_SS

—

V_SS− 0.1 V_SS+ 0.1

3.0 3.6

V

)

3

V_{DD_BV}

SR Voltage on VDD_BV pin (regulator supply)

with respect to ground (V_SS

—

Relative to V_DD

—

)

V_DD− 0.1 V_DD+ 0.1

V_SS− 0.1 V_SS+ 0.1

V_{SS_ADC}

SR Voltage on VSS_HV_ADC0,

V

VSS_HV_ADC1 (ADC reference) pin with

respect to ground (V_SS

)

3.0⁵

V_DD− 0.1 V_DD+ 0.1

3.6

4

V_{DD_ADC}

SR Voltage on VDD_HV_ADC0,

—

VDD_HV_ADC1 (ADC reference) with

Relative to V_DD

respect to ground (V_SS

)

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

37

Electrical characteristics

Table 12. Recommended operating conditions (3.3 V) (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Max

V_IN

SR Voltage on any GPIO pin with respect to

—

Relative to V_DD

—

V_SS− 0.1

—

V_DD+ 0.1

5

V

ground (V_SS

)

—

I_INJPAD

I_INJSUM

TV_DD

SR Injected input current on any pin during

overload condition

−5

mA

SR Absolute sum of all injected input currents

during overload condition

—

−50

50

SR V_DDslope to ensure correct power up⁶

—

3.0⁷

−40

0.25 V/µs V/s

T_{A C-Grade Part}SR Ambient temperature under bias

T_{J C-Grade Part}SR Junction temperature under bias

T_{A V-Grade Part}SR Ambient temperature under bias

T_{J V-Grade Part}SR Junction temperature under bias

T_{A M-Grade Part}SR Ambient temperature under bias

T_{J M-Grade Part}SR Junction temperature under bias

f_CPU≤ 64 MHz⁸

85

°C

—

110

105

130

125

150

f_CPU≤ 64 MHz⁸

—

f_CPU≤ 64 MHz⁸

—

1

2

3

100 nF capacitance needs to be provided between each V_DD/V_SSpair.

330 nF capacitance needs to be provided between each V_{DD_LV}/V_{SS_LV}supply pair.

470 nF capacitance needs to be provided between V_{DD_BV}and the nearest V_{SS_LV}(higher value may be needed

depending on external regulator characteristics). Supply ramp slope on VDD_BV should always be faster or equal

to slope of VDD_HV. Otherwise, device may enter regulator bypass mode if slope on VDD_BV is slower.

4

5

100 nF capacitance needs to be provided between V_{DD_ADC}/V_{SS_ADC}pair.

Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical

characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below V_LVDHVL

device is reset.

,

6

7

8

Guaranteed by device validation

Minimum value of TV_DDmust be guaranteed until V_DDreaches 2.6 V (maximum value of V_PORH

)

When the FMPLL uses the frequency modulation with a modulation depth of 4ꢀ from the center spread frequency,

the maximum value of f_CPUis 66.56 MHz.

Table 13. Recommended operating conditions (5.0 V)

Value

Symbol

Parameter

Conditions

Unit

Min

Max

V_SS

SR Digital ground on VSS_HV pins

—

0

V

1

V_DD

SR Voltage on VDD_HV pins with respect to ground

—

Voltage drop²

—

4.5

3.0

5.5

(V_SS

)

3

V_{SS_LV}

SR Voltage on VSS_LV (low voltage digital supply)

V_SS− 0.1 V_SS+ 0.1

V

pins with respect to ground (V_SS

)

4

V_{DD_BV}

SR Voltage on VDD_BV pin (regulator supply) with

respect to ground (V_SS

—

4.5

3.0

5.5

)

Voltage drop²

Relative to V_DD

V_DD+ 0.1

MPC5607B Microcontroller Data Sheet, Rev. 9

38

NXP Semiconductors

Electrical characteristics

Table 13. Recommended operating conditions (5.0 V) (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Max

V_{SS_ADC}

SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1

(ADC reference) pin with respect to ground (V_SS

—

V_SS− 0.1 V_SS+ 0.1

V

)

5

V_{DD_ADC}

SR Voltage on VDD_HV_ADC0, VDD_HV_ADC1

—

4.5

3.0

5.5

(ADC reference) with respect to ground (V_SS

)

Voltage drop²

Relative to V_DDV_DD− 0.1 V_DD+ 0.1

V_IN

SR Voltage on any GPIO pin with respect to ground

(V_SS

—

Relative to V_DD

—

V_SS− 0.1

—

V_DD+ 0.1

5

V

)

—

I_INJPAD

I_INJSUM

TV_DD

SR Injected input current on any pin during overload

condition

−5

mA

SR Absolute sum of all injected input currents during

overload condition

—

−50

50

SR V_DDslope to ensure correct power up⁶

—

3.0⁷

−40

0.25 V/µs V/s

T_{A C-Grade Part}SR Ambient temperature under bias

T_{J C-Grade Part}SR Junction temperature under bias

T_{A V-Grade Part}SR Ambient temperature under bias

T_{J V-Grade Part}SR Junction temperature under bias

T_{A M-Grade Part}SR Ambient temperature under bias

T_{J M-Grade Part}SR Junction temperature under bias

f_CPU≤ 64 MHz⁸

85

°C

—

110

105

130

125

150

f_CPU≤ 64 MHz⁸

—

f_CPU≤ 64 MHz⁸

—

1

100 nF capacitance needs to be provided between each V_DD/V_SSpair.

2

Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain

analog electrical characteristics will not be guaranteed to stay within the stated limits.

3

4

330 nF capacitance needs to be provided between each V_{DD_LV}/V_{SS_LV}supply pair.

470 nF capacitance needs to be provided between V_{DD_BV}and the nearest V_{SS_LV}(higher value may be needed

depending on external regulator characteristics). While the supply voltage ramps up, the slope on V_{DD_BV}should

be less than 0.9V_{DD_HV}in order to ensure the device does not enter regulator bypass mode.

5

6

7

8

100 nF capacitance needs to be provided between V_{DD_ADC}/V_{SS_ADC}pair.

Guaranteed by device validation

Minimum value of TV_DDmust be guaranteed until V_DDreaches 2.6 V (maximum value of V_PORH

)

When the FMPLL uses the frequency modulation with a modulation depth of 4ꢀ from the center spread frequency,

the maximum value of f_CPUis 66.56 MHz.

NOTE

RAM data retention is guaranteed with V

not below 1.08 V.

DD_LV

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

39

Electrical characteristics

4.5

Thermal characteristics

4.5.1

External ballast resistor recommendations

External ballast resistor on V

pin helps in reducing the overall power dissipation inside the device.

DD_BV

This resistor is required only when maximum power consumption exceeds the limit imposed by package

thermal characteristics.

As stated in Table 14 LQFP thermal characteristics, considering a thermal resistance of 144 LQFP as

48.3 °C/W, at ambient temperature T = 125 °C, the junction temperature T will cross 150 °C if the total

A

j

power dissipation is greater than (150 – 125)/48.3 = 517 mW. Therefore, the total device current I

DDMAX

at 125 °C/5.5 V must not exceed 94.1 mA (i.e., PD/VDD). Assuming an average I (V

) of

DD DD_HV

15–20 mA consumption typically during device RUN mode, the LV domain consumption I (V

)

DD DD_BV

is thus limited to I

– I (V

), i.e., 80 mA.

DDMAX

DD DD_HV

Therefore, respecting the maximum power allowed as explained in 4.5.2, Package thermal characteristics,

it is recommended to use this resistor only in the 125 °C/5.5 V operating corner as per the following

guidelines:

•

If I (V

) < 80 mA, then no resistor is required.

DD DD_BV

If 80 mA < I (V

) < 90 mA, then 4 Ω resistor can be used.

DD DD_BV

If I (V

) > 90 mA, then 8 Ω resistor can be used.

DD DD_BV

Using resistance in the range of 4–8 Ω, the gain will be around 10–20% of total consumption on V

.

DD_BV

For example, if 8 Ω resistor is used, then power consumption when I (V

) is 110 mA is equivalent

DD DD_BV

to power consumption when I (V

) is 90 mA (approximately) when resistor not used.

DD DD_BV

In order to ensure correct power up, the minimum V

to be guaranteed is 30 ms/V. If the supply ramp

DD_BV

is slower than this value, then LVDHV3B monitoring ballast supply V

pin gets triggered leading to

DD_BV

device reset. Until the supply reaches certain threshold, this low voltage detector (LVD) generates

destructive reset event in the system. This threshold depends on the maximum I (V

) possible

DD DD_BV

across the external resistor.

4.5.2

Package thermal characteristics

1

Table 14. LQFP thermal characteristics

Value

Min Typ Max

Symbol

C

Parameter

Conditions²

Pin count

Unit

R_θJACC D Thermal resistance,

junction-to-ambient natural

convection³

Single-layer board — 1s

100

144

176

100

144

176

—

64 °C/W

64

Four-layer board — 2s2p

49.7

48.3

47.3

MPC5607B Microcontroller Data Sheet, Rev. 9

40

NXP Semiconductors

Electrical characteristics

1

Table 14. LQFP thermal characteristics (continued)

Value

Unit

Symbol

C

Parameter

Conditions²

Pin count

Min Typ Max

R_θJBCC

Thermal resistance,

Single-layer board — 1s

100

144

176

100

144

176

100

144

176

100

144

176

—

36 °C/W

38

junction-to-board⁴

38

Four-layer board — 2s2p

Single-layer board — 1s

Four-layer board — 2s2p

33.6

33.4

23 °C/W

23

R_θJCCC

Thermal resistance,

junction-to-case⁵

23

19.8

19.2

18.8

1

2

3

Thermal characteristics are targets based on simulation.

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C.

Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board

meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as R_thJA

and R_thJMA

.

4

5

Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC

specification for the specified package. When Greek letters are not available, the symbols are typed as R_thJB

.

Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate

temperature is used for the case temperature. Reported value includes the thermal resistance of the interface

layer. When Greek letters are not available, the symbols are typed as R_thJC

.

4.5.3

Power considerations

The average chip-junction temperature, T , in degrees Celsius, may be calculated using Equation 1:

J

T = T + (P x R )

θJA

Eqn. 1

J

A

D

Where:

T is the ambient temperature in °C.

A

R

is the package junction-to-ambient thermal resistance, in °C/W.

θJA

P is the sum of P

and P (P = P

+ P ).

D

INT

I/O

D

INT I/O

P

is the product of I and V , expressed in watts. This is the chip internal power.

DD DD

INT

I/O

represents the power dissipation on input and output pins; user determined.

Most of the time for the applications, P < P

and may be neglected. On the other hand, P may be

I/O

INT

I/O

significant, if the device is configured to continuously drive external modules and/or memories.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

41

Electrical characteristics

An approximate relationship between P and T (if P is neglected) is given by:

D

J

I/O

P = K / (T + 273 °C)

Eqn. 2

Eqn. 3

D

J

Therefore, solving equations 1 and 2:

2

K = P x (T + 273 °C) + R

x P

D

A

θJA

Where:

K is a constant for the particular part, which may be determined from Equation 3 by measuring

P (at equilibrium) for a known T Using this value of K, the values of P and T may be

D

A.

D

J

obtained by solving equations 1 and 2 iteratively for any value of T .

A

4.6

I/O pad electrical characteristics

I/O pad types

4.6.1

The device provides four main I/O pad types depending on the associated alternate functions:

•

Slow pads—are the most common pads, providing a good compromise between transition time and

low electromagnetic emission.

•

Medium pads—provide transition fast enough for the serial communication channels with

controlled current to reduce electromagnetic emission.

•

Fast pads—provide maximum speed. These are used for improved Nexus debugging capability.

Input only pads—are associated with ADC channels and 32 kHz low power external crystal

oscillator providing low input leakage.

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of

reducing AC performance.

4.6.2

I/O input DC characteristics

Table 15 provides input DC electrical characteristics as described in Figure 6.

MPC5607B Microcontroller Data Sheet, Rev. 9

42

NXP Semiconductors

Electrical characteristics

V

IN

V

DD

V

IH

V

HYS

V

IL

PDIx = ‘1

(GPDI register of SIUL)

PDIx = ‘0’

Figure 6. I/O input DC electrical characteristics definition

Table 15. I/O input DC electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_IHSR P Input high level CMOS (Schmitt

Trigger)

—

0.65V_DD

—

V_DD+ 0.4

V

V_ILSR P Input low level CMOS (Schmitt

Trigger)

−0.4

—

0.35V_DD

—

V_HYSCC C Input hysteresis CMOS (Schmitt

Trigger)

0.1V_DD

I_LKGCC D Digital input leakage

No injection

on adjacent

T_A= −40 °C

T_A= 25 °C

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

—

2

200

300

500

1000

40

nA

D

P

—

5

—

12

70

—

2

W_FISR P Wakeup input filtered pulse

—

ns

2

W_NFISR P Wakeup input not filtered pulse

1000

—

1

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and

voltage.

2

4.6.3

I/O output DC characteristics

The following tables provide DC characteristics for bidirectional pads:

•

Table 16 provides weak pull figures. Both pull-up and pull-down resistances are supported.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

43

Electrical characteristics

•

Table 17 provides output driver characteristics for I/O pads when in SLOW configuration.

Table 18 provides output driver characteristics for I/O pads when in MEDIUM configuration.

Table 19 provides output driver characteristics for I/O pads when in FAST configuration.

Table 16. I/O pull-up/pull-down DC electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

|I_WPU| CC P Weak pull-up current

V_IN= V_IL, V_DD= 5.0 V 10ꢀ PAD3V5V = 0

10

—

150 µA

250

absolute value

C

PAD3V5V = 1²10

P

V_IN= V_IL, V_DD= 3.3 V 10ꢀ PAD3V5V = 1

10

150

|I_WPD| CC P Weak pull-down current

V_IN= V_IH, V_DD= 5.0 V 10ꢀ PAD3V5V = 0

PAD3V5V = 1

150 µA

250

absolute value

C

P

V_IN= V_IH, V_DD= 3.3 V 10ꢀ PAD3V5V = 1

150

1

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified.

The configuration PAD3V5 = 1 when V_DD= 5 V is only a transient configuration during power-up. All pads but

RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

2

Table 17. SLOW configuration output buffer electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_OHCC P Output high level

SLOW configuration

Push Pull I_OH= −2 mA,

0.8V_DD

—

V

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

(recommended)

C

I

_OH= −2 mA,

0.8V_DD

—

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 1²

I_OH= −1 mA,

V_DD− 0.8

V_DD= 3.3 V 10ꢀ,

PAD3V5V = 1

(recommended)

V_OLCC P Output low level

SLOW configuration

Push Pull I_OL= 2 mA,

—

0.1V_DD

V

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

(recommended)

C

I_OL= 2 mA,

—

0.1V_DD

0.5

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 1²

I_OL= 1 mA,

V_DD= 3.3 V 10ꢀ,

PAD3V5V = 1

(recommended)

1

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

MPC5607B Microcontroller Data Sheet, Rev. 9

44

NXP Semiconductors

Electrical characteristics

The configuration PAD3V5 = 1 when V_DD= 5 V is only a transient configuration during power-up. All pads but

2

RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 18. MEDIUM configuration output buffer electrical characteristics

Value

Symbol C

Parameter

Conditions¹

Unit

Min

Typ Max

V_OHCC C Output high level

MEDIUM configuration

Push Pull I_OH= −3.8 mA,

0.8V_DD

—

V

V_DD= 5.0 V 10ꢀ, PAD3V5V = 0

P

I_OH= −2 mA,

0.8V_DD

—

V_DD= 5.0 V 10ꢀ, PAD3V5V = 0

(recommended)

C

I

_OH= −1 mA,

0.8V_DD

—

V_DD= 5.0 V 10ꢀ, PAD3V5V = 1²

I

_OH= −1 mA,

_DD= 3.3 V 10ꢀ, PAD3V5V = 1

(recommended)

V_DD− 0.8

V

C

I

_OH= −100 µA,

0.8V_DD

—

V_DD= 5.0 V 10ꢀ, PAD3V5V = 0

V_OLCC C Output low level

Push Pull I_OL= 3.8 mA,

0.2V_DD

0.1V_DD

V

MEDIUM configuration

V_DD= 5.0 V 10ꢀ, PAD3V5V = 0

P

I_OL= 2 mA,

—

V_DD= 5.0 V 10ꢀ, PAD3V5V = 0

(recommended)

C

I_OL= 1 mA,

—

0.1V_DD

0.5

V_DD= 5.0 V 10ꢀ, PAD3V5V = 1²

I_OL= 1 mA,

V_DD= 3.3 V 10ꢀ, PAD3V5V = 1

(recommended)

C

I

_OL= 100 µA,

—

0.1V_DD

V_DD= 5.0 V 10ꢀ, PAD3V5V = 0

1

2

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

The configuration PAD3V5 = 1 when V_DD= 5 V is only a transient configuration during power-up. All pads but

RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

45

Electrical characteristics

Table 19. FAST configuration output buffer electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_OHCC P Output high level Push Pull I_OH= −14 mA,

FAST configuration V_DD= 5.0 V 10ꢀ,

0.8V_DD

—

V

PAD3V5V = 0

(recommended)

C

I

V

_OH= −7 mA,

_DD= 5.0 V 10ꢀ,

PAD3V5V = 1²

0.8V_DD

—

I

V

_OH= −11 mA,

_DD= 3.3 V 10ꢀ,

V_DD− 0.8

PAD3V5V = 1

(recommended)

V_OLCC P Output low level

FAST configuration

Push Pull I_OL= 14 mA,

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

—

0.1V_DD

V

(recommended)

C

I_OL= 7 mA,

—

0.1V_DD

0.5

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 1²

I_OL= 11 mA,

V_DD= 3.3 V 10ꢀ,

PAD3V5V = 1

(recommended)

1

2

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

The configuration PAD3V5 = 1 when V_DD= 5 V is only a transient configuration during power-up. All pads but

RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

4.6.4

Output pin transition times

Table 20. Output pin transition times

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

t_tr

CC D Output transition time output pin²C_L= 25 pF

SLOW configuration

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

—

50

ns

T

D

T

C_L= 50 pF

C_L= 100 pF

C_L= 25 pF

C_L= 50 pF

C_L= 100 pF

100

125

50

V_DD= 3.3 V 10ꢀ,

PAD3V5V = 1

100

125

D

MPC5607B Microcontroller Data Sheet, Rev. 9

46

NXP Semiconductors

Electrical characteristics

Table 20. Output pin transition times (continued)

Parameter

Conditions¹

Value

Unit

Min Typ Max

Symbol

C

t_tr

CC D Output transition time output pin²C_L= 25 pF

MEDIUM configuration

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

SIUL.PCRx.SRC = 1

—

10

20

40

12

25

40

4

ns

T

D

T

C_L= 50 pF

C_L= 100 pF

C_L= 25 pF

C_L= 50 pF

C_L= 100 pF

V_DD= 3.3 V 10ꢀ,

PAD3V5V = 1

SIUL.PCRx.SRC = 1

D

t_tr

CC D Output transition time output pin²C_L= 25 pF

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

ns

FAST configuration

C_L= 50 pF

6

C_L= 100 pF

C_L= 25 pF

C_L= 50 pF

C_L= 100 pF

12

4

V_DD= 3.3 V 10ꢀ,

PAD3V5V = 1

7

12

1

2

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

C_Lincludes device and package capacitances (C_PKG< 5 pF).

4.6.5

I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a

/V supply pair as described in Table 21.

V

DD SS

Table 22 provides I/O consumption figures.

In order to ensure device reliability, the average current of the I/O on a single segment should remain below

the I

maximum value.

AVGSEG

Table 21. I/O supply segments

Supply segment

Package

1

2

3

4

5

6

7

8

208

Equivalent to 176 LQFP segment pad distribution

MCKO

MDOn

/MSEO

MAPBGA¹

176 LQFP

144 LQFP

100 LQFP

pin7 –

pin27

pin28 –

pin57

pin59 –

pin85

pin86 –

pin123

pin124 –

pin150

pin151 –

pin6

—

pin20 –

pin49

pin51 –

pin99

pin100 –

pin122

pin 123 –

pin19

—

pin16 –

pin35

pin37 –

pin69

pin70 –

pin83

pin84 –

pin15

—

1

208 MAPBGA available only as development package for Nexus2+

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

47

Electrical characteristics

Table 22. I/O consumption

Conditions¹

Value

Symbol

C

Parameter

Unit

Min Typ Max

,2

I_SWTSLWCC D Dynamic I/O current for

SLOW configuration

C_L= 25 pF

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

—

20 mA

V_DD= 3.3 V 10ꢀ,

16

PAD3V5V = 1

2

I_SWTMEDCC D Dynamic I/O current for

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

29 mA

17

MEDIUM configuration

V_DD= 3.3 V 10ꢀ,

PAD3V5V = 1

2

I_SWTFSTCC D Dynamic I/O current for

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

110 mA

50

FAST configuration

V_DD= 3.3 V 10ꢀ,

PAD3V5V = 1

I_RMSSLWCC D Root mean square I/O

current for SLOW

C_L= 25 pF, 2 MHz

C_L= 25 pF, 4 MHz

C_L= 100 pF, 2 MHz

C_L= 25 pF, 2 MHz

C_L= 25 pF, 4 MHz

C_L= 100 pF, 2 MHz

C_L= 25 pF, 13 MHz

C_L= 25 pF, 40 MHz

C_L= 100 pF, 13 MHz

C_L= 25 pF, 13 MHz

C_L= 25 pF, 40 MHz

C_L= 100 pF, 13 MHz

C_L= 25 pF, 40 MHz

C_L= 25 pF, 64 MHz

C_L= 100 pF, 40 MHz

C_L= 25 pF, 40 MHz

C_L= 25 pF, 64 MHz

C_L= 100 pF, 40 MHz

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

—

2.3 mA

3.2

configuration

6.6

V_DD= 3.3 V 10ꢀ,

PAD3V5V = 1

1.6

2.3

4.7

I_RMSMEDCC D Root mean square I/O

current for MEDIUM

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

6.6 mA

13.4

18.3

5

configuration

V_DD= 3.3 V 10ꢀ,

PAD3V5V = 1

8.5

11

I_RMSFSTCC D Root mean square I/O

current for FAST

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

22 mA

33

configuration

56

V_DD= 3.3 V 10ꢀ,

PAD3V5V = 1

14

20

35

I_AVGSEGSR D Sum of all the static I/O

current within a supply

segment

V_DD= 5.0 V 10ꢀ, PAD3V5V = 0

V_DD= 3.3 V 10ꢀ, PAD3V5V = 1

70 mA

65

1

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to125 °C, unless otherwise specified

Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

2

Table 23 provides the weight of concurrent switching I/Os.

MPC5607B Microcontroller Data Sheet, Rev. 9

48

NXP Semiconductors

Electrical characteristics

Due to the dynamic current limitations, the sum of the weight of concurrent switching I/Os on a single

segment must not exceed 100% to ensure device functionality.

1

Table 23. I/O weight

176 LQFP

Weight 5 V Weight 3.3 V

SRC²= 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1

144/100 LQFP

Supply segment

Weight 5 V Weight 3.3 V

Pad

176

144

100

LQFP LQFP LQFP

6

4

PB[3]

PC[9]

PC[14]

PC[15]

PJ[4]

5ꢀ

4ꢀ

3ꢀ

2ꢀ

3ꢀ

4ꢀ

—

6ꢀ

5ꢀ

4ꢀ

3ꢀ

4ꢀ

5ꢀ

—

13ꢀ

12ꢀ

—

15ꢀ

—

4ꢀ

3ꢀ

4ꢀ

—

4ꢀ

3ꢀ

4ꢀ

—

18ꢀ

—

16ꢀ

—

4

—

4

1

PH[15]

PH[13]

PH[14]

PI[6]

—

PI[7]

—

PG[5]

PG[4]

PG[3]

PG[2]

PA[2]

—

10ꢀ

9ꢀ

8ꢀ

7ꢀ

6ꢀ

5ꢀ

—

12ꢀ

11ꢀ

10ꢀ

9ꢀ

8ꢀ

7ꢀ

6ꢀ

—

6ꢀ

—

5ꢀ

—

13ꢀ

—

12ꢀ

—

6ꢀ

—

5ꢀ

—

12ꢀ

—

11ꢀ

—

PE[0]

PA[1]

—

PE[1]

PE[8]

PE[9]

PE[10]

PA[0]

6ꢀ

—

6ꢀ

—

10ꢀ

—

9ꢀ

—

6ꢀ

—

5ꢀ

—

8ꢀ

—

7ꢀ

—

PE[11]

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

49

Electrical characteristics

Supply segment

1

Table 23. I/O weight (continued)

176 LQFP

144/100 LQFP

Weight 5 V Weight 3.3 V

SRC²= 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1

Weight 5 V

Weight 3.3 V

Pad

176

144

100

LQFP LQFP LQFP

2

1

—

1

PG[9]

PG[8]

PC[11]

PC[10]

PG[7]

PG[6]

PB[0]

9ꢀ

—

10ꢀ

11ꢀ

12ꢀ

11ꢀ

10ꢀ

9ꢀ

—

9ꢀ

—

10ꢀ

11ꢀ

12ꢀ

11ꢀ

10ꢀ

9ꢀ

—

9ꢀ

—

9ꢀ

—

9ꢀ

13ꢀ

—

12ꢀ

—

9ꢀ

13ꢀ

—

12ꢀ

—

1

9ꢀ

10ꢀ

9ꢀ

14ꢀ

—

12ꢀ

—

10ꢀ

9ꢀ

14ꢀ

—

12ꢀ

—

PB[1]

—

1

PF[9]

—

PF[8]

14ꢀ

15ꢀ

—

13ꢀ

—

14ꢀ

15ꢀ

—

13ꢀ

—

PF[12]

PC[6]

PC[7]

PF[10]

PF[11]

PA[15]

PF[13]

PA[14]

PA[4]

—

1

14ꢀ

—

12ꢀ

—

14ꢀ

—

12ꢀ

—

8ꢀ

12ꢀ

—

10ꢀ

—

8ꢀ

12ꢀ

—

10ꢀ

—

1

8ꢀ

11ꢀ

—

10ꢀ

—

8ꢀ

11ꢀ

—

10ꢀ

—

7ꢀ

9ꢀ

7ꢀ

9ꢀ

PA[13]

PA[12]

7ꢀ

10ꢀ

—

8ꢀ

9ꢀ

—

7ꢀ

10ꢀ

—

8ꢀ

9ꢀ

—

7ꢀ

8ꢀ

7ꢀ

8ꢀ

MPC5607B Microcontroller Data Sheet, Rev. 9

50

NXP Semiconductors

Electrical characteristics

1

Table 23. I/O weight (continued)

176 LQFP

144/100 LQFP

Weight 5 V Weight 3.3 V

SRC²= 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1

Supply segment

Weight 5 V

Weight 3.3 V

Pad

176

144

100

LQFP LQFP LQFP

3

2

PB[9]

PB[8]

PB[10]

PF[0]

PF[1]

PF[2]

PF[3]

PF[4]

PF[5]

PF[6]

PF[7]

PJ[3]

PJ[2]

PJ[1]

PJ[0]

PI[15]

PI[14]

PD[0]

PD[1]

PD[2]

PD[3]

PD[4]

PD[5]

PD[6]

PD[7]

1ꢀ

5ꢀ

6ꢀ

1ꢀ

—

1ꢀ

6ꢀ

7ꢀ

1ꢀ

—

1ꢀ

6ꢀ

7ꢀ

8ꢀ

9ꢀ

—

1ꢀ

7ꢀ

8ꢀ

9ꢀ

10ꢀ

11ꢀ

—

2

—

2

—

1ꢀ

2ꢀ

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

51

Electrical characteristics

Supply segment

1

Table 23. I/O weight (continued)

176 LQFP

144/100 LQFP

Weight 5 V Weight 3.3 V

SRC²= 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1

Weight 5 V

Weight 3.3 V

Pad

176

144

100

LQFP LQFP LQFP

4

2

PD[8]

PB[4]

1ꢀ

—

1ꢀ

—

1ꢀ

—

2ꢀ

—

PB[5]

1ꢀ

—

1ꢀ

—

PB[6]

1ꢀ

—

1ꢀ

—

PB[7]

1ꢀ

—

1ꢀ

—

PD[9]

PD[10]

PD[11]

PB[11]

PD[12]

PB[12]

PD[13]

PB[13]

PD[14]

PB[14]

PD[15]

PB[15]

PI[8]

1ꢀ

—

1ꢀ

—

1ꢀ

—

1ꢀ

—

1ꢀ

—

1ꢀ

—

4

—

2

—

2

1ꢀ

—

1ꢀ

—

11ꢀ

10ꢀ

9ꢀ

—

13ꢀ

12ꢀ

11ꢀ

10ꢀ

7ꢀ

—

15ꢀ

14ꢀ

13ꢀ

—

17ꢀ

16ꢀ

15ꢀ

—

2

—

2

—

PI[9]

—

PI[10]

PI[11]

PI[12]

PI[13]

PA[3]

—

11ꢀ

10ꢀ

6ꢀ

5ꢀ

4ꢀ

—

13ꢀ

12ꢀ

7ꢀ

6ꢀ

5ꢀ

4ꢀ

—

PG[13]

PG[12]

PH[0]

PH[1]

PH[2]

PH[3]

PG[1]

PG[0]

9ꢀ

13ꢀ

8ꢀ

7ꢀ

—

11ꢀ

7ꢀ

6ꢀ

—

14ꢀ

9ꢀ

8ꢀ

7ꢀ

—

13ꢀ

12ꢀ

8ꢀ

7ꢀ

6ꢀ

—

9ꢀ

6ꢀ

7ꢀ

5ꢀ

6ꢀ

5ꢀ

4ꢀ

5ꢀ

4ꢀ

5ꢀ

4ꢀ

5ꢀ

MPC5607B Microcontroller Data Sheet, Rev. 9

52

NXP Semiconductors

Electrical characteristics

1

Table 23. I/O weight (continued)

176 LQFP

144/100 LQFP

Weight 5 V Weight 3.3 V

SRC²= 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1

Supply segment

Weight 5 V

Weight 3.3 V

Pad

176

144

100

LQFP LQFP LQFP

5

3

—

3

PF[15]

PF[14]

PE[13]

PA[7]

4ꢀ

5ꢀ

6ꢀ

8ꢀ

7ꢀ

6ꢀ

5ꢀ

—

6ꢀ

—

4ꢀ

5ꢀ

6ꢀ

7ꢀ

8ꢀ

9ꢀ

8ꢀ

7ꢀ

6ꢀ

5ꢀ

—

5ꢀ

—

4ꢀ

5ꢀ

6ꢀ

8ꢀ

7ꢀ

—

6ꢀ

—

4ꢀ

5ꢀ

6ꢀ

7ꢀ

8ꢀ

9ꢀ

—

5ꢀ

—

PA[8]

—

PA[9]

—

PA[10]

PA[11]

PE[12]

PG[14]

PG[15]

PE[14]

PE[15]

PG[10]

PG[11]

PH[11]

PH[12]

PI[5]

—

3

—

11ꢀ

—

10ꢀ

—

11ꢀ

—

10ꢀ

—

11ꢀ

—

10ꢀ

—

11ꢀ

—

10ꢀ

—

11ꢀ

10ꢀ

—

9ꢀ

—

11ꢀ

—

9ꢀ

—

3

—

PI[4]

—

PC[3]

PC[2]

PA[5]

—

6ꢀ

5ꢀ

—

8ꢀ

7ꢀ

6ꢀ

5ꢀ

—

8ꢀ

—

7ꢀ

—

8ꢀ

—

7ꢀ

—

PA[6]

PH[10]

PC[1]

7ꢀ

19ꢀ

6ꢀ

13ꢀ

7ꢀ

19ꢀ

6ꢀ

13ꢀ

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

53

Electrical characteristics

Supply segment

1

Table 23. I/O weight (continued)

176 LQFP

144/100 LQFP

Weight 5 V Weight 3.3 V

SRC²= 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1

Weight 5 V

Weight 3.3 V

Pad

176

144

100

LQFP LQFP LQFP

6

4

PC[0]

PH[9]

PE[2]

PE[3]

PC[5]

PC[4]

PE[4]

PE[5]

PH[4]

PH[5]

PH[6]

PH[7]

PH[8]

PE[6]

PE[7]

PI[3]

6ꢀ

7ꢀ

8ꢀ

9ꢀ

8ꢀ

9ꢀ

—

7ꢀ

8ꢀ

—

7ꢀ

10ꢀ

—

8ꢀ

9ꢀ

8ꢀ

—

10ꢀ

11ꢀ

12ꢀ

—

8ꢀ

9ꢀ

10ꢀ

—

8ꢀ

11ꢀ

12ꢀ

13ꢀ

14ꢀ

—

9ꢀ

10ꢀ

11ꢀ

12ꢀ

—

9ꢀ

8ꢀ

10ꢀ

11ꢀ

12ꢀ

13ꢀ

14ꢀ

—

9ꢀ

8ꢀ

9ꢀ

10ꢀ

9ꢀ

—

4

10ꢀ

11ꢀ

—

12ꢀ

—

11ꢀ

—

15ꢀ

16ꢀ

—

13ꢀ

14ꢀ

—

4

—

4

PI[2]

—

PI[1]

—

PI[0]

—

PC[12]

PC[13]

PC[8]

PB[2]

12ꢀ

—

11ꢀ

—

12ꢀ

13ꢀ

18ꢀ

—

15ꢀ

16ꢀ

—

11ꢀ

10ꢀ

18ꢀ

16ꢀ

1

2

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

SRC: “Slew Rate Control” bit in SIU_PCRx

4.6.6

RESET electrical characteristics

The device implements a dedicated bidirectional RESET pin.

MPC5607B Microcontroller Data Sheet, Rev. 9

54

NXP Semiconductors

Electrical characteristics

V

DD

V

DDMIN

RESET

V

IH

V

IL

device reset forced by RESET

device start-up phase

Figure 7. Start-up reset requirements

V_RESET

hw_rst

‘1’

V

DD

V

IH

V

IL

‘0’

filtered by

lowpass filter

unknown reset

state

filtered by

hysteresis

filtered by

lowpass filter

device under hardware reset

W

FRST

W

NFRST

Figure 8. Noise filtering on reset signal

Table 24. Reset electrical characteristics

Value

Unit

Symbol

C

Parameter

Conditions¹

Min

Typ

Max

V_IH

SR P Input High Level CMOS

(Schmitt Trigger)

—

0.65V_DD

—

V_DD+ 0.4

V

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

55

Electrical characteristics

Table 24. Reset electrical characteristics (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_IL

SR P Input low Level CMOS

(Schmitt Trigger)

—

−0.4

—

0.35V_DD

V

V_HYSCC C Input hysteresis CMOS

(Schmitt Trigger)

0.1V_DD

—

V_OL

CC P Output low level

Push Pull, I_OL= 2 mA,

V_DD= 5.0 V 10ꢀ, PAD3V5V = 0

(recommended)

0.1V_DD

Push Pull, I_OL= 1 mA,

—

0.1V_DD

0.5

V_DD= 5.0 V 10ꢀ, PAD3V5V = 1²

Push Pull, I_OL= 1 mA,

V_DD= 3.3 V 10ꢀ, PAD3V5V = 1

(recommended)

t_tr

CC D Output transition time output C_L= 25 pF,

pin³MEDIUM configuration

V_DD= 5.0 V 10ꢀ, PAD3V5V = 0

—

10

20

40

12

25

40

ns

C_L= 50 pF,

V_DD= 5.0 V 10ꢀ, PAD3V5V = 0

C_L= 100 pF,

V_DD= 5.0 V 10ꢀ, PAD3V5V = 0

C_L= 25 pF,

V_DD= 3.3 V 10ꢀ, PAD3V5V = 1

C_L= 50 pF,

V_DD= 3.3 V 10ꢀ, PAD3V5V = 1

C_L= 100 pF,

V_DD= 3.3 V 10ꢀ, PAD3V5V = 1

W_FRSTSR P RESET input filtered pulse

—

1000

10

—

40

—

ns

µA

W_NFRSTSR P RESET input not filtered pulse

|I_WPU

|

CC P Weak pull-up current absolute V_DD= 3.3 V 10ꢀ, PAD3V5V = 1

value

150

250

D

P

V_DD= 5.0 V 10ꢀ, PAD3V5V = 0

10

V

_DD= 5.0 V 10ꢀ, PAD3V5V = 1⁴

10

1

2

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of

the device reference manual).

3

4

C_Lincludes device and package capacitance (C_PKG< 5 pF).

The configuration PAD3V5 = 1 when V_DD= 5 V is only transient configuration during power-up. All pads but RESET

and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

MPC5607B Microcontroller Data Sheet, Rev. 9

56

NXP Semiconductors

Electrical characteristics

4.7

Power management electrical characteristics

Voltage regulator electrical characteristics

4.7.1

The device implements an internal voltage regulator to generate the low voltage core supply V

from

DD_LV

the high voltage ballast supply V

. The regulator itself is supplied by the common I/O supply V

.

DD_BV

DD

The following supplies are involved:

•

HV: High voltage external power supply for voltage regulator module. This must be provided

externally through V power pin.

DD

BV: High voltage external power supply for internal ballast module. This must be provided

externally through V

power pin. Voltage values should be aligned with V

.

DD_BV

DD

LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated

by the internal voltage regulator but provided outside to connect stability capacitor. It is further

split into four main domains to ensure noise isolation between critical LV modules within the

device:

— LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL

through double bonding.

— LV_CFLA: Low voltage supply for code flash module. It is supplied with dedicated ballast and

shorted to LV_COR through double bonding.

— LV_DFLA: Low voltage supply for data flash module. It is supplied with dedicated ballast and

shorted to LV_COR through double bonding.

— LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

57

Electrical characteristics

C

(LV_COR/LV_CFLA)

REG2

V

DD

V

DD_LV

SS_LV

V

DD_BV

DD_LVn

SS_LVn

V

REF

V

DD_BV

V

DD_LV

DEVICE

V

Voltage Regulator

I

V

SS_LV

V

DD

SS_LV

DD_LV

SS

DEVICE

C

DEC2

REG3

(LV_COR/LV_PLL)

(supply/IO decoupling)

Figure 9. Voltage regulator capacitance connection

The internal voltage regulator requires external capacitance (C

) to be connected to the device in order

REGn

to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as

near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board

to less than 5 nH.

Each decoupling capacitor must be placed between each of the three V

/V

supply pairs to

DD_LV SS_LV

ensure stable voltage (see 4.4, Recommended operating conditions).

Table 25. Voltage regulator electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

C_REGn

R_REG

SR — Internal voltage regulator external

capacitance

—

200

—

500

nF

Ω

SR — Stability capacitor equivalent serial

resistance

Range:

—

0.2

—

10 kHz to 20 MHz

C_DEC1

SR — Decoupling capacitance²ballast

V_{DD_BV}/V_{SS_LV}pair:

V_{DD_BV}= 4.5 V to 5.5 V

100³

400

470⁴

nF

V

_{DD_BV}/V_{SS_LV}pair:

_{DD_BV}= 3 V to 3.6 V

—

MPC5607B Microcontroller Data Sheet, Rev. 9

58

NXP Semiconductors

Electrical characteristics

Table 25. Voltage regulator electrical characteristics (continued)

Value

Unit

Symbol

C

Parameter

Conditions¹

Min

Typ

Max

C_DEC2

V_MREG

SR — Decoupling capacitance regulator

supply

V_DD/V_SSpair

10

100

—

nF

V

CC T Main regulator output voltage

P

Before exiting from reset

—

1.16

—

1.32

1.28

—

After trimming

—

I_MREG

SR — Main regulator current provided to

V_{DD_LV}domain

150

mA

I_MREGINTCC D Main regulator module current

consumption

I_MREG= 200 mA

I_MREG= 0 mA

—

2

1

V_LPREG

I_LPREG

CC P Low-power regulator output voltage After trimming

1.16

—

1.28

—

15

V

SR — Low-power regulator current provided

to V_{DD_LV}domain

—

mA

I_LPREGINTCC D Low-power regulator module current I_LPREG= 15 mA;

—

5

600

—

µA

consumption

T_A= 55 °C

—

I_LPREG= 0 mA;

T_A= 55 °C

V_ULPREGCC P Ultra low power regulator output

voltage

After trimming

1.16

—

1.28

—

2

—

V

I_ULPREG

SR — Ultra low power regulator current

provided to V_{DD_LV}domain

—

5

mA

µA

I_ULPREGINTCC D Ultra low power regulator module

current consumption

I_ULPREG= 5 mA;

T_A= 55 °C

—

100

—

I_ULPREG= 0 mA;

T_A= 55 °C

—

I_{DD_BV}

CC D In-rush average current on V_{DD_BV}

during power-up⁵

—

300⁶mA

1

2

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

This capacitance value is driven by the constraints of the external voltage regulator supplying the V_{DD_BV}voltage. A

typical value is in the range of 470 nF.

3

4

This value is acceptable to guarantee operation from 4.5 V to 5.5 V

External regulator and capacitance circuitry must be capable of providing I_{DD_BV}while maintaining supply V_{DD_BV}in

operating range.

5

6

In-rush average current is seen only for short time during power-up and on standby exit (maximum 20 µs, depending

on external capacitances to be loaded).

The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must

be sized accordingly. Refer to I_MREGvalue for minimum amount of current to be provided in cc.

4.7.2

Low voltage detector electrical characteristics

The device implements a power-on reset (POR) module to ensure correct power-up initialization, as well

as five low voltage detectors (LVDs) to monitor the V and the V

voltage while device is supplied:

DD

DD_LV

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

59

Electrical characteristics

•

POR monitors V during the power-up phase to ensure device is maintained in a safe reset state

DD

(refer to RGM Destructive Event Status (RGM_DES) Register flag F_POR in device reference

manual)

•

LVDHV3 monitors V to ensure device reset below minimum functional supply (refer to RGM

Destructive Event Status (RGM_DES) Register flag F_LVD27 in device reference manual)

DD

LVDHV3B monitors V

to ensure device reset below minimum functional supply (refer to

DD_BV

RGM Destructive Event Status (RGM_DES) Register flag F_LVD27_VREG in device reference

manual)

•

LVDHV5 monitors V when application uses device in the 5.0 V ± 10% range (refer to RGM

Functional Event Status (RGM_FES) Register flag F_LVD45 in device reference manual)

DD

LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status (RGM_DES)

Register flag F_LVD12_PD1 in device reference manual)

LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status (RGM_DES)

Register flag F_LVD12_PD0 in device reference manual)

NOTE

When enabled, power domain No. 2 is monitored through LVDLVBKP.

V

DD

V

LVDHVxH

LVDHVxL

RESET

Figure 10. Low voltage detector vs reset

MPC5607B Microcontroller Data Sheet, Rev. 9

60

NXP Semiconductors

Electrical characteristics

Table 26. Low voltage detector electrical characteristics

Value

Unit

Symbol

C

Parameter

Conditions¹

Min Typ Max

V_PORUP

V_PORH

SR P Supply for functional POR module

CC P Power-on reset threshold

T_A= 25 °C,

after trimming

1.0

1.5

—

5.5

2.6

V

V_LVDHV3HCC T LVDHV3 low voltage detector high threshold

V_LVDHV3LCC P LVDHV3 low voltage detector low threshold

2.95

2.9

2.6

—

V_LVDHV3BHCC P LVDHV3B low voltage detector high threshold

V_LVDHV3BLCC P LVDHV3B low voltage detector low threshold

V_LVDHV5HCC T LVDHV5 low voltage detector high threshold

2.95

2.9

2.6

—

4.5

V_LVDHV5L

CC P LVDHV5 low voltage detector low threshold

3.8

1.08

4.4

V_LVDLVCORLCC P LVDLVCOR low voltage detector low threshold

V_LVDLVBKPLCC P LVDLVBKP low voltage detector low threshold

1.16

1

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

4.8

Power consumption

Table 27 provides DC electrical characteristics for significant application modes. These values are

indicative values; actual consumption depends on the application.

Table 27. Power consumption on VDD_BV and VDD_HV

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

2

I_DDMAXCC D RUN mode maximum average

current

—

115 140³mA

4

I_DDRUNCC T RUN mode typical average

f_CPU= 8 MHz

—

12

27

43

56

70

10

17

—

mA

current⁵

T

f_CPU= 16 MHz

f_CPU= 32 MHz

T

—

P

f

_CPU= 48 MHz

100

125

P

f_CPU= 64 MHz

I_DDHALTCC C HALT mode current⁶

Slow internal RC

oscillator (128 kHz)

running

T_A= 25 °C

18 mA

28

P

T_A= 125 °C

I_DDSTOPCC P STOP mode current⁷

Slow internal RC

oscillator (128 kHz)

running

T_A= 25 °C

T_A= 55 °C

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

—

350 900⁸µA

D

P

750

2

—

7

mA

4

10

14

7

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

61

Electrical characteristics

Table 27. Power consumption on VDD_BV and VDD_HV (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

I_DDSTDBY2CC P STANDBY2 mode current⁹

Slow internal RC

oscillator (128 kHz)

running

T_A= 25 °C

T_A= 55 °C

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

T_A= 25 °C

T_A= 55 °C

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

—

30

75

100 µA

—

D

180 700

315 1000

560 1700

D

P

I_DDSTDBY1CC T STANDBY1 mode current¹⁰

Slow internal RC

oscillator (128 kHz)

running

20

45

60

—

µA

D

100 350

165 500

280 900

1

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

2

Running consumption does not include I/Os toggling which is highly dependent on the application. The given value

is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify

operation ongoing on data flash. Notice that this value can be significantly reduced by application: switch off not

used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used

functions, use low power mode when possible.

3

Higher current may be sunk by device during power-up and standby exit. Please refer to in-rush average current in

Table 25.

4

5

RUN current measured with typical application with accesses on both Flash and RAM.

Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and

LIN in loop back mode, DSPI as Master, PLL as system clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and

running at max frequency, periodic SW/WDG timer reset enabled.

6

Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz on. 10 MHz XTAL clock.

FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex:

instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 to 9 clocks gated. eMIOS: instance:

0 ON (16 channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI:

instance: 0 (clocked but no communication), instance: 1 to 5 clocks gated. RTC/API ON. PIT ON. STM ON. ADC1

OFF. ADC0 ON but no conversion except two analog watchdogs.

7

8

Only for the “P” classification: No clock, FIRC 16 MHz off, SIRC 128 kHz on, PLL off, HPvreg off,

ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode.

When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main

regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction

temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the

maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce

to the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA.

9

Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum

consumption, all possible modules switched off.

¹⁰ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules

switched off.

MPC5607B Microcontroller Data Sheet, Rev. 9

62

NXP Semiconductors

Electrical characteristics

4.9

Flash memory electrical characteristics

Program/erase characteristics

4.9.1

Table 28 shows the program and erase characteristics.

Table 28. Program and erase specifications

Value

Symbol

C

Parameter

Conditions

Unit

Initial

Min Typ¹

Max³

max²

t_dwprogramCC C Double word (64 bits) program time⁴

Code Flash

Data Flash

Code Flash

Data Flash

Code Flash

Data Flash

Code Flash

Data Flash

—

18

22

50

500

µs

t_16Kpperase

t_32Kpperase

t_128Kpperase

16 KB block preprogram and erase time

32 KB block preprogram and erase time

128 KB block preprogram and erase time

200 500 5000 ms

300

300 600 5000 ms

400

600 1300 7500 ms

800

t_esus

D Erase Suspend Latency

—

30

—

30

—

µs

t_ESRT

C Erase Suspend Request Rate⁵

Code Flash 20

Data Flash 10

ms

1

Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to

change pending device characterization.

2

3

Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

The maximum program and erase times occur after the specified number of program/erase cycles. These maximum

values are characterized but not guaranteed.

4

5

Actual hardware programming times. This does not include software overhead.

Time between erase suspend resume and the next erase suspend request

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

63

Electrical characteristics

Table 29. Flash module life

Conditions

Value

Symbol

C

Parameter

Unit

Min

Typ

Max

P/E

CC C Number of program/erase

cycles per block for 16 KB

blocks over the operating

temperature range (T_J)

—

100,000

—

cycles

P/E

CC C Number of program/erase

cycles per block for 32 KB

blocks over the operating

temperature range (T_J)

10,000 100,000

—

cycles

CC C Number of program/erase

cycles per block for 128 KB

blocks over the operating

temperature range (T_J)

1,000

100,000

Retention CC C Minimum data retention at

85 °C average ambient

Blocks with

0–1,000 P/E cycles

20

10

—

years

temperature¹

Blocks with

1,001–10,000 P/E

cycles

Blocks with

5

—

years

10,001–100,000 P/E

cycles

1

Ambient temperature averaged over duration of application, not to exceed recommended product operating

temperature range.

ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability

results. Some units will experience single bit corrections throughout the life of the product with no impact

to product reliability.

Table 30. Flash read access timing

Symbol

f_READ

C

Parameter

Conditions¹

Max

Unit

CC P Maximum frequency for Flash reading

2 wait states

1 wait state

0 wait states

64

40

20

MHz

C

1

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

4.9.2

Flash power supply DC characteristics

Table 31 shows the power supply DC characteristics on external supply.

MPC5607B Microcontroller Data Sheet, Rev. 9

64

NXP Semiconductors

Electrical characteristics

Table 31. Flash power supply DC electrical characteristics

Conditions¹

Value

Unit

Symbol

Parameter

Min Typ Max

I_CFREADCC Sum of the current consumption on Flash module read

Code Flash

Data Flash

Code Flash

Data Flash

—

33 mA

33

V_{DD_HV}and V_{DD_BV}on read access f_CPU= 64 MHz

I_DFREAD

I_CFMODCC Sum of the current consumption on Program/Erase

52 mA

33

V_{DD_HV}and V_{DD_BV}on matrix

modification (program/erase)

on-going while reading

Flash registers

I_DFMOD

f_CPU= 64 MHz

I_CFLPWCC Sum of the current consumption on

—

Code Flash

Data Flash

—

1.1 mA

900 µA

V_{DD_HV}and V_{DD_BV}during Flash low

I_DFLPW

power mode

I_CFPWDCC Sum of the current consumption on

—

Code Flash

Data Flash

—

150 µA

150

V_{DD_HV}and V_{DD_BV}during Flash

I_DFPWD

power down mode

1

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= –40 to 125 °C, unless otherwise specified

4.9.3

Start-up/Switch-off timings

Table 32. Start-up time/Switch-off time

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

t_FLARSTEXITCC T Delay for Flash module to exit reset mode

—

125 µs

0.5

t_FLALPEXIT

t_FLAPDEXIT

CC T Delay for Flash module to exit low-power mode

CC T Delay for Flash module to exit power-down mode

30

t_FLALPENTRYCC T Delay for Flash module to enter low-power mode

t_FLAPDENTRYCC T Delay for Flash module to enter power-down mode

0.5

1.5

1

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

4.10 Electromagnetic compatibility (EMC) characteristics

Susceptibility tests are performed on a sample basis during product characterization.

4.10.1 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application

environment and simplified MCU software. It should be noted that good EMC performance is highly

dependent on the user application and the software in particular.

Therefore it is recommended that the user apply EMC software optimization and prequalification tests in

relation with the EMC level requested for the application.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

65

Electrical characteristics

•

Software recommendations − The software flowchart must include the management of runaway

conditions such as:

— Corrupted program counter

— Unexpected reset

— Critical data corruption (control registers...)

•

Prequalification trials − Most of the common failures (unexpected reset and program counter

corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins

for 1 second.

To complete these trials, ESD stress can be applied directly on the device. When unexpected

behavior is detected, the software can be hardened to prevent unrecoverable errors occurring.

4.10.2 Electromagnetic interference (EMI)

The product is monitored in terms of emission based on a typical application. This emission test conforms

to the IEC61967-1 standard, which specifies the general conditions for EMI measurements.

1,2

Table 33. EMI radiated emission measurement

Value

Symbol

C

Parameter

Conditions

Unit

Min Typ Max

—

SR — Scan range

—

0.150

—

1000 MHz

f_CPU

SR — Operating frequency

—

64

1.28

—

MHz

V

V_{DD_LV}SR — LV operating voltages

S_EMICC T Peak level

—

V_DD= 5 V, T_A= 25 °C, No PLL frequency

—

18 dBµV

LQFP144 package

Test conforming to IEC

61967-2,

modulation

2ꢀ PLL frequency

modulation

—

14 dBµV

f_OSC= 8 MHz/f_CPU

64 MHz

=

1

2

EMI testing and I/O port waveforms per IEC 61967-1, -2, -4

For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your

local marketing representative.

4.10.3 Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed

in order to determine its performance in terms of electrical sensitivity.

4.10.3.1 Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of

each sample according to each pin combination. The sample size depends on the number of supply pins in

the device (3 parts×(n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard.

MPC5607B Microcontroller Data Sheet, Rev. 9

66

NXP Semiconductors

Electrical characteristics

1,2

Table 34. ESD absolute maximum ratings

Symbol

Ratings

Conditions

T_A= 25 °C

Class

Max value³

Unit

V_ESD(HBM)Electrostatic discharge voltage

(Human Body Model)

H1C

2000

V

conforming to AEC-Q100-002

V_ESD(MM)Electrostatic discharge voltage

(Machine Model)

T_A= 25 °C

conforming to AEC-Q100-003

M2

200

V_ESD(CDM)Electrostatic discharge voltage

(Charged Device Model)

T_A= 25 °C

conforming to AEC-Q100-011

C3A

500

750 (corners)

1

2

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated

Circuits.

A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification requirements. Complete DC parametric and functional testing shall be performed per applicable

device specification at room temperature followed by hot temperature, unless specified otherwise in the device

specification.

3

Data based on characterization results, not tested in production

4.10.3.2 Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up performance:

•

A supply overvoltage is applied to each power supply pin.

A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with the EIA/JESD 78 IC latch-up standard.

Table 35. Latch-up results

Symbol

Parameter

Conditions

T_A= 125 °C

Class

LU

Static latch-up class

II level A

conforming to JESD 78

4.11 Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics

The device provides an oscillator/resonator driver. Figure 11 describes a simple model of the internal

oscillator driver and provides an example of a connection for an oscillator or a resonator.

Table 36 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

67

Electrical characteristics

EXTAL

C1

C2

EXTAL

XTAL

DEVICE

V

DD

I

R

EXTAL

XTAL

DEVICE

XTAL

DEVICE

Notes:

1. XTAL/EXTAL must not be directly used to drive external circuits

2. A series resistor may be required, according to crystal oscillator supplier recommendations.

Figure 11. Crystal oscillator and resonator connection scheme

Table 36. Crystal description

Shunt

Crystal

equivalent

series

resistance

ESR Ω

Crystal

motional

capacitance

(C_m) fF

Crystal

motional

inductance

(L_m) mH

Load on

xtalin/xtalout

C1 = C2

capacitance

between

xtalout

Nominal

frequency

(MHz)

NDK crystal

reference

(pF)¹

and xtalin

C0²(pF)

4

NX8045GB

NX5032GA

300

150

120

2.68

2.46

2.93

3.11

3.90

591.0

160.7

86.6

21

17

15

10

2.93

3.01

2.91

2.93

3.00

8

10

12

16

56.5

25.3

1

2

The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing

includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.

The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,

package, etc.).

MPC5607B Microcontroller Data Sheet, Rev. 9

68

NXP Semiconductors

Electrical characteristics

S_MTRANS bit (ME_GS register)

1

0

V

XTAL

1/f

MXOSC

V

MXOSC

90ꢀ

10ꢀ

V

MXOSCOP

T

valid internal clock

MXOSCSU

Figure 12. Fast external crystal oscillator (4 to 16 MHz) timing diagram

Table 37. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

f_FXOSC

SR — Fast external crystal

oscillator frequency

—

4.0

—

16.0

MHz

g_mFXOSCCC C Fast external crystal

oscillator

V_DD= 3.3 V 10ꢀ,

PAD3V5V = 1

OSCILLATOR_MARGIN = 0

2.2

2.0

2.7

2.5

—

8.2

7.4

9.7

9.2

mA/V

transconductance

CC P

CC C

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

OSCILLATOR_MARGIN = 0

V_DD= 3.3 V 10ꢀ,

PAD3V5V = 1

OSCILLATOR_MARGIN = 1

V_DD= 5.0 V 10ꢀ,

PAD3V5V = 0

OSCILLATOR_MARGIN = 1

V_FXOSC

CC T Oscillation amplitude at

EXTAL

f_OSC= 4 MHz,

OSCILLATOR_MARGIN = 0

1.3

—

V

f

_OSC= 16 MHz,

OSCILLATOR_MARGIN = 1

V_FXOSCOPCC C Oscillation operating point

—

0.95

2

—

3

V

2

I_FXOSC

CC T Fast external crystal

oscillator consumption

mA

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

69

Electrical characteristics

Table 37. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

t_FXOSCSUCC T Fast external crystal

oscillator start-up time

f_OSC= 4 MHz,

OSCILLATOR_MARGIN = 0

—

6

ms

f

_OSC= 16 MHz,

—

1.8

OSCILLATOR_MARGIN = 1

V_IH

V_IL

SR P Input high level CMOS

(Schmitt Trigger)

Oscillator bypass mode

0.65V_DD

−0.4

V_DD+ 0.4

0.35V_DD

V

SR P Input low level CMOS

(Schmitt Trigger)

Oscillator bypass mode

1

2

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified.

Stated values take into account only analog module consumption but not the digital contributor (clock tree and

enabled peripherals).

4.12 Slow external crystal oscillator (32 kHz) electrical characteristics

The device provides a low power oscillator/resonator driver.

OSC32K_EXTAL

C1

C2

R

P

OSC32K_XTAL

DEVICE

Note: OSC32_XTAL/OSC32_EXTAL must not be directly used to drive external circuits

Figure 13. Crystal oscillator and resonator connection scheme

MPC5607B Microcontroller Data Sheet, Rev. 9

70

NXP Semiconductors

Electrical characteristics

l

C0

Crystal

R_m

L_m

C_m

C1

C2

C1

C2

Figure 14. Equivalent circuit of a quartz crystal

1

Table 38. Crystal motional characteristics

Value

Typ

Symbol

Parameter

Conditions

Unit

Min

Max

L_m

Motional inductance

Motional capacitance

—

18

11.796

—

28

KH

fF

C_m

2

C1/C2 Load capacitance at OSC32K_XTAL and

OSC32K_EXTAL with respect to ground²

—

pF

AC coupled at C0 = 2.85 pF⁴

AC coupled at C0 = 4.9 pF⁴

AC coupled at C0 = 7.0 pF⁴

AC coupled at C0 = 9.0 pF⁴

—

65

50

35

30

kΩ

3

R_m

Motional resistance

1

2

The crystal used is Epson Toyocom MC306.

This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to

ground. It includes all the parasitics due to board traces, crystal and package.

3

4

Maximum ESR (R_m) of the crystal is 50 kΩ

C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

71

Electrical characteristics

OSCON bit (OSC_CTL register)

1

0

V

OSC32K_XTAL

1/f

LPXOSC32K

V

LPXOSC32K

90ꢀ

10ꢀ

T

valid internal clock

LPXOSC32KSU

Figure 15. Slow external crystal oscillator (32 kHz) timing diagram

Table 39. Slow external crystal oscillator (32 kHz) electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

f_SXOSC

SR — Slow external crystal oscillator

frequency

—

32

32.768

40

kHz

V_SXOSC

CC T Oscillation amplitude

—

2.1

2.5

—

V

I_SXOSCBIASCC T Oscillation bias current

µA

I_SXOSC

CC T Slow external crystal oscillator

consumption

—

8

t_SXOSCSUCC T Slow external crystal oscillator

start-up time

—

2²

s

1

2

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified. Values are specified for no

neighbor GPIO pin activity. If oscillator is enabled (OSC32K_XTAL and OSC32K_EXTAL pins), neighboring pins

should not toggle.

Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.

4.13 FMPLL electrical characteristics

The device provides a frequency modulated phase locked loop (FMPLL) module to generate a fast system

clock from the main oscillator driver.

Table 40. FMPLL electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

f_PLLINSR — FMPLL reference clock²

—

4

—

64

MHz

MPC5607B Microcontroller Data Sheet, Rev. 9

72

NXP Semiconductors

Electrical characteristics

Table 40. FMPLL electrical characteristics (continued)

Value

Unit

Symbol

C

Parameter

Conditions¹

Min

Typ

Max

Δ_PLLINSR — FMPLL reference clock duty

—

40

—

60

ꢀ

cycle²

f_PLLOUTCC P FMPLL output clock frequency

—

16

—

64

MHz

3

f_VCO

CC P VCO frequency without

frequency modulation

256

512 MHz

P VCO frequency with frequency

modulation

—

245.76

—

532.48

f_CPUSR — System clock frequency

f_FREECC P Free-running frequency

t_LOCKCC P FMPLL lock time

—

40

—

64

MHz

20

150 MHz

Stable oscillator (f_PLLIN= 16 MHz)

f_sysmaximum

100

4

µs

ꢀ

Δt_STJITCC — FMPLL short term jitter⁴

Δt_LTJITCC — FMPLL long term jitter

–4

—

f_PLLCLKat 64 MHz, 4000 cycles

T_A= 25 °C

10

4

ns

I_PLL

CC C FMPLL consumption

mA

1

2

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in

functional mode. When bypass mode is used, oscillator input clock should verify f_PLLINand Δ_PLLIN

Frequency modulation is considered 4ꢀ.

.

3

4

Short term jitter is measured on the clock rising edge at cycle n and n+4.

4.14 Fast internal RC oscillator (16 MHz) electrical characteristics

The device provides a 16 MHz main internal RC oscillator. This is used as the default clock at the power-up

of the device.

Table 41. Fast internal RC oscillator (16 MHz) electrical characteristics

Value

Symbol

f_FIRC

2,

C

Parameter

Conditions¹

Unit

Min

Typ

Max

CC P Fast internal RC oscillator high T_A= 25 °C, trimmed

frequency

—

12

—

16

—

20

MHz

SR —

—

I_FIRCRUN

CC T Fast internal RC oscillator high T_A= 25 °C, trimmed

—

200

µA

frequency current in running

mode

I_FIRCPWDCC D Fast internal RC oscillator high T_A= 25 °C

frequency current in power

—

10

down mode

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

73

Electrical characteristics

Table 41. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)

Value

Typ

Symbol

C

Parameter

Conditions¹

Unit

Min

Max

I_FIRCSTOPCC T Fast internal RC oscillator high T_A= 25 °C sysclk = off

frequency and system clock

—

500

600

700

900

1250

1.1

—

2.0

µA

sysclk = 2 MHz

current in stop mode

sysclk = 4 MHz

sysclk = 8 MHz

sysclk = 16 MHz

t_FIRCSUCC C Fast internal RC oscillator

start-up time

V_DD= 5.0 V 10ꢀ

µs

ꢀ

Δ_FIRCPRECC C Fast internal RC oscillator

precision after software

T_A= 25 °C

−1

—

1

trimming of f_FIRC

Δ_FIRCTRIMCC C Fast internal RC oscillator

—

1.6

—

ꢀ

trimming step

Δ_FIRCVARCC C Fast internal RC oscillator

variation over temperature and

supply with respect to f_FIRCat

T_A= 25 °C in high-frequency

configuration

—

−5

5

1

2

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is

ON.

4.15 Slow internal RC oscillator (128 kHz) electrical characteristics

The device provides a 128 kHz low power internal RC oscillator. This can be used as the reference clock

for the RTC module.

Table 42. Slow internal RC oscillator (128 kHz) electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

f_SIRC

CC P Slow internal RC oscillator low

T_A= 25 °C, trimmed

—

100

—

128

—

150

5

kHz

frequency

SR —

2,

I_SIRC

CC C Slow internal RC oscillator low

frequency current

T_A= 25 °C, trimmed

—

µA

µs

ꢀ

t_SIRCSU

CC P Slow internal RC oscillator start-up T_A= 25 °C, V_DD= 5.0 V 10ꢀ

time

—

−2

—

8

12

2

Δ_SIRCPRECC C Slow internal RC oscillator precision T_A= 25 °C

—

after software trimming of f_SIRC

Δ_SIRCTRIMCC C Slow internal RC oscillator trimming

—

2.7

—

step

MPC5607B Microcontroller Data Sheet, Rev. 9

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NXP Semiconductors

Electrical characteristics

Table 42. Slow internal RC oscillator (128 kHz) electrical characteristics (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

Δ_SIRCVARCC C Slow internal RC oscillator variation High frequency configuration

in temperature and supply with

−10

—

10

ꢀ

respect to f_SIRCat T_A= 55 °C in high

frequency configuration

1

2

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified

This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is

ON.

4.16 ADC electrical characteristics

4.16.1 Introduction

The device provides two Successive Approximation Register (SAR) analog-to-digital converters (10-bit

and 12-bit).

MPC5607B Microcontroller Data Sheet, Rev. 9

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75

Electrical characteristics

Offset Error (E )

Gain Error (E )

G

O

1023

1022

1021

1020

1019

1 LSB ideal = V

/ 1024

DD_ADC

1018

(2)

code out

7

(1)

6

5

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(5)

4

3

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

(4)

(3)

2

1

1 LSB (ideal)

0

1

2

3

4

5

6

7

1017 1018 1019 1020 1021 1022 1023

(LSB

V

)

ideal

in(A)

Offset Error (E )

O

Figure 16. ADC_0 characteristic and error definitions

4.16.2 Input impedance and ADC accuracy

In the following analysis, the input circuit corresponding to the precise channels is considered.

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC

impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can

be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to

attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase,

when the analog signal source is a high-impedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple

RC filter). The RC filtering may be limited according to the value of source impedance of the transducer

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76

NXP Semiconductors

Electrical characteristics

or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking

into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input

impedance of the ADC itself.

In fact a current sink contributor is represented by the charge sharing effects with the sampling

capacitance: being C and C substantially two switched capacitances, with a frequency equal to the

S

p2

conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a

conversion rate of 1 MHz, with C +C equal to 3 pF, a resistance of 330 kΩ is obtained (R = 1 /

S

p2

EQ

(f × (C +C )), where f represents the conversion rate at the considered channel). To minimize the error

c

S

p2

c

induced by the voltage partitioning between this resistance (sampled voltage on C +C ) and the sum of

S

p2

R + R , the external circuit must be designed to respect the Equation 4:

S

F

Eqn. 4

R + R

S

F

1

2

V • -------------------- < -- LSB

A

R

EQ

Equation 4 generates a constraint for external network design, in particular on a resistive path.

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

V

DD

Channel

Sampling

Selection

Source

Filter

Current Limiter

R

AD

S

F

L

SW1

V

C

S

A

F

P1

P2

R

Source Impedance

Filter Resistance

Filter Capacitance

Current Limiter Resistance

Channel Selection Switch Impedance

Sampling Switch Impedance

S

F

L

R

C

R

C

SW1

AD

P

Pin Capacitance (two contributions, C and C

Sampling Capacitance

)

P1

P2

S

Figure 17. Input equivalent circuit (precise channels)

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

77

Electrical characteristics

EXTERNAL CIRCUIT

Filter

INTERNAL CIRCUIT SCHEME

V

DD

Channel

Selection

Extended

Switch

Sampling

Source

R

Current Limiter

R

F

R

L

R

AD

SW2

S

SW1

C

S

C

V

C

F

C

P2

A

P1

P3

R

C

R

C

Source Impedance

Filter Resistance

Filter Capacitance

Current Limiter Resistance

Channel Selection Switch Impedance (two contributions R

Sampling Switch Impedance

S

F

L

and R

)

SW2

SW

AD

P

SW1

Pin Capacitance (three contributions, C , C and C )

Sampling Capacitance

P1

P2

P3

S

Figure 18. Input equivalent circuit (extended channels)

A second aspect involving the capacitance network shall be considered. Assuming the three capacitances

C , C and C are initially charged at the source voltage V (refer to the equivalent circuit reported in

F

P1

P2

A

Figure 17): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch

close).

Voltage Transient on C_S

V

CS

V

A

ΔV < 0.5 LSB

V

A2

1

2

τ₁< (R_SW+ R_AD) C_S<< t_S

V

A1

τ

₂= R_L(C_S+ C_P1+ C_P2)

T

t

S

Figure 19. Transient behavior during sampling phase

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NXP Semiconductors

Electrical characteristics

In particular two different transient periods can be distinguished:

1. A first and quick charge transfer from the internal capacitance C and C to the sampling

P1

P2

capacitance C occurs (C is supposed initially completely discharged): considering a worst case

S

(since the time constant in reality would be faster) in which C is reported in parallel to C (call

P2

P1

C = C + C ), the two capacitances C and C are in series, and the time constant is

P

P1

P2

P

S

Eqn. 5

C • C

P

S

τ

= (R

+ R

) • --------------------

AD

1

SW

C + C

P

S

Equation 5 can again be simplified considering only C as an additional worst condition. In reality,

S

the transient is faster, but the A/D converter circuitry has been designed to be robust also in the

very worst case: the sampling time t is always much longer than the internal time constant:

S

Eqn. 6

τ < (R

+ R

) • C « t_s

AD S

1

SW

The charge of C and C is redistributed also on C , determining a new value of the voltage V

P1

P2

S

A1

on the capacitance according to Equation 7:

Eqn. 7

V

• (C + C + C ) = V • (C + C

P1 P2 P1

)

P2

A1

S

A

2. A second charge transfer involves also C (that is typically bigger than the on-chip capacitance)

F

through the resistance R : again considering the worst case in which C and C were in parallel

L

P2

S

to C (since the time constant in reality would be faster), the time constant is:

P1

Eqn. 8

τ < R • (C + C + C )

P1 P2

2

L

S

In this case, the time constant depends on the external circuit: in particular imposing that the

transient is completed well before the end of sampling time t , a constraints on R sizing is

s

L

obtained:

ADC_0 (10-bit)

Eqn. 9

8.5 • τ = 8.5 • R • (C + C + C ) < t_s

2

L

S

P1 P2

ADC_1 (12-bit)

Eqn. 10

10 • τ = 10 • R • (C + C + C ) < t_s

2

L

S

P1 P2

Of course, R shall be sized also according to the current limitation constraints, in combination

L

with R (source impedance) and R (filter resistance). Being C definitively bigger than C , C

S

F

P1 P2

and C , then the final voltage V (at the end of the charge transfer transient) will be much higher

S

A2

than V . Equation 11 must be respected (charge balance assuming now C already charged at

A1

S

V ):

A1

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

79

Electrical characteristics

Eqn. 11

V

• (C + C + C + C ) = V • C + V • (C + C + C )

P1 P2 A1 P1 P2

A2

S

F

A

F

S

The two transients above are not influenced by the voltage source that, due to the presence of the R C

F F

filter, is not able to provide the extra charge to compensate the voltage drop on C with respect to the ideal

S

source V ; the time constant R C of the filter is very high with respect to the sampling time (t ). The filter

A

F F

s

is typically designed to act as antialiasing.

Analog source bandwidth (V_A)

t_c< 2 R_FC_F(Conversion rate vs. filter pole)

Noise

f_F= f₀(Anti-aliasing filtering condition)

2 f₀< f_C(Nyquist)

f₀

f

Anti-aliasing filter (f_F= RC filter pole)

Sampled signal spectrum (f_C= Conversion rate)

f_F

f₀

f_C

f

Figure 20. Spectral representation of input signal

Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the

0

antialiasing filter, f ), according to the Nyquist theorem the conversion rate f must be at least 2f ; it means

F

C

0

that the constant time of the filter is greater than or at least equal to twice the conversion period (t ). Again

c

the conversion period t is longer than the sampling time t , which is just a portion of it, even when fixed

c

s

channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in

conclusion it is evident that the time constant of the filter R C is definitively much higher than the

F F

sampling time t , so the charge level on C cannot be modified by the analog signal source during the time

s

S

in which the sampling switch is closed.

The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy

error due to the voltage drop on C ; from the two charge balance equations above, it is simple to derive

S

Equation 12 between the ideal and real sampled voltage on C :

S

Eqn. 12

V

C

+ C + C

P2

----------- = -------------------------------------------------------

A2

P1

F

V

C

+ C + C + C

A

P1

P2 S

F

From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept

A

a maximum error of half a count, a constraint is evident on C value:

F

MPC5607B Microcontroller Data Sheet, Rev. 9

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NXP Semiconductors

Electrical characteristics

ADC_0 (10-bit)

> 2048 • C

Eqn. 13

C

F

S

ADC_1 (12-bit)

> 8192 • C

Eqn. 14

C

F

S

4.16.3 ADC electrical characteristics

Table 43. ADC input leakage current

Value

Unit

Symbol C

Parameter

Conditions

Min

Typ

Max

I_LKGCC D Input leakage current T_A= −40 °C No current injection on adjacent pin

—

1

70

nA

D

P

T_A= 25 °C

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

3

100

200

400

—

8

45

Table 44. ADC_0 conversion characteristics (10-bit ADC_0)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_{SS_ADC0}SR — Voltage on VSS_HV_ADC0

—

−0.1

—

0.1

V

(ADC_0 reference) pin with

2

respect to ground (V_SS

)

V_{DD_ADC0}SR — Voltage on VDD_HV_ADC pin

(ADC reference) with respect

—

V_DD− 0.1

—

V_DD+ 0.1

V

to ground (V_SS

)

V_AINx

SR — Analog input voltage³

—

V_{SS_ADC0}

− 0.1

—

V_{DD_ADC0}

+ 0.1

V

I_ADC0pwdSR — ADC_0 consumption in power

down mode

—

50

µA

mA

I_ADC0runSR — ADC_0 consumption in

running mode

5

f_ADC0SR — ADC_0 analog frequency

6

—

32 + 4ꢀ MHz

Δ

_{ADC0_SYS}SR — ADC_0 digital clock duty cycle ADCLKSEL = 1⁴

45

55

ꢀ

(ipg_clk)

t_{ADC0_PU}SR — ADC_0 power up delay

t_{ADC0_S}CC T Sampling time⁵

—

1.5

µs

f_ADC= 32 MHz,

INPSAMP = 17

0.5

f

_ADC= 6 MHz,

—

42

INPSAMP = 255

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

81

Electrical characteristics

Table 44. ADC_0 conversion characteristics (10-bit ADC_0) (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

t_{ADC0_C}CC P Conversion time⁶

f_ADC= 32 MHz,

INPCMP = 2

0.625

—

µs

pF

C_S

CC D ADC_0 input sampling

capacitance

—

3

C_P1

C_P2

C_P3

CC D ADC_0 input pin capacitance 1

CC D ADC_0 input pin capacitance 2

CC D ADC_0 input pin capacitance 3

—

3

1

3

pF

kΩ

R_SW1CC D Internal resistance of analog

source

R_SW2CC D Internal resistance of analog

source

—

−5

—

2

5

kΩ

mA

R_AD

CC D Internal resistance of analog

source

I_INJ

SR — Input current Injection

Current injection V_DD=

on one ADC_0 3.3 V 10ꢀ

input, different

V_DD

5.0 V 10ꢀ

=

from the

converted one

| INL | CC T Absolute integral nonlinearity No overload

—

0.5

1.5

1.0

LSB

| DNL | CC T Absolute differential

nonlinearity

No overload

| E_O

| E_G

|

CC T Absolute offset error

—

−2

−3

0.5

0.6

—

2

LSB

|

CC T Absolute gain error

TUEP CC P Total unadjusted error⁷for

Without current injection

With current injection

precise channels, input only

pins

T

3

TUEX CC T Total unadjusted error⁷for

Without current injection

With current injection

−3

−4

1

3

4

LSB

extended channel

T

1

2

3

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= −40 to 125 °C, unless otherwise specified.

Analog and digital V_SSmust be common (to be tied together externally).

V_AINxmay exceed V_{SS_ADC0}and V_{DD_ADC0}limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0x3FF.

4

5

Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured

by internal divider by 2.

During the sampling time the input capacitance C_Scan be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within t_{ADC0_S}. After the

end of the sampling time t_{ADC0_S}, changes of the analog input voltage have no effect on the conversion result.

Values for the sampling clock t_{ADC0_S}depend on programming.

6

7

This parameter does not include the sampling time t_{ADC0_S}, but only the time for determining the digital result and

the time to load the result’s register with the conversion result.

Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a

combination of Offset, Gain and Integral Linearity errors.

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82

NXP Semiconductors

Electrical characteristics

Offset Error (E )

Gain Error (E )

G

O

4095

4094

4093

4092

4091

1 LSB ideal = V

/ 4096

DD_ADC

4090

(2)

code out

7

(1)

6

5

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(5)

4

3

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

(4)

(3)

2

1

1 LSB (ideal)

0

1

2

3

4

5

6

7

4090 4091 4092 4093 4094 4095

V

(LSB

)

ideal

in(A)

Offset Error (E )

O

Figure 21. ADC_1 characteristic and error definitions

Table 45. ADC_1 conversion characteristics (12-bit ADC_1)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_{SS_ADC1}SR — Voltage on VSS_HV_ADC1

—

–0.1

—

0.1

V

(ADC_1 reference) pin with

2

respect to ground (V_SS

)

V_{DD_ADC1}SR — VoltageonVDD_HV_ADC1pin

(ADC_1 reference) with

—

V_DD– 0.1 — V_DD+ 0.1

V

respect to ground (V_SS

)

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

83

Electrical characteristics

Table 45. ADC_1 conversion characteristics (12-bit ADC_1) (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_AINx

SR — Analog input voltage³

—

V_{SS_ADC1}

– 0.1

—

V_{DD_ADC1}

+ 0.1

V

I_ADC1pwdSR — ADC_1 consumption in power

down mode

—

50

µA

mA

I_ADC1runSR — ADC_1consumptioninrunning

mode

—

6

f_ADC1

SR — ADC_1 analog frequency

V_DD= 3.3 V

V_DD= 5 V

—

3.33

—

20 + 4ꢀ MHz

32 + 4ꢀ

t_{ADC1_PU}SR — ADC_1 power up delay

1.5

—

µs

ns

t_{ADC1_S}CC T Sampling time⁴

V_DD= 3.3 V

f

_ADC1= 20 MHz,

INPSAMP = 12

600

Sampling time⁴

V_DD= 5.0 V

f

_ADC1= 32 MHz,

500

—

76.2

—

INPSAMP = 17

Sampling time⁴

V_DD= 3.3 V

f_ADC1= 3.33 MHz,

INPSAMP = 255

µs

Sampling time⁴

V_DD= 5.0 V

f

_ADC1= 3.33 MHz,

—

INPSAMP = 255

t_{ADC1_C}CC P Conversion time⁵

V_DD= 3.3 V

f

_ADC1= 20 MHz,

2.4

1.5

—

µs

INPCMP = 0

Conversion time⁵

V_DD= 5.0 V

f_{ADC 1}= 32 MHz,

INPCMP = 0

—

Conversion time⁵

V_DD= 3.3 V

f

_{ADC 1}= 13.33 MHz,

3.6

INPCMP = 0

Conversion time⁵

V_DD= 5.0 V

f

_ADC1= 13.33 MHz,

—

INPCMP = 0

Δ_{ADC1_SYS}SR — ADC_1 digital clock duty cycle ADCLKSEL = 1⁶

45

—

55

5

ꢀ

C_S

CC D ADC_1 input sampling

capacitance

—

pF

C_P1

C_P2

CC D ADC_1 input pin capacitance 1

CC D ADC_1 input pin capacitance 2

CC D ADC_1 input pin capacitance 3

—

3

1

pF

kΩ

C_P3

1.5

1

R_SW1

CC D Internal resistance of analog

source

R_SW2

R_AD

CC D Internal resistance of analog

source

—

2

kΩ

CC D Internal resistance of analog

source

0.3

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Electrical characteristics

Table 45. ADC_1 conversion characteristics (12-bit ADC_1) (continued)

Value

Typ

Symbol

C

Parameter

Conditions¹

Unit

Min

Max

I_INJ

SR — Input current Injection

Current

V_DD= 3.3 V 10ꢀ

V_DD= 5.0 V 10ꢀ

–5

—

5

mA

injection on

one ADC_1

input, different

from the

converted one

| INLP | CC T Absolute integral nonlinearity – No overload

Precise channels

—

1

3

5

1

LSB

| INLX | CC T Absolute integral nonlinearity – No overload

Extended channels

1.5

0.5

| DNL | CC T Absolute differential

nonlinearity

No overload

| E_O|

| E_G|

CC T Absolute offset error

—

–6

–8

2

—

6

LSB

CC T Absolute gain error

TUEP⁷CC P Total unadjusted error for

Without current injection

With current injection

—

precise channels, input only

pins

T

8

TUEX⁷CC T Total unadjusted error for

Without current injection

With current injection

–10

–12

—

10

12

LSB

extended channel

T

1

2

3

V_DD= 3.3 V 10ꢀ / 5.0 V 10ꢀ, T_A= –40 to 125 °C, unless otherwise specified

Analog and digital V_SSmust be common (to be tied together externally).

V_AINxmay exceed V_{SS_ADC1}and V_{DD_ADC1}limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0xFFF.

4

During the sampling time the input capacitance C_Scan be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within t_{ADC1_S}. After the end

of the sampling time t_{ADC1_S}, changes of the analog input voltage have no effect on the conversion result. Values for

the sampling clock t_{ADC1_S}depend on programming.

5

6

7

This parameter does not include the sampling time t_{ADC1_S}, but only the time for determining the digital result and the

time to load the result’s register with the conversion result.

Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by

internal divider by 2.

Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a

combination of Offset, Gain and Integral Linearity errors.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

85

Electrical characteristics

4.17 On-chip peripherals

4.17.1 Current consumption

1

Table 46. On-chip peripherals current consumption

Symbol

C

Parameter

Conditions

Typical value²Unit

I_{DD_BV(CAN)}CC T CAN (FlexCAN)

supply current on

Bitrate:

500 Kbyte/s

Total (static + dynamic)

consumption:

8 * f_periph+ 85 µA

V_{DD_BV}

• FlexCAN in loop-back

mode

• XTAL at 8 MHz used as

CAN engine clock source

• Message sending period is

580 µs

Bitrate:

125 Kbyte/s

8 * f_periph+ 27

I_{DD_BV(eMIOS)}CC T eMIOS supply current Static consumption:

on V_{DD_BV}• eMIOS channel OFF

29 * f_periph

µA

• Global prescaler enabled

Dynamic consumption:

3

• It does not change varying the frequency

(0.003 mA)

I_{DD_BV(SCI)}CC T SCI (LINFlex) supply Total (static + dynamic) consumption:

5 * f_periph+ 31 µA

current on V_{DD_BV}

• LIN mode

• Baudrate: 20 Kbyte/s

I_{DD_BV(SPI)}CC T SPI (DSPI) supply

current on V_{DD_BV}

Ballast static consumption (only clocked)

1

µA

Ballast dynamic consumption (continuous

communication):

16 * f_periph

• Baudrate: 2 Mbit/s

• Transmission every 8 µs

• Frame: 16 bits

I_{DD_BV}

CC T ADC_0/ADC_1supply V_DD= 5.5 V

current on V_{DD_BV}

Ballast static consumption

(no conversion)³

41 * f_periph

µA

(ADC_0/ADC_1)

Ballast dynamic consumption

(continuous conversion)³

46 * f_periph

I_{DD_HV_ADC0}CC T ADC_0 supply current V_DD= 5.5 V

on V_{DD_HV_ADC0}

Analog static consumption

(no conversion)

200

µA

mA

µA

Analog dynamic consumption

(continuous conversion)

3

I_{DD_HV_ADC1}CC T ADC_1 supply current V_DD= 5.5 V

on V_{DD_HV_ADC1}

Analog static consumption

(no conversion)

300 * f_periph

Analogdynamicconsumption

(continuous conversion)

4

mA

I_{DD_HV(FLASH)}CC T CFlash + DFlash

supply current on

V_DD= 5.5 V

—

12

V_{DD_HV}

I_{DD_HV(PLL)}CC T PLL supply current on V_DD= 5.5 V

V_{DD_HV}

—

30 * f_periph

µA

MPC5607B Microcontroller Data Sheet, Rev. 9

86

NXP Semiconductors

Electrical characteristics

1

2

3

Operating conditions: T_A= 25 °C, f_periph= 8 MHz to 64 MHz

f_periphis an absolute value.

During the conversion, the total current consumption is given from the sum of the static and dynamic consumption,

i.e., (41 + 46) * f_periph

.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

87

Electrical characteristics

Figure 22. DSPI classic SPI timing — master, CPHA = 0

2

3

PCSx

1

4

SCK Output

(CPOL = 0)

4

SCK Output

(CPOL = 1)

10

9

Last Data

SIN

First Data

Data

12

11

Last Data

SOUT

Note: Numbers shown reference Table 46.

Figure 23. DSPI classic SPI timing — master, CPHA = 1

PCSx

SCK Output

(CPOL = 0)

10

SCK Output

(CPOL = 1)

9

First Data

Data

Last Data

SIN

12

11

SOUT

Last Data

First Data

Note: Numbers shown reference Table 46.

MPC5607B Microcontroller Data Sheet, Rev. 9

90

NXP Semiconductors

Electrical characteristics

Figure 24. DSPI classic SPI timing — slave, CPHA = 0

3

2

SS

1

4

SCK Input

(CPOL = 0)

4

SCK Input

(CPOL = 1)

5

First Data

11

12

Data

6

Last Data

SOUT

SIN

9

10

Data

Last Data

First Data

Note: Numbers shown reference Table 46.

Figure 25. DSPI classic SPI timing — slave, CPHA = 1

SS

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

11

5

6

12

Last Data

Data

SOUT

SIN

First Data

10

9

Last Data

First Data

Note: Numbers shown reference Table 46.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

91

Electrical characteristics

Figure 26. DSPI modified transfer format timing — master, CPHA = 0

3

PCSx

4

1

2

SCK Output

(CPOL = 0)

4

SCK Output

(CPOL = 1)

9

10

SIN

First Data

Last Data

Data

12

11

SOUT

First Data

Data

Note: Numbers shown reference Table 46.

Figure 27. DSPI modified transfer format timing — master, CPHA = 1

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

10

9

SIN

Last Data

First Data

Data

12

Data

11

First Data

Last Data

SOUT

Note: Numbers shown reference Table 46.

MPC5607B Microcontroller Data Sheet, Rev. 9

92

NXP Semiconductors

Electrical characteristics

Figure 28. DSPI modified transfer format timing — slave, CPHA = 0

3

2

SS

1

SCK Input

(CPOL = 0)

4

SCK Input

(CPOL = 1)

12

11

6

5

First Data

9

Data

Last Data

10

SOUT

SIN

Last Data

First Data

Note: Numbers shown reference Table 46.

Figure 29. DSPI modified transfer format timing — slave, CPHA = 1

SS

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

11

5

6

12

Last Data

First Data

10

Data

SOUT

SIN

9

First Data

Last Data

Note: Numbers shown reference Table 46.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

93

Electrical characteristics

8

7

PCSS

PCSx

Note: Numbers shown reference Table 46.

Figure 30. DSPI PCS strobe (PCSS) timing

4.17.3 Nexus characteristics

Table 48. Nexus characteristics

Value

Typ

No.

Symbol

C

Parameter

Unit

Min

Max

1

2

3

4

5

6

t_TCYC

t_MCYC

t_MDOV

t_MSEOVCC D MCKO low to MSEO_b data valid

CC D TCK cycle time

64

32

—

15

5

—

8

ns

CC D MCKO cycle time

CC D MCKO low to MDO data valid

8

t_EVTOV

t_NTDIS

CC D MCKO low to EVTO data valid

CC D TDI data setup time

8

—

t_NTMSSCC D TMS data setup time

t_NTDIHCC D TDI data hold time

t_NTMSHCC D TMS data hold time

7

5

8

9

t_TDOV

t_TDOI

CC D TCK low to TDO data valid

CC D TCK low to TDO data invalid

35

6

MPC5607B Microcontroller Data Sheet, Rev. 9

94

NXP Semiconductors

Electrical characteristics

TCK

10

11

TMS, TDI

12

TDO

Note: Numbers shown reference Table 48.

Figure 31. Nexus TDI, TMS, TDO timing

4.17.4 JTAG characteristics

Table 49. JTAG characteristics

Value

Typ

No.

Symbol

C

Parameter

Unit

Max

Min

1

2

3

4

5

6

7

t_JCYC

t_TDIS

CC D TCK cycle time

CC D TDI setup time

CC D TDI hold time

64

15

5

—

33

—

ns

t_TDIH

t_TMSS

t_TMSH

t_TDOV

t_TDOI

CC D TMS setup time

CC D TMS hold time

CC D TCK low to TDO valid

CC D TCK low to TDO invalid

15

5

—

6

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

95

Electrical characteristics

TCK

2/4

3/5

INPUT DATA VALID

DATA INPUTS

6

DATA OUTPUTS

OUTPUT DATA VALID

7

DATA OUTPUTS

Note: Numbers shown reference Table 49.

Figure 32. Timing diagram — JTAG boundary scan

MPC5607B Microcontroller Data Sheet, Rev. 9

96

NXP Semiconductors

Package characteristics

5

Package characteristics

Package mechanical data

176 LQFP

5.1

5.1.1

Figure 33. 176 LQFP package mechanical drawing (Part 1 of 3)

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

97

Package characteristics

Figure 34. 176 LQFP package mechanical drawing (Part 2 of 3)

MPC5607B Microcontroller Data Sheet, Rev. 9

98

NXP Semiconductors

Package characteristics

Figure 35. 176 LQFP package mechanical drawing (Part 3 of 3)

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

99

Package characteristics

5.1.2

144 LQFP

Figure 36. 144 LQFP package mechanical drawing (Part 1 of 2)

MPC5607B Microcontroller Data Sheet, Rev. 9

100

NXP Semiconductors

Package characteristics

Figure 37. 144 LQFP package mechanical drawing (Part 2 of 2)

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

101

Package characteristics

5.1.3

100 LQFP

Figure 38. 100 LQFP package mechanical drawing (Part 1 of 3)

MPC5607B Microcontroller Data Sheet, Rev. 9

102

NXP Semiconductors

Package characteristics

Figure 39. 100 LQFP package mechanical drawing (Part 2 of 3)

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

103

Package characteristics

Figure 50. 100 LQFP package mechanical drawing (Part 3 of 3)

MPC5607B Microcontroller Data Sheet, Rev. 9

104

NXP Semiconductors

Package characteristics

5.1.4

208 MAPBGA

Figure 51. 208 MAPBGA package mechanical drawing (Part 1 of 2)

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

105

Package characteristics

Figure 52. 208 MAPBGA package mechanical drawing (Part 2 of 2)

MPC5607B Microcontroller Data Sheet, Rev. 9

106

NXP Semiconductors

Ordering information

6

Ordering information

Figure 40. Commercial product code structure

Example code:

M

PC

56

0

7

B

F1A

M

LL

6

R

Qualification Status

Power Architecture Core

Automotive Platform

Core Version

Flash Size (core dependent)

Product

Fab and Mask Indicator

Temperature spec.

Package Code

Frequency

R = Tape & Reel (blank if Tray)

Qualification Status

Flash Size (for z0 core)

5 = 768 KB

6 = 1024 KB

Temperature spec.

C = -40 to 85 °C

V = -40 to 105 °C

M = -40 to 125 °C

M = general market qualified

S = Automotive qualified

P = Engineering samples

7 = 1.5 MB

Automotive Platform

56 = PPC in 90nm

Product

B = Body

Package Code

LL = 100 LQFP

LQ = 144 LQFP

LU = 176 LQFP

MG = 208 MAPBGA

Core Version

0 = e200z0

Fab and Mask Indicator

F = ATMC Fab

1

K = TSMC Fab

0 = Version of the maskset

Frequency

A = Mask set indicator (Blank = 1st

production maskset, A = 2nd,

4 = Up to 48 MHz

6 = Up to 64 MHz

Note: Not all options are available on all devices.

1

208 MAPBGA is available only as development package for Nexus2+.

Appendix A Abbreviations

Table 53 lists abbreviations used but not defined elsewhere in this document.

Table 53. Abbreviations

Abbreviation

Meaning

CMOS

CPHA

CPOL

CS

Complementary metal oxide semiconductor

Clock phase

Clock polarity

Peripheral chip select

Event out

EVTO

MCKO

MDO

Message clock out

Message data out

MSEO

MTFE

SCK

Message start/end out

Modified timing format enable

Serial communications clock

Serial data out

SOUT

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

107

Abbreviations

Table 53. Abbreviations (continued)

Meaning

Abbreviation

TBD

TCK

TDI

To be defined

Test clock input

Test data input

Test data output

Test mode select

TDO

TMS

MPC5607B Microcontroller Data Sheet, Rev. 9

108

NXP Semiconductors

Revision history

7

Revision history

Table 54 summarizes revisions to this document.

Table 54. Revision history

Substantive changes

Revision

Date

1

2

12-Jan-2009 Initial release

09 Nov-2009 Updated Features

Replaced 27 IRQs in place of 23

ADC features

External Ballast resistor support conditions

Updated device summary-added 208 BGA details

Updated block diagram to include WKUP

Updated block diagram to include 5 ch ADC 12 -bit

Updated Block summary table

Updated LQFP 144, 176 and 100 pinouts. Applied new naming convention for ADC

signals as ADCx_P[x] and ADCx_S[x]

Section 1, “General description

Updated MPC5607B device comparison table

Updated block diagram-aligned with 512k

Updated block summary-aligned with 512k

Section 2, “Package pinouts

Updated 100,144,176,208 packages according to cut2.0 changes

Added Section 3.5.1, “External ballast resistor recommendations

Added NVUSRO [WATCHDOG_EN] field description

Updated Absolute maximum ratings

Updated LQFP thermal characteristics

Updated I/O supply segments

Updated Voltage regulator capacitance connection

Updated Low voltage monitor electrical characteristics

Updated Low voltage power domain electrical characteristics

Updated DC electrical characteristics

Updated Program/Erase specifications

Updated Conversion characteristics (10 bit ADC)

Updated FMPLL electrical characteristics

Updated Fast RC oscillator electrical characteristics-aligned with MPC5604B

Updated On-chip peripherals current consumption

Updated ADC characteristics and error definitions diagram

Updated ADC conversion characteristics (10 bit and 12 bit)

Added ADC characteristics and error definitions diagram for 12 bit ADC

3

25 Jan-2010 Updated Features

Updated block diagram to connect peripherals to pad I/O

Updated block summary to include ADC 12-bit

Updated 144, 176 and 100 pinouts to adjust format issues

Table 26 Flash module life-retention value changed from 1-5 to 5 yrs

Minor editing changes

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

109

Revision history

Table 54. Revision history (continued)

Substantive changes

Revision

Date

4

24 Aug 2010 Editorial changes and improvements.

Updated “Features“ section

Table 1: updated footnote concerning 208 MAPBGA

In the block diagram:

• Added “5ch 12-bit ADC“ block.

• Updated Legend.

• Added “Interrupt request with wakeup functionality” as an input to the WKPU block.

Figure 2: removed alternate functions

Figure 3: removed alternate functions

Figure 4: removed alternate functions

Table 2: added contents concerning the following blocks: CMU, eDMA, ECSM, MC_ME,

MC_PCU, NMI, SSCM, SWT and WKPU

Added Section 3.2, Pin muxing

4, Electrical characteristics: removed “Caution” note

4.2, NVUSRO register: removed “NVUSRO[WATCHDOG_EN] field description“ section

Table 11: V_IN: removed min value in “relative to V_DD” row

Table 12

• T_{A C-Grade Part,}T_{J C-Grade Part,}T_{A V-Grade Part,}T_{J V-Grade Part,}T_{A M-Grade Part,}T_{J M-Grade Part}

:

added new rows

• TV_DD: contents merged into one row

• V_{DD_BV}: changed min value in “relative to V_DD” row

4.5, Thermal characteristics

• 4.5.1, External ballast resistor recommendations: added new paragraph about power

supply

• Table 14: added R_θJBand R_θJCrows

• Removed “208 MAPBGA thermal characteristics” table

Table 15: rewrote parameter description of W_FIand W_NFI

4.6.5, I/O pad current specification

• Removed I_DYNSEGinformation

• Updated “I/O supply segments” table

Table 22: removed I_DYNSEGrow

Added Table 23

Table 25

• Updated all values

• Removed I_VREGREFand I_VREDLVD12rows

• Added the footnote “The duration of the in-rush current depends on the capacitance

placed on LV pins. BV decaps must be sized accordingly. Refer to IMREG value for

minimum amount of current to be provided in cc.” to the I_{DD_BV}specification.

Table 26

• Updated V_PORHmin/max value

• Updated V_LVDLVCORLmin value

Updated Table 27

Table 28

• T_dwprogram: added initial max value

• Inserted T_eslatrow

Table 29: removed the “To be confirmed” footnote

In the “Crystal oscillator and resonator connection scheme” figure, removed R_P.

Table 39

• Removed g_mSXOSCrow

• I_SXOSCBIAS: added min/typ/max value

MPC5607B Microcontroller Data Sheet, Rev. 9

110

NXP Semiconductors

Revision history

Table 54. Revision history (continued)

Substantive changes

Revision

Date

24 Aug 2010 Table 40:

4

(cont.)

(cont.) • Added f_VCOrow

• Added Δt_STJITrow

Table 41

• I_FIRCPWD: removed row for T_A= 55 °C

• Updated T_FIRCSUrow

Table 44: Added two rows: I_ADC0pwdand I_ADC0run

Table 45

• Added two rows: I_ADC1pwdand I_ADC1run

• Updated values of f_{ADC_1}and t_{ADC1_PU}

• Updated t_{ADC1_C}row

Updated Table 46

Updated Table 47

Updated Figure 40

6, Ordering information: deleted “Orderable part number summary“ table

5

6

27 Aug 2010 Removed “Preliminary—Subject to Change Without Notice” marking. This data sheet

contains specifications based on characterization data.

08 Jul 2011 Editorial and formatting changes throughout

Replaced instances of “e200z0” with “e200z0h”Device family comparison table:

• changed LINFlex count for 144-pin LQFP—was ‘6’; is ‘8’

• changed LINFlex count for 176-pin LQFP—was ‘8’; is ‘10’

• replaced 105 °C with 125 °C in footnote 2

MPC5607B block diagram: added GPIO and VREG to legend

MPC5607B series block summary: added acronym “JTAGC”; in WKPU function changed

“up to 18 external sources” to “up to 27 external sources”

144 LQFP pin configuration: for pins 37–72, restored the pin labels that existed prior to

27 July 2010

176 LQFP pin configuration: corrected name of pin 4: was EPC[15]; is PC[15]

Added following sections:

• Pad configuration during reset phases

• Pad configuration during standby mode exit

• Voltage supply pins

• Pad types

• System pins

• Functional port pins

• Nexus 2+ pins

Section “NVUSRO register”: edited content to separate configuration into electrical

parameters and digital functionality; updated footnote describing default value of ‘1’ in

field descriptions NVUSRO[PAD3V5V] and NVUSRO[OSCILLATOR_MARGIN]

Added section “NVUSRO[WATCHDOG_EN] field description”

Tables “Absolute maximum ratings” and “Recommended operating conditions (3.3 V)”:

replaced “VSS_HV_ADC0, VSS_HV_ADC1” with “VDD_HV_ADC0, VDD_HV_ADC1”

in V_{DD_ADC}parameter description

“Recommended operating conditions (5.0 V)” table: replaced “VSS_HV_ADC0,

VSS_HV_ADC1” with “VDD_HV_ADC0, VDD_HV_ADC1” in V_{DD_ADC}parameter

description; changed 3.6V to 3.0V in footnote 2

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

111

Revision history

Revision

Table 54. Revision history (continued)

Substantive changes

Date

6

08 Jul 2011 Section “External ballast resistor recommendations”: replaced “low voltage monitor” with

“low voltage detector (LVD)”

(cont’d)

“I/O input DC electrical characteristics” table: updated I_LKGcharacteristics

“MEDIUM configuration output buffer electrical characteristics” table: changed

“I_OH= 100 µA” to “I_OL= 100 µA” in V_OLconditions

I/O weight: updated table (includes replacing instances of bit “SRE” with “SRC”)

“Reset electrical characteristics” table: updated parameter classification for |I_WPU

|

Updated voltage regulator electrical characteristics

Section “Low voltage detector electrical characteristics”: changed title (was “Voltage

monitor electrical characteristics”); changed “as well as four low voltage detectors” to

“as well as five low voltage detectors”; added event status flag names found in RGM

chapter of device reference manual to POR module and LVD descriptions; replaced

instances of “Low voltage monitor” with “Low voltage detector”; updated values for

V_LVDLVBKPLand V_LVDLVCORL

Updated section “Power consumption”

Section “Program/erase characteristics”: removed table “FLASH_BIU settings vs.

frequency of operation” and associated introduction

“Program and erase specifications” table: updated symbols

PFCRn settings vs. frequency of operation: replaced “FLASH_BIU” with “PFCRn” in table

title; updated field names and frequencies

“Flash power supply DC electrical characteristics” table: deleted footnote 2

Crystal oscillator and resonator connection scheme: inserted footnote about possibly

requiring a series resistor

Fast external crystal oscillator (4 to 16 MHz) electrical characteristics: updated parameter

classification for V_FXOSCOP

Slow external crystal oscillator (32 kHz) electrical characteristics: updated footnote 1

Section “ADC electrical characteristics”: updated symbols for offset error and gain error

Section “Input impedance and ADC accuracy”: changed “V_A/V_A2” to “V_A2/V_A” in

Equation 11

ADC input leakage current: updated I_LKGcharacteristics

ADC_0 conversion characteristics table: replaced instances of

“ADCx_conf_sample_input” with “INPSAMP”; replaced instances of

“ADCx_conf_comp” with “INPCMP

ADC_1 characteristic and error definitions: replaced “AVDD” with “V_{DD_ADC}

ADC_1 conversion characteristics table: replaced instances of

“ADCx_conf_sample_input” with “INPSAMP”; replaced instances of

“ADCx_conf_comp” with “INPCMP”

”

Updated “On-chip peripherals current consumption” table

MPC5607B Microcontroller Data Sheet, Rev. 9

112

NXP Semiconductors

Revision history

Table 54. Revision history (continued)

Substantive changes

Revision

Date

7

13 May 2013 In the cover feature list:

added “and ECC” at the end of

“Up to 1.5 MB on-chip code flash memory supported with the flash memory controller”

added “with ECC” at the end of “Up to 96 KB on-chip SRAM”

Table 1 (MPC5607B family comparison), updated SCI (LINFlex) values, 8 channels for

both MPC5605B and MPC5606B 176-pin.

Table 12 (Recommended operating conditions (3.3 V)), updated conditions of T_Avalues

and relative footnote.

Table 13 (Recommended operating conditions (5.0 V)), updated conditions of T_Avalues

and relative footnote.

Table 20 (Output pin transition times), replaced T_trwith t_tr

Table 24 (Reset electrical characteristics), replaced T_trwith t_tr

Updated Section 4.16.2, “Input impedance and ADC accuracy

Table 26 (Low voltage detector electrical characteristics), changed V_LVDHV3L(min) and

V_LVDHV3BL(min) from 2.7 V to 2.6 V.

Table 28 (Program and erase specifications), added footnote about t_ESRT

Table 40 (FMPLL electrical characteristics), deleted footnote relative to maximum value

of f_CPU

Table 44 (ADC_0 conversion characteristics (10-bit ADC_0)), changed I_ADC0runvalue

from 40 mA to 5 mA.

Table 47 (DSPI characteristics), in the heading row, replaced

DSPI0/DSPI1/DSPI5/DSPI6 with DSPI0/DSPI1/DSPI3/DSPI5

8

9

19 Mar 2014 Added “K=TSMC Fab” against the Fab and mask indicator in Figure 40 (Commercial

product code structure).

9 Nov 2017 In Table 12 (Recommended operating conditions (3.3 V)) added Min value for T_VDD.

In Table 13 (Recommended operating conditions (5.0 V)) added Min value for T_VDD.

In 6, Ordering information added note “Not all options are available on all devices“.

MPC5607B Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

113

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Document Number: MPC5607B

Rev. 9

11/2017


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