935319892518_技术文档

Document Number K70P256M120SF3

Rev. 7, 02/2018

NXP Semiconductors

Data Sheet: Technical Data

K70P256M120SF3

K70 Sub-Family

Supports the following:

MK70FX512VMJ12,

MK70FN1M0VMJ12

Key features

• Security and integrity modules

– Hardware CRC module to support fast cyclic

redundancy checks

– Tamper detect and secure storage

– Hardware random-number generator

– Hardware encryption supporting DES, 3DES, AES,

MD5, SHA-1, and SHA-256 algorithms

– 128-bit unique identification (ID) number per chip

• Operating Characteristics

– Voltage range: 1.71 to 3.6 V

– Flash write voltage range: 1.71 to 3.6 V

– Temperature range (ambient): -40 to 105°C

• Performance

– Up to 120 MHz Arm® Cortex®-M4 core with DSP

instructions delivering 1.25 Dhrystone MIPS per

MHz

• Human-machine interface

– Graphic LCD controller

• Memories and memory interfaces

– Up to 1024 KB program flash memory on non-

FlexMemory devices

– Low-power hardware touch sensor interface (TSI)

– General-purpose input/output

• Analog modules

– Up to 512 KB program flash memory on

FlexMemory devices

– Up to 512 KB FlexNVM on FlexMemory devices

– 16 KB FlexRAM on FlexMemory devices

– Up to 128 KB RAM

– Serial programming interface (EzPort)

– FlexBus external bus interface

– DDR controller interface

– Four 16-bit SAR ADCs

– Programmable gain amplifier (PGA) (up to x64)

integrated into each ADC

– Two 12-bit DACs

– Four analog comparators (CMP) containing a 6-bit

DAC and programmable reference input

– Voltage reference

– NAND flash controller interface

• Timers

– Programmable delay block

– Two 8-channel motor control/general purpose/PWM

timers

– Two 2-channel quadrature decoder/general purpose

timers

• Clocks

– 3 to 32 MHz crystal oscillator

– 32 kHz crystal oscillator

– Multi-purpose clock generator

• System peripherals

– IEEE 1588 timers

– Multiple low-power modes to provide power

optimization based on application requirements

– Memory protection unit with multi-master

protection

– Periodic interrupt timers

– 16-bit low-power timer

– Carrier modulator transmitter

– Real-time clock

– 32-channel DMA controller, supporting up to 128

request sources

– External watchdog monitor

– Software watchdog

– Low-leakage wakeup unit

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

• Communication interfaces

– Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability

– USB high-/full-/low-speed On-the-Go controller with ULPI interface

– USB full-/low-speed On-the-Go controller with on-chip transceiver

– USB Device Charger detect (USBDCD)

– Two Controller Area Network (CAN) modules

– Three SPI modules

– Two I2C modules

– Six UART modules

– Secure Digital Host Controller (SDHC)

– Two I2S modules

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NXP Semiconductors

Table of Contents

1 Ordering parts.......................................................................................5

6.2 System modules........................................................................... 29

6.3 Clock modules............................................................................. 29

1.1 Determining valid orderable parts............................................... 5

2 Part identification................................................................................. 5

2.1 Description...................................................................................5

2.2 Format..........................................................................................5

2.3 Fields............................................................................................5

2.4 Example....................................................................................... 6

3 Terminology and guidelines.................................................................6

3.1 Definitions................................................................................... 6

3.2 Examples......................................................................................6

3.3 Typical-value conditions..............................................................7

3.4 Relationship between ratings and operating requirements.......... 7

3.5 Guidelines for ratings and operating requirements......................8

4 Ratings..................................................................................................8

4.1 Thermal handling ratings.............................................................8

4.2 Moisture handling ratings............................................................ 9

4.3 ESD handling ratings...................................................................9

4.4 Voltage and current operating ratings..........................................9

5 General................................................................................................. 10

5.1 AC electrical characteristics........................................................ 10

5.2 Nonswitching electrical specifications........................................ 10

6.3.1

6.3.2

6.3.3

MCG specifications.....................................................29

Oscillator electrical specifications...............................32

32 kHz oscillator electrical characteristics..................34

6.4 Memories and memory interfaces................................................34

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

Flash (FTFE) electrical specifications.........................34

EzPort switching specifications...................................39

NAND flash controller specifications......................... 40

DDR controller specifications..................................... 43

Flexbus switching specifications.................................46

6.5 Security and integrity modules.................................................... 48

6.5.1 DryIce Tamper Electrical Specifications.....................48

6.6 Analog..........................................................................................49

6.6.1

6.6.2

6.6.3

6.6.4

ADC electrical specifications......................................49

CMP and 6-bit DAC electrical specifications............. 56

12-bit DAC electrical characteristics...........................58

Voltage reference electrical specifications..................61

6.7 Timers.......................................................................................... 62

6.8 Communication interfaces........................................................... 62

6.8.1

6.8.2

6.8.3

6.8.4

6.8.5

6.8.6

6.8.7

Ethernet switching specifications................................62

USB electrical specifications.......................................65

USB DCD electrical specifications............................. 65

USB VREG electrical specifications...........................66

ULPI timing specifications..........................................66

CAN switching specifications..................................... 67

DSPI switching specifications (limited voltage

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.7

5.2.8

Voltage and current operating requirements............... 10

LVD and POR operating requirements....................... 12

Voltage and current operating behaviors.....................13

Power mode transition operating behaviors................ 16

Power consumption operating behaviors.....................17

EMC radiated emissions operating behaviors............. 20

Designing with radiated emissions in mind.................21

Capacitance attributes..................................................21

range)...........................................................................67

DSPI switching specifications (full voltage range).....69

Inter-Integrated Circuit Interface (I2C) timing............71

UART switching specifications...................................72

SDHC specifications................................................... 72

I2S/SAI switching specifications................................ 73

6.8.8

5.3 Switching specifications.............................................................. 21

6.8.9

5.3.1

5.3.2

Device clock specifications......................................... 21

General switching specifications.................................22

6.8.10

6.8.11

6.8.12

5.4 Thermal specifications.................................................................24

5.4.1

5.4.2

Thermal operating requirements..................................24

Thermal attributes........................................................24

6.9 Human-machine interfaces (HMI)...............................................80

6.9.1

6.9.2

TSI electrical specifications........................................ 80

LCDC electrical specifications....................................81

5.5 Power sequencing........................................................................ 25

6 Peripheral operating requirements and behaviors................................ 25

6.1 Core modules............................................................................... 25

7 Dimensions...........................................................................................84

7.1 Obtaining package dimensions.................................................... 84

8 Pinout................................................................................................... 84

8.1 Pins with active pull control after reset....................................... 84

6.1.1

6.1.2

Debug trace timing specifications............................... 25

JTAG electricals.......................................................... 26

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NXP Semiconductors

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8.2 K70 Signal Multiplexing and Pin Assignments...........................84

8.3 K70 Pinouts..................................................................................94

9 Revision History...................................................................................95

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Ordering parts

1 Ordering parts

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part

numbers for this device, go to nxp.com and perform a part number search for the

following device numbers: PK70 and MK70

2 Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format:

Q K## A M FFF T PP CC N

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations

are valid):

Field

Description

Values

Q

Qualification status

• M = Fully qualified, general market flow

• P = Prequalification

K##

A

Kinetis family

• K70

Key attribute

• F = Cortex-M4 w/ DSP and FPU

M

Flash memory type

• N = Program flash only

• X = Program flash and FlexMemory

FFF

Program flash memory size

• 512 = 512 KB

• 1M0 = 1 MB

Table continues on the next page...

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Terminology and guidelines

Field

Description

Values

T

Temperature range (°C)

• V = –40 to 105

• C = –40 to 85

PP

CC

N

Package identifier

• MJ = 256 MAPBGA (17 mm x 17 mm)

• 12 = 120 MHz

Maximum CPU frequency (MHz)

Packaging type

• R = Tape and reel

• (Blank) = Trays

2.4 Example

This is an example part number:

MK70FN1M0VMJ12

3 Terminology and guidelines

3.1 Definitions

Key terms are defined in the following table:

Term

Definition

Rating

A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent

chip failure:

• Operating ratings apply during operation of the chip.

• Handling ratings apply when the chip is not powered.

NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic

begins to exceed one of its operating ratings.

Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during

operation to avoid incorrect operation and possibly decreasing the useful life of the chip

Operating behavior

A specified value or range of values for a technical characteristic that are guaranteed during

operation if you meet the operating requirements and any other specified conditions

Typical value

A specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior

• Is representative of that characteristic during operation when you meet the typical-value

conditions or other specified conditions

NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.

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NXP Semiconductors

Terminology and guidelines

3.2 Examples

Operating rating:

EXAMPLE

Operating requirement:

Operating behavior that includes a typical value:

EXAMPLE

3.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as

specified):

Symbol

Description

Ambient temperature

Supply voltage

Value

Unit

T_A

25

°C

V

V_DD

3.3

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Ratings

3.4 Relationship between ratings and operating requirements

Fatal range

Degraded operating range

Normal operating range

Degraded operating range

Fatal range

Expected permanent failure

- No permanent failure

- Correct operation

- No permanent failure

Expected permanent failure

- Possible decreased life

- Possible incorrect operation

- Possible decreased life

- Possible incorrect operation

–∞

∞

Operating (power on)

Fatal range

Handling range

Fatal range

Expected permanent failure

No permanent failure

Expected permanent failure

–∞

∞

Handling (power off)

3.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.

• During normal operation, don’t exceed any of the chip’s operating requirements.

• If you must exceed an operating requirement at times other than during normal

operation (for example, during power sequencing), limit the duration as much as

possible.

4 Ratings

4.1 Thermal handling ratings

Symbol

T_STG

Description

Min.

–55

—

Max.

150

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

1

2

T_SDR

260

°C

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

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Ratings

4.2 Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol

V_HBM

V_CDM

I_LAT

Description

Min.

-2000

-500

Max.

+2000

+500

Unit

V

Notes

Electrostatic discharge voltage, human body model

Electrostatic discharge voltage, charged-device model

Latch-up current at ambient temperature of 105°C

1

2

3

V

-100

+100

mA

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

4.4 Voltage and current operating ratings

Symbol

V_DD

Description

Min.

–0.3

—

Max.

3.8

Unit

V

Digital supply voltage1

Core supply voltage

DDR I/O supply voltage

Digital supply current

Core supply current

DDR supply current

V_{DD_INT}

V_{DD_DDR}

I_DD

3.8

V

3.8

V

300

185

220

5.5

mA

V

I_{DD_INT}

I_{DD_DDR}

V_DIO

—

Digital input voltage (except RESET, EXTAL0/XTAL0, and

EXTAL1/XTAL1) ²

–0.3

V_DDDR

V_AIO

DDR input voltage

Analog³, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input

voltage

–0.3

V_{DD_DDR}+ 0.3

V_DD+ 0.3

V

I_D

Maximum current single pin limit (applies to all digital pins)

Analog supply voltage

–25

V_DD– 0.3

–0.3

25

V_DD+ 0.3

3.63

mA

V

V_DDA

V_{USB0_DP}

V_{USB1_DP}

USB0_DP input voltage

V

USB1_DP input voltage

–0.3

3.63

V

Table continues on the next page...

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General

Symbol

Description

Min.

–0.3

Max.

3.63

6.0

Unit

V

V_{USB0_DM}

V_{USB1_DM}

VREGIN

V_BAT

USB0_DM input voltage

USB1_DM input voltage

USB regulator input

RTC battery supply voltage

V

3.8

V

1. It applies for all port pins except Tamper pins.

2. It covers digital pins except Tamper pins and DDR pins.

3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

5 General

5.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

High

Low

V_IH

80%

50%

20%

Input Signal

Midpoint1

V_IL

Fall Time

Rise Time

The midpoint is V_IL+ (V_IH- V_IL) / 2

Figure 1. Input signal measurement reference

All digital I/O switching characteristics assume:

1. output pins

• have C_L=30pF loads,

• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and

• are configured for high drive strength (PORTx_PCRn[DSE]=1)

2. input pins

• have their passive filter disabled (PORTx_PCRn[PFE]=0)

5.2 Nonswitching electrical specifications

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General

Notes

5.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

Symbol

V_DD

Description

Min.

max [V_{DD_DDR}, 1.71 V]

1.71

Max.

3.6

Unit

V

Supply voltage

Core supply voltage

V_{DD_INT}

V_DD

V

V_{DD_DDR}DDR voltage — memory I/O buffers

• DDR1

2.3

2.7

1.9

V

• DDR2/LPDDR1

1.71

V_{REF_DDR}Input reference voltage (DDR1/DDR2/

LPDDR1)

0.49 × V_{DD_DDR}

V_{DD_DDR}

V

1

V_DDA

Analog supply voltage

1.71

–0.1

1.71

3.6

0.1

3.6

V

V_DD– V_DDAV_DD-to-V_DDAdifferential voltage

V_SS– V_SSAV_SS-to-V_SSAdifferential voltage

V_BAT

V_IH

RTC battery supply voltage

Input high voltage (digital pins except

Tamper pins and DDR pins)

0.7 × V_DD

—

V

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

0.75 × V_DD

V_IL

Input low voltage (digital pins except Tamper

pins and DDR pins)

—

0.35 × V_DD

0.3 × V_DD

V

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

V_{IH_DDR}

Input high voltage (DDR pins)

V_{REF_DDR}+ 0.15

V_{REF_DDR}+ 0.125

0.7 × V_{DD_DDR}

—

V

• DDR1

• DDR2

• LPDDR1

V_{IL_DDR}

Input low voltage (DDR pins)

—

V_{REF_DDR}– 0.15

V_{REF_DDR}– 0.125

0.3 × V_{DD_DDR}

—

V

• DDR1

• DDR2

• LPDDR1

—

V_HYS

I_ICDIO

Input hysteresis (digital pins except Tamper

pins and DDR pins)

0.06 × V_DD

Digital pin (except Tamper pins) negative DC

injection current — single pin

2

4

-5

—

mA

• V_IN< V_SS-0.3V

I_ICAIO

Analog³, EXTAL0/XTAL0, and EXTAL1/

XTAL1 pin DC injection current — single pin

• V_IN< V_SS-0.3V (Negative current

injection)

-5

—

+5

• V_IN> V_DD+0.3V (Positive current

injection)

Table continues on the next page...

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General

Table 1. Voltage and current operating requirements (continued)

Symbol

Description

Min.

Max.

Unit

Notes

I_ICcont

Contiguous pin DC injection current —

regional limit, includes sum of negative

injection currents or sum of positive injection

currents of 16 contiguous pins

-25

—

mA

+25

• Negative current injection

• Positive current injection

V_ODPU

V_RAM

Open drain pullup voltage level

V_DD

1.2

V_DD

—

V

5

V_DD(V_{DD_INT}) voltage required to retain RAM

V_RFVBAT

V_BATvoltage required to retain the VBAT

register file

V_{POR_VBAT}

—

1. For DDR1/DDR2, connect V_{REF_DDR}to the same reference voltage used for the memory. For LPDDR1, connect V_{REF_DDR}

to the V_{DD_DDR}voltage.

2. All 5 V tolerant digital I/O pins are internally clamped to V_SSthrough an ESD protection diode. There is no diode

connection to V_DD. If V_INis less than V_{DIO_MIN}, a current limiting resistor is required. If V_INgreater than V_{DIO_MIN}

(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC injection

current limiting resistor is calculated as R=(V_{DIO_MIN}-V_IN)/|I_ICDIO|.

3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and

XTAL are analog pins.

4. All analog pins are internally clamped to V_SSand V_DDthrough ESD protection diodes. If V_INis less than V_{AIO_MIN}or greater

than V_{AIO_MAX}, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as

R=(V_{AIO_MIN}-V_IN)/|I_ICAIO|. The positive injection current limiting resistor is calculated as R=(V_IN-V_{AIO_MAX})/|I_ICAIO|. Select the

larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.

5. Open drain outputs must be pulled to VDD.

5.2.2 LVD and POR operating requirements

Table 2. LVD and POR operating requirements

Symbol Description

Min.

0.8

Typ.

1.1

Max.

1.5

Unit

V

Notes

V_POR

Falling VDD POR detect voltage

V_LVDH

Falling low-voltage detect threshold — high

range (LVDV=01)

2.48

2.56

2.64

V

Low-voltage warning thresholds — high range

• Level 1 falling (LVWV=00)

1

V_LVW1H

V_LVW2H

V_LVW3H

V_LVW4H

2.62

2.72

2.82

2.92

2.70

2.80

2.90

3.00

2.78

2.88

2.98

3.08

V

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

V_HYSH

V_LVDL

Low-voltage inhibit reset/recover hysteresis —

high range

—

80

—

mV

V

Falling low-voltage detect threshold — low range

(LVDV=00)

1.54

1.60

1.66

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV=00)

1

V_LVW1L

V_LVW2L

1.74

1.84

1.80

1.90

1.86

1.96

V

Table continues on the next page...

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General

Notes

Table 2. LVD and POR operating requirements (continued)

Symbol Description

V_LVW3L• Level 2 falling (LVWV=01)

V_LVW4L

Min.

Typ.

Max.

Unit

1.94

2.00

2.06

V

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

2.04

2.10

2.16

V

V_HYSL

Low-voltage inhibit reset/recover hysteresis —

low range

—

60

—

mV

V_BG

t_LPO

Bandgap voltage reference

Internal low power oscillator period

factory trimmed

0.97

900

1.00

1.03

V

1000

1100

μs

1. Rising thresholds are falling threshold + hysteresis voltage

Table 3. VBAT power operating requirements

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_{POR_VBAT}Falling VBAT supply POR detect voltage

0.8

1.1

1.5

V

5.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

Symbol Description

V_OHOutput high voltage — high drive strength

Min.

Typ.

Max.

Unit

Notes

—

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= -9mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= -3mA

V_DD– 0.5

—

V

Output high voltage — low drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= -2mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= -0.6mA

—

V_DD– 0.5

—

V

I_OHT

Output high current total for all ports

—

100

mA

I_{OHT_io60}Output high current total for fast digital ports

V_{OH_DDR}Output high voltage for DDR pins

• DDR1 (I_OH= -16.2 mA)

V_{DD_DDR}

0.36

-

—

V

• DDR2 half strength (I_OH= -5.36 mA)

• DDR2 full strength (I_OH= -13.4 mA)

• LPDDR1 half strength (I_OH= -0.1 mA)

• LPDDR1 full strength (I_OH= -0.1 mA)

V_{DD_DDR}

0.28

V_{DD_DDR}

0.28

0.9 x

V_{DD_DDR}

0.9 x

V_{DD_DDR}

Table continues on the next page...

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General

Table 4. Voltage and current operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{OHT_DDR}Output high current total for DDR pins

—

100

56

mA

• DDR1

• DDR2

39

• LPDDR1

V_{OH_Tamper}Output high voltage — high drive strength

• 2.7 V ≤ V_BAT≤ 3.6 V, I_OH= -10mA

V_BAT– 0.5

—

V

• 1.71 V ≤ V_BAT≤ 2.7 V, I_OH= -3mA

Output high voltage — low drive strength

• 2.7 V ≤ V_BAT≤ 3.6 V, I_OH= -2mA

• 1.71 V ≤ V_BAT≤ 2.7 V, I_OH= -0.6mA

V_BAT– 0.5

—

V

I_{OH_Tamper}Output high current total for Tamper pins

—

100

mA

V_OL

Output low voltage — high drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 10 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 5 mA

—

0.5

V

Output low voltage — low drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 2 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 1 mA

—

0.5

V

I_OLT

Output low current total for all ports

—

100

mA

I_{OLT_io60}Output low current total for fast digital ports

V_{OL_DDR}Output low voltage for DDR pins

• DDR1 (I_OL= 16.2 mA)

—

0.37

0.28

V

• DDR2 half strength (I_OL= 5.36 mA)

• DDR2 full strength (I_OL= 13.4 mA)

• LPDDR1 half strength (I_OL= 0.1 mA)

• LPDDR1 full strength (I_OL= 0.1 mA)

0.1 x

V_{DD_DDR}

0.1 x

V_{DD_DDR}

I_{OLT_DDR}Output low current total for DDR pins

—

100

56

mA

• DDR1

• DDR2

39

• LPDDR1

V_{OL_Tamper}Output low voltage — high drive strength

• 2.7 V ≤ V_BAT≤ 3.6 V, I_OL= 10mA

—

0.5

V

• 1.71 V ≤ V_BAT≤ 2.7 V, I_OL= 3mA

Output low voltage — low drive strength

• 2.7 V ≤ V_BAT≤ 3.6 V, I_OL= 2mA

• 1.71 V ≤ V_BAT≤ 2.7 V, I_OL= 0.6mA

—

0.5

V

Table continues on the next page...

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NXP Semiconductors

General

Table 4. Voltage and current operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{OL_Tamper}Output low current total for Tamper pins

—

100

mA

I_INA

Input leakage current, analog pins and digital

pins configured as analog inputs

1, 2

• V_SS≤ V_IN≤ V_DD

• All pins except EXTAL32, XTAL32,

EXTAL, XTAL

—

0.002

0.004

0.075

0.5

1.5

10

μA

• EXTAL (PTA18) and XTAL (PTA19)

• EXTAL32, XTAL32

I_IND

Input leakage current, digital pins

• V_SS≤ V_IN≤ V_IL

2, 3

• All digital pins

—

0.002

0.5

μA

• V_IN= V_DD

—

0.002

0.004

0.5

1

μA

• All digital pins except PTD7

• PTD7

I_IND

Input leakage current, digital pins

• V_IL< V_IN< V_DD

• V_DD= 3.6 V

2, 3, 4

—

18

12

8

26

19

13

6

μA

• V_DD= 3.0 V

• V_DD= 2.5 V

• V_DD= 1.7 V

3

I_IND

Input leakage current, digital pins

• V_DD< V_IN< 5.5 V

2, 3

2, 5

—

1

50

μA

Z_IND

Input impedance examples, digital pins

• V_DD= 3.6 V

—

48

55

57

85

kΩ

• V_DD= 3.0 V

• V_DD= 2.5 V

• V_DD= 1.7 V

I_{IN_DDR}

Input leakage current (per DDR pin) for full

temperature range

—

1

μA

Input leakage current (per DDR pin) at 25°C

—

0.025

1

μA

I_{IN_Tamper}Input leakage current (per Tamper pin) for full

temperature range

I_{IN_Tamper}Input leakage current (per Tamper pin) at 25°C

—

20

—

0.025

50

μA

kΩ

R_PU

R_PD

Internal pullup resistors (except Tamper pins)

Internal pulldown resistors (except Tamper pins)

On-die termination (ODT) resistance for DDR2

6

7

50

R_ODT

60

—

90

Ω

• R_tt1(eff)- 75 Ω

• R_tt2(eff)- 150 Ω

120

180

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General

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

2. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.

3. Internal pull-up/pull-down resistors disabled.

4. Characterized, not tested in production.

5. Examples calculated using V_ILrelation, V_DD, and max I_IND: Z_IND=V_IL/I_IND. This is the impedance needed to pull a high

signal to a level below V_ILdue to leakage when V_IL< V_IN< V_DD. These examples assume signal source low = 0 V. See

Figure 2.

6. Measured at V_DDsupply voltage = V_DDmin and Vinput = V_SS

7. Measured at V_DDsupply voltage = V_DDmin and Vinput = V_DD

Figure 2. 5 V Tolerant Input IIND Parameter

5.2.4 Power mode transition operating behaviors

All specifications except t_POR, and VLLSx→RUN recovery times in the following table

assume this clock configuration:

• CPU and system clocks = 100 MHz

• Bus clock = 50 MHz

• FlexBus clock = 50 MHz

• Flash clock = 25 MHz

• MCG mode: FEI

Table 5. Power mode transition operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

t_POR

After a POR event, amount of time from the point V_DD

reaches 1.71 V to execution of the first instruction

across the operating temperature range of the chip.

1

μs

—

300

• V_DDslew rate ≥ 5.7 kV/s

• V_DDslew rate < 5.7 kV/s

1.7 V / (V_DD

slew rate)

—

160

μs

• VLLS1 → RUN

• VLLS2 → RUN

114

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General

Notes

Table 5. Power mode transition operating behaviors (continued)

Symbol

Description

Min.

Max.

Unit

—

114

μs

• VLLS3 → RUN

—

5.0

5

μs

• LLS → RUN

• VLPS → RUN

• STOP → RUN

4.8

1. Normal boot (FTFE_FOPT[LPBOOT]=1)

5.2.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

Symbol

I_DDA

Description

Min.

Typ.

Max.

Unit

Notes

Analog supply current

—

See note

mA

1

2

I_{DD_RUN}

Run mode current — all peripheral clocks

disabled, code executing from flash

—

49.28

49.08

73.85

73.93

mA

• @ 1.8V

• @ 3.0V

I_{DD_RUN}

Run mode current — all peripheral clocks

enabled, code executing from flash

3

—

74.43

74.28

99.97

mA

• @ 1.8V

• @ 3.0V

100.41

I_{DD_WAIT}Wait mode high frequency current at 3.0 V — all

peripheral clocks disabled

—

34.67

18.03

58.5

mA

2

4

I_{DD_WAIT}Wait mode reduced frequency current at 3.0 V —

all peripheral clocks disabled

41.91

I_{DD_STOP}Stop mode current at 3.0 V

• @ –40 to 25°C

—

1.25

2.93

7.08

1.62

4.39

mA

• @ 70°C

10.74

• @ 105°C

I_{DD_VLPR}Very-low-power run mode current at 3.0 V — all

peripheral clocks disabled

—

1.03

1.58

0.64

4.48

4.96

4.29

mA

5

I_{DD_VLPR}Very-low-power run mode current at 3.0 V — all

peripheral clocks enabled

I_{DD_VLPW}Very-low-power wait mode current at 3.0 V

I_{DD_VLPS}Very-low-power stop mode current at 3.0 V

• @ –40 to 25°C

—

0.22

0.78

0.38

1.33

mA

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General

Table 6. Power consumption operating behaviors (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

• @ 70°C

—

2.18

3.56

mA

• @ 105°C

I_{DD_LLS}

Low leakage stop mode current at 3.0 V

• @ –40 to 25°C

—

0.22

0.78

2.16

0.37

1.33

3.52

mA

• @ 70°C

• @ 105°C

I_{DD_VLLS3}Very low-leakage stop mode 3 current at 3.0 V

—

4.09

20.98

84.95

5.58

28.93

111.15

μA

• @ –40 to 25°C

• @ 70°C

• @ 105°C

I_{DD_VLLS2}Very low-leakage stop mode 2 current at 3.0 V

—

2.68

8.8

4.22

10.74

43.61

μA

• @ –40 to 25°C

• @ 70°C

37.28

• @ 105°C

I_{DD_VLLS1}Very low-leakage stop mode 1 current at 3.0 V

—

2.46

7.04

4.02

8.99

μA

• @ –40 to 25°C

• @ 70°C

30.68

37.04

• @ 105°C

I_{DD_VBAT}Average current when CPU is not accessing

RTC registers at 3.0 V

6

—

0.89

1.28

3.10

1.10

1.85

4.30

μA

• @ –40 to 25°C

• @ 70°C

• @ 105°C

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

2. 120 MHz core and system clock, 60 MHz bus, 30 MHz FlexBus clock, and 20 MHz flash clock. MCG configured for PEE

mode. All peripheral clocks disabled.

3. 120 MHz core and system clock, 60 MHz bus, 30 MHz FlexBus clock, and 20 MHz flash clock. MCG configured for PEE

mode. All peripheral clocks enabled, but peripherals are not in active operation.

4. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode.

5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All

peripheral clocks disabled.

6. Includes 32kHz oscillator current and RTC operation.

5.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater

than 50 MHz frequencies. MCG in PEE mode at greater than 100 MHz frequencies.

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General

• USB regulator disabled

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFE

Figure 3. Run mode supply current vs. core frequency

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General

Figure 4. VLPR mode supply current vs. core frequency

5.2.6 EMC radiated emissions operating behaviors

Table 7. EMC radiated emissions operating behaviors for 256MAPBGA

Symbol

Description

Frequency

band (MHz)

Typ.

Unit

Notes

V_RE1

V_RE2

V_RE3

V_RE4

Radiated emissions voltage, band 1

Radiated emissions voltage, band 2

Radiated emissions voltage, band 3

Radiated emissions voltage, band 4

0.15–50

50–150

21

24

29

28

dBμV

1, 2, 3

150–500

500–1000

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of

Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported

emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the

measured orientations in each frequency range.

2. V_DD= 3.3 V, T_A= 25 °C, f_OSC= 12 MHz (crystal), f_SYS= 72 MHz, f_BUS= 72 MHz

3. Determined according to IEC Standard JESD78, IC Latch-Up Test

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General

5.2.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.nxp.com.

2. Perform a keyword search for “EMC design.”

5.2.8 Capacitance attributes

Table 8. Capacitance attributes

Symbol

C_{IN_A}

Description

Min.

—

Max.

Unit

pF

Input capacitance: analog pins

Input capacitance: digital pins

Input capacitance: fast digital pins

7

9

C_{IN_D}

—

pF

C_{IN_D_io60}

—

pF

5.3 Switching specifications

5.3.1 Device clock specifications

Table 9. Device clock specifications

Symbol

Description

Min.

Max.

Unit

Notes

Normal run mode

f_SYS

System and core clock

—

120

—

MHz

f_{SYS_USBFS}

System and core clock when Full Speed USB in

operation

20

f_{SYS_USBHS}

f_ENET

System and core clock when High Speed USB in

operation

60

—

MHz

System and core clock when ethernet in operation

• 10 Mbps

• 100 Mbps

5

—

50

—

f_BUS

FB_CLK

f_FLASH

f_DDR

Bus clock

60

50

25

150

25

MHz

FlexBus clock

Flash clock

DDR clock

f_LPTMR

LPTMR clock

VLPR mode¹

Table continues on the next page...

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General

Table 9. Device clock specifications (continued)

Symbol

f_SYS

f_BUS

Description

System and core clock

Bus clock

Min.

—

Max.

Unit

MHz

Notes

4

—

FB_CLK

f_FLASH

f_LPTMR

FlexBus clock

Flash clock

—

4

—

0.5

4

LPTMR clock

—

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any

other module.

5.3.2 General switching specifications

These general purpose specifications apply to all pins configured for:

• GPIO signaling

• Other peripheral module signaling not explicitly stated elsewhere

Table 10. General switching specifications

Symbol

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5

—

Bus clock

cycles

1, 2

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter enabled) — Asynchronous path

100

16

—

ns

3

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter disabled) — Asynchronous path

External reset pulse width (digital glitch filter disabled)

100

2

—

Mode select (EZP_CS) hold time after reset

deassertion

Bus clock

cycles

Port rise and fall time (high drive strength)

• Slew disabled

4

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

14

8

ns

• Slew enabled

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

36

24

ns

Port rise and fall time (low drive strength)

• Slew disabled

5

• 1.71 ≤ V_DD≤ 2.7V

—

14

8

ns

• 2.7 ≤ V_DD≤ 3.6V

• Slew enabled

—

36

ns

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General

Notes

Table 10. General switching specifications (continued)

Symbol

Description

• 1.71 ≤ V_DD≤ 2.7V

Min.

Max.

Unit

—

24

ns

• 2.7 ≤ V_DD≤ 3.6V

t_io50

Port rise and fall time (high drive strength)

• Slew disabled

6

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

7

3

ns

—

• Slew enabled

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

28

14

ns

—

t_io50

t_io60

Port rise and fall time (low drive strength)

• Slew disabled

-1

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

18

9

ns

—

• Slew enabled

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

48

24

ns

—

Port rise and fall time (high drive strength)

• Slew disabled

6

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

6

3

ns

—

• Slew enabled

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

28

14

ns

—

Port rise and fall time (low drive strength)

• Slew disabled

-1

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

18

6

ns

—

• Slew enabled

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

48

24

ns

—

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be

recognized in that case.

2. The greater synchronous and asynchronous timing must be met.

3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and

VLLSx modes.

4. 75 pF load

5. 15 pF load

6. 25 pF load

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General

5.4 Thermal specifications

5.4.1 Thermal operating requirements

Table 11. Thermal operating requirements

Symbol

T_J

Description

Min.

–40

Max.

125

Unit

°C

Die junction temperature

Ambient temperature¹

T_A

105

°C

1. Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not exceed maximum T_J. The simplest method to

determine T_Jis:

T_J= T_A+ R_θJAx chip power dissipation

5.4.2 Thermal attributes

Board type

Symbol

Description

256 MAPBGA

Unit

Notes

Single-layer (1s)

R_θJA

Thermal

43

°C/W

1, 2

1,2, 3

1,3

resistance, junction

to ambient (natural

convection)

Four-layer (2s2p)

Single-layer (1s)

Four-layer (2s2p)

R_θJA

Thermal

28

36

25

resistance, junction

to ambient (natural

convection)

R_θJMA

Thermal

resistance, junction

to ambient (200 ft./

min. air speed)

R_θJMA

Thermal

1,3

resistance, junction

to ambient (200 ft./

min. air speed)

—

R_θJB

R_θJC

Ψ_JT

Thermal

resistance, junction

to board

17

8

°C/W

4

5

6

Thermal

resistance, junction

to case

Thermal

2

characterization

parameter, junction

to package top

outside center

(natural

convection)

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Peripheral operating requirements and behaviors

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions

—Natural Convection (Still Air) with the single layer board horizontal. Board meets JESD51-9 specification.

3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions

—Forced Convection (Moving Air) with the board horizontal.

4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions

—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.

5. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

temperature used for the case temperature. The value includes the thermal resistance of the interface material between

the top of the package and the cold plate.

6. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions

—Natural Convection (Still Air).

5.5 Power sequencing

Voltage supplies must be sequenced in the proper order to avoid damaging internal

diodes. There is no limit on how long after one supply powers up before the next supply

must power up. Note that V_DDand V_{DD_INT}can use the same power source.

The power-up sequence is:

1. V_DD/V_DDA

2. V_{DD_INT}

3. V_{DD_DDR}

The power-down sequence is the reverse:

1. V_{DD_DDR}

2. V_{DD_INT}

3. V_DD/V_DDA

6 Peripheral operating requirements and behaviors

6.1 Core modules

6.1.1 Debug trace timing specifications

Table 12. Debug trace operating behaviors

Symbol

T_cyc

Description

Clock period

Min.

Max.

Unit

MHz

ns

Frequency dependent

T_wl

Low pulse width

2

—

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25

Peripheral operating requirements and behaviors

Table 12. Debug trace operating behaviors (continued)

Symbol

Description

Min.

2

Max.

—

3

Unit

ns

T_wh

T_r

High pulse width

Clock and data rise time

Clock and data fall time

Data setup

—

3

ns

T_f

3

ns

T_s

T_h

—

ns

Data hold

2

ns

TRACECLK

T

r

T

f

T

wh

wl

T

cyc

Figure 5. TRACE_CLKOUT specifications

TRACE_CLKOUT

TRACE_D[3:0]

Ts

Th

Ts

Th

Figure 6. Trace data specifications

6.1.2 JTAG electricals

Table 13. JTAG limited voltage range electricals

Symbol

Description

Min.

Max.

Unit

V

Operating voltage

2.7

3.6

J1

TCLK frequency of operation

• Boundary Scan

MHz

0

10

25

50

• JTAG and CJTAG

• Serial Wire Debug

J2

J3

TCLK cycle period

TCLK clock pulse width

• Boundary Scan

1/J1

—

ns

50

20

—

ns

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Peripheral operating requirements and behaviors

Table 13. JTAG limited voltage range electricals (continued)

Symbol

Description

• JTAG and CJTAG

Min.

10

Max.

Unit

—

ns

• Serial Wire Debug

J4

J5

TCLK rise and fall times

—

20

2.4

—

8

3

ns

Boundary scan input data setup time to TCLK rise

Boundary scan input data hold time after TCLK rise

TCLK low to boundary scan output data valid

TCLK low to boundary scan output high-Z

TMS, TDI input data setup time to TCLK rise

TMS, TDI input data hold time after TCLK rise

TCLK low to TDO data valid

—

25

—

17

—

J6

J7

J8

J9

J10

J11

J12

J13

J14

1

—

100

8

TCLK low to TDO high-Z

TRST assert time

TRST setup time (negation) to TCLK high

Table 14. JTAG full voltage range electricals

Symbol

Description

Min.

Max.

Unit

V

Operating voltage

1.71

3.6

J1

TCLK frequency of operation

• Boundary Scan

MHz

0

10

20

40

• JTAG and CJTAG

• Serial Wire Debug

J2

J3

TCLK cycle period

TCLK clock pulse width

• Boundary Scan

1/J1

—

ns

50

25

—

ns

• JTAG and CJTAG

• Serial Wire Debug

12.5

J4

J5

TCLK rise and fall times

—

20

2.4

—

8

3

—

ns

Boundary scan input data setup time to TCLK rise

Boundary scan input data hold time after TCLK rise

TCLK low to boundary scan output data valid

TCLK low to boundary scan output high-Z

TMS, TDI input data setup time to TCLK rise

TMS, TDI input data hold time after TCLK rise

TCLK low to TDO data valid

J6

—

J7

25

—

J8

J9

J10

J11

J12

J13

J14

1.4

—

100

8

—

22.1

—

TCLK low to TDO high-Z

TRST assert time

TRST setup time (negation) to TCLK high

—

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Peripheral operating requirements and behaviors

J2

J4

J3

TCLK (input)

J4

Figure 7. Test clock input timing

TCLK

J5

J6

Input data valid

Data inputs

Data outputs

J7

Output data valid

J8

J7

Output data valid

Figure 8. Boundary scan (JTAG) timing

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Peripheral operating requirements and behaviors

TCLK

TDI/TMS

TDO

J9

J10

Input data valid

J11

Output data valid

J12

J11

TDO

Output data valid

TDO

Figure 9. Test Access Port timing

TCLK

TRST

J14

J13

Figure 10. TRST timing

6.2 System modules

There are no specifications necessary for the device's system modules.

6.3 Clock modules

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29

Peripheral operating requirements and behaviors

6.3.1 MCG specifications

Table 15. MCG specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

f_{ints_ft}Internal reference frequency (slow clock) —

—

32.768

—

kHz

factory trimmed at nominal VDD and 25 °C

f_{ints_t}

Internal reference frequency (slow clock) — user

trimmed

31.25

—

39.0625

0.6

kHz

Δ_{fdco_res_t}Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using SCTRIM and SCFTRIM

0.3

%f_dco

1

Δf_{dco_res_t}Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using SCTRIM only

—

0.2

4.5

0.5

—

%f_dco

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over fixed voltage and temperature

range of 0–70°C

f_{intf_ft}

f_{intf_t}

f_{loc_low}

f_{loc_high}

Internal reference frequency (fast clock) —

factory trimmed at nominal VDD and 25°C

—

3

4

—

5

MHz

kHz

Internal reference frequency (fast clock) — user

trimmed at nominal VDD and 25 °C

—

Loss of external clock minimum frequency —

RANGE = 00

(3/5) x

f_{ints_t}

—

Loss of external clock minimum frequency —

RANGE = 01, 10, or 11

(16/5) x

f_{ints_t}

FLL

f_{fll_ref}

f_dco

FLL reference frequency range

31.25

20

—

39.0625

25

kHz

DCO output

Low range (DRS=00)

640 × f_{fll_ref}

20.97

MHz

2, 3

frequency range

Mid range (DRS=01)

1280 × f_{fll_ref}

40

60

80

—

41.94

62.91

83.89

23.99

47.97

71.99

95.98

50

75

100

—

MHz

ps

Mid-high range (DRS=10)

1920 × f_{fll_ref}

High range (DRS=11)

2560 × f_{fll_ref}

f_{dco_t_DMX32}DCO output

frequency

Low range (DRS=00)

732 × f_{fll_ref}

4, 5

Mid range (DRS=01)

1464 × f_{fll_ref}

—

Mid-high range (DRS=10)

2197 × f_{fll_ref}

—

High range (DRS=11)

2929 × f_{fll_ref}

—

J_{cyc_fll}

FLL period jitter

—

180

—

Table continues on the next page...

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Table 15. MCG specifications (continued)

Symbol Description

• f_VCO= 48 MHz

Min.

Typ.

Max.

Unit

Notes

—

150

—

• f_VCO= 98 MHz

t_{fll_acquire}FLL target frequency acquisition time

—

1

ms

6

PLL0,1

f_{pll_ref}

PLL reference frequency range

8

180

90

—

16

360

180

—

MHz

f_{vcoclk_2x}VCO output frequency

f_vcoclk

f_{vcoclk_90}PLL quadrature output frequency

I_pllPLL0 operating current

PLL output frequency

—

MHz

2.8

4.7

2.3

mA

• VCO @ 184 MHz (f_{osc_hi_1}= 32 MHz, f_{pll_ref}

= 8 MHz, VDIV multiplier = 23)

I_pll

PLL0 operating current

7

8

9

—

• VCO @ 360 MHz (f_{osc_hi_1}= 32 MHz, f_{pll_ref}

= 8 MHz, VDIV multiplier = 45)

I_pll

PLL1 operating current

• VCO @ 184 MHz (f_{osc_hi_1}= 32 MHz, f_{pll_ref}

= 8 MHz, VDIV multiplier = 23)

I_pll

PLL1 operating current

—

3.6

—

mA

s

• VCO @ 360 MHz (f_{osc_hi_1}= 32 MHz, f_{pll_ref}

= 8 MHz, VDIV multiplier = 45)

t_{pll_lock}

Lock detector detection time

100 × 10^-6

+ 1075(1/

f_{pll_ref}

)

J_{cyc_pll}

PLL period jitter (RMS)

• f_vco= 180 MHz

—

100

75

—

ps

• f_vco= 360 MHz

J_{acc_pll}

PLL accumulated jitter over 1µs (RMS)

• f_vco= 180 MHz

10

—

600

300

—

ps

• f_vco= 360 MHz

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

mode).

2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.

3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation

(Δf_{dco_t}) over voltage and temperature should be considered.

4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.

5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

7. Excludes any oscillator currents that are also consuming power while PLL is in operation.

8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled

(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes

it is already running.

9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of

each PCB and results will vary.

10. Accumulated jitter depends on VCO frequency and VDIV.

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6.3.2 Oscillator electrical specifications

6.3.2.1 Oscillator DC electrical specifications

Table 16. Oscillator DC electrical specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_DD

Supply voltage

1.71

—

3.6

V

I_DDOSC

Supply current — low-power mode (HGO=0)

1

• 32 kHz

—

500

200

300

950

1.2

—

nA

μA

mA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

• 24 MHz

• 32 MHz

1.5

I_DDOSC

Supply current — high-gain mode (HGO=1)

1

• 32 kHz

—

25

400

500

2.5

3

—

μA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

μA

mA

• 24 MHz

• 32 MHz

4

C_x

C_y

R_F

EXTAL load capacitance

XTAL load capacitance

—

2, 3

2, 4

Feedback resistor — low-frequency, low-power

mode (HGO=0)

MΩ

kΩ

Feedback resistor — low-frequency, high-gain

mode (HGO=1)

—

10

—

Feedback resistor — high-frequency, low-power

mode (HGO=0)

Feedback resistor — high-frequency, high-gain

mode (HGO=1)

1

R_S

Series resistor — low-frequency, low-power

mode (HGO=0)

—

Series resistor — low-frequency, high-gain mode

(HGO=1)

200

—

kΩ

Series resistor — high-frequency, low-power

mode (HGO=0)

kΩ

Series resistor — high-frequency, high-gain

mode (HGO=1)

—

0

—

kΩ

Table continues on the next page...

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Table 16. Oscillator DC electrical specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

5

V_pp

Peak-to-peak amplitude of oscillation (oscillator

—

0.6

—

V

mode) — low-frequency, low-power mode

(HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, high-gain mode

(HGO=1)

—

V_DD

0.6

—

V

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, low-power mode

(HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, high-gain mode

(HGO=1)

V_DD

1. V_DD=3.3 V, Temperature =25 °C

2. See crystal or resonator manufacturer's recommendation

3. C_xand C_ycan be provided by using either integrated capacitors or external components.

4. When low-power mode is selected, R_Fis integrated and must not be attached externally.

5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any

other device.

6.3.2.2 Oscillator frequency specifications

Table 17. Oscillator frequency specifications

Symbol Description

f_{osc_lo}Oscillator crystal or resonator frequency — low-

frequency mode (MCG_C2[RANGE]=00)

Min.

Typ.

Max.

Unit

Notes

32

—

40

kHz

f_{osc_hi_1}Oscillator crystal or resonator frequency — high-

frequency mode (low range)

3

8

—

8

MHz

1

(MCG_C2[RANGE]=01)

f_{osc_hi_2}Oscillator crystal or resonator frequency — high

frequency mode (high range)

32

(MCG_C2[RANGE]=1x)

f_{ec_extal}

t_{dc_extal}

t_cst

Input clock frequency (external clock mode)

Input clock duty cycle (external clock mode)

—

40

—

50

60

—

MHz

%

2, 3

4, 5

Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0)

1000

ms

Crystal startup time — 32 kHz low-frequency,

high-gain mode (HGO=1)

—

500

0.6

—

ms

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), low-power mode

(HGO=0)

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), high-gain mode

(HGO=1)

—

1

—

ms

1. Frequencies less than 8 MHz are not in the PLL range.

2. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.

3. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

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4. Proper PC board layout procedures must be followed to achieve specifications.

5. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register

being set.

NOTE

The 32 kHz oscillator works in low power mode by default and

cannot be moved into high power/gain mode.

6.3.3 32 kHz oscillator electrical characteristics

6.3.3.1 32 kHz oscillator DC electrical specifications

Table 18. 32kHz oscillator DC electrical specifications

Symbol

V_BAT

R_F

Description

Min.

1.71

—

Typ.

—

Max.

3.6

—

Unit

V

Supply voltage

Internal feedback resistor

Parasitical capacitance of EXTAL32 and XTAL32

Peak-to-peak amplitude of oscillation

100

5

MΩ

pF

V

C_para

—

7

1

V_pp

—

0.6

—

1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices.

6.3.3.2 32 kHz oscillator frequency specifications

Table 19. 32 kHz oscillator frequency specifications

Symbol Description

Min.

—

Typ.

32.768

1000

—

Max.

—

Unit

kHz

ms

Notes

f_{osc_lo}

t_start

Oscillator crystal

Crystal start-up time

—

1

v_{ec_extal32}Externally provided input clock amplitude

700

V_BAT

mV

2, 3

1. Proper PC board layout procedures must be followed to achieve specifications.

2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The

oscillator remains enabled and XTAL32 must be left unconnected.

3. The parameter specified is a peak-to-peak value and V_IHand V_ILspecifications do not apply. The voltage of the applied

clock must be within the range of V_SSto V_BAT

.

6.4 Memories and memory interfaces

6.4.1 Flash (FTFE) electrical specifications

This section describes the electrical characteristics of the FTFE module.

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6.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps are

active and do not include command overhead.

Table 20. NVM program/erase timing specifications

Symbol Description

Min.

—

Typ.

7.5

Max.

18

Unit

μs

Notes

t_hvpgm8

Program Phrase high-voltage time

t_hversscrErase Flash Sector high-voltage time

t_hversblk128kErase Flash Block high-voltage time for 128 KB

t_hversblk256kErase Flash Block high-voltage time for 256 KB

—

13

113

ms

1

—

104

208

1808

3616

—

1. Maximum time based on expectations at cycling end-of-life.

6.4.1.2 Flash timing specifications — commands

Table 21. Flash command timing specifications

Symbol Description

Read 1s Block execution time

Min.

Typ.

Max.

Unit

Notes

t_rd1blk128k

t_rd1blk256k

• 128 KB data flash

• 256 KB program flash

256 KB data flash

—

0.5

1.0

ms

t_rd1sec4kRead 1s Section execution time (4 KB flash)

—

70

100

80

μs

1

t_pgmchk

t_rdrsrc

Program Check execution time

Read Resource execution time

Program Phrase execution time

Erase Flash Block execution time

• 128 KB data flash

40

t_pgm8

150

2

t_ersblk128k

t_ersblk256k

—

110

220

925

ms

• 256 KB program flash

1850

256 KB data flash

t_ersscr

Erase Flash Sector execution time

—

15

20

115

—

ms

2

t_pgmsec4kProgram Section execution time (4KB flash)

Read 1s All Blocks execution time

t_rd1allx

t_rd1alln

• FlexNVM devices

—

3.4

ms

• Program flash only devices

t_rdonce

Read Once execution time

—

70

30

—

μs

ms

μs

1

t_pgmonceProgram Once execution time

t_ersall

Erase All Blocks execution time

Verify Backdoor Access Key execution time

Swap Control execution time

650

—

5600

30

2

1

t_vfykey

Table continues on the next page...

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Table 21. Flash command timing specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

t_swapx01

t_swapx02

t_swapx04

t_swapx08

• control code 0x01

—

200

—

μs

• control code 0x02

• control code 0x04

• control code 0x08

—

70

—

150

30

μs

Program Partition for EEPROM execution time

• 64 KB EEPROM backup

t_pgmpart64k

t_pgmpart256k

—

235

240

—

ms

• 256 KB EEPROM backup

Set FlexRAM Function execution time:

• Control Code 0xFF

t_setramff

t_setram64k

t_setram128k

t_setram256k

—

205

1.6

2.7

4.8

—

μs

ms

• 64 KB EEPROM backup

• 128 KB EEPROM backup

• 256 KB EEPROM backup

2.5

3.8

6.2

t _eewr8bersByte-write to erased FlexRAM location execution

time

—

140

225

μs

3

Byte-write to FlexRAM execution time:

t_eewr8b64k

t_eewr8b128k

t_eewr8b256k

• 64 KB EEPROM backup

• 128 KB EEPROM backup

• 256 KB EEPROM backup

—

400

450

525

1700

1800

2000

μs

t _eewr16bers16-bit write to erased FlexRAM location

execution time

—

140

225

μs

16-bit write to FlexRAM execution time:

t_eewr16b64k

t_eewr16b128k

t_eewr16b256k

• 64 KB EEPROM backup

• 128 KB EEPROM backup

• 256 KB EEPROM backup

—

400

450

525

1700

1800

2000

μs

t_eewr32bers32-bit write to erased FlexRAM location

execution time

—

180

275

μs

32-bit write to FlexRAM execution time:

t_eewr32b64k

t_eewr32b128k

t_eewr32b256k

• 64 KB EEPROM backup

• 128 KB EEPROM backup

• 256 KB EEPROM backup

—

475

525

600

1850

2000

2200

μs

1. Assumes 25MHz or greater flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.

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6.4.1.3 Flash high voltage current behaviors

Table 22. Flash high voltage current behaviors

Symbol

Description

Min.

Typ.

3.5

Max.

Unit

I_{DD_PGM}

Average current adder during high voltage flash

programming operation

—

7.5

mA

I_{DD_ERS}

Average current adder during high voltage flash

erase operation

—

1.5

4.0

mA

6.4.1.4 Reliability specifications

Table 23. NVM reliability specifications

Symbol Description

Min.

Typ.¹

Max.

Unit

Notes

Program Flash

t_nvmretp10kData retention after up to 10 K cycles

t_nvmretp1kData retention after up to 1 K cycles

n_nvmcycpCycling endurance

5

50

—

years

cycles

20

100

50 K

10 K

2

Data Flash

t_nvmretd10kData retention after up to 10 K cycles

t_nvmretd1kData retention after up to 1 K cycles

n_nvmcycdCycling endurance

5

50

—

years

cycles

20

100

50 K

10 K

FlexRAM as EEPROM

t_nvmretee100Data retention up to 100% of write endurance

t_nvmretee10Data retention up to 10% of write endurance

n_nvmcyceeCycling endurance for EEPROM backup

Write endurance

5

50

—

years

cycles

20

100

50 K

20 K

2

3

n_nvmwree16

n_nvmwree128

n_nvmwree512

n_nvmwree2k

• EEPROM backup to FlexRAM ratio = 16

• EEPROM backup to FlexRAM ratio = 128

• EEPROM backup to FlexRAM ratio = 512

• EEPROM backup to FlexRAM ratio = 2,048

70 K

630 K

2.5 M

10 M

175 K

1.6 M

6.4 M

25 M

—

writes

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant

25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering

Bulletin EB619.

2. Cycling endurance represents number of program/erase cycles at -40°C ≤ T_j≤ 125°C.

3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling

endurance of the FlexNVM and the allocated EEPROM backup per subsystem. Minimum and typical values assume all 16-

bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.

6.4.1.5 Write endurance to FlexRAM for EEPROM

When the FlexNVM partition code is not set to full data flash, the EEPROM data set size

can be set to any of several non-zero values.

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Peripheral operating requirements and behaviors

The bytes not assigned to data flash via the FlexNVM partition code are used by the

FTFE to obtain an effective endurance increase for the EEPROM data. The built-in

EEPROM record management system raises the number of program/erase cycles that can

be attained prior to device wear-out by cycling the EEPROM data through a larger

EEPROM NVM storage space.

While different partitions of the FlexNVM are available, the intention is that a single

choice for the FlexNVM partition code and EEPROM data set size is used throughout the

entire lifetime of a given application. The EEPROM endurance equation and graph

shown below assume that only one configuration is ever used.

EEPROM – 2 × EEESPLIT × EEESIZE

Writes_subsystem =

× Write_efficiency × n_nvmcycee

EEESPLIT × EEESIZE

where

• Writes_subsystem — minimum number of writes to each FlexRAM location for

subsystem (each subsystem can have different endurance)

• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART;

entered with the Program Partition command

• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program

Partition command

• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program

Partition command

• Write_efficiency —

• 0.25 for 8-bit writes to FlexRAM

• 0.50 for 16-bit or 32-bit writes to FlexRAM

• n_nvmcycee— EEPROM-backup cycling endurance

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Figure 11. EEPROM backup writes to FlexRAM

6.4.2 EzPort switching specifications

Table 24. EzPort switching specifications

Num

Description

Min.

Max.

3.6

Unit

V

Operating voltage

1.71

EP1

EZP_CK frequency of operation (all commands except

READ)

—

f_SYS/2

MHz

EP1a

EP2

EP3

EP4

EP5

EP6

EP7

EP8

EP9

EZP_CK frequency of operation (READ command)

EZP_CS negation to next EZP_CS assertion

EZP_CS input valid to EZP_CK high (setup)

EZP_CK high to EZP_CS input invalid (hold)

EZP_D input valid to EZP_CK high (setup)

EZP_CK high to EZP_D input invalid (hold)

EZP_CK low to EZP_Q output valid

—

f_SYS/8

—

MHz

ns

2 x t_{EZP_CK}

5

—

ns

—

ns

2

—

ns

5

—

ns

—

0

16

—

ns

EZP_CK low to EZP_Q output invalid (hold)

EZP_CS negation to EZP_Q tri-state

ns

—

12

ns

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EZP_CK

EP2

EP3

EP4

EZP_CS

EP9

EP8

EP7

EZP_Q (output)

EZP_D (input)

EP5

EP6

Figure 12. EzPort Timing Diagram

6.4.3 NAND flash controller specifications

The NAND flash controller (NFC) implements the interface to standard NAND flash

memory devices. This section describes the timing parameters of the NFC.

In the following table:

• T_His the flash clock high time and

• T_Lis flash clock low time,

which are defined as:

T_{input clock}

T_NFC= T_L+ T_H

=

SCALER

The SCALER value is derived from the fractional divider specified in the SIM's

CLKDIV4 register:

SIM_CLKDIV4[NFCFRAC] + 1

SIM_CLKDIV4[NFCDIV] + 1

=

SCALER

In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%,

means T_H= T_L. In case the reciprocal of SCALER is not an integer:

T_NFC

T_L= (1 + SCALER / 2) x

2

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Peripheral operating requirements and behaviors

T_NFC

2

T_H= (1 – SCALER / 2) x

For example, if SCALER is 0.2, then T_H= T_L= T_NFC/2.

T_NFC

T_HT_L

However, if SCALER is 0.667, then T_L= 2/3 x T_NFCand T_H= 1/3 x T_NFC

.

T_NFC

T_HT_L

NOTE

The reciprocal of SCALER must be a multiple of 0.5. For

example, 1, 1.5, 2, 2.5, etc.

Table 25. NFC specifications

Num

t_CLS

t_CLH

t_CS

Description

NFC_CLE setup time

NFC_CLE hold time

NFC_CEn setup time

NFC_CEn hold time

NFC_WP pulse width

NFC_ALE setup time

NFC_ALE hold time

Data setup time

Min.

2T_H+ T_L– 1

T_H+ T_L– 1

2T_H+ T_L– 1

T_H+ T_L

Max.

—

Unit

ns

t_CH

t_WP

t_ALS

t_ALH

t_DS

T_L– 1

2T_H+ T_L

T_H+ T_L

T_L– 1

t_DH

Data hold time

T_H– 1

t_WC

t_WH

t_RR

Write cycle time

T_H+ T_L– 1

T_H– 1

NFC_WE hold time

Ready to NFC_RE low

NFC_RE pulse width

Read cycle time

4T_H+ 3T_L+ 90

T_L+ 1

t_RP

t_RC

T_L+ T_H– 1

T_H– 1

t_REH

t_IS

NFC_RE high hold time

Data input setup time

11

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Peripheral operating requirements and behaviors

NFC_CLE

NFC_CEn

NFC_WE

NFC_IOn

tCLS

tCS

tCLH

tCH

tWP

tDS

tDH

Figure 13. Command latch cycle timing

NFC_ALE

NFC_CEn

NFC_WE

NFC_IOn

tALS

tCS

tALH

tCH

tWP

tDS

tDH

address

Figure 14. Address latch cycle timing

tCS

tCH

tWC

NFC_CEn

NFC_WE

NFC_IOn

tWP

tDS

tWH

tDH

data

Figure 15. Write data latch cycle timing

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tCH

tRC

tRP

NFC_CEn

NFC_RE

NFC_IOn

NFC_RB

tREH

tIS

data

tRR

Figure 16. Read data latch cycle timing in Slow mode

tCH

tRC

tRP

NFC_CEn

NFC_RE

NFC_IOn

NFC_RB

tREH

tIS

data

tRR

Figure 17. Read data latch cycle timing in Fast mode and EDO mode

6.4.4 DDR controller specifications

The following timing numbers must be followed to properly latch or drive data onto the

DDR memory bus. All timing numbers are relative to the DQS byte lanes.

Table 26. DDR controller — AC timing specifications

Symbol

Description

Frequency of operation

• DDR1

Min.

Max.

Unit

Notes

2

83.3

125¹

50

150

MHz

• DDR2

• LPDDR

t_DDRCK

Clock period

• DDR1

6.6

12

8

ns

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 26. DDR controller — AC timing specifications (continued)

Symbol

Description

Min.

Max.

Unit

Notes

• DDR2

6.6

20

ns

• LPDDR

V_OX-AC

DDRCK AC differential cross point voltage

0.5 x V_{DD_DDR}0.5 x V_{DD_DDR}

– 0.2 V + 0.2 V

V

• DDR1

• DDR2

• LPDDR

0.5 x V_{DD_DDR}0.5 x V_{DD_DDR}

– 0.125 V + 0.125 V

0.4 x V_{DD_DDR}0.4 x V_{DD_DDR}

t_DDRCKH

t_DDRCKL

t_CMV

Pulse width high

Pulse width low

0.45

0.55

—

t_DDRCK

ns

3

4

Address, DDR_CKE, DDR_CAS, DDR_RAS,

DDR_WE, DDR_CSn — output setup

0.5 x t_DDRCK

1

–

t_CMH

Address, DDR_CKE, DDR_CAS, DDR_RAS,

DDR_WE, DDR_CSn — output hold

0.5 x t_DDRCK

1

—

ns

t_DQSS

t_QS

DQS rising edge to CK rising edge

-0.2 x t_DDRCK

0.2 x t_DDRCK

—

ns

Data and data mask output setup (DQ→DQS)

relative to DQS (DDR write mode)

0.25 x t_DDRCK

1

–

5, 6

7

t_QH

Data and data mask output hold (DQS→DQ)

relative to DQS (DDR write mode)

0.25 x t_DDRCK

1

–

—

ns

t_DQSQ

DQS-DQ skew for DQS and associated DQ

signals

– (0.25 x

t_DDRCK– 1)

0.25 x t_DDRCK

1

–

8

1. This is minimum frequency of operation according to JEDEC DDR2 specification.

2. DDR data rate = 2 x DDR clock frequency

3. Pulse width high plus pulse width low cannot exceed min and max clock period.

4. Command output setup should be 1/2 the memory bus clock (t_DDRCK) plus some minor adjustments for process,

temperature, and voltage variations.

5. This specification relates to the required input setup time of DDR memories. The microprocessor's output setup should be

larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.

DDR_DQ[15:8] is relative to DDR_DQS[1]; DDR_DQ[7:0] is relative to DDR_DQS[0].

6. The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats

are valid for each subsequent DQS edge.

7. This specification relates to the required hold time of DDR memories. DDR_DQ[15:8] is relative to DDR_DQS[1];

DDR_DQ[7:0] is relative to DDR_DQS[0]

8. Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line

becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or

other factors).

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1

2

3

4

5

6

7

8

9

10

tDDRCKH

tDDRCK

tDDRCKL

DDR_CLK

DDR__CLK

tCMH

tCMV

DDR_CSn, DDR_WE

DDR_CAS, DDR_RAS

CMD

DDR_An

ROW

COL

tDQSS

DDR_DQSn

DDR_DMn

DDR_DQn

tQH

tQS

WD1

WD2

WD3

WD4

Figure 18. DDR write timing

1

2

3

tDDRCK

4

5

6

7

8

9

10

11

12

tDDRCHH

tDDRCKL

DDR_CLK

tCMH

DDR__CLK

tCMV

DDR_CSn, DDR_WE

DDR_CAS, DDR_RAS

CMD

COL

DDR_An

ROW

CL=2.5

DDR_DQS

(CL=2.5 )

DQS read preamble

DDR_DQn

RD1

RD2

RD1

RD3

RD4

RD3

CL=3.0

DDR_DQS

(CL=3.0 )

DQS read preamble

DDR_DQn

RD2

RD4

1

2

3

4

5

6

7

8

9

10

11

12

Figure 19. DDR read timing

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Peripheral operating requirements and behaviors

Figure 20. DDR read timing, DQ vs. DQS

6.4.5 Flexbus switching specifications

All processor bus timings are synchronous; input setup/hold and output delay are given in

respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be

the same as the internal system bus frequency or an integer divider of that frequency.

The following timing numbers indicate when data is latched or driven onto the external

bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be

derived from these values.

Table 27. Flexbus limited voltage range switching specifications

Num

Description

Min.

2.7

—

Max.

3.6

Unit

V

Notes

Operating voltage

Frequency of operation

Clock period

FB_CLK

—

MHz

ns

FB1

FB2

FB3

FB4

FB5

20

Address, data, and control output valid

Address, data, and control output hold

Data and FB_TA input setup

Data and FB_TA input hold

—

11.5

—

ns

1

2

0.5

8.5

0.5

ns

—

ns

—

ns

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,

and FB_TS.

2. Specification is valid for all FB_AD[31:0] and FB_TA.

Table 28. Flexbus full voltage range switching specifications

Num

Description

Min.

Max.

3.6

Unit

V

Notes

Operating voltage

1.71

Frequency of operation

Clock period

—

FB_CLK

—

MHz

ns

FB1

FB2

FB3

1/FB_CLK

Address, data, and control output valid

Address, data, and control output hold

—

0

13.5

—

ns

1

ns

Table continues on the next page...

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Table 28. Flexbus full voltage range switching specifications (continued)

Num

FB4

FB5

Description

Min.

13.7

0.5

Max.

—

Unit

ns

Notes

Data and FB_TA input setup

Data and FB_TA input hold

2

—

ns

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,

and FB_TS.

2. Specification is valid for all FB_AD[31:0] and FB_TA.

Read Timing Parameters

S0

S1

S2

S3

S0

FB1

FB_CLK

FB_A[Y]

FB_D[X]

FB_RW

FB5

FB3

Address

FB4

FB2

Address

Data

FB_TS

FB_ALE

FB_CSn

FB_OEn

FB_BEn

FB_TA

AA=1

AA=0

FB4

FB5

AA=1

AA=0

FB_TSIZ[1:0]

TSIZ

S1

S0

S2

S3

S0

Figure 21. FlexBus read timing diagram

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Peripheral operating requirements and behaviors

Write Timing Parameters

FB1

FB_CLK

FB2

FB3

FB_A[Y]

FB_D[X]

FB_RW

Address

Data

FB_TS

FB_ALE

FB_CSn

FB_OEn

FB_BEn

FB_TA

AA=1

AA=0

FB4

FB5

AA=1

AA=0

FB_TSIZ[1:0]

TSIZ

Figure 22. FlexBus write timing diagram

6.5 Security and integrity modules

6.5.1 DryIce Tamper Electrical Specifications

Information about security-related modules is not included in this document and is

available only after a nondisclosure agreement (NDA) has been signed. To request an

NDA, please contact your local NXP sales representative.

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6.6 Analog

6.6.1 ADC electrical specifications

The 16-bit accuracy specifications listed in Table 29 and Table 30 are achievable on the

differential pins ADCx_DP0, ADCx_DM0.

The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are

not direct device pins. Accuracy specifications for these pins are defined in Table 31 and

Table 32.

All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy

specifications.

6.6.1.1 16-bit ADC operating conditions

Table 29. 16-bit ADC operating conditions

Symbol Description

Conditions

Min.

1.71

-100

1.13

Typ.¹

Max.

3.6

Unit

V

Notes

V_DDA

ΔV_DDA

ΔV_SSA

V_REFH

Supply voltage

Ground voltage

Absolute

—

Delta to V_DD(V_DD– V_DDA

)

0

+100

V_DDA

mV

V

2

Delta to V_SS(V_SS– V_SSA

)

0

ADC reference

voltage high

V_DDA

V_REFL

V_ADIN

ADC reference

voltage low

V_SSA

V

Input voltage

• 16-bit differential mode

• All other modes

• 16-bit mode

VREFL

—

31/32 ×

VREFH

C_ADIN

Input capacitance

—

8

4

10

5

pF

• 8-bit / 10-bit / 12-bit

modes

R_ADIN

R_AS

Input series

resistance

—

2

5

kΩ

Analog source

resistance

(external)

13-bit / 12-bit modes

f_ADCK< 4 MHz

3

—

f_ADCK

C_rate

ADC conversion ≤ 13-bit mode

clock frequency

1.0

2.0

—

18.0

12.0

MHz

4

5

ADC conversion 16-bit mode

clock frequency

ADC conversion ≤ 13-bit modes

rate

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 29. 16-bit ADC operating conditions (continued)

Symbol Description

Conditions

Min.

Typ.¹

Max.

Unit

Notes

No ADC hardware averaging

20.000

—

818.330

kS/s

Continuous conversions

enabled, subsequent

conversion time

C_rate

ADC conversion 16-bit mode

5

rate

No ADC hardware averaging

37.037

—

461.467

kS/s

Continuous conversions

enabled, subsequent

conversion time

1. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The R_AS/C_AS

time constant should be kept to < 1 ns.

4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

SIMPLIFIED

INPUT PIN EQUIVALENT

ZADIN

CIRCUIT

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

leakage

ZAS

ADC SAR

ENGINE

RAS

RADIN

VADIN

CAS

VAS

RADIN

INPUT PIN

CADIN

Figure 23. ADC input impedance equivalency diagram

6.6.1.2 16-bit ADC electrical characteristics

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Table 30. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Symbol Description

Conditions¹

Min.

0.215

1.2

Typ.²

Max.

1.7

3.9

6.1

7.3

9.5

Unit

mA

Notes

I_{DDA_ADC}Supply current

—

3

ADC asynchronous

clock source

• ADLPC = 1, ADHSC = 0

• ADLPC = 1, ADHSC = 1

• ADLPC = 0, ADHSC = 0

• ADLPC = 0, ADHSC = 1

2.4

4.0

5.2

6.2

MHz

t_ADACK= 1/

f_ADACK

2.4

f_ADACK

3.0

4.4

Sample Time

See Reference Manual chapter for sample times

TUE

DNL

Total unadjusted

error

• 12-bit modes

• <12-bit modes

—

4

6.8

2.1

LSB⁴

5

1.4

Differential non-

linearity

• 12-bit modes

• <12-bit modes

—

0.7

0.2

–1.1 to

+1.9

–0.3 to

0.5

INL

Integral non-linearity

• 12-bit modes

• <12-bit modes

—

1.0

0.5

–2.7 to

+1.9

LSB⁴

5

–0.7 to

+0.5

5

E_FS

E_Q

Full-scale error

• 12-bit modes

• <12-bit modes

• 16-bit modes

• ≤13-bit modes

—

–4

–1.4

–1 to 0

—

–5.4

–1.8

—

LSB⁴

V_ADIN= V_DDA

Quantization error

0.5

ENOB Effective number of 16-bit differential mode

6

bits

12.8

11.9

14.5

13.8

—

bits

• Avg = 32

• Avg = 4

16-bit single-ended mode

• Avg = 32

12.2

11.4

13.9

13.1

—

bits

dB

• Avg = 4

Signal-to-noise plus See ENOB

SINAD

6.02 × ENOB + 1.76

distortion

THD

Total harmonic

distortion

16-bit differential mode

• Avg = 32

7

dB

—

-94

-85

—

16-bit single-ended mode

• Avg = 32

—

SFDR Spurious free

dynamic range

16-bit differential mode

• Avg = 32

—

dB

82

78

95

90

16-bit single-ended mode

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 30. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Symbol Description

Conditions¹

Min.

Typ.²

Max.

Unit

Notes

• Avg = 32

E_IL

Input leakage error

I_In× R_AS

mV

I_In= leakage

current

(refer to the

MCU's voltage

and current

operating

ratings)

Temp sensor slope

Across the full temperature

range of the device

1.55

706

1.62

716

1.69

726

mV/°C

mV

8

V_TEMP25Temp sensor voltage 25 °C

8

1. All accuracy numbers assume the ADC is calibrated with V_REFH= V_DDA

2. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1

MHz ADC conversion clock speed.

4. 1 LSB = (V_REFH- V_REFL)/2^N

5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)

6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

8. ADC conversion clock < 3 MHz

Typical ADC 16-bit Differential ENOB vs ADC Clock

100Hz, 90% FS Sine Input

15.00

14.70

14.40

14.10

13.80

13.50

13.20

12.90

12.60

Hardware Averaging Disabled

Averaging of 4 samples

12.30

12.00

Averaging of 8 samples

Averaging of 32 samples

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 24. Typical ENOB vs. ADC_CLK for 16-bit differential mode

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Typical ADC 16-bit Single-Ended ENOB vs ADC Clock

100Hz, 90% FS Sine Input

14.00

13.75

13.50

13.25

13.00

12.75

12.50

12.25

12.00

11.75

11.50

11.25

11.00

Averaging of 4 samples

Averaging of 32 samples

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 25. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

6.6.1.3 16-bit ADC with PGA operating conditions

Table 31. 16-bit ADC with PGA operating conditions

Symbol Description

V_DDASupply voltage

V_REFPGAPGA ref voltage

Conditions

Min.

Typ.¹

Max.

Unit

V

Notes

Absolute

1.71

—

3.6

VREF_OU VREF_OU VREF_OU

V

2, 3

T

V_ADIN

V_CM

Input voltage

V_SSA

—

V_DDA

V

Input Common

Mode range

R_PGAD

Differential input Gain = 1, 2, 4, 8

—

128

64

—

kΩ

IN+ to IN-⁴

impedance

Gain = 16, 32

Gain = 64

32

R_AS

T_S

Analog source

resistance

100

Ω

µs

5

6

7

ADC sampling

time

1.25

—

C_rate

ADC conversion ≤ 13 bit modes

18.484

450

Ksps

rate

No ADC hardware

averaging

Continuous conversions

enabled

Peripheral clock = 50

MHz

16 bit modes

37.037

—

250

Ksps

8

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Table 31. 16-bit ADC with PGA operating conditions

Symbol Description

Conditions

Min.

Typ.¹

Max.

Unit

Notes

No ADC hardware

averaging

Continuous conversions

enabled

Peripheral clock = 50

MHz

1. Typical values assume V_DDA= 3.0 V, Temp = 25°C, f_ADCK= 6 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

2. ADC must be configured to use the internal voltage reference (VREF_OUT)

3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other

than the output of the VREF module, the VREF module must be disabled.

4. For single ended configurations the input impedance of the driven input is R_PGAD/2

5. The analog source resistance (R_AS), external to MCU, should be kept as minimum as possible. Increased R_AScauses drop

in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.

6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs

time should be allowed for F_in=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at

8 MHz ADC clock.

7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1

8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1

6.6.1.4 16-bit ADC with PGA characteristics

Table 32. 16-bit ADC with PGA characteristics

Symbol

Description

Conditions

Min.

Typ.¹

Max.

Unit

Notes

I_{DDA_PGA}Supply current

Low power

—

420

644

μA

2

(ADC_PGA[PGALPb]=0)

I_{DC_PGA}

Input DC current

A

3

Gain =1, V_REFPGA=1.2V,

V_CM=0.5V

—

1.54

0.57

—

μA

Gain =64, V_REFPGA=1.2V,

V_CM=0.1V

G

Gain⁴

• PGAG=0

• PGAG=1

• PGAG=2

• PGAG=3

• PGAG=4

• PGAG=5

• PGAG=6

0.95

1.9

1

2

1.05

2.1

R_AS< 100Ω

3.8

4

4.2

7.6

8

8.4

15.2

30.0

58.8

16

31.6

63.3

16.6

33.2

67.8

BW

Input signal

bandwidth

• 16-bit modes

• < 16-bit modes

—

4

kHz

dB

40

—

PSRR

Power supply

rejection ratio

Gain=1

-84

V_DDA= 3V

100mV,

Table continues on the next page...

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Table 32. 16-bit ADC with PGA characteristics (continued)

Symbol

Description

Conditions

Min.

Typ.¹

Max.

Unit

Notes

f_VDDA= 50Hz,

60Hz

CMRR

Common mode

rejection ratio

• Gain=1

—

-84

-85

—

dB

V_CM=

500mVpp,

f_VCM= 50Hz,

100Hz

• Gain=64

V_OFS

Input offset

voltage

• Chopping disabled

(ADC_PGA[PGACHPb]

=1)

—

2.4

0.2

—

mV

Output offset =

V_OFS*(Gain+1)

• Chopping enabled

(ADC_PGA[PGACHPb]

=0)

T_GSW

Gain switching

settling time

—

10

µs

5

dG/dT

Gain drift over full

temperature range

• Gain=1

• Gain=64

—

6

31

10

42

ppm/°C

%/V

dG/dV_DDAGain drift over

supply voltage

• Gain=1

• Gain=64

0.07

0.21

0.31

V_DDAfrom 1.71

to 3.6V

0.14

%/V

E_IL

Input leakage

error

All modes

I_In× R_AS

mV

I_In= leakage

current

(refer to the

MCU's voltage

and current

operating

ratings)

V_PP,DIFFMaximum

differential input

V

6

signal swing

where V_X= V_REFPGA× 0.583

SNR

THD

Signal-to-noise

ratio

• Gain=1

80

52

90

66

—

dB

16-bit

differential

mode,

• Gain=64

Average=32

Total harmonic

distortion

• Gain=1

85

49

100

95

—

dB

16-bit

differential

mode,

• Gain=64

Average=32,

f_in=100Hz

SFDR

ENOB

Spurious free

dynamic range

• Gain=1

85

53

105

88

—

dB

16-bit

differential

mode,

Average=32,

f_in=100Hz

• Gain=64

Effective number

of bits

• Gain=1, Average=4

• Gain=1, Average=8

• Gain=64, Average=4

• Gain=64, Average=8

11.6

8.0

13.4

13.6

9.6

—

bits

16-bit

differential

mode,f_in=100Hz

7.2

6.3

9.6

12.8

14.5

Table continues on the next page...

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Table 32. 16-bit ADC with PGA characteristics (continued)

Symbol

Description

Conditions

• Gain=1, Average=32

Min.

Typ.¹

Max.

Unit

Notes

11.0

14.3

—

bits

• Gain=2, Average=32

• Gain=4, Average=32

• Gain=8, Average=32

• Gain=16, Average=32

• Gain=32, Average=32

• Gain=64, Average=32

7.9

7.3

6.8

7.5

13.8

13.1

12.5

11.5

10.6

—

bits

SINAD

Signal-to-noise

plus distortion

ratio

See ENOB

6.02 × ENOB + 1.76

dB

1. Typical values assume V_DDA=3.0V, Temp=25°C, f_ADCK=6MHz unless otherwise stated.

2. This current is a PGA module adder, in addition to ADC conversion currents.

3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong

function of input common mode voltage (V_CM) and the PGA gain.

4. Gain = 2^PGAG

5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.

6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the

PGA reference voltage and gain setting.

6.6.2 CMP and 6-bit DAC electrical specifications

Table 33. Comparator and 6-bit DAC electrical specifications

Symbol

V_DD

Description

Min.

1.71

—

Typ.

—

Max.

3.6

Unit

V

Supply voltage

I_DDHS

I_DDLS

V_AIN

Supply current, High-speed mode (EN=1, PMODE=1)

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

—

200

20

μA

V

—

V_SS– 0.3

—

V_DD

20

V_AIO

Analog input offset voltage

Analog comparator hysteresis¹

• CR0[HYSTCTR] = 00

—

mV

V_H

—

5

—

mV

10

20

30

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

V_CMPOh

V_CMPOl

t_DHS

Output high

V_DD– 0.5

—

0.5

200

600

40

V

Output low

—

20

80

—

Propagation delay, high-speed mode (EN=1, PMODE=1)

Propagation delay, low-speed mode (EN=1, PMODE=0)

Analog comparator initialization delay²

6-bit DAC current adder (enabled)

50

250

—

ns

μs

μA

t_DLS

I_DAC6b

7

—

Table continues on the next page...

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Table 33. Comparator and 6-bit DAC electrical specifications (continued)

Symbol

INL

Description

Min.

–0.5

–0.3

Typ.

—

Max.

0.5

Unit

LSB³

LSB

6-bit DAC integral non-linearity

6-bit DAC differential non-linearity

DNL

—

0.3

1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD–0.6 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.

3. 1 LSB = V_reference/64

0.08

0.07

0.06

0.05

0.04

0.03

HYSTCTR

Setting

00

01

10

11

0.02

0.01

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 26. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

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0.18

0.16

0.14

0.12

HYSTCTR

Setting

0.1

00

01

10

11

0.08

0.06

0.04

0.02

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 27. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

6.6.3 12-bit DAC electrical characteristics

6.6.3.1 12-bit DAC operating requirements

Table 34. 12-bit DAC operating requirements

Symbol

V_DDA

V_DACR

C_L

Desciption

Min.

1.71

1.13

—

Max.

3.6

100

1

Unit

V

Notes

Supply voltage

Reference voltage

Output load capacitance

Output load current

V

1

2

pF

mA

I_L

—

1. The DAC reference can be selected to be V_DDAor V_{REF_OUT}

.

2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

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6.6.3.2 12-bit DAC operating behaviors

Table 35. 12-bit DAC operating behaviors

Symbol Description

Min.

Typ.

Max.

150

Unit

Notes

I_{DDA_DACL}Supply current — low-power mode

—

μA

P

I_{DDA_DACH}Supply current — high-speed mode

—

100

15

0.7

—

700

200

30

μA

μs

P

t_DACLPFull-scale settling time (0x080 to 0xF7F) —

low-power mode

1

t_DACHPFull-scale settling time (0x080 to 0xF7F) —

high-power mode

μs

t_CCDACLPCode-to-code settling time (0xBF8 to 0xC08)

— low-power mode and high-speed mode

1

μs

V_dacoutlDAC output voltage range low — high-speed

mode, no load, DAC set to 0x000

100

V_DACR

8

mV

LSB

V_dacouthDAC output voltage range high — high-

speed mode, no load, DAC set to 0xFFF

V_DACR

−100

—

INL

DNL

Integral non-linearity error — high speed

mode

—

2

3

4

Differential non-linearity error — V_DACR> 2

V

—

1

Differential non-linearity error — V_DACR

VREF_OUT

=

—

1

V_OFFSETOffset error

E_GGain error

PSRR Power supply rejection ratio, V_DDA≥ 2.4 V

—

60

—

0.4

0.1

0.8

0.6

90

%FSR

dB

5

—

T_CO

T_GE

Rop

SR

Temperature coefficient offset voltage

Temperature coefficient gain error

Output resistance (load = 3 kΩ)

Slew rate -80h→ F7Fh→ 80h

3.7

—

μV/C

%FSR/C

Ω

6

0.000421

—

250

V/μs

• High power (SP_HP

• Low power (SP_LP

)

1.2

1.7

—

)

0.05

0.12

CT

Channel to channel cross talk

3dB bandwidth

—

-80

dB

BW

kHz

• High power (SP_HP

• Low power (SP_LP

)

550

40

—

)

1. Settling within 1 LSB

2. The INL is measured for 0 + 100 mV to V_DACR−100 mV

3. The DNL is measured for 0 + 100 mV to V_DACR−100 mV

4. The DNL is measured for 0 + 100 mV to V_DACR−100 mV with V_DDA> 2.4 V

5. Calculated by a best fit curve from V_SS+ 100 mV to V_DACR− 100 mV

6. V_DDA= 3.0 V, reference select set for V_DDA(DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to

0x800, temperature range is across the full range of the device

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8

6

4

2

0

-2

-4

-6

-8

0

500

1000

1500

2000

2500

3000

3500

4000

Digital Code

Figure 28. Typical INL error vs. digital code

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1.499

1.4985

1.498

1.4975

1.497

1.4965

1.496

55

85

25

105

125

-40

Temperature °C

Figure 29. Offset at half scale vs. temperature

6.6.4 Voltage reference electrical specifications

Table 36. VREF full-range operating requirements

Symbol

V_DDA

T_A

Description

Supply voltage

Temperature

Min.

Max.

Unit

Notes

1.71

3.6

V

Operating temperature

range of the device

°C

C_L

Output load capacitance

100

nF

1, 2

1. C_Lmust be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external

reference.

2. The load capacitance should not exceed +/-25% of the nominal specified C_Lvalue over the operating temperature range of

the device.

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Table 37. VREF full-range operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_out

Voltage reference output with factory trim at

1.1915

1.195

1.1977

V

1

nominal V_DDAand temperature=25C

Voltage reference output — factory trim

Voltage reference output — user trim

Voltage reference trim step

V_out

1.1584

1.193

—

1.2376

1.197

—

V

1

V_step

V_tdrift

0.5

—

mV

Temperature drift (Vmax -Vmin across the full

temperature range)

—

80

I_bg

I_hp

Bandgap only current

—

80

1

µA

mA

mV

1

High-power buffer current

ΔV_LOADLoad regulation

• current = + 1.0 mA

1, 2

—

2

5

—

• current = - 1.0 mA

T_stup

Buffer startup time

—

2

100

—

µs

V_vdrift

Voltage drift (Vmax -Vmin across the full voltage

range)

mV

1

1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.

2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 38. VREF limited-range operating requirements

Symbol

Description

Min.

Max.

Unit

Notes

T_A

Temperature

0

50

°C

Table 39. VREF limited-range operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

V_out

Voltage reference output with factory trim

1.173

1.225

V

6.7 Timers

See General switching specifications.

6.8 Communication interfaces

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6.8.1 Ethernet switching specifications

The following timing specs are defined at the chip I/O pin and must be translated

appropriately to arrive at timing specs/constraints for the physical interface.

6.8.1.1 MII signal switching specifications

The following timing specs meet the requirements for MII style interfaces for a range of

transceiver devices.

Table 40. MII signal switching specifications

Symbol

—

Description

Min.

—

Max.

25

Unit

MHz

RXCLK frequency

RXCLK pulse width high

MII1

35%

65%

RXCLK

period

RXCLK

period

ns

MII2

RXCLK pulse width low

35%

65%

MII3

MII4

—

RXD[3:0], RXDV, RXER to RXCLK setup

RXCLK to RXD[3:0], RXDV, RXER hold

TXCLK frequency

5

—

ns

—

25

MHz

MII5

TXCLK pulse width high

35%

65%

TXCLK

period

TXCLK

period

ns

MII6

TXCLK pulse width low

35%

65%

MII7

MII8

TXCLK to TXD[3:0], TXEN, TXER invalid

TXCLK to TXD[3:0], TXEN, TXER valid

2

—

25

ns

MII6

MII5

MII7

TXCLK (input)

MII8

Valid data

TXD[n:0]

TXEN

Valid data

TXER

Figure 30. RMII/MII transmit signal timing diagram

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Peripheral operating requirements and behaviors

MII2

MII3

MII1

MII4

RXCLK (input)

RXD[n:0]

RXDV

Valid data

RXER

Figure 31. RMII/MII receive signal timing diagram

6.8.1.2 RMII signal switching specifications

The following timing specs meet the requirements for RMII style interfaces for a range of

transceiver devices.

Table 41. RMII signal switching specifications

Num

—

Description

Min.

—

Max.

50

Unit

EXTAL frequency (RMII input clock RMII_CLK)

RMII_CLK pulse width high

MHz

RMII1

35%

65%

RMII_CLK

period

RMII2

RMII_CLK pulse width low

35%

65%

RMII_CLK

period

RMII3

RMII4

RMII7

RMII8

RXD[1:0], CRS_DV, RXER to RMII_CLK setup

RMII_CLK to RXD[1:0], CRS_DV, RXER hold

RMII_CLK to TXD[1:0], TXEN invalid

4

2

—

15

ns

4

RMII_CLK to TXD[1:0], TXEN valid

—

6.8.1.3 MDIO serial management timing specifications

Table 42. MDIO serial management channel signal timing

Num

E10

E11

E12

Characteristic

MDC cycle time

Min

400

40

Max

—

Unit

ns

MDC pulse width

60

% t_MDC

ns

MDC to MDIO output valid

Fsys period

—

1

E13

E14

E15

MDC to MDIO output invalid

MDIO input to MDC setup

MDIO input to MDC hold

Fsys period¹

—

ns

10

0

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1. MDIO output valid and hold time can be adjusted using the ENET_MSCR[HOLDTIME] field. The minimum specification

shown here is for the default ENET_MSCR value, where HOLDTIME = 0. The minimum output valid and output hold times

can be increased by changing the HOLDTIME register field

E10

E11

MDC (Output)

E11

E13

E12

MDIO (Output)

MDIO (Input)

Valid Data

E14

E15

Valid Data

Figure 32. MDIO serial management channel timing diagram

6.8.2 USB electrical specifications

The USB electricals for the USB On-the-Go module conform to the standards

documented by the Universal Serial Bus Implementers Forum. For the most up-to-date

standards, visit usb.org.

NOTE

The MCGPLLCLK meets the USB jitter and signaling rate

specifications for certification with the use of an external clock/

crystal for both Device and Host modes.

The MCGFLLCLK does not meet the USB jitter or signaling

rate specifications for certification.

6.8.3 USB DCD electrical specifications

Table 43. USB0 DCD electrical specifications

Symbol

V_{DP_SRC}

V_LGC

Description

Min.

0.5

Typ.

—

Max.

0.7

Unit

V

USB_DP source voltage (up to 250 μA)

Threshold voltage for logic high

USB_DP source current

USB_DM sink current

0.8

—

2.0

V

I_{DP_SRC}

I_{DM_SINK}

7

10

13

μA

kΩ

V

50

100

—

150

24.8

0.4

R_{DM_DWN}D- pulldown resistance for data pin contact detect

V_{DAT_REF}Data detect voltage

14.25

0.25

0.325

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6.8.4 USB VREG electrical specifications

Table 44. USB VREG electrical specifications

Symbol Description

Min.

2.7

—

Typ.¹

Max.

5.5

Unit

V

Notes

VREGIN Input supply voltage

—

I_DDon

I_DDstby

I_DDoff

Quiescent current — Run mode, load current

equal zero, input supply (VREGIN) > 3.6 V

125

186

μA

Quiescent current — Standby mode, load current

equal zero

—

1.1

10

μA

Quiescent current — Shutdown mode

—

650

—

4

nA

μA

• VREGIN = 5.0 V and temperature=25 °C

• Across operating voltage and temperature

I_LOADrunMaximum load current — Run mode

I_LOADstbyMaximum load current — Standby mode

—

120

1

mA

V_Reg33outRegulator output voltage — Input supply

(VREGIN) > 3.6 V

• Run mode

3

3.3

2.8

—

3.6

V

• Standby mode

2.1

V_Reg33outRegulator output voltage — Input supply

(VREGIN) < 3.6 V, pass-through mode

2

C_OUT

ESR

External output capacitor

1.76

1

2.2

—

8.16

100

μF

External output capacitor equivalent series

resistance

mΩ

I_LIM

Short circuit current

—

290

—

mA

1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.

2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I_Load

.

6.8.5 ULPI timing specifications

The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin

Interface. Control and data timing requirements for the ULPI pins are given in the

following table. These timings apply to synchronous mode only. All timings are

measured with respect to the clock as seen at the USB_CLKIN pin.

Table 45. ULPI timing specifications

Num

Description

Min.

Typ.

Max.

Unit

USB_CLKIN

operating

—

60

—

MHz

frequency

Table continues on the next page...

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Table 45. ULPI timing specifications (continued)

Num

Description

Min.

Typ.

Max.

Unit

USB_CLKIN duty

cycle

—

50

—

%

U1

U2

U3

U4

U5

USB_CLKIN clock

period

—

5

16.67

—

ns

Input setup (control

and data)

Input hold (control

and data)

1

—

Output valid

(control and data)

—

1

—

9.5

—

Output hold (control

and data)

—

U1

USB_CLKIN

U2

U3

ULPI_DIR/ULPI_NXT

(control input)

ULPI_DATAn (input)

U5

U4

ULPI_STP

(control output)

ULPI_DATAn (output)

Figure 33. ULPI timing diagram

6.8.6 CAN switching specifications

See General switching specifications.

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6.8.7 DSPI switching specifications (limited voltage range)

The DMA Serial Peripheral Interface DSPI provides a synchronous serial bus with master

and slave operations. Many of the transfer attributes are programmable. The tables below

provide DSPI timing characteristics for classic DSPI timing modes. Refer to the DSPI

chapter of the Reference Manual for information on the modified transfer formats used

for communicating with slower peripheral devices.

Table 46. Master mode DSPI timing (limited voltage range)

Num

Description

Min.

2.7

Max.

3.6

30

Unit

V

Notes

Operating voltage

Frequency of operation

—

MHz

ns

DS1

DS2

DS3

DSPI_SCK output cycle time

DSPI_SCK output high/low time

DSPI_PCSn valid to DSPI_SCK delay

2 x t_BUS

—

(t_SCK/2) − 2 (t_SCK/2) + 2

ns

(t_BUSx 2) −

2

—

ns

1

2

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(t_BUSx 2) −

2

—

ns

DS5

DS6

DS7

DS8

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

—

−2

15

0

8.5

—

ns

1. The delay is programmable in DSPIx_CTARn[PSSCK] and DSPIx_CTARn[CSSCK].

2. The delay is programmable in DSPIx_CTARn[PASC] and DSPIx_CTARn[ASC].

SPI_PCSn

DS1

DS3

DS2

DS4

SPI_SCK

(CPOL=0)

DS8

DS7

Data

Last data

First data

SPI_SIN

DS5

DS6

First data

Data

Last data

SPI_SOUT

Figure 34. DSPI classic DSPI timing — master mode

Table 47. Slave mode DSPI timing (limited voltage range)

Num

Description

Min.

Max.

3.6

15

Unit

V

Operating voltage

2.7

Frequency of operation

MHz

ns

DS9

DSPI_SCK input cycle time

4 x t_BUS

—

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Table 47. Slave mode DSPI timing (limited voltage range) (continued)

Num

DS10

DS11

DS12

DS13

DS14

DS15

DS16

Description

DSPI_SCK input high/low time

Min.

Max.

Unit

ns

(t_SCK/2) − 2

(t_SCK/2) + 2

DSPI_SCK to DSPI_SOUT valid

—

0

10

—

14

ns

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

DSPI_SS active to DSPI_SOUT driven

DSPI_SS inactive to DSPI_SOUT not driven

ns

2

ns

7

ns

—

ns

SPI_SS

DS10

DS9

SPI_SCK

(POL=0)

DS15

DS12

DS16

DS11

First data

DS14

Last data

SPI_SOUT

Data

DS13

First data

Last data

SPI_SIN

Figure 35. DSPI classic DSPI timing — slave mode

6.8.8 DSPI switching specifications (full voltage range)

The DMA Serial Peripheral Interface DSPI provides a synchronous serial bus with master

and slave operations. Many of the transfer attributes are programmable. The tables below

provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI

chapter of the Reference Manual for information on the modified transfer formats used

for communicating with slower peripheral devices.

Table 48. Master mode DSPItiming (full voltage range)

Num

Description

Min.

1.71

Max.

3.6

15

Unit

V

Notes

Operating voltage

1

Frequency of operation

—

MHz

ns

DS1

DS2

DS3

DSPI_SCK output cycle time

DSPI_SCK output high/low time

DSPI_PCSn valid to DSPI_SCK delay

4 x t_BUS

—

(t_SCK/2) - 4 (t_SCK/2)+ 4

ns

(t_BUSx 2) −

4

—

ns

2

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Table 48. Master mode DSPItiming (full voltage range) (continued)

Num

Description

Min.

Max.

Unit

Notes

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(t_BUSx 2) −

4

—

ns

3

DS5

DS6

DS7

DS8

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

—

-4.5

20.5

0

10

—

ns

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].

3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

SPI_PCSn

DS1

DS3

DS2

DS4

SPI_SCK

(CPOL=0)

DS8

DS7

Data

Last data

First data

SPI_SIN

DS5

DS6

First data

Data

Last data

SPI_SOUT

Figure 36. DSPI classic SPI timing — master mode

Table 49. Slave mode DSPI timing (full voltage range)

Num

Description

Min.

Max.

Unit

V

Operating voltage

1.71

3.6

Frequency of operation

—

7.5

MHz

ns

DS9

DSPI_SCK input cycle time

8 x t_BUS

—

DS10

DS11

DS12

DS13

DS14

DS15

DS16

DSPI_SCK input high/low time

(t_SCK/2) - 4

(t_SCK/2)+ 4

ns

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

DSPI_SS active to DSPI_SOUT driven

DSPI_SS inactive to DSPI_SOUT not driven

—

0

20

—

19

ns

2

ns

7

ns

—

ns

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SPI_SS

DS10

DS9

SPI_SCK

(POL=0)

DS15

DS12

DS16

DS11

First data

DS14

Last data

SPI_SOUT

Data

DS13

First data

SPI_SIN

Figure 37. DSPI classic SPI timing — slave mode

6.8.9 Inter-Integrated Circuit Interface (I²C) timing

Table 50. I ²C timing

Characteristic

Symbol

Standard Mode

Minimum Maximum

100

Fast Mode

Unit

Minimum

Maximum

400 ¹

SCL Clock Frequency

f_SCL

0

kHz

µs

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated.

t_HD; STA

4

—

0.6

—

LOW period of the SCL clock

HIGH period of the SCL clock

t_LOW

t_HIGH

4.7

4

—

1.25

0.6

—

µs

Set-up time for a repeated START

condition

t_SU; STA

4.7

0.6

Data hold time for I²C bus devices

t_HD; DAT

t_SU; DAT

t_r

0²

250⁵

—

3.45³

—

0⁴

100^3,6

20 +0.1C_b

0.6

0.9²

—

µs

ns

µs

Data set-up time

7

6

Rise time of SDA and SCL signals

Fall time of SDA and SCL signals

Set-up time for STOP condition

1000

300

—

300

—

t_f

—

t_SU; STO

t_BUF

4

Bus free time between STOP and

START condition

4.7

—

1.3

—

Pulse width of spikes that must be

suppressed by the input filter

t_SP

N/A

0

50

ns

1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using a pin

configured for high drive across the full voltage range and when using the a pin configured for low drive with VDD ≥ 2.7 V.

2. The master mode I²C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves

acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL

lines.

3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.

4. Input signal Slew = 10 ns and Output Load = 50 pF

5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.

6. A Fast mode I²C bus device can be used in a Standard mode I2C bus system, but the requirement t_{SU; DAT}≥ 250 ns must

then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a

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device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t_rmax+ t_{SU; DAT}

= 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification) before the SCL line is released.

7. C_b= total capacitance of the one bus line in pF.

SDA

t_{SU; DAT}

t_f

t_r

t_BUF

t_f

t_r

t_{HD; STA}

t_SP

t_LOW

SCL

t_{SU; STA}

t_{SU; STO}

HD; STA

S

SR

P

S

t_{HD; DAT}

t_HIGH

Figure 38. Timing definition for fast and standard mode devices on the I²C bus

6.8.10 UART switching specifications

See General switching specifications.

6.8.11 SDHC specifications

The following timing specs are defined at the chip I/O pin and must be translated

appropriately to arrive at timing specs/constraints for the physical interface.

Table 51. SDHC switching specifications over a limited operating voltage range

Num

Symbol

Description

Min.

Max.

Unit

Operating voltage

2.7

3.6

V

Card input clock

SD1

fpp

f_OD

t_WL

t_WH

t_TLH

t_THL

Clock frequency (low speed)

0

400

25\40

25\50

400

—

kHz

MHz

kHz

ns

Clock frequency (SD\SDIO full speed\high speed)

Clock frequency (MMC full speed\high speed)

Clock frequency (identification mode)

Clock low time

0

SD2

SD3

SD4

SD5

7

Clock high time

7

—

ns

Clock rise time

—

3

ns

Clock fall time

3

ns

SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SDHC output delay (output valid) -5 6.5

SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SD6

t_OD

ns

SD7

SD8

t_ISU

t_IH

SDHC input setup time

SDHC input hold time

5

0

—

ns

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Table 52. SDHC switching specifications over the full operating voltage range

Num

Symbol

Description

Min.

Max.

Unit

Operating voltage

1.71

3.6

V

Card input clock

SD1

fpp

f_OD

t_WL

t_WH

t_TLH

t_THL

Clock frequency (low speed)

0

400

25\40

25\50

400

—

kHz

MHz

kHz

ns

Clock frequency (SD\SDIO full speed\high speed)

Clock frequency (MMC full speed\high speed)

Clock frequency (identification mode)

Clock low time

0

SD2

SD3

SD4

SD5

7

Clock high time

7

—

ns

Clock rise time

—

3

ns

Clock fall time

3

ns

SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SDHC output delay (output valid) -5 6.5

SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SD6

t_OD

ns

SD7

SD8

t_ISU

t_IH

SDHC input setup time

SDHC input hold time

5

—

ns

1.3

SD3

SD6

SD2

SD1

SDHC_CLK

Output SDHC_CMD

Output SDHC_DAT[3:0]

Input SDHC_CMD

SD7

SD8

Input SDHC_DAT[3:0]

Figure 39. SDHC timing

6.8.12 I2S/SAI switching specifications

This section provides the AC timing for the I2S/SAI module in master mode (clocks are

driven) and slave mode (clocks are input). All timing is given for noninverted serial clock

polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]

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is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been

inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the

frame sync (FS) signal shown in the following figures.

6.8.12.1 Normal Run, Wait and Stop mode performance over a limited

operating voltage range

This section provides the operating performance over a limited operating voltage for the

device in Normal Run, Wait and Stop modes.

Table 53. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage

range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

2.7

40

3.6

—

V

S1

S2

S3

S4

S5

I2S_MCLK cycle time

ns

I2S_MCLK pulse width high/low

45%

80

55%

—

MCLK period

I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

ns

45%

—

55%

15

BCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

S6

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output invalid

0

—

ns

S7

S8

S9

I2S_TX_BCLK to I2S_TXD valid

I2S_TX_BCLK to I2S_TXD invalid

—

0

15

—

ns

I2S_RXD/I2S_RX_FS input setup before

I2S_RX_BCLK

15

S10

I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK

0

—

ns

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S1

S2

I2S_MCLK (output)

S3

S4

I2S_TX_BCLK/

I2S_RX_BCLK (output)

S4

S5

S7

S6

I2S_TX_FS/

I2S_RX_FS (output)

S10

S9

I2S_TX_FS/

I2S_RX_FS (input)

S7

S8

I2S_TXD

I2S_RXD

S9

S10

Figure 40. I2S/SAI timing — master modes

Table 54. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage

range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

2.7

80

3.6

—

V

S11

S12

I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)

ns

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

(input)

45%

55%

MCLK period

S13

S14

S15

I2S_TX_FS/I2S_RX_FS input setup before

I2S_TX_BCLK/I2S_RX_BCLK

4.5

2

—

ns

I2S_TX_FS/I2S_RX_FS input hold after

I2S_TX_BCLK/I2S_RX_BCLK

—

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid

• Multiple SAI Synchronous mode

• All other modes

—

21

15

S16

S17

S18

S19

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid

I2S_RXD setup before I2S_RX_BCLK

0

—

25

ns

4.5

2

I2S_RXD hold after I2S_RX_BCLK

I2S_TX_FS input assertion to I2S_TXD output valid¹

—

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

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S11

S12

I2S_TX_BCLK/

I2S_RX_BCLK (input)

S12

S15

S16

I2S_TX_FS/

I2S_RX_FS (output)

S13

S14

I2S_TX_FS/

I2S_RX_FS (input)

S15

S19

S16

I2S_TXD

I2S_RXD

S17

S18

Figure 41. I2S/SAI timing — slave modes

6.8.12.2 Normal Run, Wait and Stop mode performance over the full

operating voltage range

This section provides the operating performance over the full operating voltage for the

device in Normal Run, Wait and Stop modes.

Table 55. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage

range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

40

3.6

—

V

S1

S2

S3

S4

S5

I2S_MCLK cycle time

ns

I2S_MCLK pulse width high/low

45%

80

55%

—

MCLK period

I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

ns

45%

—

55%

15

BCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

S6

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output invalid

-1.0

—

ns

S7

S8

S9

I2S_TX_BCLK to I2S_TXD valid

I2S_TX_BCLK to I2S_TXD invalid

—

15

—

ns

0

I2S_RXD/I2S_RX_FS input setup before

I2S_RX_BCLK

20.5

S10

I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK

0

—

ns

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S1

S2

I2S_MCLK (output)

S3

S4

I2S_TX_BCLK/

I2S_RX_BCLK (output)

S4

S5

S7

S6

I2S_TX_FS/

I2S_RX_FS (output)

S10

S9

I2S_TX_FS/

I2S_RX_FS (input)

S7

S8

I2S_TXD

I2S_RXD

S9

S10

Figure 42. I2S/SAI timing — master modes

Table 56. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage

range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

80

3.6

—

V

S11

S12

I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)

ns

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

(input)

45%

55%

MCLK period

S13

S14

S15

I2S_TX_FS/I2S_RX_FS input setup before

I2S_TX_BCLK/I2S_RX_BCLK

5.8

2

—

ns

I2S_TX_FS/I2S_RX_FS input hold after

I2S_TX_BCLK/I2S_RX_BCLK

—

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid

• Multiple SAI Synchronous mode

• All other modes

—

24

20.6

S16

S17

S18

S19

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid

I2S_RXD setup before I2S_RX_BCLK

0

—

25

ns

5.8

2

I2S_RXD hold after I2S_RX_BCLK

I2S_TX_FS input assertion to I2S_TXD output valid¹

—

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

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S11

S12

I2S_TX_BCLK/

I2S_RX_BCLK (input)

S12

S15

S16

I2S_TX_FS/

I2S_RX_FS (output)

S13

S14

I2S_TX_FS/

I2S_RX_FS (input)

S15

S19

S16

I2S_TXD

I2S_RXD

S17

S18

Figure 43. I2S/SAI timing — slave modes

6.8.12.3 VLPR, VLPW, and VLPS mode performance over the full

operating voltage range

This section provides the operating performance over the full operating voltage for the

device in VLPR, VLPW, and VLPS modes.

Table 57. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

62.5

45%

250

45%

—

3.6

—

V

S1

S2

S3

S4

S5

I2S_MCLK cycle time

ns

I2S_MCLK pulse width high/low

55%

—

MCLK period

I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

ns

55%

45

BCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

S6

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output invalid

0

—

ns

S7

S8

S9

I2S_TX_BCLK to I2S_TXD valid

I2S_TX_BCLK to I2S_TXD invalid

—

45

—

ns

-1.6

45

I2S_RXD/I2S_RX_FS input setup before

I2S_RX_BCLK

S10

I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK

0

—

ns

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S1

S2

I2S_MCLK (output)

S3

S4

I2S_TX_BCLK/

I2S_RX_BCLK (output)

S4

S5

S7

S6

I2S_TX_FS/

I2S_RX_FS (output)

S10

S9

I2S_TX_FS/

I2S_RX_FS (input)

S7

S8

I2S_TXD

I2S_RXD

S9

S10

Figure 44. I2S/SAI timing — master modes

Table 58. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

250

3.6

—

V

S11

S12

I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)

ns

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

(input)

45%

55%

MCLK period

S13

S14

I2S_TX_FS/I2S_RX_FS input setup before

I2S_TX_BCLK/I2S_RX_BCLK

30

3

—

ns

I2S_TX_FS/I2S_RX_FS input hold after

I2S_TX_BCLK/I2S_RX_BCLK

—

S15

S16

S17

S18

S19

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid

I2S_RXD setup before I2S_RX_BCLK

—

0

63

—

72

ns

30

2

I2S_RXD hold after I2S_RX_BCLK

I2S_TX_FS input assertion to I2S_TXD output valid¹

—

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

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S11

S12

I2S_TX_BCLK/

I2S_RX_BCLK (input)

S12

S15

S16

I2S_TX_FS/

I2S_RX_FS (output)

S13

S14

I2S_TX_FS/

I2S_RX_FS (input)

S15

S19

S16

I2S_TXD

I2S_RXD

S17

S18

Figure 45. I2S/SAI timing — slave modes

6.9 Human-machine interfaces (HMI)

6.9.1 TSI electrical specifications

Table 59. TSI electrical specifications

Symbol Description

V_DDTSIOperating voltage

C_ELETarget electrode capacitance range

Min.

1.71

1

Typ.

—

20

8

Max.

3.6

500

15

Unit

V

Notes

pF

1

f_REFmaxReference oscillator frequency

f_ELEmaxElectrode oscillator frequency

—

MHz

pF

2, 3

2, 4

—

1

1.8

—

C_REF

V_DELTA

I_REF

Internal reference capacitor

Oscillator delta voltage

—

1

—

600

—

mV

μA

2, 5

2, 6

Reference oscillator current source base current

• 2 μA setting (REFCHRG = 0)

—

2

3

36

50

• 32 μA setting (REFCHRG = 15)

I_ELE

Electrode oscillator current source base current

• 2 μA setting (EXTCHRG = 0)

μA

2, 7

—

2

36

3

50

• 32 μA setting (EXTCHRG = 15)

Pres5

Electrode capacitance measurement precision

—

8.3333

1.46

—

38400

—

fF/count

bits

8

9

Pres20 Electrode capacitance measurement precision

Pres100 Electrode capacitance measurement precision

MaxSens Maximum sensitivity

—

10

11

0.008

—

Res

Resolution

16

T_Con20

Response time @ 20 pF

8

15

25

μs

12

13

I_{TSI_RUN}Current added in run mode

I_{TSI_LP}Low power mode current adder

—

55

—

μA

—

1.3

2.5

μA

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1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.

2. Fixed external capacitance of 20 pF.

3. REFCHRG = 2, EXTCHRG=0.

4. REFCHRG = 0, EXTCHRG = 10.

5. V_DD= 3.0 V.

6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.

7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.

8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.

9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.

10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.

11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity

depends on the configuration used. The documented values are provided as examples calculated for a specific

configuration of operating conditions using the following equation: (C_ref* I_ext)/( I_ref* PS * NSCN)

The typical value is calculated with the following configuration:

I_ext= 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, I_ref= 16 μA (REFCHRG = 7), C_ref= 1.0 pF

The minimum value is calculated with the following configuration:

I_ext= 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, I_ref= 32 μA (REFCHRG = 15), C_ref= 0.5 pF

The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be

measured by a single count.

12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1

electrode, EXTCHRG = 7.

13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of

20 pF. Data is captured with an average of 7 periods window.

6.9.2 LCDC electrical specifications

Table 60. GLCD_LSCLK Timing

Num

T1

Description

Min.

25

8

Max.

2000

—

Unit

ns

GLCD_LSCLK Period

Pixel data setup time

Pixel data up time

T2

ns

T3

8

—

ns

NOTE

The pixel clock is equal to GLCD_LSCLK / (PCD + 1). When

it is in CSTN, TFT, or monochrome mode with bus width = 1,

GLCD_LSCLK is equal to the pixel clock. When it is in

monochrome with other bus width settings, GLCD_LSCLK is

equal to the pixel clock divided by bus width. The polarity of

GLCD_LSCLK and GLCD_D signals can also be programmed.

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T1

GLCD_LSCLK

GLCD_D[17:0]

T2

T3

Figure 46. GLCD_LSCLK to GLCD_D[17:0] Timing

Non-display region

T3

Display region

T1

T4

GLCD_VSYNC

GLCD_HSYNC

GLCD_OE

T2

Line

Y

Line

1

Line

Y

GLCD_D[17:0]

T5

T6

XMAX

T7

GLCD_HSYNC

GLCD_LSCLK

GLCD_OE

(1,1) (1,2)

(1,X)

GLCD_D[15:0]

Figure 47. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing

Table 61. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing

Num

Description

Min.

Max.

Unit

T1

End of GLCD_OE to beginning of GLCD_VSYNC

T5 + T6 + T7

– 1

(VWAIT1 ×

T2) + T5 + T6

+ T7 – 1

Ts

T2

GLCD_HSYNC period

—

XMAX + T5 +

T6 + T7

Ts

T3

T4

GLCD_VSYNC pulse width

T2

1

VWIDTH × T2

Ts

End of GLCD_VSYNC to beginning of GLCD_OE

(VWAIT2 ×

T2) + 1

T5

T6

T7

GLCD_HSYNC pulse width

1

3

1

HWIDTH + 1

HWAIT2 + 3

HWAIT1 + 1

Ts

End of GLCD_HSYNC to beginning to GLCD_OE

End of GLCD_OE to beginning of GLCD_HSYNC

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NOTE

• Ts is the GLCD_LSCLK period. GLCD_VSYNC,

GLCD_HSYNC, and GLCD_OE can be programmed as

active high or active low. In the preceding figure, all 3

signals are active low. GLCD_LSCLK can be programmed

to be deactivated during the GLCD_VSYNC pulse or the

GLCD_OE deasserted period. In the preceding figure,

GLCD_LSCLK is always active.

• XMAX is defined in number of pixels in one line.

T1

GLCD_VSYNC

GLCD_HSYNC

GLCD_LSCLK

GLCD_D[15:0]

T2

T3

XMAX

T4

T2

TS

Figure 48. Non-TFT Mode Panel Timing

Table 62. Non-TFT Mode Panel Timing

Num

T1

Description

Min.

Max.

Unit

Tpix

—

GLCD_HSYNC to GLCD_VSYNC delay

GLCD_HSYNC pulse width

2

1

HWAIT2 + 2

HWIDTH + 1

0 ≤ T3 ≤ Ts

HWAIT1 + 1

T2

T3

GLCD_VSYNC to GLCD_LSCLK

GLCD_LSCLK to GLCD_HSYNC

—

1

T4

Tpix

NOTE

Ts is the GLCD_LSCLK period while Tpix is the pixel clock

period. GLCD_VSYNC, GLCD_HSYNC, and GLCD_LSCLK

can be programmed as active high or active low. In the

preceding figure, all these 3 signals are active high. When it is

in CSTN mode or monochrome mode with bus width = 1, T3 =

Tpix = Ts. When it is in monochrome mode with bus width = 2,

4 and 8, T3 = 1, 2 and 4 Tpix respectively.

K70 Sub-Family, Rev. 7, 02/2018

NXP Semiconductors

83

Dimensions

7 Dimensions

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

To find a package drawing, go to nxp.com and perform a keyword search for the

drawing’s document number:

If you want the drawing for this package

256-pin MAPBGA

Then use this document number

98ASA00346D

8 Pinout

8.1 Pins with active pull control after reset

The following pins are actively pulled up or down after reset:

Table 63. Pins with active pull control after reset

Active pull direction after reset

PTA0

pulldown

pullup

PTA1

PTA3

PTA4

RESET_b

8.2 K70 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is responsible

for selecting which ALT functionality is available on each pin.

K70 Sub-Family, Rev. 7, 02/2018

84

NXP Semiconductors

Pinout

256

MAP

BGA

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

E2

F2

F3

G2

PTE0

ADC1_SE4a

ADC1_SE5a

ADC1_SE6a

ADC1_SE7a

ADC1_SE4a

ADC1_SE5a

ADC1_SE6a

ADC1_SE7a

PTE0

SPI1_PCS1

SPI1_SOUT

SPI1_SCK

SPI1_SIN

UART1_TX

UART1_RX

SDHC0_D1

SDHC0_D0

GLCD_D0

GLCD_D1

I2C1_SDA

I2C1_SCL

RTC_

CLKOUT

PTE1/

LLWU_P0

PTE1/

LLWU_P0

SPI1_SIN

PTE2/

LLWU_P1

PTE2/

LLWU_P1

UART1_CTS_ SDHC0_DCLK GLCD_D2

b

PTE3

UART1_RTS_ SDHC0_CMD

b

GLCD_D3

SPI1_SOUT

G7

H7

H8

F1

VDD

VDDINT

VSS

VDDINT

VSS

VDDINT

VSS

PTF17

PTF18

DISABLED

PTF17

PTF18

SPI2_SCK

SPI2_SOUT

SPI1_PCS0

FTM0_CH4

FTM1_CH0

UART3_TX

UART0_RX

UART0_TX

SDHC0_D3

GLCD_D13

GLCD_D14

GLCD_D4

G1

G3

PTE4/

LLWU_P2

G4

H2

PTE5

PTE6

DISABLED

PTE5

PTE6

SPI1_PCS2

SPI1_PCS3

UART3_RX

SDHC0_D2

GLCD_D5

GLCD_D6

FTM3_CH0

FTM3_CH1

UART3_CTS_ I2S0_MCLK

b

USB_SOF_

OUT

H1

H5

H3

PTF19

PTF20

PTE7

DISABLED

PTF19

PTF20

PTE7

SPI2_SIN

FTM1_CH1

FTM2_CH0

UART5_RX

UART5_TX

GLCD_D15

GLCD_D16

GLCD_D7

SPI2_PCS1

UART3_RTS_ I2S0_RXD0

b

FTM3_CH2

H4

J1

PTE8

PTE9

ADC2_SE16

ADC2_SE17

ADC2_SE16

ADC2_SE17

PTE8

PTE9

I2S0_RXD1

I2S0_TXD1

UART5_TX

UART5_RX

I2S0_RX_FS

GLCD_D8

GLCD_D9

FTM3_CH3

FTM3_CH4

I2S0_RX_

BCLK

J2

K1

K3

PTE10

PTE11

PTE12

DISABLED

ADC3_SE16

ADC3_SE17

PTE10

PTE11

PTE12

UART5_CTS_ I2S0_TXD0

b

GLCD_D10

GLCD_D11

GLCD_D12

FTM3_CH5

FTM3_CH6

FTM3_CH7

ADC3_SE16

ADC3_SE17

UART5_RTS_ I2S0_TX_FS

b

I2S0_TX_

BCLK

G8

H9

J3

VDD

VSS

PTE16

PTE17

ADC0_SE4a

ADC0_SE5a

ADC0_SE4a

ADC0_SE5a

PTE16

PTE17

SPI0_PCS0

SPI0_SCK

UART2_TX

UART2_RX

FTM_CLKIN0

FTM_CLKIN1

FTM0_FLT3

K2

LPTMR0_

ALT3

L4

PTE18

PTE19

ADC0_SE6a

ADC0_SE7a

ADC0_SE6a

ADC0_SE7a

PTE18

PTE19

SPI0_SOUT

SPI0_SIN

UART2_CTS_ I2C0_SDA

b

M3

UART2_RTS_ I2C0_SCL

b

CMP3_OUT

L2

M1

M2

L1

VSS

USB0_DP

USB0_DM

VOUT33

USB0_DP

USB0_DM

VOUT33

USB0_DP

USB0_DM

VOUT33

K70 Sub-Family, Rev. 7, 02/2018

NXP Semiconductors

85

Pinout

256

MAP

BGA

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

L3

VREGIN

N1

PGA2_DP/

ADC2_DP0/

ADC3_DP3/

ADC0_DP1

PGA2_DP/

ADC2_DP0/

ADC3_DP3/

ADC0_DP1

PGA2_DP/

ADC2_DP0/

ADC3_DP3/

ADC0_DP1

N2

P1

P2

PGA2_DM/

ADC2_DM0/

ADC3_DM3/

ADC0_DM1

PGA2_DM/

ADC2_DM0/

ADC3_DM3/

ADC0_DM1

PGA2_DM/

ADC2_DM0/

ADC3_DM3/

ADC0_DM1

PGA3_DP/

ADC3_DP0/

ADC2_DP3/

ADC1_DP1

PGA3_DP/

ADC3_DP0/

ADC2_DP3/

ADC1_DP1

PGA3_DP/

ADC3_DP0/

ADC2_DP3/

ADC1_DP1

PGA3_DM/

ADC3_DM0/

ADC2_DM3/

ADC1_DM1

PGA3_DM/

ADC3_DM0/

ADC2_DM3/

ADC1_DM1

PGA3_DM/

ADC3_DM0/

ADC2_DM3/

ADC1_DM1

R1

R2

T1

T2

PGA0_DP/

ADC0_DP0/

ADC1_DP3

PGA0_DP/

ADC0_DP0/

ADC1_DP3

PGA0_DP/

ADC0_DP0/

ADC1_DP3

PGA0_DM/

ADC0_DM0/

ADC1_DM3

PGA0_DM/

ADC0_DM0/

ADC1_DM3

PGA0_DM/

ADC0_DM0/

ADC1_DM3

PGA1_DP/

ADC1_DP0/

ADC0_DP3

PGA1_DP/

ADC1_DP0/

ADC0_DP3

PGA1_DP/

ADC1_DP0/

ADC0_DP3

PGA1_DM/

ADC1_DM0/

ADC0_DM3

PGA1_DM/

ADC1_DM0/

ADC0_DM3

PGA1_DM/

ADC1_DM0/

ADC0_DM3

N5

P4

M4

N4

P3

VDDA

VREFH

VREFL

VSSA

VDDA

VREFH

VREFL

VSSA

VDDA

VREFH

VREFL

VSSA

ADC1_SE16/

CMP2_IN2/

ADC0_SE22

ADC1_SE16/

CMP2_IN2/

ADC0_SE22

ADC1_SE16/

CMP2_IN2/

ADC0_SE22

N3

T3

ADC0_SE16/

CMP1_IN2/

ADC0_SE21

ADC0_SE16/

CMP1_IN2/

ADC0_SE21

ADC0_SE16/

CMP1_IN2/

ADC0_SE21

VREF_OUT/

CMP1_IN5/

CMP0_IN5/

ADC1_SE18

VREF_OUT/

CMP1_IN5/

CMP0_IN5/

ADC1_SE18

VREF_OUT/

CMP1_IN5/

CMP0_IN5/

ADC1_SE18

R3

R4

DAC0_OUT/

CMP1_IN3/

ADC0_SE23

DAC0_OUT/

CMP1_IN3/

ADC0_SE23

DAC0_OUT/

CMP1_IN3/

ADC0_SE23

DAC1_OUT/

CMP0_IN4/

CMP2_IN3/

ADC1_SE23

DAC1_OUT/

CMP0_IN4/

CMP2_IN3/

ADC1_SE23

DAC1_OUT/

CMP0_IN4/

CMP2_IN3/

ADC1_SE23

K70 Sub-Family, Rev. 7, 02/2018

86

NXP Semiconductors

Pinout

256

MAP

BGA

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

M5

TAMPER0/

RTC_

TAMPER0/

RTC_

TAMPER0/

RTC_

WAKEUP_B

L5

L6

TAMPER1

TAMPER2

TAMPER3

TAMPER4

TAMPER5

XTAL32

EXTAL32

VBAT

TAMPER1

TAMPER2

TAMPER3

TAMPER4

TAMPER5

XTAL32

EXTAL32

VBAT

TAMPER1

TAMPER2

TAMPER3

TAMPER4

TAMPER5

XTAL32

EXTAL32

VBAT

R5

P6

R6

T6

T5

P5

N6

M6

G9

H10

J8

TAMPER6

TAMPER7

VDD

TAMPER6

TAMPER7

VDD

TAMPER6

TAMPER7

VDD

VDDINT

VSS

VDDINT

VSS

VDDINT

VSS

P7

PTE24

ADC0_SE17/

EXTAL1

ADC0_SE17/

EXTAL1

PTE24

CAN1_TX

CAN1_RX

UART4_TX

UART4_RX

I2S1_TX_FS

GLCD_D13

GLCD_D14

GLCD_D15

GLCD_D16

GLCD_D17

EWM_OUT_b

EWM_IN

I2S1_RXD1

I2S1_TXD1

USB_CLKIN

R7

M7

K7

PTE25

PTE26

PTE27

ADC0_SE18/

XTAL1

ADC0_SE18/

XTAL1

PTE25

PTE26

PTE27

I2S1_TX_

BCLK

ADC3_SE5b

ADC3_SE4b

ADC3_SE7a

ADC3_SE5b

ENET_1588_

CLKIN

UART4_CTS_ I2S1_TXD0

b

RTC_

CLKOUT

ADC3_SE4b

UART4_RTS_ I2S1_MCLK

b

L7

T7

PTE28

PTA0

ADC3_SE7a

TSI0_CH1

PTE28

PTA0

JTAG_TCLK/

SWD_CLK/

EZP_CLK

UART0_CTS_ FTM0_CH5

b/

UART0_COL_

b

JTAG_TCLK/

SWD_CLK

EZP_CLK

N8

T8

PTA1

PTA2

JTAG_TDI/

EZP_DI

TSI0_CH2

TSI0_CH3

PTA1

PTA2

UART0_RX

FTM0_CH6

FTM0_CH7

JTAG_TDI

EZP_DI

JTAG_TDO/

TRACE_SWO/

EZP_DO

UART0_TX

JTAG_TDO/

TRACE_SWO

EZP_DO

P8

R8

PTA3

JTAG_TMS/

SWD_DIO

TSI0_CH4

TSI0_CH5

PTA3

UART0_RTS_ FTM0_CH0

b

JTAG_TMS/

SWD_DIO

PTA4/

NMI_b/

PTA4/

FTM0_CH1

NMI_b

EZP_CS_b

LLWU_P3

EZP_CS_b

LLWU_P3

T12

PTA5

DISABLED

PTA5

USB_CLKIN

FTM0_CH2

FTM2_CH1

RMII0_RXER/

MII0_RXER

CMP2_OUT

I2S0_TX_

BCLK

JTAG_TRST_

b

G10

J9

VDD

VSS

P9

PTF21

ADC3_SE6b

PTF21

UART5_RTS_

b

GLCD_D17

K70 Sub-Family, Rev. 7, 02/2018

NXP Semiconductors

87

Pinout

256

MAP

BGA

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

N9

PTF22

ADC3_SE7b

ADC3_SE6a

ADC0_SE10

ADC0_SE11

ADC3_SE5a

ADC3_SE4a

ADC3_SE15

CMP2_IN0

ADC3_SE7b

ADC3_SE6a

ADC0_SE10

ADC0_SE11

ADC3_SE5a

ADC3_SE4a

ADC3_SE15

CMP2_IN0

PTF22

I2C0_SCL

ULPI_CLK

ULPI_DIR

FTM1_CH0

FTM0_CH3

FTM0_CH4

FTM1_CH0

FTM1_CH1

FTM2_CH0

FTM2_CH1

FTM1_CH0

FTM1_CH1

UART0_TX

UART5_CTS_

b

GLCD_D18

R12

P12

N12

T13

P13

R13

M10

N10

R11

PTA6

PTA7

PTA8

PTA9

PTA10

PTA11

PTA12

I2S1_RXD0

CLKOUT

TRACE_

CLKOUT

PTA7

I2S1_RX_

BCLK

TRACE_D3

TRACE_D2

TRACE_D1

TRACE_D0

PTA8

ULPI_NXT

ULPI_STP

ULPI_DATA0

ULPI_DATA1

CAN0_TX

I2S1_RX_FS

MII0_RXD3

MII0_RXD2

MII0_RXCLK

FTM1_QD_

PHA

PTA9

FTM1_QD_

PHB

PTA10

PTA11

PTA12

FTM2_QD_

PHA

FTM2_QD_

PHB

RMII0_RXD1/

MII0_RXD1

I2S0_TXD0

FTM1_QD_

PHA

PTA13/

LLWU_P4

CMP2_IN1

PTA13/

LLWU_P4

CAN0_RX

SPI0_PCS0

RMII0_RXD0/

MII0_RXD0

I2S0_TX_FS

FTM1_QD_

PHB

PTA14

CMP3_IN0

PTA14

RMII0_CRS_

DV/

I2S0_RX_

BCLK

I2S0_TXD1

MII0_RXDV

P11

PTA15

CMP3_IN1

PTA15

SPI0_SCK

UART0_RX

RMII0_TXEN/

MII0_TXEN

I2S0_RXD0

T14

N11

VSS

PTA16

CMP3_IN2

PTA16

SPI0_SOUT

UART0_CTS_ RMII0_TXD0/

I2S0_RX_FS

I2S0_RXD1

b/

MII0_TXD0

UART0_COL_

b

T11

P10

R10

R9

PTA17

PTF23

PTF24

PTF25

PTF26

PTF27

ADC1_SE17

ADC3_SE10

ADC3_SE11

ADC3_SE12

ADC3_SE13

ADC3_SE14

ADC1_SE17

ADC3_SE10

ADC3_SE11

ADC3_SE12

ADC3_SE13

ADC3_SE14

PTA17

PTF23

PTF24

PTF25

PTF26

PTF27

SPI0_SIN

I2C0_SDA

CAN1_RX

CAN1_TX

UART0_RTS_ RMII0_TXD1/

I2S0_MCLK

b

MII0_TXD1

FTM1_CH1

TRACE_

CLKOUT

GLCD_D19

GLCD_D20

GLCD_D21

GLCD_D22

GLCD_D23

FTM1_QD_

PHA

TRACE_D3

TRACE_D2

TRACE_D1

TRACE_D0

FTM1_QD_

PHB

T9

FTM2_QD_

PHA

T10

FTM2_QD_

PHB

J7

K8

VDD

VSS

T15

T16

PTA18

PTA19

EXTAL0

XTAL0

EXTAL0

XTAL0

PTA18

PTA19

FTM0_FLT2

FTM1_FLT0

FTM_CLKIN0

FTM_CLKIN1

LPTMR0_

ALT1

R16

N13

RESET_b

PTA24

RESET_b

CMP3_IN4

RESET_b

CMP3_IN4

PTA24

ULPI_DATA2

MII0_TXD2

FB_A29

K70 Sub-Family, Rev. 7, 02/2018

88

NXP Semiconductors

Pinout

256

MAP

BGA

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

R14

M13

R15

P14

N14

P16

L13

PTA25

CMP3_IN5

PTA25

ULPI_DATA3

ULPI_DATA4

ULPI_DATA5

ULPI_DATA6

ULPI_DATA7

CAN0_TX

MII0_TXCLK

MII0_TXD3

MII0_CRS

MII0_TXER

MII0_COL

FB_A28

PTA26

PTA27

PTA28

PTA29

PTF0

ADC2_SE15

ADC2_SE14

ADC2_SE13

ADC2_SE12

ADC2_SE11

ADC2_SE10

ADC2_SE15

ADC2_SE14

ADC2_SE13

ADC2_SE12

ADC2_SE11

ADC2_SE10

PTA26

PTA27

PTA28

PTA29

PTF0

FB_A27

FB_A26

FB_A25

FB_A24

FTM3_CH0

FTM3_CH1

I2S1_RXD1

GLCD_PCLK

GLCD_DE

PTF1

CAN0_RX

I2S1_RX_

BCLK

M12

PTB0/

LLWU_P5

ADC0_SE8/

ADC1_SE8/

ADC2_SE8/

ADC3_SE8/

TSI0_CH0

ADC0_SE8/

ADC1_SE8/

ADC2_SE8/

ADC3_SE8/

TSI0_CH0

PTB0/

LLWU_P5

I2C0_SCL

FTM1_CH0

RMII0_MDIO/

MII0_MDIO

FTM1_QD_

PHA

M11

PTB1

ADC0_SE9/

ADC1_SE9/

ADC2_SE9/

ADC3_SE9/

TSI0_CH6

ADC0_SE9/

ADC1_SE9/

ADC2_SE9/

ADC3_SE9/

TSI0_CH6

PTB1

I2C0_SDA

FTM1_CH1

RMII0_MDC/

MII0_MDC

FTM1_QD_

PHB

P15

M14

PTB2

PTB3

ADC0_SE12/

TSI0_CH7

ADC0_SE12/

TSI0_CH7

PTB2

PTB3

I2C0_SCL

I2C0_SDA

UART0_RTS_ ENET0_1588_

TMR0

FTM0_FLT3

FTM0_FLT0

b

ADC0_SE13/

TSI0_CH8

ADC0_SE13/

TSI0_CH8

UART0_CTS_ ENET0_1588_

b/

TMR1

UART0_COL_

b

N15

M15

PTB4

PTB5

ADC1_SE10

ADC1_SE11

ADC1_SE10

ADC1_SE11

PTB4

PTB5

GLCD_

CONTRAST

ENET0_1588_

TMR2

FTM1_FLT0

FTM2_FLT0

ENET0_1588_

TMR3

L14

L15

K14

PTB6

PTB7

PTB8

ADC1_SE12

ADC1_SE13

DISABLED

ADC1_SE12

ADC1_SE13

PTB6

PTB7

PTB8

FB_AD23

FB_AD22

FB_AD21

UART3_RTS_

b

K15

J13

PTB9

DISABLED

PTB9

SPI1_PCS1

SPI1_PCS0

SPI1_SCK

UART3_CTS_

b

FB_AD20

FB_AD19

FB_AD18

PTB10

ADC1_SE14

PTB10

PTB11

UART3_RX

I2S1_TX_

BCLK

FTM0_FLT1

FTM0_FLT2

J14

K9

PTB11

VSS

ADC1_SE15

VSS

ADC1_SE15

VSS

UART3_TX

I2S1_TX_FS

J10

N16

M16

L16

J15

H13

H14

VDD

PTF2

PTF3

PTF4

PTB16

PTB17

PTB18

ADC2_SE6a

ADC2_SE7a

ADC2_SE4b

TSI0_CH9

TSI0_CH10

TSI0_CH11

ADC2_SE6a

ADC2_SE7a

ADC2_SE4b

TSI0_CH9

TSI0_CH10

TSI0_CH11

PTF2

I2C1_SCL

I2C1_SDA

FTM3_CH2

FTM3_CH3

FTM3_CH4

UART0_RX

UART0_TX

FTM2_CH0

I2S1_RX_FS

I2S1_RXD0

I2S1_TXD0

FB_AD17

GLCD_HFS

GLCD_VFS

GLCD_D0

PTF3

PTF4

PTB16

PTB17

PTB18

SPI1_SOUT

SPI1_SIN

CAN0_TX

I2S1_TXD0

I2S1_TXD1

EWM_IN

FB_AD16

EWM_OUT_b

I2S0_TX_

BCLK

FB_AD15

FTM2_QD_

PHA

K70 Sub-Family, Rev. 7, 02/2018

NXP Semiconductors

89

Pinout

256

MAP

BGA

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

K16

J16

PTF5

PTF6

ADC2_SE5b

ADC2_SE6b

ADC2_SE5b

ADC2_SE6b

PTF5

FTM3_CH5

FTM3_CH6

I2S1_TX_FS

GLCD_D1

GLCD_D2

PTF6

I2S1_TX_

BCLK

H15

G13

G14

G15

H16

G16

F13

F14

PTB19

PTB20

PTB21

PTB22

PTB23

PTC0

TSI0_CH12

ADC2_SE4a

ADC2_SE5a

DISABLED

TSI0_CH12

ADC2_SE4a

ADC2_SE5a

PTB19

PTB20

PTB21

PTB22

PTB23

PTC0

CAN0_RX

FTM2_CH1

I2S0_TX_FS

FB_OE_b

FTM2_QD_

PHB

SPI2_PCS0

SPI2_SCK

SPI2_SOUT

SPI2_SIN

FB_AD31/

NFC_DATA15

CMP0_OUT

CMP1_OUT

CMP2_OUT

CMP3_OUT

I2S0_TXD1

I2S0_TXD0

I2S0_TX_FS

FB_AD30/

NFC_DATA14

FB_AD29/

NFC_DATA13

SPI0_PCS5

FB_AD28/

NFC_DATA12

ADC0_SE14/

TSI0_CH13

ADC0_SE14/

TSI0_CH13

SPI0_PCS4

SPI0_PCS3

SPI0_PCS2

PDB0_EXTRG

FB_AD14/

NFC_DATA11

PTC1/

LLWU_P6

ADC0_SE15/

TSI0_CH14

ADC0_SE15/

TSI0_CH14

PTC1/

LLWU_P6

UART1_RTS_ FTM0_CH0

b

FB_AD13/

NFC_DATA10

PTC2

ADC0_SE4b/

CMP1_IN0/

TSI0_CH15

ADC0_SE4b/

CMP1_IN0/

TSI0_CH15

PTC2

UART1_CTS_ FTM0_CH1

b

FB_AD12/

NFC_DATA9

E13

PTC3/

LLWU_P7

CMP1_IN1

PTC3/

LLWU_P7

SPI0_PCS1

UART1_RX

FTM3_CH7

FTM0_CH2

UART3_RX

CLKOUT

I2S0_TX_

BCLK

F15

L9

PTF7

VSS

ADC2_SE7b

VSS

ADC2_SE7b

VSS

PTF7

I2S1_TXD1

GLCD_D3

GLCD_D4

K10

F16

E14

VDD

PTF8

VDD

DISABLED

PTF8

FTM3_FLT0

UART1_TX

UART3_TX

FTM0_CH3

I2S1_MCLK

PTC4/

LLWU_P8

PTC4/

LLWU_P8

SPI0_PCS0

SPI0_SCK

SPI0_SOUT

SPI0_SIN

FB_AD11/

NFC_DATA8

CMP1_OUT

CMP0_OUT

I2S0_MCLK

I2S1_TX_

BCLK

E15

F12

G12

H12

F11

G11

H11

J12

PTC5/

LLWU_P9

DISABLED

CMP0_IN0

CMP0_IN1

PTC5/

LLWU_P9

LPTMR0_

ALT2

I2S0_RXD0

FB_AD10/

NFC_DATA7

I2S1_TX_FS

PTC6/

LLWU_P10

CMP0_IN0

CMP0_IN1

PTC6/

LLWU_P10

PDB0_EXTRG I2S0_RX_

BCLK

FB_AD9/

NFC_DATA6

PTC7

PTC8

PTC9

PTC10

PTC7

PTC8

PTC9

PTC10

USB_SOF_

OUT

I2S0_RX_FS

FB_AD8/

NFC_DATA5

ADC1_SE4b/

CMP0_IN2

ADC1_SE4b/

CMP0_IN2

FTM3_CH4

FTM3_CH5

FTM3_CH6

FTM3_CH7

I2S0_MCLK

FB_AD7/

NFC_DATA4

ADC1_SE5b/

CMP0_IN3

ADC1_SE5b/

CMP0_IN3

I2S0_RX_

BCLK

FB_AD6/

NFC_DATA3

FTM2_FLT0

I2S1_MCLK

ADC1_SE6b

ADC1_SE7b

DISABLED

ADC1_SE6b

I2C1_SCL

I2C1_SDA

I2S0_RX_FS

FB_AD5/

NFC_DATA2

PTC11/

LLWU_P11

ADC1_SE7b

PTC11/

LLWU_P11

I2S0_RXD1

FB_RW_b/

NFC_WE

PTC12

UART4_RTS_

b

FB_AD27

FTM3_FLT0

K13

PTC13

UART4_CTS_

b

FB_AD26

K70 Sub-Family, Rev. 7, 02/2018

90

NXP Semiconductors

Pinout

256

MAP

BGA

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

J11

PTC14

DISABLED

CMP2_IN4

PTC14

UART4_RX

FB_AD25

K12

PTF9

CMP2_IN4

CMP2_IN5

PTF9

UART3_RTS_

b

GLCD_D5

GLCD_D6

L12

PTF10

CMP2_IN5

PTF10

PTC15

UART3_CTS_

b

F10

N7

PTC15

VSS

DISABLED

VSS

UART4_TX

FB_AD24

VSS

VDD

L10

K11

VDD

PTF11

DISABLED

PTF11

PTF12

PTC16

UART2_RTS_

b

GLCD_D7

GLCD_D8

L11

F9

PTF12

PTC16

DISABLED

UART2_CTS_

b

CAN1_RX

CAN1_TX

UART3_RX

UART3_TX

ENET0_1588_ FB_CS5_b/

NFC_RB

TMR0

FB_TSIZ1/

FB_BE23_16_

b

E9

PTC17

DISABLED

PTC17

ENET0_1588_ FB_CS4_b/

NFC_CE0_b

NFC_CE1_b

TMR1

FB_TSIZ0/

FB_BE31_24_

b

M9

PTC18

PTC19

PTC18

PTC19

UART3_RTS_ ENET0_1588_ FB_TBST_b/

b

TMR2

FB_CS2_b/

FB_BE15_8_b

M8

L8

DISABLED

UART3_CTS_ ENET0_1588_ FB_CS3_b/

b

FB_TA_b

TMR3

FB_BE7_0_b

PTD0/

LLWU_P12

PTD0/

LLWU_P12

SPI0_PCS0

UART2_RTS_ FTM3_CH0

b

FB_ALE/

FB_CS1_b/

FB_TS_b

I2S1_RXD1

F8

K6

J6

K5

J5

PTD1

ADC0_SE5b

DISABLED

ADC0_SE6b

ADC0_SE5b

PTD1

SPI0_SCK

SPI0_SOUT

SPI0_SIN

UART2_CTS_ FTM3_CH1

b

FB_CS0_b

FB_AD4

FB_AD3

I2S1_RXD0

PTD2/

LLWU_P13

PTD2/

LLWU_P13

UART2_RX

FTM3_CH2

I2S1_RX_FS

PTD3

UART2_TX

FTM3_CH3

I2S1_RX_

BCLK

PTD4/

LLWU_P14

PTD4/

LLWU_P14

SPI0_PCS1

SPI0_PCS2

UART0_RTS_ FTM0_CH4

b

FB_AD2/

NFC_DATA1

EWM_IN

PTD5

ADC0_SE6b

ADC0_SE7b

PTD5

UART0_CTS_ FTM0_CH5

b/

UART0_COL_

b

FB_AD1/

NFC_DATA0

EWM_OUT_b

K4

PTD6/

LLWU_P15

ADC0_SE7b

PTD6/

LLWU_P15

SPI0_PCS3

UART0_RX

FTM0_CH6

FB_AD0

FTM0_FLT0

FTM0_FLT1

H6

G6

T4

E7

PTF13

PTF14

VSS

DISABLED

VSS

PTF13

PTF14

UART2_RX

UART2_TX

GLCD_D9

GLCD_D10

VSS

PTD7

DISABLED

PTD7

CMT_IRO

UART0_TX

FTM0_CH7

K70 Sub-Family, Rev. 7, 02/2018

NXP Semiconductors

91

Pinout

256

MAP

BGA

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

J4

F7

E6

G5

PTD8

DISABLED

PTD8

I2C0_SCL

I2C0_SDA

UART5_RX

UART5_TX

FB_A16/

NFC_CLE

PTD9

FB_A17/

NFC_ALE

PTD10

PTD11

PTD10

PTD11

UART5_RTS_

b

FB_A18/

NFC_RE

SPI2_PCS0

UART5_CTS_ SDHC0_

FB_A19

GLCD_

b

CLKIN

CONTRAST

GLCD_PCLK

GLCD_DE

F5

F4

E5

E4

F6

PTD12

PTD13

PTD14

PTD15

PTF15

DISABLED

PTD12

PTD13

PTD14

PTD15

PTF15

SPI2_SCK

SPI2_SOUT

SPI2_SIN

FTM3_FLT0

SDHC0_D4

SDHC0_D5

SDHC0_D6

SDHC0_D7

FB_A20

FB_A21

FB_A22

FB_A23

GLCD_HFS

GLCD_VFS

GLCD_D11

SPI2_PCS1

UART0_RTS_

b

E1

PTF16

DISABLED

PTF16

SPI2_PCS0

FTM0_CH3

UART0_CTS_ GLCD_D12

b/

UART0_COL_

b

B1

A1

DDR_VDD

DDR_VSS

DDR_DQS1

DDR_DQ8

DDR_DQ9

DDR_VDD

DDR_VSS

DDR_DQ10

DDR_DQ11

DDR_DQ12

DDR_VDD

DDR_VSS

DDR_DQ13

DDR_DQ14

DDR_DQ15

DDR_DM1

DDR_VSS

DDR_VDD

DDR_VSS

DDR_VREF

DDR_DQ0

DDR_DQ1

DDR_DQ2

DDR_VDD

DDR_VSS

DISABLED

DDR_VDD

DDR_VSS

DISABLED

DDR_VDD

DDR_VSS

DISABLED

DDR_VSS

DDR_VDD

DDR_VSS

DDR_VREF

DISABLED

DDR_VDD

DDR_VSS

DDR_DQS1

DDR_DQ8

DDR_DQ9

DDR_VDD

DDR_VSS

DDR_DQ10

DDR_DQ11

DDR_DQ12

DDR_VDD

DDR_VSS

DDR_DQ13

DDR_DQ14

DDR_DQ15

DDR_DM1

DDR_VSS

DDR_VDD

DDR_VSS

DDR_VREF

DDR_DQ0

DDR_DQ1

DDR_DQ2

DDR_VDD

D3

D1

C1

B5

A5

D5

C2

B2

C3

B8

A12

C4

B3

A2

A3

E8

B12

A16

C6

C5

B4

A4

C16

K70 Sub-Family, Rev. 7, 02/2018

92

NXP Semiconductors

Pinout

256

MAP

BGA

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

C7

B6

DDR_VSS

DDR_DQ3

DDR_DQ4

DDR_DQ5

DDR_ODT

DDR_VSS

DDR_VDD

DDR_VSS

DDR_DQ6

DDR_DQ7

DDR_DQS0

DDR_DM0

DDR_VDD

DDR_VSS

DDR_BA0

DDR_BA1

DDR_BA2

DDR_CKB

DDR_CK

DDR_VSS

DISABLED

DDR_VSS

DDR_VDD

DDR_VSS

DISABLED

DDR_VDD

DDR_VSS

DISABLED

DDR_VDD

DDR_VSS

DISABLED

DDR_VDD

DDR_VSS

DISABLED

DDR_VDD

DDR_VSS

DISABLED

DDR_VSS

DDR_DQ3

DDR_DQ4

DDR_DQ5

DDR_ODT

DDR_VSS

DDR_VDD

DDR_VSS

DDR_DQ6

DDR_DQ7

DDR_DQS0

DDR_DM0

DDR_VDD

DDR_VSS

DDR_BA0

DDR_BA1

DDR_BA2

DDR_CKB

DDR_CK

D6

A6

A7

E11

D2

C9

B7

A8

C8

D9

D4

C14

A9

B10

B9

A10

A11

D7

DDR_VDD

DDR_VSS

DDR_A0

DDR_VDD

DDR_VSS

DDR_A0

D8

D10

C11

B11

C12

E10

D12

C10

A13

A14

D11

A15

E12

E3

DDR_A1

DDR_A2

DDR_A3

DDR_VDD

DDR_VSS

DDR_A4

DDR_VDD

DDR_VSS

DDR_A4

DDR_A5

DDR_A6

DDR_A7

DDR_A8

DDR_VDD

DDR_VSS

DDR_CKE

DDR_A9

DDR_VDD

DDR_VSS

DDR_CKE

DDR_A9

B16

B15

B13

B14

C15

D16

DDR_A10

DDR_A11

DDR_A12

DDR_A13

DDR_A10

DDR_A11

DDR_A12

DDR_A13

K70 Sub-Family, Rev. 7, 02/2018

NXP Semiconductors

93

Pinout

256

MAP

BGA

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

D15

E16

C13

D14

D13

DDR_A14

DISABLED

DDR_A14

DDR_RAS_B

DDR_CAS_B

DDR_CS_B

DDR_WE_B

DDR_RAS_B

DDR_CAS_B

DDR_CS_B

DDR_WE_B

8.3 K70 Pinouts

The below figure shows the pinout diagram for the devices supported by this document.

Many signals may be multiplexed onto a single pin. To determine what signals can be

used on which pin, see the previous section.

K70 Sub-Family, Rev. 7, 02/2018

94

NXP Semiconductors

Revision History

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

B

C

D

E

F

DDR_VSS DDR_DQ15 DDR_DM1 DDR_DQ2 DDR_VSS DDR_DQ5 DDR_ODT DDR_DQ7 DDR_BA0 DDR_CKB DDR_CK DDR_VSS DDR_A5

DDR_A6

DDR_A8 DDR_VSS

DDR_A9 DDR_CKE

A

B

C

D

E

F

DDR_VDD DDR_DQ11 DDR_DQ14 DDR_DQ1 DDR_VDD DDR_DQ3 DDR_DQ6 DDR_VDD DDR_BA2 DDR_BA1 DDR_A2 DDR_VDD DDR_A10 DDR_A11

DDR_DQ9 DDR_DQ10 DDR_DQ12 DDR_DQ13 DDR_DQ0 DDR_VREF DDR_VSS DDR_DQS0 DDR_VSS DDR_A4

DDR_DQ8 DDR_VDD DDR_DQS1 DDR_VDD DDR_VSS DDR_DQ4 DDR_VDD DDR_VSS DDR_DM0 DDR_A0

DDR_A1

DDR_A3 DDR_CAS_B DDR_VSS DDR_A12 DDR_VDD

DDR_A7 DDR_VSS DDR_WE_B DDR_CS_B DDR_A14 DDR_A13

PTC3/

LLWU_P7

PTC4/

PTC5/

PTF16

PTF17

PTF18

PTF19

PTE9

PTE0

DDR_VSS

PTE2/

PTD15

PTD13

PTE5

PTD14

PTD12

PTD11

PTF20

PTD10

PTF15

PTF14

PTF13

PTD7

PTD9

VDD

DDR_VSS

PTD1

VDD

PTC17

PTC16

VDD

DDR_VDD DDR_VSS DDR_VDD

DDR_RAS_B

PTF8

LLWU_P8 LLWU_P9

PTE1/

PTC6/

PTC1/

PTC15

VDD

PTC9

PTC2

PTB21

PTB18

PTB11

PTB8

PTF7

PTB22

PTB19

PTB16

PTB9

PTB7

PTB5

PTB4

PTB2

PTA27

LLWU_P0 LLWU_P1

LLWU_P10 LLWU_P6

PTE4/

G

H

J

PTE3

PTE6

PTE10

PTE17

VSS

PTC10

PTC7

PTC8

PTC12

PTF9

PTB20

PTB17

PTB10

PTC13

PTF1

PTC0

G

H

J

LLWU_P2

PTE7

PTC11/

PTE8

VDDINT

VDD

VSS

VDDINT

VDD

PTB23

PTF6

LLWU_P11

PTE16

PTE12

VREGIN

PTE19

PTD8

PTD5

PTD3

VSS

PTC14

PTF11

PTF12

PTB1

PTD6/

PTD4/

PTD2/

K

L

PTE11

VOUT33

PTE27

PTE28

PTE26

VSS

VDD

PTF5

K

L

LLWU_P15 LLWU_P14 LLWU_P13

PTD0/

PTE18

VREFL

VSSA

TAMPER1 TAMPER2

TAMPER0/

RTC_

WAKEUP_B

VSS

VDD

PTF10

PTB6

PTF4

LLWU_P12

PTB0/

M

N

P

R

T

USB0_DP USB0_DM

TAMPER7

TAMPER6

TAMPER4

PTC19

PTA1

PTA3

PTC18

PTF22

PTF21

PTF25

PTA12

PTA26

PTA24

PTA10

PTA11

PTB3

PTF3

M

N

P

R

T

LLWU_P5

PGA2_DP/ PGA2_DM/

ADC2_DP0/ ADC2_DM0/

ADC3_DP3/ ADC3_DM3/

ADC0_DP1 ADC0_DM1

ADC0_SE16/

CMP1_IN2/

ADC0_SE21

PTA13/

VDDA

VBAT

PTA16

PTA15

PTA14

PTA8

PTA7

PTA6

PTA29

PTA28

PTA25

PTF2

LLWU_P4

PGA3_DP/ PGA3_DM/

ADC3_DP0/ ADC3_DM0/

ADC2_DP3/ ADC2_DM3/

ADC1_DP1 ADC1_DM1

ADC1_SE16/

CMP2_IN2/ VREFH

ADC0_SE22

PTE24

PTE25

PTF23

PTF24

PTF0

DAC1_OUT/

PGA0_DP/ PGA0_DM/ DAC0_OUT/

ADC0_DP0/ ADC0_DM0/ CMP1_IN3/

ADC1_DP3 ADC1_DM3 ADC0_SE23

CMP0_IN4/

CMP2_IN3/

ADC1_SE23

PTA4/

TAMPER3 TAMPER5

RESET_b

LLWU_P3

VREF_OUT/

PGA1_DP/ PGA1_DM/

CMP1_IN5/

ADC1_DP0/ ADC1_DM0/

CMP0_IN5/

VSS

4

EXTAL32

5

XTAL32

6

PTA0

7

PTA2

8

PTF26

9

PTF27

10

PTA17

11

PTA5

12

PTA9

13

VSS

14

PTA18

15

PTA19

16

ADC0_DP3 ADC0_DM3

ADC1_SE18

1

2

3

Figure 49. K70 256 MAPBGA Pinout Diagram

9 Revision History

The following table provides a revision history for this document.

K70 Sub-Family, Rev. 7, 02/2018

NXP Semiconductors

95

Revision History

Table 64. Revision History

Rev. No.

Date

Substantial Changes

3

4

5

3/2012

10/2012

10/2013

Initial public release

Replaced TBDs throughout.

Changes for 4N96B mask set:

• Min VDD operating requirement specification updated to support operation down to

1.71V.

New specifications:

• Updated Vdd_ddr min specification.

• Added Vodpu specification.

• Removed Ioz, Ioz_ddr, and Ioz_tamper Hi-Z leakage specfications. They have been

replaced by new Iina, Iind, and Zind specifications.

• Fpll_ref_acc specification has been added.

• I²C module was previously covered by the general switching specifications. To provide

more detail on I²C operation a dedicated Inter-Integrated Circuit Interface (I²C) timing

section has been added.

Modified specifications:

• Vref_ddr max spec has been updated.

• Tpor spec has been split into two specifications based on VDD slew rate.

• Trd1allx and Trd1alln max have been updated.

• 16-bit ADC Temp sensor slope and Temp sensor voltage (Vtemp25) have been

modified. The typical values that were listed previously have been updated, and min

and max specifications have been added.

Corrections:

• Some versions of the datasheets listed incorrect clock mode information in the

"Diagram: Typical IDD_RUN operating behavior section." These errors have been

corrected.

• Fintf_ft specification was previously shown as a max value. It has been corrected to be

shown as a typical value as originally intended.

• Corrected DDR write and read timing diagrams to show the correct location of the Tcmv

specification.

• SDHC peripheral 50MHz high speed mode options were left out of the last datasheet.

These have been added to the SDHC specifications section.

6

09/2015

• Updated Power Sequencing section

• Added footnote to ambient temperature specification of Thermal Operating

requirements

• Updated the data and DQS waveforms in DDR read timing diagram

• Removed "USB HS/LS/FS on-the-go controller with on-chip high speed transceiver"

from features section

• Updated Terminology and guidelines section

• Updated the footnotes and the values of Power consumption operating behaviors table

• Added Notes in USB electrical specification section

• Updated I2C timing table

7

02/2018

• Updated maximum SDHC frequency in SDHC specifications

• Added MDIO serial management timing specifications section in Ethernet Switching

SPecifications

K70 Sub-Family, Rev. 7, 02/2018

96

NXP Semiconductors

Information in this document is provided solely to enable system and software

implementers to use NXP products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits based

on the information in this document. NXP reserves the right to make changes

without further notice to any products herein.

How to Reach Us:

Home Page:

nxp.com

Web Support:

nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of

its products for any particular purpose, nor does NXP assume any liability arising

out of the application or use of any product or circuit, and specifically disclaims

any and all liability, including without limitation consequential or incidental

damages. “Typical” parameters that may be provided in NXP data sheets and/or

specifications can and do vary in different applications, and actual performance

may vary over time. All operating parameters, including “typicals,” must be

validated for each customer application by customer's technical experts. NXP

does not convey any license under its patent rights nor the rights of others. NXP

sells products pursuant to standard terms and conditions of sale, which can be

found at the following address: nxp.com/SalesTermsandConditions.

NXP, the NXP logo,NXP SECURE CONNECTIONS FOR A SMARTER WORLD,

Freescale, the Freescale logo, the Energy Efficient Solutions logo, and Kinetis

are trademarks of NXP B.V. All other product or service names are the property

of their respective owners. Arm and Cortex are registered trademarks of Arm

Document Number K70P256M120SF3

Revision 7, 02/2018


型号：	935319892518
厂家：	NXP
描述：	RISC Microcontroller 微控制器外围集成电路
文件：	总97页 (文件大小：1351K)
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