935321423557_技术文档

Document Number: IMX51AEC

Freescale Semiconductor

Data Sheet: Technical Data

Rev. 6, 10/2012

IMX51A

Package Information

Plastic Package

Case 2017 19 x 19 mm, 0.8 mm pitch

i.MX51A Automotive and

Infotainment Applications

Processors

Ordering Information

See Table 1 on page 2 for ordering information.

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 2

1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1. Special Signal Considerations . . . . . . . . . . . . . . . 11

3. IOMUX Configuration for Boot Media . . . . . . . . . . . . . . . 13

3.1. NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2. SD/MMC IOMUX Pin Configuration . . . . . . . . . . . 14

3.3. I²C IOMUX Pin Configuration . . . . . . . . . . . . . . . . 14

3.4. eCSPI/CSPI IOMUX Pin Configuration . . . . . . . . 15

3.5. Wireless External Interface Module (WEIM) . . . . 15

3.6. UART IOMUX Pin Configuration . . . . . . . . . . . . . 15

3.7. USB-OTG IOMUX Pin Configuration . . . . . . . . . . 15

4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 16

4.2. Supply Power-Up/Power-Down Requirements and

Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4. Output Buffer Impedance Characteristics . . . . . . 29

4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 33

4.6. Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.7. External Peripheral Interfaces . . . . . . . . . . . . . . . 72

5. Package Information and Contact Assignments . . . . . 151

5.1. 19 x 19 mm Package Information . . . . . . . . . . . . 151

5.2. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 169

6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

1 Introduction

The MCIMX51A (i.MX51A) Automotive Infotainment

Processor represents Freescale Semiconductor’s latest

addition to a growing family of multimedia focused

products offering high performance processing with a

high degree of functional integration, aimed at the

growing automotive infotainment market. This device

includes two graphics processors, 720p video

processing, dual display, and many I/Os.

The i.MX51A processor features Freescale’s advanced

implementation of the ARM Cortex A8™ core, targeting

speeds up to 600 MHz with 200 MHz I/O bus clock

DDR2 and mobile DDR. This device is well-suited for

graphics rendering for HMI and navigation, high

performance speech processing with large databases,

video processing and display, audio playback and

ripping, and many other applications.

Introduction

Features of the i.MX51A processor include the following:

•

Smart Speed Technology—The i.MX51A device has power management throughout the IC that

enables the rich suite of multimedia feature and peripherals to achieve minimum power

consumption in both active and various low power modes. Smart Speed Technology enables the

designer to deliver a feature-rich product that requires levels of power that are far less than industry

expectations.

•

Multimedia—The multimedia performance of the ARM Cortex A8 is enhanced with a multi-level

cache system, a Multi-standard Hardware Video CODECs, autonomous image processing unit,

multi-standard audio CODECs, Neon (an advanced SIMD, 32 bit single-precision floating point

support and vector floating point co-processor), and a programmable smart DMA controller.

Powerful Graphics Acceleration—The i.MX51A processor has an integrated Graphics Processing

Unit which includes an OpenGl 2.0 GPU that provides 27Mtri/sec, 166Mpix/s, and 664Mpix/s

z-plane performance. Silicon version 2.0 of the i.MX51A device includes an independent OpenVG

GPU operating at166Mpix/s.

Interface Flexibility—The i.MX51A processor supports connections to all popular types of

external memories: mobile DDR, DDR2, PSRAM, NOR Flash, NAND Flash (MLC and SLC), and

OneNAND (managed NAND). The i.MX51A processor also includes a rich multimedia suite of

interfaces: LCD controller for two displays, CMOS sensor interface, High-Speed USB On-The-Go

plus three High-Speed USB hosts, high-speed MMC/SDIO, Fast Ethernet controller, UART, I2C,

I2S (SSI), and others.

1.1

Ordering Information

Table 1 provides the ordering information.

Table 1. Ordering Information

Junction

Temperature

1

Part Number

Mask Set

Features

Package

^{Range (}°C)

MCIMX514AJM6C

MCIMX516AJM6C

M77X

No hardware video codecs

Full specification

–40 to 125

19 x 19 mm, 0.8 mm pitch BGA

Case 2017

–40 to 125

19 x 19 mm, 0.8 mm pitch BGA

Case 2017

1

Case 2017 and Case 2058 are RoHS compliant, lead-free, MSL = 3.

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Introduction

1.2

Block Diagram

Figure 1 shows the functional modules of the processor.

Battery Ctrl

Device

LCD Display 1

LCD Display 2

USB

Dev/Host

DDR

Memory

NOR/Nand

Flash

Camera 1

Camera 2

Digital

Audio

ATA HDD

Application Processor Domain (AP)

USB PHY

External

Memory I/F

TV Encoder

Image Processing

Subsystem

AP Peripherals

USB OTG +

3 HS Ports

eCSPI (2

CSPI

)

Smart DMA

(SDMA)

UART (3)

AUDMUX

2

ARM Cortex A8

Platform

I C(2),HSI C

1-WIRE

PWM (2)

IIM

SPBA

ARM Cortex A8

Neon and VFP

L1 I/D cache

L2 cache

Internal

RAM

(128 Kbytes)

SDMA Peripherals

IOMUXC

KPP

eSDHC (4)

UART

SSI

eCSPI (1 of 2)

SIM

Boot

ROM

ETM, CTI0,1

GPIOx32 (4)

SJC

SPDIF Tx

FEC

P-ATA

Security

SAHARA

Lite

SSI (3)

FIRI

Video

Proc. Unit

(VPU)

RTIC

SCC

Debug

DAP

3D Graphics

Proc Unit

(GPU)

SRTC

CSU

TPIU

CTI (2)

TZIC

Fuse Box

Clock and Reset

PLL (3)

Graphics

Memory

(128 Kbytes)

Timers

WDOG (2)

CCM

GPC

SRC

GPT

2D Graphics

Proc Unit

(GPU2D)

EPIT (2)

XTALOSC

CAMP (2)

IrDA

XVR

USB-OTG

XVR

Access.

Conn.

Bluetooth

Keypad

MMC/SDIO

WLAN

JTAG

Figure 1. Functional Block Diagram

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Features

2 Features

The i.MX51A processor contains a large number of digital and analog modules that are described in

Table 2.

Table 2. i.MX51A Digital and Analog Modules

Block

Mnemonic

Block Name Subsystem

Brief Description

1-WIRE

1-Wire

Interface

Connectivity

Peripherals

1-Wire support provided for interfacing with an on-board EEPROM, and smart

battery interfaces, for example: Dallas DS2502.

ARM

The ARM Cortex™-A8 Core Platform consists of the ARM Cortex™-A8

processor version r2p5 (with TrustZone) and its essential sub-blocks. It contains

the Level 2 Cache Controller, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data

cache, and a 256 Kbyte L2 cache. The platform also contains an Event Monitor

and Debug modules. It also has a NEON co-processor with SIMD media

processing architecture, register file with 32 × 64-bit general-purpose registers,

an Integer execute pipeline (ALU, Shift, MAC), dual, single-precision floating

point execute pipeline (FADD, FMUL), load/store and permute pipeline and a

Non-Pipelined Vector Floating Point (VFP) co-processor (VFPv3).

Cortex™-A8 Cortex™-A8

Platform

Audio

Multimedia

Peripherals

The elements of the audio subsystem are three Synchronous Serial Interfaces

(SSI1-3), a Digital Audio Mux (AUDMUX), and Digital Audio Out (SPDIF TX).

See the specific interface listings in this table.

Subsystem Subsystem

AUDMUX

Digital Audio Multimedia

Mux Peripherals

The AUDMUX is a programmable interconnect for voice, audio, and

synchronous data routing between host serial interfaces (for example, SSI1,

SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The

AUDMUX has seven ports (three internal and four external) with identical

functionality and programming models. A desired connectivity is achieved by

configuring two or more AUDMUX ports.

CCM

GPC

SRC

Clock Control Clocks,

Module Resets, and

Global Power Power Control a Frequency Pre-Multiplier (FPM).

Controller

SystemReset

Controller

These modules are responsible for clock and reset distribution in the system,

and also for system power management. The modules include three PLLs and

CSPI-1,

eCSPI-2

eCSPI-3

Configurable Connectivity

Full-duplex enhanced Synchronous Serial Interface, with data rate up to

66.5 Mbit/s (for eCSPI, master mode). It is configurable to support Master/Slave

modes, four chip selects to support multiple peripherals.

SPI,

Peripherals

Enhanced

CSPI

CSU

Central

Security Unit

Security

The Central Security Unit (CSU) is responsible for setting comprehensive

security policy within the i.MX51 platform, and for sharing security information

between the various security modules. The Security Control Registers (SCR) of

the CSU are set during boot time by the High Assurance Boot (HAB) code and

are locked to prevent further writing.

Debug

System

Debug

System

Control

The Debug System provides real-time trace debug capability of both instructions

and data. It supports a trace protocol that is an integral part of the ARM Real

Time Debug solution (RealView). Real-time tracing is controlled by specifying a

set of triggering and filtering resources, which include address and data

comparators, cross-system triggers, counters, and sequencers.

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Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block Name Subsystem Brief Description

Block

Mnemonic

EMI

External

Memory

Interface

Connectivity

Peripherals

The EMI is an external and internal memory interface. It performs arbitration

between multi-AXI masters to multi-memory controllers, divided into four major

channels: fast memories (Mobile DDR, DDR2) channel, slow memories

(NOR-FLASH/PSRAM/NAND-FLASH and so on) channel, internal memory

(RAM, ROM) channel and graphical memory (GMEM) Channel.

In order to increase the bandwidth performance, the EMI separates the buffering

and the arbitration between different channels so parallel accesses can occur.

By separating the channels, slow accesses do not interfere with fast accesses.

EMI features:

• 64-bit and 32-bit AXI ports

• Enhanced arbitration scheme for fast channel, including dynamic master

priority, and taking into account which pages are open or closed and what

type (Read or Write) was the last access

• Flexible bank interleaving

• Supports 16/32-bit Mobile DDR up to 200 MHz SDCLK (mDDR400)

• Supports 16/32-bit (Non-Mobile) DDR2 up to 200 MHz SDCLK (DDR2-400)

• Supports up to 2 Gbit Mobile DDR memories

• Supports 16-bit (in muxed mode only) PSRAM memories (sync and async

operating modes), at slow frequency, for debugging purposes

• Supports 32-bit NOR-Flash memories (only in muxed mode), at slow

frequencies for debugging purposes

• Supports 4/8-ECC, page sizes of 512 Bytes, 2 Kbytes and 4 Kbytes

• NAND-Flash (including MLC)

• Multiple chip selects

• Enhanced Mobile DDR memory controller, supporting access latency hiding

• Supports watermarking for security (Internal and external memories)

• Supports Samsung OneNAND™ (only in muxed I/O mode)

EPIT-1

EPIT-2

Enhanced

Periodic

Interrupt

Timer

Peripherals

Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is

enabled by software. It is capable of providing precise interrupts at regular

intervals with minimal processor intervention. It has a 12-bit prescaler for division

of input clock frequency to get the required time setting for the interrupts to occur,

and counter values can be programmed on the fly.

eSDHC-1

eSDHC-2

eSDHC-3

Enhanced

Multi-Media

Card/

SecureDigital

Host

Connectivity

Peripherals

The features of the eSDHC module, when serving as host, include the following:

• Conforms to SD Host Controller Standard Specification version 2.0

• Compatible with the MMC System Specification version 4.2

• Compatible with the SD Memory Card Specification version 2.0

• Compatible with the SDIO Card Specification version 1.2

• Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD

Combo, MMC and MMC RS cards

Controller

• Configurable to work in one of the following modes:

—SD/SDIO 1-bit, 4-bit

—MMC 1-bit, 4-bit, 8-bit

• Full-/high-speed mode

• Host clock frequency variable between 32 kHz to 52 MHz

• Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines

• Up to 416 Mbps data transfer for MMC cards using eight parallel data lines

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Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block

Mnemonic

Block Name Subsystem

Brief Description

eSDHC-4

(muxed with Multi-Media

Enhanced

Connectivity

Peripherals

Can be configured as eSDHC (see above) and is muxed with the P-ATA

interface.

P-ATA)

Card/

SecureDigital

Host

Controller

FEC

Fast Ethernet Connectivity

The Ethernet Media Access Controller (MAC) is designed to support both

10 Mbps and 100 Mbps ethernet/IEEE Std 802.3™ networks. An external

transceiver interface and transceiver function are required to complete the

interface to the media.

Controller

Peripherals

FIRI

Fast

Infra-Red

Interface

Connectivity

Peripherals

Fast Infra-Red Interface

GPIO-1

GPIO-2

GPIO-3

GPIO-4

General

Purpose I/O

Modules

System

Control

Peripherals

These modules are used for general purpose input/output to external ICs. Each

GPIO module supports up to 32 bits of I/O.

GPT

General

Purpose

Timer

Peripherals

Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a

programmable prescaler and compare and capture register. A timer counter

value can be captured using an external event, and can be configured to trigger

a capture event on either the leading or trailing edges of an input pulse. When

the timer is configured to operate in “set and forget” mode, it is capable of

providing precise interrupts at regular intervals with minimal processor

intervention. The counter has output compare logic to provide the status and

interrupt at comparison. This timer can be configured to run either on an external

clock or on an internal clock.

GPU

Graphics

Processing

Unit

Multimedia

Peripherals

The GPU provides hardware acceleration for 2D and 3D graphics

algorithms with sufficient processor power to run desk-top quality

interactive graphics applications on displays up to HD720

resolution. It supports color representation up to 32 bits per pixel.

The GPU with its 128 KByte memory enables high performance mobile 3D and

2D vector graphics at rates up to 27 Mtriangles/sec, 166 Mpixels/sec,

664 Mpixels/sec (Z).

GPU2D

Graphics

Processing

Unit-2D Ver. 1

Multimedia

Peripherals

The GPU2D provides hardware acceleration for 2D graphic

algorithms with sufficient processor power to run desk-top quality

interactive graphics applications on displays up to HD720 resolution.

2

I C-1

I C Interface Connectivity

Peripherals

I C provides serial interface for controlling peripheral devices. Data rates of up

2

I C-2

to 400 Kbps are supported by two of the I C ports. Data rates of up to 3.4 Mbps

2

HS-I C

(I C Specification v2.1) are supported by the HS-I C.

2

Note: See the errata for the HS-I C in the i.MX51 Chip Errata. The two standard

2

I C modules have no errata.

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Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block

Mnemonic

Block Name Subsystem

Brief Description

IIM

IC

Security

The IC Identification Module (IIM) provides an interface for reading,

Identification

Module

programming, and/or overriding identification and control information stored in

on-chip fuse elements. The module supports electrically programmable poly

fuses (e-Fuses). The IIM also provides a set of volatile software-accessible

signals that can be used for software control of hardware elements not requiring

non-volatility. The IIM provides the primary user-visible mechanism for

interfacing with on-chip fuse elements. Among the uses for the fuses are unique

chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode,

boot characteristics, and various control signals requiring permanent

non-volatility. The IIM also provides up to 28 volatile control signals. The IIM

consists of a master controller, a software fuse value shadow cache, and a set

of registers to hold the values of signals visible outside the module.

IOMUXC

IPU

IOMUX

Control

System

Control

Peripherals

This module enables flexible I/O multiplexing. Each I/O pad has default as well

as several alternate functions. The alternate functions are software configurable.

Image

Processing

Unit

Multimedia

Peripherals

IPU enables connectivity to displays and image sensors, relevant processing

and synchronization. It supports two display ports and two camera ports,

through the following interfaces.

• Legacy Interfaces

• Analog TV interfaces (through a TV encoder bridge)

The processing includes:

• Support for camera control

• Image enhancement: color adjustment and gamut mapping, gamma

correction and contrast enhancement, sharpening and noise reduction

• Video/graphics combining

• Support for display backlight reduction

• Image conversion—resizing, rotation, inversion and color space conversion

• Synchronization and control capabilities, allowing autonomous operation.

• Hardware de-interlacing support

KPP

Keypad Port

Connectivity The KPP supports an 8 × 8 external keypad matrix. The KPP features are as

Peripherals

follows:

• Open drain design

• Glitch suppression circuit design

• Multiple keys detection

• Standby key press detection

P-ATA(Muxed Parallel ATA

with

eSDHC-4

Connectivity

Peripherals

The P-ATA block is an AT attachment host interface. Its main use is to interface

with hard disc drives and optical disc drives. It interfaces with the ATA-5

(UDMA-4) compliant device over a number of ATA signals. It is possible to

connect a bus buffer between the host side and the device side. This is muxed

with eSDHC-4 interfaces.

PWM-1

PWM-2

Pulse Width

Modulation

Connectivity

Peripherals

The pulse-width modulator (PWM) has a 16-bit counter and is optimized to

generate sound from stored sample audio images. It can also generate tones.

The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate sound.

RAM

128 Kbytes

Internal RAM Internal

Memory

Unified RAM, can be split between Secure RAM and Non-Secure RAM

ROM

36 Kbytes

Boot ROM

Internal

Memory

Supports secure and regular Boot Modes

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Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block

Mnemonic

Block Name Subsystem

Brief Description

RTIC

Real Time

Integrity

Checker

Security

Protecting read-only data from modification is one of the basic elements in

trusted platforms. The Run-Time Integrity Checker v3 (RTICv3) module, is a data

monitoring device responsible for ensuring that memory content is not corrupted

during program execution. The RTICv3 mechanism periodically checks the

integrity of code or data sections during normal OS run-time execution without

interfering with normal operation. The RTICv3’s purpose is to ensure the integrity

of the peripheral memory contents, protect against unauthorized external

memory elements replacement, and assist with boot authentication.

SAHARA Lite SAHARA

SAHARA (Symmetric/Asymmetric Hashing and Random Accelerator) is a

security co-processor. It implements symmetric encryption algorithms, (AES,

DES, 3DES, and RC4), public key algorithms, hashing algorithms (MD5, SHA-1,

SHA-224, and SHA-256), and a hardware random number generator. It has a

slave IP bus interface for the host to write configuration and command

information, and to read status information. It also has a DMA controller, with an

AHB bus interface, to reduce the burden on the host to move the required data

to and from memory.

security

accelerator

Lite

SCC

Security

Controller

The Security Controller is a security assurance hardware module designed to

safely hold sensitive data such as encryption keys, digital right management

(DRM) keys, passwords, and biometrics reference data. The SCC monitors the

system’s alert signal to determine if the data paths to and from it are

secure—that is, cannot be accessed from outside of the defined security

perimeter. If not, it erases all sensitive data on its internal RAM. The SCC also

features a Key Encryption Module (KEM) that allows non-volatile (external

memory) storage of any sensitive data that is temporarily not in use. The KEM

utilizes a device-specific hidden secret key and a symmetric cryptographic

algorithm to transform the sensitive data into encrypted data.

SDMA

Smart Direct System

The SDMA is multi-channel flexible DMA engine. It helps in maximizing system

performance by off loading various cores in dynamic data routing.

The SDMA features list is as follows:

Memory

Access

Control

Peripherals

• Powered by a 16-bit instruction-set micro-RISC engine

• Multi-channel DMA supports up to 32 time-division multiplexed DMA channels

• 48 events with total flexibility to trigger any combination of channels

• Memory accesses including linear, FIFO, and 2D addressing

• Shared peripherals between ARM Cortex™-A8 and SDMA

• Very fast context-switching with two-level priority-based preemptive

multi-tasking

• DMA units with auto-flush and prefetch capability

• Flexible address management for DMA transfers (increment, decrement, and

no address changes on source and destination address)

• DMA ports can handle unit-directional and bi-directional flows (copy mode)

• Up to 8-word buffer for configurable burst transfers for EMI

• Support of byte-swapping and CRC calculations

• A library of scripts and API are available

SIM

Subscriber

Identity

Module

Connectivity

Peripherals

The SIM is an asynchronous interface with additional features for allowing

communication with Smart Cards conforming to the ISO 7816 specification. The

SIM is designed to facilitate communication to SIM cards or pre-paid phone

cards.

Interface

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Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block Name Subsystem Brief Description

Secure JTAG System

Block

Mnemonic

SJC

JTAG manipulation is a known hacker’s method of executing unauthorized

program code, getting control over secure applications, and running code in

privileged modes. The JTAG port provides a debug access to several hardware

blocks including the ARM processor and the system bus.

Interface

Control

Peripherals

The JTAG port must be accessible during platform initial laboratory bring-up,

manufacturing tests and troubleshooting, as well as for software debugging by

authorized entities. However, in order to properly secure the system,

unauthorized JTAG usage should be strictly forbidden.

In order to prevent JTAG manipulation while allowing access for manufacturing

tests and software debugging, the i.MX51A processor incorporates a

mechanism for regulating JTAG access. The i.MX51A Secure JTAG Controller

provides four different JTAG security modes that can be selected via e-fuse

configuration.

SPBA

SPDIF

SRTC

Shared

Peripheral

Bus Arbiter

System

Control

Peripherals

SPBA (Shared Peripheral Bus Arbiter) is a two-to-one IP bus interface (IP bus)

arbiter.

Sony Philips Multimedia

Digital

Interface

A standard digital audio transmission protocol developed jointly by the Sony and

Philips corporations. Only the transmitter functionality is supported.

Peripherals

Secure Real Security

Time Clock

The SRTC incorporates a special System State Retention Register (SSRR) that

stores system parameters during system shutdown modes. This register and all

SRTC counters are powered by dedicated supply rail NVCC_SRTC_POW. The

NVCC_SRTC_POW can be energized even if all other supply rails are shut

down. The power for this block comes from NVCC_SRTC_POW supply. When

this supply is driven by the MC13892 power management controller, this block

can be power backed up via the coin-cell feature of the MC13892.This register

is helpful for storing warm boot parameters. The SSRR also stores the system

security state. In case of a security violation, the SSRR mark the event (security

violation indication).

SSI-1

I2S/SSI/AC97 Connectivity

The SSI is a full-duplex synchronous interface used on the i.MX51A processor

to provide connectivity with off-chip audio peripherals. The SSI interfaces

connect internally to the AUDMUX which interfaces to the i.MX51 system

memory. The SSI supports a wide variety of protocols (SSI normal, SSI network,

I2S, and AC-97), bit depths (up to 24 bits per word), and clock/frame sync

options.

Interface

Peripherals

SSI-2

SSI-3

Each SSI has two pairs of 8x24 FIFOs and hardware support for an external

DMA controller in order to minimize its impact on system performance. The

second pair of FIFOs provides hardware interleaving of a second audio stream,

which reduces CPU overhead in use cases where two timeslots are being used

simultaneously.

TVE

TV Encoder Multimedia

The TVE is implemented in conjunction with the Image Processing Unit (IPU)

allowing handheld devices to display captured still images and

video directly on a TV or LCD projector. It supports the following analog video

outputs: composite, S-video, and component video up to HD720p/1080i.

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Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block

Mnemonic

Block Name Subsystem

Brief Description

TZIC

TrustZone

Aware

Interrupt

Controller

ARM/Control The TrustZone Interrupt Controller (TZIC) collects interrupt requests from all

i.MX51 sources and routes them to the ARM core. Each interrupt can be

configured as a normal or a secure interrupt. Software Force Registers and

software Priority Masking are also supported.

UART-1

UART-2

UART-3

UART

Interface

Connectivity

Peripherals

Each of the UART modules supports the following serial data transmit/receive

protocols and configurations:

• 7 or 8 bit data words, 1 or 2 stop bits, programmable parity (even, odd, or

none)

• Programmable baud rates up to 4 MHz. This is a higher max baud rate relative

to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard and

previous Freescale UART modules.

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud

• IrDA 1.0 support (up to SIR speed of 115200 bps)

• Option to operate as 8-pins full UART, DCE, or DTE

USB

VPU

USB 2.0

Connectivity

Peripherals

USB-OTG contains one high-speed OTG module, which is internally connected

to the on-chip HS USB PHY. There are an additional three high-speed host

modules that require external USB PHYs.

High-Speed

OTG and 3x

Hosts

Video

Processing

Unit

Multimedia

Peripherals

A high-performing video processing unit (VPU), which covers many SD-level

video decoders and SD-level encoders as a multi-standard video codec engine

as well as several important video processing such as rotation and mirroring.

VPU Features:

• MPEG-4 decode: 720p, 30 fps, simple profile and advanced simple profile

• MPEG-4 encode: D1, 25/30 fps, simple profile

• H.263 decode: 720p, 30 fps, profile 3

• H.263 encode: D1, 25/30 fps, profile 3

• H.264 decode: 720p, 30 fps, baseline, main, and high profile

• H.264 encode: D1, 25/30 fps, baseline profile

• MPEG-2 decode: 720p, 30 fps, MP-ML

• MPEG-2 encode: D1, 25/30 fps, MP-ML (in software with partial acceleration

in hardware)

• VC-1 decode: 720p, 30 fps, simple, main, and advanced profile

• DivX decode: 720p, 30 fps versions 3, 4, and 5

• RV10 decode: 720p, 30 fps

• MJPEG decode: 32 Mpix/s

• MJPEG encode: 64 Mpix/s

WDOG-1

Watch Dog

Timer

Peripherals

The Watch Dog Timer supports two comparison points during each counting

period. Each of the comparison points is configurable to evoke an interrupt to the

ARM core, and a second point evokes an external event on the WDOG line.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

10

Freescale Semiconductor

Features

Table 2. i.MX51A Digital and Analog Modules (continued)

Block Name Subsystem Brief Description

Block

Mnemonic

WDOG-2

(TZ)

Watch Dog

(TrustZone)

Timer

Peripherals

The TrustZone Watchdog (TZ WDOG) timer module protects against TrustZone

starvation by providing a method of escaping normal mode and forcing a switch

to the TZ mode. TZ starvation is a situation where the normal OS prevents

switching to the TZ mode. This situation should be avoided, as it can

compromise the system’s security. Once the TZ WDOG module is activated, it

must be serviced by TZ software on a periodic basis. If servicing does not take

place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ mapped

interrupt that forces switching to the TZ mode. If it is still not served, the TZ

WDOG asserts a security violation signal to the CSU. The TZ WDOG module

cannot be programmed or deactivated by a normal mode SW.

XTALOSC

Crystal

Clocking

The XTALOSC module allows connectivity to an external crystal.

Oscillator I/F

2.1

Special Signal Considerations

Table 3 lists special signal considerations for the i.MX51. The signal names are listed in alphabetical order.

The package contact assignments are found in Section 5, “Package Information and Contact

Assignments.” Signal descriptions are defined in the i.MX51 Multimedia Applications Processor

Reference Manual (MCIMX51RM).

Table 3. Special Signal Considerations

Signal Name

CKIH1, CKIH2

Remarks

Inputs feeding CAMPs (Clock Amplifiers) that have on-chip ac coupling precluding the need for

external coupling capacitors. The CAMPs are enabled by default, but the main clocks feeding the

on-chip clock tree are sourced from XTAL/EXTAL by default. Optionally, the use of a low jitter

external oscillators to feed CKIH1 or CKIH2 (while not required) can be an advantage if low jitter

or special frequency clock sources are required by modules driven by CKIH1 or CKIH2. See CCM

chapter in the i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM) for

details on the respective clock trees.

After initialization, the CAMPs could be disabled (if not used) by CCM registers (CCR CAMPx_EN

field). If disabled, the on-chip CAMP output is low; the input is irrelevant. If unused, the user should

tie CKIH1/CKIH2 to GND for best practice.

CLK_SS

Clock Source Select is the input that selects the default reference clock source providing input to

the DPLLs. To use a reference in the megahertz range per Table 8, tie CLK_SS to GND to select

EXTAL/XTAL. To use a reference in the kilohertz range per Table 59, tie CLK_SS to NVCC_PER3

to select CKIL. After initialization, the reference clock source can be changed (initial setting is

overwritten).

Note: Because this input has a keeper circuit, Freescale recommends tying this input to directly

^{to GND or NVCC_PER3. If a series resistor is used its value must be}≤ 4.7 kΩ.

COMP

The user should bypass this reference with an external 0.1 µF capacitor tied to GND. If TV OUT is

not used, float the COMP contact and ensure the DACs are powered down.

Note: Previous engineering samples required this reference to be bypassed to a positive supply.

FASTR_ANA and

FASTR_DIG

These signals are reserved for Freescale manufacturing use only. User must tie both connections

to GND.

GPANAIO

This signal is reserved for Freescale manufacturing use only. Users should float this output.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

11

Features

Table 3. Special Signal Considerations (continued)

Remarks

Signal Name

GPIO_NAND

This is a general-purpose input/output (GPIO3_12) on the NVCC_NANDF_A power rail.

These signals are analog TV outputs that should be tied to GND when not being used.

IOB, IOG, IOR,

IOB_BACK, IOG_BACK,

and IOR_BACK

JTAG_nnnn

The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,

if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is

followed. For example, do not use an external pull down on an input that has on-chip pull-up.

JTAG_TDO is configured with a keeper circuit such that the floating condition is eliminated if an

external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and

should be avoided.

JTAG_MOD is referenced as SJC_MOD in the i.MX51 Multimedia Applications Processor

Reference Manual (MCIMX51RM). Both names refer to the same signal. JTAG_MOD must be

externally connected to GND for normal operation. Termination to GND through an external

pull-down resistor (such as 1 kΩ) is allowed.

NC

These signals are No Connect (NC) and should be floated by the user.

PMIC_INT_REQ

When using the MC13892 power management IC, the PMIC_INT_REQ high-priority interrupt input

on i.MX51 should be either floated or tied to NVCC_SRTC_POW with a 4.7 kΩ to 68 kΩ resistor.

This avoids a continuous current drain on the real-time clock backup battery due to a 100 kΩ

on-chip pull-up resistor.

PMIC_INT_REQ is not used by the Freescale BSP (board support package) software. The BSP

requires that the general-purpose INT output from the MC13892 be connected to the i.MX51 GPIO

input GPIO1_8 configured to cause an interrupt that is not high-priority.

The original intent was for PMIC_INT_REQ to be connected to a circuit that detects when the

battery is almost depleted. In this case, the I/O must be configured as alternate mode 0 (ALT0 =

power fail).

POR_B

This cold reset negative logic input resets all modules and logic in the IC.

Note: The POR_B input must be immediately asserted at power-up and remain asserted until

after the last power rail is at its working voltage.

RESET_IN_B

This warm reset negative logic input resets all modules and logic except for the following:

• Test logic (JTAG, IOMUXC, DAP)

• SRTC

• Memory repair – Configuration of memory repair per fuse settings

• Cold reset logic of WDOG – Some WDOG logic is only reset by POR_B. See WDOG chapter

in i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM) for details.

RREFEXT

Determines the reference current for the USB PHY bandgap reference. An external 6.04 kΩ 1%

resistor to GND is required.

SGND, SVCC, and

SVDDGP

These sense lines provide the ability to sense actual on-chip voltage levels on their respective

supplies. SGND monitors differentials of the on-chip ground versus an external power source.

SVCC monitors on-chip VCC, and SVDDGP monitors VDDGP. Freescale recommends connection

of the SVCC and SVDDGP signals to the feedback inputs of switching power-supplies or to test

points.

STR

This signal is reserved for Freescale manufacturing use. The user should float this signal.

TEST_MODE

TEST_MODE is for Freescale factory use only. This signal is internally connected to an on-chip

pull-down device. Users must either float this signal or tie it to GND.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

12

Freescale Semiconductor

IOMUX Configuration for Boot Media

Table 3. Special Signal Considerations (continued)

Signal Name

Remarks

VREF

When using VREF with DDR-2 I/O, the nominal 0.9 V reference voltage must be half of the

NVCC_EMI_DRAM supply. The user must tie VREF to a precision external resistor divider. Use a

1 kΩ 0.5% resistor to GND and a 1 kΩ 0.5% resistor to NVCC_EMI_DRAM. Shunt each resistor

with a closely-mounted 0.1 µF capacitor.

To reduce supply current, a pair of 1.5 kΩ 0.1% resistors can be used. Using resistors with

recommended tolerances ensures the 2% VREF tolerance (per the DDR-2 specification) is

maintained when four DDR-2 ICs plus the i.MX51 are drawing current on the resistor divider.

Note: When VREF is used with mDDR this signal must be tied to GND.

VREFOUT

This signal determines the Triple Video DAC (TVDAC) reference voltage. The user must tie

VREFOUT to an external 1.05 kΩ 1% resistor to GND.

VREG

This regulator is no longer used and should be floated by the user.

XTAL/EXTAL

The user should tie a fundamental-mode crystal across XTAL and EXTAL. The crystal must be

^{rated for a maximum drive level of 100}μW or higher. An ESR (equivalent series resistance) of

80 Ω or less is recommended. Freescale BSP (Board Support Package) software requires 24 MHz

on EXTAL.

The crystal can be eliminated if an external 24 MHz oscillator is available. In this case, EXTAL must

be directly driven by the external oscillator and XTAL is floated. The EXTAL signal level must swing

from NVCC_OSC to GND. If the clock is used for USB, then there are strict jitter requirements: < 50

ps peak-to-peak below 1.2 MHz and < 100 ps peak-to-peak above 1.2 MHz for the USB PHY. The

COSC_EN bit in the CCM (Clock Control Module) must be cleared to put the on-chip oscillator

circuit in bypass mode which allows EXTAL to be externally driven. COSC_EN is bit 12 in the CCR

register of the CCM.

Table 4. JTAG Controller Interface Summary

JTAG

I/O Type

On-Chip Termination

JTAG_TCK

Input

100 kΩ pull-down

47 kΩ pull-up

Keeper

JTAG_TMS

JTAG_TDI

JTAG_TDO

Input

3-state output

Input

JTAG_TRSTB

JTAG_DE_B

JTAG_MOD

47 kΩ pull-up

100 kΩ pull-up

Input/open-drain output

Input

3 IOMUX Configuration for Boot Media

The information provided in this section describes the contacts assigned for each type of bootable media.

It also includes data about the clocks used during boot flow and their frequencies. Signals that can be

multiplexed appear in tables throughout this section. See the IOMUXC chapter in the i.MX51 Multimedia

Applications Processor Reference Manual (MCIMX51RM) for details about how to program the IOMUX

controller.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

13

IOMUX Configuration for Boot Media

3.1

NAND

The NAND Flash Controller (NFC) signals are not configured in the IOMUX. The NFC interface uses

dedicated contacts on the IC.

3.2

SD/MMC IOMUX Pin Configuration

Table 5 shows the SD/MMC IOMUX pin configuration.

Table 5. SD/MMC IOMUX Pin Configuration

Signal

CLK

eSDHC1 eSDHC2 eSDHC3

eSDHC4

SD1_CLK.alt0

SD1_CMD.alt0

SD1_DATA0.alt0

SD2_CLK.alt0

NANDF_RDY_INT.alt5

NANDF_CS2.alt5

SD2_CMD.alt0

NANDF_CS7.alt5

NANDF_RB1.alt5

CMD

SD2_DATA0.alt0

NANDF_WE_B.alt2

NANDF_CS3.alt5

DAT0

DAT1

DAT2

CD/DAT3

DAT4

DAT5

DAT6

DAT7

1

N/A

SD1_DATA3.alt0

SD2_DATA3.alt0

NANDF_RB0.alt5

NANDF_CS6.alt5

N/A

1

N/A in the ROM code indicates the pins are not available.

Only DAT0 is available when the SD/MMC is used for boot. The remaining lines (DAT1–DAT7) are not

available.

2

3.3

I C IOMUX Pin Configuration

2

The contacts assigned to the signals used by the three I C modules is shown in Table 6.

2

Table 6. I C IOMUX Pin Configuration

2

Signal

HSI C

I C1

I C2

SDA

SCL

I2C1_DAT.alt0

I2C1_CLK.alt0

I2C1_DAT.alt0

I2C1_CLK.alt0

GPIO1_3.alt2

GPIO1_2.alt2

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

14

Freescale Semiconductor

IOMUX Configuration for Boot Media

3.4

eCSPI/CSPI IOMUX Pin Configuration

The contacts assigned to the signals used by the three SPI modules is shown in Table 7.

Table 7. SPI IOMUX Pin Configuration

Signal

eCSPI1

eCSPI2

CSPI

MISO

MOSI

RDY

SCLK

SS0

CSPI1_MISO.alt0

CSPI1_MOSI.alt0

CSPI1_RDY.alt0

CSPI1_SCLK.alt0

NANDF_RB3.alt2

USBH1_NXT.alt1

USBH1_DIR.alt1

USBH1_STP.alt1

USBH1_CLK.alt1

N/A

NANDF_D15.alt2

NANDF_RB1.alt2

NANDF_RB2.alt2

1

N/A

SS1

N/A

USBH1_DATA5.alt1

N/A

SS2

SS3

N/A

1

N/A in the ROM code indicates the pins are not available.

3.5

Wireless External Interface Module (WEIM)

The WEIM interface signals are not configured in the IOMUX. The WEIM interface uses dedicated

contacts on the IC.

3.6

UART IOMUX Pin Configuration

The contacts assigned to the signals used by the three UART modules are shown in Table 8.

Table 8. UART IOMUX Pin Configuration

Signal

UART1

UART2

UART3

TXD

RXD

CTS

RTS

UART1_TXD.alt0

UART1_RXD.alt0

UART1_CTS.alt0

UART1_RTS.alt0

UART2_TXD.alt0

UART2_RXD.alt0

USBH1_DATA0.alt1

USBH1_DATA3.alt1

UART3_TXD.alt1

UART3_RXD.alt1

KEY_COL5.alt2

KEY_COL4.alt2

3.7

USB-OTG IOMUX Pin Configuration

The interface signals of the UTMI PHY are not configured in the IOMUX. The UTMI PHY interface uses

dedicated contacts on the IC.

Table 9. ULPI PHY IOMUX Pin Configuration

Signal

ULPI PHY

USB_PWR

USB_OC

GPIO1_8.alt1

GPIO1_9.alt1

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

15

Electrical Characteristics

Table 9. ULPI PHY IOMUX Pin Configuration (continued)

Signal

ULPI PHY

USBOTG_CLK

USBOTG_NXT

USBOTG_STP

USBOTG_DAT0

USBOTG_DAT1

USBOTG_DAT2

USBOTG_DAT3

USBOTG_DAT4

USBOTG_DAT5

USBOTG_DAT6

USBOTG_DAT7

EIM_CS4.alt2

EIM_CS3.alt2

EIM_CS2.alt2

EIM_D24.alt2

EIM_D25.alt2

EIM_D26.alt2

EIM_D27.alt2

EIM_D28.alt2

EIM_D29.alt2

EIM_D30.alt2

EIM_D31.alt2

NOTE

USB OTG ULPI port is not supported and it is not functional. On-chip PHY

is always used for the OTG port.

4 Electrical Characteristics

This section provides the device and module-level electrical characteristics for the i.MX51A processor.

4.1

Chip-Level Conditions

This section provides the device-level electrical characteristics for the IC. See Table 10 for a quick

reference to the individual tables and sections.

Table 10. i.MX51A Chip-Level Conditions

For these characteristics, …

Table 11, “Absolute Maximum Ratings”

Topic appears …

on page 17

on page 18

on page 19

Table 12, “Thermal Resistance Data”

Table 13, “i.MX51A Operating Ranges”

Table 14, “Interface Frequency”

CAUTION

Stresses beyond those listed under Table 11 may cause permanent damage

to the device. These are stress ratings only. Functional operation of the

device at these or any other conditions beyond those indicated under

Table 13 is not implied. Exposure to absolute-maximum-rated conditions

for extended periods may affect device reliability.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

16

Freescale Semiconductor

Electrical Characteristics

Table 11. Absolute Maximum Ratings

Symbol

Parameter Description

Peripheral Core Supply Voltage

Min

Max

Unit

VCC

VDDGP

–0.3

–0.5

—

1.35

1.15

V

ARM Core Supply Voltage

2

Supply Voltage (UHVIO, I C)

Supplies denoted as I/O Supply

VBUS

3.6

2

Supply Voltage (except UHVIO, I C)

USB VBUS

3.3

5.25

1

Input/Output Voltage Range

ESD Damage Immunity:

V /V

–0.5

OVDD + 0.3

in out

V

esd

Human Body Model (HBM)

Charge Device Model (CDM)

—

2000

500

o

Storage Temperature Range

Junction Temperature

T

–40

—

125

C

STORAGE

2

o

T

125

C

J

1

The term OVDD in this section refers to the associated supply rail of an input or output. The association is described in

Table 128. The maximum range can be superseded by the DC tables.

2

o

During the life of the device, T must be limited to a cumulative of 2% of the time over 105 C.

J

Table 12 provides the thermal resistance data.

Table 12. Thermal Resistance Data

Rating

Junction to Case , 19 x 19 mm package

Board

Symbol

Value

Unit

1

—

R

6

°C/W

θJC

1

Rjc-x per JEDEC 51-12: The junction-to-case thermal resistance. The “x” indicates the case surface where T

is measured

case

and through which 100% of the junction power is forced to flow due to the cold plate heat sink fixture placed either at the top (T)

or bottom (B) of the package, with no board attached to the package.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

17

Electrical Characteristics

Table 13 shows the i.MX51 operating ranges.

Table 13. i.MX51A Operating Ranges

1

2

1

Symbol

Parameter

ARM core supply voltage

⁰< f_ARM≤ 600 MHz

Minimum

Nominal

Maximum

Unit

VDDGP

MCIMX51xA products

0.95

1.0

0.95

1.225

1.1

V

ARM core supply voltage

Stop mode

0.9

1.05

V

VCC

Peripheral supply voltage High Performance

Mode (HPM) The clock frequencies are derived

from AXI and AHB buses using 133 or 166 MHz

(as needed). The DDR clock rate is 200 MHz.

Note: For detailed information about the use of

133 or 166 MHz clocks, see i.MX51 Multimedia

Applications Processor Reference Manual

(MCIMX51RM).

1.175

1.275

MCIMX51xA products

Peripheral supply voltage—Stop mode

Memory arrays voltage—Run Mode

Memory arrays voltage—Stop Mode

PLL Digital supplies

0.9

1.15

0.9

0.95

1.20

0.95

1.2

1.275

1.35

V

VDDA

VDD_DIG_PLL_A

VDD_DIG_PLL_B

1.15

VDD_ANA_PLL_A

VDD_ANA_PLL_B

PLL Analog supplies

1.75

1.65

1.8

1.95

3.1

V

NVCC_EMI

NVCC_PER5

NVCC_PER10

NVCC_PER11

NVCC_PER12

NVCC_PER13

NVCC_PER14

GPIO EMI Supply and additional digital power

supplies.

1.875 or

2.775

3

NVCC_IPUx

GPIO IPU Supply and additional digital power

supplies.

1.65

1.875 or

2.775

3.1

V

NVCC_PER3

NVCC_PER8

NVCC_PER9

NVCC_EMI_DRAM

DDR and Fuse Read Supply

Fusebox Program Supply (Write Only)

Ultra High voltage I/O (UHVIO) supplies

UHVIO_L

1.65

3.0

1.8

—

1.95

3.3

V

4

VDD_FUSE

5

NVCC_NANDF_x

—

NVCC_PER15

NVCC_PER17

1.65

2.5

1.875

2.775

3.3

1.95

3.1

UHVIO_H

UHVIO_UH

3.0

3.6

NVCC_USBPHY

NVCC_OSC

USB_PHY analog supply, oscillator analog

supply

2.25

2.5

2.75

V

6

TVDAC_DHVDD,

NVCC_TV_BACK,

AHVDDRGB

TVE-to-DAC level shifter supply, cable detector

supply, analog power supply to RGB channel

2.69

2.75

2.91

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

18

Freescale Semiconductor

Electrical Characteristics

Table 13. i.MX51A Operating Ranges (continued)

1

2

1

Symbol

Parameter

Minimum

Nominal

Maximum

Unit

NVCC_HS4_1

NVCC_HS4_2

NVCC_HS6

HS-GPIO additional digital power supplies

1.65

—

3.1

V

NVCC_HS10

2

7

NVCC_I2C

I C and HS-I C I/O Supply

1.65

2.7

1.875

3.0

1.95

3.3

V

NVCC_SRTC_

POW

SRTC Core and I/O Supply (LVIO)

USB PHY I/O analog supply

1.1

1.2

1.3

VDDA33

VBUS

3.0

—

3.3

—

3.6

—

V

See Table 11 and Table 126 for details. This is

not a power supply.

—

1

2

3

4

5

Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design

must allow for supply tolerances and system voltage drops.

The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than 50 mV. Use of supplies with a

tighter tolerance allows reduction of the setpoint with commensurate power savings.

The NVCC_IPUx rails are isolated from one another. This allows the connection of different supply voltages for each one. For

example, NVCC_IPU2 can operate at 1.8 V while NVCC_IPU4 operates at 3.0 V.

In Read mode, Freescale recommends VDD_FUSE be floated or grounded. Tying VDD_FUSE to a positive supply

(3.0 V–3.3 V) increases the possibility of inadvertently blowing fuses and is not recommended.

The NAND Flash supplies are composed of three groups: A, B, and C. Each group can be powered with a different supply

voltage. For example, NVCC_NANDF_A = 1.8 V, NVCC_NANDF_B = 3.0 V, NVCC_NANDF_C = 2.7 V.

6

7

The analog supplies should be isolated in the application design. Use of series inductors is recommended.

2

Operation of the HS-I C and I C is not guaranteed when operated between the supply voltages of 1.95 to 2.7 V.

Table 14. Interface Frequency

Parameter Description

Symbol

Min

Max

Unit

JTAG: TCK Operating Frequency

CKIL: Operating Frequency

CKIH: Operating Frequency

f

See Table 99, "JTAG Timing," on page 130

MHz

kHz

tck

f

See Table 74, "FPM Specifications," on page 80

ckil

f

See Table 47, "CAMP Electrical Parameters (CKIH1,

CKIH2)," on page 46

MHz

ckih

XTAL Oscillator

f

22

27

MHz

xtal

4.1.1

Supply Current

Table 15 shows the fuse supply current.

1

Table 15. Fuse Supply Current

Description

Symbol

Min

Typ

Max

Unit

2

eFuse Program Current.

I

—

60

120

mA

program

Current required to program one eFuse bit: The associated

VDD_FUSE supply per Table 13.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

19

Electrical Characteristics

1

The read current of approximately 5 mA is derived from the DDR supply (NVCC_EMI_DRAM).

2

The current I

is only required during program time.

program

Table 16 shows the current core consumption (not including I/O) of the i.MX51.

Table 16. i.MX51 Stop Mode Current and Power Consumption

Mode

Condition

Supply

Nominal

Unit

Stop Mode

• External reference clocks

gated

• Power gating for ARM and

processing units

• Stop mode voltage

VDDGP = 0.95 V, VCC = 0.95 V, VDDA = 0.95 V

VDDGP

VCC

0.18

0.35

0.15

0.012

0.66

mA

ARM CORE in SRPG mode

L1 and L2 caches power gated

IPU in S&RPG mode

VDDA

NVCC_OSC

Total

VPU and GPU in PG mode

All PLLs off, all CCM-generated clocks off

CKIL input on with 32 kHz signal present

All modules disabled

mW

USBPHY PLL off

External (MHz) crystal and on-chip oscillator

powered down (SBYOS bit asserted)

No external resistive loads that cause current flow

Standby voltage allowed (VSTBY bit is asserted)

TA = 25 °C

Stop Mode

• External reference clocks

gated

• Power gating for ARM and

processing units

• HPM voltage

VDDGP = 1.0 V, VCC = 1.225 V, VDDA = 1.2 V

ARM CORE in SRPG mode

L1 and L2 caches power gated

IPU in S&RPG mode

VDDGP

VCC

0.24

0.45

0.2

mA

VDDA

VPU and GPU in PG mode

NVCC_OSC

Total

0.012

1.09

All PLLs off, all CCM-generated clocks off

CKIL input on with 32 kHz signal present

All modules disabled.

mW

USBPHY PLL off

External (MHz) crystal and on-chip oscillator

powered down (SBYOS bit asserted)

No external resistive loads that cause current flow

TA = 25°C

VDDGP

VCC

0.24

0.45

0.2

mA

Stop Mode

• External reference clocks

enabled

• Power gating for ARM and

processing units

• HPM voltage

VDDGP = 1.0 V, VCC = 1.225 V, VDDA = 1.20 V

ARM CORE in SRPG mode

L1 and L2 caches power gated

IPU in S&RPG mode

VDDA

NVCC_OSC

Total

1.5

VPU and GPU in PG mode

4.8

mW

All PLLs off, all CCM-generated clocks off

CKIL input on with 32 kHz signal present

All modules disabled

USBPHY PLL off

External (MHz) crystal and on-chip oscillator pow-

ered and generating reference clock

No external resistive loads that cause current flow

TA = 25 °C

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

20

Freescale Semiconductor

Electrical Characteristics

Table 16. i.MX51 Stop Mode Current and Power Consumption (continued)

Mode

Condition

Supply

Nominal

Unit

Stop Mode

• External reference clocks

enabled

• No power gating for ARM and

processing units

• HPM voltage

VDDGP

VCC

50

2

mA

VDDGP = 1.0 V, VCC = 1.225 V, VDDA = 1.2 V

All PLLs off, all CCM-generated clocks off

CKIL input on with 32 kHz signal present

All modules disabled

VDDA

1.15

1.5

63

USBPHY PLL off

NVCC_OSC

Total

External (MHz) crystal and on-chip oscillator

powered and generating reference clock

No external resistive loads that cause current flow

TA = 25 °C

mW

4.1.2

USB PHY Current Consumption

Table 17 shows the USB PHY current consumption.

Table 17. USB PHY Current Consumption

Parameter

Conditions Typical @ 25 °C

Max

Unit

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

5.5

7

6

8

Full Speed

Analog Supply

VDDA33 (3.3 V)

mA

5

6

High Speed

Full Speed

High Speed

Full Speed

5

6

6.5

12

21

6

7

Analog Supply

NVCC_USBPHY (2.5 V)

13

22

7

6

7

Digital Supply

VCC (1.2 V)

mA

6

7

High Speed

Suspend

6

7

VDDA33 + NVCC_USBPHY + VCC

50

100

μA

4.2

Supply Power-Up/Power-Down Requirements and Restrictions

The system design must comply with the power-up and power-down sequence guidelines as described in

this section to guarantee reliable operation of the device. Any deviation from these sequences may result

in the following situations:

•

Excessive current during power-up phase

Prevention of the device from booting

Irreversible damage to the i.MX51A processor (worst-case scenario)

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

21

Electrical Characteristics

4.2.1

Power-Up Sequence

Figure 2 shows the power-up sequence.

NVCC_SRTC_POW

4

VCC

VDDGP

1

NVCC_HS4_1

NVCC_HS4_2

NVCC_HS6

AHVDDRGB

NVCC_TV_BACK

TVDAC_DHVDD

VDD_DIG_PLL_A/B

VDD_ANA_PLL_A/B

NVCC_OSC

NVCC_EMI_DRAM

VDDA

VDD_FUSE

NVCC_HS10

2

NVCC_PERx

NVCC_NANDF_x

NVCC_PER15

NVCC_PER17

NVCC_EMI

NVCC_IPU

NVCC_I2C

NVCC_USBPHY

VDDA33

1. VDD_FUSE should only be powered when writing.

2. NVCC_PERx refers to NVCC_PER 3, 5, 8, 9, 10, 11, 12, 13, 14.

3. No power-up sequence dependencies exist between the supplies shown in the block diagram shaded in gray.

4. There is no requirement for VDDGP to be preceded by any other power supply other than NVCC_SRTC_POW.

5. If all of the UHVIO supplies (NVCC_NANDFx, NVCC_PER15 and NVCC_PER17) are less than 2.75 V then there is no

requirement on the power up sequence order between NVCC_EMI_DRAM and the UHVIO supplies. However, if the voltage

is 2.75 V and above, then NVCC_EMI_DRAM needs to power up before the UHVIO supplies as shown here.

Figure 2. Power-Up Sequence

NOTE

The POR_B input must be immediately asserted at power-up and remain

asserted until after the last power rail is at its working voltage.

For more information on power up, see i.MX51 Power-Up Sequence

(AN4053).

4.3

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

•

General Purpose I/O and High-Speed General Purpose I/O (GPIO/HSGPIO)

Double Data Rate 2 (DDR2)

Low Voltage I/O (LVIO)

Ultra High Voltage I/O (UHVIO)

2

High-Speed I C and I C

Enhanced Secure Digital Host Controller (eSDHC)

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

22

Freescale Semiconductor

Electrical Characteristics

NOTE

The term OVDD in this section refers to the associated supply rail of an

input or output. The association is shown in Table 128.

4.3.1

GPIO/HSGPIO DC Parameters

The parameters in Table 18 are guaranteed per the operating ranges in Table 13, unless otherwise noted.

Table 18. GPIO/HSGPIO DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

High-level output voltage

Low-level output voltage

High-level output current

Voh

Vol

Ioh

Iout = -1 mA

Iout = 1mA

OVDD –0.15

—

OVDD + 0.3

V

0.15

—

^{Vout = 0.8}×OVDD

Low drive

–1.9

–3.7

–5.2

–6.6

Medium drive

High drive

Max drive

mA

Low-level output current

Iol

^{Vout = 0.2}×OVDD

Low drive

—

1.9

3.7

5.2

6.6

Medium drive

High drive

Max drive

1

High-Level DC input voltage

Low-Level DC input voltage¹

Input Hysteresis

VIH

VIL

—

^0.7× OVDD

—

OVDD

0.3×OVDD

—

V

0

VHYS

OVDD = 1.875

OVDD = 2.775

0.25

0.34

0.45

2

Schmitt trigger VT+^1,

VT+

VT-

Iin

—

0.5OVDD

—

V

Schmitt trigger VT-^{1, 2}

—

0.5 × OVDD

V

3

Input current (no pull-up/down)

Input current (22 kΩ Pull-up)

Input current (47 kΩ Pull-up)

Input current (100 kΩ Pull-up)

Input current (100 kΩ Pull-down)

Keeper Circuit Resistance

Vin = OVDD or 0

Vin = 0

See Note

—

Iin

161

76

μA

kΩ

Iin

Vin = 0

Iin

Vin = 0

36

Iin

Vin = OVDD

36

—

OVDD = 1.875V

OVDD = 2.775V

—

22

17

—

1

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.

2

3

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

I/O leakage currents are listed in Table 25.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

23

Electrical Characteristics

4.3.2

DDR2 I/O DC Parameters

The parameters in Table 19 are guaranteed per the operating ranges in Table 13, unless otherwise noted.

Table 19. DDR2 I/O DC Electrical Parameters

Parameters

High-level output voltage

Symbol

Test Conditions

Min

Max

Unit

Voh

Vol

Ioh

—

OVDD – 0.28

—

0.28

—

V

Low-level output voltage

—

Output minimum Source Current

OVDD = 1.7 V

Vout = 1.42 V

–13.4

mA

Output min Sink Current

Iol

OVDD = 1.7 V

Vout = 0.28 V

13.4

—

mA

DC input Logic High

VIH

VIL

Vin

—

OVDD/2 + 0.125

OVDD + 0.3

OVDD/2 – 0.125

OVDD + 0.3

V

DC input Logic Low

–0.3

0.25

Input voltage range of each differential input

V

Differential input voltage required for switching Vid

OVDD + 0.6

V

Termination Voltage

Vtt

Iin

Vtt tracking OVDD/2 OVDD/2 – 0.04 OVDD/2 + 0.04

V

1

Input current (no pull-up/down)

VI = 0

—

See Note

—

VI = OVDD

1

I/O leakage currents are listed in Table 25.

4.3.3

Low Voltage I/O (LVIO) DC Parameters

The parameters in Table 20 are guaranteed per the operating ranges in Table 13, unless otherwise noted.

Table 20. LVIO DC Electrical Characteristics

DC Electrical Characteristics

Symbol

Test Conditions

Min

Typ

Max

Unit

High-level output voltage

Low-level output voltage

High-level output current

Voh

Vol

I

Iout = –1 mA

Iout = 1 mA

OVDD – 0.15

—

0.15

—

V

Vout = 0.8 × OVDD

Low Drive

–2.1

–4.2

–6.3

–8.4

Ioh

Medium Drive

High Drive

Max Drive

mA

Low-level output current

I

Vout = 0.2 × OVDD

Low Drive

—

2.1

4.2

6.3

8.4

Iol

Medium Drive

High Drive

Max Drive

1

High-Level DC input voltage

VIH

VIL

—

0.7 × OVDD

—

OVDD

0.3 × OVDD

—

V

1

Low-Level DC input voltage

0

Input Hysteresis

VHYS

OVDD = 1.875

OVDD = 2.775

0.35

0.62

1.27

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

24

Freescale Semiconductor

Electrical Characteristics

Table 20. LVIO DC Electrical Characteristics (continued)

DC Electrical Characteristics

Symbol

Test Conditions

Min

Typ

Max

Unit

1, 2

Schmitt trigger VT+

VT+

VT–

Iin

—

0.5 × OVDD

—

V

1, 2

Schmitt trigger VT–

—

0.5 × OVDD

V

3

Input current (no pull-up/down)

Input current (22 kΩ Pull-up)

Input current (47 kΩ Pull-up)

Input current (100 kΩ Pull-up)

Input current (100 kΩ Pull-down)

Keeper Circuit Resistance

VI = 0 or OVDD

VI = 0

See Note

—

Iin

161

76

μA

kΩ

Iin

VI = 0

Iin

VI = 0

36

Iin

VI = OVDD

36

—

OVDD = 1.875 V

OVDD = 2.775 V

—

22

17

—

1

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.

2

3

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

I/O leakage currents are listed in Table 25.

4.3.4

Ultra-High Voltage I/O (UHVIO) DC Parameters

The parameters in Table 21 are guaranteed per the operating ranges in Table 13, unless otherwise noted.

Table 21. UHVIO DC Electrical Characteristics

DC Electrical Characteristics

High-level output voltage

Symbol

Test Conditions

Min

Typ

Max

Unit

Voh

Vol

Iout = –1mA

Iout = 1mA

OVDD–0.15

—

0.15

—

V

Low-level output voltage

High-level output current, low voltage mode

Vout = 0.8 × OVDD

Low Drive

Ioh_lv

Ioh_hv

Iol_lv

–2.2

–4.4

–6.6

Medium Drive

High Drive

mA

High-level output current, high voltage mode

Low-level output current, low voltage mode

Low-level output current, high voltage mode

Vout = 0.8 × OVDD

Low Drive

—

–5.1

–10.2

–15.3

Medium Drive

High Drive

Vout = 0.2 × OVDD

Low Drive

2.2

4.4

6.6

Medium Drive

High Drive

Vout = 0.2 × OVDD

Low Drive

Iol_hv

5.1

10.2

15.3

Medium Drive

High Drive

1 2

High-Level DC input voltage ,

VIH

VIL

—

0.7 × OVDD

—

OVDD

V

2,3

Low-Level DC input voltage

0

0.3 × OVDD

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

25

Electrical Characteristics

Table 21. UHVIO DC Electrical Characteristics (continued)

DC Electrical Characteristics

Symbol

Test Conditions

Min

Typ

Max

Unit

Input Hysteresis

VHYS

Low voltage mode

High voltage mode

0.38

0.95

—

0.43

1.33

V

2,3

2,4

Schmitt trigger VT+

Schmitt trigger VT–

VT+

VT–

Iin

—

0.5OVDD

—

V

—

0.5 × OVDD

4

Input current (no pull-up/down)

Vin = 0

See Note

—

Vin = OVDD

Input current (22 kΩ Pull-up)

Input current (75 kΩ Pull-up)

Input current (100 kΩ Pull-up)

Input current (360 kΩ Pull-down)

Keeper Circuit Resistance

Iin

—

Vin = 0

—

17

202

61

μA

kΩ

Vin = 0

47

Vin = OVDD

NA

5.7

—

1

To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.

2

Overshoot and undershoot conditions (transitions above OVDD and below OVSS) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be

controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.

Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

3

4

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

I/O leakage currents are listed in Table 25.

The UHVIO type of I/O cells have to be configured properly according to their supply voltage level, in

order to prevent permanent damage to them and in order to not degrade their timing performance.

The HVE control bit of the I/O cell (in IOMUX control registers) should be set to 1 for Low voltage

operation and to 0 for High voltage operation.

The HVE bit should be set as follows:

•

HVE = 0: High output voltage mode (3.0V to 3.6V)

HVE = 1: Low output voltage mode (1.65V to 3.1V)

This is related to power domains, such as NVCC_NANDF, NVCC_PER15, and NVCC_PER17.

If HVE bit is not set properly when high voltage level is applied for long durations, it may cause permanent

damage over a period of time, causing reduced timing performance of the pad. Similarly, not setting HVE

bit properly for low voltage will degrade pad timing performance.

The below discussion clarifies concerns about boot-up period.

The HVE bit is set, by default, to 1 for low voltage operation. As a result, there might be a short period

conflict between the HVE bit value and the applied voltage. This conflict is acceptable under the following

conditions:

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

26

Freescale Semiconductor

Electrical Characteristics

•

The UHVIO pads receive supply voltage up to 3.3V (3.6V max); however, the pads do not toggle

during the boot-up sequence (using another interface as a boot code source), for boot-up period of

about 22 msec.

The UHVIO pads receive up to 3.15V (3.3V max) and are used for accessing the boot code, for

boot-up period of about 11 msec.

In any case, it is recommended to try to minimize the duration of this period and reduce the amount of

toggling on the pads as much as possible. For this, it is recommended to add proper HVE bit programming

to the DCD boot-up tables. DCD is a table located in the start of the image that can hold up to 60

address/values. ROM code reads addresses and writes values to it. This space should be sufficient to

reprogram the NAND Flash pads for HVE bits.

4.3.5

I²C I/O DC Parameters

NOTE

See the errata for HS-I2C in i.MX51 Chip Errata document. The two

2

standard I C modules have no errata.

The DC Electrical Characteristics listed in Table 22 are guaranteed using operating ranges per Table 13,

unless otherwise noted.

2

Table 22. I C Standard/Fast/High-Speed Mode Electrical Parameters for Low/Medium Drive Strength

Parameter

Symbol Test Conditions

Min

Typ

Max

Unit

Low-level output voltage

Vol

VIH

VIL

Iol = 3 mA

—

0.4

OVDD

V

1

High-Level DC input voltage

—

0.7 × OVDD

1

Low-Level DC input voltage

Input Hysteresis

—

0

0.3 × OVDD

—

V

VHYS

VT+

VT–

Iin

—

0.25

V

1,2

Schmitt trigger VT+

—

0.5 × OVDD

—

V

1,2

Schmitt trigger VT–

—

0.5 × OVDD

V

3

I/O leakage current (no pull-up)

VI = OVDD or 0

See Note

—

1

To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current

DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.

2

3

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

I/O leakage currents are listed in Table 25.

4.3.6

USBOTG Electrical DC Parameters

This section describes the electrical DC parameters of USBOTG.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

27

Electrical Characteristics

4.3.7

USB Port Electrical DC Characteristics

Table 23 and Table 24 list the electrical DC characteristics.

Table 23. USBOTG Interface Electrical Specification

Parameter

Symbol

Signals

Min

Max

Unit

Test Conditions

Input High Voltage

VIH

USB_VPOUT

USB_VMOUT

USB_XRXD,

USB_VPIN,

USB_VMIN

VDD x 0.7

VDD

V

—

Input low Voltage

VIL

USB_VPOUT

USB_VMOUT

USB_XRXD,

USB_VPIN,

USB_VMIN

0

VDD × 0.3

V

—

Output High Voltage

Output Low Voltage

VOH

VOL

USB_VPOUT

USB_VMOUT

USB_TXENB

VDD – 0.43

—

V

7 mA Drv

at IOH = 5 mA

USB_VPOUT

USB_VMOUT

USB_TXENB

0.43

7 mA Drv

at IOH = 5 mA

Table 24. USB Interface Electrical Specification

Parameter

Symbol

VIH

Signals

Min

Max

Unit

Test Conditions

Input High Voltage

USB_DAT_VP

USB_SE0_VM

USB_RCV,

USB_VP1,

USB_VM1

VDD x 0.7

VDD

V

—

Input Low Voltage

VIL

USB_DAT_VP

USB_SE0_VM

USB_RCV,

0

VDD x 0.3

—

USB_VP1,

USB_VM1

Output High Voltage

Output Low Voltage

VOH

VOL

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

VDD –0.43

—

V

7 mA Drv

at Iout = 5 mA

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

0.43

7 mA Drv

at Iout = 5 mA

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

28

Freescale Semiconductor

Electrical Characteristics

Table 25 shows the I/O leakage currents that are based on the operating ranges in Table 13 and the

operating temperatures in Table 1.

.

Table 25. I/O Leakage Current

Contact Group

Supply Rail

Test Condition

Min

Typ

Max

Unit

NANDF

NVCC_NANDF

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

—

1

μA

EIM

NVCC_EMI

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

—

1

2.5

1.5

1

μA

DRAM

NVCC_DRAM

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

CSI1, CSI2, DISP1_Data[5:0] NVCC_HSx

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

2

I C1

NVCC_I2C

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

DI1_DAT[23:6],

DISPB_SER_x, DI_GPx

NVCC_IPU

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

2

CKIL, PMIC_x

NVCC_SRTC_POW

NVCC_OSC

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

1

EXTAL, XTAL

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

170

2

ID, GPANAIO

NVCC_USBPHY

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

DISP2_DAT[0:15]

SD1, SD2

NVCC_IPU,

NVCC_HS

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

NVCC_PER15,

NVCC_PER17

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

10

2

Peripherals except SD1, SD2

NVCC_PERx

V[I/O] = GND or Positive

Supply Rail, I/O = High Z

4.4

Output Buffer Impedance Characteristics

This section defines the I/O Impedance parameters of the i.MX51A processor.

4.4.1

LVIO I/O Output Buffer Impedance

Table 26 shows the LVIO I/O output buffer impedance.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

29

Electrical Characteristics

Parameter Symbol

Table 26. LVIO I/O Output Buffer Impedance

Typical

Conditions

Min

Max

Unit

OVDD 2.775 V OVDD 1.875 V

OutputDriver

Impedance

Rpu

Rpd

Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

Max Drive Strength, Ztl = 37.5 Ω

80

40

27

20

104

52

35

150

75

51

250

125

83

Ω

26

38

62

OutputDriver

Impedance

Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

Max Drive Strength, Ztl = 37.5 Ω

64

32

21

16

88

44

30

22

134

66

44

243

122

81

Ω

34

61

4.4.2

DDR2 Output Buffer Impedance

Table 27 shows the DDR2 output buffer impedance.

Table 27. DDR2 I/O Output Buffer Impedance HVE = 0

Best Case

T = –40 °C

Typical

T = 25 °C

Worst Case

T = 105 °C

j

OVDD = 1.95 V OVDD = 1.8 V OVDD = 1.6 V

Parameter

Symbol

Test Conditions

VCC = 1.3 V

VCC = 1.2 V

VCC = 1.1 V Unit

s0–s5

000000

101010

111111

Output Driver

Impedance

Rpu

Rpd

Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

Max Drive Strength

185

92.5

61.7

26.5

140

70

47

111.4

55.7

37.2

15.4

Ω

19.5

Output Driver

Impedance

Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

Max Drive Strength

190.3

95.1

63.4

27.6

145.4

72.7

48.5

19.9

120.6

60.3

40.2

16.9

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

30

Freescale Semiconductor

Electrical Characteristics

4.4.3

UHVIO Output Buffer Impedance

Table 28 shows the UHVIO output buffer impedance.

Table 28. UHVIO Output Buffer Impedance

Min

Typ

Max

Parameter Symbol

Test Conditions

Unit

OVDD OVDD OVDD

1.95 V 3.0 V 1.875 V 3.3 V

1.65 V 3.6 V

Output Driver

Impedance

Rpu

Rpd

Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

98

49

32

114

57

38

124

62

41

135

67

45

198

99

66

206

103

69

Ω

Output Driver

Impedance

Low Drive Strength, Ztl =1 50 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

97

49

32

118

59

40

126

63

42

154

77

51

179

89

60

217

109

72

NOTE

Output driver impedance is measured with long transmission line of

impedance Ztl attached to I/O pad and incident wave launched into

transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines

specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 3).

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

31

Electrical Characteristics

OVDD

PMOS (Rpu)

Ztl Ω, L = 20 inches

ipp_do

pad

predriver

Cload = 1p

NMOS (Rpd)

OVSS

U,(V)

VDD

(do)

Vin

t,(ns)

0

U,(V)

Vout (pad)

OVDD

Vref2

Vref1

Vref

t,(ns)

0

Vovdd – Vref1

Vref1

Rpu =

× Ztl

Vref2

Rpd =

Vovdd – Vref2

Figure 3. Impedance Matching Load for Measurement

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

32

Freescale Semiconductor

Electrical Characteristics

4.5

I/O AC Parameters

The load circuit and output transition time waveforms are shown in Figure 4 and Figure 5. AC electrical

characteristics for slow and fast I/O are presented in the Table 29 and Table 30, respectively.

From Output

Under Test

Test Point

CL

CL includes package, probe and fixture capacitance

Figure 4. Load Circuit for Output

NVCC

0V

80%

20%

80%

20%

Output (at I/O)

tf

tr

Figure 5. Output Transition Time Waveform

4.5.1

Slow I/O AC Parameters

Table 29 shows the slow I/O AC parameters.

Table 29. Slow I/O AC Parameters

Parameter

Symbol Test Condition Min Rise/Fall Typ Max Rise/Fall

Unit

Output Pad Transition Times (Max Drive)

tr, tf

tps

15 pF

35 pF

—

1.98/1.52

3.08/2.69

ns

Output Pad Transition Times (High Drive)

Output Pad Transition Times (Medium Drive)

Output Pad Transition Times (Low Drive)

Output Pad Slew Rate (Max Drive)

15 pF

35 pF

2.31/1.838

3.8/2.4

ns

15 pF

35 pF

2.92/2.43

5.37/4.99

15 pF

35 pF

4.93/4.53

10.55/9.79

ns

15 pF

35 pF

0.5/0.65

0.32/0.37

—

V/ns

Output Pad Slew Rate (High Drive)

Output Pad Slew Rate (Medium Drive)

Output Pad Slew Rate (Low Drive)

tps

15 pF

35 pF

0.43/0.54

0.26/0.41

tps

15 pF

35 pF

0.34/0.41

0.18/0.2

tps

15 pF

35 pF

0.20/0.22

0.09/0.1

Output Pad di/dt (Max Drive)

Output Pad di/dt (High Drive)

Output Pad di/dt (Medium drive)

tdit

—

30

23

15

mA/ns

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

33

Electrical Characteristics

Table 29. Slow I/O AC Parameters (continued)

Parameter

Symbol Test Condition Min Rise/Fall Typ Max Rise/Fall

Unit

Output Pad di/dt (Low drive)

tdit

—

7

mA/ns

ns

1

Input Transition Times

trm

25

1

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

4.5.2

Fast I/O AC Parameters

Table 30 shows the fast I/O AC parameters.

Table 30. Fast I/O AC Parameters

Test

Condition

Parameter

Symbol

Min Rise/Fall Typ

Max Rise/Fall

Unit

Output Pad Transition Times (Max Drive)

tr, tf

15 pF

35 pF

—

1.429/1.275

2.770/2.526

ns

Output Pad Transition Times (High

Drive)

tr, tf

tps

15 pF

35 pF

1.793/1.607

3.565/3.29

ns

Output Pad Transition Times (Medium

Drive)

15 pF

35 pF

2.542/2.257

5.252/4.918

Output Pad Transition Times (Low Drive)

Output Pad Slew Rate (Max Drive)

Output Pad Slew Rate (High Drive)

Output Pad Slew Rate (Medium Drive)

Output Pad Slew Rate (Low Drive)

15 pF

35 pF

4.641/4.456

10.699/10.0

ns

15 pF

35 pF

0.69/0.78

0.36/0.39

—

V/ns

tps

15 pF

35 pF

0.55/0.62

0.28/0.30

tps

15 pF

35 pF

0.39/0.44

0.19/0.20

tps

15 pF

35 pF

0.21/0.22

0.09/0.1

Output Pad di/dt (Max Drive)

Output Pad di/dt (High Drive)

Output Pad di/dt (Medium drive)

Output Pad di/dt (Low drive)

tdit

trm

—

70

53

35

18

25

mA/ns

ns

1

Input Transition Times

1

Hysteresis mode is recommended for inputs with transition time greater than 25 ns.

4.5.3

I²C AC Parameters

NOTE

2

See the errata for HS-I C in the i.MX51 Chip Errata document. The two

standard I C modules have no errata

2

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

34

Freescale Semiconductor

Electrical Characteristics

Figure 6 depicts the load circuit for output pads for standard- and fast-mode. Figure 7 depicts the output

pad transition time definition. Figure 8 depicts load circuit with external pull-up current source for

HS-mode. Figure 9 depicts HS-mode timing definition.

From Output

Under Test

Test Point

CL

CL includes package, probe and fixture capacitance

Figure 6. Load Circuit for Standard and Fast-Mode

OVDD

0V

70%

Output

30%

tf

Figure 7. Definition of Timing for Standard and Fast-Mode

OVDD

1

3 mA

From Output

Under Test

Test Point

2

CL

Notes:

1

Load current when output is between 0.3×OVDD and 0.7×OVDD

2

CL includes package, probe, and fixture capacitance.

Figure 8. Load Circuit for HS-Mode with External Pull-Up Current Source

OVDD

70%

30%

70%

30%

Output (at pad)

0V

t_THL

and t

t

TLH

PA3Max = max of t

TLH

THL

PA4Max = max t

Figure 9. Definition of Timing for HS-Mode

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

35

Electrical Characteristics

2

The electrical characteristics for I C I/O are listed in Table 31 to Table 34. Characteristics are guaranteed

using operating ranges per Table 13, unless otherwise noted.

2

Table 31. I C Standard- and Fast-Mode Electrical Parameters

for Low/Medium Drive Strength and OVDD = 2.7 V–3.3 V

Parameter

Output fall time,

Symbol

Test Conditions

Min

Typ

Max Unit

tf

from V

to V

with C from 10 pF to 400 pF

—

52

ns

IHmin

ILmax

L

(low driver strength)

Output fall time,

tf

with C from 10 pF to 400 pF

—

28

ns

ILmax

L

(medium driver strength)

2

Table 32. I C Standard- and Fast-Mode Electrical Parameters

for Low/Medium Drive Strength and OVDD = 1.65 V–1.95 V

Parameter

Symbol

Test Conditions

Min

Typ Max Unit

Output fall time,

(low driver strength)

t

from V

to V

with C from 10 pF to 400 pF

—

70

ns

of

IHmin

ILmax

L

Output fall time,

t

with C from 10 pF to 400 pF

—

35

ns

L

(medium driver strength)

2

Table 33. I C High-Speed Mode Electrical Parameters

for Low/Medium Drive Strength and OVDD = 2.7 V–3.3 V

Parameter

Symbol

Test Conditions

Min Typ

Max

Unit

Output rise time (current-source enabled) and

fall time at SCLH

(low driver strength)

t

, t

with a 3mA external

pull-upcurrentsource

—

18/21

ns

rCL fCL

and C = 100 pF

L

Output rise time (current-source enabled) and

fall time at SCLH

t

, t

with a 3mA external

pull-upcurrentsource

9/9

ns

rCL fCL

(medium driver strength)

and C = 100 pF

L

Output fall time at SDAH

(low driver strength)

t

with C from 10 pF to

—

14

8

ns

fDA

L

100 pF

Output fall time at SDAH

(medium driver strength)

with C from 10 pF to

L

100 pF

Output fall time at SDAH

(low driver strength)

C = 400 pF

52

27

L

Output fall time at SDAH

(medium driver strength)

C = 400 pF

L

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

36

Freescale Semiconductor

Electrical Characteristics

2

Table 34. I C High-Speed Mode Electrical Parameters

for Low/Medium Drive Strength and OVDD = 1.65 V–1.95 V

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Output rise time (current-source

enabled) and fall time at SCLH

(low driver strength)

t

, t

with a 3 mA external pull-up current

—

10/74

ns

rCL fCL

source and C = 100 pF

L

Output rise time (current-source

enabled) and fall time at SCLH

(medium driver strength)

t

, t

with a 3 mA external pull-up current

—

7/14

ns

rCL fCL

source and C = 100 pF

L

Output fall time at SDAH

(low driver strength)

t

with C from 10 pF to 100 pF

0

—

17

9

ns

fDA

L

Output fall time at SDAH

(medium driver strength)

with C from 10 pF to 100 pF

L

Output fall time at SDAH

(low driver strength)

C = 400 pF

30

15

67

34

L

Output fall time at SDAH

(medium driver strength)

C = 400 pF

L

2

Table 35. Low Voltage I C I/O Parameters

Parameter

Symbol

Test Condition Min Rise/Fall

Typ

Max Rise/Fall

Unit

Output Pad di/dt (Medium drive)

Output Pad di/dt (Low drive)

tdit

trm

—

22

11

25

mA/ns

ns

1

Input Transition Times

1

Hysteresis mode is recommended for inputs with transition time greater than 25 ns

2

Table 36. High Voltage I C I/O Parameters

Parameter

Symbol Test Condition Min Rise/Fall Typ

Max Rise/Fall

Unit

Output Pad Transition Times (Medium Drive)

tr, tf

tps

15 pF

35 pF

—

3/3

6/5

ns

Output Pad Transition Times (Low Drive)

Output Pad Slew Rate (Medium Drive)

Output Pad Slew Rate (Low Drive)

15 pF

35 pF

5/5

9/9

ns

15 pF

35 pF

0/0

—

V/ns

tps

15 pF

35 pF

0/0

—

Output Pad di/dt (Medium drive)

Output Pad di/dt (Low drive)

tdit

trm

—

36

16

25

mA/ns

ns

1

Input Transition Times

1

Hysteresis mode is recommended for inputs with transition time > 25 ns

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

37

Electrical Characteristics

4.5.4

AC Electrical Characteristics for DDR2

The load circuit for output pads, the output pad transition time waveform and the output pad propagation

and transition time waveform are below.

Figure 10 shows the output pad transition time waveform.

Figure 10. Output Pad Transition Time Waveform

Figure 11 shows the output pad propagation and transition time waveform.

Figure 11. Output Pad Propagation and Transition Time Waveform

AC electrical characteristics in DDR2 mode for fast mode and for ovdd = 1.65 – 1.95 V, ipp_hve = 0 are

placed in Table 37.

Table 37. AC Electrical Characteristics of DDR2 IO Pads for Fast mode and

for ovdd=1.65–1.95 V (ipp_hve=0)

Test

Min

Max

rise/fall

Parameter

Symbol

Typ

Units

Condition rise/fall

1

Output Pad Transition Times

tpr

15pF

35pF

0.57/0.57

1.29/1.29

0.45/0.44

0.97/0.94

0.45/0.45

0.82/0.85

ns

1

Output Pad Propagation Delay, 50%-50%

tpo

tps

15pF

35pF

0.98/0.96

1.47/1.50

1.27/1.19

1.63/1.57

1.89/1.72

2.20/2.07

ns

1

Output Pad Slew Rate

15pF

35pF

2.05/2.05

0.91/0.91

2.40/2.45

1.11/1.15

2.20/2.20

1.21/1.16

V/ns

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

38

Freescale Semiconductor

Electrical Characteristics

Table 37. AC Electrical Characteristics of DDR2 IO Pads for Fast mode and

for ovdd=1.65–1.95 V (ipp_hve=0) (continued)

Test

Min

Max

rise/fall

Parameter

Symbol

Typ

Units

Condition rise/fall

1

Output Pad di/dt

di/dt

trfi

—

390

201

99

mA/ns

ns

2

Input Pad Transition Times

1.2 pF

0.09/0.09 0.132/0.128 0.212/0.213

Input Pad Propagation Delay without Hysteresis

(CMOS input), 50%-50%

tpi

0.45/0.93

0.55/0.55

0.38/0.38

—

0.6/0.58

0.71/0.7

0.58/0.61

—

0.9/0.88

1.03/0.98

1.014/1.07

5

ns

2

Input Pad Propagation Delay with Hysteresis

(CMOS input), 50%-50%

tpi

1.2 pF

—

ns

2

Input Pad Propagation Delay (DDR input),

2

50%-50%

3

Maximum Input Transition Times

trm

1

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,

tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5 = 101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, –40 °C and s0-s5=000000.

2

3

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO

1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR2 mode for Slow mode and for ovdd=1.65 – 1.95 V, ipp_hve = 0 are

placed in Table 38:

Table 38. AC Electrical Characteristics of DDR2 IO Pads for Slow Mode and

for ovdd=1.65–1.95 V (ipp_hve=0)

Test

Min

Max

rise/fall

Parameter

Symbol

Typ

Units

Condition rise/fall

1

Output Pad Transition Times

tpr

15pF

35pF

0.75/0.76

1.39/1.40

0.70/0.74

1.18/1.21

1.06/1.00

1.49/1.47

ns

1

Output Pad Propagation Delay, 50%-50%

tpo

tps

15pF

35pF

1.50/1.55

2.05/2.16

1.90/1.95

2.36/2.48

3.23/3.10

3.82/3.75

ns

1

Output Pad Slew Rate

15pF

35pF

1.56/1.54

0.84/0.84

1.54/1.46

0.92/0.89

0.93/0.99

0.66/0.67

V/ns

1

Output Pad di/dt

di/dt

trfi

—

82

40

19

mA/ns

ns

2

Input Pad Transition Times

1.2 pF

0.09/0.09 0.132/0.128 0.212/0.213

Input Pad Propagation Delay without Hysteresis

(CMOS input), 50%-50%

tpi

0.45/0.93

0.55/0.55

0.38/0.38

—

0.6/0.58

0.71/0.7

0.58/0.61

—

0.9/0.88

1.03/0.98

1.014/1.07

5

ns

2

Input Pad Propagation Delay with Hysteresis

(CMOS input), 50%-50%

tpi

1.2 pF

—

ns

2

Input Pad Propagation Delay (DDR input),

2

50%-50%

3

Maximum Input Transition Times

trm

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

39

Electrical Characteristics

1

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,

tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5 = 101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, –40 °C and s0-s5 = 000000.

2

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO

1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.

3

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR mobile for Fast mode and ovdd=1.65 – 1.95 V, ipp_hve=0 are placed

in Table 39.

Table 39. AC Electrical Characteristics of DDR mobile IO Pads for Fast Mode and

ovdd=1.65–1.95 V (ipp_hve=0)

Test

Min

Max

rise/fall

Parameter

Symbol

Typ

Units

Condition rise/fall

1

Output Pad Transition Times (High Drive)

tpr

15pF

35pF

1.35/1.31

2.99/2.94

1.02/1.03

2.28/2.29

0.89/0.89

1.85/1.94

ns

1

Output Pad Transition Times (Medium Drive)

tpr

15pF

35pF

2.00/1.99

4.55/4.44

1.56/1.53

3.38/3.45

1.28/1.32

2.79/2.85

ns

1

Output Pad Transition Times (Low Drive)

15pF

35pF

4.08/3.92

8.93/8.95

3.11/3.06

6.84/6.81

2.50/2.61

5.56/5.76

1

Output Pad Propagation Delay (High Drive)

tpo

tps

15pF

35pF

1.54/1.52

2.69/2.75

1.73/1.62

2.59/2.55

2.36/2.09

3.04/2.86

ns

1

Output Pad Propagation Delay (Medium Drive)

15pF

35pF

2.00/2.02

3.75/3.86

2.08/2.00

3.38/3.39

2.64/2.40

3.65/3.56

ns

1

Output Pad Propagation Delay (Low Drive)

15pF

35pF

3.43/3.52

6.92/7.20

3.13/3.13

5.72/5.94

3.47/3.34

5.49/5.65

ns

1

Output Pad Slew Rate (High Drive)

15pF

35pF

0.87/0.89

0.39/0.40

1.06/1.05

0.47/0.47

1.11/1.11

0.54/0.51

V/ns

1

Output Pad Slew Rate (Medium Drive)

15pF

35pF

0.58/0.59

0.26/0.26

0.69/0.71

0.32/0.31

0.77/0.75

0.35/0.35

1

Output Pad Slew Rate (Low Drive)

15pF

35pF

0.29/0.30

0.13/0.13

0.35/0.35

0.16/0.16

0.40/0.38

0.18/0.17

1

Output Pad di/dt (High Drive)

di/dt

trfi

—

185

124

62

91

61

30

46

31

16

mA/ns

ns

1

Output Pad di/dt (Medium drive)

1

Output Pad di/dt (Low drive)

—

2

Input Pad Transition Times

1.2 pF

0.09/0.09 0.132/0.128 0.212/0.213

Input Pad Propagation Delay without Hysteresis

tpi

0.45/0.93

0.55/0.55

0.38/0.38

—

0.6/0.58

0.71/0.7

0.58/0.61

—

0.9/0.88

1.03/0.98

1.014/1.07

5

ns

2

(CMOS input), 50%-50%

Input Pad Propagation Delay with Hysteresis

tpi

1.2 pF

—

ns

—

ns

2

(CMOS input), 50%-50%

Input Pad Propagation Delay (DDR input),

2

50%-50%

3

Maximum Input Transition Times

trm

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

40

Freescale Semiconductor

Electrical Characteristics

1

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,

tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5 = 101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, –40 °C and s0-s5 = 000000.

2

3

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO

1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR mobile for Slow mode and ovdd=1.65-1.95V, ipp_hve=0 are placed

in Table 40.

Table 40. AC Electrical Characteristics of DDR mobile IO Pads for Slow Mode

ovdd=1.65–1.95 V (ipp_hve=0)

Test

Min

Max

rise/fall

Parameter

Symbol

Typ

Units

Condition rise/fall

1

Output Pad Transition Times (High Drive)

tpr

15pF

35pF

1.42/1.43

3.03/2.92

1.20/1.27

2.39/2.38

1.43/1.49

2.35/2.46

ns

1

Output Pad Transition Times (Medium Drive)

tpr

15pF

35pF

2.04/2.04

4.51/4.49

1.68/1.74

3.47/3.50

1.82/1.91

3.16/3.30

ns

1

Output Pad Transition Times (Low Drive)

15pF

35pF

4.08/3.93

9.06/8.93

3.16/3.19

6.92/6.93

2.90/3.01

5.74/5.96

1

Output Pad Propagation Delay (High Drive)

tpo

tps

15pF

35pF

2.00/2.17

3.15/3.42

2.33/2.50

3.24/3.52

3.70/3.70

4.63/4.75

ns

1

Output Pad Propagation Delay (Medium Drive)

15pF

35pF

2.47/2.68

4.2/4.53

2.72/2.92

4.01/4.37

4.10/4.16

5.33/5.55

ns

1

Output Pad Propagation Delay (Low Drive)

15pF

35pF

3.87/4.18

7.32/7.86

3.78/4.10

6.35/6.90

5.13/5.30

7.25/7.73

ns

1

Output Pad Slew Rate (High Drive)

15pF

35pF

0.82/0.82

0.39/0.40

0.90/0.85

0.45/0.49

0.69/0.66

0.42/0.40

V/ns

1

Output Pad Slew Rate (Medium Drive)

15pF

35pF

0.57/0.57

0.26/0.26

0.70/0.62

0.31/0.31

0.54/0.52

0.31/0.30

1

Output Pad Slew Rate (Low Drive)

15pF

35pF

0.29/0.30

0.13/0.13

0.34/0.34

0.16/0.16

0.34/0.33

0.17/0.17

1

Output Pad di/dt (High Drive)

di/dt

trfi

47

27

12

14

9

6

3

mA/ns

ns

1

Output Pad di/dt (Medium drive)

—

1

Output Pad di/dt (Low drive)

—

5

2

Input Pad Transition Times

1.2 pF

0.09/0.09 0.132/0.128 0.212/0.213

Input Pad Propagation Delay without Hysteresis

tpi

0.45/0.93

0.55/0.55

0.38/0.38

—

0.6/0.58

0.71/0.7

0.58/0.61

—

0.9/0.88

1.03/0.98

1.014/1.07

5

ns

2

(CMOS input), 50%-50%

Input Pad Propagation Delay with Hysteresis

tpi

1.2 pF

—

ns

—

ns

2

(CMOS input), 50%-50%

Input Pad Propagation Delay (DDR input),

2

50%-50%

3

Maximum Input Transition Times

trm

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

41

Electrical Characteristics

1

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,

tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, –40 °C and s0-s5=000000.

2

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO

1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.

3

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR2 mode for Fast mode and for ovdd=1.65–1.95V, ipp_hve=0 are

placed in Table 41.

Table 41. AC Electrical Characteristics of DDR2_clk IO Pads for Fast mode and

for ovdd=1.65–1.95 V

Test

Min

Max

rise/fall

Parameter

Symbol

Typ

Units

Condition rise/fall

1

Output Pad Transition Times

tpr

15pF

35pF

0.58/0.57

1.29/1.28

0.45/0.44

0.97/0.93

0.45/0.45

0.82/0.85

ns

1

Output Pad Propagation Delay, 50%-50%

tpo

tps

15pF

35pF

1.05/1.03

1.54/1.56

1.40/1.31

1.75/1.69

2.12/1.96

2.43/2.31

ns

1

Output Pad Slew Rate

15pF

35pF

2.02/2.05

0.91/0.91

2.40/2.45

1.11/1.16

2.20/2.20

1.21/1.16

V/ns

1

Output Pad di/dt

di/dt

trfi

—

390

201

99

mA/ns

ns

2

Input Pad Transition Times

1.2 pF

0.09/0.09 0.132/0.128 0.212/0.213

Input Pad Propagation Delay (DDR input),

tpi

0.3/0.36

0.5/0.52

0.82/0.94

ns

2

50%-50%

3

Maximum Input Transition Times

trm

—

5

ns

1

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,

tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, -40 °C and s0-s5=000000.

2

3

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO 1.8

V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and -40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR2 mode for Slow mode and for ovdd=1.65-1.95V, ipp_hve=0 are

placed in Table 42.

Table 42. AC Electrical Characteristics of DDR2_clk IO Pads for Slow mode and for

ovdd=1.65 – 1.95 V (ipp_hve=0)

Test

Min

Max

rise/fall

Parameter

Symbol

Typ

Units

Condition rise/fall

1

Output Pad Transition Times

tpr

15pF

35pF

0.74/0.76

1.40/1.39

0.69/0.72

1.18/1.20

1.04/1.01

1.48/1.47

ns

1

Output Pad Propagation Delay, 50%-50%

tpo

tps

15pF

35pF

1.56/1.61

2.12/2.22

2.02/2.08

2.49/2.61

3.45/3.33

4.05/3.98

ns

1

Output Pad Slew Rate

15pF

35pF

1.58/1.54

0.84/0.84

1.57/1.50

0.92/0.90

0.95/0.98

0.67/0.67

V/ns

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Electrical Characteristics

Table 42. AC Electrical Characteristics of DDR2_clk IO Pads for Slow mode and for

ovdd=1.65 – 1.95 V (ipp_hve=0) (continued)

Test

Min

Max

rise/fall

Parameter

Symbol

Typ

Units

Condition rise/fall

1

Output Pad di/dt

di/dt

trfi

—

82

40

19

mA/ns

ns

2

Input Pad Transition Times

1.2 pF

0.09/0.09 0.132/0.128 0.212/0.213

Input Pad Propagation Delay (DDR input),

tpi

0.3/0.36

0.5/0.52

0.82/0.94

ns

2

50%-50%

3

Maximum Input Transition Times

trm

—

5

ns

1

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,

tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, -40 °C and s0-s5=000000.

2

3

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO 1.8

V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and -40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR mobile for Fast mode and ovdd=1.65-1.95V, ipp_hve=0 are placed in

Table 43.

Table 43. AC Electrical Characteristics of DDR_clk mobile IO Pads for Fast mode

and ovdd=1.65 – 1.95 V (ipp_hve=0)

Test

Min

Max

rise/fall

Parameter

Symbol

Typ

Units

Condition rise/fall

1

Output Pad Transition Times (High Drive)

tpr

15pF

35pF

1.35/1.32

3.01/2.96

1.03/1.03

2.29/2.30

0.89/0.89

1.84/1.92

ns

1

Output Pad Transition Times (Medium Drive)

tpr

15pF

35pF

1.98/1.98

4.52/4.38

1.55/1.54

3.46/3.45

1.29/1.30

2.80/2.88

ns

1

Output Pad Transition Times (Low Drive)

15pF

35pF

3.99/3.94

8.93/8.86

3.10/3.04

6.77/6.85

2.50/2.57

5.40/5.68

1

Output Pad Propagation Delay (High Drive)

tpo

tps

15pF

35pF

1.60/1.58

2.74/2.81

1.85/1.74

2.71/2.67

2.58/2.31

3.26/3.08

ns

1

Output Pad Propagation Delay (Medium Drive)

15pF

35pF

2.07/2.08

3.79/3.92

2.19/2.12

3.46/3.51

2.86/2.62

3.87/3.77

ns

1

Output Pad Propagation Delay (Low Drive)

15pF

35pF

3.47/3.57

6.94/7.26

3.23/3.25

5.84/6.06

3.69/3.55

5.73/5.87

ns

1

Output Pad Slew Rate (High Drive)

15pF

35pF

0.87/0.89

0.39/0.40

1.05/1.05

0.47/0.47

1.11/1.11

0.54/0.52

V/ns

1

Output Pad Slew Rate (Medium Drive)

15pF

35pF

0.59/0.59

0.26/0.27

0.70/0.70

0.31/0.31

0.77/0.76

0.35/0.34

1

Output Pad Slew Rate (Low Drive)

15pF

35pF

0.29/0.30

0.13/0.13

0.35/0.36

0.16/0.16

0.40/0.39

0.18/0.17

1

Output Pad di/dt (High Drive)

di/dt

—

185

124

91

61

46

31

mA/ns

1

Output Pad di/dt (Medium drive)

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43

Electrical Characteristics

Table 43. AC Electrical Characteristics of DDR_clk mobile IO Pads for Fast mode

and ovdd=1.65 – 1.95 V (ipp_hve=0) (continued)

Test

Min

Max

rise/fall

Parameter

Symbol

Typ

Units

Condition rise/fall

1

Output Pad di/dt (Low drive)

di/dt

trfi

—

62

30

16

mA/ns

ns

2

Input Pad Transition Times

1.2 pF

0.09/0.09 0.132/0.128 0.212/0.213

Input Pad Propagation Delay (DDR input),

tpi

0.3/0.36

0.5/0.52

0.82/0.94

—

2

50%-50%

3

Maximum Input Transition Times

trm

—

5

ns

1

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,

tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, –40 °C and s0-s5=000000.

2

3

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO

1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

AC electrical characteristics in DDR mobile for Slow mode and ovdd=1.65-1.95V, ipp_hve=0 are placed

in Table 44.

Table 44. AC Electrical Characteristics of DDR mobile IO Pads for Slow Mode and

ovdd=1.65 – 1.95 V (ipp_hve=0)

Test

Min

Max

rise/fall

Parameter

Symbol

Typ

Units

Condition rise/fall

1

Output Pad Transition Times (High Drive)

tpr

15pF

35pF

1.42/1.42

3.01/2.96

1.20/1.27

2.38/2.40

1.43/1.49

2.37/2.44

ns

1

Output Pad Transition Times (Medium Drive)

tpr

15pF

35pF

2.05/2.04

4.50/4.42

1.67/1.71

3.48/3.52

1.82/1.87

3.16/3.28

ns

1

Output Pad Transition Times (Low Drive)

15pF

35pF

4.06/3.98

8.94/8.86

3.15/3.17

6.92/6.93

2.92/ 3.02

5.69/5.96

1

Output Pad Propagation Delay (High Drive)

tpo

tps

15pF

35pF

2.07/2.23

3.21/3.48

2.46/2.62

3.35/3.63

3.92/3.93

4.84/4.97

ns

1

Output Pad Propagation Delay (Medium Drive)

15pF

35pF

2.53/2.74

4.26/4.58

2.83/3.04

4.12/4.49

4.32/4.35

5.55/5.76

ns

1

Output Pad Propagation Delay (Low Drive)

15pF

35pF

3.93/4.23

7.38/7.91

3.89/4.21

6.43/7.01

5.37/5.51

7.45/7.94

ns

1

Output Pad Slew Rate (High Drive)

15pF

35pF

0.82/0.82

0.39/0.40

0.90/0.85

0.45/0.45

0.69/0.66

0.42/0.41

V/ns

1

Output Pad Slew Rate (Medium Drive)

15pF

35pF

0.57/0.57

0.26/0.26

0.65/0.63

0.31/0.31

0.54/0.53

0.31/0.30

1

Output Pad Slew Rate (Low Drive)

15pF

35pF

0.29/0.29

0.13/0.13

0.34/0.34

0.16/0.16

0.34/0.33

0.17/0.17

1

Output Pad di/dt (High Drive)

di/dt

—

47

27

14

9

6

mA/ns

1

Output Pad di/dt (Medium drive)

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Freescale Semiconductor

Electrical Characteristics

Table 44. AC Electrical Characteristics of DDR mobile IO Pads for Slow Mode and

ovdd=1.65 – 1.95 V (ipp_hve=0) (continued)

Test

Min

Max

rise/fall

Parameter

Symbol

Typ

Units

Condition rise/fall

1

Output Pad di/dt (Low drive)

di/dt

trfi

—

12

5

3

mA/ns

ns

2

Input Pad Transition Times

1.2 pF

0.09/0.09 0.132/0.128 0.212/0.213

Input Pad Propagation Delay (DDR input),

tpi

0.3/0.36

0.5/0.52

0.82/0.94

—

2

50%-50%

3

Maximum Input Transition Times

trm

—

5

ns

1

Max condition for tpr, tpo, tps and didt: wcs model, 1.1 V, IO 1.65 V, 105 °C and s0-s5=111111. Typ condition for tpr, tpo,

tps and didt: typ model, 1.2 V, IO 1.8 V, 25 °C and s0-s5=101010. Min condition for tpr, tpo, tps and didt: bcs model, 1.3 V,

IO 1.95 V, –40 °C and s0-s5=000000.

2

3

Max condition for trfi and tpi: wcs model, 1.1 V, IO 1.65 V and 105 °C. Typ condition for trfi and tpi: typ model, 1.2 V, IO

1.8 V and 25 °C. Min condition for trfi and tpi: bcs model, 1.3 V, IO 1.95 V and –40 °C.

Hysteresis mode is recommended for input with transition time greater than 25 ns.

4.6

Module Timing

This section contains the timing and electrical parameters for the modules in the i.MX51 processor.

4.6.1

Reset Timings Parameters

Figure 12 shows the reset timing and Table 45 lists the timing parameters.

RESET_IN

(Input)

CC1

Figure 12. Reset Timing Diagram

Table 45. Reset Timing Parameters

ID

Parameter

Min

Max

Unit

CC1

Duration of RESET_IN to be qualified as valid (input slope = 5 ns)

50

—

ns

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

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45

Electrical Characteristics

4.6.2

WDOG Reset Timing Parameters

Figure 13 shows the WDOG reset timing and Table 46 lists the timing parameters.

WATCHDOG_RST

(Input)

CC5

Figure 13. WATCHDOG_RST Timing Diagram

Table 46. WATCHDOG_RST Timing Parameters

ID

Parameter

Min

Max

Unit

CC5

Duration of WATCHDOG_RESET Assertion

1

—

T

CKIL

NOTE

is one period or approximately 30 μs.

CKIL is approximately 32 kHz. T

CKIL

4.6.3

AUDMUX Timing Parameters

The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between

internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is hence governed by the SSI module.

4.6.4

Clock Amplifier Parameters (CKIH1, CKIH2)

The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave

or sinusoidal frequency source. No external series capacitors are required. Table 47 shows the CAMP

electrical parameters.

Table 47. CAMP Electrical Parameters (CKIH1, CKIH2)

Parameter

Input frequency

Min

Typ

Max

Unit

8.0

—

50

40.0

0.3

MHz

V

VIL (for square wave input)

VIH (for square wave input)

Sinusoidal input amplitude

Output duty cycle

0

NVCC_PER3 - 0.25

NVCC_PER3

VDD

V

0.4

45

Vp-p

%

55

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Electrical Characteristics

4.6.5

DPLL Electrical Parameters

Table 48 shows the DPLL electrical parameters.

Table 48. DPLL Electrical Parameters

Parameter

Test Conditions/Remarks

Min

Typ

Max

Unit

1

Reference clock frequency range

—

10

—

100

40

MHz

Reference clock frequency range after

pre-divider

Output clock frequency range (dpdck_2)

—

300

—

50

—

1025

16

MHz

—

2

Pre-division factor

—

1

Multiplication factor integer part

—

5

15

—

3

Multiplication factor numerator

Should be less than denominator

–67108862

67108862

67108863

51.5

—

2

Multiplication factor denominator

—

1

—

Output Duty Cycle

48.5

—

%

4

Frequency lock time

398

T

d

pdref

(FOL mode or non-integer MF)

Phase lock time

—

0.02

2.0

—

100

0.04

3.5

µs

5

Frequency jitter (peak value)

—

T

dck

Phase jitter (peak value)

Power dissipation

FPL mode, integer and fractional MF

ns

f

= 300 MHz @ avdd = 1.8 V,

dvdd = 1.2 V

= 650 MHz @ avdd = 1.8 V,

0.65 (avdd)

0.92 (dvdd)

1.98 (avdd)

1.8 (dvdd)

mW

dck

f

dck

dvdd = 1.2 V

1

2

Device input range cannot exceed the electrical specifications of the CAMP, see Table 47.

The values specified here are internal to DPLL. Inside the DPLL, a “1” is added to the value specified by the user.Therefore,

the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD.

3

4

5

The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15.Therefore, if the MFI value is 15, MFN value must be

zero.

T

is the time period of the reference clock after predivider.According to the specification, the maximum lock time in FOL

dpdref

mode is 398 cycles of divided reference clock when DPLL starts after full reset.

Tdck is the time period of the output clock, dpdck_2.

4.6.6

NAND Flash Controller (NFC) Parameters

This section provides the relative timing requirements among different signals of NFC at the module level

in the different operational modes.

Timing parameters in Figure 14, Figure 15, Figure 16, Figure 17, Figure 19, and Table 50 show the default

NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B. Timing

parameters in Figure 14, Figure 15, Figure 16, Figure 18, Figure 19, and Table 50 show symmetric NFC

mode using one Flash clock cycle per one access of RE_B and WE_B.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

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47

Electrical Characteristics

With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20%

of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is 20

pF (except for NF16 - 40 pF) and there is max drive strength on all contacts.

All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system

level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The

clock is derived from emi_slow_clk after single divider. Table 49 demonstrates few examples for clock

frequency settings.

Table 49. NFC Clock Settings Examples

1

emi_slow_clk (MHz)

nfc_podf (Division Factor)

enfc_clk (MHz)

T—Clock Period (ns)

133 (max value)

5 (reset value)

26.6

33.25

44.33

38

31

23

133

4

3

1

Rounded up to whole nanoseconds.

NOTE

A potential limitation for minimum clock frequency may exist for some

devices. When the clock frequency is too low the actual data bus capturing

might occur after the specified trhoh (RE_B high to output hold) period.

Setting the clock frequency above 25.6 MHz (T = 39 ns) guarantees proper

operation for devices having trhoh > 15 ns. It is also recommended to set the

NFC_FREQ_SEL Fuse accordingly to initiate the boot with 33.33 MHz

clock.

Lower frequency operation can be supported for most available devices in

the market, relying on data lines Bus-Keeper logic. This depends on device

behavior on the data bus in the time interval between data output valid to

data output high-Z state. In NAND device parameters this period is marked

between trhoh and trhz (RE_B high to output high-Z). In most devices, the

data transition from valid value to high-Z occurs without going through

other states. Setting the data bus pads to Bus-Keeper mode in the IOMUX

registers, keeps the data bus valid internally after the specified hold time,

allowing proper capturing with slower clock.

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Electrical Characteristics

NFCLE

NF2

NF1

NF3

NF4

NFCE_B

NF5

NFWE_B

NFIO[7:0]

NF8

NF9

command

Figure 14. Command Latch Cycle Timing

NF4

NF3

NFCE_B

NF10

NF11

NF5

NFWE_B

NFALE

NF7

NF6

NF8

NF9

NFIO[7:0]

NFCE_B

Address

Figure 15. Address Latch Cycle Timing

NF3

NF10

NF11

NF5

NFWE_B

NF8

NF9

NFIO[15:0]

Data to NF

Figure 16. Write Data Latch Timing

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49

Electrical Characteristics

NFCE_B

NF14

NF13

NF15

NFRE_B

NFRB_B

NF17

NF16

NF12

NFIO[15:0]

NFCE_B

Data from NF

Figure 17. Read Data Latch Timing—Asymmetric Mode

NF14

NF15

NF13

NFRE_B

NFRB_B

NF18

NF16

NF12

NFIO[15:0]

Data from NF

Figure 18. Read Data Latch Timing—Symmetric Mode

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Freescale Semiconductor

Electrical Characteristics

NF19

NFCLE

NF20

NFCE_B

NFWE_B

NF21

NF22

NFRE_B

NFRB_B

Figure 19. Other Timing Parameters

Table 50. NFC—Timing Characteristics

Asymmetric

Mode Min

Symmetric

Mode Min

ID

Parameter

NFCLE setup Time

Symbol

Max

NF1

NF2

tCLS

tCLH

tCS

2T-1

T-4.45

2T-1

T-4.45

T-1

—

NFCLE Hold Time

NFCE_B Setup Time

NFCE_B Hold Time

NFWE_B Pulse Width

NFALE Setup Time

NFALE Hold Time

Data Setup Time

NF3

—

NF4

tCH

2T-5.55

T-2.5

0.5T-5.55

0.5T-1.5

2T-2.7

T-4.45

0.5T-2.25

0.5T-5.55

T

—

NF5

tWP

tALS

tALH

tDS

—

NF6

2T-2.7

T-4.45

T-2.25

T-6.55

2T

—

NF7

—

NF8

—

NF9

Data Hold Time

tDH

—

NF10

NF11

NF12

NF13

NF14

NF15

Write Cycle Time

tWC

tWH

tRR

—

NFWE_B Hold Time

Ready to NFRE_B Low

NFRE_B Pulse Width

READ Cycle Time

NFRE_B High Hold Time

Data Setup on READ

Data Hold on READ

CLE to RE delay

T-1.25

9T

0.5T-1.25

9T

—

tRP

1.5T-2.7

2T

0.5T

—

tRC

T

—

tREH

tDSR

tDHR

tCLR

tCRE

0.5T-1.5

11.2+0.5T-Tdl

0

0.5T-1.5

—

1

2

NF16

NF17

NF18

11.2-Tdl

—

3

4

—

2Taclk+T

—

2

—

Tdl

NF19

NF20

13T

CE to RE delay

T-3.45

1.5T-3.45

—

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

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51

Electrical Characteristics

Table 50. NFC—Timing Characteristics (continued)

Asymmetric

Mode Min

Symmetric

Mode Min

ID

Parameter

Symbol

Max

NF21

WE high to RE low

WE high to busy

tWHR

tWB

14T-5.45

—

14T-5.45

—

NF22

6T

1

tDSR is calculated by the following formula:

2

Asymmetric mode: tDSR = tREpd + tDpd + ¹/₂T – Tdl

2

Symmetric mode: tDSR = tREpd + tDpd – Tdl

tREpd + tDpd = 11.2 ns (including clock skew)

where tREpd is RE propogation delay in the chip including IO pad delay, and tDpd is Data propogation delay

from IO pad to EMI including IO pad delay.

tDSR can be used to determine tREA max parameter with the following formula: tREA = 1.5T – tDSR.

2

3

Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk

period (Taclk). Default is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates

a total of 1 aclk period. Taclk is “emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz).

NF17 is defined only in asymmetric operation mode.

NF17 max value is equivalent to max tRHZ value that can be used with NFC.

Taclk is “emi_slow_clk” of the system.

4

NF18 is defined only in Symmetric operation mode.

2

tDHR (MIN) is calculated by the following formula:

Tdl – (tREpd + tDpd)

where tREpd is RE propogation delay in the chip including IO pad delay, and tDpd is Data propogation delay

from IO pad to EMI including IO pad delay.

NF18 max value is equivalent to max tRHZ value that can be used with NFC.

Taclk is “emi_slow_clk” of the system.

4.6.7

External Interface Module (WEIM)

The following sections provide information on the WEIM.

4.6.7.1 WEIM Signal Cross Reference

Table 51 is a guide to help the user identify signals in the WEIM Chapter of the i.MX51 Multimedia

Applications Processor Reference Manual (MCIMX51RM) that are the same as those mentioned in this

data sheet.

Table 51. WEIM Signal Cross Reference

Data Sheet Nomenclature,

Reference Manual

Reference Manual External Signals and Pin Multiplexing Chapter,

WEIM Chapter Nomenclature

and IOMUX Controller Chapter Nomenclature

BCLK

CSx

EIM_BCLK

EIM_CSx

EIM_RW

EIM_OE

WE_B

OE_B

BEy_B

ADV

EIM_EBx

EIM_LBA

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Table 51. WEIM Signal Cross Reference (continued)

Data Sheet Nomenclature,

Reference Manual

Reference Manual External Signals and Pin Multiplexing Chapter,

and IOMUX Controller Chapter Nomenclature

WEIM Chapter Nomenclature

ADDR

ADDR/M_DATA

DATA

EIM_A[27:16], EIM_DA[15:0]

EIM_DAx (Addr/Data muxed mode)

EIM_NFC_D (Data bus shared with NAND Flash)

EIM_Dx (dedicated data bus)

WAIT_B

EIM_WAIT

4.6.7.2

WEIM Internal Module Multiplexing

Table 52 provides WEIM internal muxing information.

384

Table 52. WEIM Interface Pinout in Various Configurations

Multiplexed

Address/Data Mode

(MUM=1)

Non Multiplexed Address/Data Mode

(MUM=0)

1

8-Bit

16-Bit

32-Bit

16-Bit

32-Bit

(DSZ=100) (DSZ=101) (DSZ=110 (DSZ=111 (DSZ=001) (DSZ=010) (DSZ=011 (DSZ=001) (DSZ=011)

)

A[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

A[27:16]

EIM_A

[27:16]

EIM_A

[27:16]

EIM_A

[27:16]

EIM_A

[27:16]

EIM_A

[27:16]

EIM_A

[27:16]

EIM_A

[27:16]

EIM_A

[27:16]

NANDF_D

[11:0]

D[7:0],

EIM_EB0

NANDF_D

[7:0]

—

NANDF_D

[7:0]

—

NANDF_D EIM_DA

[7:0] [7:0]

EIM_DA

[7:0]

D[15:8],

EIM_EB1

—

NANDF_D

[15:8]

—

NANDF_D

[15:8]

—

NANDF_D EIM_DA

EIM_DA

[15:8]

D[23:16],

EIM_EB2

—

EIM_D

[23:16]

—

EIM_D

[23:16]

EIM_D

[23:16]

—

NANDF_D

[7:0]

D[31:24],

EIM_EB3

—

EIM_D

[31:24]

—

EIM_D

[31:24]

EIM_D

[31:24]

—

NANDF_D

[15:8]

1

This mode is not supported due to erratum ENGcm11244.

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Electrical Characteristics

4.6.7.3

General WEIM Timing-Synchronous Mode

Figure 20, Figure 21, and Table 53 specify the timings related to the WEIM module. All WEIM output

control signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising

edge according to corresponding assertion/negation control fields.

,

WE2

...

WE3

BCLK

WE1

WE4

WE6

WE5

WE7

WE9

Address

CSx_B

WE8

WE10

WE12

WE_B

OE_B

BEy_B

WE11

WE13

WE15

WE17

WE14

WE16

ADV_B

Output Data

Figure 20. WEIM Outputs Timing Diagram

BCLK

WE18

WE20

Input Data

WE19

WE21

WAIT_B

Figure 21. WEIM Inputs Timing Diagram

1

Table 53. WEIM Bus Timing Parameters

BCD = 0 BCD = 1

Max Min Max

BCD = 2

Max

BCD = 3

Max

ID

Parameter

Min

2

WE1 BCLK Cycle time

t

2 x t

3 x t

4 x t

WE2 BCLK Low Level

Width

0.4 x t

0.8 x t

1.2 x t

1.6 x t

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BCD = 3

1

Table 53. WEIM Bus Timing Parameters (continued)

BCD = 0 BCD = 1 BCD = 2

Min Max

0.8 x t

ID

Parameter

Min

Max

Min

1.2 x t

Max

Min

Max

WE3 BCLK High Level

Width

0.4 x t

1.6 x t

WE4 Clock rise to address

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t -

1.25

-1.5 x t

+1.75

-2 x t -

1.25

-2 x t +

1.75

3

valid

WE5 Clock rise to address

invalid

0.5 x t - 0.5 x t + 1.75 t - 1.25

1.25

t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t - 2 x t + 1.75

1.25

WE6 Clock rise to CSx_B

valid

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t - -1.5 x t +

-2 x t -

1.25

-2 x t +

1.75

1.25

1.75

WE7 Clock rise to CSx_B

invalid

0.5 x t - 0.5 x t + 1.75 t - 1.25

1.25

t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t - 2 x t + 1.75

1.25

WE8 Clock rise to WE_B

Valid

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t - -1.5 x t +

-2 x t -

1.25

-2 x t +

1.75

1.25

1.75

WE9 Clock rise to WE_B

Invalid

0.5 x t - 0.5 x t + 1.75 t - 1.25

1.25

t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t - 2 x t + 1.75

1.25

WE10 Clock rise to OE_B

Valid

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t - -1.5 x t +

-2 x t -

1.25

-2 x t +

1.75

1.25

1.75

WE11 Clock rise to OE_B

Invalid

0.5 x t - 0.5 x t + 1.75 t - 1.25

1.25

t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t - 2 x t + 1.75

1.25

WE12 Clock rise to BEy_B

Valid

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t - -1.5 x t +

-2 x t -

1.25

-2 x t +

1.75

1.25

1.75

WE13 Clock rise to BEy_B

Invalid

0.5 x t - 0.5 x t + 1.75 t - 1.25

1.25

t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t - 2 x t + 1.75

1.25

WE14 Clock rise to ADV_B

Valid

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t - -1.5 x t +

-2 x t -

1.25

-2 x t +

1.75

1.25

1.75

WE15 Clock rise to ADV_B

Invalid

0.5 x t - 0.5 x t + 1.75 t - 1.25

1.25

t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t - 2 x t + 1.75

1.25

WE16 Clock rise to Output

Data Valid

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t - -1.5 x t +

-2 x t -

1.25

-2 x t +

1.75

1.25

1.75

WE17 Clock rise to Output

Data Invalid

0.5 x t - 0.5 x t + 1.75 t - 1.25

1.25

t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t - 2 x t + 1.75

1.25

WE18 Input Data setup time

to Clock rise

2 ns

—

4 ns

2 ns

4 ns

2 ns

—

WE19 Input Data hold time

from Clock rise

WE20 WAIT_B setup time to

Clock rise

WE21 WAIT_B hold time

from Clock rise

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55

Electrical Characteristics

1

t is the maximal WEIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum

allowed BCLK frequency is 104 MHz. As a result, if BCD = 0, axi_clk must be ≤ 104 MHz. If BCD = 1, then 133 MHz is allowed

for axi_clk, resulting in a BCLK of 66.5 MHz. When the clock branch to WEIM is decreased to 104 MHz, other busses are

impacted which are clocked from this source. See the CCM chapter of the i.MX51 Reference Manual for a detailed clock tree

description.

2

BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined

as 50% as signal value.

3

For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.

4.6.7.4

Examples of WEIM Synchronous Accesses

Figure 22 to Figure 25 provide few examples of basic WEIM accesses to external memory devices with

the timing parameters mentioned previously for specific control parameters settings.

BCLK

WE4

WE6

WE5

WE7

ADDR

CSx_B

WE_B

ADV_B

OE_B

Address v1

Last Valid Address

WE14

WE10

WE12

WE15

WE18

WE11

WE13

BEy_B

DATA

D(v1)

WE19

Figure 22. Synchronous Memory Read Access, WSC=1

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Electrical Characteristics

BCLK

ADDR

WE5

WE4

Last Valid Address

Address V1

WE7

WE6

WE8

CSx_B

WE_B

ADV_B

OE_B

WE9

WE14

WE15

WE13

WE12

WE16

BEy_B

DATA

WE17

D(V1)

Figure 23. Synchronous Memory, Write Access, WSC=1, WBEA=0, and WADVN=0

BCLK

WE16

WE17

WE5

WE4

ADDR/

M_DATA

Write Data

Address V1

Valid Addr

Last

WE6

WE7

WE9

CSx_B

WE_B

WE8

WE14

WE15

ADV_B

OE_B

WE10

WE11

BEy_B

Figure 24. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6, ADVA=0, ADVN=1, and

ADH=1

NOTE

In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the

data bus.

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Electrical Characteristics

BCLK

WE4

WE5

WE19

WE18

ADDR/

M_DATA

Last Valid Addr Address V1

WE6

Data

CSx_B

WE_B

WE7

WE15

WE10

WE14

WE12

ADV_B

OE_B

WE11

WE13

BEy_B

Figure 25. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, and OEA=0

4.6.7.5

General WEIM Timing-Asynchronous Mode

Figure 26 through Figure 31, and Table 54 help to determine timing parameters relative to the chip select

(CS) state for asynchronous and DTACK WEIM accesses with corresponding WEIM bit fields and the

timing parameters mentioned above.

Asynchronous read and write access length in cycles may vary from what is shown in Figure 26 through

Figure 29 as RWSC, OEN, and CSN is configured differently. See i.MX51 reference manual for the

WEIM programming model.

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Electrical Characteristics

end of

access

start of

access

INT_CLK

CSx_B

MAXCSO

WE31

WE32

ADDR/

M_DATA

Next Address

Last Valid Address

Address V1

WE_B

WE39

WE40

WE36

WE38

ADV_B

WE35

WE37

OE_B

BEy_B

WE44

MAXCO

DATA[7:0]

D(V1)

WE43

MAXDI

Figure 26. Asynchronous Memory Read Access (RWSC = 5)

end of

access

start of

access

INT_CLK

CSx_B

MAXCSO

MAXDI

WE31

D(V1)

Addr. V1

WE32A

ADDR/

M_DATA

WE44

WE_B

WE40A

WE39

WE35A

WE37

ADV_B

WE36

WE38

OE_B

BEy_B

MAXCO

Figure 27. Asynchronous A/D Muxed Read Access (RWSC = 5)

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59

Electrical Characteristics

CSx_B

ADDR

WE31

Last Valid Address

WE32

WE34

WE40

Next Address

Address V1

WE33

WE_B

ADV_B

OE_B

WE39

WE45

WE41

WE46

BEy_B

DATA

WE42

D(V1)

Figure 28. Asynchronous Memory Write Access

CSx_B

WE41A

WE31

D(V1)

Addr. V1

WE32A

ADDR/

M_DATA

WE42

WE33

WE39

WE34

WE_B

WE40A

ADV_B

OE_B

WE45

WE46

WE42

BEy_B

Figure 29. Asynchronous A/D Muxed Write Access

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Electrical Characteristics

CSx_B

ADDR

WE31

WE32

Next Address

Last Valid Address

Address V1

WE_B

ADV_B

OE_B

WE39

WE35

WE37

WE40

WE36

WE38

BEy_B

WE44

DATA[7:0]

D(V1)

WE43

WE48

DTACK

WE47

Figure 30. DTACK Read Access (DAP=0)

CSx_B

ADDR

WE31

WE32

WE34

WE40

Next Address

Last Valid Address

Address V1

WE33

WE_B

ADV_B

OE_B

WE39

WE45

WE41

WE46

BEy_B

DATA

WE42

D(V1)

WE48

DTACK

WE47

Figure 31. DTACK Write Access (DAP=0)

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Electrical Characteristics

Table 54. WEIM Asynchronous Timing Parameters Table Relative Chip Select

Determination by

Max

Ref No.

Parameter

Synchronous measured

Min

(If 133 MHz is

supported by SOC)

Unit

12

parameters

3

WE31

WE32

CSx_B valid to Address Valid

WE4 - WE6 - CSA

—

3 - CSA

3 - CSN

ns

4

Address Invalid to CSx_B

invalid

WE7 - WE5 - CSN

5

WE32A( CSx_B valid to Address Invalid

muxed

A/D

t + WE4 - WE7 + (ADVN +

-3 + (ADVN +

ADVA + 1 - CSA)

—

ns

3

ADVA + 1 - CSA )

WE33

WE34

WE35

CSx_B Valid to WE_B Valid

WE8 - WE6 + (WEA - CSA)

—

3 + (WEA - CSA)

3 - (WEN_CSN)

3 + (OEA - CSA)

3 + (OEA +

ns

WE_B Invalid to CSx_B Invalid WE7 - WE9 + (WEN - CSN)

—

CSx_B Valid to OE_B Valid

WE10 - WE6 + (OEA - CSA)

WE10 - WE6 + (OEA + RADVN

WE35A

(muxed

A/D)

-3 + (OEA +

+ RADVA + ADH + 1 - CSA) RADVN+RADVA+ RADVN+RADVA+AD

ADH+1-CSA)

H+1-CSA)

WE36

WE37

OE_B Invalid to CSx_B Invalid WE7 - WE11 + (OEN - CSN)

—

3 - (OEN - CSN)

ns

6

CSx_B Valid to BEy_B Valid

(Read access)

WE12 - WE6 + (RBEA - CSA)

3 + (RBEA - CSA)

7

WE38 BEy_B Invalid to CSx_B Invalid WE7 - WE13 + (RBEN - CSN)

(Read access)

—

3 - (RBEN - CSN)

ns

WE39

WE40

CSx_B Valid to ADV_B Valid

WE14 - WE6 + (ADVA - CSA)

WE7 - WE15 - CSN

—

3 + (ADVA - CSA)

3 - CSN

ns

ADV_B Invalid to CSx_B

Invalid (ADVL is asserted)

WE40A CSx_B Valid to ADV_B Invalid WE14 - WE6 + (ADVN + ADVA

-3 + (ADVN +

ADVA + 1 - CSA)

3 + (ADVN + ADVA +

1 - CSA)

ns

(muxed

A/D)

+ 1 - CSA)

WE41

CSx_B Valid to Output Data

Valid

WE16 - WE6 - WCSA

—

3 - WCSA

ns

WE41A

(muxed

A/D)

CSx_B Valid to Output Data

Valid

WE16 - WE6 + (WADVN +

WADVA + ADH + 1 - WCSA)

3 + (WADVN +

WADVA + ADH + 1 -

WCSA)

WE42

Output Data Invalid to CSx_B

Invalid

WE17 - WE7 - CSN

10

—

3 - CSN

ns

MAXCO Output max. delay from internal

driving ADDR/control FFs to

chip outputs.

—

MAXCS Output max. delay from CSx

10

5

—

O

internal driving FFs to CSx out.

MAXDI

DATA MAXIMUM delay from

chip input data to its internal FF

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Table 54. WEIM Asynchronous Timing Parameters Table Relative Chip Select

Determination by

Max

Ref No.

Parameter

Synchronous measured

Min

(If 133 MHz is

supported by SOC)

Unit

12

parameters

-

WE43

Input Data Valid to CSx_B

Invalid

MAXCO - MAXCSO + MAXDI

MAXCO

—

ns

MAXCSO +

MAXDI

WE44

WE45

CSx_B Invalid to Input Data

invalid

0

—

ns

—

CSx_B Valid to BEy_B Valid WE12 - WE6 + (WBEA - CSA)

(Write access)

—

3 + (WBEA - CSA)

-3 + (WBEN - CSN)

—

WE46 BEy_B Invalid to CSx_B Invalid WE7 - WE13 + (WBEN - CSN)

(Write access)

MAXDTI DTACK MAXIMUM delay from

chip dtack input to its internal

FF + 2 cycles for

synchronization

WE47

Dtack Active to CSx_B Invalid MAXCO - MAXCSO + MAXDTI

MAXCO -

MAXCSO +

MAXDTI

—

ns

WE48

CSx_B Invalid to Dtack invalid

0

1

2

3

4

5

6

7

Parameters WE4... WE21 value see column BCD = 0 in Table 53.

All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units.

CS Assertion. This bit field determines when CS signal is asserted during read/write cycles.

CS Negation. This bit field determines when CS signal is negated during read/write cycles.

t is axi_clk cycle time.

BE Assertion. This bit field determines when BE signal is asserted during read cycles.

BE Negation. This bit field determines when BE signal is negated during read cycles.

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Electrical Characteristics

4.6.8

SDRAM Controller Timing Parameters

Mobile DDR SDRAM Timing Parameters

4.6.8.1

Figure 32 shows the basic timing parameters for mobile DDR (mDDR) SDRAM. The timing parameters

for this diagram is shown in Table 55.

DD1

SDCLK

DD2

DD4

DD3

CS

RAS

CAS

DD5

DD4

DD6

DD5

WE

DD7

ADDR

ROW/BA

COL/BA

Figure 32. mDDR SDRAM Basic Timing Parameters

Table 55. mDDR SDRAM Timing Parameter Table

200 MHz

166 MHz

133 MHz

ID

Parameter

Symbol

Unit

Min

Max

Min

Max

Min

Max

DD1

DD2

DD3

DD4

DD5

DD6

DD7

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

tCH

tCL

tCK

0.45

5

0.55

—

0.45

6

0.55

—

0.45

7.5

0.55

—

tCK

ns

1

CS, RAS, CAS, CKE, WE setup time

CS, RAS, CAS, CKE, WE hold time

Address output setup time

tIS

0.9

—

1.1

—

1.3

—

1

tIH

—

1.3

—

1

tIS

—

1.3

—

1

Address output hold time

tIH

—

1.3

—

1

This parameter is affected by pad timing. if the slew rate is < 1 V/ns, 0.2 ns should be added to the value. For cmos65 pads

this is true for medium and low drive strengths.

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Electrical Characteristics

Figure 33 shows the timing diagram for mDDR SDRAM write cycle. The timing parameters for this

diagram is shown in Table 56.

SDCLK

SDCLK_B

DD19

DD22

DD17

DD20

DD21

DD23

DD18

DQS (output)

DQ (output)

DD18

Data

DD17

Data

DM

Data

DM

Data

DM

Data

DM

DD17

DM

DQM (output)

DD17

DD18

Figure 33. mDDR SDRAM Write cycle Timing Diagram

1

Table 56. mDDR SDRAM Write Cycle Parameter Table

2

200 MHz

166 MHz

133 MHz

ID

Parameter

Symbol

Unit

Min

Max

Min

Max

Min

Max

3

DD17

DD18

DD19

DQ and DQM setup time to DQS

DQ and DQM hold time to DQS

tDS

0.48

0.2

—

0.6

0.2

—

0.8

0.2

—

ns

1

tDH

Write cycle DQS falling edge to

SDCLK output setup time

tDSS

tDSH

tCK

DD20

DD21

Write cycle DQS falling edge to

SDCLK output hold time

0.2

—

0.2

—

0.2

—

tCK

Write command to first DQS latching

transition

tDQSS

0.75

1.25

0.75

1.25

0.75

1.25

DD22

DD23

DQS high level width

DQS low level width

tDQSH

tDQSL

0.4

0.6

0.4

0.6

0.4

0.6

tCK

1

2

Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for

address and controls.

SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal

value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK

and SDCLK (inverted clock).

3

This parameter is affected by pad timing. If the slew rate is < 1 V/ns, 0.1 ns should be increased to this value.

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65

Electrical Characteristics

Figure 34 shows the timing diagram for mDDR SDRAM DQ versus DQS and SDCLK read cycle. The

timing parameters for this diagram is shown in Table 57.

SDCLK

SDCLK_B

DD26

DQS (input)

DD25

DD24

Data

DQ (input)

Figure 34. mDDR SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram

1

Table 57. mDDR SDRAM Read Cycle Parameter Table

2

200 MHz

166 MHz 133 MHz

ID

PARAMETER

Symbol

Unit

Min Max Min Max Min Max

DD24 DQS - DQ Skew (defines the Data valid window in read cycles

related to DQS)

tDQSQ

—

0.4

—

0.75

—

0.85 ns

DD25 DQS DQ in HOLD time from DQS

tQH

1.75

2

—

5

2.05

2

—

2.6

2

—

ns

DD26 DQS output access time from SDCLK posedge

tDQSCK

5.5

6.5 ns

1

Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for

address and controls

2

SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal

value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK

and SDCLK (inverted clock)

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Electrical Characteristics

4.6.9

DDR2 SDRAM Specific Parameters

Figure 35 shows the timing parameters for DDR2. The timing parameters for this diagram appear in

Table 58.

DDR1

SDCLK

DDR2

DDR4

DDR3

CS

DDR5

RAS

DDR5

DDR4

CAS

DDR4

DDR5

WE

ODT/CKE

DDR4

DDR6

DDR7

ADDR

ROW/BA

COL/BA

Figure 35. DDR2 SDRAM Basic Timing Parameters

Table 58. DDR2 SDRAM Timing Parameter Table

SDCLK = 200 MHz

ID

Parameter

Symbol

Unit

Min

Max

DDR1

DDR2

DDR3

DDR4

DDR5

SDRAM clock high-level width

tCH

tCL

tCK

0.45

5

0.55

—

tCK

ns

SDRAM clock low-level width

SDRAM clock cycle time

1

CS, RAS, CAS, CKE, WE, ODT setup time

CS, RAS, CAS, CKE, WE, ODT hold time

tIS

1.5

1.7

—

ns

1

tIH

—

ns

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Electrical Characteristics

Table 58. DDR2 SDRAM Timing Parameter Table (continued)

SDCLK = 200 MHz

ID

Parameter

Symbol

Unit

Min

Max

1

DDR6

DDR7

Address output setup time

Address output hold time

tIS

1.7

1.5

—

ns

1

tIH

1

These values are for command/address slew rates of 1 V/ns and SDCLK / SDCLK_B differential slew rate of 2 V/ns. For

different values use the settings shown in Table 59.

NOTE

Measurements are taken from Vref to Vref (cross-point to cross-point), but

JEDEC timings for single-ended signals are defined from Vref to Vil(ac)

max or to Vih(ac) min.

Table 59. Derating Values for DDR2-400 (SDCLK = 200 MHz)

1,2

SDCLK Differential Slew Rates

Command /

Address

Slew Rate

(V/ns)

2.0 V/ns

1.5 V/ns

1.0 V/ns

Unit

ΔtlS

ΔtlH

ΔtlS

ΔtlH

ΔtlS

ΔtlH

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.25

0.2

0.15

0.1

+187

+179

+167

+150

+125

+83

+94

+89

+217

+209

+197

+180

+155

+113

+30

+124

+119

+113

+105

+75

+247

+239

+227

+210

+185

+143

+60

+154

+149

+143

+135

+105

+81

ps

+83

+75

+45

+21

+51

+0

+30

+60

–11

–14

+19

+16

+49

+46

–25

–31

+5

–1

+35

+29

–43

–54

–13

–24

+17

+6

–67

–83

–37

–53

–7

–23

–110

–175

–285

–350

–525

–800

–1450

–125

–188

–292

–375

–500

–708

–1125

–80

–95

–50

–65

–145

–255

–320

–495

–770

–1420

–158

–262

–345

–470

–678

–1095

–115

–225

–290

–465

–740

–1390

–128

–232

–315

–440

–648

–1065

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

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Electrical Characteristics

1

2

Test conditions are: Capacitance 15 pF for DDR contacts. Recommended drive strengths: Medium for SDCLK and High for

address and controls.

SDCLK and DQS related parameters are measured from the 50% point. For example, a high is defined as 50% of the signal

value and a low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of

SDCLK and SDCLK_B.

Figure 36 shows the timing diagram for DDR2 SDRM write cycle. The timing parameters for this diagram

appear in Table 60.

SDCLK

DDR20

SDCLK_B

DDR21

DDR17

DDR19

DDR22

DDR23

DDR18

DQS (output)

DQ (output)

DDR18

Data

DDR17

Data

DM

Data

DM

DQM (output)

DDR17

DDR18

Figure 36. DDR2 SDRAM Write Cycle Timing Diagram

Table 60. DDR2 SDRAM Write Cycle Parameter Table

SDCLK = 200 MHz

ID

Parameter

Symbol

Unit

Min

Max

1

DDR17 DQ & DQM setup time to DQS

tDS

tDH

0.8

—

0.3

—

ns

2

DDR18 DQ & DQM hold time to DQS

0.8

DDR19 DQS falling edge to SDCLK output setup time

DDR20 DQS falling edge SDCLK output hold time

DDR21 DQS latching rising transitions to associated clock edges

DDR22 DQS high level width

tDSS

1.6

2.4

ns

tDSH

tDQSS

tDQSH

tDQSL

ns

-0.7

0.35

ns

tCK

DDR23 DQS low level width

1

2

- In order to meet these setup/hold values, write calibration should be performed to place the DQS in the middle of DQ

window. The minimum window width is 1.6ns (DDR17+DDR18).

- From DDR controller perspective, the timing is the same for both differential and single ended mode.

- In order to meet these setup/hold values, write calibration should be performed to place the DQS in the middle of DQ

window. The minimum window width is 1.6ns (DDR17+DDR18).

- From DDR controller perspective, the timing is the same for both differential and single ended mode.

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69

Electrical Characteristics

NOTE

Measurements are taken from Vref to Vref (cross-point to cross-point), but

JEDEC timings for single-ended signals are defined from Vref to Vil(ac)

max or to Vih(ac) min.

1 2

Table 61. Derating values for DDR2 Differential DQS ,

3 4

Table 62. Derating values for DDR2 Single Ended DQS ,

1. Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for

address and controls.

2. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal

value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK

and SDCLK (inverted clock).

3. Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for

address and controls.

4. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal

value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK

and SDCLK (inverted clock).

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Electrical Characteristics

Figure 37 shows the timing diagram for DDR2 SDRM read cycle. The timing parameters for this diagram

appear in Table 63.

SDCLK

SDCLK_B

DQS (input)

DDR24

DDR25

DATA

DQ (input)

Figure 37. DDR2 SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram

Table 63. DDR2 SDRAM Read Cycle Parameter Table

SDCLK = 200 MHz

ID

Parameter

Symbol

Unit

Min

Max

1

DDR24 DQS—DQ Skew (defines the Data valid window during read cycles

related to DQS).

tDQSQ

—

0.5

ns

2

DDR25 DQ HOLD time from DQS

tQH

1.8

—

1

2

The actual timing may vary depending on read calibration settings. What is actually important for the controller is

DDR25-DDR24 which results in the minimum required DQ valid window width: 1.8ns-0.5ns = 1.3ns of minimum width.

The actual timing may vary depending on read calibration settings. What is actually important for the controller is

DDR25-DDR24 which results in the minimum required DQ valid window width: 1.8ns-0.5ns = 1.3ns of minimum width.

NOTE

It is recommended to perform read calibration process in order to achieve

the best performance.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

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Electrical Characteristics

4.7

External Peripheral Interfaces

The following sections provide information on external peripheral interfaces.

4.7.1

CSPI Timing Parameters

This section describes the timing parameters of the CSPI. The CSPI has separate timing parameters for

master and slave modes. The nomenclature used with the CSPI modules and the respective routing of

these signals is shown in Table 64.

Table 64. CSPI Nomenclature and Routing

Module

I/O Access

1

eCSPI1

eCSPI2

CSPI

CSPI1 , USBH1, and DI1 via IOMUX

NANDF and USBH1 via IOMUX

NANDF, USBH1, SD1, SD2, and GPIO via IOMUX

1

This set of BGA contacts is labeled CSPI, but is actually an eCSPI channel

4.7.1.1

CSPI Master Mode Timing

Figure 38 depicts the timing of CSPI in Master mode and Table 65 lists the CSPI Master Mode timing

characteristics.

RDY

CS10

SSx

CS5

CS6

CS2

CS1

CS3

CS4

SCLK

MOSI

MISO

CS2

CS7

CS3

CS9

CS8

Figure 38. CSPI Master Mode Timing Diagram

Table 65. CSPI Master Mode Timing Parameters

ID

Parameter

SCLK Cycle Time

Symbol

Min

Max

Unit

CS1

CS2

CS3

CS4

t

60

26

—

26

—

ns

clk

SCLK High or Low Time

t

SW

t

RISE/FALL

1

SCLK Rise or Fall

SSx pulse width

t

CSLH

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Electrical Characteristics

Table 65. CSPI Master Mode Timing Parameters (continued)

ID

Parameter

Symbol

Min

Max

Unit

CS5

SSx Lead Time (Slave Select

setup time)

t

26

—

ns

SCS

CS6

CS7

SSx Lag Time (SS hold time)

t

26

–1

—

ns

HCS

MOSI Propagation Delay

t

21

PDmosi

(C

= 20 pF)

LOAD

CS8

CS9

MISO Setup Time

MISO Hold Time

t

5

—

ns

Smiso

Hmiso

2

CS10

RDY to SSx Time

t

SDRY

1

2

See specific I/O AC parameters Section 4.5, “I/O AC Parameters”

SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

4.7.1.2

CSPI Slave Mode Timing

Figure 39 depicts the timing of CSPI in Slave mode. Table 66 lists the CSPI Slave Mode timing

characteristics.

SSx

CS5

CS6

CS2

CS1

CS4

SCLK

MISO

CS2

CS9

CS8

CS7

MOSI

Figure 39. CSPI Slave Mode Timing Diagram

Table 66. CSPI Slave Mode Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

CS1

CS2

CS4

CS5

CS6

CS7

SCLK Cycle Time

t

60

26

5

—

ns

clk

SCLK High or Low Time

SSx pulse width

t

SW

t

CSLH

SSx Lead Time (SS setup time)

SSx Lag Time (SS hold time)

MOSI Setup Time

t

SCS

HCS

t

Smosi

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73

Electrical Characteristics

Table 66. CSPI Slave Mode Timing Parameters (continued)

ID

Parameter

Symbol

Min

Max

Unit

CS8

CS9

MOSI Hold Time

MISO Propagation Delay (C

t

5

0

—

35

ns

Hmosi

= 20 pF)

t

PDmiso

LOAD

4.7.2

eCSPI Timing Parameters

This section describes the timing parameters of the eCSPI. The eCSPI has separate timing parameters for

master and slave modes. The nomenclature used with the CSPI modules and the respective routing of these

signals is shown in Table 64.

4.7.2.1

eCSPI Master Mode Timing

Figure 40 depicts the timing of eCSPI in Master mode and Table 67 lists the eCSPI Master Mode timing

characteristics.

eCSPIx_DRYN1

CS11

eCSPIx_CS_x

CS6

CS5

CS2

CS1

CS3

CS4

eCSPIx_CLK

eCSPIx_DO

eCSPIx_DI

CS2

CS7

CS9

CS8

CS3

CS10

Figure 40. eCSPI Master Mode Timing Diagram

Table 67. eCSPI Master Mode Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

CS1

eCSPIx_CLK Cycle Time–Read

eCSPIx_CLK Cycle Time–Write

t

60

15

—

ns

clk

CS2

CS3

CS4

CS5

CS6

CS7

eCSPIx_CLK High or Low Time

eCSPIx_CLK Rise or Fall

t

6

—

15

5

—

ns

SW

t

RISE/FALL

eCSPIx_CS_x pulse width

t

CSLH

eCSPIx_CS_x Lead Time (CS setup time)

eCSPIx_CS_x Lag Time (CS hold time)

eCSPIx_DO Setup Time

t

SCS

HCS

t

5

t

5

Smosi

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Electrical Characteristics

Table 67. eCSPI Master Mode Timing Parameters (continued)

ID

Parameter

eCSPIx_DO Hold Time

Symbol

Min

Max

Unit

CS8

CS9

t

5

—

ns

Hmosi

Smiso

Hmiso

eCSPIx_DI Setup Time

eCSPIx_DI Hold Time

eCSPIx_DRYN Setup Time

CS10

CS11

t

SDRY

4.7.2.2

eCSPI Slave Mode Timing

Figure 41 depicts the timing of eCSPI in Slave mode and Table 68 lists the eCSPI Slave Mode timing

characteristics.

eCSPIx_CS_x

CS6

CS5

CS2

CS1

CS3

CS4

eCSPIx_CLK

eCSPIx_DI

CS2

CS3

CS9

CS7

CS10

CS8

eCSPIx_DO

Figure 41. eCSPI Slave Mode Timing Diagram

Table 68. eCSPI Slave Mode Timing Parameters

ID

Parameter

Symbol

Min

Max

Unit

CS1

eCSPIx_CLK Cycle Time–Read

eCSPIx_CLK Cycle Time–Write

t

60

15

—

ns

clk

CS2

CS3

CS4

CS5

CS6

CS7

CS8

CS9

CS10

eCSPIx_CLK High or Low Time

eCSPIx_CLK Rise or Fall

t

6

—

15

5

—

ns

SW

t

RISE/FALL

eCSPIx_CS_x pulse width

eCSPIx_CS_x Lead Time (CS setup time)

eCSPIx_CS_x Lag Time (CS hold time)

eCSPIx_DO Setup Time

t

CSLH

t

SCS

HCS

5

t

5

Smosi

Hmosi

Smiso

Hmiso

eCSPIx_DO Hold Time

5

eCSPIx_DI Setup Time

5

eCSPIx_DI Hold Time

5

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Electrical Characteristics

4.7.3

eSDHCv2 Timing Parameters

This section describes the electrical information of the eSDHCv2.

Figure 42 depicts the timing of eSDHCv2, and Table 69 lists the eSDHCv2 timing characteristics.

SD4

SD2

SD1

SD5

MMCx_CLK

SD3

MMCx_CMD

SD6

MMCx_DAT_0

MMCx_DAT_1

output from eSDHCv2 to card

......

MMCx_DAT_7

SD7 SD8

MMCx_CMD

MMCx_DAT_0

MMCx_DAT_1

input from card to eSDHCv2

......

MMCx_DAT_3

Figure 42. eSDHCv2 Timing

Table 69. eSDHCv2 Interface Timing Specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

1

SD1 Clock Frequency (Low Speed)

f

0

400

25/50

20/52

400

—

kHz

MHz

kHz

ns

PP

2

3

Clock Frequency (SD/SDIO Full Speed/High Speed)

Clock Frequency (MMC Full Speed/High Speed)

Clock Frequency (Identification Mode)

0

f

100

7

OD

WL

WH

SD2 Clock Low Time

t

SD3 Clock High Time

SD4 Clock Rise Time

SD5 Clock Fall Time

t

7

—

ns

t

—

3

ns

TLH

THL

t

3

ns

eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)

–3

4

SD6

eSDHC Output Delay

t

3

ns

OD

eSDHC Input / Card Outputs CMD, DAT (Reference to CLK)

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Electrical Characteristics

Table 69. eSDHCv2 Interface Timing Specification (continued)

ID

Parameter

Symbols

Min

Max

Unit

SD7 eSDHC Input Setup Time

SD8 eSDHC Input Hold Time

t

2.5

—

ns

ISU

5

t

IH

1

2

In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

In normal speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode, clock

frequency can be any value between 0–50 MHz.

3

In normal speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock

frequency can be any value between 0–52 MHz.

4

5

Measurement taken with CLoad = 20 pF

To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

4.7.4

FEC AC Timing Parameters

This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC

is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver

interface and transceiver function are required to complete the interface to the media. The FEC supports

the 10/100 Mbps MII (18 pins in total) and the 10 Mbps-only 7-wire interface, which uses 7 of the MII

pins, for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, see i.MX51

Multimedia Applications Processor Reference Manual (MCIMX51RM).

This section describes the AC timing specifications of the FEC.

4.7.4.1

MII Receive Signal Timing

The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and

FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of

25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must

exceed twice the FEC_RX_CLK frequency. Table 70 lists the MII receive channel signal timing

parameters and Figure 43 shows MII receive signal timings.

.

Table 70. MII Receive Signal Timing

1

Num

Characteristic

Min

Max

Unit

M1

M2

M3

M4

FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup

FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold

FEC_RX_CLK pulse width high

5

—

ns

5

—

ns

35%

65%

FEC_RX_CLK period

FEC_RX_CLK pulse width low

1

FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode.

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Electrical Characteristics

M3

FEC_RX_CLK (input)

M4

FEC_RXD[3:0] (inputs)

FEC_RX_DV

FEC_RX_ER

M1

M2

Figure 43. MII Receive Signal Timing Diagram

4.7.4.2

MII Transmit Signal Timing

The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and

FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency

of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency

must exceed twice the FEC_TX_CLK frequency. Table 71 lists MII transmit channel timing parameters

and Figure 44 shows MII transmit signal timing diagram for the values listed in Table 71.

Table 71. MII Transmit Signal Timing

1

Num

Characteristic

Min

Max

Unit

M5

M6

M7

M8

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid

FEC_TX_CLK pulse width high

5

—

20

ns

—

ns

35%

65%

FEC_TX_CLK period

FEC_TX_CLK pulse width low

1

FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.

.

M7

FEC_TX_CLK (input)

M5

M8

FEC_TXD[3:0] (outputs)

FEC_TX_EN

FEC_TX_ER

M6

Figure 44. MII Transmit Signal Timing Diagram

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Electrical Characteristics

4.7.4.3

MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)

Table 72 lists MII asynchronous inputs signal timing information. Figure 45 shows MII asynchronous

input timings listed in Table 72.

Table 72. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

1

M9

FEC_CRS to FEC_COL minimum pulse width

1.5

—

FEC_TX_CLK period

1

FEC_COL has the same timing in 10 Mbit 7-wire interface mode.

.

FEC_CRS, FEC_COL

M9

Figure 45. MII Async Inputs Timing Diagram

4.7.4.4

MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

Table 73 lists MII serial management channel timings. Figure 46 shows MII serial management channel

timings listed in Table 73. The MDC frequency should be equal to or less than 2.5 MHz to be compliant

with the IEEE 802.3 MII specification. However the FEC can function correctly with a maximum MDC

frequency of 15 MHz.

Table 73. MII Transmit Signal Timing

ID

Characteristic

Min Max

Unit

M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)

M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)

M12 FEC_MDIO (input) to FEC_MDC rising edge setup

M13 FEC_MDIO (input) to FEC_MDC rising edge hold

M14 FEC_MDC pulse width high

0

—

18

0

—

5

ns

—

40% 60% FEC_MDC period

M15 FEC_MDC pulse width low

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79

Electrical Characteristics

M14

M15

FEC_MDC (output)

M10

FEC_MDIO (output)

FEC_MDIO (input)

M11

M12

Figure 46. MII Serial Management Channel Timing Diagram

M13

4.7.5

Frequency Pre-Multiplier (FPM) Electrical Parameters (CKIL)

The FPM is a DPLL that converts a signal operating in the kilohertz region into a clock signal operating

in the megahertz region. The output of the FPM provides the reference frequency for the on-chip DPLLs.

Parameters of the FPM are listed in Table 74.

Table 74. FPM Specifications

Parameter

Reference clock frequency range—CKIL

Min

Typ

Max

Unit

32

8

32.768

256

33

kHz

MHz

—

FPM output clock frequency range

—

8

FPM multiplication factor (test condition is changed by a factor of 2)

128

—

1024

312.5

20

1

Lock-in time

µs

Cycle-to-cycle frequency jitter (peak to peak)

—

ns

1

plrf = 1 cycle assumed missed + x cycles for reset deassert + y cycles for calibration and lock x[ts] = {2,3,5,9};

y[ts] = {7,8,10,14}; where ts is the chosen time scale of the reference clock. In this case reference clock = 32 kHz which makes

ts = 0, therefore total time required for achieving lock is 10(1+2+7) cycles or 312.5 µs.

4.7.6

High-Speed I²C (HS-I²C) Timing Parameters

2

This section describes the timing parameters of the HS-I C module. This module can operate in the

following modes: Standard, Fast and High speed.

NOTE

2

See the errata for the HS-I C module in the i.MX51 Chip Errata. There are

two standard I C modules that have no errata.

2

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Electrical Characteristics

4.7.6.1

Standard and Fast Mode Timing Parameters

2

Figure 47 depicts the standard and fast mode timings of HS-I C module, and Table 75 lists the timing

characteristics.

IC11

IC9

IC10

SDAH

SCLH

IC7

IC4

IC2

IC3

IC8

IC10

IC6

IC11

STOP

START

IC5

IC1

2

Figure 47. HS-I C Standard and Fast Mode Bus Timing

2

Table 75. HS-I C Timing Parameters—Standard and Fast Mode

Standard Mode

Fast Mode

ID

Parameter

Unit

Min

Max

Min

Max

IC1

IC2

IC3

IC4

IC5

IC6

IC7

IC8

IC9

SCLH cycle time

10

4.0

—

2.5

0.6

—

µs

ns

µs

ns

pF

Hold time (repeated) START condition

Set-up time for STOP condition

Data hold time

1

2

1

2

0

3.45

—

0

0.9

HIGH Period of SCLH Clock

4.0

4.7

250

4.7

—

0.6

1.3

0.6

—

LOW Period of the SCLH Clock

Set-up time for a repeated START condition

Data set-up time

—

3

—

100

1.3

—

Bus free time between a STOP and START condition

—

4

IC10 Rise time of both SDAH and SCLH signals

IC11 Fall time of both SDAH and SCLH signals

1000

300

100

20+0.1C

—

300

100

b

—

IC12 Capacitive load for each bus line (C )

—

b

1

A device must internally provide a hold time of at least 300 ns for SDAH signal in order to bridge the undefined region of the

falling edge of SCLH.

2

3

The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC6) of the SCLH signal

2

A Fast-mode I C-bus device can be used in a Standard-mode I C-bus system, but the requirement of Set-up time (ID No IC8)

of 250 ns must then be met. This automatically is the case if the device does not stretch the LOW period of the SCLH signal.

If such a device does stretch the LOW period of the SCLH signal, it must output the next data bit to the SDAH line max_rise_time

2

(ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I C-bus specification)

before the SCLH line is released.

4

C = total capacitance of one bus line in pF.

b

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Electrical Characteristics

4.7.6.2

High-Speed Mode Timing Parameters

2

Figure 48 depicts the high-speed mode timings of HS-I C module, and Table 76 lists the timing

characteristics.

IC12

IC11

SDAH

IC2

IC7

IC3

IC6

SCLH

IC13

IC9

IC4

IC10

STOP

START

IC5

IC8

IC1

Figure 48. High-Speed Mode Timing

2

Table 76. HS-I C High-Speed Mode Timing Parameters

High-Speed Mode

ID

Parameter

Unit

Min

Max

IC1 SCLH cycle time

10

160

60

3.4

—

MHz

ns

pF

IC2 Setup time (repeated) START condition

IC3 Hold time (repeated) START condition

IC4 LOW Period of the SCLH Clock

IC5 HIGH Period of SCLH Clock

—

IC6 Data set-up time

10

—

1

IC7 Data hold time

0

70

40

80

40

80

—

IC8 Rise time of SCLH

10

160

—

IC9 Rise time of SCLH signal after a repeated START condition and after an acknowledge bit

IC10 Fall time of SCLH signal

IC11 Rise time of SDAH signal

IC12 Fall time of SDAH signal

IC13 Set-up time for STOP condition

IC14 Capacitive load for each bus line (C )

100

b

1

A device must internally provide a hold time of at least 300 ns for SDAH signal in order to bridge the undefined region of the

falling edge of SCLH.

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4.7.7

I²C Module Timing Parameters

2

This section describes the timing parameters of the I C Module. Figure 49 depicts the timing of I C

module, and Table 77 lists the I C Module timing characteristics.

2

IC11

IC9

IC10

I2DAT

I2CLK

IC7

IC4

IC2

IC3

IC8

IC10

IC6

IC11

STOP

START

IC5

IC1

2

Figure 49. I C Bus Timing

2

Table 77. I C Module Timing Parameters

Standard Mode

Supply Voltage =

1.65 V–1.95 V, 2.7 V–3.3 V

Fast Mode

Supply Voltage =

2.7 V–3.3 V

ID

Parameter

Unit

Min

Max

Min

Max

IC1

IC2

IC3

IC4

IC5

IC6

IC7

IC8

IC9

IC10

IC11

IC12

I2CLK cycle time

10

—

2.5

0.6

—

µs

ns

µs

Hold time (repeated) START condition

Set-up time for STOP condition

Data hold time

4.0

1

2

1

2

0

3.45

—

0

0.9

HIGH Period of I2CLK Clock

4.0

4.7

250

4.7

—

0.6

1.3

0.6

—

LOW Period of the I2CLK Clock

Set-up time for a repeated START condition

Data set-up time

—

3

—

100

1.3

Bus free time between a STOP and START condition

Rise time of both I2DAT and I2CLK signals

Fall time of both I2DAT and I2CLK signals

—

4

1000

300

400

20 + 0.1C

—

300 ns

400 pF

b

—

Capacitive load for each bus line (C )

—

b

1

A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the

falling edge of I2CLK.

2

3

The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)

of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.

If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line

max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)

before the I2CLK line is released.

4

C = total capacitance of one bus line in pF.

b

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Electrical Characteristics

4.7.8

Image Processing Unit (IPU) Module Parameters

The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor

and/or to a display device. This support covers all aspects of these activities:

•

Connectivity to relevant devices—cameras, displays, graphics accelerators, and TV encoders.

Related image processing and manipulation: display processing, image conversions, and other

related functions.

•

Synchronization and control capabilities such as avoidance of tearing artifacts.

4.7.8.1

Sensor Interface Timings

There are three camera timing modes supported by the IPU.

4.7.8.1.1

BT.656 and BT.1120 Video Mode

Smart camera sensors, which include imaging processing, usually support video mode transfer. They use

an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing

syntax is defined by the BT.656/BT.1120 standards.

This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only

control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data

stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking

is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data

stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one

component per cycle is received over the SENSB_DATA bus. On BT.1120 two components per cycle are

received over the SENSB_DATA bus.

4.7.8.1.2

Gated Clock Mode

The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See

Figure 50.

Active Line

Start of Frame

nth frame

n+1th frame

SENSB_VSYNC

SENSB_HSYNC

SENSB_PIX_CLK

invalid

SENSB_DATA[19:0]

1st byte

Figure 50. Gated Clock Mode Timing Diagram

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Electrical Characteristics

A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the

corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid

as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.

SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops

receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the

SENSB_VSYNC timing repeats.

4.7.8.1.3

Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.7.8.1.2, “Gated Clock Mode”),

except for the SENSB_HSYNC signal, which is not used. See Figure 51. All incoming pixel clocks are

valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states

low) until valid data is going to be transmitted over the bus.

Start of Frame

nth frame

n+1th frame

SENSB_VSYNC

SENSB_PIX_CLK

invalid

SENSB_DATA[19:0]

1st byte

Figure 51. Non-Gated Clock Mode Timing Diagram

The timing described in Figure 51 is that of a typical sensor. Some other sensors may have a slightly

different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;

active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.

4.7.8.2

Electrical Characteristics

Figure 52 shows the sensor interface timing diagram. SENSB_PIX_CLK signal described here is not

generated by the IPU. Table 78 shows the timing characteristics for the diagram shown in Figure 52.

SENSB_PIX_CLK

(Sensor Output)

1/IP1

IP2

IP3

SENSB_DATA,

SENSB_VSYNC,

SENSB_HSYNC

Figure 52. Sensor Interface Timing Diagram

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Electrical Characteristics

Table 78. Sensor Interface Timing Characteristics

ID

Parameter

Symbol

Fpck

Min

Max

Unit

MHz

IP1

IP2

IP3

Sensor output (pixel) clock frequency

Data and control setup time

0.01

3

120

—

Tsu

Thd

ns

Data and control holdup time

2

—

4.7.8.3

IPU Display Interface Signal Mapping

The IPU supports a number of display output video formats. Table 79 defines the mapping of the Display

Interface Pins used during various supported video interface formats.

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Table 79. Video Signal Cross-Reference

LCD

i.MX51A

1

RGB/TV Signal Allocation (Example)

16-bit 18-bit 24-bit 8-bit 16-bit 20-bit

Smart

Comment

RGB,

Signal

Name

Port Name

(x=1,2)

Signal

Name

2

(General) RGB RGB RGB YCrCb YCrCb YCrCb

DISPx_DAT0

DISPx_DAT1

DISPx_DAT2

DISPx_DAT3

DISPx_DAT4

DISPx_DAT5

DISPx_DAT6

DISPx_DAT7

DISPx_DAT8

DISPx_DAT9

DAT[0]

DAT[1]

DAT[2]

DAT[3]

DAT[4]

DAT[5]

DAT[6]

DAT[7]

DAT[8]

DAT[9]

B[0]

B[1]

B[2]

B[3]

B[4]

G[0]

G[1]

G[2]

G[3]

G[4]

G[5]

R[0]

R[1]

R[2]

R[3]

R[4]

—

B[0]

B[1]

B[2]

B[3]

B[4]

B[5]

G[0]

G[1]

G[2]

G[3]

G[4]

G[5]

R[0]

R[1]

R[2]

R[3]

R[4]

R[5]

—

B[0]

B[1]

B[2]

B[3]

B[4]

B[5]

B[6]

B[7]

G[0]

G[1]

G[2]

G[3]

G[4]

G[5]

G[6]

G[7]

R[0]

R[1]

R[2]

R[3]

R[4]

R[5]

Y/C[0]

Y/C[1]

Y/C[2]

Y/C[3]

Y/C[4]

Y/C[5]

Y/C[6]

Y/C[7]

—

C[0]

C[1]

C[2]

C[3]

C[4]

C[5]

C[6]

C[7]

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

—

C[0]

C[1]

C[2]

C[3]

C[4]

C[5]

C[6]

C[7]

C[8]

C[9]

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

Y[8]

Y[9]

—

DAT[0]

DAT[1]

DAT[2]

DAT[3]

DAT[4]

DAT[5]

DAT[6]

DAT[7]

DAT[8]

DAT[9]

DAT[10]

DAT[11]

DAT[12]

DAT[13]

DAT[14]

DAT[15]

—

The restrictions are as follows:

a) There are maximal three

continuous groups of bits that

could be independently mapped to

the external bus.

Groups should not be overlapped.

b) The bit order is expressed in

each of the bit groups, for example

B[0] = least significant blue pixel

bit

—

DISPx_DAT10 DAT[10]

DISPx_DAT11 DAT[11]

DISPx_DAT12 DAT[12]

DISPx_DAT13 DAT[13]

DISPx_DAT14 DAT[14]

DISPx_DAT15 DAT[15]

DISPx_DAT16 DAT[16]

DISPx_DAT17 DAT[17]

DISPx_DAT18 DAT[18]

DISPx_DAT19 DAT[19]

DISPx_DAT20 DAT[20]

DISPx_DAT21 DAT[21]

—

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Table 79. Video Signal Cross-Reference (continued)

LCD

i.MX51A

1

RGB/TV Signal Allocation (Example)

16-bit 18-bit 24-bit 8-bit 16-bit 20-bit

Smart

Comment

RGB,

Signal

Name

Port Name

(x=1,2)

Signal

Name

2

(General) RGB RGB RGB YCrCb YCrCb YCrCb

DISPx_DAT22 DAT[22]

DISPx_DAT23 DAT[23]

DIx_DISP_CLK

—

R[6]

R[7]

—

PixCLK

—

DIx_PIN1

VSYNC_IN May be required for anti-tearing

DIx_PIN2

DIx_PIN3

DIx_PIN4

DIx_PIN5

DIx_PIN6

DIx_PIN7

DIx_PIN8

DIx_D0_CS

DIx_D1_CS

HSYNC

—

VSYNC

—

VSYNC out

—

Additional frame/row synchronous

signals with programmable timing

—

CS0

CS1

—

Alternate mode of PWM output for

contrast or brightness control

DIx_PIN11

DIx_PIN12

DIx_PIN13

DIx_PIN14

DIx_PIN15

DIx_PIN16

DIx_PIN17

—

WR

RD

—

RS1

RS2

DRDY

—

Register select signal

Optional RS2

—

DRDY/DV

Data validation/blank, data enable

—

Q

Additional data synchronous

signals with programmable

features/timing

—

1

Signal mapping (both data and control/synchronization) is flexible. The table provides examples.

2

This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line

start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data

during blanking intervals is not supported.

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4.7.8.4

IPU Display Interface Timing

The IPU Display Interface supports two kinds of display’s accesses: synchronous and asynchronous. There

are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.

4.7.8.4.1

Synchronous Controls

The synchronous control is a signal that changes its value as a function either of a system or of an external

clock. This control has a permanent period and a permanent wave form.

There are special physical outputs to provide synchronous controls:

•

The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display

(component, pixel) clock for a display.

•

The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide

HSYNC, VSYNC, DRDY or any else independent signal to a display.

The IPU has a system of internal binding counters for internal events (like HSYNC/VSYCN and so on)

calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control

starts from the local start point with predefined UP and DOWN values to calculate control’s changing

points with half DI_CLK resolution. A full description of the counters system is in the IPU chapter of the

i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM).

4.7.8.4.2

Asynchronous Controls

The asynchronous control is a data oriented signal that changes its a value with an output data according

to an additional internal flags coming with the data.

There are special physical outputs to provide asynchronous controls, as follows:

•

The ipp_d0_cs and ipp_d1_cspins are dedicated to provide chip select signals to two displays

The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide

WR. RD, RS or any else data oriented signal to display.

NOTE

The IPU has independent signal generators for asynchronous signals

toggling. When a DI decides to put a new asynchronous data in the bus, a

new internal start (local start point) is generated. The signals generators

calculate predefined UP and DOWN values to change pins states with half

DI_CLK resolution.

4.7.8.5

Synchronous Interfaces to Standard Active Matrix TFT LCD Panels

IPU Display Operating Signals

4.7.8.5.1

The IPU uses four control signals and data to operate a standard synchronous interface:

•

IPP_DISP_CLK—Clock to display

HSYNC—Horizontal synchronization

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Electrical Characteristics

•

VSYNC—Vertical synchronization

DRDY—Active data

All synchronous display controls are generated on base of an internal generated “local start point”. The

synchronous display controls can be placed on time axis with DI’s offset, up and down parameters. The

display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved relative

to the local start point.

4.7.8.5.2

LCD Interface Functional Description

Figure 53 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure

signals are shown with negative polarity. The sequence of events for active matrix interface timing is:

•

DI_CLK internal DI clock, used for calculation of other controls.

IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).

In active mode, IPP_DISP_CLK runs continuously.

•

HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC)

VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.

(Usually IPP_PIN_3 is used as VSYNC)

•

DRDY acts like an output enable signal to the CRT display. This output enables the data to be

shifted onto the display. When disabled, the data is invalid and the trace is off.

(For DRDY can be used either synchronous or asynchronous generic purpose pin as well.)

VSYNC

HSYNC

LINE 1

LINE 2

LINE 3

LINE 4

LINE n-1 LINE n

HSYNC

DRDY

1

2

3

m-1

m

IPP_DISP_CLK

IPP_DATA

Figure 53. Interface Timing Diagram for TFT (Active Matrix) Panels

4.7.8.5.3

TFT Panel Sync Pulse Timing Diagrams

Figure 54 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and

the data. All shown on the figure parameters are programmable. All controls are started by corresponding

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Electrical Characteristics

internal events—local start points. The timing diagrams correspond to inverse polarity of the

IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC and DRDY signals.

IP13o

IP7

IP5

IP5o

IP8o

IP8

DI clock

IPP_DISP_CLK

VSYNC

HSYNC

DRDY

IPP_DATA

Dn

D0

D1

IP9o

IP10

IP9

IP6

Figure 54. TFT Panels Timing Diagram—Horizontal Sync Pulse

Figure 55 depicts the vertical timing (timing of one frame). All parameters shown in the figure are

programmable.

End of frame

Start of frame

IP13

VSYNC

HSYNC

DRDY

IP11

IP15

IP14

IP12

Figure 55. TFT Panels Timing Diagram—Vertical Sync Pulse

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Electrical Characteristics

Table 80 shows timing characteristics of signals presented in Figure 54 and Figure 55.

Table 80. Synchronous Display Interface Timing Characteristics (Pixel Level)

ID

Parameter

Symbol

Value

Description

Unit

1

IP5

IP6

Display interface clock period Tdicp

Display pixel clock period

( )

Display interface clock. IPP_DISP_CLK

ns

Tdpcp DISP_CLK_PER_PIXEL Time of translation of one pixel to display,

× Tdicp

DISP_CLK_PER_PIXEL—number of pixel

components in one pixel (1.n). The

DISP_CLK_PER_PIXEL is virtual

parameter to define Display pixel clock

period.

The DISP_CLK_PER_PIXEL is received by

DC/DI one access division to n

components.

IP7

Screen width time

Tsw

(SCREEN_WIDTH)

SCREEN_WIDTH—screen width in,

interface clocks. horizontal blanking

included.

ns

× Tdicp

The SCREEN_WIDTH should be built by

2

suitable DI’s counter .

IP8

IP9

HSYNC width time

Thsw

Thbi1

(HSYNC_WIDTH)

HSYNC_WIDTH—Hsync width in DI_CLK

with 0.5 DI_CLK resolution. Defined by DI’s

counter.

ns

Horizontal blank interval 1

^BGXP× Tdicp

BGXP—Width of a horizontal blanking

before a first active data in a line. (in

interface clocks). The BGXP should be built

by suitable DI’s counter.

IP10 Horizontal blank interval 2

Thbi2

Tsh

(SCREEN_WIDTH -

^{BGXP - FW)}× Tdicp

Width a horizontal blanking after a last

active data in a line. (in interface clocks)

FW—with of active line in interface clocks.

The FW should be built by suitable DI’s

counter.

ns

IP12 Screen height

(SCREEN_HEIGHT)

SCREEN_HEIGHT— screen height in lines ns

with blanking

The SCREEN_HEIGHT is a distance

between 2 VSYNCs.

× Tsw

The SCREEN_HEIGHT should be built by

suitable DI’s counter.

IP13 VSYNC width

Tvsw

Tvbi1

Tvbi2

VSYNC_WIDTH

VSYNC_WIDTH—Vsync width in DI_CLK

with 0.5 DI_CLK resolution. Defined by DI’s

counter

ns

IP14 Vertical blank interval 1

IP15 Vertical blank interval 2

^BGYP× Tsw

BGYP—width of first Vertical

blanking interval in line.The BGYP should

be built by suitable DI’s counter.

(SCREEN_HEIGHT -

width of second Vertical

^{BGYP - FH)}× Tsw

blanking interval in line.The FH should be

built by suitable DI’s counter.

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Electrical Characteristics

Table 80. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)

ID

Parameter

Symbol

Value

Description

Unit

IP5o Offset of IPP_DISP_CLK

Todicp

DISP_CLK_OFFSET— offset of

IPP_DISP_CLK edges from local start

^{point, in DI_CLK}×2

ns

^DISP_×^CLT^Kd^_ic^Olk^FFSET

(0.5 DI_CLK Resolution)

Defined by DISP_CLK counter

IP13o Offset of VSYNC

Tovs

Tohs

VSYNC_OFFSET

VSYNC_OFFSET—offset of Vsync edges

from a local start point, when a Vsync

^{should be active, in DI_CLK}×2

(0.5 DI_CLK Resolution).The

VSYNC_OFFSET should be built by

suitable DI’s counter.

ns

× Tdiclk

IP8o Offset of HSYNC

HSYNC_OFFSET

HSYNC_OFFSET—offset of Hsync edges

from a local start point, when a Hsync

^{should be active, in DI_CLK}×2

(0.5 DI_CLK Resolution).The

HSYNC_OFFSET should be built by

suitable DI’s counter.

× Tdiclk

IP9o Offset of DRDY

Todrdy

DRDY_OFFSET

DRDY_OFFSET— offset of DRDY edges

from a suitable local start point, when a

corresponding data has been set on the

^{bus, in DI_CLK}×2

× Tdiclk

(0.5 DI_CLK Resolution)

The DRDY_OFFSET should be built by

suitable DI’s counter.

1

Display interface clock period immediate value.

⎧

DISP_CLK_PERIOD

------------------------------------------------------

DISP_CLK_PERIOD

DI_CLK_PERIOD

⎪ T

⎪

×

,

for integer ------------------------------------------------------

diclk

DI_CLK_PERIOD

Tdicp =

⎨

DISP_CLK_PERIOD

------------------------------------------------------

DISP_CLK_PERIOD

⎪

⎛

⎞

T

floor

+ 0.5 0.5 ,

for fractional ------------------------------------------------------

diclk

⎪

⎩

⎝

⎠

DI_CLK_PERIOD

DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK

DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency

Display interface clock period average value.

DISP_CLK_PERIOD

------------------------------------------------------

Tdicp = T

×

DI_CLK_PERIOD

diclk

2

DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the

counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by

corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance

between HSYNCs is a SCREEN_WIDTH.

The maximal accuracy of UP/DOWN edge of controls is

Accuracy = (0.5 × T

) 0.75ns

diclk

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Electrical Characteristics

The maximal accuracy of UP/DOWN edge of IPP_DATA is

Accuracy = T

0.75ns

diclk

The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are programmed via registers.

Figure 56 shows the synchronous display interface timing diagram for access level. The

DISP_CLK_DOWN and DISP_CLK_UP parameters are set by using the register. Table 81 shows the

timing characteristics for the diagram shown in Figure 56.

IP20o IP20

VSYNC

HSYNC

DRDY

other controls

IPP_DISP_CLK

Tdicd

Tdicu

IP18

IPP_DATA

IP16

IP17

IP19

local start point

Figure 56. Synchronous Display Interface Timing Diagram—Access Level

Table 81. Synchronous Display Interface Timing Characteristics (Access Level)

1

ID

Parameter

Symbol

Min

Typ

Max

Unit

2

3

IP16

Display interface clock Tckl

low time

Tdicd-Tdicu–1.5

Tdicd –Tdicu

Tdicd–Tdicu+1.5

ns

IP17

Display interface clock Tckh

high time

Tdicp–Tdicd+Tdicu–1.5 Tdicp–Tdicd+Tdicu Tdicp–Tdicd+Tdicu+1.5

ns

IP18

IP19

IP20o

Data setup time

Data holdup time

Tdsu

Tdhd

Tocsu

Tdicd–1.5

Tdicu

—

ns

—

Tdicp–Tdicd–1.5

Tocsu–1.5

Tdicp–Tdicu

Tocsu

Control signals offset

times (defines for each

pin)

Tocsu+1.5

IP20

Control signals setup

time to display interface

clock (defines for each

pin)

Tcsu

Tdicd–1.5–Tocsu%Tdicp Tdicu

—

ns

1

The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

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2

3

Display interface clock down time

Display interface clock up time

2 × DISP_CLK_DOWN

1

2

⎛

⎞

⎠

-------------------------------------------------------------

Tdicd = -- T

× ceil

diclk

⎝

DI_CLK_PERIOD

2 × DISP_CLK_UP

1

2

⎛

⎞

⎠

--------------------------------------------------

Tdicu = -- T

× ceil

diclk

⎝

DI_CLK_PERIOD

where CEIL(X) rounds the elements of X to the nearest integers towards infinity.

4.7.8.6

Interface to a TV Encoder

The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of

the interface is described in Figure 57.

NOTE

•

The frequency of the clock DISP_CLK is 27 MHz (within 10%)

The HSYNC, VSYNC signals are active low.

The DRDY signal is shown as active high.

The transition to the next row is marked by the negative edge of the

HSYNC signal. It remains low for a single clock cycle

•

The transition to the next field/frame is marked by the negative edge of

the VSYNC signal. It remains low for at least one clock cycles

— At a transition to an odd field (of the next frame), the negative edges

of VSYNC and HSYNC coincide.

— At a transition is to an even field (of the same frame), they do not

coincide.

•

The active intervals—during which data is transferred—are marked by

the HSYNC signal being high.

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95

Electrical Characteristics

DISP_CLK

HSYNC

VSYNC

DRDY

Cb

Y

Cr

Y

Cb

Y

Cr

IPP_DATA

Pixel Data Timing

523

524

525

1

2

3

4

5

6

10

HSYNC

DRDY

VSYNC

Even Field

262 263

Odd Field

268 269

261

264

265

266

267

273

HSYNC

DRDY

VSYNC

Even Field

Odd Field

Line and Field Timing - NTSC

621

622

623

624

625

1

2

3

4

23

HSYNC

DRDY

VSYNC

Even Field

Odd Field

308

309

310

311

312

313

314

315

316

336

HSYNC

DRDY

VSYNC

Even Field

Odd Field

Line and Field Timing - PAL

Figure 57. TV Encoder Interface Timing Diagram

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Electrical Characteristics

4.7.8.6.1

TV Encoder Performance Specifications

All the parameters in the table are defined under the following conditions:

Rset = 1.05 kΩ 1%, resistor on VREFOUT pin to Ground

Rload = 37.5 Ω 1%, output load to Ground

The TV encoder output specifications are shown in Table 82.

Table 82. TV Encoder Video Performance Specifications

Parameter

Conditions

Min

Typ

Max

Unit

DAC STATIC PERFORMANCE

1

Resolution

—

10

1

—

2

Bits

2

Integral Nonlinearity (INL)

LSBs

%

2

Differential Nonlinearity (DNL)

—

0.6

2

1

2

Channel-to-channel gain matching

—

2

Full scale output voltage

Rset = 1.05 kΩ 1%

Rload = 37.5 Ω 1%

1.24

1.35

1.45

V

DAC DYNAMIC PERFORMANCE

Spurious Free Dynamic Range (SFDR)

F

= 3.38 MHz

—

59

54

—

dBc

out

= 216 MHz

samp

Spurious Free Dynamic Range (SFDR)

F

= 9.28 MHz

= 297 MHz

out

samp

2, 3

VIDEO PERFORMANCE IN SD MODE

Short Term Jitter (Line to Line)

Long Term Jitter (Field to Field)

Frequency Response

—

2.5

3.5

—

0.1

0

ns

—

0-4.0 MHz

5.75 MHz

—

ns

–0.1

–0.7

—

dB

—

dB

Luminance Nonlinearity

Differential Gain

0.5

0.35

0.6

75

—

%

—

%

Differential Phase

—

Degrees

Signal-to-Noise Ratio (SNR)

Hue Accuracy

Flat field full bandwidth

—

dB

—

0.8

1.5

–70

–47

0.5

2.5

0.1

Degrees

Color Saturation Accuracy

Chroma AM Noise

—

%

dB

—

Chroma PM Noise

—

dB

Chroma Nonlinear Phase

Chroma Nonlinear Gain

Chroma/Luma Intermodulation

—

Degrees

%

—

%

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Electrical Characteristics

Table 82. TV Encoder Video Performance Specifications (continued)

Chroma/Luma Gain Inequality

Chroma/Luma Delay Inequality

—

1.0

—

%

ns

—

2

VIDEO PERFORMANCE IN HD MODE

Luma Frequency Response

0-30 MHz

–0.2

—

0.2

dB

Chroma Frequency Response

0-15 MHz,

YCbCr 422 mode

Luma Nonlinearity

—

3.2

3.4

62

—

%

Chroma Nonlinearity

—

%

Luma Signal-to-Noise Ratio

Chroma Signal-to-Noise Ratio

0-30 MHz

0-15 MHz

dB

72

1

Guaranteed by design

2

3

Guaranteed by characterization

R

= VREFOUT's external resistor to ground = 1.05 kΩ

set

4.7.8.7

Asynchronous Interfaces

Standard Parallel Interfaces

4.7.8.7.1

The IPU has four signal generator machines for asynchronous signal. Each machine generates IPU’s

internal control levels (0 or 1) by UP and DOWN are defined in Registers. Each asynchronous pin has a

dynamic connection with one of the signal generators. This connection is redefined again with a new

display access (pixel/component) The IPU can generate control signals according to system 80/68

requirements. The burst length is received as a result from predefined behavior of the internal signal

generator machines.

The access to a display is realized by the following:

•

CS (IPP_CS) chip select

WR (IPP_PIN_11) write strobe

RD (IPP_PIN_12) read strobe

RS (IPP_PIN_13) Register select (A0)

Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 58,

Figure 59, Figure 60, and Figure 61. The timing images correspond to active-low IPP_CS, WR and RD

signals.

Each asynchronous access is defined by an access size parameter. This parameter can be different between

different kinds of accesses. This parameter defines a length of windows, when suitable controls of the

current access are valid. A pause between two different display accesses can be guaranteed by programing

of suitable access sizes. There are no minimal/maximal hold/setup time hard defined by DI. Each control

signal can be switched at any time during access size.

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Electrical Characteristics

IPP_CS

RS

WR

RD

IPP_DATA

Burst access mode with sampling by CS signal

IPP_CS

RS

WR

RD

IPP_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 58. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram

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Electrical Characteristics

IPP_CS

RS

WR

RD

IPP_DATA

Burst access mode with sampling by WR/RD signals

IPP_CS

RS

WR

RD

IPP_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 59. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram

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Electrical Characteristics

IPP_CS

RS

WR

(READ/WRITE)

RD

(ENABLE)

IPP_DATA

Burst access mode with sampling by CS signal

IPP_CS

RS

WR

(READ/WRITE)

RD

(ENABLE)

IPP_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 60. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram

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Electrical Characteristics

IPP_CS

RS

WR

(READ/WRITE)

RD

(ENABLE)

IPP_DATA

Burst access mode with sampling by ENABLE signal

IPP_CS

RS

WR

(READ/WRITE)

RD

(ENABLE)

IPP_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 61. Asynchronous Parallel System 68k Interface (Type 2) TIming Diagram

Display operation can be performed with IPP_WAIT signal. The DI reacts to the incoming IPP_WAIT

signal with 2 DI_CLK delay. The DI finishes a current access and a next access is postponed until

IPP_WAIT release.

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Electrical Characteristics

Figure 62 shows timing of the parallel interface with IPP_WAIT control.

DI clock

IPP_CS

IPP_DATA

WR

RD

IPP_WAIT

IPP_DATA_IN

waiting

IP39

waiting

Figure 62. Parallel Interface Timing Diagram—Read Wait States

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Electrical Characteristics

4.7.8.7.2

Asynchronous Parallel Interface Timing Parameters

Figure 63 depicts timing of asynchronous parallel interfaces based on the system 80 and system 68k

interfaces. Table 84 shows the timing characteristics at display access level. Table 83 shows the timing

characteristics at the logical level—from configuration perspective. All timing diagrams are based on

active low control signals (signals polarity is controlled through the DI_DISP_SIG_POL register).

IP29 IP32

IP35

IP30

IP36

IP47

IP31

IP33

IP34

DI clock

IPP_CS

RS

WR

RD

IPP_DATA

A0

D0

D1

D2

D3

PP_DATA_IN

IP27

IP28a

IP28d

IP37

IP38

Figure 63. Asynchronous Parallel Interface Timing Diagram

Table 83. Asynchronous Display Interface Timing Parameters (Pixel Level)

ID

Parameter

Read system cycle time

Symbol

Value

Description

Unit

IP27

Tcycr

ACCESS_SIZE_#

UP#

predefined value in DI REGISTER

ns

IP28a Address Write system cycle time Tcycwa

IP28d Data Write system cycle time

Tcycwd

Tdcsrr

IP29

RS start

RS strobe switch, predefined value

in DI REGISTER

IP30

CS start

Tdcsc

UP#

CS strobe switch, predefined value

in DI REGISTER

ns

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Table 83. Asynchronous Display Interface Timing Parameters (Pixel Level) (continued)

ID

Parameter

Symbol

Value

Description

Unit

IP31

CS hold

Tdchc

DOWN#

CS strobe release, predefined

value in DI REGISTER

—

IP32

IP33

IP34

IP35

IP36

IP37

RS hold

Tdchrr

Tdcsr

Tdchr

Tdcsw

Tdchw

Tracc

DOWN#

UP#

RS strobe release, predefined

value in DI REGISTER

—

ns

Read start

Read hold

Write start

read strobe switch, predefined

value in DI REGISTER

DOWN#

read strobe release signal,

predefined value in DI REGISTER

UP#

write strobe switch, predefined

value in DI REGISTER

Controls hold time for write

DOWN#

write strobe release, predefined

value in DI REGISTER

1

Slave device data delay

Delay of incoming data

Physical delay of display’s data,

defined from Read access local

start point

3

IP38

IP47

Slave device data hold time

Troh

Tdrp

Hold time of data on the buss Time that display read data is valid

in input bus

ns

—

13

Read time point

Data sampling point

Point of input data sampling by DI,

predefined in DC Microcode

1

This parameter is a requirement to the display connected to the IPU.

Table 84. Asynchronous Parallel Interface Timing Parameters (Access Level)

1

ID

Parameter

Symbol

Min

Tdicpr–1.5

Typ

Max

Unit

2

IP27 Read system cycle time

IP28 Write system cycle time

IP29 RS start

Tcycr

Tdicpr

Tdicpr+1.5

ns

3

Tcycw Tdicpw–1.5

Tdicpw

Tdicpw+1.5

Tdicurs+1.5

Tdicucs+1.5

Tdcsrr

Tdcsc

Tdchc

Tdicurs–1.5

Tdicurs

Tdicur

IP30 CS start

Tdicucs–1.5

4

5

IP31 CS hold

TdicdcsTdicucs–1.5

Tdicdcs –Tdicucs Tdicdcs–Tdicucs+1.5

6

7

IP32 RS hold

Tdchrr Tdicdrs–Tdicurs–1.5

Tdicdrs –Tdicurs

Tdicdrs–Tdicurs+1.5

Tdicur+1.5

IP33 Controls setup time for read Tdcsr

IP34 Controls hold time for read Tdchr

Tdicur–1.5

Tdicur

8

9

Tdicdr–Tdicur–1.5

Tdicdr –Tdicur

Tdicdr–Tdicur+1.5

Tdicuw+1.5

IP35 Controls setup time for write Tdcsw Tdicuw–1.5

Tdicuw

10

11

IP36 Controls hold time for write

Tdchw Tdicdw–Tdicuw–1.5

Tdicpw –Tdicuw

Tdicdw–Tdicuw+1.5

12

13

14

IP37 Slave device data delay

Tracc

0

—

Tdrp –Tlbd –Tdicur–1.5 ns

Tdicpr–Tdicdr–1.5 ns

8

IP38 Slave device data hold time Troh

Tdrp–Tlbd–Tdicdr+1.5

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Electrical Characteristics

Table 84. Asynchronous Parallel Interface Timing Parameters (Access Level) (continued)

1

ID

Parameter

Symbol

Min

Typ

Max

Unit

IP39 Setup time for wait signal

Tswait

Tdrp

—

ns

13

IP47 Read time point

Tdrp–1.5

Tdrp

Tdrp+1.5

1

The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

2

Display period value for read

DI_ACCESS_SIZE_#

--------------------------------------------------------

× ceil

Tdicpr = T

DI_CLK

DI_CLK_PERIOD

ACCESS_SIZE is predefined in REGISTER

3

Display period value for write

DI_ACCESS_SIZE_#

--------------------------------------------------------

Tdicpw = T

DI_CLK × ceil

DI_CLK_PERIOD

ACCESS_SIZE is predefined in REGISTER

4

Display control down for CS

2 × DISP_DOWN_#

1

2

⎛

⎞

⎠

----------------------------------------------------

DI_CLK_PERIOD

Tdicdcs = -- T

⎝ DI_CLK

× ceil

DISP_DOWN is predefined in REGISTER

5

Display control up for CS

2 × DISP_UP_#

1

2

⎛

⎞

----------------------------------------------

DI_CLK_PERIOD

Tdicucs = -- T

× ceil

DI_CLK

⎝

⎠

DISP_UP is predefined in REGISTER

6

Display control down for RS

2 × DISP_DOWN_#

1

2

⎛

⎞

----------------------------------------------------

Tdicdrs = -- T

× ceil

DI_CLK

⎝

⎠

DI_CLK_PERIOD

DISP_DOWN is predefined in REGISTER

7

Display control up for RS

2 × DISP_UP_#

1

2

⎛

⎞

⎠

----------------------------------------------

× ceil

Tdicurs = -- T

⎝ DI_CLK

DI_CLK_PERIOD

DISP_UP is predefined in REGISTER

8

Display control down for read

2 × DISP_DOWN_#

1

2

⎛

⎞

----------------------------------------------------

Tdicdr = -- T

× ceil

DI_CLK

⎝

⎠

DI_CLK_PERIOD

DISP_DOWN is predefined in REGISTER

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Electrical Characteristics

9

Display control up for read

2 × DISP_UP_#

1

2

⎛

⎞

⎠

----------------------------------------------

Tdicur = -- T

× ceil

DI_CLK

⎝

DI_CLK_PERIOD

DISP_UP is predefined in REGISTER

10

Display control down for read

2 × DISP_DOWN_#

1

2

⎛

⎞

⎠

----------------------------------------------------

Tdicdrw = -- T

⎝ DI_CLK

DI_CLK_PERIOD

DISP_DOWN is predefined in REGISTER

11

Display control up for write

2 × DISP_UP_#

1

⎛

⎞

----------------------------------------------

Tdicuw = -- T

DI_CLK

⎝

⎠

DI_CLK_PERIOD

2

DISP_UP is predefined in REGISTER

12

This parameter is a requirement to the display connected to the IPU

Data read point

13

DISP#_READ_EN

------------------------------------------------

× ceil

Tdrp = T

DI_CLK

DI_CLK_PERIOD

Note: DISP#_READ_EN—operand of DC’s MICROCDE READ command to sample incoming data

14

Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a

chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific.

4.7.8.8

Standard Serial Interfaces

The IPU supports the following types of asynchronous serial interfaces:

1. 3-wire (with bidirectional data line).

2. 4-wire (with separate data input and output lines).

3. 5-wire type 1 (with sampling RS by the serial clock).

4. 5-wire type 2 (with sampling RS by the chip select signal).

The IPU has four independent outputs and one input. The port can be configured to provide 3, 4, or 5-wire

interfaces.

Figure 64 depicts the timing diagram of the 3-wire serial interface. The timing diagrams correspond to

active-low IPP#_CS signal and the straight polarity of the IPP_CLK signal.

For this interface, a bidirectional data line is used outside the chip. The IPU still uses separate input and

output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide

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Electrical Characteristics

joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D

signal provided by the IPU.

programed

delay

programed

delay

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

RW

RS

D7

D6

D5

D4

D3

D2

D1

D0

Input or output data

Preamble

Figure 64. 3-Wire Serial Interface Timing Diagram

Figure 65 depicts timing diagram of the 4-wire serial interface. For this interface, there are separate input

and output data lines both inside and outside the chip.

Write

programed

delay

programed

delay

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

RW

RS

D7

D6

D5

D4

D3

D2

D1

D0

Preamble

Output data

DISPB_SD_D

(Input)

Read

programed

delay

programed

delay

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

RW

RS

Preamble

DISPB_SD_D

(Input)

D7

D6

D5

D4

D3

D2

D1

D0

Input data

Figure 65. 4-Wire Serial Interface Timing Diagram

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Electrical Characteristics

Figure 66 depicts timing of the 5-wire serial interface. For this interface, a separate RS line is added.

Write

programed

delay

programed

delay

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

RW

D7

D6

D5

D4

D3

D2

D1

D0

Output data

Preamble

DISPB_SD_D

(Input)

programed

delay

DISPB_SER_RS

Read

programed

delay

programed

delay

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

RW

Preamble

DISPB_SD_D

(Input)

D7

D6

D5

D4

D3

D2

D1

D0

Input data

programed

delay

DISPB_SER_RS

Figure 66. 5-Wire Serial Interface Timing Diagram

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4.7.8.8.1

Asynchronous Serial Interface Timing Parameters

Figure 67 depicts timing of the serial interface. Table 85 shows timing characteristics at display access

level.

IP73

IP72

DI clock

IPP_DISPB_DO_SD_D

IPP_DO_DISPB_SER_CS

IP71

IP70

IPP_DO_DISPB_SER_RS

IP68

IP58

IPP_IND_DISPB_SD_D

IP59

IP60,

IP64, IP66

IP55, IP57,

IP54, IP56,

IP65, IP67

IP61

IP69

IP50, IP52

IPP_DO_DISPB_SD_D_CLK

IP51,53

IP48, IP49, IP62, IP63

Figure 67. Asynchronous Serial Interface Timing Diagram

Table 85. Asynchronous Serial Interface Timing Characteristics (Access Level)

1

ID

Parameter

Symbol

Min

Typ

Max

Tdicpr+1.5

Unit

ns

2

IP48 Read system cycle time

IP49 Write system cycle time

Tcycr

Tdicpr–1.5

Tdicpr

3

Tcycw

Tdicpw–1.5

Tdicpw

Tdicpw+1.5

ns

4

5

IP50 Read clock low pulse width Trl

IP51 Read clock high pulse width Trh

Tdicdr–Tdicur–1.5

Tdicdr –Tdicur

Tdicdr–Tdicur+1.5

Tdicpr–Tdicdr+Tdicur–1.5 Tdicpr–Tdicdr+

Tdicur

Tdicpr–Tdicdr+Tdicur+ ns

1.5

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Table 85. Asynchronous Serial Interface Timing Characteristics (Access Level) (continued)

1

ID

Parameter

Symbol

Min

Typ

Max

Unit

6

7

IP52 Write clock low pulse width Twl

IP53 Write clock high pulse width Twh

Tdicdw–Tdicuw–1.5

Tdicdw –Tdicuw Tdicdw–Tdicuw+1.5

ns

Tdicpw–Tdicdw+

Tdicuw–1.5

Tdicpw–Tdicdw+ Tdicpw–Tdicdw+

Tdicuw

Tdicur

Tdicuw+1.5

IP54 Controls setup time for read Tdcsr

Tdicur–1.5

—

ns

IP55 Controls hold time for read

Tdchr

Tdicpr–Tdicdr–1.5

Tdicpr–Tdicdr

Tdicuw

Tdicpw–Tdicdw

—

IP56 Controls setup time for write Tdcsw Tdicuw–1.5

IP57 Controls hold time for write Tdchw Tdicpw–Tdicdw–1.5

—

8

9

10

IP58 Slave device data delay

Tracc

0

Tdrp –Tlbd -Tdicur-1.5 ns

8

IP59 Slave device data hold time Troh

Tdrp-Tlbd-Tdicdr+1.5

Tdicdw-1.5

—

Tdicpr-Tdicdr-1.5

—

ns

IP60 Write data setup time

IP61 Write data hold time

Tds

Tdicdw

Tdicpw-Tdicdw

Tdicpr

Tdh

Tdicpw-Tdicdw-1.5

Tdicpr-1.5

—

2

IP62 Read period

Tdicpr

Tdicpr+1.5

Tdicpw+1.5

Tdicdr+1.5

Tdicur+1.5

Tdicdw+1.5

Tdicuw+1.5

Tdrp+1.5

3

IP63 Write period

Tdicpw Tdicpw-1.5

Tdicpw

Tdicdr

4

IP64 Read down time

Tdicdr

Tdicur

Tdicdr-1.5

Tdicur-1.5

5

IP65 Read up time

Tdicur

6

IP66 Write down time

Tdicdw Tdicdw-1.5

Tdicuw Tdicuw-1.5

Tdicdw

Tdicuw

Tdrp

7

IP67 Write up time

9

IP68 Read time point

Tdrp

Toclk

Tdrp-1.5

Toclk-1.5

11

IP69 Clock offset

Toclk

Toclk+1.5

Tdicurs+1.5

Tdicdrs+1.5

Tdicucs+1.5

Tdicdcs+1.5

12

IP70 RS up time

Tdicurs Tdicurs–1.5

Tdicdrs Tdicdrs -1.5

Tdicucs Tdicucs –1.5

Tdicdcs Tdicdcs –1.5

Tdicurs

Tdicdrs

Tdicucs

Tdicdcs

13

IP71 RS down time

14

IP72 CS up time

15

IP73 CS down time

1

The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

2

Display interface clock period value for read

DISP#_IF_CLK_PER_RD

--------------------------------------------------------------------

Tdicpr = T

× ceil

DI_CLK

DI_CLK_PERIOD

3

Display interface clock period value for write

DISP#_IF_CLK_PER_WR

---------------------------------------------------------------------

Tdicpw = T

DI_CLK

DI_CLK_PERIOD

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4

Display interface clock down time for read

2 × DISP_DOWN_#

1

2

⎛

⎞

⎠

----------------------------------------------------

Tdicdr = -- T

× ceil

DI_CLK

⎝

DI_CLK_PERIOD

5

6

7

Display interface clock up time for read

2 × DISP_UP_#

1

⎛

⎞

----------------------------------------------

Tdicur = -- T

DI_CLK

⎝

⎠

DI_CLK_PERIOD

2

Display interface clock down time for write

2 × DISP_DOWN_#

1

2

⎛

⎞

----------------------------------------------------

Tdicdw = -- T

× ceil

DI_CLK

⎝

⎠

DI_CLK_PERIOD

Display interface clock up time for write

2 × DISP_UP_#

1

2

⎛

⎞

----------------------------------------------

Tdicuw = -- T

× ceil

DI_CLK

⎝

⎠

DI_CLK_PERIOD

8

9

This parameter is a requirement to the display connected to the IPU

Data read point

DISP_READ_EN

----------------------------------------------

Tdrp = T

× ceil

DI_CLK

DI_CLK_PERIOD

DISP_RD_EN is predefined in REGISTER

10

Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a

chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific.

11

Display interface clock offset value

DISP_CLK_OFFSET

-------------------------------------------------------

DI_CLK_PERIOD

Toclk = T

× ceil

DI_CLK

CLK_OFFSET is predefined in REGISTER

12

Display RS up time

DISP_RS_UP_#

----------------------------------------------

DI_CLK_PERIOD

Tdicurs = T

× ceil

DI_CLK

DISP_RS_UP is predefined in REGISTER

13

Display RS down time

DISP_RS_DOWN_#

------------------------------------------------------

Tdicdrs = T

× ceil

DI_CLK

DI_CLK_PERIOD

DISP_RS_DOWN is predefined in REGISTER

14

Display RS up time

DISP_CS_UP_#

DI_CLK_PERIOD

----------------------------------------------

Tdicucs = T

× ceil

DI_CLK

DISP_CS_UP is predefined in REGISTER

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15

Display RS down time

DISP_CS_DOWN_#

------------------------------------------------------

Tdicdcs = (T

× ceil)

DI_CLK

DI_CLK_PERIOD

DISP_CS_DOWN is predefined in REGISTER.

4.7.9

1-Wire Timing Parameters

Figure 68 depicts the RPP timing and Table 86 lists the RPP timing parameters.

1-WIRE Tx

DS2502 Tx

“Presence Pulse”

“Reset Pulse”

OW2

One-Wire bus

(BATT_LINE)

OW3

OW1

OW4

Figure 68. Reset and Presence Pulses (RPP) Timing Diagram

Table 86. RPP Sequence Delay Comparisons Timing Parameters

ID

Parameters

Reset Time Low

Symbol

Min

Typ

Max

Unit

OW1

t

480

15

511

—

60

µs

RSTL

OW2

OW3

OW4

Presence Detect High

Presence Detect Low

Reset Time High

t

PDH

t

60

—

240

—

PDL

t

480

512

RSTH

Figure 69 depicts Write 0 Sequence timing, and Table 87 lists the timing parameters.

OW6

One-Wire bus

(BATT_LINE)

OW5

Figure 69. Write 0 Sequence Timing Diagram

Table 87. WR0 Sequence Timing Parameters

ID

Parameter

Symbol

Min

Typ

Max

Unit

OW5

OW6

Write 0 Low Time

Transmission Time Slot

t

60

100

117

120

µs

WR0_low

t

OW5

SLOT

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Figure 70 depicts Write 1 Sequence timing, Figure 71 depicts the Read Sequence timing, and Table 88

lists the timing parameters.

OW8

One-Wire bus

(BATT_LINE)

OW7

Figure 70. Write 1 Sequence Timing Diagram

OW8

One-Wire bus

(BATT_LINE)

OW7

OW9

Figure 71. Read Sequence Timing Diagram

Table 88. WR1 /RD Timing Parameters

ID

Parameter

Write /Read Low Time

Symbol

Min

Typ

Max

Unit

OW7

OW8

OW9

t

1

5

15

120

45

µs

LOW1

Transmission Time Slot

Release Time

t

60

15

117

—

SLOT

t

RELEASE

4.7.10 Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM.The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

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Electrical Characteristics

Figure 72 depicts the timing of the PWM, and Table 89 lists the PWM timing parameters.

1

2a

3b

System Clock

PWM Output

2b

4b

3a

4a

Figure 72. PWM Timing

Table 89. PWM Output Timing Parameter

Ref. No.

Parameter

Min

Max

Unit

1

System CLK frequency

Clock high time

Clock low time

0

12.29

9.91

—

ipg_clk

—

MHz

ns

2a

2b

3a

3b

4a

4b

—

ns

Clock fall time

0.5

ns

Clock rise time

—

0.5

ns

Output delay time

Output setup time

—

9.37

—

ns

8.71

ns

1

CL of PWMO = 30 pF

4.7.11 P-ATA Timing Parameters

This section describes the timing parameters of the Parallel ATA module which are compliant with

ATA/ATAPI-5 specification.

Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode

has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 66 Mbyte/s. Parallel ATA

module interface consist of a total of 29 pins, Some pins act on different function in different transfer

mode. There are different requirements of timing relationships among the function pins conform with

ATA/ATAPI-5 specification and these requirements are configurable by the ATA module registers.

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Table 90 and Figure 73 define the AC characteristics of all the P-ATA interface signals on all data

transfer modes.

ATA Interface Signals

SI2

SI1

Figure 73. P-ATA Interface Signals Timing Diagram

Table 90. AC Characteristics of All Interface Signals

ID

Parameter

Symbol

Min

Max

Unit

1

SI1

SI2

SI3

Rising edge slew rate for any signal on ATA interface.

S

—

1.25

20

V/ns

pF

rise

Falling edge slew rate for any signal on ATA interface (see note)

Host interface signal capacitance at the host connector

S

fall

C

host

1

SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal

amplitude with all capacitive loads from 15–40 pF where all signals have the same capacitive load value.

The user needs to use level shifters for 5.0 V compatibility on the ATA interface. The i.MX51 P-ATA

interface is 3.3 V compatible.

The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors

make it difficult to operate the bus at the highest speed (UDMA-4) when bus buffers are used. If fast

UDMA mode operation is needed, this may not be compatible with bus buffers.

Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.

According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with

a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.

When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a

direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus

should drive from host to device. When its low, the bus should drive from device to host. Steering of the

signal is such that contention on the host and device tri-state busses is always avoided.

In the timing equations, some timing parameters are used. These parameters depend on the implementation

of the i.MX51 P-ATA interface on silicon, the bus buffer used, the cable delay and cable skew.

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Table 91 shows ATA timing parameters.

Table 91. P-ATA Timing Parameters

Value/

Contributing Factor

Name

Description

1

T

Bus clock period (ipg_clk_ata)

Peripheral clock frequency

ti_ds

Set-up time ata_data to ata_iordy edge (UDMA-in only)

UDMA0

UDMA1

UDMA2, UDMA3

UDMA4

15 ns

10 ns

7 ns

5 ns

ti_dh

tco

Hold time ata_iordy edge to ata_data (UDMA-in only)

UDMA0, UDMA1, UDMA2, UDMA3, UDMA4

Propagation delay bus clock L-to-H to

5.0 ns

12.0 ns

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data, ata_buffer_en

tsu

tsui

Set-up time ata_data to bus clock L-to-H

Set-up time ata_iordy to bus clock H-to-L

Hold time ata_iordy to bus clock H to L

8.5 ns

2.5 ns

7 ns

thi

tskew1

Max difference in propagation delay bus clock L-to-H to any of following signals

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data (write), ata_buffer_en

tskew2

tskew3

Max difference in buffer propagation delay for any of following signals

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data (write), ata_buffer_en

Transceiver

Max difference in buffer propagation delay for any of following signals ata_iordy,

ata_data (read)

tbuf

Max buffer propagation delay

Transceiver

Cable

tcable1

tcable2

Cable propagation delay for ata_data

Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy,

ata_dmack

Cable

tskew4

tskew5

Max difference in cable propagation delay between ata_iordy and ata_data (read)

Cable

Max difference in cable propagation delay between (ata_dior, ata_diow,

ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)

tskew6

Max difference in cable propagation delay without accounting for ground bounce

Cable

1

Values provided where applicable.

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4.7.11.1 PIO Mode Read Timing

Figure 74 shows timing for PIO read and Table 92 lists the timing parameters for PIO read.

Figure 74. PIO Read Timing Diagram

Table 92. PIO Read Timing Parameters

ATA

Parameter

Controlling

Variable

Value

Parameter from Figure 74

t1

t2

t9

t5

t1

t2r

t9

^{t1 (min) = time_1}× T – (tskew1 + tskew2 + tskew5)

^{t2 min) = time_2r}× T – (tskew1 + tskew2 + tskew5)

^{t9 (min) = time_9}× T – (tskew1 + tskew2 + tskew6)

t5 (min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2

time_1

time_2r

time_3

t5

If not met, increase

time_2

t6

tA

t6

tA

0

—

^{tA (min) = (1.5 + time_ax)}× T – (tco + tsui + tcable2 + tcable2 + 2×tbuf)

time_ax

trd

trd1

trd1 (max) = (–trd) + (tskew3 + tskew4)

time_pio_rdx

^{trd1 (min) = (time_pio_rdx – 0.5)}×T – (tsu + thi)

^{(time_pio_rdx – 0.5)}× T > tsu + thi + tskew3 + tskew4

t0

—

^{t0 (min) = (time_1 + time_2 + time_9)}× T

time_1, time_2r, time_9

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Figure 75 shows timing for PIO write and Table 93 lists the timing parameters for PIO write.

Figure 75. Multi-word DMA (MDMA) Timing

Table 93. PIO Write Timing Parameters

ATA

Parameter

Controlling

Variable

Value

Parameter from Figure 75

t1

t2

t9

t3

t1

t2w

t9

^{t1 (min) = time_1}× T – (tskew1 + tskew2 + tskew5)

^{t2 (min) = time_2w}× T – (tskew1 + tskew2 + tskew5)

^{t9 (min) = time_9}× T – (tskew1 + tskew2 + tskew6)

^{t3 (min) = (time_2w – time_on)}× T – (tskew1 + tskew2 +tskew5)

time_1

time_2w

time_9

—

If not met, increase

time_2w

t4

tA

t0

t4

tA

—

^{t4 (min) = time_4}× T – tskew1

^{tA = (1.5 + time_ax)}× T – (tco + tsui + tcable2 + tcable2 + 2×tbuf)

^{t0(min) = (time_1 + time_2 + time_9)}× T

time_4

time_ax

time_1, time_2r,

time_9

—

Avoid bus contention when switching buffer on by making ton long enough

Avoid bus contention when switching buffer off by making toff long enough

—

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Figure 76 shows timing for MDMA read, Figure 77 shows timing for MDMA write, and Table 94 lists

the timing parameters for MDMA read and write.

Figure 76. MDMA Read Timing Diagram

Figure 77. MDMA Write Timing Diagram

Table 94. MDMA Read and Write Timing Parameters

Parameter

ATA

Parameter

from

Figure 76,

Figure 77

Controlling

Variable

Value

tm, ti

tm

td, td1

tk

^{tm (min) = ti (min) = time_m}× T – (tskew1 + tskew2 + tskew5)

^{td1.(min) = td (min) = time_d}× T – (tskew1 + tskew2 + tskew6)

^{tk.(min) = time_k}× T – (tskew1 + tskew2 + tskew6)

^{t0 (min) = (time_d + time_k)}× T

time_m

time_d

td

tk

time_k

t0

—

time_d, time_k

time_d

tg(read)

tgr

tgr (min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2

tgr.(min-drive) = td – te(drive)

tf(read)

tg(write)

tf(write)

tL

tfr

—

tfr (min-drive) = 0

—

time_d

^{tg (min-write) = time_d}× T – (tskew1 + tskew2 + tskew5)

^{tf (min-write) = time_k}× T – (tskew1 + tskew2 + tskew6)

^{tL (max) = (time_d + time_k–2)}×T – (tsu + tco + 2×tbuf + 2×tcable2)

time_k

time_d, time_k

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Table 94. MDMA Read and Write Timing Parameters (continued)

Parameter

from

Figure 76,

Figure 77

ATA

Parameter

Controlling

Variable

Value

tn, tj

—

tkjn

tn= tj= tkjn = (max(time_k,. time_jn) × T – (tskew1 + tskew2 + tskew6)

time_jn

—

ton

toff

^{ton = time_on}× T – tskew1

^{toff = time_off}× T – tskew1

4.7.11.2 Ultra DMA (UDMA) Input Timing

Figure 78 shows timing when the UDMA in transfer starts, Figure 79 shows timing when the UDMA in

host terminates transfer, Figure 80 shows timing when the UDMA in device terminates transfer, and

Table 95 lists the timing parameters for UDMA in burst.

Figure 78. UDMA In Transfer Starts Timing Diagram

Figure 79. UDMA In Host Terminates Transfer Timing Diagram

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Figure 80. UDMA In Device Terminates Transfer Timing Diagram

Table 95. UDMA In Burst Timing Parameters

Parameter

from

Figure 78,

Figure 79,

Figure 80

ATA

Parameter

Description

Controlling Variable

tack

tenv

tack

tenv

^{tack (min) = (time_ack}× T) – (tskew1 + tskew2)

time_ack

time_env

^{tenv (min) = (time_env}× T) – (tskew1 + tskew2)

^{tenv (max) = (time_env}× T) + (tskew1 + tskew2)

tds

tdh

tds1

tdh1

tc1

tds – (tskew3) – ti_ds > 0

tskew3, ti_ds, ti_dh

should be low enough

tdh – (tskew3) – ti_dh > 0

tcyc

trp

(tcyc – tskew) > T

T big enough

time_rp

trp

^{trp (min) = time_rp}× T – (tskew1 + tskew2 + tskew6)

^(time_rp× T) – (tco + tsu + 3T + 2 ×tbuf + 2×tcable2) > trfs (drive)

^{tmli1 (min) = (time_mlix + 0.4)}× T

^{tzah (min) = (time_zah + 0.4)}× T

^{tdzfs = (time_dzfs}× T) – (tskew1 + tskew2)

^{tcvh = (time_cvh}×T) – (tskew1 + tskew2)

1

—

tx1

time_rp

tmli

tzah

tdzfs

tcvh

—

tmli1

tzah

tdzfs

tcvh

ton

time_mlix

time_zah

time_dzfs

time_cvh

—

^{ton = time_on}× T – tskew1

2

toff

^{toff = time_off}× T – tskew1

1

2

There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last

active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.

Make ton and toff big enough to avoid bus contention.

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4.7.11.3 UDMA Output Timing

Figure 81 shows timing when the UDMA out transfer starts, Figure 82 shows timing when the UDMA out

host terminates transfer, Figure 83 shows timing when the UDMA out device terminates transfer, and

Table 96 lists the timing parameters for UDMA out burst.

Figure 81. UDMA Out Transfer Starts Timing Diagram

Figure 82. UDMA Out Host Terminates Transfer Timing Diagram

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Figure 83. UDMA Out Device Terminates Transfer Timing Diagram

Table 96. UDMA Out Burst Timing Parameters

Parameter

from

Figure 81,

Figure 82,

Figure 83

ATA

Parameter

Controlling

Variable

Value

tack

tenv

tack

tenv

^{tack (min) = (time_ack}× T) – (tskew1 + tskew2)

time_ack

time_env

^{tenv (min) = (time_env}× T) – (tskew1 + tskew2)

^{tenv (max) = (time_env}× T) + (tskew1 + tskew2)

tdvs

tdvh

tcyc

t2cyc

trfs1

—

tdvs

tdvh

tcyc

—

^{tdvs = (time_dvs}× T) – (tskew1 + tskew2)

^{tdvs = (time_dvh}× T) – (tskew1 + tskew2)

^{tcyc = time_cyc}× T – (tskew1 + tskew2)

^{t2cyc = time_cyc}× 2 × T

time_dvs

time_dvh

time_cyc

—

trfs

^{trfs = 1.6}× T + tsui + tco + tbuf + tbuf

^{tdzfs = time_dzfs}× T – (tskew1)

^{tss = time_ss}× T – (tskew1 + tskew2)

^{tdzfs_mli =max (time_dzfs, time_mli)}× T – (tskew1 + tskew2)

tli1 > 0

tdzfs

tss

time_dzfs

time_ss

—

tss

tmli

tli

tdzfs_mli

tli1

—

tli

tli2

tli2 > 0

—

tli

tli3

tli3 > 0

—

tcvh

—

tcvh

^{tcvh = (time_cvh}×T) – (tskew1 + tskew2)

time_cvh

—

ton

toff

^{ton = time_on}× T – tskew1

^{toff = time_off}× T – tskew1

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4.7.12 SIM (Subscriber Identification Module) Timing

This section describes the electrical parameters of the SIM module. Each SIM module interface consists

of 12 signals (two separate ports each containing six signals). Typically a a port uses five signals.

The interface is designed to be used with synchronous SIM cards meaning the SIM module provides the

clock used by the SIM card. The clock frequency is typically 372 times the Tx/Rxdata rate, however the

SIM module can work with CLK frequencies of 16 times the Tx/Rx data rate.

There is no timing relationship between the clock and the data. The clock that the SIM module provides

to the SIM card is used by the SIM card to recover the clock from the data in the same manner as standard

UART data exchanges. All six signals (5 for bi-directional Tx/Rx) of the SIM module are asynchronous to

each other.

There are no required timing relationships between signals in normal mode. The SIM card is initiated by

the interface device; the SIM card responds with Answer to Reset. Although the SIM interface has no

defined requirements, the ISO-7816 defines reset and power-down sequences. (For detailed information,

see ISO-7816.)

Table 97 defines the general timing requirements for the SIM interface.

Table 97. SIM Timing Parameters, High Drive Strength

ID

Parameter

Symbol

Min

Max

Unit

1

SI1

SI2

SI3

SI4

SIM Clock Frequency (SIMx_CLKy) ,

S

0.01

—

25

0.09×(1/S

25

MHz

ns

freq

2

SIM Clock Rise Time (SIMx_CLKy)

)

rise

freq

3

SIM Clock Fall Time (SIMx_CLKy)

S

—

ns

fall

SIM Input Transition Time

S

10

ns

trans

(SIMx_DATAy_RX_TX, SIMx_SIMPDy)

SI5

SIM I/O Rise Time / Fall

Time(SIMx_DATAy_RX_TX)

Tr/Tf

—

1

µs

4

5

SI6

SIM RST Rise Time / Fall Time(SIMx_RSTy)

1

2

3

4

5

50% duty cycle clock

With C = 50 pF

With Cin = 30 pF, Cout = 30 pF

With Cin = 30 pF

1/SI1

SIMx_CLKy

SI3

SI2

Figure 84. SIM Clock Timing Diagram

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Electrical Characteristics

4.7.12.1 Reset Sequence

4.7.12.1.1 Cards with internal reset

The sequence of reset for this kind of SIM Cards is as follows (see Figure 85):

•

After power up, the clock signal is enabled on SIMx_CLKy(time T0)

After 200 clock cycles, RX must be high.

The card must send a response on RX acknowledging the reset between 400 and 40000 clock cycles

after T0.

SIMx_SVENy

SIMx_CLKy

SIMx_DATAy_RX_TX

response

1

2

< 200 clock cycles

1

2

T0

400 clock cycles <

Figure 85. Internal-Reset Card Reset Sequence

< 40000 clock cycles

4.7.12.1.2 Cards with Active Low Reset

The sequence of reset for this kind of card is as follows (see Figure 86):

•

After power-up, the clock signal is enabled on SIMx_CLKy (time T0)

After 200 clock cycles, SIMx_DATAy_RX_TX must be high.

SIMx_RSTy must remain Low for at least 40000 clock cycles after T0 (no response is to be

received on RX during those 40000 clock cycles)

•

SIMx_RSTy is set High (time T1)

SIMx_RSTy must remain High for at least 40000 clock cycles after T1 and a response must be

received on SIMx_DATAy_RX_TX between 400 and 40000 clock cycles after T1.

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Electrical Characteristics

SIMx_SVENy

SIMx_RSTy

SIMx_CLKy

SIMx_DATAy_RX_TX

response

2

1

3

T0

T1

< 200 clock cycles

1

2

3

400 clock cycles <

< 40000 clock cycles

400000 clock cycles <

Figure 86. Active-Low-Reset Cards Reset Sequence

4.7.12.2 Power Down Sequence

Power down sequence for SIM interface is as follows:

•

SIMx_SIMPDy port detects the removal of the SIM Card

SIMx_RSTy goes Low

SIMx_CLKy goes Low

SIMx_DATAy_RX_TX goes Low

SIMx_SVENy goes Low

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Electrical Characteristics

Each of these steps is done in one CKIL period (usually 32 kHz). Power-down can be started because of

a SIM Card removal detection or launched by the processor. Figure 87 and Table 98 shows the usual

timing requirements for this sequence, with Fckil = CKIL frequency value.

SI10

SIMx_SIMPDy

SIMx_RSTy

SI7

SIMx_CLKy

SI8

SIMx_DATAy_RX_TX

SI9

SIMx_SVENy

Figure 87. SmartCard Interface Power Down AC Timing

Table 98. Timing Requirements for Power Down Sequence

ID

Parameter

Symbol

Min

Max

Unit

SI7

SI8

SI9

SIM reset to SIM clock stop

S

0.9×1/Fckil

1.8×1/Fckil

2.7×1/Fckil

0.9×1/Fckil

1.1×1/Fckil

2.2×1/Fckil

3.3×1/Fckil

1.1×1/Fckil

ns

rst2clk

SIM reset to SIM TX data low

SIM reset to SIM voltage enable low

S

rst2dat

S

rst2ven

SI10 SIM presence detect to SIM reset low

S

pd2rst

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4.7.13 SCAN JTAG Controller (SJC) Timing Parameters

Figure 88 depicts the SJC test clock input timing. Figure 89 depicts the SJC boundary scan timing.

Figure 91 depicts the TRST timing with respect to TCK. Figure 90 depicts the SJC test access port. Signal

parameters are listed in Table 99.

SJ1

SJ2

VM

SJ2

VM

TCK

(Input)

VIH

VIL

SJ3

Figure 88. Test Clock Input Timing Diagram

TCK

(Input)

VIH

SJ5

Input Data Valid

VIL

SJ4

Data

Inputs

SJ6

Data

Outputs

Output Data Valid

SJ7

SJ6

Data

Outputs

Data

Outputs

Output Data Valid

Figure 89. Boundary Scan (JTAG) Timing Diagram

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Electrical Characteristics

TCK

(Input)

VIH

SJ9

VIL

SJ8

Input Data Valid

TDI

TMS

(Input)

SJ10

SJ11

SJ10

TDO

Output Data Valid

(Output)

TDO

(Output)

TDO

(Output)

Output Data Valid

Figure 90. Test Access Port Timing Diagram

TCK

(Input)

SJ13

TRST

(Input)

SJ12

Figure 91. TRST Timing Diagram

Table 99. JTAG Timing

All Frequencies

1,2

ID

Parameter

Unit

Min

Max

1

SJ0

SJ1

SJ2

SJ3

SJ4

SJ5

SJ6

SJ7

SJ8

TCK frequency of operation 1/(3•T

TCK cycle time in crystal mode

)

0.001

45

22.5

—

22

—

3

MHz

ns

DC

2

TCK clock pulse width measured at V_M

TCK rise and fall times

ns

Boundary scan input data set-up time

Boundary scan input data hold time

TCK low to output data valid

5

—

40

—

ns

24

—

ns

TCK low to output high impedance

TMS, TDI data set-up time

—

ns

5

ns

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Table 99. JTAG Timing (continued)

All Frequencies

1,2

ID

Parameter

Unit

Min

Max

SJ9

TMS, TDI data hold time

25

—

44

—

ns

SJ10 TCK low to TDO data valid

SJ11 TCK low to TDO high impedance

SJ12 TRST assert time

—

100

40

SJ13 TRST set-up time to TCK low

1

2

T

= target frequency of SJC

= mid-point voltage

DC

V

M

4.7.14 SPDIF Timing Parameters

Table 100 shows the timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF).

Table 100. SPDIF Timing

All Frequencies

Characteristics

Symbol

Unit

Min

Max

SPDIFOUT output (load = 50 pF)

• Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

ns

SPDIFOUT output (load = 30 pF)

• Skew

• Transition rising

• Transition falling

—

1.5

13.6

18.0

4.7.15 SSI Timing Parameters

This section describes the timing parameters of the SSI module. The connectivity of the serial synchronous

interfaces is summarized in Table 101.

Table 101. AUDMUX Port Allocation

Port

Signal Nomenclature

Type and Access

AUDMUX port 1

AUDMUX port 2

AUDMUX port 3

AUDMUX port 4

AUDMUX port 5

SSI 1

SSI 2

AUD3

AUD4

AUD5

Internal

External—AUD3 I/O

External—EIM or CSPI1 I/O via IOMUX

External—EIM or SD1 I/O via IOMUX

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Electrical Characteristics

Port

Table 101. AUDMUX Port Allocation (continued)

Signal Nomenclature

Type and Access

AUDMUX port 6

AUDMUX port 7

AUD6

SSI 3

External—EIM or DISP2 via IOMUX

Internal

NOTE

•

The terms WL and BL used in the timing diagrams and tables refer to

Word Length (WL) and Bit Length (BL).

The SSI timing diagrams use generic signal names wherein the names

used in the i.MX51 Multimedia Applications Processor Reference

Manual (MCIMX51RM) are channel specific signal names. For

example, a channel clock referenced in the IOMUXC chapter as

AUD3_TXC appears in the timing diagram as TXC.

4.7.15.1 SSI Transmitter Timing with Internal Clock

Figure 92 depicts the SSI transmitter internal clock timing and Table 102 lists the timing parameters for

the SSI transmitter internal clock.

.

SS1

SS5

SS4

SS3

SS2

TXC

(Output)

SS8

SS6

TXFS (bl)

(Output)

SS10

SS12

SS14

SS17

TXFS (wl)

(Output)

SS15

SS16

SS18

TXD

(Output)

SS43

SS42

SS19

RXD

(Input)

Note: SRXD input in synchronous mode only

Figure 92. SSI Transmitter Internal Clock Timing Diagram

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Electrical Characteristics

Table 102. SSI Transmitter Timing with Internal Clock

ID

Parameter

Internal Clock Operation

Min

Max

Unit

SS1

SS2

(Tx/Rx) CK clock period

81.4

36.0

—

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Tx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

(Tx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

(Tx/Rx) Internal FS rise time

(Tx/Rx) Internal FS fall time

SS3

6.0

SS4

36.0

—

SS5

6.0

SS6

—

15.0

6.0

SS8

—

SS10

SS12

SS14

SS15

SS16

SS17

SS18

SS19

—

6.0

(Tx) CK high to STXD valid from high impedance

(Tx) CK high to STXD high/low

—

15.0

6.0

—

(Tx) CK high to STXD high impedance

STXD rise/fall time

—

Synchronous Internal Clock Operation

SS42

SS43

SS52

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

Loading

30

0.0

—

ns

pF

25.0

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables

and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

”Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

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Electrical Characteristics

4.7.15.2 SSI Receiver Timing with Internal Clock

Figure 93 depicts the SSI receiver internal clock timing and Table 103 lists the timing parameters for the

SSI receiver internal clock.

SS1

SS3

SS5

SS4

SS2

TXC

(Output)

SS9

SS7

TXFS (bl)

(Output)

SS11

SS13

TXFS (wl)

(Output)

SS20

SS21

RXD

(Input)

SS51

SS50

SS47

SS49

SS48

RXC

(Output)

Figure 93. SSI Receiver Internal Clock Timing Diagram

Table 103. SSI Receiver Timing with Internal Clock

ID

Parameter

Internal Clock Operation

Min

Max

Unit

SS1

SS2

(Tx/Rx) CK clock period

81.4

36.0

—

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Rx) CK high to FS (bl) high

(Rx) CK high to FS (bl) low

(Rx) CK high to FS (wl) high

(Rx) CK high to FS (wl) low

SS3

6.0

—

SS4

36.0

—

SS5

6.0

15.0

—

SS7

—

SS9

—

SS11

SS13

SS20

SS21

—

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

30

0.0

—

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Electrical Characteristics

Table 103. SSI Receiver Timing with Internal Clock (continued)

ID

Parameter

Min

Max

Unit

Oversampling Clock Operation

SS47

SS48

SS49

SS50

SS51

Oversampling clock period

15.04

6.0

—

ns

Oversampling clock high period

Oversampling clock rise time

Oversampling clock low period

Oversampling clock fall time

3.0

—

6.0

—

3.0

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables

and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

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Electrical Characteristics

4.7.15.3 SSI Transmitter Timing with External Clock

Figure 94 depicts the SSI transmitter external clock timing and Table 104 lists the timing parameters for

the SSI transmitter external clock.

SS22

SS23

SS25

SS26

SS24

TXC

(Input)

SS27

SS29

TXFS (bl)

(Input)

SS33

SS31

TXFS (wl)

(Input)

SS39

SS37

SS38

TXD

(Output)

SS45

SS44

RXD

(Input)

SS46

Note: SRXD Input in Synchronous mode only

Figure 94. SSI Transmitter External Clock Timing Diagram

Table 104. SSI Transmitter Timing with External Clock

ID

Parameter

External Clock Operation

Min

Max

Unit

SS22

SS23

SS24

SS25

SS26

SS27

SS29

SS31

SS33

SS37

SS38

(Tx/Rx) CK clock period

81.4

36.0

—

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Tx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

(Tx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

—

6.0

—

36.0

—

6.0

15.0

—

–10.0

10.0

–10.0

10.0

—

15.0

—

(Tx) CK high to STXD valid from high impedance

(Tx) CK high to STXD high/low

15.0

30

—

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Electrical Characteristics

Table 104. SSI Transmitter Timing with External Clock (continued)

ID

Parameter

Min

Max

Unit

SS39

(Tx) CK high to STXD high impedance

—

15.0

ns

Synchronous External Clock Operation

SS44

SS45

SS46

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

SRXD rise/fall time

10.0

2.0

—

ns

6.0

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables

and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

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Electrical Characteristics

4.7.15.4 SSI Receiver Timing with External Clock

Figure 95 depicts the SSI receiver external clock timing and Table 105 lists the timing parameters for the

SSI receiver external clock.

SS22

SS26

SS25

SS24

SS23

TXC

(Input)

SS30

SS28

TXFS (bl)

(Input)

SS32

SS35

SS34

TXFS (wl)

(Input)

SS41

SS36

SS40

RXD

(Input)

Figure 95. SSI Receiver External Clock Timing Diagram

Table 105. SSI Receiver Timing with External Clock

ID

Parameter

External Clock Operation

Min

Max

Unit

SS22

SS23

SS24

SS25

SS26

SS28

SS30

SS32

SS34

SS35

SS36

SS40

SS41

(Tx/Rx) CK clock period

81.4

36

—

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Rx) CK high to FS (bl) high

(Rx) CK high to FS (bl) low

(Rx) CK high to FS (wl) high

(Rx) CK high to FS (wl) low

(Tx/Rx) External FS rise time

(Tx/Rx) External FS fall time

6.0

—

36

—

6.0

15.0

—

–10

10

–10

10

—

15.0

—

6.0

—

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

10

2

—

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Electrical Characteristics

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables

and in the figures.

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

4.7.16 UART

Table 106 shows the UART I/O configuration based on which mode is enabled.

Table 106. UART I/O Configuration vs. Mode

DTE Mode

Description

DCE Mode

Port

Direction

Description

RTS

CTS

Output

Input

RTS from DTE to DCE

CTS from DCE to DTE

DTR from DTE to DCE

DSR from DCE to DTE

DCD from DCE to DTE

RING from DCE to DTE

Serial data from DCE to DTE

Serial data from DTE to DCE

Input

Output

Input

RTS from DTE to DCE

CTS from DCE to DTE

DTR from DTE to DCE

DSR from DCE to DTE

DCD from DCE to DTE

RING from DCE to DTE

Serial data from DCE to DTE

Serial data from DTE to DCE

DTR

Output

Input

DSR

Output

Input

DCD

Input

RI

Input

TXD_MUX

RXD_MUX

Input

Output

4.7.16.1 UART Electrical

This section describes the electrical information of the UART module.

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Electrical Characteristics

4.7.16.1.1 UART RS-232 Serial Mode Timing

UART Transmitter

Figure 96 depicts the transmit timing of UART in RS-232 serial mode, with 8 data bit/1 stop bit format.

Table 107 lists the UART RS-232 serial mode transmit timing characteristics.

Figure 96. UART RS-232 Serial Mode Transmit Timing Diagram

Table 107. UART RS-232 Serial Mode Transmit Timing Diagram

ID

Parameter

Symbol

Min

Max

+T

Units

1

2

UA1

Transmit Bit Time

t

1/F

-T

1/F

—

Tbit

baud_rate

ref_clk

baud_rate ref_clk

1

2

1/F

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

baud_rate

T

: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

ref_clk

UART Receiver

Figure 97 depicts the RS-232 serial mode receive timing, with 8 data bit/1 stop bit format. Table 108 lists

serial mode receive timing characteristics.

Figure 97. UART RS-232 Serial Mode Receive Timing Diagram

Table 108. UART RS-232 Serial Mode Transmit Timing Diagram

ID

Parameter

Symbol

Min

Max

Units

1

2

UA1

Receive Bit Time

t

1/F

-1/(16×F

)

1/F

+1/(16×F )

baud_rate

—

Rbit

baud_rate

1

2

The UART receiver can tolerate 1/(16×Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must

not exceed 3/(16×Fbaud_rate).

F

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

baud_rate

4.7.16.1.2 UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode.

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UART IrDA Mode Transmitter

Figure 98 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 109 lists

the transmit timing characteristics.

Figure 98. UART IrDA Mode Transmit Timing Diagram

Table 109. IrDA Mode Transmit Timing Parameters

ID

Parameter

Symbol

Min

Max

+T

Units

1

2

UA3

Transmit Bit Time in

IrDA mode

t

1/F

-T

1/F

—

TIRbit

baud_rate

ref_clk

baud_rate ref_clk

UA4

Transmit IR Pulse

Duration

t

(3/16)×(1F

)-T

(3/16)×(1F

)+T

ref_clk

—

TIRpulse

baud_rate ref_clk

baud_rate

1

2

F

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

baud_rate

Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

UART IrDA Mode Receiver

Figure 99 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 110 lists

the receive timing characteristics.

Figure 99. UART IrDA Mode Receive Timing Diagram

Table 110. IrDA Mode Receive Timing Parameters

ID

Parameter

Symbol

Min

Max

Units

1

2

UA5

Receive Bit Time in

IrDA mode

t

1/F

1/(16×F

-

1/F

1/(16×F

+

—

RIRbit

baud_rate

)

baud_rate

UA6

Receive IR Pulse

Duration

t

1.41 us

(5/16)×(1/F

)

—

RIRpulse

baud_rate

1

The UART receiver can tolerate 1/(16×F

) tolerance in each bit. But accumulation tolerance in one frame must

baud_rate

not exceed 3/(16×F

).

baud_rate

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2

Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

4.7.17 USBOH3 Parameters

This section describes the electrical parameters of the USB OTG port and USB HOST ports. For on-chip

USB PHY parameters see Section 4.7.19, “USB PHY Parameters.”

4.7.17.1 USB Serial Interface

In order to support four serial different interfaces, the USB serial transceiver can be configured to operate

in one of four modes:

•

DAT_SE0 bidirectional, 3-wire mode

DAT_SE0 unidirectional, 6-wire mode

VP_VM bidirectional, 4-wire mode

VP_VM unidirectional, 6-wire mode

The USB controller does not support ULPI Serial mode. Only the legacy serial mode is supported.

Table 111 shows the serial mode signal map for 6-pin Full speed/Low speed (FsLs) serial mode.

Table 112 shows the serial mode signal map for 3-pin FsLs serial mode.

Table 111. Serial Mode Signal Map for 6-pin FsLs Serial Mode

Signal

Maps to

Direction

Description

tx_enable

tx_dat

tx_se0

int

data(0)

data(1)

data(2)

data(3)

In

Active high transmit enable

Transmit differential data on D+/D–

Transmit single-ended zero on D+/D–

In

Out

Active high interrupt indication

Must be asserted whenever any unmasked interrupt occurs

rx_dp

rx_dm

data(4)

data(5)

data(6)

data(7)

Out

Single-ended receive data from D+

Single-ended receive data from D–

Differential receive data from D+/D–

Reserved The PHY must drive this signal low

rx_rcv

Reserved

Table 112. Serial Mode Signal Map for 3-pin FsLs Serial Mode

Signal

Maps to

Direction

Description

tx_enable

dat

data(0)

data(1)

In

Active high transmit enable

I/O

Transmit differential data on D+/D– when tx_enable is high

Receive differential data on D+/D– when tx_enable is low

se0

int

data(2)

data(3)

I/O

Transmit single-ended zero on D+/D– when tx_enable is high

Receive single-ended zero on D+/D– when tx_enable is low

Out

Active high interrupt indication

Must be asserted whenever any unmasked interrupt occurs

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4.7.17.1.1 USB DAT_SE0 Bi-Directional Mode

Table 113 shows the signal definitions in DAT_SE0 bi-directional mode and Figure 100 shows the USB

transmit waveform in DAT_SE0 bi-directional mode.

Table 113. Signal Definitions—DAT_SE0 Bi-Directional Mode

Name

Direction

Signal Description

Transmit enable, active low

USB_TXOE_B

USB_DAT_VP

Out

In

TX data when USB_TXOE_B is low

Differential RX data when USB_TXOE_B is high

USB_SE0_VM

Out

In

SE0 drive when USB_TXOE_B is low

SE0 RX indicator when USB_TXOE_B is high

Transmit

US3

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US1

US4

US2

Figure 100. USB Transmit Waveform in DAT_SE0 Bi-Directional Mode

Figure 101 shows the USB receive waveform in DAT_SE0 bi-directional mode and Table 114 shows the

definitions of USB receive waveform in DAT_SE0 bi-directional mode.

Receive

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US7

US8

USB_SE0_VM

Figure 101. USB Receive Waveform in DAT_SE0 Bi-Directional Mode

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Electrical Characteristics

Table 114. Definitions of USB Receive Waveform in DAT_SE0 Bi-Directional Mode

Conditions/

Reference Signal

ID

Parameter

Signal Name

Direction

Min

Max

Unit

US1

US2

US3

US4

US7

US8

TX Rise/Fall Time

TX Duty Cycle

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Out

In

—

5.0

ns

%

50 pF

—

49.0

—

51.0

3.0

RX Rise/Fall Time

ns

35 pF

In

—

4.7.17.1.2 USB DAT_SE0 Unidirectional Mode

Table 115 shows the signal definitions in DAT_SE0 unidirectional mode

Table 115. Signal Definitions—DAT_SE0 Unidirectional Mode

Name

Direction

Signal Description

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

Out

In

Transmit enable, active low

TX data when USB_TXOE_B is low

SE0 drive when USB_TXOE_B is low

Buffered data on DP when USB_TXOE_B is high

Buffered data on DM when USB_TXOE_B is high

Differential RX data when USB_TXOE_B is high

USB_VM1

In

USB_RCV

In

Figure 102 and Figure 103 shows the USB transmit/receive waveform in DAT_SE0 uni-directional mode

respectively.

US11

Transmit

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US9

US12

US10

Figure 102. USB Transmit Waveform in DAT_SE0 Uni-directional Mode

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Electrical Characteristics

Receive

USB_TXOE_B

USB_DAT_VP

USB_RCV

US16

US15/US17

USB_SE0_VM

Figure 103. USB Receive Waveform in DAT_SE0 Uni-directional Mode

Table 116 shows the USB port timing specification in DAT_SE0 uni-directional mode.

Table 116. USB Port Timing Specification in DAT_SE0 Uni-Directional Mode

Signal

Source

Condition/

Reference Signal

ID

Parameter

Signal Name

Min

Max

Unit

US9 TX Rise/Fall Time

US10 TX Rise/Fall Time

US11 TX Rise/Fall Time

US12 TX Duty Cycle

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_VP1

Out

In

—

5.0

51.0

3.0

ns

%

50 pF

—

49.0

—

US15 RX Rise/Fall Time

US16 RX Rise/Fall Time

US17 RX Rise/Fall Time

ns

35 pF

USB_VM1

In

—

USB_RCV

In

—

4.7.17.1.3 USB VP_VM Bi-Directional Mode

Table 117 shows the signal definitions in VP_VM bi-directional mode. Figure 104 and Figure 105 shows

the USB transmit/receive waveform in VP_VM bi-directional mode respectively.

Table 117. Signal Definitions—VP_VM Bi-Directional Mode

Name

Direction

Signal Description

Transmit enable, active low

USB_TXOE_B

USB_DAT_VP

Out

Out (Tx)

In (Rx)

TX VP data when USB_TXOE_B is low

RX VP data when USB_TXOE_B is high

USB_SE0_VM

USB_RCV

Out (Tx)

In (Rx)

TX VM data when USB_TXOE_B low

RX VM data when USB_TXOE_B high

In

Differential RX data

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Transmit

US20

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US18

US21

US19

US22

Figure 104. USB Transmit Waveform in VP_VM Bi-Directional Mode

Receive

US26

USB_DAT_VP

USB_SE0_VM

USB_RCV

US27

US28

US29

Figure 105. USB Receive Waveform in VP_VM Bi-Directional Mode

Table 118 shows the USB port timing specification in VP_VM bi-directional mode.

Table 118. USB Port Timing Specification in VP_VM Bi-directional Mode

ID

Parameter

Signal Name

Direction Min Max Unit

Condition/Reference Signal

US18 TX Rise/Fall Time

US19 TX Rise/Fall Time

US20 TX Rise/Fall Time

US21 TX Duty Cycle

US22 TX Overlap

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Out

—

5.0

ns

%

50 pF

49.0 51.0

–3.0 3.0

—

ns

USB_DAT_VP

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Table 118. USB Port Timing Specification in VP_VM Bi-directional Mode (continued)

ID

Parameter

Signal Name

Direction Min Max Unit

Condition/Reference Signal

US26 RX Rise/Fall Time

US27 RX Rise/Fall Time

US28 RX Skew

USB_DAT_VP

USB_SE0_VM

USB_DAT_VP

USB_RCV

In

—

3.0

ns

35 pF

–4.0 4.0

–6.0 2.0

USB_SE0_VM

USB_DAT_VP

US29 RX Skew

4.7.17.1.4 USB VP_VM Uni-Directional Mode

Table 119 shows the signal definitions in VP_VM uni-directional mode. Figure 106 and Figure 107

shows the USB transmit/receive waveform in VP_VM uni-directional mode respectively.

Table 119. USB Signal Definitions—VP_VM Uni-Directional Mode

Name

Direction

Signal Description

Transmit enable, active low

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

Out

In

TX VP data when USB_TXOE_B is low

TX VM data when USB_TXOE_B is low

RX VP data when USB_TXOE_B is high

RX VM data when USB_TXOE_B is high

Differential RX data

USB_VM1

In

USB_RCV

In

Transmit

US32

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US30

US33

US31

US34

Figure 106. USB Transmit Waveform in VP_VM Unidirectional Mode

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Electrical Characteristics

Receive

USB_TXOE_B

USB_VP1

US38

USB_VM1

USB_RCV

US40

US39

US41

Figure 107. USB Receive Waveform in VP_VM Uni-directional Mode

Table 120 shows the USB port timing specification in VP_VM uni-directional mode.

Table 120. USB Timing Specification in VP_VM Unidirectional Mode

ID

Parameter

Signal

Direction

Min Max Unit

Conditions / Reference Signal

US30 TX Rise/Fall Time

US31 TX Rise/Fall Time

US32 TX Rise/Fall Time

US33 TX Duty Cycle

US34 TX Overlap

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

Out

In

—

5.0

ns

%

50 pF

49.0 51.0

—

–3.0

—

3.0

4.0

2.0

ns

USB_DAT_VP

35 pF

US38 RX Rise/Fall Time

US39 RX Rise/Fall Time

US40 RX Skew

USB_VM1

In

—

35 pF

USB_VP1

In

–4.0

–6.0

USB_VM1

USB_VP1

US41 RX Skew

USB_RCV

In

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4.7.18 USB Parallel Interface Timing

Electrical and timing specifications of Parallel Interface are presented in the subsequent sections.

Table 121 shows the signal definitions in parallel mode. Figure 108 shows the USB transmit/receive

waveform in parallel mode. Table 122 shows the USB timing specification for ULPI parallel mode.

Table 121. Signal Definitions—Parallel Interface (Normal ULPI)

Name

Direction

Signal Description

USB_Clk

In

Interface clock. All interface signals are synchronous to Clock.

USB_Data[7:0]

I/O

Bi-directional data bus, driven low by the link during idle. Bus

ownership is determined by Dir.

USB_Dir

USB_Stp

In

Direction. Control the direction of the Data bus.

Out

Stop. The link asserts this signal for 1 clock cycle to stop the data

stream currently on the bus.

USB_Nxt

In

Next. The PHY asserts this signal to throttle the data.

USB_Clk

US15

US16

USB_Dir/Nxt

US15

US16

USB_Data

USB_Stp

US17

Figure 108. USB Transmit/Receive Waveform in Parallel Mode

Table 122. USB Timing Specification for ULPI Parallel Mode

Conditions/

Reference Signal

ID

Parameter

Min

Max

Unit

US15 Setup Time (Dir, Nxt in, Data in)

US16 Hold Time (Dir, Nxt in, Data in)

6

0

—

9

ns

10 pF

1

US17 Output delay Time (Stp out, Data out) for H3 routed to DISP2 I/O

and H1

—

US17 Output delay Time (Stp out, Data out) for H2

—

11

ns

10 pF

1

H3 routed to NANDF I/O is recommended for Full and Low-Speed use only.

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4.7.19 USB PHY Parameters

This section describes the USB PHY parameters.

4.7.19.1 USB PHY AC Parameters

Table 123 lists the AC timing parameters for USB PHY.

Table 123. USB PHY AC Timing Parameters

Parameter

Conditions

Min

Typ

Max

Unit

trise

1.5 Mbps

12 Mbps

480 Mbps

75

4

0.5

—

300

20

ns

tfall

1.5 Mbps

12 Mbps

480 Mbps

75

4

0.5

—

300

20

ns

Jitter

1.5 Mbps

12 Mbps

480 Mbps

—

10

1

0.2

4.7.19.2 USB PHY Additional Electrical Parameters

Table 124 lists the parameters for additional electrical characteristics for USB PHY.

Table 124. Additional Electrical Characteristics for USB PHY

Parameter

Conditions

HS Mode

Min

Typ

Max

Unit

Vcm DC

–0.05

0.8

—

0.5

2.5

V

(dc level measured at receiver connector)

LS/FS Mode

Crossover Voltage

LS Mode

FS Mode

1.3

—

0

2

V

Power supply ripple noise

(analog 3.3 V)

<160 MHz

–50

50

mV

Power supply ripple noise

(analog 2.5 V)

<1.2 MHz

>1.2 MHz

–10

–50

0

10

50

Power supply ripple noise

(Digital 1.2)

All conditions

–50

0

50

4.7.19.3 USB PHY System Clocking (SYSCLK)

Table 125 lists the USB PHY system clocking parameters.

Table 125. USB PHY System Clocking Parameters

Parameter

Conditions

Min

Typ

Max

Unit

Clock deviation

Rise/fall time

—

–150

—

150

200

ppm

ps

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Package Information and Contact Assignments

Table 125. USB PHY System Clocking Parameters (continued)

Parameter

Conditions

Min

Typ

Max

Unit

Jitter (peak-peak)

Duty-cycle

<1.2 MHz

>1.2 MHz

—

0

—

50

100

60

ps

%

40

4.7.19.4 USB PHY Voltage Thresholds

Table 126 lists the USB PHY voltage thresholds.

Table 126. VBUS Comparators Thresholds

Parameter

Conditions

Min

Typ

Max

Unit

A-Device Session Valid

—

0.8

0.2

4.4

1.4

2.0

4.0

V

B-Device Session Valid

B-Device Session End

0.45

4.6

0.8

1

VBUS Valid Comparator Threshold

4.75

1

For VBUS maximum rating, see Table 11 on page 17

5 Package Information and Contact Assignments

This section includes the contact assignment information and mechanical package drawing.

5.1

19 x 19 mm Package Information

This section contains the outline drawing, signal assignment map, ground/power/reference ID (by ball grid

location) for the 19 × 19 mm, 0.8 mm pitch package.

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Package Information and Contact Assignments

5.1.1

BGA—Case 2017, 19 x 19 mm, 0.8 mm Pitch

Figure 109 shows the top view, bottom view, and side view of the 19 ×19 mm package.

Figure 109. 19 x 19 mm Package: Case 2017-01—0.8 mm Pitch

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Package Information and Contact Assignments

5.1.1.1

19 x 19 mm Package Drawing Notes

The following notes apply to Figure 109.

1

All dimensions in millimeters.

2

Dimensioning and tolerancing per ASME Y14.5M-1994.

3

Maximum solder ball diameter measured parallel to Datum A.

4

Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

Parallelism measurement shall exclude any effect of mark on top surface of package.

5

5.1.2

19 x 19 mm Signal Assignments, Power Rails, and I/O

Table 127 shows the device connection list and Table 128 displays an alpha-sorted list of the signal

assignments including associated power supplies.

5.1.2.1

19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments

Table 127 shows the device connection list for ground, power, sense, and reference contact signals

alpha-sorted by name.

Table 127. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments

Contact Name

Contact Assignment

AHVDDRGB

AHVSSRGB

GND

Y18, AA18

Y19, AA19

A1, A23, G5, H9, J8, J9, J10, J12, J13, J14, K8, K9, K10, K11, K12, K13, K14, L8, L9, L10, L11,L12,

L13, L14, M9, M10, M11, M12, M13, M14, M15, N8, N9, N10, N11, N12, N13, N14, N15, N16, P8,

P9, P10, P11, P12, P13, P14, P15, R8, R9, R10, R11,R12, R13, R14, R15, R16, T5, T16, AC1,

AC21, AC23

GND_ANA_PLL_A

GND_ANA_PLL_B

GND_DIG_PLL_A

GND_DIG_PLL_B

NGND_OSC

U7

U17

T7

V18

V17

NGND_TV_BACK

NGND_USBPHY

NVCC_EMI

T15

L16

U8, U9, U10, U11, U12, V7

NVCC_EMI_DRAM

NVCC_HS10

H6, J6, K6, L6, M6, N6, P6, R6, T6

M16

M18

N18

M17

T14

NVCC_HS4_1

NVCC_HS4_2

NVCC_HS6

NVCC_I2C

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Table 127. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments (continued)

Contact Name

Contact Assignment

NVCC_IPU2

NVCC_IPU4

NVCC_IPU5

NVCC_IPU6

NVCC_IPU7

NVCC_IPU8

NVCC_IPU9

NVCC_NANDF_A

NVCC_NANDF_B

NVCC_NANDF_C

NVCC_OSC

NVCC_PER3

NVCC_PER5

NVCC_PER8

NVCC_PER9

NVCC_PER10

NVCC_PER11

NVCC_PER12

NVCC_PER13

NVCC_PER14

NVCC_PER15

NVCC_PER17

NVCC_SRTC_POW

NVCC_TV_BACK

NVCC_USBPHY

RREFEXT

T18

G16

H17

J17

K17

P18

R18

E6, F5

G9

G10

W17

U18

G15

H16

H10

H11

G11

G12

G13

U13

H15

G14

U14

U16

L17

K19

J11

SGND

SVCC

H14

F13

V16

K20

SVDDGP

TVDAC_DHVDD

VBUS

VCC

H13, J15, J16, K15, K16, L7, L15, M7, N7, N17, P7, P17, R17, T8, T9, T10, T11, T12, T17

V6

VDD_ANA_PLL_A

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Package Information and Contact Assignments

Table 127. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments (continued)

Contact Name

Contact Assignment

VDD_ANA_PLL_B

VDD_DIG_PLL_A

VDD_DIG_PLL_B

VDD_FUSE

VDDA

W19

U6

W18

R7

G8, H8, H12, M8, P16, T13

L18

VDDA33

VDDGP

F6, F7, F8, F9, F10, F11, F12, G6, G7, H7, J7, K7

VREFOUT

VREF

U15

R5

VREG

K21

5.1.2.2

19 x 19 mm, Signal Assignments, Power Rails, and I/O

Table 128 displays an alpha-sorted list of the signal assignments including power rails.

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O

Contact

Assignment

Direction after

Configuraton

after Reset

Contact Name

Power Rail

I/O Buffer Type

1

Reset

AUD3_BB_CK

AUD3_BB_FS

AUD3_BB_RXD

AUD3_BB_TXD

BOOT_MODE0

BOOT_MODE1

CKIH1

C8

A9

NVCC_PER9

NVCC_PER3

NVCC_SRTC_POW

NVCC_PER3

AHVDDRGB

NVCC_HS10

GPIO

Input

Keeper

B9

GPIO

Keeper

E9

GPIO

Keeper

AB21

AB22

V19

AA20

Y16

AA21

Y17

R22

R23

P22

P23

M20

LVIO

100 kΩ pull-up

Analog

LVIO

Analog

GPIO

CKIH2

Analog

CKIL

Standard CMOS

100 kΩ pull-up

Analog

CLK_SS

LVIO

2

COMP

Analog

HSGPIO

CSI1_D10

CSI1_D11

CSI1_D12

CSI1_D13

CSI1_D14

Keeper

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Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

Direction after

Configuraton

after Reset

Contact Name

Power Rail

I/O Buffer Type

1

Reset

CSI1_D15

CSI1_D16

CSI1_D17

CSI1_D18

CSI1_D19

CSI1_D8

M21

N22

N23

M22

M23

E18

A21

A20

B20

F18

G18

B8

NVCC_HS10

NVCC_PER8

NVCC_PER9

NVCC_HS4_1

NVCC_PER9

NVCC_PER8

NVCC_PER10

NVCC_IPU6

NVCC_IPU7

HSGPIO

GPIO

Input

Keeper

CSI1_D9

GPIO

Keeper

CSI1_HSYNC

CSI1_MCLK

CSI1_PIXCLK

CSI1_VSYNC

CSI2_D12

CSI2_D13

CSI2_D14

CSI2_D15

CSI2_D16

CSI2_D17

CSI2_D18

CSI2_D19

CSI2_HSYNC

CSI2_PIXCLK

CSI2_VSYNC

CSPI1_MISO

CSPI1_MOSI

CSPI1_RDY

CSPI1_SCLK

CSPI1_SS0

CSPI1_SS1

DI_GP1

GPIO

Keeper

GPIO

Keeper

GPIO

Keeper

GPIO

Keeper

GPIO

Keeper

C7

GPIO

Keeper

L20

L21

L22

L23

D9

HSGPIO

GPIO

Keeper

A8

GPIO

Keeper

C18

E19

F19

C10

D10

C9

GPIO

Keeper

GPIO

Keeper

GPIO

Keeper

GPIO

100 kΩ pull-up

Keeper

GPIO

A10

E10

B10

H21

J19

H22

J22

GPIO

100 kΩ pull-up

Keeper

GPIO

DI_GP2

GPIO

Keeper

DI_GP3

GPIO

100 kΩ pull-up

DI_GP4

GPIO

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Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

Direction after

Configuraton

after Reset

Contact Name

Power Rail

I/O Buffer Type

1

Reset

DI1_D0_CS

DI1_D1_CS

DI1_DISP_CLK

DI1_PIN11

DI1_PIN12

DI1_PIN13

DI1_PIN15

DI1_PIN2

U21

AB23

J18

NVCC_IPU2

NVCC_IPU6

NVCC_IPU2

NVCC_IPU6

NVCC_IPU7

NVCC_HS6

NVCC_IPU4

NVCC_IPU5

NVCC_HS6

NVCC_IPU5

NVCC_HS6

GPIO

HSGPIO

GPIO

HSGPIO

GPIO

HSGPIO

Output

Input

High

Low

Y22

AA22

T20

H20

G23

G22

J21

High

DI1_PIN3

High

DI2_DISP_CLK

DI2_PIN2

High

J20

High

DI2_PIN3

K18

H23

N20

N21

D22

D23

E21

F20

E22

G19

E23

F21

G20

H18

U22

F23

H19

F22

G21

U23

T22

High

DI2_PIN4

Keeper

DISP1_DAT0

DISP1_DAT1

Input

3

DISP1_DAT10

Input

3

DISP1_DAT11

Input

3

DISP1_DAT12

Input

3

DISP1_DAT13

Input

3

DISP1_DAT14

Input

3

DISP1_DAT15

Input

3

DISP1_DAT16

Input

3

DISP1_DAT17

Input

3

DISP1_DAT18

Input

3

DISP1_DAT19

Input

DISP1_DAT2

Input

3

DISP1_DAT20

Input

3

DISP1_DAT21

Input

3

DISP1_DAT22

Input

3

DISP1_DAT23

Input

DISP1_DAT3

DISP1_DAT4

Input

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Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

Direction after

Configuraton

after Reset

Contact Name

Power Rail

I/O Buffer Type

1

Reset

DISP1_DAT5

T23

C22

C23

D21

E20

R21

M19

W22

R19

Y23

T19

AA23

T21

P20

P21

V22

V23

N19

W23

P19

R20

AC22

U19

V21

W21

K22

K23

AB1

AA2

V2

NVCC_HS6

NVCC_IPU4

NVCC_IPU8

NVCC_IPU9

NVCC_HS4_2

NVCC_IPU8

NVCC_IPU9

NVCC_IPU2

VDDA33

HSGPIO

GPIO

Input

Keeper

High

3

DISP1_DAT6

3

DISP1_DAT7

GPIO

Input

3

DISP1_DAT8

GPIO

Input

3

DISP1_DAT9

GPIO

Input

DISP2_DAT0

DISP2_DAT1

DISP2_DAT10

DISP2_DAT11

DISP2_DAT12

DISP2_DAT13

DISP2_DAT14

DISP2_DAT15

DISP2_DAT2

DISP2_DAT3

DISP2_DAT4

DISP2_DAT5

DISP2_DAT6

DISP2_DAT7

DISP2_DAT8

DISP2_DAT9

DISPB2_SER_CLK

DISPB2_SER_DIN

DISPB2_SER_DIO

DISPB2_SER_RS

DN

GPIO

Input

GPIO

Input

GPIO

Input

GPIO

Input

GPIO

Input

GPIO

Input

GPIO

Input

GPIO

Input

HSGPIO

GPIO

Input

GPIO

Input

GPIO

Input

GPIO

Input

GPIO

Output

Input

GPIO

100 kΩ pull-up

High

GPIO

Input

GPIO

Output

Analog

DDR2

–

DP

VDDA33

–

DRAM_A0

NVCC_EMI_DRAM

High

DRAM_A1

High

DRAM_A10

High

DRAM_A11

U4

High

DRAM_A12

U2

High

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Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

Direction after

Configuraton

after Reset

Contact Name

Power Rail

I/O Buffer Type

1

Reset

DRAM_A13

DRAM_A14

DRAM_A2

DRAM_A3

DRAM_A4

DRAM_A5

DRAM_A6

DRAM_A7

DRAM_A8

DRAM_A9

DRAM_CAS

DRAM_CS0

DRAM_CS1

DRAM_D0

DRAM_D1

DRAM_D10

DRAM_D11

DRAM_D12

DRAM_D13

DRAM_D14

DRAM_D15

DRAM_D16

DRAM_D17

DRAM_D18

DRAM_D19

DRAM_D2

DRAM_D20

DRAM_D21

DRAM_D22

DRAM_D23

DRAM_D24

DRAM_D25

U1

T2

AA3

V5

W4

Y2

W3

Y1

W2

V3

V4

Y4

Y3

T1

R3

M3

M4

M1

M5

L5

NVCC_EMI_DRAM

DDR2

Output

High

L4

L3

L2

L1

K1

R2

K3

K4

J3

J4

K5

H1

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Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

Direction after

Configuraton

after Reset

Contact Name

Power Rail

I/O Buffer Type

1

Reset

DRAM_D26

DRAM_D27

H2

J5

NVCC_EMI_DRAM

NVCC_EMI

DDR2

Output

Input

High

DRAM_D28

G1

G2

R1

G3

G4

R4

P5

P4

N5

N2

N1

P3

M2

K2

H5

W1

AA1

W5

T3

DDR2

High

DRAM_D29

DDR2

DRAM_D3

DDR2

DRAM_D30

DDR2

DRAM_D31

DDR2

DRAM_D4

DDR2

DRAM_D5

DDR2

DRAM_D6

DDR2

DRAM_D7

DDR2

DRAM_D8

DDR2

DRAM_D9

DDR2

DRAM_DQM0

DRAM_DQM1

DRAM_DQM2

DRAM_DQM3

DRAM_RAS

DDR2

High

DDR2

High

DDR2

High

DDR2

High

DRAM_SDCKE0

DRAM_SDCKE1

DRAM_SDCLK

DRAM_SDCLK_B

DRAM_SDQS0

DRAM_SDQS0_B

DRAM_SDQS1

DRAM_SDQS1_B

DRAM_SDQS2

DRAM_SDQS2_B

DRAM_SDQS3

DRAM_SDQS3_B

DRAM_SDWE

DDR2

High

DDR2

DDR2CLK

DDR2

T4

P2

P1

N4

N3

J1

J2

H3

H4

U5

AA9

3

EIM_A16

GPIO

100 kΩ pull-up

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Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

Direction after

Configuraton

after Reset

Contact Name

Power Rail

I/O Buffer Type

1

Reset

3

EIM_A17

AB9

AC8

AA8

AB8

AC7

AB7

AC6

AC5

AB6

AC4

AB5

AA4

AB2

W6

NVCC_EMI

GPIO

Input

Output

Input

Output

Input

100 kΩ pull-up

High

3

EIM_A18

3

EIM_A19

3

EIM_A20

3

EIM_A21

EIM_A22

3

EIM_A23

100 kΩ pull-up

Keeper

EIM_A24

EIM_A25

EIM_A26

EIM_A27

EIM_BCLK

EIM_CRE

EIM_CS0

EIM_CS1

EIM_CS2

EIM_CS3

EIM_CS4

EIM_CS5

EIM_D16

EIM_D17

EIM_D18

EIM_D19

EIM_D20

EIM_D21

EIM_D22

EIM_D23

EIM_D24

EIM_D25

EIM_D26

EIM_D27

EIM_D28

Keeper

High

Y6

High

Y7

Keeper

AC3

AA6

AA5

AC12

W10

AA11

Y10

AB11

W9

Keeper

AC11

V8

Keeper

AA10

Y9

Keeper

AB10

W8

Keeper

AC10

Keeper

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Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

Direction after

Configuraton

after Reset

Contact Name

Power Rail

I/O Buffer Type

1

Reset

EIM_D29

EIM_D30

Y8

AC9

W7

NVCC_EMI

GPIO

DDR2

Input

Keeper

100 kΩ pull-up

High

EIM_D31

NVCC_EMI

Input

EIM_DA0

EIM_DA1

EIM_DA10

EIM_DA11

EIM_DA12

EIM_DA13

EIM_DA14

EIM_DA15

EIM_DA2

EIM_DA3

EIM_DA4

EIM_DA5

EIM_DA6

EIM_DA7

EIM_DA8

EIM_DA9

EIM_DTACK

EIM_EB0

EIM_EB1

EIM_EB2

EIM_EB3

EIM_LBA

AC15

V13

AC13

V11

AA12

W11

AB12

Y11

AA14

AB14

AC14

Y13

AA13

W13

AB13

Y12

Y5

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

NVCC_EMI

Input

V12

W12

V10

V9

NVCC_EMI

Output

Input

NVCC_EMI

High

NVCC_EMI

Keeper

High

NVCC_EMI

Input

AC2

AA7

AB3

V1

NVCC_EMI

Output

EIM_OE

NVCC_EMI

High

EIM_RW

NVCC_EMI

High

EIM_SDBA0

EIM_SDBA1

EIM_SDBA2

EIM_SDODT0

EIM_SDODT1

NVCC_EMI_DRAM

High

U3

High

F1

High

F3

High

F2

High

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Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

Direction after

Configuraton

after Reset

Contact Name

Power Rail

I/O Buffer Type

1

Reset

EIM_WAIT

AB4

AB20

W20

Y20

NVCC_EMI

NVCC_OSC

NVCC_PER3

NVCC_USBPHY

NVCC_NANDF_A

NVCC_PER5

NVCC_I2C

GPIO

Analog

—

Input

100 kΩ pull-up

—

2

EXTAL

2

FASTR_ANA

Input

—

2

FASTR_DIG

—

Input

—

2

GPANAIO

J23

Analog

UHVIO

GPIO

I2CIO

Analog

GPIO

Output

Input

—

GPIO_NAND

GPIO1_0

GPIO1_1

GPIO1_2

GPIO1_3

GPIO1_4

GPIO1_5

GPIO1_6

GPIO1_7

GPIO1_8

GPIO1_9

I2C1_CLK

I2C1_DAT

ID

D5

100 kΩ pull-up

Keeper

47 kΩ pull-up

Pull-up

—

B21

Input

D20

Input

A22

Input

D18

Input

B22

Input

D19

Input

C19

Input

B23

Input

C21

Input

C20

Input

W15

AB16

L19

Input

NVCC_I2C

Input

NVCC_USBPHY

AHVDDRGB

—

Input

2

IOB

AC19

AB19

AC18

AB18

AC17

AB17

AB15

Output

2

IOB_BACK

—

2

IOG

AHVDDRGB

—

2

IOG_BACK

—

2

IOR

AHVDDRGB

—

2

IOR_BACK

—

JTAG_DE_B

NVCC_PER14

Input/Open-drain

output

47 kΩ pull-up

JTAG_MOD

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

V14

V15

NVCC_PER14

GPIO

Input

100 kΩ pull-up

100 kΩ pull-down

47 kΩ pull-up

Keeper

Y14

Input

AA15

AC16

3-state output

Input

47 kΩ pull-up

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Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

Direction after

Configuraton

after Reset

Contact Name

Power Rail

I/O Buffer Type

1

Reset

JTAG_TRSTB

KEY_COL0

KEY_COL1

KEY_COL2

W14

E15

A16

D15

B17

F16

C16

D14

B16

F15

C15

E3

NVCC_PER14

NVCC_PER13

GPIO

Input

47 kΩ pull-up

100 kΩ pull-up

High

NVCC_PER13

GPIO

Input

NVCC_PER13

GPIO

Input

4

KEY_COL3

NVCC_PER13

GPIO

Output

Input

4

KEY_COL4

NVCC_PER13

GPIO

Low

4

KEY_COL5

NVCC_PER13

GPIO

Low

KEY_ROW0

KEY_ROW1

KEY_ROW2

KEY_ROW3

NANDF_ALE

NANDF_CLE

NANDF_CS0

NANDF_CS1

NANDF_CS2

NANDF_CS3

NANDF_CS4

NANDF_CS5

NANDF_CS6

NANDF_CS7

NANDF_D0

NANDF_D1

NANDF_D10

NANDF_D11

NANDF_D12

NANDF_D13

NANDF_D14

NANDF_D15

NANDF_D2

NANDF_D3

NANDF_D4

NVCC_PER13

GPIO

100 kΩ pull-up

High

NVCC_PER13

GPIO

Input

NVCC_PER13

GPIO

Input

NVCC_PER13

GPIO

Input

NVCC_NANDF_A

NVCC_NANDF_B

NVCC_NANDF_C

NVCC_NANDF_B

NVCC_NANDF_C

UHVIO

Output

Input

F4

High

C3

High

C2

High

E4

High

B1

High

B2

Low

A2

Low

E5

Low

C4

Low

A7

Keeper

E8

Input

B5

Input

D7

Input

C5

Input

A3

Input

B4

Input

D6

Input

A6

Input

D8

Input

B7

Input

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Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

Direction after

Configuraton

after Reset

Contact Name

Power Rail

I/O Buffer Type

1

Reset

NANDF_D5

NANDF_D6

A5

B6

NVCC_NANDF_C

NVCC_NANDF_B

NVCC_NANDF_A

NVCC_NANDF_B

NVCC_NANDF_A

NVCC_PER12

UHVIO

GPIO

Input

Output

Input

Output

Input

Output

Input

Keeper

NANDF_D7

C6

Keeper

NANDF_D8

A4

Keeper

NANDF_D9

E7

Keeper

NANDF_RB0

NANDF_RB1

NANDF_RB2

NANDF_RB3

NANDF_RDY_INT

NANDF_RE_B

NANDF_WE_B

NANDF_WP_B

OWIRE_LINE

PMIC_INT_REQ

PMIC_ON_REQ

PMIC_RDY

D2

100 kΩ pull-up

—

D4

D3

C1

B3

E2

E1

—

D1

—

E14

AA16

W16

AA17

Y15

U20

Y21

A17

E16

D16

A18

F17

A19

B18

G17

E17

B19

D17

C17

100 kΩ pull-up

—

NVCC_SRTC_POW

NVCC_PER3

GPIO

PMIC_STBY_REQ

POR_B

GPIO

LVIO

RESET_IN_B

SD1_CLK

NVCC_PER3

LVIO

NVCC_PER15

UHVIO

SD1_CMD

NVCC_PER15

47 kΩ pull-up

360 kΩ pull-down

—

SD1_DATA0

SD1_DATA1

SD1_DATA2

SD1_DATA3

SD2_CLK

NVCC_PER15

NVCC_PER17

SD2_CMD

NVCC_PER17

47 kΩ pull-up

360 kΩ pull-down

SD2_DATA0

SD2_DATA1

SD2_DATA2

SD2_DATA3

NVCC_PER17

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Package Information and Contact Assignments

Table 128. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

Direction after

Configuraton

after Reset

Contact Name

Power Rail

I/O Buffer Type

1

Reset

STR

A15

V20

B14

D13

E13

A13

A14

C14

F14

B15

D11

E12

A11

B12

C12

D12

A12

B13

C13

B11

C11

E11

AC20

NVCC_PER12

NVCC_PER3

NVCC_PER12

NVCC_PER11

NVCC_OSC

—

100 kΩ pull-down

100 kΩ pull-up

Keeper

TEST_MODE

UART1_CTS

UART1_RTS

UART1_RXD

UART1_TXD

UART2_RXD

UART2_TXD

UART3_RXD

UART3_TXD

USBH1_CLK

USBH1_DATA0

USBH1_DATA1

USBH1_DATA2

USBH1_DATA3

USBH1_DATA4

USBH1_DATA5

USBH1_DATA6

USBH1_DATA7

USBH1_DIR

USBH1_NXT

USBH1_STP

GPIO

Analog

Input

Output

Keeper

2

XTAL

—

1

2

3

4

The state immediately after reset and before ROM firmware or software has executed.

See Table 3 on page 11 for more information.

During power-on reset this port acts as input for fuse override signal. See Table 129 on page 167 for more information.

During power-on reset this port acts as output for diagnostic signal. See Table 129 on page 167 for more information.

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Package Information and Contact Assignments

5.1.2.3

Fuse Override Considerations

Table 129 lists the contacts that can be overridden with fuse settings.

Table 129. Fuse Override Contacts

Direction

After Reset

Configuration

After Reset

1

Contact Name

Signal Configuration

External Termination for Fuse Override

DISP1_DAT10

DISP1_DAT11

DISP1_DAT12

DISP1_DAT13

DISP1_DAT14

DISP1_DAT15

DISP1_DAT16

DISP1_DAT17

DISP1_DAT18

DISP1_DAT19

DISP1_DAT20

DISP1_DAT21

DISP1_DAT22

DISP1_DAT23

DISP1_DAT6

DISP1_DAT7

DISP1_DAT8

DISP1_DAT9

EIM_A16

Input

Output

Keeper

BT_SPARE_SIZE

BT_LPB_FREQ[2]

BT_MLC_SEL

4.7 kΩ pull-up or pull-down

BT_MEM_CTL[0]

BT_MEM_CTL[1]

BT_BUS_WIDTH

BT_PAGE_SIZE[0]

BT_PAGE_SIZE[1]

BT_WEIM_MUXED[0]

BT_WEIM_MUXED[1]

BT_MEM_TYPE[0]

BT_MEM_TYPE[1]

BT_LPB_FREQ[0]

BT_LPB_FREQ[1]

2

BT_USB_SRC

BT_EEPROM_CFG

BT_SRC[0]

BT_SRC[1]

3

100 kΩ pull-up OSC_FREQ_SEL[0]

100 kΩ pull-up OSC_FREQ_SEL[1]

100 kΩ pull-up BT_LPB[0]

4.7 kΩ pull-down or none for high level

2

EIM_A17

4.7 kΩ pull-down or none for high level

2

EIM_A18

4.7 kΩ pull-down or none for high level

2

EIM_A19

100 kΩ pull-up BT_LPB[1]

4.7 kΩ pull-down or none for high level

2

EIM_A20

100 kΩ pull-up BT_UART_SRC[0]

100 kΩ pull-up BT_UART_SRC[1]

4.7 kΩ pull-down or none for high level

2

EIM_A21

4.7 kΩ pull-down or none for high level

KEY_COL3

High

Output for diagnostic signal

INT_BOOT during

—

power-on reset

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Package Information and Contact Assignments

Table 129. Fuse Override Contacts (continued)

Direction

After Reset

Configuration

After Reset

1

Contact Name

Signal Configuration

External Termination for Fuse Override

KEY_COL4

Output

Low

Output for diagnostic signal

ANY_PU_RST during

power-on reset

—

KEY_COL5

Output

Low

Output for diagnostic signal

JTAG_ACT during power-on

reset

—

1

Signal Configuration as Fuse Override Input at Power Up. These are special I/O lines that control the boot up configuration

during product development. In production, the boot configuration is controlled by fuses.

2

3

External USB PHY selection is not functional.

Consider using an external 68 kΩ pull-up if system constraints indicate that the on-chip 100 kΩ pull-up is too weak.

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Package Information and Contact Assignments

5.2

19 x 19 mm, 0.8 Pitch Ball Map

Table 130 shows the 19 × 19 mm, 0.8 pitch ball map.

Table 130. 19 × 19 mm, 0.8 Pitch Ball Map

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Package Information and Contact Assignments

Table 130. 19 × 19 mm, 0.8 Pitch Ball Map (continued)

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Package Information and Contact Assignments

Table 130. 19 × 19 mm, 0.8 Pitch Ball Map (continued)

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Package Information and Contact Assignments

Table 130. 19 × 19 mm, 0.8 Pitch Ball Map (continued)

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Revision History

6 Revision History

Table 131 provides a revision history for this data sheet.

2

Table 131. i.MX51 Data Sheet Document Revision History

Substantive Change(s)

Rev.

Number

Date

Rev. 6 10/2012 • In Table 25, "I/O Leakage Current," on page 29, updated supply rail names for SD1 and SD2 to

NVCC_PER15 and NVCC_PER17, respectively.

• Updated Section 4.6.7.3, “General WEIM Timing-Synchronous Mode.”

• Updated Section 4.6.7.4, “Examples of WEIM Synchronous Accesses.”

• Updated Section 4.6.7.5, “General WEIM Timing-Asynchronous Mode.”

Rev. 5 03/2012 • In Table 4, "JTAG Controller Interface Summary," on page 13, changed On-Chip Termination column

value for JTAG_MOD from “100 kΩ pull-down” to “100 kΩ pull-up.”

• In Section 3.7, “USB-OTG IOMUX Pin Configuration,” removed the third sentence from the first

paragraph and added a note after Table 9.

• In Section 4.3.4, “Ultra-High Voltage I/O (UHVIO) DC Parameters,” added clarification about UHVIO I/O

cell HVE bit functionality after Table 21.

• In Section 4.6.9, “DDR2 SDRAM Specific Parameters:”

—Updated Table 58, "DDR2 SDRAM Timing Parameter Table," on page 67

—Added a note after Table 58

—Updated Figure 36, "DDR2 SDRAM Write Cycle Timing Diagram," on page 69

—Updated Table 60, "DDR2 SDRAM Write Cycle Parameter Table," on page 69

—Added a note after Table 60

—Updated Figure 37, "DDR2 SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram," on

page 71

—Updated Table 63, "DDR2 SDRAM Read Cycle Parameter Table," on page 71

—Added a note after Table 63

• In Section 4.7.8.2, “Electrical Characteristics,” changed signal name in the second sentence of the first

paragraph from “SENSB_MCLK” to “SENSB_PIX_CLK.”

• In Table 128, "19 x 19 mm Signal Assignments, Power Rails, and I/O," on page 155, changed

Configuraton after Reset column value for contacts, DI1_D0_CS, DI1_D1_CS, DI1_PIN11, and

DI1_PIN12, from “Low” to “High.”

• In Table 128, "19 x 19 mm Signal Assignments, Power Rails, and I/O," on page 155, changed

Configuraton after Reset column value for contact, JTAG_MOD, from “100 kΩ pull-down” to “100 kΩ

pull-up.”

• In Table 128, "19 x 19 mm Signal Assignments, Power Rails, and I/O," on page 155, changed Power Rail

column value for contacts, UART1_CTS, UART1_RTS, UART1_RXD, UART1_TXD, UART2_RXD,

UART2_TXD, UART3_RXD, and UART3_TXD, from “NVVCC_PER12” to “NVCC_PER12.”

• In Table 129, "Fuse Override Contacts," on page 167:

—Added a footnote for contact, DISP1_DAT6

—Removed information about contact, EIM_A23, because the signal configuration it corresponds to,

BT_HPN_EN, is not in use.

• Corrected cross-references throughout the document.

Rev. 4 08/2010 • Removed table footnote in Table 47, "CAMP Electrical Parameters (CKIH1, CKIH2)," on page 46.

• Updated Table 52, "WEIM Interface Pinout in Various Configurations," on page 53.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

Freescale Semiconductor

173

Revision History

Table 131. i.MX51 Data Sheet Document Revision History (continued)

Substantive Change(s)

Rev.

Date

Number

Rev. 3 06/2010 • Updated Max column of Table 15, "Fuse Supply Current," on page 19. Deleted eFuse Read Current row

from the same table.

• Updated Symbol, Test Conditions, and Max columns of Table 18, "GPIO/HSGPIO DC Electrical

Characteristics," on page 23.

• Updated Max and Unit columns of Table 19, "DDR2 I/O DC Electrical Parameters," on page 24.

• Updated Test Conditions, Max, and Unit columns of Table 20, "LVIO DC Electrical Characteristics," on

page 24

• Updated Symbol, Test Conditions, Max, and Unit columns of Table 21, "UHVIO DC Electrical

Characteristics," on page 25.

• Updated Max and Unit columns of Table 22, "I2C Standard/Fast/High-Speed Mode Electrical

Parameters for Low/Medium Drive Strength," on page 27.

• Added a new table Table 25, "I/O Leakage Current," on page 29.

Rev. 2 05/2010 • Changed the VREFOUT column in Table 3, "Special Signal Considerations," on page 11.

• Added Section 3, “IOMUX Configuration for Boot Media”.

• Updated Figure 2, "Power-Up Sequence," on page 22.

• Added a note in Section 4.2.1, “Power-Up Sequence”.

• Updated Section 4.2.1, “Power-Up Sequence.”

• Changed the Input current (47 kΩ Pull-up) column in Table 21, "UHVIO DC Electrical Characteristics,"

on page 25 to Input current (75 kO Pull-up).

• Added new table for parameters for DDR2 Pad output buffer Impedance. See Table 27, "DDR2 I/O

Output Buffer Impedance HVE = 0," on page 30.

• Added new section under Section 4.5, “I/O AC Parameters”. See Section 4.5.4, “AC Electrical

Characteristics for DDR2”.

• Updated Table 47, "CAMP Electrical Parameters (CKIH1, CKIH2)," on page 46. In the VIH (for square

wave input) parameter, the minimum frequency was changed to NVCC_PER3 - 0.25V and the maximum

frequency was changed to NVCC_PER3.

• Added a note in Section 4.6.6, “NAND Flash Controller (NFC) Parameters” after Table 49.

• Updated Asymmetric Mode Min, Symmetric Mode Min, and Max columns of Table 50.

• Removed Conditions parameters of the Full scale output voltage row in Table 82.

• Updated Section 4.7.11, “P-ATA Timing Parameters”. Replaced ATA/ATAPI-6 specification with

ATA/ATAPI-5 specification.

• In Table 102, "SSI Transmitter Timing with Internal Clock," on page 133, under the Synchronous Internal

Clock Operation sections for the ID SS42, minimum frequency was changed from 10.0 to 30.

• In Table 103, "SSI Receiver Timing with Internal Clock," on page 134, under the Internal Clock

Operation section for ID SS20, minimum frequency was changed from 10.0 to 30.

• In Table 104, "SSI Transmitter Timing with External Clock," on page 136, under the External Clock

Operation section for ID SS38, maximum frequency was changed from 15.0 to 30.

• Added a new section Section 4.7.16.1, “UART Electrical”, under Section 4.7.16, “UART”.

• In Table 118, "USB Port Timing Specification in VP_VM Bi-directional Mode," on page 146, for IDs SS28

and SS29, direction was changed from out to in.

• In Table 120, "USB Timing Specification in VP_VM Unidirectional Mode," on page 148, for IDs US40 and

US41, direction was changed from out to in and the reference signal was changed to USB_VM1 and

USB_VP1 respectively.

• In Table 122, "USB Timing Specification for ULPI Parallel Mode," on page 149, added an extra row for

ID17.

• Updated Signal and Direction columns in Table 120, "USB Timing Specification in VP_VM Unidirectional

Mode," on page 148.

• Updated Signal names in Table 118, "USB Port Timing Specification in VP_VM Bi-directional Mode," on

page 146.

Rev. 1 10/2009 Initial public release.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 6

174

Freescale Semiconductor

Information in this document is provided solely to enable system and software

implementers to use Freescale products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits based on the

information in this document.

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herein. Freescale makes no warranty, representation, or guarantee regarding the

suitability of its products for any particular purpose, nor does Freescale assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. “Typical” parameters that may be provided in Freescale data sheets and/or

specifications can and do vary in different applications, and actual performance may

vary over time. All operating parameters, including “typicals,” must be validated for each

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Document Number: IMX51AEC

Rev. 6

09/2012


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描述：	Multifunction Peripheral
文件：	总175页 (文件大小：3372K)
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