935324297557 [NXP]
Microcontroller;
| 型号： | 935324297557 |
| 厂家： | 
NXP |
| 描述： | Microcontroller 微控制器 外围集成电路 |
| 文件： | 总106页 (文件大小：2381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Technical Data
Document Number: MC56F8006
Rev. 4, 06/2011
MC56F8006/MC56F8002
48-pin LQFP
Case: 932-03
7 x 7 mm2
32-pin LQFP
Case: 873A-03
7 x 7 mm2
28-pin SOIC
Case: 751F-05
7.5 x 18 mm2
MC56F8006/MC56F8002
Digital Signal Controller
32-pin PSDIP
Case: 1376-02
9 x 28.5 mm2
This document applies to parts marked with 2M53M.
RAM. Program flash memory can be independently bulk
erased or erased in small pages of 512 bytes (256 words).
The 56F8006/56F8002 is a member of the 56800E core-based
family of digital signal controllers (DSCs). It combines, on a
single chip, the processing power of a DSP and the
functionality of a microcontroller with a flexible set of
peripherals to create a cost-effective solution. Because of its
low cost, configuration flexibility, and compact program
code, the 56F8006/56F8002 is well-suited for many
applications. It includes many peripherals that are especially
useful for cost-sensitive applications, including:
• Industrial control
On-chip features include:
• Up to 32 MIPS at 32 MHz core frequency
• DSP and MCU functionality in a unified, C-efficient
architecture
• On-chip memory
– 56F8006: 16 KB (8K x 16) flash memory
– 56F8002: 12 KB (6K x 16) flash memory
– 2 KB (1K x 16) unified data/program RAM
• One 6-channel PWM module
• Home appliances
• Smart sensors
• Two 28-channel, 12-bit analog-to-digital converters
(ADCs)
• Fire and security systems
• Switched-mode power supply and power management
• Power metering
• Two programmable gain amplifiers (PGA) with gain up to
32x
• Three analog comparators
• Motor control (ACIM, BLDC, PMSM, SR, and stepper)
• Handheld power tools
• Arc detection
• One programmable interval timer (PIT)
• One high-speed serial communication interface (SCI) with
LIN slave functionality
• Medical device/equipment
• Instrumentation
• Lighting ballast
• One serial peripheral interface (SPI)
• One 16-bit dual timer (2 x 16 bit timers)
• One programmable delay block (PDB)
2
• One SMBus compatible inter-integrated circuit (I C) port
• One real time counter (RTC)
The 56800E core is based on a dual Harvard-style architecture
consisting of three execution units operating in parallel, allowing
as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow
straightforward generation of efficient, compact DSP and control
code. The instruction set is also highly efficient for C compilers
to enable rapid development of optimized control applications.
The 56F8006/56F8002 supports program execution from internal
memories. Two data operands can be accessed from the on-chip
data RAM per instruction cycle. The 56F8006/56F8002 also
offers up to 40 general-purpose input/output (GPIO) lines,
depending on peripheral configuration.
• Computer operating properly (COP)/watchdog
• Two on-chip relaxation oscillators — 1 kHz and 8 MHz
(400 kHz at standby mode)
• Crystal oscillator
• Integrated power-on reset (POR) and low-voltage interrupt
(LVI) module
• JTAG/enhanced on-chip emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 40 GPIO lines
• 28-pin SOIC, 32-pin LQFP, 32-pin PSDIP, and 48-pin
LQFP packages
The 56F8006/56F8002 digital signal controller includes up to
16 KB of program flash and 2 KB of unified data/program
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009–2011. All rights reserved.
Table of Contents
1
2
3
MC56F8006/MC56F8002 Family Configuration . . . . . . . . . . . .3
8.1 General Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 41
8.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 42
8.3 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 43
8.4 Recommended Operating Conditions . . . . . . . . . . . . . 45
8.5 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . 46
8.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . 51
8.7 Flash Memory Characteristics. . . . . . . . . . . . . . . . . . . 53
8.8 External Clock Operation Timing. . . . . . . . . . . . . . . . . 53
8.9 Phase Locked Loop Timing . . . . . . . . . . . . . . . . . . . . . 54
8.10 Relaxation Oscillator Timing . . . . . . . . . . . . . . . . . . . . 54
8.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing. 56
8.12 External Oscillator (XOSC) Characteristics. . . . . . . . . 56
8.13 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 57
8.14 COP Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.15 PGA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.16 ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8.17 HSCMP Specifications . . . . . . . . . . . . . . . . . . . . . . . . 68
8.18 Optimize Power Consumption . . . . . . . . . . . . . . . . . . . 68
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . 70
9.2 Electrical Design Considerations. . . . . . . . . . . . . . . . . 71
9.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3.1 56F8006/56F8002 Features . . . . . . . . . . . . . . . . . . . . . .4
3.2 Award-Winning Development Environment. . . . . . . . . . .8
3.3 Architecture Block Diagram. . . . . . . . . . . . . . . . . . . . . . .9
3.4 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . .11
Signal/Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . .11
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.2 Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.3 56F8006/56F8002 Signal Pins . . . . . . . . . . . . . . . . . . .17
Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.2 Program Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.3 Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.4 Interrupt Vector Table and Reset Vector . . . . . . . . . . . .31
5.5 Peripheral Memory-Mapped Registers . . . . . . . . . . . . .32
5.6 EOnCE Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .33
General System Control Information . . . . . . . . . . . . . . . . . . .34
6.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.2 Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.3 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.4 On-chip Clock Synthesis. . . . . . . . . . . . . . . . . . . . . . . .34
6.5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.6 System Integration Module (SIM) . . . . . . . . . . . . . . . . .37
6.7 PWM, PDB, PGA, and ADC Connections. . . . . . . . . . .38
6.8 Joint Test Action Group (JTAG)/Enhanced On-Chip
Emulator (EOnCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4
5
6
9
10 Package Mechanical Outline Drawings. . . . . . . . . . . . . . . . . 73
10.1 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.2 32-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.3 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.4 32-Pin PSDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Appendix A
7
8
Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7.1 Operation with Security Enabled. . . . . . . . . . . . . . . . . .40
7.2 Flash Access Lock and Unlock Mechanisms . . . . . . . .40
7.3 Product Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Appendix B
Peripheral Register Memory Map and Reset Value . . . . . . . 86
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
2
Freescale Semiconductor
MC56F8006/MC56F8002 Family Configuration
1
MC56F8006/MC56F8002 Family Configuration
MC56F8006/MC56F8002 device comparison in Table 1.
Table 1. MC56F8006 Series Device Comparison
MC56F8006
MC56F8002
Feature
28-pin
32-pin
48-pin
28-pin
Flash memory size (Kbytes)
16
12
RAM size (Kbytes)
2
3
2
Analog comparators (ACMP)
Analog-to-digital converters (ADC)
Unshielded ADC inputs
6
9
7
7
6
9
Shielded ADC inputs
11
18
17
24
Total number of ADC input pins1
Programmable gain amplifiers (PGA)
Pulse-width modulator (PWM) outputs
PWM fault inputs
15
15
2
6
3
4
4
3
Inter-integrated circuit (IIC)
1
1
1
1
1
2
1
Serial peripheral interface (SPI)
High speed serial communications interface (SCI)
Programmable interrupt timer (PIT)
Programmable delay block (PDB)
16-bit multi-purpose timers (TMR)
Real-time counter (RTC)
Computer operating properly (COP) timer
Phase-locked loop (PLL)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1 kHz on-chip oscillator
8 MHz (400 kHz at standby mode) on-chip ROSC
Crystal oscillator
Power management controller (PMC)
IEEE 1149.1 Joint Test Action Group (JTAG) interface
Enhanced on-chip emulator (EOnCE) IEEE 1149.1 Joint
Test Action Group (JTAG) interface
1
Some ADC inputs share the same pin. See Table 4.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
3
Block Diagram
2
Block Diagram
Figure 1 shows a top-level block diagram of the MC56F8006/MC56F8002 digital signal controller. Package options for this
family are described later in this document. Italics indicate a 56F8002 device parameter.
V
V
V
V
DD
SS
DDA SSA
RESET
4
3
3
JTAG/EOnCE
Port or GPIOD
Digital Reg
Low-Voltage
Supervisor
Analog Reg
PWM
6
PWM Outputs
PMC
16-Bit 56800E Core
3
Fault Inputs
Data ALU 16 x 16 + 36 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Program Controller
and Hardware
Looping Unit
Address
Generation Unit
Bit
Manipulation
Unit
programmable
delay block
PAB
PDB
CDBR
CDBW
ADCA
24 Total
PGA/ADC
ADCB
R/W Control
XDB2
XAB1
XAB2
Memory
Flash Memory
16 Kbytes flash
12 Kbytes flash
2
2
CMP0
System Bus
Control
CMP
PAB
PDB
CDBR
or
GPIOD
CMP1
Unified Data /
Program RAM
2KB
CDBW
PIT
2
CMP2
GPIO are
muxed with
all other func
pins.
IPBus Bridge
Note: All pins
40
are muxed with
other peripheral
pins.
Power
Dual GP Timer
Management
Controller
4
RTC
2
System
ROSC
Clock
Interrupt
Controller
SCI
SPI
I C
COP/
Watchdog
Integration
Generator*
OSC
Module
2
2
2
4
Crystal
Oscillator
Figure 1. MC56F8006/MC56F8002 Block Diagram
3
Overview
3.1
56F8006/56F8002 Features
3.1.1
Core
•
•
•
•
•
•
Efficient 16-bit 56800E family digital signal controller (DSC) engine with dual Harvard architecture
As many as 32 million instructions per second (MIPS) at 32 MHz core frequency
155 basic instructions in conjunction with up to 20 address modes
Single-cycle 16 16-bit parallel multiplier-accumulator (MAC)
Four 36-bit accumulators, including extension bits
32-bit arithmetic and logic multi-bit shifter
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
4
Freescale Semiconductor
Overview
•
•
•
•
•
•
•
•
•
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging
3.1.2
Operation Range
•
•
•
1.8 V to 3.6 V operation (power supplies and I/O)
From power-on-reset: approximately 1.9 V to 3.6 V
Ambient temperature operating range:
— –40 °C to 125 °C
3.1.3
Memory
•
•
•
Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security and protection that prevent unauthorized users from gaining access to the internal flash
On-chip memory
— 16 KB of program flash for 56F8006 and 12 KB of program flash for 56F8002
— 2 KB of unified data/program RAM
•
EEPROM emulation capability using flash
3.1.4
Interrupt Controller
•
Five interrupt priority levels
— Three user programmable priority levels for each interrupt source: Level 0, 1, 2
— Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, SWI3
instruction. Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, EOnCE trace
buffer
— Lowest-priority software interrupt: level LP
•
•
•
•
•
Allow nested interrupt that higher priority level interrupt request can interrupt lower priority interrupt subroutine
The masking of interrupt priority level is managed by the 56800E core
One programmable fast interrupt that can be assigned to any interrupt source
Notification to system integration module (SIM) to restart clock out of wait and stop states
Ability to relocate interrupt vector table
3.1.5
Peripheral Highlights
•
One multi-function, six-output pulse width modulator (PWM) module
— Up to 96 MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and edge-aligned PWM signal mode
— Phase shifting PWM pulse generation
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
5
Overview
— Four programmable fault inputs with programmable digital filter
— Double-buffered PWM registers
— Separate deadtime insertions for rising and falling edges
— Separate top and bottom pulse-width correction by means of software
— Asymmetric PWM output within both Center Aligned and Edge Aligned operation
— Separate top and bottom polarity control
— Each complementary PWM signal pair allows selection of a PWM supply source from:
–
–
–
PWM generator
Internal timers
Analog comparator outputs
•
•
Two independent 12-bit analog-to-digital converters (ADCs)
— 2 x 14 channel external inputs plus seven internal inputs
— Support simultaneous and software triggering conversions
— ADC conversions can be synchronized by PWM and PDB modules
— Sampling rate up to 400 KSPS for 10- or 12-bit conversion result; 470 KSPS for 8-bit conversion result
— Two 16-word result registers
Two programmable gain amplifier (PGAs)
— Each PGA is designed to amplify and convert differential signals to a single-ended value fed to one of the ADC
inputs
— 1X, 2X, 4X, 8X, 16X, or 32X gain
— Software and hardware triggers are available
— Integrated sample/hold circuit
— Includes additional calibration features:
–
Offset calibration eliminates any errors in the internal reference used to generate the VDDA/2 output center
point
–
–
Gain calibration can be used to verify the gain of the overall datapath
Both features require software correction of the ADC result
•
•
Three analog comparators (CMPs)
— Selectable input source includes external pins, internal DACs
— Programmable output polarity
— Output can drive timer input, PWM fault input, PWM source, external pin output, and trigger ADCs
— Output falling and rising edge detection able to generate interrupts
One dual channel 16-bit multi-purpose timer module (TMR)
— Two independent 16-bit counter/timers with cascading capability
— Up to 96 MHz operating clock
— Each timer has capture and compare and quadrature decoder capability
— Up to 12 operating modes
— Four external inputs and two external outputs
One serial communication interface (SCI) with LIN slave functionality
— Up to 96 MHz operating clock
•
— Full-duplex or single-wire operation
— Programmable 8- or 9- bit data format
— Two receiver wakeup methods:
–
–
Idle line
Address mark
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
6
Freescale Semiconductor
Overview
— 1/16 bit-time noise detection
•
•
One serial peripheral interface (SPI)
— Full-duplex operation
— Master and slave modes
— Programmable length transactions (2 to 16 bits)
— Programmable transmit and receive shift order (MSB as first or last bit transmitted)
— Maximum slave module frequency = module clock frequency/2
2
One inter-integrated Circuit (I C) port
— Operates up to 400 kbps
— Supports master and slave operation
— Supports 10-bit address mode and broadcasting mode
— Supports SMBus, Version 2
•
•
One 16-bit programmable interval timer (PIT)
— 16 bit counter with programmable counter modulo
— Interrupt capability
One 16-bit programmable delay block (PDB)
— 16 bit counter with programmable counter modulo and delay time
— Counter is initiated by positive transition of internal or external trigger pulse
— Supports two independently controlled delay pulses used to synchronize PGA and ADC conversions with input
trigger event
— Two PDB outputs can be ORed together to schedule two conversions from one input trigger event
— PDB outputs can be can be used to schedule precise edge placement for a pulsed output that generates the control
signal for the CMP windowing comparison
— Supports continuous or single shot mode
— Bypass mode supported
•
Computer operating properly (COP)/watchdog timer capable of selecting different clock sources
— Programmable prescaler and timeout period
— Programmable wait, stop, and partial powerdown mode operation
— Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected
— Choice of clock sources from four sources in support of EN60730 and IEC61508:
–
–
–
–
On-chip relaxation oscillator
External crystal oscillator/external clock source
System clock (IPBus up to 32 MHz)
On-chip low power 1 kHz oscillator
•
•
Real-timer counter (RTC)
— 8-bit up-counter
— Three software selectable clock sources
–
–
–
External crystal oscillator/external clock source
On-chip low-power 1 kHz oscillator
System bus (IPBus up to 32 MHz)
— Can signal the device to exit power down mode
Phase lock loop (PLL) provides a high-speed clock to the core and peripherals
— Provides 3x system clock to PWM and dual timer and SCI
— Loss of lock interrupt
— Loss of reference clock interrupt
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
7
Overview
•
Clock sources
— On-chip relaxation oscillator with two user selectable frequencies: 400 kHz for low speed mode, 8 MHz for
normal operation
— On-chip low-power 1 kHz oscillator can be selected as clock source to the RTC and/or COP
— External clock: crystal oscillator, ceramic resonator, and external clock source
Power management controller (PMC)
•
— On-chip regulator for digital and analog circuitry to lower cost and reduce noise
— Integrated power-on reset (POR)
— Low-voltage interrupt with a user selectable trip voltage of 1.81 V or 2.31 V
— User selectable brown-out reset
— Run, wait, and stop modes
— Low-power run, wait, and stop modes
— Partial power down mode
•
•
Up to 40 general-purpose I/O (GPIO) pins
— Individual control for each pin to be in peripheral or GPIO mode
— Individual input/output direction control for each pin in GPIO mode
— Hysteresis and configurable pullup device on all input pins
— Configurable slew rate and drive strength and optional input low pass filters on all output pins
— 20 mA sink/source current
JTAG/EOnCE debug programming interface for real-time debugging
— IEEE 1149.1 Joint Test Action Group (JTAG) interface
— EOnCE interface for real-time debugging
3.1.6
Power Saving Features
•
Three low power modes
— Low-speed run, wait, and stop modes: 200 kHz IP bus clock provided by ROSC
— Low-power run, wait, and stop modes: clock provided by external 32–38.4 kHz crystal
— Partial power down mode
•
•
•
•
Low power external oscillator can be used in any low-power mode to provide accurate clock to active peripherals
Low power real time counter for use in run, wait, and stop modes with internal and external clock sources
32 s typical wakeup time from partial power down modes
Each peripheral can be individually disabled to save power
3.2
Award-Winning Development Environment
TM
Processor Expert (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based
software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging.
A complete set of evaluation modules (EVMs), demonstration board kit, and development system cards support concurrent
engineering. Together, PE, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast, and efficient
development.
2
A full set of programmable peripherals — PWM, PGAs, ADCs, SCI, SPI, I C, PIT, timers, and analog comparators — supports
various applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals can also be
used as general-purpose input/outputs (GPIOs).
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
8
Freescale Semiconductor
Overview
3.3
Architecture Block Diagram
The 56F8006/56F8002’s architecture is shown in Figure 2 and Figure 3. Figure 2 illustrates how the 56800E system buses
communicate with internal memories and the IPBus interface and the internal connections among each unit of the 56800E core.
Figure 3 shows the peripherals and control blocks connected to the IPBus bridge. Please see the system integration module
(SIM) section in the MC56F8006 Reference Manual for information about which signals are multiplexed with those of other
peripherals.
DSP56800E Core
Program Control Unit
ALU1
ALU2
Address
Generation
Unit
PC
LA
LA2
HWS0
HWS1
FIRA
Instruction
Decoder
R0
R1
(AGU)
R2
R3
R4
R5
N
Interrupt
Unit
Program
Memory
M01
N3
OMR
SR
LC
LC2
Looping
Unit
SP
FISR
XAB1
XAB2
PAB
Data/
Program
RAM
PDB
CDBW
CDBR
XDB2
A2
B2
C2
D2
A1
B1
C1
D1
Y1
Y0
X0
A0
B0
C0
D0
Bit-
Manipulation
Unit
IPBus
Interface
Y
Data
Enhanced
OnCE™
Arithmetic
Logic Unit
(ALU)
JTAG TAP
MAC and ALU Multi-Bit Shifter
Figure 2. 56800E Core Block Diagram
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
9
Overview
IPBus Bridge
RTC
GPIOA7
GPIOA6
GPIOA5
GPIOA4
GPIOA3
GPIOA2
GPIOA1
GPIOA0
COP
System
Clock
Second Clcok source
Crystal
RESTE
COSC
ROSC
OCCS
SIM
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2
GPIOB1
GPIOB0
PMC
1KHz
INTC
SPI
SCI
I2C
GPIOC7
GPIOC6
GPIOC5
GPIOC4
GPIOC3
GPIOC2
GPIOC1
GPIOC0
Dual Timer (TMR)
PWM
PWM Synch
PWM Input Mux
GPIOD3
GPIOD2
GPIOD1
GPIOD0
CMP0
CMP1
GPIOE7
GPIOE6
GPIOE5
GPIOE4
GPIOE3
GPIOE2
GPIOE1
GPIOE0
CMP2
PGA0
PDB
Trigger A
ADCA
PreTrigger A
ANA15
GPIOF3
GPIOF2
GPIOF1
GPIOF0
Trigger B
ADCB
PreTrigger B
ANB15
PGA1
Figure 3. Peripheral Subsystem
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
10
Freescale Semiconductor
Signal/Connection Descriptions
3.4
Product Documentation
The documents listed in Table 2 are required for a complete description and proper design with the 56F8006/56F8002.
Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature
Distribution Centers, or online at http://www.freescale.com.
Table 2. 56F8006/56F8002 Device Documentation
Topic
Description
Order Number
DSP56800E Reference Detailed description of the 56800E family architecture,
DSP56800ERM
Manual
16-bit digital signal controller core processor, and the
instruction set
56F800x Peripheral
Reference Manual
Detailed description of peripherals of the 56F8006 and
56F8002 devices
MC56F8006RM
TBD
56F80x Serial Bootloader Detailed description of the Serial Bootloader in the
User Guide
56F800x family of devices
56F8006/56F8002
Technical Data Sheet
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
MC56F8006
MC56F8006E
56F8006/56F8002 Errata Details any chip issues that might be present
4
Signal/Connection Descriptions
4.1
Introduction
The input and output signals of the 56F8006/56F8002 are organized into functional groups, as detailed in Table 3. Table 4
summarizes all device pins. In Table 4, each table row describes the signal or signals present on a pin, sorted by pin number.
Table 3. Functional Group Pin Allocations
Number of Pins Number of Pins Number of Pins Number of Pins
Functional Group
in 28 SOIC
in 32 LQFP
in 32 PSDIP
in 48 LQFP
Power Inputs (VDD, VDDA
)
2
3
2
3
2
3
4
4
Ground (VSS, VSSA
Reset1
)
1
1
1
1
Pulse Width Modulator (PWM) Ports1
Serial Peripheral Interface (SPI) Ports1
Serial Communications Interface 0 (SCI) Ports1
Inter-Integrated Circuit Interface (I2C) Ports1
Analog-to-Digital Converter (ADC) Inputs1
High Speed Analog Comparator Inputs1
Programmable Gain Amplifiers (PGA)1
Dual Timer Module (TMR) Ports1
10
5
12
7
12
7
12
7
4
5
5
5
6
7
7
7
16
13
4
18
15
4
18
15
4
24
25
4
8
10
—
5
10
—
5
10
1
Programmable Delay Block (PDB)1
Clock1
—
5
5
JTAG/Enhanced On-Chip Emulation (EOnCE1)
4
4
4
4
1
Pins may be shared with other peripherals. See Table 4.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
11
Signal/Connection Descriptions
In Table 4, peripheral pins in bold identify reset state.
Table 4. 56F8006/56F8002 Pins
Pin Number
Peripherals
Pin Name
Power
and JTAG Misc.
Ground
28
32
32
48
Dual
Timer
2
GPIO
I C
SCI
SPI
ADC
PGA
COMP
PWM
SOIC LQFP PSDIP LQFP
1
1
1
26
27
1
2
3
4
29
30
31
32
1
2
3
GPIOB6/RXD/SDA/ANA13
and CMP0_P2/CLKIN
B6
B1
B7
SDA RXD
SDA
ANA13
ANA12
ANA11
CMP0_P2
CMP2_P3
CMP2_M3
CLKIN
GPIOB1/SS/SDA/ANA12
SS
andCMP2_P3
GPIOB7/TXD/SCL/ANA11
SCL
TXD
and CMP2_M3
4
5
6
GPIOB5/T1/FAULT3/SCLK
B5
E0
E1
SCLK
T1
FAULT3
GPIOE0
1
GPIOE1/ANB9 and
ANB9
CMP0_P1
CMP0_P1
1
28
1
5
6
7
1
2
3
7
8
ANB8 and PGA1+ and
CMP0_M2/GPIOC4
C4
E2
C5
C7
C6
ANB8 PGA1+ CMP0_M2
1
GPIOE2/ANB7 and
ANB7
CMP0_M1
CMP0_M1
1
9
ANB6 and PGA1– and
CMP0_P4/GPIOC5
ANB6 PGA1– CMP0_P4
1
10
11
GPIOC7/ANB5 and
ANB5
ANB4
CMP1_M2
CMP1_P1
CMP1_M2
1
2
ANB4 and
PWM2
CMP1_P1/GPIOC6/PWM2
3
4
8
9
4
5
12
13
14
V
V
V
V
DDA
SSA
DDA
SSA
1
GPIOE3/ANA10 and
E3
C2
E5
C1
E4
C0
ANA10
CMP2_M1
CMP2_M1
1
5
6
10
11
6
7
15
16
17
18
19
ANA9 and PGA0– and
CMP2_P4/GPIOC2
ANA9 PGA0– CMP2_P4
1
GPIOE5/ANA8 and
ANA8
CMP2_P1
CMP2_P1
1
ANA7 and PGA0+ and
CMP2_M2/GPIOC1
ANA7 PGA0+ CMP2_M2
1
GPIOE4/ANA6 and
CMP2_P2
ANA6
ANA5
CMP2_P2
CMP1_M1
1
7
8
12
13
8
9
ANA5 and
CMP1_M1/GPIOC0/FAULT0
FAULT0
20
21
22
V
V
SS
DD
SS
V
V
DD
1
9
14
10
TCK/GPIOD2/ANA4 and
D2
ANA4
CMP1_P2,
TCK
CMP1_P2/CMP2_OUT
CMP2_OUT
10
11
15
16
11
12
23
24
RESET/GPIOA7
A7
B3
RESET
1
1
GPIOB3/MOSI/TIN3/ANA3
and
ANB3/PWM5/CMP1_OUT
MOSI ANA3
and
CMP1_OUT TIN3 PWM5
ANB3
17
18
19
13
14
15
25
26
GPIOB2/MISO/TIN2/ANA2
and ANB2/CMP0_OUT
B2
A6
B4
MISO ANA2
and
CMP0_OUT TIN2
ANB2
12
13
GPIOA6/FAULT0/ANA1 and
ANB1/SCL/TXD/CLKO_1
SCL
TXD
ANA1
and
ANB1
FAULT0
CLKO_1
CLKO_0
27 GPIOB4/T0/CLKO_0/MISO/
SDA RXD MISO ANA0
T0
SDA/RXD/ANA0 and ANB0
and
ANB0
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
12
Freescale Semiconductor
Signal/Connection Descriptions
Table 4. 56F8006/56F8002 Pins (continued)
Pin Number
32 32
Peripherals
Pin Name
Power
Dual
28
48
2
GPIO
I C
SCI
SPI
ADC
PGA
COMP
PWM
and JTAG Misc.
SOIC LQFP PSDIP LQFP
Timer
Ground
28
GPIOE6
E6
A5
14
20
16
29
GPIOA5/PWM5/FAULT2 or
TIN3 PWM5,
FAULT2
EXT_SYNC/TIN3
or EXT_
SYNC
30
31
V
V
SS
SS
V
V
DD
DD
15
16
21
22
17
18
32 GPIOB0/SCLK/SCL/ANB13/
B0
SCL
SDA
SCLK ANB13
T1
PWM3
PWM3/T1
33 GPIOA4/PWM4/SDA/FAULT1 A4
TIN2 PWM4,
FAULT1
/TIN2
34
35
GPIOE7/CMP1_M3
GPIOA2/PWM2
E7
A2
A3
F0
CMP1_M3
23
24
25
26
27
19
20
21
22
23
PWM2
PWM3
17
18
19
20
36 GPIOA3/PWM3/TXD/EXTAL
TXD
EXTAL
XTAL
37
38
39
40
41
42
43
44
45
GPIOF0/XTAL
V
V
DD
DD
V
V
SS
SS
GPIOF1/CMP1_P3
GPIOF2/CMP0_M3
GPIOF3/CMP0_P3
GPIOA1/PWM1
F1
F2
F3
A1
A0
D0
CMP1_P3
CMP0_M3
CMP0_P3
21
22
23
28
29
30
24
25
26
PWM1
PWM0
GPIOA0/PWM0
TDI/GPIOD0/ANB12/SS/
SS
ANB12
CMP0_OUT TIN2
TDI
TIN2/CMP0_OUT
46
47
48
GPIOC3/EXT_TRIGGER
C3
D3
D1
EXT_
TRGGER
24
25
31
32
27
28
TMS/GPIOD3/ANB11/T1/
ANB11
ANB10
CMP1_OUT
CMP2_OUT
T1
T0
TMS
TDO
CMP1_OUT
TDO/GPIOD1/ANB10/T0/
CMP2_OUT
1
Shielded ADC input.
4.2
Pin Assignment
MC56F8006 and MC56F8002 28-pin small outline IC (28SOIC) assignment is shown in Figure 4; MC56F8006 32-pin
low-profile quad flat pack (32LQFP) is shown in Figure 5; MC56F8006 32-pin plastic shrink dual in-line package (PSDIP) is
shown in Figure 6; MC56F8006 48-pin low-profile quad flat pack (48LQFP) is shown in Figure 7.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
13
Signal/Connection Descriptions
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ANB6 & PGA1– & CMP0_P4/GPIOC5
ANB8 & PGA1+ & CMP0_M2/GPIOC4
GPIOB1/SS/SDA/ANA12 & CMP2_P3
GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN
TDO/GPIOD1/ANB10/T0/CMP2_OUT
TMS/GPIOD3/ANB11/T1/CMP1_OUT
TDI/GPIOD0/ANB12/SS/TIN2/CMP0_OUT
GPIOA0/PWM0
ANB4 & CMP1_P1/GPIOC6/PWM2
V
3
DDA
4
V
SSA
5
ANA9 & PGA0– & CMP2_P4/GPIOC2
ANA7 & PGA0+ & CMP2_M2/GPIOC1
ANA5 and CMP1_M1/GPIOC0/FAULT0
6
7
GPIOA1/PWM1
8
V
SS
V
V
9
SS
DD
TCK/GPIOD2/ANA4 & CMP1_P2/CMP2_OUT
RESET/GPIOA7
10
11
12
13
14
GPIOF0/XTAL
GPIOB3/MOSI/TIN3/ANA3 & ANB3/PWM5/CMP1_OUT
GPIOA6/FAULT0/ANA1 & ANB1/SCL/TXD/CLKO_1
GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0
GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3
GPIOA3/PWM3/TXD/EXTAL
GPIOA4/PWM4/SDA/FAULT1/TIN2
GPIOB0/SCLK/SCL/ANB13/PWM3/T1
Figure 4. Top View, MC56F8006/MC56F8002 28-Pin SOIC Package
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
14
Freescale Semiconductor
Signal/Connection Descriptions
GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN
GPIOB1/SS/SDA/ANA12 & CMP2_P3
GPIOB7/TXD/SCL/ANA11 & CMP2_M3
GPIOB5/T1/FAULT3/SCLK
GPIOA3/PWM3/TXD/EXTAL
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GPIOA2/PWM2
ORIENTATION
MARK
GPIOA4/PWM4/SDA/FAULT1/TIN2
GPIOB0/SCLK/SCL/ANB13/PWM3/T1
ANB8 and PGA1+ & CMP0_M2/GPIOC4
ANB6 and PGA1– & CMP0_P4/GPIOC5
ANB4 & CMP1_P1/GPIOC6/PWM2
GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3
GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0
GPIOA6/FAULT0/ANA1 & ANB1/SCL/TXD/CLKO_1
GPIOB2/MISO/TIN2/ANA2 & ANB2/CMP0_OUT
V
DDA
Figure 5. Top View, MC56F8006 32-Pin LQFP Package
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
15
Signal/Connection Descriptions
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ꢈ
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Figure 6. Top View, MC56F8006 32-Pin PSDIP Package
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
16
Freescale Semiconductor
Signal/Connection Descriptions
36
35
34
33
32
31
30
29
28
27
26
25
GPIOA3/PWM3/TXD/EXTAL
1
GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN
GPIOB1/SS/SDA/ANA12 & CMP2_P3
GPIOB7/TXD/SCL/ANA11 & CMP2_M3
GPIOB5/T1/FAULT3/SCLK
2
GPIOA2/PWM2
GPIOE7/CMP1_M3
3
Orientation Mark
GPIOA4/PWM4/SDA/FAULT1/TIN2
GPIOB0/SCLK/SCL/ANB13/PWM3/T1
4
5
GPIOE0
V
GPIOE1/ANB9 & CMP0_P1
6
DD
Vss
ANB8 and PGA1+ & CMP0_M2/GPIOC4
GPIOE2/ANB7 & CMP0_M1
7
GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3
GPIOE6
8
ANB6 and PGA1– & CMP0_P4/GPIOC5
GPIOC7/ANB5 & CMP1_M2
9
GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0
GPIOA6/FAULT0/ANA1 & ANB1/SCL/TXD/CLKO_1
GPIOB2/MISO/TIN2/ANA2 & ANB2/CMP0_OUT
10
11
12
ANB4 & CMP1_P1/GPIOC6/PWM2
V
DDA
Figure 7. Top View, MC56F8006 48-Pin LQFP Package
4.3
56F8006/56F8002 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed via the
GPIO module’s peripheral enable registers (GPIO_x_PER) and SIM module’s (GPS_xn) GPIO peripheral select registers. If
CLKIN or XTAL is selected as device external clock input, the CLK_MOD bit in the OCCS oscillator control register (OSCTL)
needs to be set too. EXT_SEL bit in OSCTL selects CLKIN or XTAL.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
17
Signal/Connection Descriptions
Table 5. 56F8006/56F8002 Signal and Package Information
32
PSDI
P
State
During
Reset
Signal
Name
28
32
48
LQFP
Type
Signal Description
SOIC LQFP
VDD
VDD
VDD
VSS
VSS
VSS
VDDA
21
31
38
20
30
39
12
Supply
Supply I/O Power — This pin supplies 3.3 V power to the chip I/O interface.
19
8
26
13
22
9
Supply
Supply I/O Ground — These pins provide ground for chip I/O interface.
20
3
27
8
23
4
Supply
Supply
Input
Supply Analog Power — This pin supplies 3.3 V power to the analog
modules. It must be connected to a clean analog power supply.
VSSA
4
9
5
13
23
Supply Analog Ground — This pin supplies an analog ground to the analog
modules. It must be connected to a clean power supply.
RESET
10
15
11
Input, Reset — This input is a direct hardware reset on the processor.
internal When RESET is asserted low, the device is initialized and placed in
pullup the reset state. A Schmitt-trigger input is used for noise immunity.
enabled The internal reset signal is deasserted synchronous with the
internal clocks after a fixed number of internal clocks.
(GPIOA7)
GPIOA0
Input/
Output
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin. RESET functionality is disabled in this mode
and the chip can be reset only via POR, COP reset, or software
reset.
After reset, the default state is RESET.
22
21
29
28
23
25
24
19
44
43
35
Input/
Output
Input, Port A GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
enabled
(PWM0)
GPIOA1
Output
PWM0 — The PWM channel 0.
After reset, the default state is GPIOA0.
Input/
Output
Input, Port A GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
enabled
(PWM1)
GPIOA2
Output
PWM1 — The PWM channel 1.
After reset, the default state is GPIOA1.
Input/
Input, Port A GPIO — This GPIO pin can be individually programmed as
Output
internal an input or output pin.
pullup
enabled
(PWM2)
Output
PWM2 — The PWM channel 2.
After reset, the default state is GPIOA2.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
18
Freescale Semiconductor
Signal/Connection Descriptions
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
32
PSDI
P
State
During
Reset
Signal
Name
28
32
48
LQFP
Type
Signal Description
SOIC LQFP
GPIOA3
17
24
20
36
Input/
Input, Port A GPIO — This GPIO pin can be individually programmed as
Output
internal an input or output pin.
pullup
enabled
(PWM3)
(TXD)
Output
Output
PWM3 — The PWM channel 3.
TXD — The SCI transmit data output or transmit/receive in single
wire operation.
(EXTAL)
Analog
Input
EXTAL — External Crystal Oscillator Input. This input can be
connected to a 32.768 kHz or 1–16 MHz external crystal or ceramic
resonator. When used to supply a source to the internal PLL, the
crystal/resonator must be in the 4 MHz to 8 MHz range. Tie this pin
low or configure as GPIO if XTAL is being driven by an external
clock source.
If using a 32.768 kHz crystal, place the crystal as close as possible
to device pins to speed startup.
After reset, the default state is GPIOA3.
GPIOA4
16
22
18
33
Input/
Output
Input, Port A GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
(PWM4)
(SDA)
Output
enabled PWM4 — The PWM channel 4.
Input/Open-
drain
SDA — The I2C serial data line.
Output
(FAULT1)
(TIN2)
Input
Input
FAULT1 — PWM fault input 1used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
TIN2 — Dual timer module channel 2 input
After reset, the default state is GPIOA4.
GPIOA5
(PWM5)
14
20
16
29
Input/
Output
Input, Port A GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
Output
enabled PWM5 — The PWM channel 5.
(FAULT2/
EXT_SYNC)
Input/
Output
FAULT2 — PWM fault input 2 used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
EXT_SYNC — When not being used as a fault input, this pin can be
used to receive a pulse to reset the PWM counter or to generate a
positive pulse at the start of every PWM cycle.
(TIN3)
Input
TIN3 — Dual timer module channel 3 input
After reset, the default state is GPIOA5.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
19
Signal/Connection Descriptions
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
32
PSDI
P
State
During
Reset
Signal
Name
28
32
48
LQFP
Type
Signal Description
SOIC LQFP
GPIOA6
12
18
14
26
Input/
Output
Input, Port A GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
(FAULT0)
Input
enabled FAULT0 — PWM fault input 0 used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
(ANA1 &
ANB1)
Analog
Input
ANA1 and ANB1 — Analog input to channel 1 of ADCA and ADCB.
SCL — The I2C serial clock
(SCL)
Input/Open-
drain
Output
TXD — The SCI transmit data output or transmit/receive in single
wire operation.
(TXD)
Output
Output
CLKO_1 — This is a buffered clock output; the clock source is
selected by clockout select (CLKOSEL) bits in the clock output
select register (CLKOUT) in the SIM.
(CLKO_1)
When used as an analog input, the signal goes to the ANA1 and
ANB1.
After reset, the default state is GPIOA6.
GPIOB0
(SCLK)
15
21
17
32
Input/
Output
Input, Port B GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
enabled SCLK — The SPI serial clock. In master mode, this pin serves as
an output, clocking slaved listeners. In slave mode, this pin serves
as the data clock input.
Input/
Output
(SCL)
Input/Open-
drain
SCL — The I2C serial clock.
Output
(ANB13)
Analog
Input
ANB13 — Analog input to channel 13 of ADCB
(PWM3)
(T1)
Output
PWM3 — The PWM channel 3.
Input/
Output
T1 — Dual timer module channel 1 input/output.
After reset, the default state is GPIOB0.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
20
Freescale Semiconductor
Signal/Connection Descriptions
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
32
PSDI
P
State
During
Reset
Signal
Name
28
32
48
LQFP
Type
Signal Description
SOIC LQFP
GPIOB1
27
2
30
2
Input/
Output
Input, Port B GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
(SS)
Input/
Output
enabled SS — SS is used in slave mode to indicate to the SPI module that
the current transfer is to be received.
(SDA)
Input/Open-
drain
SDA — The I2C serial data line.
Output
(ANA12 and
CMP2_P3)
Analog
input
ANA12 and CMP2_P3 — Analog input to channel 12 of ADCA and
Positive input 3 of analog comparator 2.
When used as an analog input, the signal goes to the ANA12 and
CMP2_P3.
After reset, the default state is GPIOB1.
GPIOB2
(MISO)
17
13
25
Input/
Output
Input, Port B GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
enabled MISO — Master in/slave out. In master mode, this pin serves as the
data input. In slave mode, this pin serves as the data output. The
MISO line of a slave device is placed in the high-impedance state if
the slave device is not selected.
Input/
Output
(TIN2)
Input/
TIN2 — Dual timer module channel 2 input.
Output
(ANA2 and
ANB2)
Analog
Input
ANA2 and ANB2 — Analog input to channel 2 of ADCA and ADCB.
CMP0_OUT— Analog comparator 0 output.
(CMP0_
OUT)
Output
When used as an analog input, the signal goes to the ANA2 and
ANB2.
After reset, the default state is GPIOB2.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
21
Signal/Connection Descriptions
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
32
PSDI
P
State
During
Reset
Signal
Name
28
32
48
LQFP
Type
Signal Description
SOIC LQFP
GPIOB3
(MOSI)
(TIN3)
11
16
12
24
Input/
Output
Input, Port B GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
enabled MOSI — Master out/slave in. In master mode, this pin serves as the
data output. In slave mode, this pin serves as the data input.
Input/
Output
Input/
TIN3 — Dual timer module channel 3 input.
Output
(ANA3 and
ANB3)
Input
ANA3 and ANB3 — Analog input to channel 3 of ADCA and ADCB.
PWM5 — The PWM channel 5.
(PWM5)
Output
Output
CMP1_OUT— Analog comparator 1 output.
(CMP1_
OUT
When used as an analog input, the signal goes to the ANA3 and
ANB3.
After reset, the default state is GPIOB3.
GPIOB4
(T0)
13
19
15
27
Input/
Output
Input, Port B GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
Input/
enabled T0 — Dual timer module channel 0 input/output.
Output
(CLKO_0)
Output
CLKO_0 — This is a buffered clock output; the clock source is
selected by clockout select (CLKOSEL) bits in the clock output
select register (CLKOUT) of the SIM.
(MISO)
Input/
Output
MISO — Master in/slave out. In master mode, this pin serves as the
data input. In slave mode, this pin serves as the data output. The
MISO line of a slave device is placed in the high-impedance state if
the slave device is not selected.
(SDA)
(RXD)
Input/Open-
drain
SDA — The I2C serial data line.
Output
Input
RXD — The SCI receive data input.
(ANA0 and
ANB0)
Analog
Input
ANA0 and ANB0 — Analog input to channel 0 of ADCA and ADCB.
When used as an analog input, the signal goes to the ANA0 and
ANB0.
After reset, the default state is GPIOB4.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
22
Freescale Semiconductor
Signal/Connection Descriptions
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
32
PSDI
P
State
During
Reset
Signal
Name
28
32
48
LQFP
Type
Signal Description
SOIC LQFP
GPIOB5
4
32
4
Input/
Output
Input, Port B GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
(T1)
Input/
enabled T1 — Dual timer module channel 1 input/output.
Output
(FAULT3)
(SCLK)
Input
Input
FAULT3 — PWM fault input 3 used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
SCLK — SPI serial clock. In master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input.
After reset, the default state is GPIOB5.
GPIOB6
(SDA)
26
1
29
1
Input/
Output
Input, Port B GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
Input/Open- enabled SDA — The I2C serial data line.
drain
Output
(ANA13 and
CMP0_P2)
Analog
Input
ANA13 and CMP0_P2 — Analog input to channel 13 of ADCA and
positive input 2 of analog comparator 0.
(CLKIN)
Input
External Clock Input — This pin serves as an external clock input.
When used as an analog input, the signal goes to the ANA13 and
CMP0_P2.
After reset, the default state is GPIOB6.
GPIOB7
(TXD)
3
31
3
Input/
Output
Input, Port B GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
enabled TXD — The SCI transmit data output or transmit/receive in single
wire operation.
Input/
Output
(SCL)
Input/Open-
drain
SCL — The I2C serial clock.
Output
(ANA11 and
CMP2_M3)
Analog
Input
ANA11 and CMP2_M3 — Analog input to channel 11 of ADCA and
negative input 3 of analog comparator 2.
When used as an analog input, the signal goes to the ANA11 and
CMP2_M3.
After reset, the default state is GPIOB7.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
23
Signal/Connection Descriptions
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
32
PSDI
P
State
During
Reset
Signal
Name
28
32
48
LQFP
Type
Signal Description
SOIC LQFP
ANA5 and
CMP1_M1
7
12
8
19
Analog
Input
Analog ANA5 and CMP1_M1— Analog input to channel 5 of ADCA and
Input negative input 1 of analog comparator 1.
(GPIOC0)
(FAULT0)
Analog
Input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Input
FAULT0 — PWM fault input 0 is used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
When used as an analog input, the signal goes to the ANA5 and
CMP1_M1.
After reset, the default state is ANA5 and CMP1_M1.
ANA7 and
PGA0+ and
CMP2_M2
6
11
7
17
15
46
Analog
Input
Analog ANA7 and PGA0+ and CMP2_M2 — Analog input to channel 7 of
Input ADCA and PGA0 positive input and negative input 2 of analog
comparator 2.
(GPIOC1)
Input/
Output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
When used as an analog input, The signal goes to the ANA7 and
PGA0+ and CMP2_M2.
After reset, the default state is ANA7 and PGA0+ and CMP2_M2.
ANA9 and
PGA0– and
CMP2_P4
5
10
6
Analog
Input
Analog ANA9 and PGA0– and CMP2_P4 — Analog input to channel 9 of
Input ADCA and PGA0 negative input and positive input 4 of analog
comparator 2.
(GPIOC2)
Input/
Output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
When used as an analog input, The signal goes to the ANA9 and
PGA0– and CMP2_P4.
After reset, the default state is ANA9 and PGA0– and CMP2_P4.
GPIOC3
Input/
Output
Input, Port C GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
(EXT_
Input
enabled EXT_TRIGGER — PDB external trigger input.
TRIGGER)
After reset, the default state is GPIOC3.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
24
Freescale Semiconductor
Signal/Connection Descriptions
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
32
PSDI
P
State
During
Reset
Signal
Name
28
32
48
LQFP
Type
Signal Description
SOIC LQFP
ANB8 and
PGA1+ and
CMP0_M2
28
5
6
7
1
2
3
7
Analog
Input
Analog ANB8 and PGA1+ and CMP0_M2 — Analog input to channel 8 of
Input ADCB and PGA1 positive input and negative input 2 of analog
comparator 0.
(GPIOC4)
Input/
Output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
When used as an analog input, the signal goes to the ANB8 and
PGA1+ and CMP0_M2.
After reset, the default state is ANB8 and PGA1+ and CMP0_M2.
ANB6 and
PGA1– and
CMP0_P4
1
9
Input/
Output
Analog ANB6 and PGA1– and CMP0_P4 — Analog input to channel 6 of
Input ADCB and PGA1 negative input and positive input 4 of analog
comparator 0.
(GPIOC5)
Analog
Input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
When used as an analog input, the signal goes to the ANB6 and
PGA1– and CMP0_P4.
After reset, the default state is ANB6 and PGA1– and CMP0_P4.
ANB4 and
CMP1_P1
2
11
Analog
Input
Analog ANB4 and CMP1_P1 — Analog input to channel 4 of ADCB and
Input positive input 1 of analog comparator 1.
(GPIOC6)
(PWM2)
Input/
Output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
PWM2 — The PWM channel 2.
When used as an analog input, the signal goes to the ANB4 and
CMP1_P1.
After reset, the default state is ANB4 and CMP1_P1.
GPIOC7
10
Input/
Input, Port C GPIO — This GPIO pin can be individually programmed as
Output
internal an input or output pin.
pullup
enabled
(ANB5 and
CMP1_M2)
Analog
Input
ANB5 and CMP1_M2 — Analog input to channel 5 of ADCB and
negative input 2 of analog comparator 1.
After reset, the default state is GPIOC7.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
25
Signal/Connection Descriptions
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
32
PSDI
P
State
During
Reset
Signal
Name
28
32
48
LQFP
Type
Signal Description
SOIC LQFP
TDI
23
30
26
45
Input
Input, Test Data Input — This input pin provides a serial input data stream
internal to the JTAG/EOnCE port. It is sampled on the rising edge of TCK
pullup and has an on-chip pullup resistor.
enabled
(GPIOD0)
(ANB12)
(SS)
Input/
Output
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Analog
Input
ANB12 — Analog input to channel 12 of ADCB
Input
SS — SS is used in slave mode to indicate to the SPI module that
the current transfer is to be received.
(TIN2)
Input
TIN2 — Dual timer module channel 2 input.
CMP1_OUT — Analog comparator 1 output.
After reset, the default state is TDI.
(CMP0_
OUT)
Output
TDO
25
32
28
48
Output
Output, Test Data Output — This three-stateable output pin provides a serial
tri-stated, output data stream from the JTAG/EOnCE port. It is driven in the
internal shift-IR and shift-DR controller states, and changes on the falling
pullup edge of TCK.
enabled
(GPIOD1)
(ANB10)
(T0)
Input/
Output
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Analog
Input
ANB10 — Analog input to channel 10 of ADCB.
T0 — Dual timer module channel 0 input/output.
Input/
Output
(CMP2_
OUT)
Output
Input
CMP2_OUT — Analog comparator 2 output.
After reset, the default state is TDO.
TCK
9
14
10
22
Input, Test Clock Input — This input pin provides a gated clock to
internal synchronize the test logic and shift serial data to the JTAG/EOnCE
pullup port. The pin is connected internally to a pullup resistor. A
enabled Schmitt-trigger input is used for noise immunity.
(GPIOD2)
Input/
Output
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(ANA4 and
CMP1_P2)
Analog
Input
ANA4 and CMP1_P2 — Analog input to channel 4 of ADCA and
positive input 2 of analog comparator 1.
(CMP2_
OUT)
Output
CMP2_OUT — Analog comparator 2 output.
After reset, the default state is TCK.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
26
Freescale Semiconductor
Signal/Connection Descriptions
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
32
PSDI
P
State
During
Reset
Signal
Name
28
32
48
LQFP
Type
Signal Description
SOIC LQFP
TMS
24
31
27
47
Input
Input, Test Mode Select Input — This input pin is used to sequence the
internal JTAG TAP controller’s state machine. It is sampled on the rising
pullup edge of TCK and has an on-chip pullup resistor.
enabled
(GPIOD3)
(ANB11)
(T1)
Input/
Output
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Analog
Input
ANB11 — Analog input to channel 11 of ADCB.
T1 — Dual timer module channel 1 input/output.
Input/
Output
(CMP1_
OUT)
Output
CMP1_OUT — Analog comparator 2 output.
After reset, the default state is TMS.
Always tie the TMS pin to VDD through a 2.2 k resistor.
GPIOE0
GPIOE1
5
6
Input/
Output
Input, Port E GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
enabled After reset, the default state is GPIOE0.
Input/
Output
Input, Port E GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
(ANB9 and
CMP0_P1)
Analog
Input
enabled ANB9 and CMP0_P1 — Analog input to channel 9 of ADCB and
positive input 1 of analog comparator 0.
After reset, the default state is GPIOE1.
GPIOE2
8
Input/
Output
Input, Port E GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
(ANB7 and
CMP0_M1)
Analog
Input
enabled ANB7 and CMP0_M1 — Analog input to channel 7 of ADCB and
negative input 1 of analog comparator 0.
After reset, the default state is GPIOE2.
GPIOE3
14
18
Input/
Output
Input, Port E GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
enabled ANA10 and CMP2_M1 — Analog input to channel 10 of ADCA and
negative input 1 of analog comparator 2.
(ANA10 and
CMP2_M1)
Analog
Input
After reset, the default state is GPIOE3.
GPIOE4
Input/
Output
Input, Port E GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
(ANA6 and
CMP2_P2)
Analog
Input
enabled ANA6 and CMP2_P2 — Analog input to channel 6 of ADCA and
positive input 2 of analog comparator 2.
After reset, the default state is GPIOE4.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
27
Signal/Connection Descriptions
Table 5. 56F8006/56F8002 Signal and Package Information (continued)
32
PSDI
P
State
During
Reset
Signal
Name
28
32
48
LQFP
Type
Signal Description
SOIC LQFP
GPIOE5
16
Input/
Output
Input, Port E GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
(ANA8 and
CMP2_P1)
Analog
Input
enabled ANA8 and CMP2_P1— Analog input to channel 8 of ADCA and
positive input 1 of analog comparator 2.
After reset, the default state is GPIOE5.
GPIOE6
28
34
Input/
Output
Input, Port E GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
enable After reset, the default state is GPIOE6.
GPIOE7
Input/
Input, Port E GPIO — This GPIO pin can be individually programmed as
Output
internal an input or output pin
pullup
(CMP1_M3)
Analog
Input
enabled CMP1_M3 — Analog input to both negative input 3 of analog
comparator 1.
After reset, the default state is GPIOE7.
GPIOF0
(XTAL)
18
25
21
37
Input/
Output
Input, Port F GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
enabled XTAL — External Crystal Oscillator Output. This output connects
the internal crystal oscillator output to an external crystal or ceramic
resonator.
Analog
Input/
Output
After reset, the default state is GPIOF0.
GPIOF1
40
41
42
Input/
Output
Input, Port F GPIO — This GPIO pin can be individually programmed as
internal an input or output pin
pullup
enabled CMP1_P3 — Analog input to both positive input 3 of analog
comparator 1.
(CMP1_P3)
Analog
Input
After reset, the default state is GPIOF1
GPIOF2
Input/
Output
Input, Port F GPIO — This GPIO pin can be individually programmed as
internal an input or output pin.
pullup
enabled CMP0_M3 — Analog input to both negative input 3 of analog
comparator 0.
(CMP0_M3)
Analog
Input
After reset, the default state is GPIOF2.
GPIOF3
Input/
Input, Port F GPIO — This GPIO pin can be individually programmed as
Output
internal an input or output pin.
pullup
(CMP0_P3)
Analog
Input
enabled CMP0_P3 — Analog input to both positive input 3 of analog
comparator 0.
After reset, the default state is GPIOF3.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
28
Freescale Semiconductor
Memory Maps
5
Memory Maps
5.1
Introduction
The 56F8006/56F8002 device is based on the 56800E core. It uses a dual Harvard-style architecture with two independent
memory spaces for Data and Program. On-chip RAM is shared by both data and program spaces and flash memory is used only
in program space.
This section provides memory maps for:
•
•
Program address space, including the interrupt vector table
Data address space, including the EOnCE memory and peripheral memory maps
On-chip memory sizes for the device are summarized in Table 6. Flash memories’ restrictions are identified in the “Use
Restrictions” column of Table 6.
Table 6. Chip Memory Configurations
On-Chip Memory
56F8006
56F8002
Use Restrictions
Program Flash
(PFLASH)
8K x 16
or
6K x 16
or
Erase/program via flash interface unit and word writes to CDBW
16 KB
12 KB
Unified RAM (RAM)
1K x 16
or
1K x 16
or
Usable by the program and data memory spaces
2 KB
2 KB
5.2
Program Map
The 56F8006/56F8002 series provide up to 16 KB on-chip flash memory. It primarily accesses through the program memory
buses (PAB; PDB). PAB is used to select program memory addresses; instruction fetches are performed over PDB. Data can be
read and written to program memory space through primary data memory buses: CDBW for data write and CDBR for data read.
Accessing program memory space over the data memory buses takes longer access time compared to accessing data memory
space. The special MOVE instructions are provided to support these accesses. The benefit is that non time critical constants or
tables can be stored and accessed in program memory.
The program memory map is shown in Table 7 and Table 8.
1
Table 7. Program Memory Map for 56F8006 at Reset
Begin/End Address
Memory Allocation
P: 0x1F FFFF
P: 0x00 8800
RESERVED
P: 0x00 83FF
P: 0x00 8000
On-Chip RAM2: 2 KB
RESERVED
P: 0x00 7FFF
P: 0x00 2000
P: 0x00 1FFF
P: 0x00 0000
• Internal program flash: 16 KB
• Interrupt vector table locates from 0x00 0000 to 0x00 0065
• COP reset address = 0x00 0002
• Boot location = 0x00 0000
1
2
All addresses are 16-bit word addresses.
This RAM is shared with data space starting at address X: 0x00 0000; see Figure 8.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
29
Memory Maps
1
Table 8. Program Memory Map for 56F8002 at Reset (continued)
Begin/End Address Memory Allocation
P: 0x1F FFFF
P: 0x00 8800
RESERVED
P: 0x00 83FF
P: 0x00 8000
On-Chip RAM2: 2 KB
RESERVED
P: 0x00 7FFF
P: 0x00 2000
P: 0x00 1FFF
P: 0x00 0800
• Internal program flash: 12 KB
• Interrupt vector table locates from 0x00 0800 to 0x00 0865
• COP reset address = 0x00 0802
• Boot location = 0x00 0800
P: 0x00 07FF
P: 0x00 0000
RESERVED
1
All addresses are 16-bit word addresses.
2
This RAM is shared with data space starting at address X: 0x00 0000; see Figure 9.
5.3
Data Map
The 56F8006/56F8002 series contain a dual access memory. It can be accessed from core primary data buses (XAB1; CDBW;
CDBR) and secondary data buses (XAB2; XDB2). Addresses in data memory are selected on the XAB1 and XAB2 buses. Byte,
word, and long data transfers occur on the 32-bit CDBR and CDBW buses. A second 16-bit read operation can be performed
in parallel on the XDB2 bus.
Peripheral registers and on-chip JTAG/EOnCE controller registers are memory-mapped into data memory access. A special
direct address mode is supported for accessing a first 64-location in data memory by using a single word instruction.
The data memory map is shown in Table 9.
1
Table 9. Data Memory Map
Begin/End Address
Memory Allocation
X:0xFF FFFF
X:0xFF FF00
EOnCE
256 locations allocated
X:0xFF FEFF
X:0x01 0000
RESERVED
X:0x00 FFFF
X:0x00 F000
On-Chip Peripherals
4096 locations allocated
X:0x00 EFFF
X:0x00 8800
RESERVED
RESERVED
RESERVED
X:0x00 87FF
X:0x00 8000
X:0x00 7FFF
X:0x00 0400
X:0x00 03FF
X:0x00 0000
On-Chip Data RAM
2 KB2
1
2
All addresses are 16-bit word addresses.
This RAM is shared with Program space starting at P: 0x00 8000. See Figure 8 and
Figure 9.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
30
Freescale Semiconductor
Memory Maps
On-chip RAM is also mapped into program space starting at P: 0x00 8000. This makes for easier online reprogramming of
on-chip flash.
Program
Data
EOnCE
0xFF FF00
Reserved
Reserved
0x00 8400
0x00 8000
RAM
0x01 0000
0x00 F000
0x00 0400
0x00 0000
Peripherals
Reserved
RAM
Dual Port RAM
Reserved
Flash
0x00 2000
0x00 0000
Figure 8. 56F8006 Dual Port RAM Map
Program
Data
EOnCE
0xFF FF00
Reserved
Reserved
0x00 8400
0x00 8000
RAM
0x01 0000
0x00 F000
0x00 0400
0x00 0000
Peripherals
Reserved
RAM
Reserved
Dual Port RAM
0x00 2000
Flash
0x00 0800
0x00 0000
Reserved
Figure 9. 56F8002 Dual Port RAM Map
5.4
Interrupt Vector Table and Reset Vector
The location of the vector table is determined by the vector base address register (VBA). The value in this register is used as
the upper 14 bits of the interrupt vector VAB[20:0]. The lower seven bits are determined based on the highest priority interrupt
and are then appended onto VBA before presenting the full VAB to the core. Please see the MC56F8006 Peripheral Reference
Manual for detail. The reset startup addresses of 56F8002 and 56F8006 are different.
•
56F8006 startup address is located at 0x00 0000. The reset value of VBA is reset to a value of 0x0000 that corresponds
to address 0x00 0000
•
56F8002 startup address is located at 0x00 0800. The reset value of VBA is reset to a value of 0x0010 that corresponds
to address 0x00 0800
By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these
instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR
instructions.
The highest number vector, a user assignable vector USER6 (vector 50), can be defined as a fast interrupt if the instruction
located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference
Manual for detail.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
31
Memory Maps
Table 43 provides the 56F8006/56F8002’s reset and interrupt priority structure, including on-chip peripherals.
5.5
Peripheral Memory-Mapped Registers
The locations of on-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be
accessed with the same addressing modes used for ordinary data memory, except all peripheral registers should be read or
written using word accesses only.
Table 10 summarizes the base addresses for the set of peripherals on the 56F8006/56F8002 devices. Peripherals are listed in
order of the base address.
Table 10. Data Memory Peripheral Base Address Map Summary
Peripheral
Prefix
Base Address
Dual Channel Timer
PWM Module
TMR
PWM
INTC
ADCA
ADCB
PGA0
PGA1
SCI
X:0x00 F000
X:0x00 F020
X:0x00 F040
X:0x00 F060
X:0x00 F080
X:0x00 F0A0
X:0x00 F0C0
X:0x00 F0E0
X:0x00 F100
X:0x00 F120
X:0x00 F140
X:0x00 F160
X:0x00 F180
X:0x00 F1A0
X:0x00 F1C0
X:0x00 F1E0
X:0x00 F200
X:0x00 F220
X:0x00 F240
X:0x00 F260
X:0x00 F280
X:0x00 F2A0
X:0x00 F2C0
X:0x00 F2E0
X:0x00 F300
X:0x00 F320
X:0x00 F400
Interrupt Controller
ADCA
ADCB
Programmable Gain Amplifier 0
Programmable Gain Amplifier 1
SCI
SPI
SPI
I2C
I2C
Computer Operating Properly
On-Chip Clock Synthesis
GPIO Port A
COP
OCCS
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
SIM
GPIO Port B
GPIO Port C
GPIO Port D
GPIO Port E
GPIO Port F
System Integration Module
Power Management Controller
Analog Comparator 0
Analog Comparator 1
Analog Comparator 2
Programmable Interval Timer
Programmable Delay Block
Real Timer Clock
Flash Memory Interface
PMC
CMP0
CMP1
CMP2
PIT
PDB
RTC
FM
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
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Freescale Semiconductor
Memory Maps
5.6
EOnCE Memory Map
Control registers of the EOnCE are located at the top of data memory space. These locations are fixed by the 56F800E core.
These registers can also be accessed through JTAG port if flash security is not set. Table 11 lists all EOnCE registers necessary
to access or control the EOnCE.
Table 11. EOnCE Memory Map
Address
Register Acronym
Register Name
X:0xFF FFFF
OTX1/ORX1
Transmit Register Upper Word
Receive Register Upper Word
X:0xFF FFFE
OTX/ORX
(32 bits)
Transmit Register
Receive Register
X:0xFF FFFD
X:0xFF FFFC
OTXRXSR
OCLSR
Transmit and Receive Status and Control Register
Core Lock/Unlock Status Register
Reserved
X:0xFF FFFB–
X:0xFF FFA1
X:0xFF FFA0
OCR
Control Register
X:0xFF FF9F–
X:0xFF FF9E
OSCNTR
(24 bits)
Instruction Step Counter
X:0xFF FF9D
X:0xFF FF9C
X:0xFF FF9B
X:0xFF FF9A
OSR
Status Register
OBASE
OTBCR
OTBPR
Peripheral Base Address Register
Trace Buffer Control Register
Trace Buffer Pointer Register
Trace Buffer Register Stages
X:0xFF FF99–
X:0xFF FF98
OTB
(21–24 bits/stage)
X:0xFF FF97–
X:0xFF FF96
OBCR
(24 bits)
Breakpoint Unit Control Register
Breakpoint Unit Address Register 1
Breakpoint Unit Address Register 2
Breakpoint Unit Mask Register 2
X:0xFF FF95–
X:0xFF FF94
OBAR1
(24 bits)
X:0xFF FF93–
X:0xFF FF92
OBAR2 (32 bits)
X:0xFF FF91–
X:0xFF FF90
OBMSK (32 bits)
X:0xFF FF8F
X:0xFF FF8E
X:0xFF FF8D
X:0xFF FF8C
X:0xFF FF8B
X:0xFF FF8A
Reserved
EOnCE Breakpoint Unit Counter
Reserved
OBCNTR
OESCR
Reserved
Reserved
External Signal Control Register
Reserved
X:0xFF FF89 –
X:0xFF FF00
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
33
General System Control Information
6
General System Control Information
6.1
Overview
This section discusses power pins, reset sources, interrupt sources, clock sources, the system integration module (SIM), ADC
synchronization, and JTAG/EOnCE interfaces.
6.2
Power Pins
V
, V and V
, V
are the primary power supply pins for the devices. This voltage source supplies power to all on-chip
DD SS
DDA SSA
peripherals, I/O buffer circuitry and to internal voltage regulators. Device has multiple internal voltages provide regulated
lower-voltage source for the peripherals, core, memory, and on-chip relaxation oscillators.
Typically, there are at least two separate capacitors across the power pins to bypass the glitches and provide bulk charge storage.
In this case, there should be a bulk electrolytic or tantalum capacitor, such as a 10 F tantalum capacitor, to provide bulk charge
storage for the overall system and a 0.1 F ceramic bypass capacitor located as near to the device power pins as practical to
suppress high-frequency noise. Each pin must have a bypass capacitor for best noise suppression.
V
and V are the analog power supply pins for the device. This voltage source supplies power to the ADC, PGA, and
SSA
DDA
CMP modules. A 0.1 F ceramic bypass capacitor should be located as near to the device V
and V
pins as practical to
DDA
SSA
suppress high-frequency noise. V
and V
are also the voltage reference high and voltage reference low inputs,
DDA
SSA
respectively, for the ADC module.
6.3
Reset
Resetting the device provides a way to start processing from a known set of initial conditions. During reset, most control and
status registers are forced to initial values and the program counter is loaded from the reset vector. On-chip peripheral modules
are disabled and I/O pins are initially configured as the reset status shown in Table 5. The 56F8006/56F8002 has the following
sources for reset:
•
•
•
•
•
•
•
Power-on reset (POR)
Partial power down reset (PPD)
Low-voltage detect (LVD)
External pin reset (EXTR)
Computer operating properly loss of reference reset (COP_LOR)
Computer operating properly time-out reset (COP_CPU)
Software Reset (SWR)
Each of these sources has an associated bit in the reset status register (RSTAT) in the system integration module (SIM).
The external pin reset function is shared with an GPIO port A7 on the RESET/GPIOA7 pin. The reset function is enabled
following any reset of the device. Bit 7 of GPIOA_PER register must be cleared to use this pin as an GPIO port pin. When
enabled as the RESET pin, an internal pullup device is automatically enabled.
6.4
On-chip Clock Synthesis
The on-chip clock synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal, or an
external clock to run 56F8000 family devices at user-selectable frequencies up to 32 MHz.
The features of OCCS module include:
•
•
•
Ability to power down the internal relaxation oscillator or crystal oscillator
Ability to put the internal relaxation oscillator into standby mode
Ability to power down the PLL
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
34
Freescale Semiconductor
General System Control Information
Provides a 3X system clock that operates at three times the system clock to PWM, timer, and SCI modules
•
•
•
Safety shutdown feature is available if the PLL reference clock is lost
Can be driven from an external clock source
The clock generation module provides the programming interface for the PLL, internal relaxation oscillator, and crystal
oscillator. It also provides a postscaler to divide clock frequency down by 1, 2, 4, 8, 16, 32, 64, 128, 256 before feeding to the
SIM. The SIM is responsible for further dividing these frequencies by two, which ensures a 50% duty cycle in the system clock
output. For detail, see the OCCS chapter in the MC56F8006 Peripheral Reference Manual.
6.4.1
Internal Clock Source
An internal relaxation oscillator can supply the reference frequency when an external frequency source or crystal is not used. It
is optimized for accuracy and programmability while providing several power-saving configurations that accommodate
different operating conditions. The internal relaxation oscillator has little temperature and voltage variability. To optimize
power, the internal relaxation oscillator supports a run state (8 MHz), standby state (400 kHz), and a power-down state.
During a boot or reset sequence, the relaxation oscillator is enabled by default (the PRECS bit in the PLLCR word is set to 0).
Application code can then also switch to the external clock source and power down the internal oscillator, if desired. If a
changeover between internal and external clock sources is required at power-on, ensure that the clock source is not switched
until the desired external clock source is enabled and stable.
To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally
adjusted to within + 0.078% of 8 MHz by trimming an internal capacitor. Bits 0–9 of the OSCTL (oscillator control) register
allow you to set in an additional offset (trim) to this preset value to increase or decrease capacitance. Each unit added or
subtracted changes the output frequency by about 0.078% of 8 MHz, allowing incremental adjustment until the desired
frequency accuracy is achieved.
The center frequency of the internal oscillator is calibrated at the factory to 8 MHz and the TRIM value is stored in the flash
information block and loaded to the FMOPT1 register at reset. When using the relaxation oscillator, the boot code should read
the FMOPT1 register and set this value as OSCTL TRIM. For further information, see the MC56F8006 Peripheral Reference
Manual.
6.4.2
Crystal Oscillator/Ceramic Resonator
The internal crystal oscillator circuit is designed to interface with a parallel-resonant crystal resonator in the frequency range,
specified for the external crystal, of 32.768 kHz (Typ) or 1–16 MHz. A ceramic resonator can be substituted for the 1–16 MHz
range. When used to supply a source to the internal PLL, the recommended crystal/resonator is in the 4 MHz to 8 MHz
(recommend 8 MHz) range to achieve optimized PLL performance. Oscillator circuits are shown in Figure 10, Figure 11, and
Figure 12. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal parameters determine the
component values required to provide maximum stability and reliable start-up. The load capacitance values used in the
oscillator circuit design should include all stray layout capacitances. The crystal and associated components should be mounted
as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. When using
low-frequency, low-power mode, the only external component is the crystal itself. In the other oscillator modes, load capacitors
(Cx, Cy) and feedback resistor (R ) are required. In addition, a series resistor (R ) may be used in high-gain modes.
F
S
Recommended component values are listed in Table 28.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
35
General System Control Information
56F8002/56F8006
XTAL
EXTAL
Crystal Frequency = 32–38.4 kHz
Figure 10. Typical Crystal Oscillator Circuit: Low-Range, Low-Power Mode
56F8002/56F8006
XTAL
EXTAL
Crystal Frequency = 1–16 MHz
RF
C1
C2
Figure 11. Typical Crystal or Ceramic Resonator Circuit: High-Range, Low-Power Mode
56F8002/56F8006
XTAL
EXTAL
RS
Low Range: Crystal Frequency = 32–38.4 kHz
or
High Range: Crystal Frequency = 1–16 MHz
RF
C1
C2
Figure 12. Typical Crystal or Ceramic Resonator Circuit: Low Range and High Range, High-Gain Mode
6.4.3
External Clock Input — Crystal Oscillator Option
The recommended method of connecting an external clock is illustrated in Figure 13. The external clock source is connected to
XTAL and the EXTAL pin is grounded or configured as GPIO while CLK_MOD bit in OSCTL register is set. The external
clock input must be generated using a relatively low impedance driver with maximum frequency less than 8 MHz.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
36
Freescale Semiconductor
General System Control Information
56F8006/56F8002
CLK_MOD = 1
XTAL
EXTAL
External Clock
(<50 MHz)
GND or GPIO
Figure 13. Connecting an External Clock Signal Using XTAL
6.4.4
Alternate External Clock Input
The recommended method of connecting an external clock is illustrated in Figure 14. The external clock source is connected
to GPIOB6/RXD/SDA/ANA13 and CMP0_P2/CLKIN while EXT_SEL bit in OSCTL register is set and corresponding bits in
GPIOB_PER register GPIO module and GPSB1 register in the system integration module (SIM) are set to the correct values.
The external clock input must be generated using a relatively low impedance driver with maximum frequency not greater than
64 MHz.
EXT_SEL = 1;
56F8002/56F8006
GPIO_B_PER[6] = 0;
GPS_B6 = 11
GPIOB6/RXD/SDA/ANA13 and CMP0_P2/CLKIN
External Clock ( 64 MHz)
Figure 14. Connecting an External Clock Signal Using GPIO
6.5
Interrupt Controller
The 56F8006/56F8002 interrupt controller (INTC) module arbitrates the various interrupt requests (IRQs). The INTC signals
to the 56800E core when an interrupt of sufficient priority exists and what address to jump to to service this interrupt.
The interrupt controller contains registers that allow up to three interrupt sources to be set to priority level 1 and other up to
three interrupt sources to be set to priority level 2. By default, all peripheral interrupt sources are set to priority level 0. Next,
all of the interrupt requests of a given level are priority encoded to determine the lowest numeric value of the active interrupt
requests for that level. Within a given priority level, the lowest vector number is the highest priority and the highest vector
number is the lowest.
The highest vector number, a user assignable vector USER6 (vector 50), can be defined as a fast interrupt if the instruction
located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference
Manual for detail.
6.6
System Integration Module (SIM)
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets
and clocks and provides a number of control features including the pin muxing control; inter-module connection control (for
example connecting comparator output to PWM fault input); individual peripheral enable/disable; PWM, timer, and SCI clock
rate control; enabling peripheral operation in stop mode; port configuration overwrite protection. For further information, see
the MC56F8006 Peripheral Reference Manual.
The SIM is responsible for the following functions:
•
•
•
•
Chip reset sequencing
Core and peripheral clock control and distribution
Stop/wait mode control
System status control
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
37
General System Control Information
•
•
•
•
•
•
•
•
•
•
•
•
•
Registers containing the JTAG ID of the chip
Controls for programmable peripheral and GPIO connections
Peripheral clocks for TMR and PWM and SCI with a high-speed (3X) option
Power-saving clock gating for peripherals
Controls the enable/disable functions of large regulator standby mode with write protection capability
Permits selected peripherals to run in stop mode to generate stop recovery interrupts
Controls for programmable peripheral and GPIO connections
Software chip reset
I/O short address base location control
Peripheral protection control to provide runaway code protection for safety-critical applications
Controls output of internal clock sources to CLKO pin
Four general-purpose software control registers are reset only at power-on
Peripherals stop mode clocking control
6.7
PWM, PDB, PGA, and ADC Connections
The comparators, timers, and PWM_reload_sync output can be connected to the programmable delay block (PDB) trigger input.
The PDB pre-trigger A and trigger A outputs are connected to the ADCA and PGA0 hardware trigger inputs. The PDB
pre-trigger B and trigger B outputs are connected to the ADCB and PGA1 hardware trigger inputs. When the input trigger of
PDB is asserted, PDB trigger and pre-trigger outputs are asserted after a delay of a pre-programmed period. See the MC56F8006
Peripheral Reference Manual for additional information.
CMP0 CMP1 CMP2 PWM
EXT TMR0 TMR1
SW
Trigger0
Trigger1
Trigger2
Trigger3
Trigger4
Trigger5
Trigger6
Trigger7
System
Clock
Programmable Delay Block (PDB)
Pre-
Pre-
TriggerA
TriggerA
TriggerB TriggerB
SSEL[1]
SSEL[1]
SSEL[0]
SSEL[0]
ADCA
Trigger
ADCB
Trigger
ADCA
ADCB
ADHWT
ANA15
ADHWT
ANB15
ANB6
ANA7 ANA9
ANB8
PGA0 Controller
PGA1 Controller
Figure 15. Synchronization of ADC, PDB
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
38
Freescale Semiconductor
Security Features
Each ADC contains a temperature sensor. Outputs of temperature sensors, PGAs, on-chip regulators and VDDA are internally
routed to ADC inputs.
•
•
•
•
•
•
•
•
•
•
•
•
•
Internal PGA0 output available on ANA15
Internal PGA0 positive input calibration voltage available on ANA16
Internal PGA0 negative input calibration voltage available on ANA17
Internal PGA1 output available on ANB15
Internal PGA1 positive input calibration voltage available on ANB16
Internal PGA1 negative input calibration voltage available on ANB17
ADCA temperature sensor available on ANA26
ADCB temperature sensor available on ANB26
Output of on-chip digital voltage regulator is routed to ANA24
Output of on-chip analog voltage regulator is routed to ANA25
Output of on-chip small voltage regulator for ROSC is routed to ANB24
Output of on-chip small voltage regulator for PLL is routed to ANB25
VDDA is routed to ANA27 and ANB27
6.8
Joint Test Action Group (JTAG)/Enhanced On-Chip Emulator
(EOnCE)
The DSP56800E Family includes extensive integrated support for application software development and real-time debugging.
Two modules, the Enhanced On-Chip Emulation module (EOnCE) and the core test access port (TAP, commonly called the
JTAG port), work together to provide these capabilities. Both are accessed through a common 4-pin JTAG/EOnCE interface.
These modules allow you to insert the 56F8006/56F8002 into a target system while retaining debug control. This capability is
especially important for devices without an external bus, because it eliminates the need for a costly cable to bring out the
footprint of the chip, as is required by a traditional emulator system.
The DSP56800E EOnCE module is a Freescale-designed module used to develop and debug application software used with the
chip. This module allows non-intrusive interaction with the CPU and is accessible through the pins of the JTAG interface or by
software program control of the DSP56800E core. Among the many features of the EOnCE module is the support for data
communication between the controller and the host software development and debug systems in real-time program execution.
Other features allow for hardware breakpoints, the monitoring and tracking of program execution, and the ability to examine
and modify the contents of registers, memory, and on-chip peripherals, all in a special debug environment. No user-accessible
resources need to be sacrificed to perform debugging operations.
The DSP56800E JTAG port is used to provide an interface for the EOnCE module to the DSP JTAG pins. Joint Test Action
Group (JTAG) boundary scan is an IEEE 1149.1 standard methodology enabling access to test features using a test access port
(TAP). A JTAG boundary scan consists of a TAP controller and boundary scan registers. Please contact your Freescale sales
representative or authorized distributor for device-specific BSDL information.
NOTE
In normal operation, an external pullup on the TMS pin is highly recommend to place the
JTAG state machine in reset state if this pin is not configured as GPIO.
7
Security Features
The 56F8006/56F8002 offers security features intended to prevent unauthorized users from reading the contents of the flash
memory (FM) array. The 56F8006/56F8002’s flash security consists of several hardware interlocks that prevent unauthorized
users from gaining access to the flash array.
After flash security is set, an authorized user can be enabled to access on-chip memory if a user-defined software subroutine,
which reads and transfers the contents of internal memory via peripherals, is included in the application software. This
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
39
Security Features
application software could communicate over a serial port, for example, to validate the authenticity of the requested access, then
grant it until the next device reset. The inclusion of such a back door technique is at the discretion of the system designer.
7.1
Operation with Security Enabled
After you have programmed flash with the application code, or as part of the programming of the flash with the application
code, the 56F8006/56F8002 can be secured by programming the security word, 0x0002, into program memory location 0x00
1FF7. This can also be effected by use of the CodeWarrior IDE menu flash lock command. This nonvolatile word keeps the
device secured after reset, caused, for example, by a power-down of the device. Refer to the flash memory chapter in the
MC56F8006 Peripheral Reference Manual for detail. When flash security mode is enabled, the 56F8006/56F8002 disables the
core EOnCE debug capabilities. Normal program execution is otherwise unaffected.
7.2
Flash Access Lock and Unlock Mechanisms
There are several methods that effectively lock or unlock the on-chip flash.
7.2.1
Disabling EOnCE Access
On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU. The
TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the
device boots, the chip-level JTAG TAP (test access port) is active and provides the chip’s boundary scan capability and access
to the ID register, but proper implementation of flash security blocks any attempt to access the internal flash memory via the
EOnCE port when security is enabled. This protection is effective when the device comes out of reset, even prior to the
execution of any code at startup.
7.2.2
Flash Lockout Recovery Using JTAG
If the device is secured, one lockout recovery mechanism is the complete erasure of the internal flash contents, including the
configuration field, thus disabling security (the protection register is cleared). This does not compromise security, as the entire
contents of your secured code stored in flash are erased before security is disabled on the device on the next reset or power-up
sequence.
To start the lockout recovery sequence via JTAG, the JTAG public instruction (LOCKOUT_RECOVERY) must first be shifted
into the chip-level TAP controller’s instruction register. After the LOCKOUT_RECOVERY instruction has been shifted into
the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. After the data register
has been updated, you must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to
commence. The controller must remain in this state until the erase sequence is complete. Refer to the MC56F8006 Peripheral
Reference Manual for detail, or contact Freescale.
NOTE
After the lockout recovery sequence has completed, you must reset the JTAG TAP
controller and device to return to normal unsecured operation. Power-on reset resets both
too.
7.2.3
Flash Lockout Recovery Using CodeWarrior
CodeWarrior can unlock a device by selecting the Debug menu, then selecting DSP56800E, followed by Unlock Flash. Another
mechanism is also built into CodeWarrior using the device’s memory configuration file. The command
“Unlock_Flash_on_Connect 1” in the .cfg file accomplishes the same task as using the Debug menu.
This lockout recovery mechanism is the complete erasure of the internal flash contents, including the configuration field, thus
disabling security (the protection register is cleared).
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
40
Freescale Semiconductor
Specifications
7.2.4
Flash Lockout Recovery without Mass Erase
7.2.4.1
Without Presenting Back Door Access Keys to the Flash Unit
A user can un-secure a secured device by programming the word 0x0000 into program flash location 0x00 1FF7. After
completing the programming, the JTAG TAP controller and the device must be reset to return to normal unsecured operation.
You are responsible for directing the device to invoke the flash programming subroutine to reprogram the word 0x0000 into
program flash location 0x00 1FF7. This is done by, for example, toggling a specific pin or downloading a user-defined key
through serial interfaces.
NOTE
Flash contents can be programmed only from 1s to 0s.
7.2.4.2
Presenting Back Door Access Key to the Flash Unit
It is possible to temporarily bypass the security through a back door access scheme, using a 4-word key, to temporarily unlock
of the flash. A back door access requires support from the embedded software. This software would typically permit an external
user to enter a four word code through one of the communications interfaces and then use it to attempt the unlock sequence. If
your input matches the four word code stored at location 0x00 1FFC–0x00 1FFF in the flash memory, the part immediately
becomes unsecured (at runtime) and you can access internal memory via JTAG/EOnCE port. Refer to the MC56F8006
Peripheral Reference Manual for detail. The key must be entered in four consecutive accesses to the flash, so this routine should
be designed to run in RAM.
7.3
Product Analysis
The recommended method of unsecuring a secured device for product analysis of field failures is via the method described in
Section 7.2.4.2, “Presenting Back Door Access Key to the Flash Unit.” The customer would need to supply technical support
with the details of the protocol to access the subroutines in flash memory. An alternative method for performing analysis on a
secured device would be to mass-erase and reprogram the flash with the original code, but modify the security word or not
program the security word.
8
Specifications
8.1
General Characteristics
The 56F8006/56F8002 is fabricated in high-density low power and low leakage CMOS with a maximum voltage of 3.6 V digital
inputs during normal operation without causing damage.
Absolute maximum ratings in Table 12 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress
beyond these ratings may affect device reliability or cause permanent damage to the device.
Unless otherwise stated, all specifications within this chapter apply over the temperature range of –40ºC to 105ºC ambient
temperature over the following supply ranges: V = V
= 0V, V = V
= 3.0–3.6 V, CL < 50 pF, f = 32 MHz
SS
SSA
DD
DDA OP
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage
or electrical fields. However, normal precautions are advised to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate voltage level.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
41
Specifications
8.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified Table 12 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, take normal
precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either V or V ) or the
SS
DD
programmable pullup resistor associated with the pin is enabled.
Table 12. Absolute Maximum Ratings
(VSS = 0 V, VSSA = 0 V)
Characteristic
Symbol
Notes
Min
Max
Unit
Supply Voltage Range
Analog Supply Voltage Range
Voltage difference VDD to VDDA
Voltage difference VSS to VSSA
Digital Input Voltage Range
VDD
VDDA
VDD
VSS
VIN
–0.3
–0.3
–0.3
–0.3
–0.3
TBD
–0.3
—
3.8
3.6
V
V
0.3
V
0.3
V
Pin Groups 1, 2
Pin Group 4
VDD+0.3
TBD
3.6
V
Oscillator Voltage Range
VOSC
VINA
VIC
V
Analog Input Voltage Range
Pin Group 3
V
Input clamp current, per pin (VIN < 0)1 2 3
Output clamp current, per pin (VO < 0)1 2 3
–25.0
–20.0
VDD
mA
mA
V
VOC
—
Output Voltage Range
VOUT
Pin Group 1
–0.3
(Normal Push-Pull mode)
Ambient Temperature
Industrial
TA
–40
–55
105
150
°C
°C
Storage Temperature Range
(Extended Industrial)
TSTG
1
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values.
2
3
All functional non-supply pins are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD loads shunt current greater than maximum injection
current. This is the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present or if the
clock rate is low (which would reduce overall power consumption).
8.2.1
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, use
normal handling precautions to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices
can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM), and the
charge device model (CDM).
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
42
Freescale Semiconductor
Specifications
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 13. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
Series Resistance
Storage Capacitance
R1
C
1500
100
3
Human
Body
pF
Number of Pulses per Pin
Series Resistance
—
R1
C
0
Machine
Latch-up
Storage Capacitance
200
3
pF
Number of Pulses per Pin
Minimum inpUt Voltage Limit
Maximum Input Voltage Limit
—
–2.5
7.5
V
V
Table 14. 56F8006/56F8002 ESD Protection
Characteristic 1
Min
Typ
Max
Unit
ESD for Human Body Model (HBM)
ESD for Machine Model (MM)
2000
200
—
—
—
—
—
—
V
V
ESD for Charge Device Model (CDM)
750
V
Latch-up current at TA= 85oC (ILAT
)
100
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices un-
der typical conditions unless otherwise noted.
8.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine
I/O
the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of
SS
DD
unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very small.
SS
DD
Table 15. 28SOIC Package Thermal Characteristics
Value
(LQFP)
Characteristic
Comments
Symbol
Unit
Junction to ambient
Natural convection
Single layer board
(1s)
RJA
RJMA
RJMA
70
47
55
°C/W
°C/W
°C/W
Junction to ambient
Natural convection
Four layer board
(2s2p)
Junction to ambient
(@200 ft/min)
Single layer board
(1s)
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
43
Specifications
Table 15. 28SOIC Package Thermal Characteristics (continued)
Value
Characteristic
Comments
Symbol
Unit
(LQFP)
Junction to ambient
(@200 ft/min)
Four layer board
(2s2p)
RJMA
42
°C/W
Junction to board
Junction to case
RJB
RJC
JT
23
26
9
°C/W
°C/W
°C/W
Junction to package top
Natural Convection
Table 16. 32LQFP Package Thermal Characteristics
Value
(LQFP)
Characteristic
Comments
Symbol
Unit
Junction to ambient
Natural convection
Single layer board
(1s)
RJA
84
56
70
49
°C/W
°C/W
°C/W
°C/W
Junction to ambient
Natural convection
Four layer board
(2s2p)
RJMA
RJMA
RJMA
Junction to ambient
(@200 ft/min)
Single layer board
(1s)
Junction to ambient
(@200 ft/min)
Four layer board
(2s2p)
Junction to board
Junction to case
RJB
RJC
JT
33
20
4
°C/W
°C/W
°C/W
Junction to package top
Natural convection
Table 17. 32PSDIP Package Thermal Characteristics
Value
(LQFP)
Characteristic
Comments
Symbol
Unit
Junction to ambient
Natural convection
Single layer board
(1s)
RJA
56
41
45
36
°C/W
°C/W
°C/W
°C/W
Junction to ambient
Natural convection
Four layer board
(2s2p)
RJMA
RJMA
RJMA
Junction to ambient
(@200 ft/min)
Single layer board
(1s)
Junction to ambient
(@200 ft/min)
Four layer board
(2s2p)
Junction to board
Junction to case
RJB
RJC
JT
18
24
10
°C/W
°C/W
°C/W
Junction to package top
Natural convection
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
44
Freescale Semiconductor
Specifications
Table 18. 48LQFP Package Thermal Characteristics
Value
(LQFP)
Characteristic
Comments
Symbol
Unit
Junction to ambient
Natural convection
Single layer board
(1s)
RJA
79
55
66
48
°C/W
°C/W
°C/W
°C/W
Junction to ambient
Natural convection
Four layer board
(2s2p)
RJMA
RJMA
RJMA
Junction to ambient
(@200 ft/min)
Single layer board
(1s)
Junction to ambient
(@200 ft/min)
Four layer board
(2s2p)
Junction to board
Junction to case
RJB
RJC
JT
34
20
4
°C/W
°C/W
°C/W
Junction to package top
Natural Convection
NOTE
Junction-to-ambient thermal resistance determined per JEDEC JESD51–3 and JESD51–6.
Thermal test board meets JEDEC specification for this package.
Junction-to-board thermal resistance determined per JEDEC JESD51–8. Thermal test
board meets JEDEC specification for the specified package.
Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1.
The cold plate temperature is used for the case temperature. Reported value includes the
thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between the
package top and the junction temperature per JEDEC JESD51–2. When Greek letters are
not available, the thermal characterization parameter is written as Psi-JT
Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power
dissipation of other components on the board, and board thermal resistance.
See Section 9.1, “Thermal Design Considerations,” for more detail on thermal design
considerations.
8.4
Recommended Operating Conditions
This section includes information about recommended operating conditions.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
45
Specifications
Table 19. Recommended Operating Conditions
(V
= 0 V, V
= 0 V, V = 0 V)
REFL x
SSA
SS
Characteristic
Symbol
Notes
Min
Typ
Max
Unit
Supply voltage
VDD, VDDA
VDD
3
3.3
0
3.6
0.1
0.1
V
V
V
Voltage difference VDD to VDDA
Voltage difference VSS to VSSA
–0.1
–0.1
VSS
0
Device Clock Frequency
Using relaxation oscillator
Using external clock source
FSYSCLK
1
0
32
32
MHz
Input Voltage High (digital inputs)
Input Voltage Low (digital inputs)
Oscillator Input Voltage High
VIH
VIL
Pin Groups 1, 2
Pin Groups 1, 2
Pin Group 4
2.0
–0.3
2.0
VDD
0.8
V
V
V
VIHOSC
VDDA + 0.3
XTAL driven by an external clock source
Oscillator Input Voltage Low
VILOSC
IOH
Pin Group 4
–0.3
0.8
V
Output Source Current High at VOH min.)1
When programmed for low drive strength
When programmed for high drive strength
Pin Group 1
Pin Group 1
—
—
–4
–8
mA
Output Source Current Low (at VOL max.)1
When programmed for low drive strength
When programmed for high drive strength
IOL
Pin Groups 1, 2
Pin Groups 1, 2
—
—
4
8
mA
°C
Ambient Operating Temperature (Extended
Industrial)
TA
–40
105
Flash Endurance
NF
TA = –40°Cto 125°C
10,000
—
cycles
(Program Erase Cycles)
Flash Data Retention
tR
TJ 85°C avg
TJ 85°C avg
15
20
—
—
years
years
Flash Data Retention with <100
Program/Erase Cycles
tFLRET
—
1
Total chip source or sink current cannot exceed 75 mA.
Table 20. Default Mode
Pin Group 1
Pin Group 2
GPIO, TDI, TDO, TMS, TCK
SCL, SDA
ADC and Comparator
Analog Inputs and PGA
Inputs
Pin Group 3
Pin Group 4
XTAL, EXTAL
8.5
DC Electrical Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
46
Freescale Semiconductor
Specifications
Table 21. DC Characteristics
Ambient
temperature
operating
range
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
Operating Voltage
1.82
3.6
—
V
V
Output high
voltage
All I/O pins, VOH
low-drive strength
1.8 V, ILoad = –2 mA
VDD – 0.5
—
All I/O pins,
high-drive strength
2.7 V, ILoad = –10 mA VDD – 0.5
—
—
—
—
—
—
2.3 V, ILoad = –6 mA
1.8 V, ILoad = –3 mA
VDD – 0.5
VDD – 0.5
—
—
Output high
current
Max total IOH for all IOHT
ports
100
mA
V
Output low
voltage
All I/O pins, VOL
low-drive strength
1.8 V, ILoad = 2 mA
—
—
0.5
All I/O pins,
high-drive strength
2.7 V, ILoad = 10 mA
2.3 V, ILoad = 6 mA
1.8 V, ILoad = 3 mA
—
—
—
—
—
—
—
—
0.5
0.5
0.5
100
Output low
current
Max total IOL for all IOLT
ports
mA
V
Input high
voltage
all digital inputs
VIH
VDD 2.7 V
VDD 1.8 V
VDD 2.7 V
VDD 1.8 V
0.70 x VDD
—
—
—
—
—
—
—
—40 C ~
+125 C
0.85 x VDD
—
0.35 x VDD
0.30 x VDD
—
Input low voltage
all digital inputs
VIL
—
—
0.06 x VDD
—
Input hysteresis
all digital inputs Vhys
mV
Input leakage
current
all input only pins
(Per pin)
|IIn|
VIn = VDD or VSS
VIn = VDD or VSS
1
A
Hi-Z (off-state)
leakage current
all input/output |IOZ
|
—
—
—
1
A
k
(per pin)
Pullup resistors
all digital inputs, when RPU
enabled
17.5
52.5
DC injection
current 3, 4, 5
Single pin limit
IIC
VIn < VSS, VIn > VDD
–0.2
–5
—
—
0.2
5
mA
mA
Total MCU limit, includes
sum of all stressed pins
Input Capacitance, all pins
RAM retention voltage
POR re-arm voltage6
POR re-arm time
CIn
—
—
—
0.6
1.4
—
8
pF
V
VRAM
VPOR
tPOR
1.0
1.79
—
0.9
10
V
s
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
47
Specifications
Table 21. DC Characteristics (continued)
Ambient
temperature
operating
range
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
8
Low-voltage detection threshold —
high range7
VLVDH
VDD falling
2.31
2.16
2.38
2.23
1.8
2.34
2.3
2.36
2.48
2.47
2.49
1.87
N/A
V
–40 C ~
105 C
—40 C ~
+125 C
VDD rising
VDD falling
2.44
2.39
1.84
N/A
1.93
2.62
2.61
2.67
2.66
50
–40 C ~
105 C
—40 C ~
+125 C
Low-voltage detection threshold —
low range7
VLVDL
V
V
–40 C ~
105 C
N/A
1.88
2.58
2.5
—40 C ~
+125 C
VDD rising
1.96
2.71
2.74
2.74
2.79
—
–40 C ~
105 C
9
Low-voltage warning threshold
VLVW
VDD falling
–40 C ~
105 C
—40 C ~
+125 C
VDD rising
2.59
2.51
—
–40 C ~
105 C
—40 C ~
+125 C
Low-voltage inhibit reset/recover
hysteresis7
Vhys
VBG
mV
V
—40 C ~
+105 C
Bandgap Voltage Reference10
1.15
1.14
1.17
1.18
–40 C ~
105 C
—40 C ~
+125 C
1
2
Typical values are measured at 25 C. Characterized, not tested
As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above VLVDL. If the system clock
frequency < 16 MHz, VDD can be 1.7 V to 3.6 V.
3
4
All functional non-supply pins are internally clamped to VSS and VDD
.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
5
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load shunts current greater than maximum injection current.
This is the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present or if clock rate is low
(which would reduce overall power consumption).
6
7
Maximum is highest voltage that POR is guaranteed.
Low voltage detection and warning limits measured at 32 MHz bus frequency. This characteristic is not applicable to devices with
a temperature range from –40 C to 125 C. Please see the PMC chapter in the reference manual for details.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
48
Freescale Semiconductor
Specifications
8
9
Runs at 32 MHz bus frequency.
Both Low Voltage Warning (LVW) and Out Of Regulation (OOR) sample the same input source. The OOR flag is a stick bit which
is in the PMC_SCR register.
10 Factory trimmed at VDD = 3.3 V, Temp = 25 C.
PULLUP RESISTOR TYPICALS
40
PULLDOWN RESISTOR TYPICALS
85C
40
35
30
25
20
85C
25C
25C
–40C
–40C
35
30
25
20
1.8
2
2.2 2.4 2.6 2.8
DD (V)
3
3.2 3.4 3.6
1.8
2.3
2.8
VDD (V)
3.3
3.6
V
Figure 16. Pullup and Pulldown Typical Resistor Values
TYPICAL VOL VS IOL AT VDD = 3.0 V
TYPICAL VOL VS VDD
0.2
0.15
0.1
1.2
85
C
25C
1
0.8
0.6
0.4
0.2
0
–40C
85
25
–40
C, IOL = 2 mA
0.05
0
C, IOL = 2 mA
C, IOL = 2 mA
1
2
3
4
0
5
10
IOL (mA)
15
20
VDD (V)
Figure 17. Typical Low-Side Driver (Sink) Characteristics — Low Drive (GPIO_x_DRIVEn = 0)
TYPICAL VOL VS VDD
TYPICAL VOL VS IOL AT VDD = 3.0 V
1
0.4
0.3
0.2
0.1
85C
85C
25C
25C
0.8
–40C
–40C
0.6
0.4
0.2
IOL = 10 mA
IOL = 6 mA
I
OL = 3 mA
0
0
0
10
20
30
1
2
3
4
VDD (V)
I
OL (mA)
Figure 18. Typical Low-Side Driver (Sink) Characteristics — High Drive (GPIO_x_DRIVEn = 1)
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
49
Specifications
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
TYPICAL VDD – VOH VS VDD AT SPEC IOH
1.2
1
0.25
0.2
0.15
0.1
0.05
0
85
C
85C, IOH = 2 mA
25C
25
C, IOH = 2 mA
–40C
–40
C, IOH = 2 mA
0.8
0.6
0.4
0.2
0
0
–5
–10
OH (mA))
–15
–20
1
2
3
4
VDD (V)
I
Figure 19. Typical High-Side (Source) Characteristics — Low Drive (GPIO_x_DRIVEn = 0)
TYPICAL VDD – VOH VS VDD AT SPEC IOH
0.4
85C
25C
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
–40C
0.3
0.2
0.1
0.8
0.6
0.4
0.2
0
85C
25C
–40C
IOH = –10 mA
IOH = –6 mA
IOH = –3 mA
0
0
–5
–10
–15
–20
–25
–30
1
2
3
4
IOH (mA)
VDD (V)
Figure 20. Typical High-Side (Source) Characteristics — High Drive (GPIO_x_DRIVEn = 1)
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
50
Freescale Semiconductor
Specifications
8.6
Supply Current Characteristics
Table 22. Supply Current Consumption
Typical @ 3.3 V,
25 °C
Maximum @ 3.6 V,
105 °C
Maximum @ 3.6 V,
125 °C
Mode
Conditions
1
1
1
IDD
IDDA
IDD
IDDA
IDD
IDDA
Run
32 MHz device clock;
41.52 mA 1.71 mA
53 mA
2.7 mA
53 mA
2.9 mA
relaxation oscillator (ROSC) in high speed
mode;
PLL engaged;
All peripheral modules enabled. TMR and
PWM using 1X clock;
continuous MAC instructions with fetches
from program flash;
ADC/DAC powered on and clocked;
comparator powered on.
LSrun 2
LPrun 3
Wait
200 kHz device clock;
relaxation oscillator (ROSC) in standby
mode;
PLL disabled
All peripheral modules disabled and clock
gated off;
340.75 A 1.70 mA
166.30 A 1.74 mA
19.3 mA 1.78 mA
480 A
390 A
28 mA
2.5 mA
3.4 mA
2.7 mA
495 A
399 A
28 mA
2.6 mA
3.8 mA
2.8 mA
simple loop with fetches from program flash;
32.768 kHz device clock;
Clocked by a 32.768 kHz external crystal
relaxation oscillator (ROSC) in power down;
PLL disabled
All peripheral modules disabled and clock
gated off;
simple loop with fetches from program flash;
32 MHz device clock
relaxation oscillator (ROSC) in high speed
mode
PLL engaged;
All non-communication peripherals enabled
and running;
all communication peripherals disabled but
clocked;
processor core in wait state
LSwait 2
200 kHz device clock;
relaxation oscillator (ROSC) in standby
mode;
265.42 A 1.70 mA
380 A
2.5 mA
398 A
2.6 mA
PLL disabled;
All peripheral modules disabled and clock
gated off;
processor core in wait state
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
51
Specifications
Mode
Table 22. Supply Current Consumption (continued)
Typical @ 3.3 V,
25 °C
Maximum @ 3.6 V,
105 °C
Maximum @ 3.6 V,
125 °C
Conditions
1
1
1
IDD
IDDA
IDD
IDDA
IDD
IDDA
LPwait 3
32.768 kHz device clock;
157.55 A 1.57 mA
8.21 mA 65.51 A
194.69 A 65.51 A
2.77 A 13.99 nA
879.72 nA 11.56 nA
380 A
9.8 mA
340 A
45 A
3.4 mA
398 A
3.6 mA
Clocked by a 32.768 kHz external crystal
oscillator in power down;
PLL disabled;
All peripheral modules disabled and clock
gated off;
processor core in wait state
Stop
32 MHz device clock
relaxation oscillator (ROSC) in high speed
mode;
130 A 10.3 mA 132 A
PLL engaged;
all peripheral module and core clocks are off;
ADC/DAC/comparator powered off;
processor core in stop state
LSstop 2 200 kHz device clock;
relaxation oscillator (ROSC) in standby
120 A
357 A
123 A
mode;
PLL disabled;
all peripheral modules disabled and clock
gated off;
processor core in stop state.
LPstop 2 32.768 kHz device clock;
3.0 A
58 A
3.6 A
Clocked by a 32.768 kHz external crystal
relaxation oscillator (ROSC) in power down;
PLL disabled;
all peripheral modules disabled and clock
gated off;
processor core in stop state.
PPD 4 with 32.768 kHz clock fed on XTAL
XOSC
18 A
14 A
14 A
2.4 A
2.4 A
2.4 A
22 A
17 A
17 A
3.0 A
2.8 mA
2.8 A
RTC or COP monitoring XOSC (but no
wakeup)
processor core in stop state
PPD with LP RTC or COP monitoring LP oscillator (but no 499.15 nA 13.9 nA
oscillator wakeup);
(1 kHz)
enabled
processor core in stop state.
PPD with no RTC and LP oscillator are disabled;
494.04 nA 12.88 nA
clock
processor core in stop state.
monitoring
1
2
3
4
No output switching; all ports configured as inputs; all inputs low; no DC loads.
Low speed mode: LPR (lower voltage regulator control bit) = 0 and voltage regulator is in full regulation. Characterization only.
Low power mode: LPR (lower voltage regulator control bit) = 1; the voltage regulator is put into standby.
Partial power down mode: PPDE (partial power down enable bit) = 1; power management controller (PMC) enters partial power
down mode the next time that the STOP command is executed.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
52
Freescale Semiconductor
Specifications
8.7
Flash Memory Characteristics
Table 23. Flash Timing Parameters
Characteristic
Symbol
Min
Typ
Max
Unit
Program time1
Erase time 2
tprog
terase
tme
20
20
—
—
—
40
—
—
s
ms
ms
Mass erase time
100
1
There is additional overhead that is part of the programming sequence. See the MC56F8006 Peripheral Reference
Manual for detail.
2
Specifies page erase time. There are 512 bytes per page in the program flash memory.
8.8
External Clock Operation Timing
1
Table 24. External Clock Operation Timing Requirements
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)2
Clock pulse width3
fosc
tPW
trise
tfall
Vih
Vil
—
6.25
—
—
—
—
—
—
—
64
MHz
ns
ns
ns
V
—
External clock input rise time4
3
3
External clock input fall time5
—
Input high voltage overdrive by an external clock
Input high voltage overdrive by an external clock
Parameters listed are guaranteed by design.
0.85VDD
—
—
0.3VDD
V
1
2
3
4
5
See Figure 21 for detail on using the recommended connection of an external clock driver.
The chip may not function if the high or low pulse width is smaller than 6.25 ns.
External clock input rise time is measured from 10% to 90%.
External clock input fall time is measured from 90% to 10%.
VIH
External
Clock
90%
50%
10%
90%
50%
10%
tfall
VIL
trise
tPW
tPW
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 21. External Clock Timing
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
53
Specifications
8.9
Phase Locked Loop Timing
Table 25. Phase Locked Loop Timing
Characteristic
Symbol
Min
Typ
Max
Unit
PLL input reference frequency1
PLL output frequency2
PLL lock time3 4
fref
fop
4
120
—
8
—
—
MHz
MHz
µs
192
40
tplls
100
0.37
—
Accumulated jitter using an 8 MHz external crystal as the PLL source5
JA
—
—
%
Cycle-to-cycle jitter
tjitterpll
—
350
ps
1
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The
PLL is optimized for 8 MHz input.
2
3
4
5
The core system clock operates at 1/6 of the PLL output frequency.
This is the time required after the PLL is enabled to ensure reliable operation.
From powerdown to powerup state at 32 MHz system clock state.
This is measured on the CLKO signal (programmed as system clock) over 264 system clocks at 32 MHz system clock
frequency and using an 8 MHz oscillator frequency.
8.10 Relaxation Oscillator Timing
Table 26. Relaxation Oscillator Timing
Characteristic
Symbol Minimum Typical
Maximum
Unit
Relaxation oscillator output frequency1
Normal Mode
fop
—
—
8.05
400
MHz
kHz
Standby Mode
Relaxation oscillator stabilization time2
troscs
—
—
1
3
ms
ps
Cycle-to-cycle jitter. This is measured on the CLKO signal tjitterrosc
(programmed prescaler_clock) over 264 clocks3
400
—
Variation over temperature –40 C to 105 C4
Variation over temperature 0 C to 105 C5
Variation over temperature –40 C to 125 C4
—
—
—
—
—
—
–3.0 to +2.0
–2.0 to +2.0
–3.5 to +3.0
%
%
%
1
Output frequency after factory trim.
2
3
4
This is the time required from standby to normal mode transition.
JA is required to meet QSCI requirements.
See Figure 22. The power supply VDD must be greater than or equal to 2.6 V. Below 2.6 V, the maximum variation
over the whole temperature and whole voltage range from 1.8 V to 2.6 V will be +/-16%.
5
This data is only applied to devices with temperature range from –40 C to 105 C.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
54
Freescale Semiconductor
Specifications
Degrees C (Junction)
Figure 22. Relaxation Oscillator Temperature Variation (Typical) After Trim for devices with temperature
operating range from –40 C to 105 C
Figure 23. Relaxation Oscillator Temperature Variation (Typical) After Trim for devices with temperature
operating range from –40 C to 125 C
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
55
Specifications
8.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing
NOTE
All address and data buses described here are internal.
1,2
Table 27. Reset, Stop, Wait, Mode Select, and Interrupt Timing
Characteristic
Symbol
Typical Min
Typical Max
Unit
See Figure
Minimum RESET Assertion Duration
Minimum GPIO pin Assertion for Interrupt
RESET deassertion to First Address Fetch
tRA
tIW
tRDA
tIF
4T
—
ns
ns
ns
ns
—
Figure 24
—
2T
96TOSC + 64T
—
—
97TOSC + 65T
6T
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
—
1
2
In the formulas, T = system clock cycle and Tosc = oscillator clock cycle. For an operating frequency of 32 MHz, T = 31.25 ns.
At 4 MHz (used coming out of reset and stop modes), T = 250 ns.
Parameters listed are guaranteed by design.
GPIO pin
(Input)
tIW
Figure 24. GPIO Interrupt Timing (Negative Edge-Sensitive)
8.12 External Oscillator (XOSC) Characteristics
Reference Figure 10, and Figure 11, and Figure 12 for crystal or resonator circuits.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
56
Freescale Semiconductor
Specifications
Unit
Table 28. Crystal Oscillator Characteristics
Characteristic
Symbol
Min
Typ1
Max
Oscillator crystal or resonator (PRECS = 1, CLK_MOD = 0)
Low range (RANGE = 0)
flo
fhi
fhi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
High range (RANGE = 1), high gain (COHL =0)
High range (RANGE = 1), low power (COHL =1)
Load capacitors
C1,C2
See Note2
See Note3
Low range (RANGE=0), low power (COHL =1)
Other oscillator settings
Feedback resistor
RF
M
k
Low range, low power (RANGE=0, COHL =1)2
Low range, high gain (RANGE=0, COHL =0)
High range (RANGE=1, COHL=X)
—
—
—
—
10
1
—
—
—
Series resistor
RS
Low range, low power (RANGE = 0, COHL =1)2
—
—
—
0
100
0
—
—
—
Low range, high gain (RANGE = 0, COHL =0)
High range, low power (RANGE = 1, COHL =1)
High range, high gain (RANGE = 1,COHL =0)
8 MHz
4 MHz
1 MHz
—
—
—
0
0
0
0
10
20
Crystal start-up time 4
Low range, low power
Low range, high gain
High range, low power
High range, high gain
t
—
—
—
—
TBD
TBD
TBD
TBD
—
—
—
—
ms
CSTL
t
CSTH
Square wave input clock frequency (PRECS = 1, CLK_MOD = 1)
fxtal
—
—
50.0
MHz
1
2
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when
RANGE=HGO=0.
3
4
See crystal or resonator manufacturer’s recommendation.
Proper PC board layout procedures must be followed to achieve specifications.
8.13 AC Electrical Characteristics
Tests are conducted using the input levels specified in Table 22. Unless otherwise specified, propagation delays are measured
from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure 25.
Low
High
VIH
90%
50%
10%
Midpoint1
Input Signal
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH – VIL)/2.
Figure 25. Input Signal Measurement References
Figure 26 shows the definitions of the following signal states:
•
Active state, when a bus or signal is driven, and enters a low impedance state
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
57
Specifications
•
•
•
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached V or V
OL
OH
Data Invalid state, when a signal level is in transition between V and V
OL
OH
Data1 Valid
Data1
Data2 Valid
Data2
Data3 Valid
Data3
Data
Three-stated
Data Invalid State
Data Active
Data Active
Figure 26. Signal States
8.13.1 Serial Peripheral Interface (SPI) Timing
1
Table 29. SPI Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
tC
Figure 27,
Figure 28,
Figure 29,
Figure 30
125
62.5
—
—
ns
ns
Enable lead time
Master
tELD
tELG
tCH
Figure 30
—
31
—
—
ns
ns
Slave
Enable lag time
Master
Figure 30
—
125
—
—
ns
ns
Slave
Clock (SCK) high time
Figure 27,
Figure 28,
Figure 29,
Figure 30
Master
Slave
50
31
—
—
ns
ns
Clock (SCK) low time
Master
tCL
Figure 30
50
31
—
—
ns
ns
Slave
Data set-up time required for inputs
tDS
Figure 27,
Figure 28,
Figure 29,
Figure 30
Master
Slave
20
0
—
—
ns
ns
Data hold time required for inputs
tDH
Figure 27,
Figure 28,
Figure 29,
Figure 30
Master
Slave
0
2
—
—
ns
ns
Access time (time to data active from high-impedance
tA
Figure 30
state)
Slave
4.8
3.7
15
ns
ns
Disable time (hold time to high-impedance state)
Slave
tD
Figure 30
15.2
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
58
Freescale Semiconductor
Specifications
1
Table 29. SPI Timing (continued)
Characteristic
Symbol
Min
Max
Unit
See Figure
Data valid for outputs
Master
Slave (after enable edge)
tDV
Figure 27,
Figure 28,
Figure 29,
Figure 30
—
—
4.5
20.4
ns
ns
Data invalid
Master
tDI
tR
tF
Figure 27,
Figure 28,
Figure 29,
Figure 30
0
0
—
—
ns
ns
Slave
Rise time
Master
Slave
Figure 27,
Figure 28,
Figure 29,
Figure 30
—
—
11.5
10.0
ns
ns
Fall time
Master
Slave
Figure 27,
Figure 28,
Figure 29,
Figure 30
—
—
9.7
9.0
ns
ns
1
Parameters listed are guaranteed by design.
SS
(Input)
SS is held high on master
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
(Input)
tDV
Bits 14–1
MOSI
(Output)
Master MSB out
tF
Master LSB out
tR
Figure 27. SPI Master Timing (CPHA = 0)
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
59
Specifications
SS
(Input)
SS is held High on master
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tCL
SCLK (CPOL = 1)
(Output)
tCH
tDS
tR
tDH
MISO
MSB in
tDI
Bits 14–1
LSB in
(Input)
tDV(ref)
tDV
Bits 14– 1
tDI(ref)
MOSI
(Output)
Master MSB out
tF
Master LSB out
tR
Figure 28. SPI Master Timing (CPHA = 1)
SS
(Input)
tC
tF
tELG
tCL
tR
SCLK (CPOL = 0)
(Input)
tCH
tELD
tCL
SCLK (CPOL = 1)
(Input)
tCH
tF
tA
tR
tD
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
Slave LSB out
tDI
tDS
tDI
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 29. SPI Slave Timing (CPHA = 0)
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
60
Freescale Semiconductor
Specifications
SS
(Input)
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tCH
tR
tD
tA
tF
MISO
Slave MSB out
MSB in
Bits 14–1
tDV
Slave LSB out
(Output)
tDS
tDI
tDH
MOSI
(Input)
Bits 14–1
LSB in
Figure 30. SPI Slave Timing (CPHA = 1)
8.13.2 Serial Communication Interface (SCI) Timing
1
Table 30. SCI Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
Baud rate2
BR
—
(fMAX/16)
1.04/BR
1.04/BR
Mbps
ns
—
RXD pulse width
TXD pulse width
RXDPW
TXDPW
0.965/BR
0.965/BR
Figure 31
Figure 32
ns
LIN Slave Mode
Deviation of slave node clock from
nominal clock rate before
synchronization
FTOL_UNSYNCH
FTOL_SYNCH
TBREAK
–14
–2
14
2
%
%
—
—
Deviation of slave node clock relative to
the master node clock after
synchronization
Minimum break character length
13
11
—
—
Master node
bit periods
—
—
Slave node
bit periods
1
2
Parameters listed are guaranteed by design.
fMAX is the frequency of operation of the SCI in MHz, which can be selected system clock (max. 32 MHz) or 3x system clock
(max. 96 MHz) for the 56F8006/56F8002 device.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
61
Specifications
RXD
SCI receive
data pin
(Input)
RXDPW
Figure 31. RXD Pulse Width
TXD
SCI receive
data pin
TXDPW
(Input)
Figure 32. TXD Pulse Width
8.13.3 Inter-Integrated Circuit Interface (I2C) Timing
2
Table 31. I C Timing
Standard Mode
Minimum Maximum
Characteristic
Symbol
Unit
SCL Clock Frequency
fSCL
0
100
—
MHz
Hold time (repeated) START condition.
tHD; STA
4.0
s
After this period, the first clock pulse is generated.
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
tSU; STA
tHD; DAT
tSU; DAT
tr
4.7
4.0
4.7
01
—
—
s
s
s
s
ns
ns
ns
s
s
ns
Set-up time for a repeated START condition
Data hold time for I2C bus devices
—
3.452
Data set-up time
250
—
—
Rise time of SDA and SCL signals
1000
300
—
Fall time of SDA and SCL signals
tf
—
Set-up time for STOP condition
tSU; STO
tBUF
4.0
4.7
N/A
Bus free time between STOP and START condition
Pulse width of spikes that must be suppressed by the input filter
—
tSP
N/A
1
2
The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
62
Freescale Semiconductor
Specifications
SDA
SCL
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
tSU; STA
tHD; STA
tSU; STO
S
SR
P
S
tHD; DAT
tHIGH
2
Figure 33. Timing Definition for Standard Mode Devices on the I C Bus
8.13.4 JTAG Timing
Table 32. JTAG Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
TCK frequency of operation1
TCK clock pulse width
fOP
tPW
tDS
tDH
tDV
tTS
DC
50
5
SYS_CLK/8
MHz
ns
Figure 34
Figure 34
Figure 35
Figure 35
Figure 35
Figure 35
—
—
—
30
30
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
ns
5
ns
—
—
ns
TCK low to TDO tri-state
ns
1
TCK frequency of operation must be less than 1/8 the processor rate.
1/fOP
tPW
VM
tPW
VIH
VM
TCK
(Input)
VIL
Figure 34. Test Clock Input Timing Diagram
VM = VIL + (VIH – VIL)/2
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
63
Specifications
TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
(Input)
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
Figure 35. Test Access Port Timing Diagram
8.13.5 Dual Timer Timing
1, 2
Table 33. Timer Timing
Min
Characteristic
Symbol
Max
Unit
See Figure
Timer input period
Timer input high/low period
Timer output period
PIN
2T + 6
1T + 3
125
—
—
—
—
ns
ns
ns
ns
Figure 36
Figure 36
Figure 36
Figure 36
PINHL
POUT
Timer output high/low period
POUTHL
50
1
In the formulas listed, T = the clock cycle. For 32 MHz operation, T = 31.25ns.
2. Parameters listed are guaranteed by design.
Timer Inputs
PINHL
PINHL
PIN
Timer Outputs
POUTHL
POUTHL
POUT
Figure 36. Timer Timing
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
64
Freescale Semiconductor
Specifications
8.14 COP Specifications
Table 34. COP Specifications
Parameter
Symbol
Min
500
Typ
Max
Unit
Oscillator output frequency
LPFosc
IDD
1000
TBD
1500
Hz
nA
Oscillator current consumption in partial power down mode
8.15 PGA Specifications
Table 35. PGA Specifications
Parameter
Symbol
Min
Max
Unit
Digital logic inputs amplitude (_2p5 signal)
DC analog input level (@ VDD = avdd3p3)
V2p5
VIL
2.75
V
V
0
PGA S/H stage enabled (BP=0)
VDD
PGA S/H stage disabled (BP=1)
VDD – 0.5
Max differential input voltage (@ Gain and VDD = avdd3p3)
VDIFFMAX
(VDD – 1) x 0.5/gain
V
Linearity (@ voltage gain)
1x
2x
4x
1 – 1/2 LSB
2 – 1/2 LSB
4 – 1 LSB
1 + 1/2 LSB
2 + 1/2 LSB
4 + 1 LSB
LV
V/V
8x
8 – 1 LSB
8 + 1 LSB
16x
32x
16 – 4 LSB
32 – 4 LSB
16 + 4 LSB
32 + 4 LSB
Gain error (@ voltage gain)
1x
2x
4x
AV
1%
V/V
8x
16x
32x
Sampling frequency (pga_clk_2p5)
normal mode (pga_lp_2p5 asserted) SFmax
low power mode (pga_lp_2p5 negated)
8
4
MHz
Hz
Input signal bandwidth
Motor Control mode (BP=0) BWmax
General Purpose mode (BP=1)
PGA sampling rate/2
PGA sampling rate/8
Internal voltage doubler clock frequency(pga_clk_doubler_2p5) VDclk
100
–40
2000
125
kHz
oC
Operating temperature
T
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
65
Specifications
8.16 ADC Specifications
Table 36. ADC Operating Conditions
Characteristic
Conditions
Symb
Min
Typ1
Max
Unit
Comment
2
3
Input voltage
VADIN
CADIN
VREFL
—
—
VREFH
5.5
V
Input
4.5
pF
capacitance
Input resistance
RADIN
RAS
—
5
7
k
k
Analog source 12-bit mode
resistance fADCK > 4 MHz
fADCK < 4 MHz
External to MCU
—
—
—
—
2
5
10-bit mode
ADCK > 4 MHz
f
—
—
—
—
5
10
fADCK < 4 MHz
8-bit mode (all valid fADCK
)
—
—
—
—
10
8.0
4.0
ADC conversion High speed (ADLPC=0)
fADCK
0.4
0.4
MHz
clock freq.
Low power (ADLPC=1)
1
Typical values assume VDDAD = 3.0 V, Temp = 25C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2
3
VREFL = VSSA
VREFH = VDDA
Simplified
Input Pin Equivalent
ZADIN
Circuit
Simplified
Channel Select
Circuit
Pad
leakage
due to
input
protection
ZAS
ADC SAR
Engine
RAS
RADIN
+
VADIN
–
CAS
VAS
+
–
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 37. ADC Input Impedance Equivalency Diagram
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
66
Freescale Semiconductor
Specifications
Comment
Table 37. ADC Characteristics (V
= V
, V
= V
)
SSA
REFH
Min
—
DDA
REFL
Characteristic
Conditions
Symb
Typ1
Max
Unit
Supply current
ADLPC=1
ADLSMP=1
ADCO=1
IDDAD
120
202
—
A
Supply current
ADLPC=1
ADLSMP=0
ADCO=1
IDDAD
IDDAD
IDDAD
—
—
—
—
—
1
A
Supply current
ADLPC=0
ADLSMP=1
ADCO=1
288
A
Supply current
ADLPC=0
ADLSMP=0
ADCO=1
0.532
mA
MHz
ADC
asynchronous
clock source
High speed (ADLPC=0)
Low power (ADLPC=1)
fADACK
2
3.3
2
5
tADACK =
1/fADACK
1.25
3.3
Conversion time Short sample (ADLSMP=0)
tADC
—
—
20
40
—
—
ADCK
cycles
(including
Long sample (ADLSMP=1)
sample time)
Sample time
Short sample (ADLSMP=0)
Long sample (ADLSMP=1)
12-bit mode
tADS
DNL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.5
23.5
1.75
0.5
0.3
1.5
0.5
0.3
–1 to 0
—
—
—
ADCK
cycles
Differential
Non-linearity
—
LSB2
LSB2
LSB2
LSB2
10-bit mode3
8-bit mode3
1.0
0.5
—
Integral
non-linearity
12-bit mode
INL
EQ
EIL
10-bit mode
1.0
0.5
—
8-bit mode
Quantization
error
12-bit mode
10-bit mode
0.5
0.5
—
8-bit mode
—
Input leakage
error
12-bit mode
2
Pad leakage4 *
RAS
10-bit mode
0.2
0.1
1.646
1.769
701.2
4
8-bit mode
1.2
—
Temp sensor
slope
–40C–25C
25C–125C
25C
m
mV/C
—
Temp sensor
voltage
VTEMP25
—
mV
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
67
Specifications
1
Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2
3
4
1 LSB = (VREFH – VREFL)/2N
Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes
Based on input pad leakage current. Refer to pad electricals.
8.17 HSCMP Specifications
Table 38. HSCMP Specifications
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VPWR
1.8
3.6
V
Supply current, high speed mode (EN=1,
IDDAHS
150
10
A
PMODE=1, VDDA VLVI_trip
)
Supply current, low speed mode (EN=1,
PMODE=0)
IDDALS
A
Supply current, off mode (EN=0,)
Analog input voltage
IDDAOFF
VAIN
100
VDDA + 0.01
40
nA
V
VSSA – 0.01
3.0
Analog input offset voltage
Analog comparator hysteresis
VAIO
VH
mV
mV
ns
20.0
1
Propagation Delay, high speed mode (EN=1,
PMODE=1), 2.4 V < VDDA < 3.6 V
tDHSN
70
70
140
2
Propagation Delay, High Speed Mode (EN=1,
PMODE=1), 1.8 V < VDDA < 2.4 V
tDHSB
249
600
600
ns
ns
ns
3
Propagation Delay, Low Speed Mode (EN=1,
PMODE=0), 2.4 V < VDDA < 3.6 V
tAINIT
400
400
4
Propagation Delay, Low Speed Mode (EN=1,
PMODE=0), 1.8 V < VDDA < 2.4 V
tAINIT
1
2
3
4
Measured with an input waveform that switches 30 mV above and below the reference, to the CMPO output pin. VDDA
VLVI_WARNING => LVI_WARNING NOT ASSERTED.
>
<
>
<
Measured with an input waveform that switches 30mV above and below the reference, to the CMPO output pin. VDDA
VLVI_WARNING => LVI_WARNING ASSERTED.
Measured with an input waveform that switches 30mV above and below the reference, to the CMPO output pin. VDDA
VLVI_WARNING => LVI_WARNING NOT ASSERTED.
Measured with an input waveform that switches 30mV above and below the reference, to the CMPO output pin. VDDA
VLVI_WARNING => LVI_WARNING ASSERTED.
8.18 Optimize Power Consumption
See Section 8.6, “Supply Current Characteristics,” for a list of I requirements for the 56F8006/56F8002. This section
DD
provides additional detail that can be used to optimize power consumption for a given application.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
68
Freescale Semiconductor
Specifications
Power consumption is given by the following equation:
Eqn. 1
Total power =
A:
internal [static component]
+B: internal [state-dependent component]
+C:
+D:
+E:
internal [dynamic component]
external [dynamic component]
external [static component]
A, the internal [static] component, is comprised of the DC bias currents for the oscillator, leakage currents, PLL, and voltage
references. These sources operate independently of processor state or operating frequency.
B, the internal [state-dependent] component, reflects the supply current required by certain on-chip resources only when those
resources are in use. These include RAM, flash memory, and the ADCs.
2
C, the internal [dynamic] component, is classic C*V *F CMOS power dissipation corresponding to the 56800E core and
standard cell logic.
D, the external [dynamic] component, reflects power dissipated on-chip as a result of capacitive loading on the external pins of
2
the chip. This is also commonly described as C*V *F, although simulations on two of the I/O cell types used on the 56800E
reveal that the power-versus-load curve does have a non-zero Y-intercept.
Table 39. I/O Loading Coefficients at 10 MHz
Intercept
Slope
8 mA drive
4 mA drive
1.3
0.11 mW/pF
0.11 mW/pF
1.15 mW
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the
outputs change. Table 39 provides coefficients for calculating power dissipated in the I/O cells as a function of capacitive load.
In these cases:
TotalPower = ((Intercept + Slope*Cload)*frequency/10 MHz)
Eqn. 2
where:
•
•
•
Summation is performed over all output pins with capacitive loads
Total power is expressed in mW
C
is expressed in pF
load
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when
averaged over a period of time.
E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. Sum the total of
2
all V /R or IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations.
For instance, if there is a total of eight PWM outputs driving 10 mA into LEDs, then P = 8*0.5*0.01 = 40 mW.
In previous discussions, power consumption due to parasitics associated with pure input pins is ignored, as it is assumed to be
negligible.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
69
Design Considerations
9
Design Considerations
9.1
Thermal Design Considerations
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
x P )
Eqn. 3
J
A
J
D
where:
TA
RJ
PD
=
=
=
Ambient temperature for the package (oC)
Junction-to-ambient thermal resistance (oC/W)
Power dissipation in the package (W)
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board and the value
obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a
single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low-power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a
case-to-ambient thermal resistance:
R
= R
+ R
CA
Eqn. 4
JA
JC
where:
RJA
RJC
RCA
=
=
=
Package junction-to-ambient thermal resistance (°C/W)
Package junction-to-case thermal resistance (°C/W)
Package case-to-ambient thermal resistance (°C/W)
R
is device related and cannot be adjusted. You control the thermal environment to change the case to ambient thermal
JC
resistance, R
. For instance, you can change the size of the heat sink, the air flow around the device, the interface material,
CA
the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding
the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization
parameter ( ) can be used to determine the junction temperature with a measurement of the temperature at the top center of
JT
the package case using the following equation:
T = T + ( x P )
Eqn. 5
J
T
JT
D
where:
TT
JT
PD
=
=
=
Thermocouple temperature on top of package (oC)
Thermal characterization parameter (oC/W)
Power dissipation in package (W)
The thermal characterization parameter is measured per JESD51–2 specification using a 40-gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
70
Freescale Semiconductor
Design Considerations
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case
of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of
the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to
the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature
and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this
case temperature, the junction temperature is determined from the junction-to-case thermal resistance.
9.2
Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage
or electrical fields. However, take normal precautions to avoid application of any voltages
higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation of the 56F8006/56F8002:
•
Provide a low-impedance path from the board power supply to each V pin on the 56F8006/56F8002 and from the
DD
board ground to each V (GND) pin.
SS
•
The minimum bypass requirement is to place 0.01–0.1µF capacitors positioned as near as possible to the package
supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the V /V pairs,
DD SS
including V
/V
Ceramic and tantalum capacitors tend to provide better tolerances.
DDA SSA.
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip V and V (GND) pins are
DD SS
as short as possible.
•
•
•
Bypass the V and V with approximately 100 µF, plus the number of 0.1 µF ceramic capacitors.
DD
SS
PCB trace lengths should be minimal for high-frequency signals.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is
especially critical in systems with higher capacitive loads that could create higher transient currents in the V and
DD
V
circuits.
SS
•
•
Take special care to minimize noise levels on the V , V
, and V
pins.
SSA
REF DDA
Using separate power planes for V and V
and separate ground planes for V and V
are recommended.
SSA
DD
DDA
SS
Connect the separate analog and digital power and ground planes as near as possible to power supply outputs. If an
analog circuit and digital circuit are powered by the same power supply, you should connect a small inductor or ferrite
bead in serial with V
and V
traces.
DDA
SSA
•
•
•
•
•
•
Physically separate analog components from noisy digital components by ground planes. Do not place an analog trace
in parallel with digital traces. Place an analog ground trace around an analog signal trace to isolate it from digital traces.
2
Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI, or I C, the designer should
provide an interface to this port if in-circuit flash programming is desired.
If desired, connect an external RC circuit to the RESET pin. The resistor value should be in the range of 4.7 k–10 k;
the capacitor value should be in the range of 0.22 µF–4.7 µF.
Configuring the RESET pin to GPIO output in normal operation in a high-noise environment may help to improve the
performance of noise transient immunity.
Add a 2.2 k external pullup on the TMS pin of the JTAG port to keep EOnCE in a restate during normal operation if
JTAG converter is not present.
During reset and after reset but before I/O initialization, all I/O pins are at input state with internal pullup enabled. The
typical value of internal pullup is around 33 k. These internal pullups can be disabled by software.
•
•
To eliminate PCB trace impedance effect, each ADC input should have a no less than 33 pF 10 RC filter.
External clamp diodes on analog input pins are recommended.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
71
Design Considerations
9.3
Ordering Information
Table 40 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized
distributor to determine availability and to order devices.
Table 40. 56F8006/56F8002 Ordering Information
Ambient
Temperature
Range
Supply
Voltage
Pin
Count
Frequency
(MHz)
Device
Package Type
Order Number
MC56F8002 1.8–3.6 V
MC56F8006 1.8–3.6 V
MC56F8006 1.8–3.6 V
MC56F8006 1.8–3.6 V
MC56F8006 1.8–3.6 V
Small Outline IC (SOIC)
Small Outline IC (SOIC)
28
28
32
48
32
32
32
32
32
32
–40° to + 105° C MC56F8002VWL
–40° to + 125° C MC56F8002MWL1
–40° to + 105° C MC56F8006VWL
–40° to + 125° C MC56F8006MWL1
Low-Profile Quad Flat Pack
(LQFP)
–40° to + 105° C MC56F8006VLC
–40° to + 125° C MC56F8006MLC1
Low-Profile Quad Flat Pack
(LQFP)
–40° to + 105° C MC56F8006VLF
–40° to + 125° C MC56F8006MLF1
Plastic Shrink Dual In-line
Package (PSDIP)
–40° to + 105° C MC56F8006VBM
1
This package is RoHS compliant.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
72
Freescale Semiconductor
Package Mechanical Outline Drawings
10 Package Mechanical Outline Drawings
10.1 28-pin SOIC Package
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
73
Package Mechanical Outline Drawings
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
74
Freescale Semiconductor
Package Mechanical Outline Drawings
Figure 38. 56F8006/56F8002 28-Pin SOIC Mechanical Information
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
75
Package Mechanical Outline Drawings
10.2 32-pin LQFP
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
76
Freescale Semiconductor
Package Mechanical Outline Drawings
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
77
Package Mechanical Outline Drawings
Figure 39. 56F8006/56F8002 32-Pin LQFP Mechanical Information
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
78
Freescale Semiconductor
Package Mechanical Outline Drawings
10.3 48-pin LQFP
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
79
Package Mechanical Outline Drawings
Figure 40. 56F8006/56F8002 48-Pin LQFP Mechanical Information
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
80
Freescale Semiconductor
Package Mechanical Outline Drawings
10.4 32-Pin PSDIP
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
81
Package Mechanical Outline Drawings
Figure 41. 56F8006/56F8002 32-Pin PSDIP Mechanical Information
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
82
Freescale Semiconductor
Revision History
11 Revision History
Table 41 lists major changes between versions of the MC56F8006 document.
Table 41. Changes Between Revisions 2 and 3
Location
Introduction on page 1
Description
Added part marking for devices covered by this document
Section 6.7, “PWM, PDB, PGA, and ADC Updated routing details for ANB24 and ANB25
Connections,” on page 38
Table 12 on page 42
Table 21 on page 47
Removed row about open drain mode (GPIO supports only push-pull mode)
Updated specifications for low-voltage detection threshold (high and low range) and
low-voltage warning threshold
Table 22 on page 51
Updated all Supply Current Consumption specifications
Table 26 and Figure 22 on page 55
Table 31 on page 62
Updated ROSC variation over temperature specifications (both ranges)
Removed I2C fast mode specifications and footnote about setup time if the TX FIFO
is empty (fast mode and FIFO not supported)
Appendix B on page 86
Table 44 on page 86
Added note explaining ADC and GPIO naming conventions
For I2C_SMB_CSR, clarified that bits 7 and 6 are reserved
Table 42. Changes Between Revisions 3 and 4
Description
Location
Throughout document.
Added information for 32-pin PSDIP device and devices with temperature range
from –40 C to + 125 C.
Appendix A
Interrupt Vector Table
Table 43 provides the 56F8006/56F8002’s reset and interrupt priority structure, including on-chip peripherals. The table is
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an
interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts are serviced
before level 2 and so on. For a selected priority level, the lowest vector number has the highest priority.
The location of the vector table is determined by the vector base address (VBA). Please see the MC56F8006 Peripheral
Reference Manual for detail.
By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these
instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR
instructions.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
83
Interrupt Vector Table
1
Table 43. Interrupt Vector Table Contents
Vector
Number Encoding
User
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
PMC
PLL
P:0x00
P:0x02
P:0x04
P:0x06
P:0x08
P:0x0A
P:0x0C
P:0x0E
P:0x10
P:0x12
P:0x14
P:0x16
P:0x18
P:0x1A
P:0x1C
P:0x1E
P:0x20
P:0x22
P:0x24
P:0x26
P:0x28
P:0x2A
P:0x2C
P:0x2E
P:0x30
P:0x32
P:0x34
P:0x36
P:0x38
P:0x3A
P:0x3C
P:0x3E
P:0x40
P:0x42
Reserved for Reset Overlay2
Reserved for COP Reset Overlay
Illegal Instruction
2
N/A
N/A
3
3
3
3
3
3
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
HW Stack Overflow
4
N/A
Misaligned Long Word Access
EOnCE Step Counter
5
N/A
6
N/A
EOnCE Breakpoint Unit
EOnCE Trace Buffer
7
N/A
9
N/A
EOnCE Transmit Register Empty
EOnCE Receive Register Full
Low-Voltage Detector
9
N/A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
29
30
33
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
Phase-Locked Loop Loss of Locks and Loss of Clock
ADCA Conversion Complete
ADCB Conversion Complete
Reload PWM and/or PWM Faults
Comparator 0 Rising/Falling Flag
Comparator 1 Rising/Falling Flag
Comparator 2 Rising/Falling Flag
Flash Memory Access Status
SPI Receiver Full
ADCA
ADCB
PWM
CMP0
CMP1
CMP2
FM
SPI
SPI
SPI Transmitter Empty
SCI
SCI Transmitter Empty/Idle
SCI Receiver Full/Overrun/Errors
I2C Interrupt
SCI
I2C
PIT
Interval Timer Interrupt
TMR0
TMR1
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
RTC
Dual Timer, Channel 0 Interrupt
Dual Timer, Channel 1 Interrupt
GPIOA Interrupt
GPIOB Interrupt
GPIOC Interrupt
GPIOD Interrupt
GPIOE Interrupt
GPIOF Interrupt
Real Time Clock
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
84
Freescale Semiconductor
Interrupt Vector Table
1
Table 43. Interrupt Vector Table Contents (continued)
Vector
Number Encoding
User
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
Reserved
34- 39
0x22-0x27
0
P:0x44 -
P:0x4E
Reserved
core
core
40
41
42
43
44
45
46
47
48
49
50
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
2
3
-1
1
1
1
2
2
2
P:0x50
P:0x52
P:0x54
P:0x56
P:0x58
P:0x5A
P:0x5C
P:0x5E
P:0x60
P:0x62
P:0x64
SW Interrupt 0
SW Interrupt 1
core
SW Interrupt 2
core
SW Interrupt 3
SWILP
USER1
USER2
USER3
USER4
USER5
USER6 3
SW Interrupt Low Priority
User Programmable Priority Level 1 Interrupt
User Programmable Priority Level 1 Interrupt
User Programmable Priority Level 1 Interrupt
User Programmable Priority Level 2 Interrupt
User Programmable Priority Level 2 Interrupt
User Programmable Priority Level 2 Interrupt
1
2
3
Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from
the vector table, providing only 19 bits of address.
If the VBA is set to the reset value, the first two locations of the vector table overlay the chip reset addresses because the
reset address would match the base of this vector table.
USER6 vector can be defined as a fast interrupt if the instruction located in this vector location is not a JSR or BSR instruction.
Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual for detail.
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
85
Appendix B
Peripheral Register Memory Map and Reset Value
NOTE
In Table 44, ADC0 stands for ADCA, ADC1 stands for ADCB, and GPIOn is the same as GPIO_n (for example,
GPIOA_PUR is the same as GPIO_A_PUR).
Table 44. Detailed Peripheral Memory Map
Offset Reset
Bit
Bit
0
Addr. Value Periph. Register
(Hex) (Hex)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
TMR0_
COMP1
00
01
02
03
04
05
0000 TMR0
0000 TMR0
0000 TMR0
0000 TMR0
0000 TMR0
0000 TMR0
COMPARISON_1
COMPARISON_2
CAPTURE
LOAD
TMR0_
COMP2
TMR0_
CAPT
TMR0_
LOAD
TMR0_
HOLD
HOLD
TMR0_
CNTR
COUNTER
TMR0_
CTRL
06
07
0000 TMR0
0000 TMR0
CM
PCS
SCS
DIR
OM
TMR0_
SCTRL
CAPTURE_
MODE
TCF
TOF
IEF IEFIE IPS
VAL
OPS OEN
TMR0_
CMPLD1
08
09
0000 TMR0
0000 TMR0
COMPARATOR_LOAD_1
COMPARATOR_LOAD_2
TMR0_
CMPLD2
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TMR0_
CSCTRL
0A
0000 TMR0
DBG_EN
0
0
0
0
0
TCF2 TCF1
CL2
CL1
TMR0_
FILT
0B
0C–0E
0F
0000 TMR0
0
0
0
0
0
0
0
0
FILT_CNT
FILT_PER
0
—
TMR0 Reserved
RESERVED
TMR_
ENBL
000F TMR0
0000 TMR1
0000 TMR1
0000 TMR1
0000 TMR1
0000 TMR1
0000 TMR1
0
0
0
0
0
0
0
ENBL
TMR1_
COMP1
10
11
12
13
14
15
COMPARISON_1
COMPARISON_2
CAPTURE
LOAD
TMR1_
COMP2
TMR1_
CAPT
TMR1_
LOAD
TMR1_
HOLD
HOLD
TMR1_
CNTR
COUNTER
TMR1_
CTRL
16
17
0000 TMR1
0000 TMR1
CM
PCS
SCS
DIR
OM
TMR1_
SCTRL
CAPTURE_
MODE
TCF
TOF
IEF IEFIE IPS
VAL
OPS OEN
TMR1_
CMPLD1
18
19
0000 TMR1
0000 TMR1
COMPARATOR_LOAD_1
COMPARATOR_LOAD_2
TMR1_
CMPLD2
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TMR1_
CSCTRL
1A
0000 TMR1
DBG_EN
0
0
0
0
0
TCF2 TCF1
CL2
CL1
TMR1_
FILT
1B
0000 TMR1
0
0
0
0
FILT_CNT
FILT_PER
1C–1F
—
TMR1 Reserved
RESERVED
PWM_
PWM
20
0000
LDFQ
HALF
PRSC
ISENS
CTRL
PWM_
PWM
21
22
0000
0000
0
0
0
0
0
FIE3
FIE2
FIE1
FIE0
FCTRL
PWM_
PWM
FLTACK
PWM_
PWM
23
0000
0
0
OUT
PWM_
PWM
24
25
26
27
28
0000
0000
0000
0000
0000
0
0
CR
CNTR
PWM_
PWM
PWMCM
CMOD
PWM_
PWM
PMVAL
VAL0
PWM_
PWM
PMVAL
PMVAL
VAL1
PWM_
PWM
VAL2
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PWM_
VAL3
29
2A
2B
2C
2D
2E
2F
0000
0000
0000
PWM
PWM
PWM
PMVAL
PWM_
VAL4
PMVAL
PMVAL
PWM_
VAL5
PWM_
DTIM0
0FFF PWM
0FFF PWM
FFFF PWM
00FF PWM
0
0
0
0
0
0
0
0
PWMDT0
PWMDT1
PWM_
DTIM1
PWM_
DMAP1
DISMAP_15_0
0
PWM_
DMAP2
0
0
0
0
0
0
0
0
0
DISMAP_23_16
PWM_
CNFG
30
31
0000
0000
PWM
PWM
EDG
0
0
WP
PWM_
CCTRL
nBX
0
0
VLMODE
0
PWM_
PORT
32
33
00-U1 PWM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PORT
PWM_
ICCTRL
0000
0000
PWM
PWM
PEC2 PEC1 PEC0 ICC2 ICC1 ICC0
PWM_
SCTRL
34
0
0
0
SRC2
0
SRC1
0
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PWM_
SYNC
35
0000
PWM
SYNC_WINDOW
PWM_
FFILT0
36
37
38
0000
0000
0000
PWM
PWM
PWM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FILT0_CNT
FILT1_CNT
FILT2_CNT
FILT3_CNT
FILT0_PER
FILT1_PER
FILT2_PER
FILT3_PER
PWM_
FFILT1
PWM_
FFILT2
PWM_
FFILT3
39
0000
—
PWM
PWM
3B–3F
Reserved
RESERVED
INTC_
ICSR
40
0000
INTC
INT
IPIC
VAB
BKPT
INTC_
VBA
41
42
43
0000
0000
0000
INTC
INTC
INTC
0
0
0
0
0
0
0
0
VECTOR_BASE_ADDRESS
INTC_
IAR0
USER2
0
0
0
0
0
USER1
INTC_
IAR1
USER4
USER6
USER3
USER5
INTC_
IAR2
44
0000
—
INTC
INTC
0
45–5F
Reserved
RESERVED
ADC0_
ADCSC1A
60
001F ADC0
0
0
0
0
0
0
0
0
AIEN
ADCH
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ADC0_
ADCSC2
61
0000 ADC0
ADC0
0
0
0
0
0
0
0
0
0
0
0
0
ECC
REFSEL
ADICLK
62–65
—
Reserved
RESERVED
0
ADC0_
ADCCFG
66
0000 ADC0
0
0
0
0
0
0
0
0
0
0
0
0
ADIV
MODE
67–69
6A
—
ADC0
Reserved
RESERVED
0
ADC0_
ADCSC1B
001F ADC0
0000 ADC0
0000 ADC0
0
0
0
AIEN
ADCH
ADC0_
ADCRA
6B
0
0
0
0
0
0
ADC0_
ADCRB
6C
6D–6F
80
—
ADC0
Reserved
RESERVED
0
ADC1_
ADCSC1A
001F ADC1
0000 ADC1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AIEN
ADCH
ECC
ADC1_
ADCSC2
81
0
0
0
0
REFSEL
ADICLK
82–85
—
ADC1
Reserved
RESERVED
ADC1_
ADCCFG
86
0000 ADC1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADIV
MODE
87–89
8A
—
ADC1
Reserved
RESERVED
0
ADC1_
ADCSC1B
001F ADC1
AIEN
ADCH
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ADC1_
ADCRA
8B
8C
0000 ADC1
0000 ADC1
0
0
0
0
0
0
0
0
ADC1_
ADCRB
8D–8F
A0
—
ADC1
Reserved
RESERVED
PGA0_
CNTL0
0000 PGA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TM
GAINSEL
LP
EN
PGA0_
CNTL1
A1
0002 PGA0
0
0
0
CALMODE
CPD
PGA0_
CNTL2
A2
A3
000E PGA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NUM_CLK_GS
ADIV
0000 PGA0 PGA0_STS
0
0
0
A4–BF
C0
—
PGA0
Reserved
RESERVED
PGA1_
CNTL0
0000 PGA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TM
GAINSEL
LP
EN
PGA1_
CNTL1
C1
C2
0002 PGA1
0
0
CALMODE
CPD
PGA1_
CNTL2
000E PGA1
0
0
0
0
0
0
0
0
0
0
NUM_CLK_GS
ADIV
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C3
0000 PGA1 PGA1_STS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C4–DF
E0
—
PGA1
SCI
Reserved
RESERVED
0200
SCI_RATE
SBR
PE
FRAC_SBR
SCI_
CTRL1
E1
E2
E3
0000
0000
C000
SCI
SCI
SCI
SWAI
0
M
0
POL
0
PT
0
TEIE TIIE RFIE REIE TE
RE RWU SBK
SCI_
CTRL2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCI_STAT
OR
0
NF
0
FE
0
PF
LSE
RAF
E4
0000
—
SCI
SCI
SCI_DATA
Reserved
0
SPR
0
0
RECEIVE_TRANSMIT_DATA
E5–FF
RESERVED
SPI_
SCTRL
00
01
6141
000F
SPI
SPI
DSO
BD2X
SPE
SPTE
SPI_
DSCTRL
WOM
0
SPR3
DS
02
03
0000
0000
—
SPI
SPI
SPI
I2C
SPI_DRCV R15 R14 R13 R12 R11 R10
R9
T9
R8
T8
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SPI_DXMIT T15
Reserved
T14
T13
T12
T11
T10
04–1F
20
RESERVED
0000
I2C_ADDR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AD7 AD6 AD5 AD4 AD3 AD2 AD1
MULT ICR
0
I2C_
FREQDIV
21
0000
I2C
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
22
0000
I2C
I2C_CR1
0
0
0
0
0
0
0
0
IICIE MST
TX TXAK RSTA
0
0
23
24
0080
0000
I2C
I2C
I2C_SR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TCF IAAS
ARBL
DATA
0
SRW IICIF
I2C_DATA
25
0000
I2C
I2C_CR2
0
0
0
0
0
0
0
0
0
0
0
AD10 AD9 AD8
I2C_SMB_
CSR
26
0000
I2C
0
0
0
0
0
0
0
0
SLTF SHTF
0
0
0
I2C_
ADDR2
27
28
0000
0000
I2C
I2C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SAD7 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1
I2C_SLT1
29
0000
—
I2C
I2C
I2C_SLT2
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
30–3F
RESERVED
COP_
CTRL
40
41
0302
FFFF
COP
COP
PSS
0
CLKSEL
CEN CWP
COP_
TOUT
TIMEOUT
COP_
CNTR
42
FFFF
—
COP
COP
COUNT_SERVICE
RESERVED
43–5F
Reserved
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
OCCS_
CTRL
60
61
0011 OCCS
2000 OCCS
PLLIE1
PLLIE0
0
0
0
0
0
0
0
0
0
ZSRC
OCCS_
DIVBY
LORTP
COD
0
0
0
0
0
0
OCCS_
STAT
62
64
0015 OCCS
LOCI
0
0
0
0
0
LCK1 LCK0
0
ZSRC
OCCS_
OCTRL
1611 OCCS
0000 OCCS
TRIM
OCCS_
CLKCHKR
65
66
REFERENCE_CNT
OCCS_
CLKCHKT
0000 OCCS
0000 OCCS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TARGET_CNT
OSCEP
OCCS_
PROT
67
68–7F
80
0
FRQEP
PLLEP
—
OCCS Reserved
RESERVED
GPIOA_
PUR
00FF GPIOA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PU
D
81
0000 GPIOA GPIOA_DR
GPIOA_
0000 GPIOA
DDR
82
DD
GPIOA_
0080 GPIOA
PER
83
84
0
0
0
0
0
0
0
0
PE
—
GPIOA Reserved
RESERVED
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GPIOA_
IENR
85
86
87
0000 GPIOA
0000 GPIOA
0000 GPIOA
0000 GPIOA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IEN
IPOL
IP
GPIOA_
IPOLR
GPIOA_
IPR
GPIOA_
IESR
88
89
8A
IES
—
GPIOA Reserved
RESERVED
0
GPIOA_
RAWDATA
0000 GPIOA
0000 GPIOA
0
0
0
0
0
0
0
RAWDATA
GPIOA_
DRIVE
8B
8C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRIVE
IFE
00FF GPIOA GPIOA_IFE
0
GPIOA_
0000 GPIOA
SLEW
8D
0
SLEW
8E–9F
A0
—
GPIOA Reserved
RESERVED
GPIOB_
PUR
00FF GPIOB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PUR
DR
A1
0000 GPIOB GPIOB_DR
GPIOB_
0000 GPIOB
DDR
A2
DDR
GPIOB_
0080 GPIOB
PER
A3
A4
A5
0
0
0
0
0
0
0
0
PER
—
GPIOB Reserved
RESERVED
0
GPIOB_
IENR
0000 GPIOB
0000 GPIOB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IENR
GPIOB_
IPOLR
A6
0
IPOLR
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GPIOB_
IPR
A7
0000 GPIOB
0000 GPIOB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IPR
GPIOB_
IESR
A8
A9
AA
IESR
—
GPIOB Reserved
RESERVED
0
GPIOB_
RAWDATA
0000 GPIOB
0000 GPIOB
0
0
0
0
0
0
0
RAWDATA
GPIOB_
DRIVE
AB
AC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRIVE
IFE
00FF GPIOB GPIOB_IFE
0
GPIOB_
0000 GPIOB
SLEW
AD
0
SLEW
AE–BF
C0
—
GPIOB Reserved
RESERVED
GPIOC_
PUR
00FF GPIOC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PUR
DR
C1
0000 GPIOC GPIOC_DR
GPIOC_
0000 GPIOC
DDR
C2
DDR
GPIOC_
0080 GPIOC
PER
C3
C4
C5
0
0
0
0
0
0
0
0
PER
—
GPIOC Reserved
RESERVED
0
GPIOC_
IENR
0000 GPIOC
0000 GPIOC
0000 GPIOC
0000 GPIOC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IENR
IPOLR
IPR
GPIOC_
IPOLR
C6
C7
C8
0
0
0
GPIOC_
IPR
GPIOC_
IESR
IESR
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C9
CA
—
GPIOC Reserved
GPIOC_
RESERVED
0
0000 GPIOC
0000 GPIOC
00FF GPIOC
0000 GPIOC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RAWDATA
DRIVE
IFE
RAWDATA
GPIOC_
DRIVE
CB
CC
0
0
GPIOC_
IFE
GPIOC_
SLEW
CD
CE–DF
E0
0
SLEW
—
GPIOC Reserved
RESERVED
GPIOD_
PUR
00FF GPIOD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PUR
DR
E1
0000 GPIOD GPIOD_DR
GPIOD_
0000 GPIOD
DDR
E2
DDR
GPIOD_
0080 GPIOD
PER
E3
E4
E5
0
0
0
0
0
0
0
0
0
0
0
0
PER
—
GPIOD Reserved
RESERVED
GPIOD_
IENR
0000 GPIOD
0000 GPIOD
0000 GPIOD
0000 GPIOD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IENR
GPIOD_
IPOLR
E6
E7
IPOLR
IPR
GPIOD_
IPR
GPIOD_
IESR
E8
E9
EA
IESR
—
GPIOD Reserved
RESERVED
GPIOD_
RAWDATA
0000 GPIOD
0
0
0
0
0
0
0
0
0
0
0
0
RAWDATA
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GPIOD_
DRIVE
EB
EC
0000 GPIOD
00FF GPIOD
0000 GPIOD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRIVE
GPIOD_
IFE
IFE
GPIOD_
SLEW
ED
EE–9F
00
SLEW
—
GPIOD Reserved
RESERVED
GPIOE_
PUR
00FF GPIOE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PUR
DR
01
0000 GPIOE GPIOE_DR
GPIOE_
0000 GPIOE
DDR
02
DDR
GPIOE_
0080 GPIOE
PER
03
04
05
0
0
0
0
0
0
0
0
PER
—
GPIOE Reserved
RESERVED
0
GPIOE_
IENR
0000 GPIOE
0000 GPIOE
0000 GPIOE
0000 GPIOE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IENR
GPIOE_
IPOLR
06
07
0
0
IPOLR
IPR
GPIOE_
IPR
GPIOE_
IESR
08
09
0A
0
IESR
—
GPIOE Reserved
RESERVED
0
GPIOE_
RAWDATA
0000 GPIOE
0000 GPIOE
0
0
0
0
0
0
0
RAWDATA
GPIOE_
DRIVE
0B
0C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRIVE
IFE
00FF GPIOE GPIOE_IFE
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GPIOE_
SLEW
0D
0E–1F
20
0000 GPIOE
0
0
0
0
0
0
0
0
SLEW
—
GPIOE Reserved
RESERVED
GPIOF_
PUR
00FF GPIOF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PUR
DR
21
0000 GPIOF GPIOF_DR
GPIOF_
0000 GPIOF
DDR
22
DDR
GPIOF_
0080 GPIOF
PER
23
24
25
0
0
0
0
0
0
0
0
0
0
0
0
PER
—
GPIOF Reserved
RESERVED
GPIOF_
IENR
0000 GPIOF
0000 GPIOF
0000 GPIOF
0000 GPIOF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IENR
GPIOF_
IPOLR
26
27
IPOLR
IPR
GPIOF_
IPR
GPIOF_
IESR
28
29
2A
IESR
—
GPIOF Reserved
RESERVED
GPIOF_
RAWDATA
0000 GPIOF
0000 GPIOF
0
0
0
0
0
0
0
0
0
0
0
0
RAWDATA
GPIOF_
DRIVE
2B
2C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRIVE
IFE
00FF GPIOF GPIOF_IFE
GPIOF_
0000 GPIOF
SLEW
2D
SLEW
2E–3F
—
GPIOF Reserved
RESERVED
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
STOP_
DISABLE
WAIT_
DISABLE
40
41
0000
0001
SIM
SIM
SIM_CTRL
0
0
0
0
0
0
0
0
0
0
0
SIM_
RSTAT
0
0
0
0
0
0
0
0
SWR
LVDR PPD POR
SIM_
MSHID
42
43
01F2
601D
SIM
SIM
SIM_MSH_ID
SIM_LSH_ID
SIM_
LSHID
SIM_
CLKOUT
45
46
2020
0000
SIM
SIM
0
0
0
0
0
0
CLKOSEL1
0
0
0
0
0
CLKOSEL0
SIM_PCR
0
0
0
0
0
0
0
0
47
48
0000
0000
SIM
SIM
SIM_PCE
SIM_SDR
I2C
I2C
SCI
SCI
SPI PWM COP PDB PIT
SPI PWM COP PDB PIT
TA1
TA0
TA1
0
TA0
0
49
4A
4B
F000
0000
0000
SIM
SIM
SIM
SIM_ISAL
SIM_PROT
SIM_GPSA
ADDR_15_6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCEP
GIPSP
GPS_A3
GPS_A6
GPS_A5
GPS_A4
SIM_
GPSB0
4C
4D
0000
0000
SIM
SIM
GPS_B5
GPS_B4
0
GPS_B3
0
GPS_B2
0
0
GPS_B1
GPS_B0
SIM_
GPSB1
0
0
0
0
0
0
0
0
GPS_B7
GPS_B6
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
4E
4F
0000
0000
SIM
SIM
SIM_GPSC
SIM_GPSD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPS_D3
GPS_D2
GPS_D1
IPS_PSRC1
IPS_T1
GPS_D0
50
0000
SIM
SIM_IPS0
0
0
0
0
0
IPS_PSRC2
IPS_PSRC0
IPS_T0
51
0000
—
SIM
SIM
SIM_IPS1
Reserved
IPS_C2_WS
IPS_C1_WS
IPS_C0_WS
RESERVED
52–5F
60
61
0208
PMC PMC_SCR
PMC PMC_CR2
LVDF
LPR LPRS
LVDE LVLS
TRIM
PROT
00--2
—
0
0
0
0
0
0
0
LPO_TRIM
7F
80
PMC
Reserved
RESERVED
CMP0_
CR0
0000 CMP0
0000 CMP0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FILTER_CNT
PMC
MMC
CMP0_
CR1
81
SE
WE
0
INV COS OPE
EN
CMP0_
FPR
82
83
0000 CMP0
0000 CMP0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FILT_PER
CMP0_
SCR
0
0
0
IER
IEF CFR CFF
84–9F
A0
—
CMP0 Reserved
CMP1_
RESERVED
0000 CMP1
0
0
0
0
0
0
0
0
0
FILTER_CNT
PMC
MMC
CR0
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CMP1_
CR1
A1
0000 CMP1
0
0
0
0
0
0
0
0
SE
WE
0
INV COS OPE
EN
CMP1_
FPR
A2
A3
0000 CMP1
0000 CMP1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FILT_PER
CMP1_
SCR
0
0
0
IER
IEF CFR CFF
A4–BF
C0
—
CMP1 Reserved
CMP2_
RESERVED
0000 CMP2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FILTER_CNT
PMC
MMC
CR0
CMP2_
CR1
C1
C2
0000 CMP2
SE
WE
0
INV COS OPE
EN
CMP2_
FPR
0000 CMP2
0000 CMP2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FILT_PER
CMP2_
SCR
C3
0
0
0
IER
IEF CFR CFF
C4–DF
—
CMP2 Reserved
RESERVED
E0
0000
PIT
PIT_CTRL
0
0
0
0
0
0
0
0
0
PRESCALER
PRF PRIE
E1
E2
0000
0000
—
PIT
PIT
PIT
PIT_MOD
PIT_CNTR
Reserved
MODULO_VALUE
COUNTER_VALUE
RESERVED
E3–FF
00
01
0000
0000
PDB
PDB
PDB_SCR
PRESCALER
0
AOS
0
BOS
TRIGSEL
ENA ENB
PDB_
DELAYA
DELAYA
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PDB_
DELAYB
02
03
04
0000
FFFF
FFFF
PDB
DELAYB
MOD
PDB PDB_MOD
PDB_
PDB
COUNT
COUNT
05–1F
20
—
PDB
RTC
RTC
RTC
RTC
Reserved
RTC_SC
RESERVED
0000
0000
0000
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RTIF
RTCLKS
RTIE
RTCPS
21
RTC_CNT
RTC_MOD
Reserved
RTCCNT
RTCMOD
22
23–FF
RESERVED
FM_
CLKDIV
00
01
0000
0000
HFM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DIV
HFM FM_CNFG
HFM FM_SECHI
AEIE
CCIE
0
0
0
LBTS BTS
03
04
-0003
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FM_
HFM
0000
—
0
0
0
SEC
SECLO
06–0F
10
HFM
Reserved
FM_PROT
Reserved
RESERVED
PROTECT
FFFF6 HFM
11
—
HFM
RESERVED
13
14
00C0
0000
HFM FM_USTAT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CCIF
0
0
0
HFM
FM_CMD
0
0
CMD
Table 44. Detailed Peripheral Memory Map (continued)
Offset Reset
Addr. Value Periph. Register
(Hex) (Hex)
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
1A
1B
—
0000
—
HFM
HFM
HFM
Reserved
FM_DATA
Reserved
FM_OPT0
FM_OPT1
RESERVED
FMDATA
RESERVED
IFR_OPT0
IFR_OPT1
FFFF4 HFM
FFFF5 HFM
FM_
TSTSIG
1D
FFFF6 HFM
TST_AREA_SIG
RESERVED
1E–3F
—
HFM
Reserved
1
2
3
The binary reset value of this register is 0000 0000 0UUU UUUU, where U represents an undefined value. Spaces have been added to the value for clarity.
The binary reset value of this register is 0000 0000 111NC NC NC NC NC. Spaces have been added to the value for clarity.
The binary reset value of this register is FS00 0000 0000 0000, where F indicates that the reset state is loaded from the flash array during reset, and where S
indicates that the reset state is determined by the security state of the module. Spaces have been added to the value for clarity.
4
5
6
The reset state is loaded from the flash array during reset.
The reset state is loaded from the flash array during reset.
The reset state is loaded from the flash array during reset.
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Document Number: MC56F8006
Rev. 4
06/2011
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