935324621557 [NXP]

Microprocessor Circuit;


型号：	935324621557
厂家：	NXP
描述：	Microprocessor Circuit 外围集成电路
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Document Number: MKW01Z128

Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Data Sheet: Technical Data

MKW01Z128

ꢀꢁꢂꢀꢀ

Package Information

Ordering Information

MKW01Z128

Highly-integrated, cost-effective

single-package solution for

sub-1 GHz applications

Device

Device Marking

Package

MKW01Z128CHN MKW01Z128CHN

60 LGA

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Software Solutions . . . . . . . . . . . . . . . . . . . . . 5

4 Smart Radio Sub-1 GHz Wireless Node . . . . 5

5 MKW01 Pin Assignments and Connections 9

6 System and Power Management . . . . . . . . 15

7 Development Environment . . . . . . . . . . . . . 20

8 System Electrical Specification . . . . . . . . . 20

9 Typical Applications Circuit . . . . . . . . . . . . 25

10Mechanical Drawings . . . . . . . . . . . . . . . . . . 28

Appendix AMKW01 MCU Section Data Sheet 30

1 Introduction

The MKW01 device is highly-integrated, cost-effective,

smart radio, sub-1 GHz wireless node solution composed

of a transceiver supporting FSK, GFSK, MSK, or OOK

modulations with a low-power ARM® Cortex M0+

CPU. The highly integrated RF transceiver operates over

a wide frequency range including 315 MHz, 433 MHz,

470 MHz, 868 MHz, 915 MHz, 928 MHz, and 955 MHz

in the license-free Industrial, Scientific and Medical

(ISM) frequency bands. This configuration allows users

to minimize the use of external components.

The MKW01 is targeted for the following low-power

wireless applications:

•

Automated Meter Reading

Wireless Sensor Networks

Home and Building Automation

Wireless Alarm and Security Systems

Industrial Monitoring and Control

Freescale supplements the MKW01 with tools and

software that include hardware evaluation and

development boards, software development IDE and applications, drivers, custom PHY usable with

Freescale’s IEEE 802.15.4 compatible MAC and SMAC.

2 Features

This section provides a simplified block diagram and highlights MKW01 features.

2.1

Block Diagram

Figure 1 shows a simplified block diagram of the MKW01.

Kinetis MKW01 Wireless MCU

Memory

Sub-1 GHz Transceiver

Core

System

DMA

ARM Cortex-M0+

48 MHz

RF Transmitter and

Receiver

128 KB Flash

Low-Leakage

Wake-Up Unit

16 KB RAM

Interrupt

Controller

PLL

Synthesizer

Debug

Interfaces

32 MHz

Oscillator

Packet Engine

(AES)

66 Byte

FIFO

Interfaces

Clocks

Analog

Timers

2x I²C

Six-Channel

Timer/PWM (TPM)

Phase-Locked

Loop

12-bit DAC

3x UART

1x SPI

Periodic

Interrupt

Timers

Frequency-

Locked Loop

16-bit ADC

Reference

Oscillators

Analog

Comparator

Low-Power

Timer

GPIOs

Real-Time Clock

32-bit Timer

Internal Reference

Clocks

Touch Sensing

Figure 1. MKW01 Simplified Block Diagram

2.2

Features Summary

•

RF Transceiver Features

— Operating Voltage from 1.8V to 3.6V.

— Programmable bit rate up to 600kbps (FSK)

— High Sensitivity: down to -120 dBm at 1.2 kbps

— High Selectivity: 16-tap FIR Channel Filter

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

— Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm, 80 dB Blocking Immunity, no Image

Frequency response

— Low current: Rx = 16mA, 100nA register retention

— Programmable Pout : -18 to +17 dBm in 1 dB steps

— Constant RF performance over voltage range of chip

— Fully integrated synthesizer with a resolution of 61 Hz

— FSK, GFSK, MSK, GMSK and OOK modulations

— Built-in Bit Synchronizer performing Clock recovery

— Incoming Sync Word Recognition

— Automatic RF Sense with ultra-fast AFC

— Packet engine with CRC, AES-128 encryption and 66-byte FIFO

— Built-in temperature sensor and Low battery indicator

— 32 MHz crystal oscillator clock source

— Dedicated I/O’s for connection with an external 32 kHz crystal

— Can be configured to be compliant with the relevant sections of numerous world-wide

standards, including but not limited to: ARIB-T108 and T67, FCC 15.231, 15.247, and 15.249,

EN54-25, and ETSI 300 220.

•

MCU Features

System:

— 48 MHz Max. Central Processor Unit (CPU) frequency

— 24 MHz Max. Bus frequency

— Vectored Interrupt Controller (NVIC) with 32 core-vectored interrupts with 4 programmable

interrupt priority levels

— Asynchronous Wake-up Interrupt Controller (AWIC)

— 4 channel Direct Memory Access (DMA)

— DMA request multiplex

— Non Maskable Interrupt (NMI)

— COP Watchdog

— Low leakage Wake-up Unit (LLWU)

— Debug and Trace

– 2-pin Serial Wire Debug (SWD)

— 80-bit wide ID number

Memory:

— 128 KB P-Flash with 64 byte flash cache

— 16 KB RAM

Clocks:

— External crystal oscillator or resonator:

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

– 32 - 40 kHz low range, low power or full swing

– 3 MHz - 32 MHz high range, low power or full swing

— DC - 48 MHz external square wave input clock

— Internal clock references:

– 31.25 kHz to 39.063 kHz oscillator with +/– 1.5% max. deviation from 0 to +70C

– 4 MHz oscillator with +/– 3% max. deviation across temperature

– 1 kHz oscillator

— Phase Locked Loop (PLL) with up to 100 MHz VCO

— Frequency Locked Loop (FLL):

– Low range: 20 - 25 MHz

– Mid range: 40 - 48 MHz

Analog:

— Power Management Controller (PMC) with low voltage warning (LVW) and detect with

selectable trip points.

— 16-bit analog to digital converter

– 11 single ended channels available

– 2 status, control and results registers

– DMA support

— 1 High Speed Comparator (HSCMP) with internal 6-bit digital to analog converters (DAC)

— One 12-bit DAC with DMA support and 2 word data buffer

Timers:

— Six channel Timer/PWM (TPM)

— Periodic interrupt timers

— 16-bit low-power timer (LPTMR) can be configured to operate as a time counter or as a pulse

counter, across all power modes, including the low-leakage modes

— Real-time clock 32-bit timer

Wired Communication Interface:

— One Serial Peripheral Interface (SPI) available externally

— Two Inter-Integrated Circuits (I C) with DMA support

— Three Universal Asynchronous Receiver / Transmitter (UART) with DMA Support

– UART0 supports standard features plus:

• TxD pin can be configured as pseudo open drain for 1-wire half-duplex

• x4 to x32 oversampling

• Functional in VLPS mode

• LIN slave operation

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

– UART1 and UART2 support standard features

Human Machine Interface (HMI)

— General Purpose Input/Output (GPIO) supporting:

– Default to disabled (no leakage)

– 4 pins with 18 mA high current drive capability

– Hysteresis and configurable pull up device on all input pins

– Slew rate and drive strength fixed on all output pins

– Single cycle GPIO control via IOPORT

— Touch Sensor Inputs (TSI)

– 9-channel

– Selectable single channel wakeup source available in all modes

– DMA support

— Pin Interrupt

1.8 V to 3.6 V operating voltage with on-chip voltage regulators

Temperature range of –40C to 85C

60-pin LGA (8x8 mm) package

3 Software Solutions

Freescale will support the MKW01x128 platform with several software solutions:

•

A radio utility GUI will be available that allows testing of various features and setting registers. A

connectivity test firmware will allow a limited set of testing controlled with a terminal emulator on

any computer.

SMAC (Simple Media Access Controller) — This codebase provides simple communication and

test apps based on drivers/PHY utilities available as source code. This environment is useful for

hardware and RF debug, hardware standards certification, and developing proprietary applications.

Additional software will be available through 3rd party providers.

4 Smart Radio Sub-1 GHz Wireless Node

The MKW01 brings together a transceiver chip and an MCU chip on a single substrate to provide a small

footprint, cost-effective sub-1 GHz wireless node. The transceiver is controlled by the MCU through a

dedicated SPI interface. The SPI bus interface and some status signals are connected in-package the

substrate to eliminate the need for external connections. The SPI supports bit order swapping providing

hardware support for bit endianess reducing processing overhead.

4.1

RF Transceiver

The transceiver (see Figure 2) is a single-chip integrated circuit ideally suited for today's high performance

ISM band RF applications. Its advanced features set, including state of the art packet engine, greatly

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

simplifies system design while the high level of integration reduces the external RF component bill of

material (BOM) to a handful of passive de-coupling and matching components. It is intended for use as a

high-performance, low-cost FSK, GFSK, MSK, GMSK, and OOK RF transceiver for robust, frequency

agile, half-duplex bi-directional RF links.

The MKW01 is intended for applications over a wide frequency range, including the 433 MHz, the

868 MHz European, and the 902-928 MHz North American ISM bands. Coupled with a link budget in

excess of 135 dB, the transceiver advanced system features include a 66 byte TX/RX FIFO, configurable

automatic packet handler, listen mode, temperature sensor and configurable DIO’s which greatly enhance

system flexibility while at the same time significantly reducing MCU requirements. The transceiver

complies with both ETSI and FCC regulatory requirements.

Figure 2. MKW01 Transceiver Block Diagram

The major RF communication parameters of the MKW01 transceiver are programmable and most can be

dynamically set. This feature offers the unique advantage of programmable narrow-band and wide-band

communication modes without the need to modify external components. The transceiver is also optimized

for low power consumption while offering high RF output power and channelized operation.

4.2

ARM ® 32-bit Cortex M0+ CPU

The in-package MCU integrated circuit features an ARM ® Cortex M0+ CPU, up to 16 KB RAM, 128

KB Flash memory, and a rich set of peripherals (see Section 2.2, “Features Summary”). The RF transceiver

is controlled through the MCU SPI port which is dedicated to the RF device interface. Two of the

transceiver status IO lines are also directly connected to the MCU GPIO to monitor the transceiver

operation. In addition, the transceiver reset and additional status can be connected to the MCU through

external connections.

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Operational modes of the MKW01 are determined by the software running on the MCU. The MCU itself

has a run mode as well as an array of low power modes that are coordinated by the PMC. The MCU in turn

set the operational modes of the transceiver which include sleep, standby, and radio operational modes.

Two common application scenarios are:

•

Low power, battery-operated standalone wireless node - a common example of this configuration

would be a remote sensor monitor. The wireless node programmed for standalone operation,

typically has a low active-mode duty cycle, and is designed for long battery life, i.e., lowest power.

•

Communication channel to a higher level controller - in this example, the wireless node

implements the lower levels of a communications stack and is subordinate to the primary

controller. Typically the MKW01 is connected to the controller through a command channel

implemented via a UART/SCI port or other serial communication port.

4.3

System Clock Configuration

The MKW01 device allows for various system clock configurations:

•

Pins 46 & 47 are provided to input a 32 or 30 MHz crystal for the transceiver reference clock source

(required) as shown in Figure 3.

•

The transceiver can be programmed to provide a programmable frequency clock output (DIO5

which alternates as CLKOUT, pin 54) that can be used as an external source to the CPU (see

Figure 3 and Figure 4). As a result, a single crystal system clock solution is possible where the

transceiver reference clock source. Routing CLKOUT to the MCU without dividing it is

recommended, but it can be divided by 2, 4, 8, 16 and 32.

•

The MCU provides a trimmable internal reference clock and also supports an external clock

source. An optional on-chip frequency locked loop (FLL) can be used with either clock source to

support a CPU clock as high as 48 MHz at 3.6 V.

Pins 16 and 15 are available to provide an external 32.768 kHz external clock source for the MCU.

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Figure 3. MKW01 Single Crystal System Clock Connection

Figure 4. MKW01 Two Crystal System Clock Connection

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

5 MKW01 Pin Assignments and Connections

Figure 5 shows the MKW01 pinout.

Figure 5. MKW01 Pinout (Top View)

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

5.1

Pin Definitions

Table 1 details the MKW01 pinout and functionality.

Table 1. Pin Function Description (Sheet 1 of 5)

Pin Name¹

Type

Description

Functionality

VREFH

VREFL

VSSA

VSS

Input

MCU high reference voltage for ADC

MCU low reference voltage for ADC

Power Input MCU ADC Ground

Power Input MCU Ground

Connect to ground

PTE16/ADC0_DP1/ADCO_S Digital Input / MCU Port E Bit 16 / ADC0 Single Ended

E1/SPI0_PCS0/TPM/UART2_ Output

analog channel input DP1/ ADC0 Single

Ended analog channel input SE1 / SPI

module 0 PCS0 / TPM module Clock In 0 /

UART2_TX

PTE17/ADC0_DM1/ADCO_S Digital Input / MCU Port E Bit 17 / ADC0 Single Ended

E5a/SPI0_SCK/

TPM_CLKIN1/UART2_RX/

LPTMR0_ALT3

Output

analog channel input DM1/ ADC0 Single

Ended analog channel input 5a / SPI

module 0 SCK / TPM module Clock In 1 /

UART2_RX / Low Power Timer Module 0

ALT3

PTE18/ADC0_DP2/ADC0_SE Digital Input / MCU Port E Bit 18 / ADC0 Single Ended

2/SPI0_MOSI/IIC0_SDA/SPI0 Output

_MISO

analog channel input DP2/ ADC0 Single

Ended analog channel input 2 / SPI module

0 MOSI / IIC0 Bus Data / SPI module 0

MISO

PTE19/ADC0_DM2/

Digital Input / MCU Port E Bit 19 / ADC0 Single Ended

ADC0_SE6a/SPI0_MISO

/IIC0_SCL/ SPI0_MOSI

Output

analog channel input DM2/ ADC0 Single

Ended analog channel input 6a / SPI

module 0 MISO / IIC0 Bus Clock / SPI

module 0 MOSI

PTE30/DAC0_OUT/

ADCO_SE23/

CMP0_IN4/TPM0_CH3/TPM_

CLKIN1

Digit-l Input / MCU Port E Bit 30 / DAC0 Output/ ADC0

Output

Single Ended analog channel input 23 /

Comparator 0 Analog Voltage Input 4/ TPM

Timer module 0 Channel 3 / TPM module

Clock In 1

PTA0/SWD_CLK/TSI0_CH1/T Digital Input / MCU Port A Bit 0 / Serial Wire Data Clock

PM0_CH5

Output

/ Touch Screen Interface Channel 1/ TPM

module 0 Channel 5

PTA3/SWD_DIO/TSI0_CH4/

IIC1_SCL/TPM0_CH0

Digital Input / MCU Port A Bit 3 / Serial Wire Data DIO /

Output

Touch Screen Interface Channel 4 / IIC1

Bus Clock / TPM module 0 Channel 0

PTA4/NMI_b/TSI0_CH5/

IIC1_SDA/TPM0_CH1

Digital Input / MCU Port A Bit 4/ / Non Maskable

Output

Interrupt_ b/Touch Screen Interface

Channel 5 /IIC1 Bus Data / TPM module 0

Channel 1

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Table 1. Pin Function Description (Sheet 2 of 5)

Type Description

PTA2/TSI0_CH3/UART0_TX/ Digital Input / MCU Port A Bit 2/Touch Screen Interface

Pin Name¹

Functionality

TPM2_CH1

Output

Channel 3/UART module 0 Transmit / TPM

module 2 Channel 1

PTA1/TSI0_CH2/UART0_RX/ Digital Input / MCU Port A Bit 1/Touch Screen Interface

TPM2_CH0

Output

Channel 2/UART module 0 Receive / TPM

module Channel 0

PTA18/EXTAL0/UART1_RX/

TPM_CLKIN0

Digital Input / MCU Port A Bit 18 / EXTAL0/ UART

Output module 1 Receive / TPM module Clock In 0

PTA19/XTAL0/UART1_TX/TP Digital Input / MCU Port A Bit 19 / XTAL0/ UART module

M_CLKIN1/LPTMR0_ALT1

Output

1 Transmit / TPM module Clock In 1

/Low Power Timer module 0 ALT1

PTB0/ADC0_SE8/TSI0_CH0/ Digital Input / MCU Port B Bit 0 / ADC0 Single Ended

LLWU_P5/IIC0_SCL/

TPM1_CH0

Output

analog channel input SE8 / Touch Screen

Interface Channel 0/ Low Leakage Wake

Up Port 5 / IIC0 Bus Clock / TPM module 1

Channel 0

PTB1/ADCO_SE9/TSI0_CH6/ Digital Input / MCU Port B Bit 1 / ADC0 Single Ended

IIC0_SDA/ TPM1_CH1

Output

analog channel input SE9 / Touch Screen

Interface Channel 6 / IIC0 Bus Data / TPM

module 1 Channel 1

VDD

VSS

Power Input MCU VDD supply input

Connect to system VDD

supply

Power Input MCU Ground

Connect to ground

PTB2/ADC0_SE12/TSI0_CH7 Digital

/IIC0_SCL/TPM2_CH0

MCU Port B Bit 2 / ADC0 Single Ended

Input/Output analog channel input SE12 / Touch Screen

Interface Channel 7 / IIC0 Bus Clock / TPM

Timer module 2 Channel 0

PTB17/TSI0_CH10/SPI1_MIS Digital

O/UART0_TX/TPM_CLKIN1/ Input/Output Channel 10/SPI1 MOSI or MISO/UART0

SPI1_MOSI TX / TPM timer clock

MCU Port B Bit 17 / Touch Screen Interface

PTC4/LLWU_P8/SPI0_PCS0/ Digital Input / MCU Port C bit 4 / Low leakage Wake Up

UART1_TX/TPM0_CH3

Output

port 8 / SPI0 Chip Select / UART1 TX /

TPM Timer module 0 channel 3

PTC1/ADC0_SE15/TSI0_CH1 Digital Input MCU Port C Bit 1 /ADC0 Single Ended

4/LLWU_P6/RTC_CLKIN/

IIC1_SCL/TPM0_CH0

Output /

analog channel input SE15/ Touch Screen

Analog Input Interface Channel 14/ Low Leakage Wake

Up Port 6 / Real Time Counter Clock Input/

IC1 Bus Clock/ TPM module 0 Channel 0

PTC2/ADC0_SE11/TSI0_CH1 Digital Input / MCU Port C Bit 2 / ADC0 Single Ended

5/IIC1_SDA/TPM0_CH1 Output / analog channel input SE11/ / Touch Screen

Analog Input Interface Channel 15 / IIC1 Bus Data / TPM

module 0 Channel 1

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Table 1. Pin Function Description (Sheet 3 of 5)

Type Description

PTC3/LLWU_P7/UART1_RX/ Digital Input / MCU Port C Bit 3 / Low Leakage Wake Up

Pin Name¹

Functionality

TPM0_CH2/CLKOUTa

Output

Port 7 / UART module 1 Receive / TPM

module 0 Channel 2/ Clock OutA

PTD4/LLWU_P14/SPI1_PCS0 Digital Input / MCU Port D Bit 4 / Low Leak Wake Up Port

/UART2_RX/TPM0_CH4

Output

14/ SPI module 1 PCS0 / UART2 Receiver

input / TPM module 0 Channel 4

PTD5/ADC0_SE6b/SPI1_SC Digital Input / MCU Port D bit 5 / ADC0 Single Ended

K/UART2_TX/TPM0_CH5 Output / analog channel input SE6b / SPI1 clock /

Analog Input UART2 TX / TPM module 0 Channel 5

PTD6/ADC0_SE7b/LLWU_P1 Digital Input / MCU Port D bit 6 / ADC0 Single Ended

5/SPI1_MOSI/UART0_RX/SPI Output / analog channel input SE7b / Low leakage

1_MISO

Analog Input Wake Up port 15 / SPI1 MOSI / UART0 RX

/ SPI module 1 MISO

No Connect

PTD7/SPI0_MISO/UART0_TX Digital

MCU Port D Bit 7 / SPI module 0 MISO /

/SPI1_MOSI

Input/Output UART module 0 Transmit / SPI module 1

MOSI

PTE0/SPI1_MISO/UART1_TX Digital

MCU Port E Bit 0 / SPI module 1 MISO /

/RTC_CLKOUT/CMP0_OUT/ Input/Output UART module 1 Transmit / Real Time

IIC1_SDA

Counter Clock Output / Comparator 0

Analog voltage Output / IIC1 Bus Data

PTA20/RESETB

Digital

Input/Output

MCU Port A Bit 20/MCU RESET

PTE1 / SPI1_MOSI /

UART1_RX /SPI1_MISO /

IIC1_SCL

Digital

MCU Port E Bit 1 / SPI module 1 MOSI /

Input/Output UART module 1 RX / SPI1_MISO /

IIC1_SCL

VBAT2 (RF)

Power Input Transceiver VDD

Connect to system VDD

supply

GND/SCAN (RF)

RXTX (RF)

Power Input Transceiver Ground

Connect to ground

Digital

Output

Transceiver Rx / Tx RF Switch Control

Output; high when in TX

GND_PA2 (RF)

RFIO (RF)

Power Input Transceiver RF Ground

RF Input /

Output

Transceiver RF Input / Output

GND_PA1 (RF)

Power Input Transceiver RF Ground

PA_BOOST (RF)

RF Output

Transceiver Optional High-Power PA

Output

VR_PA (RF)

VBAT1 (RF)

Power

Output

Transceiver regulated output voltage for

VR_PA use.

De-coupling cap

suggested.

Power Input Transceiver VDD for RF circuitry

Connect to system VDD

supply

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Table 1. Pin Function Description (Sheet 4 of 5)

Pin Name¹

VR_ANA (RF)

Type

Power

Description

Functionality

Transceiver regulated output voltage for

analog circuitry.

Decouple to ground with

100 nF capacitor

Output

VR_DIG (RF)

XTA (RF)

Power

Output

Transceiver regulated output voltage for

digital circuitry.

Decouple to ground with

100 nF capacitor

Xtal Osc

Transceiver crystal reference oscillator

Connect to 32 MHz

crystal and load capacitor

XTB (RF)

Xtal Osc

Transceiver crystal reference oscillator

Connect to 32 MHz

crystal and load capacitor

RESET (RF)

DIO0/PTE2/SPI1_SCK

Digital Input Transceiver hardware reset input

Typically driven from

MCU GPIO

Digital

Internally connected to Transceiver GPIO MCU IO and Transceiver

Input/Output bit 0 and MCU Port E bit 2 / SPI1 clock

IO connected in-package

DIO1/PTE3/SPI1_MISO/SPI1 Digital

_MOSI

Internally connected to Transceiver GPIO MCU IO and Transceiver

Input/Output bit 1 and MCU Port E bit 3 /SPI1 in or out IO connected in-package

DIO2

Digital

Input/Output

Transceiver GPIO Bit 2

Transceiver GPIO Bit 3

Transceiver GPIO Bit 4

Transceiver GPIO Bit 5 / ClkOut

DIO3

Digital

Input/Output

DIO4

Digital

Input/Output

DIO5/CLKOUT

Digital

Input/Output

Commonly programmed

as ClkOut to supply MCU

clock; connect to Pin 15

VDD

Power Input MCU VDD supply

Power Input MCU Analog supply

Connect to VDD supply

VDDAD

Connect to Analog

supply

MISO/PTC7/SPI0_MISO/SPI0 Digital

Internal SPI data connection from

• MCU IO and

Transceiver IO

connected in-package

• MCU IO must be

configured for this

connection

_MOSI

Input/Output Transceiver MISO bit 1 to MCU SPI0 (Port

C bit 7 )

NSS/PTD0/SPI0_PCS0

Digital

Internal SPI select connection between

• MCU IO and

Transceiver IO

connected in-package

• MCU IO must be

configured for this

connection

Input/Output Transceiver NSS and MCU SPI0 (Port D bit

SCK/PTC5/SPI0_SCK

Digital

Internal SPI clock connection between

• MCU IO and

Input/Output Transceiver SCK and MCU SPI0 (port C bit

Transceiver IO

connected in-package

• MCU IO must be

configured for this

connection

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Table 1. Pin Function Description (Sheet 5 of 5)

Type Description

Digital Internal SPI data connection to Transceiver • MCU IO and

Pin Name¹

Functionality

MOSI/PTC6/SPI0_MOSI/

SPI0_MISO

Input/Output MOSI bit 1 to MCU SPI0 (Port C bit 6 )

Transceiver IO

connected in-package

• MCU IO must be

configured for this

connection

FLAG VSS

Power input External package flag. Common VSS

Connect to ground.

Refer to ADD Table 1-3 for additional pin-out information on default and alternate setting selections.

5.2

Internal Functional Interconnects

The MCU provides control to the transceiver through the SPI Port and receives status from the transceiver

from the DIOx pins. Certain interconnects between the devices are routed on chip. In addition, the signals

are brought out to external pads.

Table 2. MKW01 Internal Functional Interconnects

Transceiver

MCU Signal

Description

Signal

49 DIO0/PTE2/SPI1_

SCK

DIO0

Transceiver DIO0 can be programmed to provide status to the MCU

50 DIO1/PTE3/SPI1_

MISO/SPI1_MOSI

DIO1

Transceiver DIO1 can be programmed to provide status to the MCU

SPI data from transceiver to MCU

SPI chip select

57 MISO/PTC7/SPI0_

MISO/SPI0_MOSI

MISO

58 NSS/PTD0/SPI0_

PCS0

NSS

SCK

MOSI

59 SCK/PTC5/SPI0_

SCK

SPI Clock

60 MOSI/PTC6/SPI0_

MOSI/SPI0_MISO

SPI data from MCU to transceiver

NOTE

•

As shown in Table 2, the MCU SPI Port pin selection must be

configured by software.

•

The transceiver DIO pins must be programmed to provide desired status.

Enhanced performance can be achieved by additionally routing some

DIO pins externally to other GPIO pins.

5.3

External Functional Interconnects

In addition to the in-package device interconnection, other external connections between the MCU and the

transceiver are common:

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

1. Freescale recommends driving/controlling the transceiver reset from an MCU GPIO - This allows

overriding control of the transceiver from the system application.

2. The other DIO2-DIO4 status and RXTX signals can prove useful for monitoring the transceiver

operation - the DIO2-DIO4 signals must be programmed to provide operational status. All signals

must be connected externally to appropriate MCU GPIO for this function.

6 System and Power Management

The MKW01 consists of an independent transceiver and MCU. The MCU controls the transceiver through

programming of the SPI Port, and sets its operational mode through this control channel. Total current

draw for the MKW01 is dependent on the operation mode of both devices where different modes allow for

different levels of power-down. Some additional features supported are:

•

Transceiver Sleep with MCU set at the lowest power state.

The transceiver mode selection being independent of the MCU’s mode selection.

The transceiver uses/powers-up the transmitter or receiver only as required.

MCU peripheral control clock gating being disabled on a module-by-module basis to provide

lowest power.

•

RTC can be used as wake-up timer.

LLWU (Low Leakage Wake-up Unit) available.

6.1

MCU Power Modes

The MCU has 9 different modes of operation to allow the user to optimize power consumption for the level

of functionality needed. Depending on the STOP requirements of the user application, a variety of STOP

modes are available that provide state retention, partial power down or full power down of certain logic

and/or memory. I/O states are held in all modes of operation. Table 3 outlines the various available power

modes of MCU operation.

For each RUN mode there is a corresponding WAIT and STOP mode. WAIT modes are similiar to ARM

sleep modes. STOP modes (VLPS, STOP) are similiar to ARM sleep deep mode. The very low power run

(VLPR) operating mode can greatly reduce runtime power when the maximum bus frequency is not

required to handle application needs. The 3 primary modes of operation are RUN, WAIT and STOP. The

WFI instruction invokes both WAIT and STOP modes for the MCU. The primary modes are augmented

in a number of ways to provide lower power based on application needs.

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Table 3. MCU power modes

Description

Normal

Recovery

Method

Chip Power

Mode

Core Mode

Normal run

Allows maximum performance of chip. Default mode out of reset;

onchip voltage regulator is on.

Run

—

Normal Wait - via Allows peripherals to function while the core is in sleep mode,

Sleep

Interrupt

WFI

reducing power. NVIC remains sensitive to interrupts;

peripherals continue to be clocked.

Normal Stop - via Places chip in static state. Lowest power mode that retains all

Sleep Deep

Run

Interrupt

WFI

registers while maintaining LVD protection. NVIC is disabled;

AWIC is used to wake up from interrupt; peripheral clocks are

stopped.

VLPR (Very Low On-chip voltage regulator is in a low power mode that supplies

—

Power Run)

only enough power to run the chip at a reduced frequency.

Reduced frequency Flash access mode (1 MHz); LVD off; in

BLPI clock mode, the fast internal reference oscillator is

available to provide a low power nominal 4 MHz source for the

core with the nominal bus and flash clock required to be <800

kHz; alternatively, BLPE clock mode can be used with an

external clock or the crystal oscillator providing the clock source.

VLPW (Very Low Same as VLPR but with the core in sleep mode to further reduce

Power Wait) -via power; NVIC remains sensitive to interrupts (FCLK = ON).

Sleep

Interrupt

WFI

On-chip voltage regulator is in a low power mode that supplies

only enough power to run the chip at a reduced frequency.

VLPS (Very Low Places chip in static state with LVD operation off. Lowest power

Power Stop)-via mode with ADC and pin interrupts functional. Peripheral clocks

Sleep Deep

WFI

are stopped, but OSC, LPTMR, RTC, CMP, TSI can be used.

TPM and UART can optionally be enabled if their clock source is

enabled. NVIC is disabled (FCLK = OFF); AWIC is used to wake

up from interrupt. On-chip voltage regulator is in a low power

mode that supplies only enough power to run the chip at a

reduced frequency. All SRAM is operating (content retained and

I/O states held).

LLS (Low

State retention power mode. Most peripherals are in state

Sleep Deep

Wakeup

Leakage Stop) retention mode (with clocks stopped), but OSC, LLWU, LPTMR,

RTC, CMP,, TSI can be used. NVIC is disabled; LLWU is used to

wake up.

Interrupt¹

NOTE: The LLWU interrupt must not be masked by the interrupt

controller to avoid a scenario where the system does not fully exit

stop mode on an LLS recovery.

All SRAM is operating (content retained and I/O states held).

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Table 3. MCU power modes

Description

Normal

Recovery

Method

Chip Power

Mode

Core Mode

VLLS3 (Very

Most peripherals are disabled (with clocks stopped), but OSC,

Sleep Deep

Wakeup

Reset²

Low Leakage LLWU, LPTMR, RTC, CMP, TSI can be used. NVIC is disabled;

Stop3)

LLWU is used to wake up.

SRAM_U and SRAM_L remain powered on (content retained

and I/O states held).

VLLS1 (Very

Most peripherals are disabled (with clocks stopped), but OSC,

Sleep Deep

Wakeup

Reset²

Low Leakage LLWU, LPTMR, RTC, CMP, TSI can be used. NVIC is disabled;

Stop1)

LLWU is used to wake up. All of SRAM_U and SRAM_L are

powered off.

VLLS0 (Very

Most peripherals are disabled (with clocks stopped), but LLWU,

Wakeup

Reset²

Low Leakage LPTMR, RTC, TSI can be used. NVIC is disabled; LLWU is used

Stop 0)

to wake up.

All of SRAM_U and SRAM_L are powered off.

LPO disabled, optional POR brown-out detection

Resumes normal run mode operation by executing the LLWU interrupt service routine.

Follows the reset flow with the LLWU interrupt flag set for the NVIC.

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

6.1.1

Power mode transitions

Figure 6 shows power mode transitions. Any reset always brings the MCU back to normal state run. In

RUN, WAIT and STOP modes active power regulation is enabled. The VLPx modes are limited in

frequency but offer a lower power operating power mode than normal modes. The LLS and VLLSx modes

are the lowest power stop modes based on the amount of logic or memory that is required to be reatined

by the application.

Figure 6. Power mode state transition diagram

6.2

Transceiver modes of operation.

The transceiver can be set in numerous modes of operation as described in Table 4. By default, when

switching from one mode to another various features are selectively turned on coordinated by a

pre-defined optimized sequence using the automatic sequencer. Alternatively, these operating modes can

be selected directly by disabling the automatic sequencer.

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Table 4. Basic Transceiver modes

Selected Mode

Enabled blocks

Sleep

Stand-by

Idle

None

Main regulator and crystal oscillator

Main regulator and RC oscillator

Frequency synthesizer

Transmit

Receive

Listen

Frequency synthesizer and transmitter

Frequency synthesizer and receiver

Periodical receive wake-up from Idle operation

An overview of the transceiver modes of operation is described below:

•

Sleep - provides lowest power consumption and is the full power down state.

Idle - provides very low standby power consumption and has the main voltage regulator and the

RC oscillator enabled.

•

Standby - similar to Idle with low standby power consumption but has the main voltage regulator

and the crystal oscillator enabled.

FS (Frequency synthesizer) - the frequency synthesizer is alive to shorten startup time to transmit

or receive states.

•

Transmit - transmitter is active.

Receive - receiver is active.

6.3

System Protection

The MKW01 provides numerous vehicles to maintain security or a high level of system robustness:

•

Standard COP Watchdog reset with option to run from dedicated 1 kHz internal clock source or bus

clock. The COP watchdog is intended to force a system reset when the application software fails

to execute as expected.

•

LVD protection with reset or interrupt; selectable trip points.

HardFault exception on attempts to execute undefined instructions or access to undefined memory

space.

•

LOCKUP reset resource from core.

Flash protection

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

7 Development Environment

Development support for the ARM® Cortex M0+ MCU on the MKW01 is configured to provide

maximum flexibility as allowed by the restrictions of the pinout and other available resources. One debug

interface is supported:

• Two-wire Serial Wire Debug (SWD) interface

Table 5 presents a brief description of the serial wire debug description.

NOTE

Electrical specifications for the SWD lines can be found in the appendix.

Table 5. Debug Components Description

Module

Type

Description

SWCLK

Input

Serial Wire Clock. This pin is the clock for debug logic when in the Serial Wire

Debug mode. This pin is pulled down internally.

SWDIO

Input /Output Serial Wire debug data input / output. The SWDIO pin is used by an external

debug tool for communication and devive control. This pin is pulled up internally.

8 System Electrical Specification

This section details maximum ratings for the 60-pin LGA package and recommended operating

conditions, DC characteristics, and AC characteristics for the modem, and the MCU.

8.1

LGA Package Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maximum rating is not

guaranteed. Stress beyond the limits specified in Table 6 may affect device reliability or cause permanent

damage to the device. For functional operating conditions, refer to the remaining tables in this section.

This device contains circuitry protecting against damage due to high static voltage or electrical fields;

however, it is advised that normal precautions be taken to avoid application of any voltages higher than

maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage level (for instance, either V or V ) or the programmable

pull-up resistor associated with the pin is enabled.

Table 6 shows the maximum ratings for the 60-pin LGA package.

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Table 6. LGA Package Maximum Ratings

Symbol

Rating

Maximum Junction Temperature

Value

Unit

T_J

T_stg

-55 to 115

-0.3 to 3.8

-0.3 to (V_DDINT+ 0.3)

C

Storage Temperature Range

Power Supply Voltage

Digital Input Voltage

RF Input Power

V_BATT, V_DDINT

Vin

Vdc

P_max

dBm

Note: Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the limits in the Electrical Characteristics

or Recommended Operating Conditions tables.

Note: Meets Human Body Model (HBM) = 2 kV. RF input/output pins have no ESD protection.

8.2

ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early

CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.

Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels

of static without suffering any permanent damage.

All ESD testing is in conformity with the JESD22 Stress Test Qualification for Commercial Grade

Integrated Circuits. During the device qualification ESD stresses were performed for the human body

model (HBM), the machine model (MM) and the charge device model (CDM).

All latchup testing is in conformity with the JESD78 IC Latch-Up Test.

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification.

Table 7. ESD and Latch-up Test Conditions

Model

Description

Series resistance

Symbol

Value

Unit

1500

100



Human

Body

Storage capacitance

Number of pulses per pin¹

Series resistance

—



Machine Storage capacitance

Number of pulses per pin¹

200

—

Minimum input voltage limit

Latch-up

– 1.8

4.32

Maximum input voltage limit

This number represents a minimum number for both positive pulse(s) and negative pulse(s)

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Table 8. ESD and Latch-Up Protection Characteristics

No.

Rating¹

Symbol

Min

Max

Unit

Human body model (HBM)

Machine model (MM)

V_HBM

V_MM

V_CDM

I_LAT

2000

200

500

100

—

Charge device model (CDM)

Latch-up current at T_A= 85C

Parameter is achieved by design characterization on a small sample size from typical devices

under typical conditions unless otherwise noted.

8.3

Transceiver Electrical Characteristics

The tables below give the electrical specifications of the transceiver under the following conditions:

Supply voltage VBAT1= VBAT2=VDD=3.3 V, temperature = 25 °C, FXOSC = 32 MHz, FRF = 915 MHz,

Pout = +13dBm, 2-level FSK modulation without pre-filtering, FDA = 5 kHz, Bit Rate = 4.8 kb/s and

terminated in a matched 50 Ohm impedance, unless otherwise specified.

NOTE

Unless otherwise specified, the performances in the other frequency bands

are similar or better.

8.3.1

Transceiver Recommended Operating Conditions

Table 9. Recommended Operating Conditions

Characteristic

Power Supply Voltage (V_BATT

Symbol

Min

Typ

Max

Unit

)

1.8

-40

3.6

Vdc

C

Operating Temperature Range

Logic Input Voltage Low

T_A

V_IL

20%

V_BATT

Logic Input Voltage High

V_IH

V_OL

V_OH

80%

V_BATT

Logic Output Voltage Low (I_max= -1 mA)

Logic Output Voltage High (I_max= 1 mA)

10%

V_BATT

90%

V_BATT

Load capacitance on digital ports

SPI Clock Rate

C_L

f_SPI

P_max

f_ref

8.0

MHz

dBm

RF Input Power

Crystal Reference Oscillator Frequency

32 MHz Only

(Some variants may use 30 MHz instead)

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

8.3.2

Transceiver Power Consumption

Table 10. Power Supply Current

Characteristic

Conditions

Symbol

Min

Typ

Max

Unit

Supply current in Sleep mode

Supply current in Idle mode

IDDSL

IDDIDLE

IDDST

IDDFS

IDDR

0.1

1.2

1.25

µA

RC oscillator enabled

Supply current in Standby mode

Supply current in Synthesizer mode

Supply current in Receive mode

Crystal oscillator enabled

1.5

4.8 kbps

500 kbps

Supply current in Transmit mode with RFOP = +17 dBm, on PA_BOOST

appropriate matching, RF power RFOP = +13 dBm, on RFIO pin

stable across VDD range, DC current RFOP = +10 dBm, on RFIO pin

varies with VDD, lower IDDT at lower RFOP = 0 dBm, on RFIO pin

VDD, typical numbers correspond to RFOP = -1 dBm, on RFIO pin

mid-range VDD, about 2.7 V

IDDT

8.3.3

Transceiver Frequency Synthesis

Table 11. Frequency Synthesizer Specification

Characteristic

Conditions

Symbol

Min

Typ

Max

Unit

Synthesizer Frequency Range

Programmable, 32 MHz clock

290

424

862

340

510

1020

MHz

Crystal oscillator frequency

FXOSC

TS_OSC

TS_FS

250

MHz

µs

Crystal oscillator wake-up time

500

150

Frequency synthesizer wake-up time From Standby mode

to PllLock signal

µs

Frequency synthesizer hop time at

most 10 kHz away from the target

200 kHz step TS_HOP

1 MHz step

5 MHz step

µs

7 MHz step

12 MHz step

20 MHz step

25 MHz step

Frequency synthesizer step

RC Oscillator frequency

Bit rate, FSK

FSTEP = FXOSC/2¹⁹

After calibration

Programmable

FSTEP

FRC

61.0

62.5

kHz

kbps

BRF

1.2

0.6

600

Bit rate, OOK

Programmable

BRO

FDA

32.768 kbps

300 kHz

Frequency deviation, FSK

Programmable

FDA + BRF/2 =< 500 kHz

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

8.3.4

Receiver

All receiver tests are performed with RxBw = 10 kHz (Single Side Bandwidth) as programmed in

RegRxBw, receiving a PN15 sequence with a BER of 0.1% (Bit Synchronizer is enabled), unless otherwise

specified. The LNA impedance is set to 200 Ohms, by setting bit LnaZin in RegLna to 1. Blocking tests

are performed with an unmodulated interferer. The wanted signal power for the Blocking Immunity, ACR,

IIP2, IIP3 and AMR tests is set 3 dB above the nominal sensitivity level.

Table 12. Receiver Specification

Characteristic

Conditions

Symbol

Min

Typ

Max

Unit

FSK sensitivity, highest LNA gain

FDA = 5 kHz, BR = 1.2 kb/s

FDA = 5 kHz, BR = 4.8 kb/s

FDA = 40 kHz, BR = 38.4 kb/s

RFS_F

-118

-114

-105

dBm

FDA = 5 kHz, BR = 1.2 kb/s ¹

BR = 4.8 kb/s

-120

-112

-10

-109

dBm

OOK sensitivity, highest LNA gain

Co-Channel Rejection

RFS_O

CCR

-13

Adjacent Channel Rejection

Offset = +/- 25 kHz

Offset = +/- 50 kHz

ACR

Blocking Immunity

Offset = +/- 1 MHz

Offset = +/- 2 MHz

Offset = +/- 10 MHz

Blocking Immunity

Wanted signal at sensitivity +16dB

Offset = +/- 1 MHz

Offset = +/- 2 MHz

Offset = +/- 10 MHz

AM Rejection , AM modulated

interferer with 100% modulation

depth, fm = 1 kHz, square

Offset = +/- 1 MHz

Offset = +/- 2 MHz

Offset = +/- 10 MHz

AMR

IIP2

2nd order Input Intercept Point

Unwanted tones are 20 MHz above

the LO

Lowest LNA gain

Highest LNA gain

+75

+35

dBm

3rd order Input Intercept point

Unwanted tones are 1MHz and 1.995

MHz above the LO

Lowest LNA gain

Highest LNA gain

IIP3

+20

-18

dBm

-23

Single Side channel filter BW

Image rejection in OOK mode

Programmable

BW_SSB

2.6

500

kHz

Wanted signal level = -106 dBm

IMR_

OOK

Receiver wake-up time, from PLL

locked state to RxReady

RxBw = 10 kHz, BR = 4.8 kb/s

RxBw = 200 kHz, BR = 100 kb/s

TS_RE

1.7

µs

Receiver wake-up time, from PLL

locked state, AGC enabled

RxBw= 10 kHz, BR = 4.8 kb/s

RxBw = 200 kHz, BR = 100 kb/s

TS_RE_

AGC

3.0

163

µs

Receiver wake-up time, from PLL lock RxBw= 10 kHz, BR = 4.8 kb/s

TS_RE_

AGC&AFC

4.8

265

µs

state, AGC and AFC enabled

RxBw = 200 kHz, BR = 100 kb/s

FEI sampling time

Receiver is ready

TS_FEI

4.T

bit

AFC Response Time

Receiver is ready

TS_AFC

4.T

bit

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Table 12. Receiver Specification

Conditions Symbol

Characteristic

Min

Typ

Max

Unit

RSSI Response Time

RSSI Dynamic Range

Receiver is ready

AGC enabled

TS_RSSI

2.T

bit

Min DR_RSSI

Max

-115

dBm

Set SensitivityBoost in RegTestLna to 0x2D to reduce the noise floor in the receiver

8.3.5

Transmitter

Table 13. Transmitter Specidication

Characteristic

Conditions

Symbol

Min

Typ

Max

Unit

RF output power in 50 ohms

On RFIO pin

Programmable with 1dB steps

Max

Min

RF_OP

+13

-18

dBm

Max RF output power, on PA_BOOST With external match to 50 ohms

RF_OPH

RF_OP

PHN

+17

dBm

RF output power stability

Transmitter Phase Noise

From VDD=1.8V to 3.6V

50 kHz Offset from carrier

+/-0.3

868 / 915 MHz bands

434 / 315 MHz bands

-95

-99

dBc/Hz

dBm

µs

Transmitter adjacent channel power BT=0.5 . Measurement conditions

(measured at 25 kHz offset) as defined by EN 300 220-1 V2.1.1

ACP

-37

Transmitter wake up time, to the first Frequency Synthesizer enabled,

rising edge of DCLK PaRamp = 10 µs, BR = 4.8 kb/s.

TS_TR

120

9 Typical Applications Circuit

Figure 7 shows a MKW01 typical applications circuit with and without use of an external power amplifier

(PA) (driven by the RF power boost feature). Note a number of circuit features:

1. The two metal flags on the package bottom are independent (unconnected), and as a result, both

must be connected to ground.

2. The topology of the external RF matching components is consistent across various frequency

bandwidths. Only the component values differ as determined by the desired frequency range.

3. Freescale recommends using a single crystal design (as shown) to minimize systems costs - the

circuit must connect transceiver signal DIO5/CLKOUT to the MCU EXTAL input to supply the

MCU with a crystal accurate clock source. Also, the MCU initialization must enable the DIO5 pin

as the ClkOut function.

Freescale also recommends that the transceiver RESET is driven by an MCU GPIO to provide total hard-

ware control of the transceiver. Figure 7 shows GPIO PTE30 (preferred), but any GPIO can be used.

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

4. The MKW01Z128 provides in-package connection for the DIO1-DIO0 status to the MCU.

External connection of DIO4-DIO2 status to MCU GPIO may be useful or required to implement

a wireless node communication algorithm. Enhanced performance can be achieved by routing

DIO1 and DIO0 externally to GPIO pins PTC4 and PTC3.

5. The transceiver reference oscillator uses the specified 32 MHz crystal (pins XTA and XTB).

6. A debug port connector will beprovided for programming the MKW01 MCU FLASH and

debugging code via the SWD interface.

Two common RF wiring options are shown in Figure 7:

1. Bi-directional single port operation - this mode uses the bi-directional RF port pin of the MKW01

designated as RFIO. The device transmits and receives through this single port.

— Typical +13 dBm TX output power

— An inductor acts to provide DC power to the transmitter’s output amplifier while also acting as

an AC signal block.

— A circuit topology consisting of inductors and capacitors will provide:

– Impedance matching between the RFIO port and the antenna

– Low pass filtering for the transmit output path — when fully populated can implement an

elliptic-function low pass filter.

NOTE

•

The topology for the RF matching network can be used over the various

bands of interest with changes in component values

•

Not all indicated components are used at all frequencies

Refer to MKW01Z128 Sub 1 GHz Low Power Transceiver plus

Microcontroller Reference Manual (MKW01Z128RM.pdf) for

additional information

2. Dual port operation with external amplification - this mode uses the RFIO port pin of the

MKW01Z128 typically as the RX input and the auxiliary port PA_BOOST as the TX output. An

external PA can optionally be inserted into the transmit path and an external antenna switch is also

required.

— The PA_BOOST has typical +17 dBm output power - this is +4 dBm higher than the RFIO and

helps achieve higher power at the PA output.

— The PA_BOOST transmit path has a similar filter matching network discussed in the

single-port to do low pass filtering and impedance match. The above note about components

values also applies.

— With separate transmit and receive paths, an antenna switch is required - the RXTX signal or

another programmed GPIO can be used to switch paths depending on radio operation.

— The receive side matching network can be simplified as no PA DC bias, low pass filtering or

harmonic trap is required as is in the transmit and single port networks. When implemented on

a new board design, both transmit and receive path component values and even topology

should be optimized for best performance on the most important parameters for the application.

1. Or 30 MHz, in some cases.

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

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10 Mechanical Drawings

Figure 8. Mechanical Drawing (1 of 2)

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Figure 9. Mechanical Drawing (2 of 2)

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

MKW01 MCU Section Data Sheet

Appendix A MKW01 MCU Section Data Sheet

MKW01Z128 Datasheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Document Number MKW01Z128

Rev. 6, 04/2016

Freescale Semiconductor

Data Sheet: Technical Data

MKW01Z128

MKW01 MCU Section Data

Sheet

Supports the following: MKW01Z128

Key features

• Security and integrity modules

– 80-bit unique identification (ID) number per chip

• Operating Characteristics

– Voltage range: 1.8 to 3.6 V

• Human-machine interface

– Flash write voltage range: 1.8 to 3.6 V

– Temperature range (ambient): -40 to 85°C

– Low-power hardware touch sensor interface (TSI)

– General-purpose input/output

• Performance

• Analog modules

– Up to 48 MHz ARM® Cortex-M0+ core

– 16-bit SAR ADC

– 12-bit DAC

– Analog comparator (CMP) containing a 6-bit DAC

and programmable reference input

• Memories and memory interfaces

– 128 KB program flash memory

– 16 KB RAM

• Timers

• Clocks

– Six channel Timer/PWM (TPM)

– Two 2-channel Timer/PWM (TPM)

– Periodic interrupt timers

– 16-bit low-power timer (LPTMR)

– Real-time clock

– 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal

oscillator

– Multi-purpose clock source

• System peripherals

– Nine low-power modes to provide power

optimization based on application requirements

– 4-channel DMA controller, supporting up to 63

request sources

– COP Software watchdog

– Low-leakage wakeup unit

• Communication interfaces

– One 16-bit serial peripheral communcation (SPI)

module available externally

– Two I2C modules

– One low power UART module

– Two UART modules

– SWD interface and Micro Trace buffer

– Bit Manipulation Engine (BME)

Table of Contents

1 General................................................................................................. 3

2.3.1 MCG specifications........................................................15

2.3.2 Oscillator electrical specifications................................. 17

2.4 Memories and memory interfaces................................................19

2.4.1 Flash electrical specifications........................................ 19

2.5 Security and integrity modules.................................................... 21

2.6 Analog..........................................................................................21

2.6.1 ADC electrical specifications.........................................21

2.6.2 CMP and 6-bit DAC electrical specifications................25

2.6.3 12-bit DAC electrical characteristics............................. 27

2.7 Timers.......................................................................................... 30

2.8 Communication interfaces........................................................... 30

2.8.1 SPI switching specifications.......................................... 30

2.8.2 Inter-Integrated Circuit Interface (I2C) timing.............. 34

2.8.3 UART.............................................................................35

2.9 Human-machine interfaces (HMI)...............................................36

2.9.1 TSI electrical specifications........................................... 36

3 Revision History...................................................................................36

1.1 Voltage and current operating requirements................................3

1.2 LVD and POR operating requirements........................................3

1.3 Voltage and current operating behaviors.....................................4

1.4 Power mode transition operating behaviors.................................5

1.5 Power consumption operating behaviors.....................................6

1.5.1 Diagram: Typical IDD_RUN operating behavior..........10

1.6 Designing with radiated emissions in mind.................................12

1.7 Capacitance attributes..................................................................12

1.8 Switching specifications.............................................................. 13

1.8.1 Device clock specifications............................................13

1.8.2 General switching specifications....................................13

2 Peripheral operating requirements and behaviors................................ 14

2.1 Core modules............................................................................... 14

2.1.1 SWD electricals .............................................................14

2.2 System modules........................................................................... 15

2.3 Clock modules............................................................................. 15

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

General

1 General

1.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

Symbol

V_DD

Description

Min.

1.8

Max.

3.6

Unit

Notes

Supply voltage

V_DDA

Analog supply voltage

1.8

3.6

V_DD– V_DDAV_DD-to-V_DDAdifferential voltage

V_SS– V_SSAV_SS-to-V_SSAdifferential voltage

–0.1

0.1

V_IH

Input high voltage

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

0.7 × V_DD

—

0.75 × V_DD

V_IL

Input low voltage

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

—

0.35 × V_DD

0.3 × V_DD

V_HYS

I_ICIO

Input hysteresis

0.06 × V_DD

-3

—

IO pin negative DC injection current — single pin

• V_IN< V_SS-0.3V

I_ICcont

Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents of 16

contiguous pins

-25

—

• Negative current injection

V_ODPU

V_RAM

Open drain pullup voltage level

V_DD

1.2

V_DD

—

V_DDvoltage required to retain RAM

1. All I/O pins are internally clamped to V_SSthrough a ESD protection diode. There is no diode connection to V_DD. If V_IN

greater than V_{IO_MIN}(= V_SS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this

limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is

calculated as R = (V_{IO_MIN}- V_IN)/|I_ICIO|.

2. Open drain outputs must be pulled to V_DD

1.2 LVD and POR operating requirements

Table 2. V_DDsupply LVD and POR operating requirements

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_POR

Falling V_DDPOR detect voltage

0.8

1.1

1.5

—

Table continues on the next page...

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

General

Table 2. V_DDsupply LVD and POR operating requirements (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_LVDH

Falling low-voltage detect threshold — high

range (LVDV = 01)

2.48

2.56

2.64

—

Low-voltage warning thresholds — high range

• Level 1 falling (LVWV = 00)

V_LVW1H

V_LVW2H

V_LVW3H

V_LVW4H

2.62

2.72

2.82

2.92

—

2.70

2.80

2.90

3.00

2.78

2.88

2.98

3.08

—

• Level 2 falling (LVWV = 01)

• Level 3 falling (LVWV = 10)

• Level 4 falling (LVWV = 11)

V_HYSH

V_LVDL

Low-voltage inhibit reset/recover hysteresis —

high range

—

Falling low-voltage detect threshold — low range

(LVDV=00)

1.54

1.60

1.66

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV = 00)

V_LVW1L

V_LVW2L

V_LVW3L

V_LVW4L

1.74

1.84

1.94

2.04

—

1.80

1.90

2.00

2.10

1.86

1.96

2.06

2.16

—

• Level 2 falling (LVWV = 01)

• Level 3 falling (LVWV = 10)

• Level 4 falling (LVWV = 11)

V_HYSL

Low-voltage inhibit reset/recover hysteresis —

low range

—

V_BG

t_LPO

Bandgap voltage reference

0.97

900

1.00

1.03

—

Internal low power oscillator period — factory

trimmed

1000

1100

μs

1. Rising thresholds are falling threshold + hysteresis voltage

1.3 Voltage and current operating behaviors

Table 3. Voltage and current operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

V_OH

Output high voltage — Normal drive pad (except

RESET_b)

1, 2

V_DD– 0.5

—

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= -5 mA

• 1.8 V ≤ V_DD≤ 2.7 V, I_OH= -2.5 mA

V_OH

Output high voltage — High drive pad (except

RESET_b)

1, 2

V_DD– 0.5

—

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= -20 mA

• 1.8 V ≤ V_DD≤ 2.7 V, I_OH= -10 mA

I_OHT

V_OL

Output high current total for all ports

Output low voltage — Normal drive pad

—

100

Table continues on the next page...

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

General

Notes

Table 3. Voltage and current operating behaviors (continued)

Symbol

Description

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 5 mA

Min.

Max.

Unit

—

0.5

• 1.8 V ≤ V_DD≤ 2.7 V, I_OL= 2.5 mA

—

0.5

V_OL

Output low voltage — High drive pad

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 20 mA

• 1.8 V ≤ V_DD≤ 2.7 V, I_OL= 10 mA

—

0.5

I_OLT

I_IN

Output low current total for all ports

—

100

μA

Input leakage current (per pin) for full temperature

range

I_IN

Input leakage current (per pin) at 25 °C

—

0.025

μA

Input leakage current (total all pins) for full temperature

range

I_OZ

Hi-Z (off-state) leakage current (per pin)

Internal pullup and pulldown resistors

—

μA

kΩ

R_PU

1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated

PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When

configured as a GPIO output, it acts as a pseudo open drain output.

3. Measured at V_DD= 3.6 V

4. Measured at V_DDsupply voltage = V_DDmin and Vinput = V_SS

1.4 Power mode transition operating behaviors

All specifications except t_PORand VLLSx→RUN recovery times in the following table

assume this clock configuration:

• CPU and system clocks = 48 MHz

• Bus and flash clock = 24 MHz

• FEI clock mode

POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system

frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.

Table 4. Power mode transition operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

t_POR

After a POR event, amount of time from the point

—

300

μs

V_DDreaches 1.8 V to execution of the first

instruction across the operating temperature

range of the chip.

• VLLS0 → RUN

—

106

120

μs

Table continues on the next page...

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

General

Table 4. Power mode transition operating behaviors (continued)

Symbol Description

Min.

Typ.

105

Max.

117

Unit

Notes

• VLLS1 → RUN

—

μs

• VLLS3 → RUN

• LLS → RUN

—

μs

—

4.5

5.0

μs

• VLPS → RUN

• STOP → RUN

—

μs

—

μs

1. Normal boot (FTFA_FOPT[LPBOOT]=11).

1.5 Power consumption operating behaviors

Table 5. Power consumption operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_DDA

Analog supply current

—

See note

I_{DD_RUNCO_}Run mode current in compute operation - 48

MHz core / 24 MHz flash / bus disabled, LPTMR

running using 4 MHz internal reference clock,

CoreMark benchmark code executing from flash

—

6.1

—

• at 3.0 V

I_{DD_RUNCO}Run mode current in compute operation - 48

MHz core / 24 MHz flash / bus clock disabled,

code of while(1) loop executing from flash

—

3.8

4.6

5.9

6.1

• at 3.0 V

I_{DD_RUN}Run mode current - 48 MHz core / 24 MHz bus

and flash, all peripheral clocks disabled, code of

while(1) loop executing from flash

• at 3.0 V

I_{DD_RUN}Run mode current - 48 MHz core / 24 MHz bus

and flash, all peripheral clocks enabled, code of

while(1) loop executing from flash

3, 4

• at 3.0 V

• at 25 °C

• at 70 °C

• at 125 °C

—

6.0

6.2

6.3

6.5

6.8

7.1

Table continues on the next page...

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

General

Table 5. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_WAIT}Wait mode current - core disabled / 48 MHz

system / 24 MHz bus / flash disabled (flash doze

enabled), all peripheral clocks disabled

• at 3.0 V

—

2.7

5.7

I_{DD_WAIT}Wait mode current - core disabled / 24 MHz

system / 24 MHz bus / flash disabled (flash doze

enabled), all peripheral clocks disabled

• at 3.0 V

—

2.1

2.2

732

5.5

4.1

—

μA

I_{DD_PSTOP2}Stop mode current with partial stop 2 clocking

option - core and system disabled / 10.5 MHz

bus

• at 3.0 V

I_{DD_VLPRCO}Very-low-power run mode current in compute

operation - 4 MHz core / 0.8 MHz flash / bus

clock disabled, LPTMR running with 4 MHz

internal reference clock, CoreMark benchmark

code executing from flash

_CM

• at 3.0 V

I_{DD_VLPRCO}Very-low-power run mode current in compute

operation - 4 MHz core / 0.8 MHz flash / bus

clock disabled, code of while(1) loop executing

from flash

—

161

185

367

372

μA

• at 3.0 V

I_{DD_VLPR}Very-low-power run mode current - 4 MHz core /

0.8 MHz bus and flash, all peripheral clocks

disabled, code of while(1) loop executing from

flash

• at 3.0 V

I_{DD_VLPR}Very-low-power run mode current - 4 MHz core /

4, 6

—

256

110

420

355

μA

0.8 MHz bus and flash, all peripheral clocks

enabled, code of while(1) loop executing from

flash

• at 3.0 V

I_{DD_VLPW}Very-low-power wait mode current - core

disabled / 4 MHz system / 0.8 MHz bus / flash

disabled (flash doze enabled), all peripheral

clocks disabled

• at 3.0 V

I_{DD_STOP}Stop mode current at 3.0 V

at 25 °C

—

301

311

342

382

428

722

758

809

at 50 °C

μA

at 70 °C

at 85 °C

I_{DD_VLPS}Very-low-power stop mode current at 3.0 V

at 25 °C

—

2.3

8.4

Table continues on the next page...

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

General

Table 5. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

at 50 °C

—

5.2

18.3

μA

at 70 °C

—

10.5

19.3

26.1

58.5

at 85 °C

I_{DD_LLS}Low-leakage stop mode current at 3.0 V

μA

at 25 °C

—

1.7

3.2

3.3

at 50 °C

34.9

38.5

43.8

at 70 °C

5.8

at 85 °C

11.6

I_{DD_VLLS3}Very-low-leakage stop mode 3 current at 3.0 V

at 25 °C

—

1.3

2.3

4.7

8.5

3.0

at 50 °C

17.6

19.5

24.1

at 70 °C

at 85 °C

I_{DD_VLLS1}Very-low-leakage stop mode 1 current at 3.0V

at 25°C

at 50°C

at 70°C

at 85°C

—

0.7

1.2

2.2

4.8

1.3

11.7

12.6

15.3

μA

I_{DD_VLLS0}Very-low-leakage stop mode 0 current

(SMC_STOPCTRL[PORPO] = 0) at 3.0 V

at 25 °C

at 50 °C

at 70 °C

at 85 °C

—

310

778

844

3861

1928

3906

13055

15457

I_{DD_VLLS0}Very-low-leakage stop mode 0 current

(SMC_STOPCTRL[PORPO] = 1) at 3.0 V

at 25 °C

at 50 °C

at 70 °C

at 85 °C

—

139

600

747

3418

1674

3554

11143

13683

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

2. MCG configured for PEE mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized for

balanced.

3. MCG configured for FEI mode.

4. Incremental current consumption from peripheral activity is not included.

5. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized for

balanced.

6. MCG configured for BLPI mode.

7. No brownout

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

General

Table 6. Low power mode peripheral adders — typical value

Symbol

Description

Temperature (°C)

Unit

-40

I_IREFSTEN4MHz

4 MHz internal reference clock (IRC) adder.

Measured by entering STOP or VLPS mode

with 4 MHz IRC enabled.

µA

I_{IREFSTEN32KHz}

I_EREFSTEN4MHz

I_{EREFSTEN32KHz}

32 kHz internal reference clock (IRC)

adder. Measured by entering STOP mode

with the 32 kHz IRC enabled.

µA

External 4 MHz crystal clock adder.

Measured by entering STOP or VLPS mode

with the crystal enabled.

250

262

266

268

272

External 32 kHz crystal clock adder by

means of the OSC0_CR[ERCLKEN and

EREFSTEN] bits. Measured by entering all

modes with the crystal enabled.

440

490

510

490

560

540

560

570

610

VLLS1

VLLS3

LLS

VLPS

STOP

I_CMP

CMP peripheral adder measured by placing

the device in VLLS1 mode with CMP

enabled using the 6-bit DAC and a single

external input for compare. Includes 6-bit

DAC power consumption.

µA

I_RTC

RTC peripheral adder measured by placing

the device in VLLS1 mode with external 32

kHz crystal enabled by means of the

432

357

388

475

532

RTC_CR[OSCE] bit and the RTC ALARM

set for 1 minute. Includes ERCLK32K (32

kHz external crystal) power consumption.

I_UART

UART peripheral adder measured by

placing the device in STOP or VLPS mode

with selected clock source waiting for RX

data at 115200 baud rate. Includes selected

clock source power consumption.

MCGIRCLK (4 MHz internal reference

clock)

µA

259

271

275

277

281

OSCERCLK (4 MHz external crystal)

I_TPM

TPM peripheral adder measured by placing

the device in STOP or VLPS mode with

selected clock source configured for output

compare generating 100 Hz clock signal.

No load is placed on the I/O generating the

clock signal. Includes selected clock source

and I/O switching currents.

µA

MCGIRCLK (4 MHz internal reference

clock)

Table continues on the next page...

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

General

Table 6. Low power mode peripheral adders — typical value (continued)

Symbol

Description

Temperature (°C)

Unit

-40

OSCERCLK (4 MHz external crystal)

275

288

290

295

300

I_BG

Bandgap adder when BGEN bit is set and

device is placed in VLPx, LLS, or VLLSx

mode.

µA

I_ADC

ADC peripheral adder combining the

measured values at V_DDand V_DDAby

placing the device in STOP or VLPS mode.

ADC is configured for low-power mode

using the internal clock and continuous

conversions.

366

1.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFA

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

General

Run Mode Current VS Core Frequency

Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE

7.00E-03

6.00E-03

5.00E-03

4.00E-03

3.00E-03

2.00E-03

1.00E-03

000.00E+00

All Peripheral CLK Gates

All Off

All On

CLK Ratio

'1-1

'1-2

Flash-Core

Core Freq (MHz)

Figure 1. Run mode supply current vs. core frequency

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

General

VLPR Mode Current Vs Core Frequency

Temperature = 25, V_DD= 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE

400.00E-06

350.00E-06

300.00E-06

250.00E-06

200.00E-06

150.00E-06

100.00E-06

50.00E-06

All Peripheral CLK Gates

All Off

All On

000.00E+00

CLK Ratio

Flash-Core

'1-1

'1-2

'1-4

Core Freq (MHz)

Figure 2. VLPR mode current vs. core frequency

1.6 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.freescale.com.

2. Perform a keyword search for “EMC design.”

1.7 Capacitance attributes

Table 7. Capacitance attributes

Symbol

Description

Min.

Max.

Unit

C_IN

Input capacitance

—

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

General

1.8 Switching specifications

1.8.1 Device clock specifications

Table 8. Device clock specifications

Symbol

Description

Min.

Max.

Unit

Normal run mode

f_SYS

f_BUS

f_FLASH

f_LPTMR

System and core clock

Bus clock

—

MHz

Flash clock

LPTMR clock

VLPR and VLPS modes¹

f_SYS

f_BUS

System and core clock

Bus clock

—

MHz

f_FLASH

f_LPTMR

f_ERCLK

Flash clock

LPTMR clock²

External reference clock

f_{LPTMR_ERCLK}LPTMR external reference clock

f_{osc_hi_2}

Oscillator crystal or resonator frequency — high frequency

mode (high range) (MCG_C2[RANGE]=1x)

f_TPM

TPM asynchronous clock

—

MHz

f_UART0

UART0 asynchronous clock

1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing

specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN or

from VLPR.

2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

1.8.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO and UART

signals.

Table 9. General switching specifications

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter disabled) —

Synchronous path

1.5

—

Bus clock

cycles

External RESET and NMI pin interrupt pulse width —

Asynchronous path

100

—

GPIO pin interrupt pulse width — Asynchronous path

Port rise and fall time

—

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

1. The greater synchronous and asynchronous timing must be met.

2. This is the shortest pulse that is guaranteed to be recognized.

3. 75 pF load

2 Peripheral operating requirements and behaviors

2.1 Core modules

2.1.1 SWD electricals

Table 10. SWD full voltage range electricals

Symbol

Description

Min.

Max.

Unit

Operating voltage

1.8

3.6

SWD_CLK frequency of operation

• Serial wire debug

—

MHz

SWD_CLK cycle period

SWD_CLK clock pulse width

• Serial wire debug

1/J1

—

SWD_CLK rise and fall times

—

SWD_DIO input data setup time to SWD_CLK rise

SWD_DIO input data hold time after SWD_CLK rise

SWD_CLK high to SWD_DIO data valid

SWD_CLK high to SWD_DIO high-Z

—

J10

J11

J12

—

SWD_CLK (input)

Figure 3. Serial wire clock input timing

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

SWD_CLK

SWD_DIO

J10

Input data valid

J11

Output data valid

J12

J11

Output data valid

Figure 4. Serial wire data timing

2.2 System modules

There are no specifications necessary for the device's system modules.

2.3 Clock modules

2.3.1 MCG specifications

Table 11. MCG specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

f_{ints_ft}Internal reference frequency (slow clock) —

—

32.768

—

kHz

factory trimmed at nominal V_DDand 25 °C

f_{ints_t}

Internal reference frequency (slow clock) — user

trimmed

31.25

—

39.0625

0.6

kHz

Δ_{fdco_res_t}Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using C3[SCTRIM] and C4[SCFTRIM]

0.3

%f_dco

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over voltage and temperature

—

+0.5/-0.7

%f_dco

1, 2

Table continues on the next page...

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 11. MCG specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over fixed voltage and temperature

range of 0–70 °C

—

0.4

1.5

%f_dco

1, 2

f_{intf_ft}

Internal reference frequency (fast clock) —

factory trimmed at nominal V_DDand 25 °C

—

MHz

Δf_{intf_ft}

Frequency deviation of internal reference clock

(fast clock) over temperature and voltage —

factory trimmed at nominal V_DDand 25 °C

+1/-2

%f_{intf_ft}

f_{intf_t}

Internal reference frequency (fast clock) — user

trimmed at nominal V_DDand 25 °C

—

MHz

kHz

f_{loc_low}

f_{loc_high}

Loss of external clock minimum frequency —

RANGE = 00

(3/5) x

f_{ints_t}

—

Loss of external clock minimum frequency —

RANGE = 01, 10, or 11

(16/5) x

f_{ints_t}

FLL

f_{fll_ref}

f_dco

FLL reference frequency range

31.25

—

39.0625

kHz

DCO output

frequency range

Low range (DRS = 00)

640 × f_{fll_ref}

20.97

MHz

3, 4

5, 6

Mid range (DRS = 01)

1280 × f_{fll_ref}

—

41.94

23.99

47.97

180

—

MHz

f_{dco_t_DMX32}DCO output

frequency

Low range (DRS = 00)

732 × f_{fll_ref}

Mid range (DRS = 01)

1464 × f_{fll_ref}

J_{cyc_fll}

FLL period jitter

• f_VCO= 48 MHz

t_{fll_acquire}FLL target frequency acquisition time

—

PLL

f_vco

I_pll

VCO operating frequency

PLL operating current

48.0

—

100

—

MHz

µA

1060

• PLL at 96 MHz (f_{osc_hi_1}= 8 MHz, f_{pll_ref}= 2

MHz, VDIV multiplier = 48)

I_pll

PLL operating current

—

600

—

µA

• PLL at 48 MHz (f_{osc_hi_1}= 8 MHz, f_{pll_ref}= 2

MHz, VDIV multiplier = 24)

f_{pll_ref}

PLL reference frequency range

PLL period jitter (RMS)

• f_vco= 48 MHz

2.0

4.0

MHz

J_{cyc_pll}

—

120

—

• f_vco= 100 MHz

J_{acc_pll}

PLL accumulated jitter over 1µs (RMS)

• f_vco= 48 MHz

—

1350

600

—

• f_vco= 100 MHz

Table continues on the next page...

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 11. MCG specifications (continued)

Symbol Description

Min.

1.49

4.47

—

Typ.

—

Max.

2.98

5.97

Unit

Notes

D_lock

D_unl

Lock entry frequency tolerance

Lock exit frequency tolerance

Lock detector detection time

—

t_{pll_lock}

—

150 × 10^-6

+ 1075(1/

f_{pll_ref}

)

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

mode).

2. The deviation is relative to the factory trimmed frequency at nominal V_DDand 25 °C, f_{ints_ft}

3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.

4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation

(Δf_{dco_t}) over voltage and temperature must be considered.

5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.

6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

7. This specification is based on standard deviation (RMS) of period or frequency.

8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

9. Excludes any oscillator currents that are also consuming power while PLL is in operation.

10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of

each PCB and results will vary.

11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled

(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes

it is already running.

2.3.2 Oscillator electrical specifications

2.3.2.1 Oscillator DC electrical specifications

Table 12. Oscillator DC electrical specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_DD

Supply voltage

1.8

—

3.6

I_DDOSC

Supply current — low-power mode (HGO=0)

• 32 kHz

—

500

200

300

950

1.2

—

μA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

• 24 MHz

• 32 MHz

1.5

I_DDOSC

Supply current — high gain mode (HGO=1)

• 32 kHz

• 4 MHz

—

μA

400

Table continues on the next page...

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 12. Oscillator DC electrical specifications (continued)

Symbol Description

• 8 MHz (RANGE=01)

Min.

Typ.

Max.

Unit

Notes

—

500

—

μA

• 16 MHz

• 24 MHz

• 32 MHz

—

2.5

—

C_x

C_y

R_F

EXTAL load capacitance

XTAL load capacitance

—

2, 3

2, 4

Feedback resistor — low-frequency, low-power

mode (HGO=0)

MΩ

kΩ

Feedback resistor — low-frequency, high-gain

mode (HGO=1)

—

Feedback resistor — high-frequency, low-power

mode (HGO=0)

Feedback resistor — high-frequency, high-gain

mode (HGO=1)

R_S

Series resistor — low-frequency, low-power

mode (HGO=0)

—

Series resistor — low-frequency, high-gain mode

(HGO=1)

200

—

kΩ

Series resistor — high-frequency, low-power

mode (HGO=0)

kΩ

Series resistor — high-frequency, high-gain

mode (HGO=1)

—

kΩ

V_pp

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, low-power mode

(HGO=0)

0.6

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, high-gain mode

(HGO=1)

—

V_DD

0.6

—

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, low-power mode

(HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, high-gain mode

(HGO=1)

V_DD

1. V_DD=3.3 V, Temperature =25 °C

2. See crystal or resonator manufacturer's recommendation

3. C_x,C_ycan be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all

other cases external capacitors must be used.

4. When low power mode is selected, R_Fis integrated and must not be attached externally.

5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any

other devices.

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

2.3.2.2 Oscillator frequency specifications

Table 13. Oscillator frequency specifications

Symbol Description

f_{osc_lo}Oscillator crystal or resonator frequency — low-

frequency mode (MCG_C2[RANGE]=00)

Min.

Typ.

Max.

Unit

Notes

—

kHz

f_{osc_hi_1}Oscillator crystal or resonator frequency — high-

frequency mode (low range)

—

MHz

(MCG_C2[RANGE]=01)

f_{osc_hi_2}Oscillator crystal or resonator frequency — high

frequency mode (high range)

(MCG_C2[RANGE]=1x)

f_{ec_extal}

t_{dc_extal}

t_cst

Input clock frequency (external clock mode)

Input clock duty cycle (external clock mode)

—

MHz

1, 2

3, 4

Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0)

750

Crystal startup time — 32 kHz low-frequency,

high-gain mode (HGO=1)

—

250

0.6

—

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), low-power mode

(HGO=0)

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), high-gain mode

(HGO=1)

—

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.

2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

3. Proper PC board layout procedures must be followed to achieve specifications.

4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register

being set.

2.4 Memories and memory interfaces

2.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

2.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps are

active and do not include command overhead.

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 14. NVM program/erase timing specifications

Symbol Description

Min.

—

Typ.

7.5

Max.

Unit

μs

Notes

t_hvpgm4

Longword Program high-voltage time

—

t_hversscrSector Erase high-voltage time

—

113

452

t_hversall

Erase All high-voltage time

—

1. Maximum time based on expectations at cycling end-of-life.

2.4.1.2 Flash timing specifications — commands

Table 15. Flash command timing specifications

Symbol Description

Min.

—

Typ.

—

Max.

Unit

μs

Notes

t_rd1sec1kRead 1s Section execution time (flash sector)

t_pgmchk

t_rdrsrc

t_pgm4

Program Check execution time

Read Resource execution time

Program Longword execution time

Erase Flash Sector execution time

Read 1s All Blocks execution time

Read Once execution time

—

μs

—

μs

—

145

114

1.8

μs

—

t_ersscr

t_rd1all

μs

t_rdonce

—

t_pgmonceProgram Once execution time

—

μs

—

t_ersall

Erase All Blocks execution time

650

μs

t_vfykey

Verify Backdoor Access Key execution time

1. Assumes 25 MHz flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

2.4.1.3 Flash high voltage current behaviors

Table 16. Flash high voltage current behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

I_{DD_PGM}

Average current adder during high voltage

flash programming operation

—

2.5

6.0

I_{DD_ERS}

Average current adder during high voltage

flash erase operation

—

1.5

4.0

2.4.1.4 Reliability specifications

Table 17. NVM reliability specifications

Symbol Description

Min.

Program Flash

Typ.¹

Max.

Unit

Notes

t_nvmretp10kData retention after up to 10 K cycles

t_nvmretp1kData retention after up to 1 K cycles

n_nvmcycpCycling endurance

—

years

cycles

—

100

50 K

10 K

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant

25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering

Bulletin EB619.

2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ T_j≤ 125 °C.

2.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

2.6 Analog

2.6.1 ADC electrical specifications

The 16-bit accuracy specifications listed in Table 1 and Table 19 are achievable on the

differential pins ADCx_DP0, ADCx_DM0.

All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy

specifications.

2.6.1.1 16-bit ADC operating conditions

Table 18. 16-bit ADC operating conditions

Symbol Description

Conditions

Min.

1.8

Typ.¹

Max.

3.6

Unit

Notes

V_DDA

ΔV_DDA

ΔV_SSA

V_REFH

Supply voltage

Ground voltage

Absolute

—

Delta to V_DD(V_DD– V_DDA

)

-100

1.13

+100

V_DDA

Delta to V_SS(V_SS– V_SSA

)

ADC reference

voltage high

V_DDA

V_REFL

V_ADIN

ADC reference

voltage low

V_SSA

Input voltage

• 16-bit differential mode

• All other modes

• 16-bit mode

VREFL

—

31/32 *

VREFH

C_ADIN

Input capacitance

—

• 8-bit / 10-bit / 12-bit

modes

R_ADIN

R_AS

Input series

resistance

—

kΩ

Analog source

resistance

(external)

13-bit / 12-bit modes

f_ADCK< 4 MHz

—

Table continues on the next page...

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 18. 16-bit ADC operating conditions (continued)

Symbol Description

Conditions

Min.

Typ.¹

Max.

Unit

Notes

f_ADCK

C_rate

ADC conversion ≤ 13-bit mode

clock frequency

1.0

—

18.0

MHz

ADC conversion 16-bit mode

clock frequency

2.0

—

12.0

MHz

Ksps

ADC conversion ≤ 13-bit modes

rate

No ADC hardware averaging

20.000

818.330

Continuous conversions

enabled, subsequent

conversion time

C_rate

ADC conversion 16-bit mode

rate

No ADC hardware averaging

37.037

—

461.467

Ksps

Continuous conversions

enabled, subsequent

conversion time

1. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. For packages without dedicated VREFH and VREFL pins, V_REFHis internally tied to V_DDA, and V_REFLis internally tied to

V_SSA

4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The R_AS/C_AS

time constant should be kept to < 1 ns.

5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

SIMPLIFIED

INPUT PIN EQUIVALENT

ZADIN

CIRCUIT

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

ZAS

leakage

due to

input

ADC SAR

ENGINE

RAS

RADIN

protection

VADIN

CAS

VAS

RADIN

INPUT PIN

CADIN

Figure 5. ADC input impedance equivalency diagram

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

2.6.1.2 16-bit ADC electrical characteristics

Table 19. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Symbol Description

Conditions¹

Min.

0.215

1.2

Typ.²

Max.

1.7

3.9

6.1

7.3

9.5

Unit

Notes

I_{DDA_ADC}Supply current

—

ADC asynchronous

clock source

• ADLPC = 1, ADHSC = 0

• ADLPC = 1, ADHSC = 1

• ADLPC = 0, ADHSC = 0

• ADLPC = 0, ADHSC = 1

2.4

4.0

5.2

6.2

MHz

t_ADACK= 1/

f_ADACK

2.4

f_ADACK

3.0

4.4

Sample Time

See Reference Manual chapter for sample times

TUE

DNL

Total unadjusted

error

• 12-bit modes

• <12-bit modes

—

6.8

2.1

LSB⁴

1.4

Differential non-

linearity

• 12-bit modes

• <12-bit modes

—

0.7

0.2

–1.1 to

+1.9

–0.3 to

0.5

INL

Integral non-linearity

• 12-bit modes

• <12-bit modes

—

1.0

0.5

–2.7 to

+1.9

LSB⁴

–0.7 to

+0.5

E_FS

E_Q

Full-scale error

• 12-bit modes

• <12-bit modes

• 16-bit modes

• ≤13-bit modes

—

–4

–1.4

–1 to 0

—

–5.4

–1.8

—

LSB⁴

V_ADIN= V_DDA

Quantization error

0.5

ENOB Effective number of 16-bit differential mode

bits

12.8

11.9

14.5

13.8

—

bits

• Avg = 32

• Avg = 4

16-bit single-ended mode

• Avg = 32

12.2

11.4

13.9

13.1

—

bits

• Avg = 4

Signal-to-noise plus See ENOB

SINAD

6.02 × ENOB + 1.76

distortion

THD

Total harmonic

distortion

16-bit differential mode

• Avg = 32

—

-94

-85

—

16-bit single-ended mode

• Avg = 32

—

Table continues on the next page...

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 19. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Symbol Description

Conditions¹

Min.

Typ.²

Max.

Unit

Notes

SFDR Spurious free

dynamic range

16-bit differential mode

• Avg = 32

—

16-bit single-ended mode

• Avg = 32

E_IL

Input leakage error

I_In× R_AS

I_In= leakage

current

(refer to the

MCU's voltage

and current

operating

ratings)

Temp sensor slope

Across the full temperature

range of the device

1.55

706

1.62

716

1.69

726

mV/°C

V_TEMP25Temp sensor voltage 25 °C

1. All accuracy numbers assume the ADC is calibrated with V_REFH= V_DDA

2. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1

MHz ADC conversion clock speed.

4. 1 LSB = (V_REFH- V_REFL)/2^N

5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)

6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

8. ADC conversion clock < 3 MHz

Typical ADC 16-bit Differential ENOB vs ADC Clock

100Hz, 90% FS Sine Input

15.00

14.70

14.40

14.10

13.80

13.50

13.20

12.90

12.60

Hardware Averaging Disabled

Averaging of 4 samples

12.30

12.00

Averaging of 8 samples

Averaging of 32 samples

ADC Clock Frequency (MHz)

Figure 6. Typical ENOB vs. ADC_CLK for 16-bit differential mode

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Typical ADC 16-bit Single-Ended ENOB vs ADC Clock

100Hz, 90% FS Sine Input

14.00

13.75

13.50

13.25

13.00

12.75

12.50

12.25

12.00

11.75

11.50

11.25

11.00

Averaging of 4 samples

Averaging of 32 samples

ADC Clock Frequency (MHz)

Figure 7. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

2.6.2 CMP and 6-bit DAC electrical specifications

Table 20. Comparator and 6-bit DAC electrical specifications

Symbol

V_DD

Description

Min.

1.8

Typ.

—

Max.

3.6

Unit

Supply voltage

I_DDHS

I_DDLS

V_AIN

Supply current, High-speed mode (EN=1, PMODE=1)

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

—

200

μA

—

V_SS– 0.3

—

V_DD

V_AIO

Analog input offset voltage

Analog comparator hysteresis¹

• CR0[HYSTCTR] = 00

—

V_H

—

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

V_CMPOh

V_CMPOl

t_DHS

Output high

Output low

V_DD– 0.5

—

0.5

200

—

Propagation delay, high-speed mode (EN=1,

PMODE=1)

t_DLS

Propagation delay, low-speed mode (EN=1,

PMODE=0)

250

600

Analog comparator initialization delay²

6-bit DAC current adder (enabled)

6-bit DAC integral non-linearity

—

μs

μA

LSB³

I_DAC6b

INL

–0.5

–0.3

—

0.5

0.3

DNL

6-bit DAC differential non-linearity

LSB

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD–0.6 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.

3. 1 LSB = V_reference/64

0.08

0.07

0.06

0.05

0.04

0.03

HYSTCTR

Setting

0.02

0.01

0.1

0.4

0.7

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 8. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

0.18

0.16

0.14

0.12

HYSTCTR

Setting

0.1

0.08

0.06

0.04

0.02

0.1

0.4

0.7

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

2.6.3 12-bit DAC electrical characteristics

2.6.3.1 12-bit DAC operating requirements

Table 21. 12-bit DAC operating requirements

Symbol

V_DDA

V_DACR

C_L

Desciption

Min.

1.8

1.13

—

Max.

3.6

100

Unit

Notes

Supply voltage

Reference voltage

Output load capacitance

Output load current

I_L

—

1. The DAC reference can be selected to be V_DDAor VREFH.

2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

2.6.3.2 12-bit DAC operating behaviors

Table 22. 12-bit DAC operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DDA_DACL}Supply current — low-power mode

—

250

μA

I_{DDA_DACH}Supply current — high-speed mode

—

100

0.7

—

900

200

μA

μs

t_DACLPFull-scale settling time (0x080 to 0xF7F) —

low-power mode

t_DACHPFull-scale settling time (0x080 to 0xF7F) —

high-power mode

μs

t_CCDACLPCode-to-code settling time (0xBF8 to 0xC08)

— low-power mode and high-speed mode

μs

V_dacoutlDAC output voltage range low — high-speed

mode, no load, DAC set to 0x000

100

V_DACR

LSB

V_dacouthDAC output voltage range high — high-

speed mode, no load, DAC set to 0xFFF

V_DACR

−100

—

INL

DNL

Integral non-linearity error — high speed

mode

—

Differential non-linearity error — V_DACR> 2

—

Differential non-linearity error — V_DACR

VREF_OUT

—

V_OFFSETOffset error

E_GGain error

PSRR Power supply rejection ratio, V_DDA≥ 2.4 V

—

0.4

0.1

0.8

0.6

%FSR

—

T_CO

T_GE

Rop

Temperature coefficient offset voltage

Temperature coefficient gain error

Output resistance (load = 3 kΩ)

Slew rate -80h→ F7Fh→ 80h

3.7

—

μV/C

%FSR/C

0.000421

—

250

V/μs

• High power (SP_HP

)

1.2

1.7

—

• Low power (SP_LP

3dB bandwidth

)

0.05

0.12

kHz

• High power (SP_HP

• Low power (SP_LP

)

550

—

)

1. Settling within 1 LSB

2. The INL is measured for 0 + 100 mV to V_DACR−100 mV

3. The DNL is measured for 0 + 100 mV to V_DACR−100 mV

4. The DNL is measured for 0 + 100 mV to V_DACR−100 mV with V_DDA> 2.4 V

5. Calculated by a best fit curve from V_SS+ 100 mV to V_DACR− 100 mV

6. V_DDA= 3.0 V, reference select set for V_DDA(DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to

0x800, temperature range is across the full range of the device

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

-2

-4

-6

-8

500

1000

1500

2000

2500

3000

3500

4000

Digital Code

Figure 10. Typical INL error vs. digital code

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

1.499

1.4985

1.498

1.4975

1.497

1.4965

1.496

105

125

-40

Temperature °C

Figure 11. Offset at half scale vs. temperature

2.7 Timers

See General switching specifications.

2.8 Communication interfaces

2.8.1 SPI switching specifications

The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following tables

provide timing characteristics for classic SPI timing modes. See the SPI chapter of the

chip's Reference Manual for information about the modified transfer formats used for

communicating with slower peripheral devices.

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

All timing is shown with respect to 20% V_DDand 80% V_DDthresholds, unless noted, as

well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.

Table 23. SPI master mode timing on slew rate disabled pads

Num.

Symbol Description

Min.

Max.

Unit

Note

f_op

Frequency of operation

f_periph/2048

2 x t_periph

f_periph/2

t_SPSCK

SPSCK period

2048 x

t_periph

t_Lead

t_Lag

Enable lead time

Enable lag time

1/2

—

t_SPSCK

—

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

1024 x

t_periph

t_SU

t_HI

Data setup time (inputs)

Data hold time (inputs)

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

—

t_v

—

t_HO

t_RI

—

t_periph- 25

t_FI

Fall time input

t_RO

t_FO

Rise time output

—

Fall time output

1. For SPI0 f_periphis the bus clock (f_BUS). For SPI1 f_periphis the system clock (f_SYS).

2. t_periph= 1/f_periph

Table 24. SPI master mode timing on slew rate enabled pads

Num.

Symbol Description

Min.

Max.

Unit

Note

f_op

Frequency of operation

f_periph/2048

2 x t_periph

f_periph/2

t_SPSCK

SPSCK period

2048 x

t_periph

t_Lead

t_Lag

Enable lead time

Enable lag time

1/2

—

t_SPSCK

—

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

1024 x

t_periph

t_SU

t_HI

Data setup time (inputs)

Data hold time (inputs)

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

—

t_v

—

t_HO

t_RI

—

t_periph- 25

t_FI

Fall time input

t_RO

t_FO

Rise time output

—

Fall time output

1. For SPI0 f_periphis the bus clock (f_BUS). For SPI1 f_periphis the system clock (f_SYS).

2. t_periph= 1/f_periph

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

(OUTPUT)

SPSCK

(CPOL=0)

(OUTPUT)

SPSCK

(CPOL=1)

(OUTPUT)

MISO

(INPUT)

BIT 6 . . . 1

MSB IN

LSB IN

MOSI

(OUTPUT)

BIT 6 . . . 1

MSB OUT

LSB OUT

1. If configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 12. SPI master mode timing (CPHA = 0)

(OUTPUT)

SPSCK

(CPOL=0)

(OUTPUT)

SPSCK

(CPOL=1)

(OUTPUT)

MISO

(INPUT)

BIT 6 . . . 1

LSB IN

MSB IN

MOSI

(OUTPUT)

PORT DATA

BIT 6 . . . 1

MASTER MSB OUT

PORT DATA

MASTER LSB OUT

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 13. SPI master mode timing (CPHA = 1)

Table 25. SPI slave mode timing on slew rate disabled pads

Num.

Symbol Description

Min.

Max.

f_periph/4

—

Unit

Note

f_op

t_SPSCK

t_Lead

t_Lag

Frequency of operation

SPSCK period

Enable lead time

Enable lag time

4 x t_periph

—

t_periph

—

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

—

Table continues on the next page...

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 25. SPI slave mode timing on slew rate disabled pads (continued)

Num.

Symbol Description

Min.

2.5

3.5

—

Max.

—

Unit

Note

—

t_SU

t_HI

t_a

Data setup time (inputs)

Data hold time (inputs)

Slave access time

—

t_periph

t_dis

t_v

Slave MISO disable time

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

—

t_HO

t_RI

t_FI

—

t_periph- 25

Fall time input

t_RO

t_FO

Rise time output

—

Fall time output

1. For SPI0 f_periphis the bus clock (f_BUS). For SPI1 f_periphis the system clock (f_SYS).

2. t_periph= 1/f_periph

3. Time to data active from high-impedance state

4. Hold time to high-impedance state

Table 26. SPI slave mode timing on slew rate enabled pads

Num.

Symbol Description

Min.

Max.

f_periph/4

—

Unit

Note

f_op

t_SPSCK

t_Lead

t_Lag

Frequency of operation

SPSCK period

Enable lead time

Enable lag time

4 x t_periph

—

t_periph

—

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

—

t_SU

t_HI

t_a

Data setup time (inputs)

Data hold time (inputs)

Slave access time

—

t_periph

122

t_dis

t_v

Slave MISO disable time

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

—

t_HO

t_RI

t_FI

—

t_periph- 25

Fall time input

t_RO

t_FO

Rise time output

—

Fall time output

1. For SPI0 f_periphis the bus clock (f_BUS). For SPI1 f_periphis the system clock (f_SYS).

2. t_periph= 1/f_periph

3. Time to data active from high-impedance state

4. Hold time to high-impedance state

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

(INPUT)

SPSCK

(CPOL=0)

(INPUT)

SPSCK

(CPOL=1)

(INPUT)

see

note

SEE

NOTE

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE MSB

SLAVE LSB OUT

MOSI

(INPUT)

LSB IN

MSB IN

BIT 6 . . . 1

NOTE: Not defined

Figure 14. SPI slave mode timing (CPHA = 0)

(INPUT)

SPSCK

(CPOL=0)

(INPUT)

SPSCK

(CPOL=1)

(INPUT)

SLAVE MSB OUT

see

note

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE LSB OUT

LSB IN

MOSI

(INPUT)

MSB IN

NOTE: Not defined

Figure 15. SPI slave mode timing (CPHA = 1)

2.8.2 Inter-Integrated Circuit Interface (I²C) timing

Table 27. I ²C timing

Characteristic

Symbol

Standard Mode

Minimum Maximum

100

Fast Mode

Unit

Minimum

Maximum

SCL Clock Frequency

f_SCL

400

kHz

Table continues on the next page...

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 27. I ²C timing (continued)

Characteristic

Symbol

Standard Mode

Minimum Maximum

Fast Mode

Unit

Minimum

Maximum

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated.

t_HD; STA

—

0.6

—

µs

LOW period of the SCL clock

HIGH period of the SCL clock

t_LOW

t_HIGH

4.7

—

1.3

0.6

—

µs

Set-up time for a repeated START

condition

t_SU; STA

4.7

Data hold time for I²C bus devices

t_HD; DAT

t_SU; DAT

t_r

0¹

250⁴

—

3.45²

—

0³

100^{2, 5}

20 +0.1C_b

0.6

0.9¹

—

µs

Data set-up time

Rise time of SDA and SCL signals

Fall time of SDA and SCL signals

Set-up time for STOP condition

1000

300

—

300

—

t_f

—

t_SU; STO

t_BUF

Bus free time between STOP and

START condition

4.7

—

1.3

—

Pulse width of spikes that must be

suppressed by the input filter

t_SP

N/A

1. The master mode I²C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves

acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL

lines.

2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.

3. Input signal Slew = 10 ns and Output Load = 50 pF

4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.

5. A Fast mode I²C bus device can be used in a Standard mode I2C bus system, but the requirement t_{SU; DAT}≥ 250 ns must

then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a

device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t_rmax+ t_{SU; DAT}

= 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification) before the SCL line is released.

6. C_b= total capacitance of the one bus line in pF.

SDA

t_{SU; DAT}

t_f

t_r

t_BUF

t_f

t_r

t_{HD; STA}

t_SP

t_LOW

SCL

t_{SU; STA}

t_{SU; STO}

HD; STA

t_{HD; DAT}

t_HIGH

Figure 16. Timing definition for fast and standard mode devices on the I²C bus

2.8.3 UART

See General switching specifications.

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Revision History

2.9 Human-machine interfaces (HMI)

2.9.1 TSI electrical specifications

Table 28. TSI electrical specifications

Symbol

TSI_RUNF

TSI_RUNV

Description

Min.

—

Typ.

100

—

Max.

—

Unit

µA

Fixed power consumption in run mode

Variable power consumption in run mode

(depends on oscillator's current selection)

1.0

128

µA

TSI_EN

TSI_DIS

Power consumption in enable mode

Power consumption in disable mode

TSI analog enable time

—

100

1.2

—

µA

µs

TSI_TEN

—

TSI_CREF

TSI_DVOLT

TSI reference capacitor

—

1.0

—

Voltage variation of VP & VM around nominal

values

0.19

1.03

3 Revision History

The following table provides a revision history for this document.

Table 29. Revision History

Rev. No.

Date

Substantial Changes

April 2016

• Updated RF Transceiver features list in topic 2.2.

• Made text changes in the 'Supply current in Transmit mode' characteristic in Table 10.

Power Supply Current.

• Updated Typical values of 'Blocking Immunity', 'AM Rejection , AM modulated'

characteristics in Table 12. Receiver Specification.

• Updated content of RF wiring options in topic "Typical Applications Circuit" and also

updated the circuit diagram to be visually clear.

• Corrected description of I_{EREFSTEN32KHz}in Table 6. Low power mode peripheral adders

— typical value.

MKW01 MCU Section Data Sheet, Rev. 6, 04/2016

Freescale Semiconductor, Inc.

Information in this document is provided solely to enable system and

software implementers to use Freescale products. There are no express

or implied copyright licenses granted hereunder to design or fabricate

any integrated circuits based on the information in this document.

Freescale reserves the right to make changes without further notice to

any products herein.

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Freescale assume any liability arising out of the application or use of

any product or circuit, and specifically disclaims any and all liability,

including without limitation consequential or incidental damages.

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actual performance may vary over time. All operating parameters,

including “typicals,” must be validated for each customer application by

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