935346773557_技术文档

Document Number MPC5746C

Rev. 6, 11/2018

NXP Semiconductors

Data Sheet: Technical Data

MPC5746C

MPC5746C Microcontroller

Datasheet

Features

• 32-channel eDMA controller with multiple transfer

request sources using DMAMUX

• 1 × 160 MHz Power Architecture® e200z4 Dual issue,

32-bit CPU

• Boot Assist Flash (BAF) supports internal flash

programming via a serial link (SCI)

– Single precision floating point operations

– 8 KB instruction cache and 4 KB data cache

– Variable length encoding (VLE) for significant code

density improvements

• Analog

– Two analog-to-digital converters (ADC), one 10-bit

and one 12-bit

• 1 x 80 MHz Power Architecture® e200z2 Single issue,

32-bit CPU

– Three analog comparators

– Cross Trigger Unit to enable synchronization of

ADC conversions with a timer event from the

eMIOS or from the PIT

– Using variable length encoding (VLE) for

significant code size footprint reduction

• End to end ECC

• Communication

– All bus masters, for example, cores, generate a

single error correction, double error detection

(SECDED) code for every bus transaction

– SECDED covers 64-bit data and 29-bit address

– Four Deserial Serial Peripheral Interface (DSPI)

– Four Serial Peripheral interface (SPI)

– 16 serial communication interface (LIN) modules

– Eight enhanced FlexCAN3 with FD support

– Four inter-IC communication interface (I2C)

– ENET complex (10/100 Ethernet) that supports

Multi queue with AVB support, 1588, and MII/

RMII

• Memory interfaces

– 3 MB on-chip flash memory supported with the

flash memory controller

– 3 x flash memory page buffers (3-port flash memory

controller)

– Dual-channel FlexRay controller

– 384 KB on-chip SRAM across three RAM ports

• Audio

– Synchronous Audio Interface (SAI)

– Fractional clock dividers (FCD) operating in

conjunction with the SAI

• Clock interfaces

– 8-40 MHz external crystal (FXOSC)

– 16 MHz IRC (FIRC)

– 128 KHz IRC (SIRC)

• Configurable I/O domains supporting FlexCAN,

LINFlexD, Ethernet, and general I/O

– 32 KHz external crystal (SXOSC)

– Clock Monitor Unit (CMU)

– Frequency modulated phase-locked loop (FMPLL)

– Real Time Counter (RTC)

• Supports wake-up from low power modes via the

WKPU controller

• On-chip voltage regulator (VREG)

• System Memory Protection Unit (SMPU) with up to 32

region descriptors and 16-byte region granularity

• Debug functionality

– e200z2 core:NDI per IEEE-ISTO 5001-2008

• 16 Semaphores to manage access to shared resources

Class3+

• Interrupt controller (INTC) capable of routing

interrupts to any CPU

– e200z4 core: NDI per IEEE-ISTO 5001-2008 Class

3+

• Crossbar switch architecture for concurrent access to

peripherals, flash memory, and RAM from multiple

bus masters

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

• Timer

– 16 Periodic Interrupt Timers (PITs)

– Two System Timer Modules (STM)

– Three Software Watchdog Timers (SWT)

– 64 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels

• Device/board boundary Scan testing supported with Joint Test Action Group (JTAG) of IEEE 1149.1 and IEEE 1149.7

(CJTAG)

• Security

– Hardware Security Module (HSMv2)

– Password and Device Security (PASS) supporting advanced censorship and life-cycle management

– One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts

• Functional Safety

– ISO26262 ASIL-B compliance

• Multiple operating modes

– Includes enhanced low power operation

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

2

NXP Semiconductors

Table of Contents

1

2

3

Block diagram.................................................................................... 4

6.3.2

Flash memory Array Integrity and Margin Read

specifications.......................................................... 39

Flash memory module life specifications............... 40

Data retention vs program/erase cycles.................. 40

Flash memory AC timing specifications................ 41

Flash read wait state and address pipeline control

settings ................................................................... 42

Family comparison.............................................................................4

Ordering parts.....................................................................................8

3.1 Determining valid orderable parts ..........................................8

3.2 Ordering Information ............................................................. 9

General............................................................................................... 9

4.1 Absolute maximum ratings..................................................... 9

4.2 Recommended operating conditions....................................... 11

4.3 Voltage regulator electrical characteristics............................. 13

4.4 Voltage monitor electrical characteristics...............................17

4.5 Supply current characteristics................................................. 18

4.6 Electrostatic discharge (ESD) characteristics......................... 22

4.7 Electromagnetic Compatibility (EMC) specifications............ 22

I/O parameters....................................................................................23

5.1 AC specifications @ 3.3 V Range...........................................23

5.2 DC electrical specifications @ 3.3V Range............................24

5.3 AC specifications @ 5 V Range..............................................25

5.4 DC electrical specifications @ 5 V Range..............................25

5.5 Reset pad electrical characteristics..........................................26

5.6 PORST electrical specifications..............................................28

Peripheral operating requirements and behaviours............................28

6.1 Analog..................................................................................... 28

6.3.3

6.3.4

6.3.5

6.3.6

4

6.4 Communication interfaces.......................................................43

6.4.1

6.4.2

DSPI timing............................................................ 43

FlexRay electrical specifications............................ 49

6.4.2.1

6.4.2.2

6.4.2.3

6.4.2.4

FlexRay timing....................................49

TxEN...................................................49

TxD..................................................... 50

RxD..................................................... 51

5

6.4.3

6.4.4

Ethernet switching specifications........................... 52

SAI electrical specifications .................................. 53

6.5 Debug specifications............................................................... 55

6.5.1

6.5.2

6.5.3

6.5.4

JTAG interface timing ........................................... 55

Nexus timing...........................................................58

WKPU/NMI timing................................................ 60

External interrupt timing (IRQ pin)........................ 61

6

7

8

9

Thermal attributes.............................................................................. 61

7.1 Thermal attributes................................................................... 61

Dimensions.........................................................................................65

8.1 Obtaining package dimensions ...............................................65

Pinouts................................................................................................66

9.1 Package pinouts and signal descriptions................................. 66

6.1.1

6.1.2

ADC electrical specifications................................. 28

Analog Comparator (CMP) electrical

specifications.......................................................... 33

6.2 Clocks and PLL interfaces modules........................................34

6.2.1

6.2.2

6.2.3

6.2.4

Main oscillator electrical characteristics.................34

32 kHz Oscillator electrical specifications ............ 36

16 MHz RC Oscillator electrical specifications......36

128 KHz Internal RC oscillator Electrical

10 Reset sequence................................................................................... 66

10.1 Reset sequence........................................................................ 66

10.1.1

10.1.2

10.1.3

Reset sequence duration..........................................66

BAF execution duration..........................................66

Reset sequence description..................................... 67

specifications ......................................................... 37

PLL electrical specifications ..................................37

6.2.5

6.3 Memory interfaces...................................................................38

6.3.1 Flash memory program and erase specifications....38

11 Revision History.................................................................................69

11.1 Revision History......................................................................69

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

3

Block diagram

1 Block diagram

80 MHz e200z2

System bus masters

160 MHz e200z4

64-bit AHB

E2 E-ECC

Nexus 3+

System

2 x STM

8 KB i-cache 4 KB d-cache

WKPU

BAF

Ethernet

(ENET)

HSMv2

Flexray

SPFP-APU

E2 E-ECC

Nexus 3+

PMC

eDMA

64-bit AHB

FMPLL

16 MHz FIRC

RTC/API

DEBUG/

JTAG

2 x SWTs

16 x SEMA42

16 x PIT-RTI

FCCU

PASS

SSCM

64-bit data

E2 E-ECC

SMPU

32 KHz

SXOSC

MC_CGM,

MC_PCU,

MC_ME,

Peripheral

Flash Memory

E2 E-ECC

2xRAM

E2 E-ECC

Low power

unit interface

(LPU)

bridge

MC_RGM

E2 E-ECC

3 x SA-PF buffers

Triple ported

64-bit wide RAM

256 KB array

128 KHz

SIRC

SIUL

8–40 MHz

FXOSC

STCU

(MBIST)

3 MB array (inc EEE)

MEMU

CMU

TDM

Peripheral clusters

Padkeeper

support

68 ch 10-bit ADC0 31 ch 12-bit ADC1 1 x FlexCAN(PN)* 16 x LINFlexD

(mix int and ext)

7 x FlexCAN*

Register

protection

2

C

4 x I

3 x analog

4 x DSPI

4 x SPI

3 x SAI

comparator (CMP)

3 x FCD

2 x eMIOS + BCTU

2-core INTC

DMA and

2 x channel mux

1 x CRC

* All FlexCANs optionally support

CAN FD

Figure 1. MPC5746C block diagram

2 Family comparison

The following table provides a summary of the different members of the MPC5746C

family and their proposed features. This information is intended to provide an

understanding of the range of functionality offered by this family. For full details of all of

the family derivatives please contact your marketing representative.

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

4

NXP Semiconductors

Family comparison

NOTE

All optional features (Flash memory, RAM, Peripherals) start

with lowest number or address (e.g., FlexCAN0) and end at

highest available number or address (e.g., MPC574xB/C have 6

CAN, ending with FlexCAN5).

Table 1. MPC5746C Family Comparison1

Feature

MPC5745B

MPC5744B

MPC5746B

MPC5744C

e200z4

MPC5745C

e200z4

MPC5746C

e200z4

CPUs

e200z4

e200z2

FPU

e200z4

Maximum

Operating

Frequency²

160MHz (Z4)

80MHz (Z2)

160MHz (Z4)

80MHz (Z2)

160MHz (Z4)

80MHz (Z2)

Flash memory

2 MB

1.5 MB

3 MB

1.5 MB

2 MB

3 MB

EEPROM

support

Emulated up to 64K

Emulated up to 128K

RAM

256 KB

192 KB

384 KB

(Optional

512KB)³

192 KB

256 KB

384 KB

(Optional

512KB)³

ECC

SMPU

End to End

16 entry

32 channels

DMA

10-bit ADC

36 Standard channels

32 External channels

15 Precision channels

16 Standard channels

3

12-bit ADC

Analog

Comparator

BCTU

SWT

1

1, SWT[0]

1, STM[0]

2⁴

2

STM

PIT-RTI

16 channels PIT

1 channels RTI

1

RTC/API

Total Timer I/O⁵

64 channels

16-bits

LINFlexD

1

Master and Slave (LINFlexD[0], 11 Master

(LINFlexD[1:11])

Master and Slave (LINFlexD[0], 15 Master

(LINFlexD[1:15])

FlexCAN

DSPI/SPI

6 with optional CAN FD support (FlexCAN[0:5])

8 with optional CAN FD support (FlexCAN[0:7])

4 x DSPI

4 x SPI

Table continues on the next page...

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

5

Family comparison

Table 1. MPC5746C Family Comparison1 (continued)

Feature

I²C

MPC5745B

MPC5744B

MPC5746B

MPC5744C

MPC5745C

MPC5746C

4

3

4

3

4

3

4

3

SAI/I²S

FXOSC

SXOSC

FIRC

8 - 40 MHz

32 KHz

16 MHz

128 KHz

1

SIRC

FMPLL

Low Power Unit

(LPU)

Yes

FlexRay 2.1

(dual channel)

Yes, 128 MB

1

Yes, 128 MB

1

Yes, 128 MB

1

Ethernet (RMII,

MII + 1588, Muti

queue AVB

1

support)

CRC

1

MEMU

STCU2

2

1

HSM-v2

Optional

(security)

Censorship

FCCU

Yes

1

Safety level

User MBIST

Specific functions ASIL-B certifiable

Yes

I/O Retention in

Standby

GPI

1 (100 BGA), 17 (176 LQFP-EP), 18 (256 BGA), 18 (324 BGA)

65 (100 BGA), 129 (176 LQFP-EP), 178 (256 BGA), 246 (324 BGA)

JTAGC,

GPIO

Debug

cJTAG

Nexus

Z4 N3+ (Only available on 324BGA (development only) )

Z2 N3+ (Only available on 324BGA (development only) )

Packages

176 LQFP-EP

256 BGA

176 LQFP-EP

256 BGA

176 LQFP-EP

256 BGA

176 LQFP-EP

256 BGA

176 LQFP-EP

256 BGA

176 LQFP-EP

256 BGA,

100 BGA

324 BGA

(development

only)

100 BGA

1. Feature set dependent on selected peripheral multiplexing, table shows example. Peripheral availability is package

dependent.

2. Based on 125°C ambient operating temperature and subject to full device characterization.

3. Contact NXP representative for part number

4. Additional SWT included when HSM option selected

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

6

NXP Semiconductors

Family comparison

5. See device datasheet and reference manual for information on to timer channel configuration and functions.

Table 2. MPC5746C Family Comparison - NVM Memory Map 1

Start Address

End Address

Flash block

RWW partition

MPC5744

MPC5745

MPC5746

0x01000000

0x0103FFFF

256 KB code

Flash block 0

6

available

0x01040000

0x01080000

0x010C0000

0x01100000

0x01140000

0x01180000

0x011C0000

0x01200000

0x01240000

0x0107FFFF

0x010BFFFF

0x010FFFFF

0x0113FFFF

0x0117FFFF

0x011BFFFF

0x011FFFFF

0x0123FFFF

0x0127FFFF

256 KB code

Flash block 1

6

7

available

256 KB code

Flash block 2

256 KB code

Flash block3

available

256 KB code

Flash block 4

not available

available

256 KB code

Flash block 5

available

256 KB code

Flash block 6

not available

256 KB code

Flash block 7

256 KB code

Flash block 8

256 KB code

Flash block 9

Table 3. MPC5746C Family Comparison - NVM Memory Map 2

Start Address

End Address

Flash block

RWW partition

MPC5744B

MPC5745B

MPC5746B

MPC5744C

MPC5745C

MPC5746C

0x00F90000¹

0x00F94000

0x00F98000

0x00F9C000

0x00FA0000

0x00FA4000

0x00FA8000

0x00FAC000

0x00FB0000

0x00FB8000

0x00FC0000

0x00FC8000

0x00FD0000

0x00FD8000

0x00FE0000

0x00FF0000

0x00F93FFF

0x00F97FFF

0x00F9BFFF

0x00F9FFFF

0x00FA3FFF

0x00FA7FFF

0x00FABFFF

0x00FAFFFF

0x00FB7FFF

0x00FBFFFF

0x00FC7FFF

0x00FCFFFF

0x00FD7FFF

0x00FDFFFF

0x00FEFFFF

0x00FFFFFF

16 KB data Flash

32 KB data Flash

64 KB data Flash

2

3

available

available¹

available

not available

Reserved

available

0

1

0

1

available

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

7

Ordering parts

1. Flexible patitions for boot and EEPROM

Table 4. MPC5748G Family Comparison - NVM Memory Map 3

Start Address

End Address

Flash block

RWW

MPC5744B

MPC5745B

MPC5746B

MPC5744C

MPC5745C

MPC5746C

0x00610000

0x00620000

0x0061FFFF

0x0062FFFF

64 KB HSM Code

block 2

0

1

available

64 KB HSM Code

block 3

available

HSM Data

0x00630000

0x00F7FFFF

9536 KB

Reserved

HSM Data

0x00F80000

0x00F84000

0x00F88000

0x00F83FFF

0x00F87FFF

0x00F8BFFF

16 KB HSM data

block 0

4

5

available

Reserved

available

16 KB HSM data

block 1

16 KB

Small HSM Code Block

0x00F8C000

0x00F8FFFF

16 KB Code Flash

block

0

available

Table 5. MPC5746C Family Comparison - RAM Memory Map

Start Address

0x40000000

0x40002000

0x40010000

0x40020000

0x40030000

0x40040000

0x40050000

0x40060000

0x40070000

End Address

0x40001FFF

0x4000FFFF

0x4001FFFF

0x4002FFFF

0x4003FFFF

0x4004FFFF

0x4005FFFF

0x4006FFFF

0x4007FFFF

Allocated size

8 KB

Description

SRAM0

SRAM1

SRAM2

SRAM3

SRAM4

SRAM5

SRAM6

SRAM7

SRAM8

MPC5744

available

MPC5745

available

MPC5746

available

optional

56 KB

available

64 KB

available

64 KB

available

64 KB

not available

available

64 KB

not available

64 KB

optional

3 Ordering parts

3.1 Determining valid orderable parts

To determine the orderable part numbers for this device, go to www.nxp.com and

perform a part number search for the following device number: MPC5746C.

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

8

NXP Semiconductors

General

3.2 Ordering Information

P

PC 57

4

6

C

S

K0

MJ

6

M

R

Example Code

Qualification Status

Power Architecture

Automotive Platform

Core Version

Flash Size (core dependent)

Product

Optional fields

Fab and mask indicator

Temperature spec.

Package Code

CPU Frequency

R = Tape & Reel (blank if Tray)

Product Version

B = Single core

C = Dual core

Package Code

Fab and mask version indicator

K = TSMC Fab

#(0,1,etc.) = Version of the

maskset, like rev. 0=0N65H

Qualification Status

P = Engineering samples

S = Automotive qualified

KU = 176 LQFP EP

MJ = 256 MAPBGA

MN = 324 MAPBGA

PC = Power Architecture

Automotive Platform

MH = 100MAPBGA

Temperature spec.

CPU Frequency

C = -40.C to +85.C Ta

V = -40.C to +105.C Ta

M = -40.C to +125.C Ta

57 = Power Architecture in 55nm

2 = Z4 operates upto 120 MHz

6 = Z4 operates upto 160 MHz

Optional fields

Core Version

Blank = No optional feature

S = HSM (Security Module)

4 = e200z4 Core Version (highest

core version in the case of multiple

cores)

F = CAN FD

B = HSM + CAN FD

R = 512K RAM

T = HSM + 512K RAM

G* = CAN FD + 512K RAM

H* = HSM + CAN FD + 512K RAM

* G and H for 5746 B/C only

Shipping Method

R = Tape and reel

Blank = Tray

Flash Memory Size

4 = 1.5 MB

5 = 2 MB

6 = 3 MB

Note: Not all part number combinations are available as production product

4 General

4.1 Absolute maximum ratings

NOTE

Functional operating conditions appear in the DC electrical

characteristics. Absolute maximum ratings are stress ratings

only, and functional operation at the maximum values is not

guaranteed. See footnotes in Table 6 for specific conditions

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

9

General

Stress beyond the listed maximum values may affect device

reliability or cause permanent damage to the device.

Table 6. Absolute maximum ratings

Symbol

V_{DD_HV_A}, V_DD_2,_{_}₃_{HV_B}

V_{DD_HV_C}

Parameter

Conditions¹

Min

Max

Unit

,

3.3 V - 5. 5V input/output supply voltage

—

–0.3

6.0

V

4, 5

V_{DD_HV_FLA}

3.3 V flash supply voltage (when supplying

from an external source in bypass mode)

—

–0.3

3.63

V

6

V_{DD_LP_DEC}

Decoupling pin for low power regulators⁷

3.3 V / 5.0 V ADC1 high reference voltage

3.3 V to 5.5V ADC supply voltage

—

–0.3

1.32

6

V

8

V_{DD_HV_ADC1_REF}

V_{DD_HV_ADC0}

V_{DD_HV_ADC1}

V_{SS_HV_ADC0}

V_{SS_HV_ADC1}

6.0

3.3V to 5.5V ADC supply ground

—

–0.1

0.1

V

9, 10, 11, 12

V_{DD_LV}

Core logic supply voltage

—

–0.3

1.32

V

V_INA

Voltage on analog pin with respect to

Min (V_{DD_HV_x},

ground (V_{SS_HV}

)

V_{DD_HV_ADCx}

V_{DD_ADCx_REF}

+0.3

,

)

V_IN

Voltage on any digital pin with respect to

ground (V_{SS_HV}

Relative to

–0.3

V_{DD_HV_x}+ 0.3

V

)

V_{DD_HV_A}

V_{DD_HV_B}

,

V_{DD_HV_C}

I_INJPAD

I_INJSUM

T_ramp

Injected input current on any pin during

overload condition

Always

–5

5

mA

Absolute sum of all injected input currents

during overload condition

—

–50

50

Supply ramp rate

—

0.5 V / min

-40

100V/ms

125

—

°C

13

T_A

Ambient temperature

Storage temperature

T_STG

–55

165

1. All voltages are referred to VSS_HV unless otherwise specified

2. VDD_HV_B and VDD_HV_C are common together on the 176 LQFP-EP package.

3. Allowed V_{DD_HV_x}= 5.5–6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in

reset, T_J= 150 °C, remaining time at or below 5.5 V.

4. VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V

5. VDD_HV_FLA must be disconnected from ANY power sources when VDD_HV_A = 5V

6. This pin should be decoupled with low ESR 1 µF capacitor.

7. Not available for input voltage, only for decoupling internal regulators

8. 10-bit ADC does not have dedicated reference and its reference is bonded to 10-bit ADC supply(VDD_HV_ADC0) inside

the package.

9. Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum T_J= 150 °C, remaining time as defined in footnotes 10

and 11.

10. Allowed 1.38 – 1.45 V– for 10 hours cumulative time at maximum T_J= 150 °C, remaining time as defined in footnote 11.

11. 1.32 – 1.38 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.326 V at

maximum T_J= 150 °C.

12. If HVD on core supply (V_{HVD_LV_x}) is enabled, it will generate a reset when supply goes above threshold.

13. T_J=150°C. Assumes T_A=125°C

• Assumes maximum θJA for 2s2p board. See Thermal attributes

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

10

NXP Semiconductors

General

4.2 Recommended operating conditions

The following table describes the operating conditions for the device, and for which all

specifications in the data sheet are valid, except where explicitly noted. The device

operating conditions must not be exceeded in order to guarantee proper operation and

reliability. The ranges in this table are design targets and actual data may vary in the

given range.

NOTE

• For normal device operations, all supplies must be within

operating range corresponding to the range mentioned in

following tables. This is required even if some of the

features are not used.

• If VDD_HV_A is in 5.0V range, VDD_HV_FLA should be

externally supplied using a 3.3V source. If VDD_HV_A is

in 3.3V range, VDD_HV_FLA should be shorted to

VDD_HV_A.

• VDD_HV_A, VDD_HV_B and VDD_HV_C are all

independent supplies and can each be set to 3.3V or 5V.

The following tables: 'Recommended operating conditions

(VDD_HV_x = 3.3 V)' and table 'Recommended operating

conditions (VDD_HV_x = 5 V)' specify their ranges when

configured in 3.3V or 5V respectively.

Table 7. Recommended operating conditions (V_{DD_HV_x}= 3.3 V)

Symbol

V_{DD_HV_A}

V_{DD_HV_B}

V_{DD_HV_C}

V_{DD_HV_FLA}

Parameter

Conditions¹

Min²

Max

Unit

HV IO supply voltage

—

3.15

3.6

V

3

HV flash supply voltage

—

3.15

3.0

3.6

5.5

3.6

V

V_{DD_HV_ADC1_REF}HV ADC1 high reference voltage

V_{DD_HV_ADC0}

V_{DD_HV_ADC1}

HV ADC supply voltage

max(VDD_H

V_A,VDD_H

V_B,VDD_H

V_C) - 0.05

V_{SS_HV_ADC0}

V_{SS_HV_ADC1}

HV ADC supply ground

—

-0.1

0.1

V

4, 5

V_{DD_LV}

Core supply voltage

—

1.2

3.15

-3.0

1.32

3.6

V

6, 7

V_{IN1_CMP_REF}

I_INJPAD

Analog Comparator DAC reference voltage

Injected input current on any pin during

overload condition

3.0

mA

Table continues on the next page...

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

11

General

Table 7. Recommended operating conditions (V_{DD_HV_x}= 3.3 V) (continued)

Symbol

Parameter

Conditions¹

Min²

Max

Unit

8

T_A

Ambient temperature under bias

f_CPU≤ 160

MHz

–40

125

°C

T_J

Junction temperature under bias

—

–40

150

°C

1. All voltages are referred to V_{SS_HV}unless otherwise specified

2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the

point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset.

3. VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V

4. Only applicable when supplying from external source.

5. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be

left floating.

6. VIN1_CMP_REF ≤ VDD_HV_A

7. This supply is shorted VDD_HV_A on lower packages.

8. T_J=150°C. Assumes T_A=125°C

• Assumes maximum θJA of 2s2p board. See Thermal attributes

NOTE

If VDD_HV_A is in 5V range, it is necessary to use internal

Flash supply 3.3V regulator. VDD_HV_FLA should not be

supplied externally and should only have decoupling capacitor.

Table 8. Recommended operating conditions (V_{DD_HV_x}= 5 V)

Symbol

V_{DD_HV_A}

V_{DD_HV_B}

V_{DD_HV_C}

V_{DD_HV_FLA}

Parameter

Conditions ¹

Min²

Max

Unit

HV IO supply voltage

—

4.5

5.5

V

3

HV flash supply voltage

—

3.15

3.6

5.5

V

V_{DD_HV_ADC1_REF}HV ADC1 high reference voltage

V_{DD_HV_ADC0}

HV ADC supply voltage

max(VDD_H

V_A,VDD_H

V_B,VDD_H

V_C) - 0.05

V_{DD_HV_ADC1}

V_{SS_HV_ADC0}

V_{SS_HV_ADC1}

HV ADC supply ground

—

-0.1

0.1

V

4

V_{DD_LV}

Core supply voltage

—

1.2

3.15

-3.0

1.32

5.5⁵

3.0

V

6

V_{IN1_CMP_REF}

Analog Comparator DAC reference voltage

I_INJPAD

Injected input current on any pin during

overload condition

mA

7

T_A

Ambient temperature under bias

f_CPU≤ 160

MHz

–40

125

150

°C

T_J

Junction temperature under bias

—

1. All voltages are referred to V_{SS_HV}unless otherwise specified

2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the

point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset.

3. When VDD_HV is in 5 V range, VDD_HV_FLA cannot be supplied externally.This pin is decoupled with C_{flash_reg}

.

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

12

NXP Semiconductors

General

4. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be

left floating

5. VIN1_CMP_REF ≤ VDD_HV_A

6. This supply is shorted VDD_HV_A on lower packages.

7. T_J=150°C. Assumes T_A=125°C

• Assumes maximum θJA of 2s2p board. See Thermal attributes

4.3 Voltage regulator electrical characteristics

The voltage regulator is composed of the following blocks:

• Choice of generating supply voltage for the core area.

• Control of external NPN ballast transistor

• Generating core supply using internal ballast transistor

• Connecting an external 1.25 V (nominal) supply directly without the NPN ballast

• Internal generation of the 3.3 V flash supply when device connected in 5V

applications

• External bypass of the 3.3 V flash regulator when device connected in 3.3V

applications

• Low voltage detector - low threshold (LVD_IO_A_LO) for V_{DD_HV_IO_A supply}

• Low voltage detector - high threshold (LVD_IO_A_Hi) for V_{DD_HV_IO_A supply}

• Low voltage detector (LVD_FLASH) for 3.3 V flash supply (VDD_HV_FLA)

• Various low voltage detectors (LVD_LV_x)

• High voltage detector (HVD_LV_cold) for 1.2 V digital core supply (VDD_LV)

• Power on Reset (POR_LV) for 1.25 V digital core supply (VDD_LV)

• Power on Reset (POR_HV) for 3.3 V to 5 V supply (VDD_HV_A)

The following bipolar transistors¹are supported, depending on the device performance

requirements. As a minimum the following must be considered when determining the

most appropriate solution to maintain the device under its maximum power dissipation

capability: current, ambient temperature, mounting pad area, duty cycle and frequency for

Idd, collector voltage, etc

1. BCP56, MCP68 and MJD31are guaranteed ballasts.

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

13

General

LPPREG

V_{DD_LP_DEC}

V_{DD_HV_BALLAST}

ULPPREG

C_LP/ULPREG

VRC_CTRL

V_{SS_HV}

FPREG

C

BE_FPREG

Flash

voltage

regulator

VDD_HV_FLA

V

DD_LV

C_{FLASH_REG}

C_{FP_REG}

V_{SS_HV}

DEVICE

Figure 2. Voltage regulator capacitance connection

NOTE

On BGA, VSS_LV and VSS_HV have been joined on substrate

and renamed as VSS.

Table 9. Voltage regulator electrical specifications

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

1

C_{fp_reg}

External decoupling / stability

capacitor

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

1.32

2.2²

3

µF

Combined ESR of external

capacitor

—

0.001

0.8

—

1

0.03

1.4

Ohm

µF

C_{lp/ulp_reg}External decoupling / stability

capacitor for internal low power

regulators

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

Combined ESR of external

capacitor

—

0.001

—

0.1

Ohm

nF

3

C_{be_fpreg}

Capacitor in parallel to base-

emitter

BCP68 and BCP56

MJD31

3.3

4.7

Table continues on the next page...

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

14

NXP Semiconductors

General

Table 9. Voltage regulator electrical specifications (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

4

C_{flash_reg}

External decoupling / stability

capacitor for internal Flash

regulators

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

1.32

2.2

3

µF

Combined ESR of external

capacitor

VDD_HV_A supply capacitor ⁵

—

0.001

—

0.03

—

Ohm

µF

C_{HV_VDD_A}

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

1

C_{HV_VDD_B}

VDD_HV_B supply capacitor⁵

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

1

—

µF

V

C_{HV_VDD_C}VDD_HV_C supply capacitor⁵

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

1

C_{HV_ADC0}HV ADC supply decoupling

capacitances

C_{HV_ADC1}

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

1

—

6

C_{HV_ADR}

HV ADC SAR reference supply

decoupling capacitances

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

0.47

2.25

—

V_{DD_HV_BALL}FPREG Ballast collector supply

When collector of NPN ballast is

directly supplied by an on board

supply source (not shared with

VDD_HV_A supply pin) without

any series resistance, that is,

R_{C_BALLAST}less than 0.01 Ohm.

5.5

7

voltage

AST

R_{C_BALLAST}Series resistor on collector of

FPREG ballast

When VDD_HV_BALLAST is

shorted to VDD_HV_A on the

board

—

74

0.1

—

Ohm

μs

t_SU

Start-up time with external

ballastafter main supply

(VDD_HV_A) stabilization

Cfp_reg = 3 μF

t_{SU_int}

Start-up time with internal ballast Cfp_reg = 3 μF

after main supply (VDD_HV_A)

stabilization

103

1.0

—

μs

t_ramp

Load current transient

Iload from 15% to 55%

C_{fp_reg}= 3 µF

µs

1. Split capacitance on each pair VDD_LV pin should sum up to a total value of C_{fp_reg}

2. Typical values will vary over temperature, voltage, tolerance, drift, but total variation must not exceed minimum and

maximum values.

3. Ceramic X7R or X5R type with capacitance-temperature characteristics +/-15% of -55 degC to +125degC is

recommended. The tolerance +/-20% is acceptable.

4. It is required to minimize the board parasitic inductance from decoupling capacitor to VDD_HV_FLA pin and the routing

inductance should be less than 1nH.

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

15

General

5. 1. For VDD_HV_x, 1µf on each side of the chip

a. 0.1 µf close to each VDD/VSS pin pair.

b. 10 µf near for each power supply source

c. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulation

mode, this amount of capacitance will need to be subtracted from the total capacitance required by the

regulator for e.g., as specified by CFP_REG parameter.

2. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulation mode, this

amount of capacitance will need to be subtracted from the total capacitance required by the regulator for e.g., as

specified by CFP_REG parameter

6. Only applicable to ADC1

7. In external ballast configuration the following must be ensured during power-up and power-down (Note: If V_{DD_HV_BALLAST}

is supplied from the same source as VDD_HV_A this condition is implicitly met):

• During power-up, V_{DD_HV_BALLAST}must have met the min spec of 2.25V before VDD_HV_A reaches the

POR_HV_RISE min of 2.75V.

• During power-down, V_{DD_HV_BALLAST}must not drop below the min spec of 2.25V until VDD_HV_A is below

POR_HV_FALL min of 2.7V.

NOTE

For a typical configuration using an external ballast transistor

with separate supply for VDD_HV_A and the ballast collector,

a bulk storage capacitor (as defined in Table 9) is required on

VDD_HV_A close to the device pins to ensure a stable supply

voltage.

Extra care must be taken if the VDD_HV_A supply is also

being used to power the external ballast transistor or the device

is running in internal regulation mode. In these modes, the

inrush current on device Power Up or on exit from Low Power

Modes is significant and may cause the VDD_HV_A voltage to

drop resulting in an LVD reset event. To avoid this, the board

layout should be optimized to reduce common trace resistance

or additional capacitance at the ballast transistor collector (or

VDD_HV_A pins in the case of internal regulation mode) is

required. NXP recommends that customers simulate the

external voltage supply circuitry.

In all circumstances, the voltage on VDD_HV_A must be

maintained within the specified operating range (see

Recommended operating conditions) to prevent LVD events.

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

16

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General

4.4 Voltage monitor electrical characteristics

Table 10. Voltage monitor electrical characteristics

Symbol

Parameter

State Conditions

Configuration

Threshold

Typ

Unit

V

Power Up

Mask

Opt²

Reset

Type

Min

Max

1

V_{POR_LV}

LV supply power Fall

on reset detector

Untrimmed Yes

Trimmed

No

POR

0.930

0.979

1.028

V

-

Rise Untrimmed

0.980

-

1.029

-

1.078

-

Trimmed

V_{HVD_LV_col}LV supply high

Fall

Untrimmed No

Trimmed

Yes

No

Function Disabled at Start

al

voltage

d

1.325

1.345

1.375

V

monitoring,

detecting at

device pin

Rise Untrimmed

Trimmed

Disabled at Start

1.345 1.365

1.395

V

V_{LVD_LV_PD}LV supply low

Fall

Untrimmed Yes

Trimmed

POR

1.0800 1.1200

1.1250 1.1425

1.1000 1.1400

1.1450 1.1625

1.1600

1.1800

voltage

2_hot

monitoring,

detecting on the

PD2 core (hot)

area

Rise Untrimmed

Trimmed

V_{LVD_LV_PD}LV supply low

Fall

Untrimmed Yes

Trimmed

No

1.0800 1.1200

1.1140 1.1370

1.1000 1.140

1.1340 1.1570

1.1600

1.1800

V

voltage

1_hot (BGFP)

monitoring,

detecting on the

PD1 core (hot)

area

Rise Untrimmed

Trimmed

V_{LVD_LV_PD}LV supply low

Fall

Untrimmed Yes

Trimmed

1.0800 1.1200

1.1140 1.1370

1.1000 1.1400

1.1340 1.1570

1.1600

1.1800

V

voltage

0_hot (BGFP)

monitoring,

detecting on the

PD0 core (hot)

area

Rise Untrimmed

Trimmed

V_{POR_HV}

HV supply power Fall

on reset detector

Untrimmed Yes

Trimmed

No

POR

2.7000 2.8500

3.0000

-

V

-

Rise Untrimmed

2.7500 2.9000

3.0500

-

Trimmed

-

V_{LVD_IO_A_L}HV IO_A supply

Fall

Untrimmed Yes

Trimmed

No

2.7500 2.9230

2.9780 3.0390

2.7800 2.9530

3.0080 3.0690

3.0950

3.1000

3.1250

3.1300

, 3

low voltage

O

monitoring - low

range

Rise Untrimmed

Trimmed

V_{LVD_IO_A_H}HV IO_A supply

Fall

Trimmed

No

Yes

Function Disabled at Start

3

low voltage

monitoring - high

range

al

I

4.0600 4.151

4.2400

4.3000

V

Rise Trimmed

Disabled at Start

4.1150 4.2010

Table continues on the next page...

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

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17

General

Table 10. Voltage monitor electrical characteristics (continued)

Symbol

Parameter

State Conditions

Configuration

Threshold

Typ

Unit

V

Power Up

Mask

Opt²

Reset

Type

Min

Max

1

V_{LVD_LV_PD}LV supply low

Fall

Untrimmed No

Trimmed

Yes

Function Disabled at Start

voltage

al

2_cold

1.1400 1.1550

1.1750

1.1950

V

monitoring,

detecting at the

device pin

Rise Untrimmed

Trimmed

Disabled at Start

1.1600 1.1750

V

1. All monitors that are active at power-up will gate the power up recovery and prevent exit from POWERUP phase until the

minimum level is crossed. These monitors can in some cases be masked during normal device operation, but when active

will always generate a POR reset.

2. Voltage monitors marked as non maskable are essential for device operation and hence cannot be masked.

3. There is no voltage monitoring on the V_{DD_HV_ADC0}, V_{DD_HV_ADC1}, V_{DD_HV_B}and V_{DD_HV_C}I/O segments. For applications

requiring monitoring of these segments, either connect these to V_{DD_HV_A}at the PCB level or monitor externally.

4.5 Supply current characteristics

Current consumption data is given in the following table. These specifications are design

targets and are subject to change per device characterization.

NOTE

The ballast must be chosen in accordance with the ballast

transistor supplier operating conditions and recommendations.

Table 11. Current consumption characteristics

Symbol

I_{DD_BODY_1}

2, 3

Parameter

Conditions¹

Min Typ

Max

Unit

RUN Body Mode Profile Operating

current

LV supply + HV supply + HV

Flash supply +

—

147

mA

2 x HV ADC supplies⁴

T_a= 125°C ^{, 5}

V_{DD_LV}= 1.25 V

VDD_HV_A = 5.5V

SYS_CLK = 80MHz

T_a= 105°C

—

142

137

246

mA

T_a= 85 °C

—

I_{DD_BODY_2}

6

RUN Body Mode Profile Operating

current

LV supply + HV supply + HV

Flash supply + 2 x HV ADC

supplies⁴

—

T_a= 125°C⁵

V_{DD_LV}= 1.25 V

VDD_HV_A = 5.5V

SYS_CLK = 160MHz

Table continues on the next page...

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General

Table 11. Current consumption characteristics (continued)

Symbol

Parameter

Conditions¹

Min Typ

Max

235

210

181

Unit

mA

T_a= 105°C

—

T_a= 85°C

—

I_{DD_BODY_3}

7

RUN Body Mode Profile Operating

current

LV supply + HV supply + HV

Flash supply + 2 x HV ADC

supplies⁴

—

T_a= 125 °C ⁵

V_{DD_LV}= 1.25 V

VDD_HV_A = 5.5V

SYS_CLK = 120MHz

T_a= 105 °C

—

176

171

264

mA

T_a= 85°C

8

I_{DD_BODY_4}

RUN Body Mode Profile Operating

current

LV supply + HV supply + HV

Flash supply + 2 x HV ADC

supplies⁴

—

T_a= 125 °C ⁵

V_{DD_LV}= 1.25 V

VDD_HV_A = 5.5V

SYS_CLK = 120MHz

T_a= 105 °C

—

176

171

49

mA

T_a= 85 °C

T_a= 125 °C⁹

I_{DD_STOP}

STOP mode Operating current

—

V_{DD_LV}= 1.25 V

T_a= 105 °C

—

10.6

8.1

—

V_{DD_LV}= 1.25 V

T_a= 85 °C

V_{DD_LV}= 1.25 V

T_a= 25 °C

4.6

—

V_{DD_LV}= 1.25 V

T_a= 125 °C⁵

10, 11

I_{DD_HV_ADC_REF}

ADC REF Operating current

—

200

400

µA

2 ADCs operating at 80 MHz

V_{DD_HV_ADC_REF}= 5.5 V

T_a= 105 °C

—

200

—

2 ADCs operating at 80 MHz

V_{DD_HV_ADC_REF}= 5.5 V

T_a= 85 °C

2 ADCs operating at 80 MHz

V_{DD_HV_ADC_REF}= 5.5 V

T_a= 25 °C

2 ADCs operating at 80 MHz

Table continues on the next page...

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

19

General

Table 11. Current consumption characteristics (continued)

Symbol

Parameter

Conditions¹

Min Typ

Max

Unit

V_{DD_HV_ADC_REF}= 3.6 V

11

I_{DD_HV_ADCx}

ADC HV Operating current

T_a= 125 °C⁵

—

1.2

2

mA

ADC operating at 80 MHz

V_{DD_HV_ADC}= 5.5 V

T_a= 25 °C

—

1

2

ADC operating at 80 MHz

V_{DD_HV_ADC}= 3.6 V

T_a= 125 °C⁵

12

I_{DD_HV_FLASH}

Flash Operating current during read

access

—

40

45

mA

3.3 V supplies

160 MHz frequency

T_a= 105 °C

—

40

3.3 V supplies

160 MHz frequency

T_a= 85 °C

—

40

3.3 V supplies

160 MHz frequency

1. The content of the Conditions column identifies the components that draw the specific current.

2. Single e200Z4 core cache disabled @80 MHz, no FlexRay, no ENET, 2 x CAN, 8 LINFlexD, 2 SPI, ADC0 and 1 used

constantly, no HSM, Memory: 2M flash, 128K RAM RUN mode, Clocks: FIRC on, XOSC, PLL on, SIRC on for TOD, no

32KHz crystal (TOD runs off SIRC).

3. Recommended Transistors:MJD31 @ 85°C, 105°C and 125°C. In case of internal ballast mode, it is expected that the

external ballast is not mounted and BAL_SELECT_INT pin is tied to VDD_HV_A supply on board. Internal ballast can be

used for all use cases with current consumption upto 150mA. For internal ballast configuration the VRC_CTL pin should be

left floating.

4. The power consumption does not consider the dynamic current of I/Os

5. Tj=150°C. Assumes Ta=125°C

• Assumes maximum θJA of 2s2p board. SeeThermal attributes

6. e200Z4 core, 160MHz, cache enabled; e200Z2 core , 80MHz, no FlexRay, no ENET, 7 CAN, 16 LINFlexD, 4 SPI, 1x ADC

used constantly, includes HSM at start-up / periodic use, Memory: 3M flash, 256K RAM, Clocks: FIRC on, XOSC on, PLL

on, SIRC on, no 32KHz crystal

7. e200Z4 core, 120MHz, cache enabled; e200Z2 core, 60MHz; no FlexRay, no ENET, 7 CAN, 16 LINFlexD, 4 SPI, 1x ADC

used constantly, includes HSM at start-up / periodic use, Memory: 3M flash, 128K RAM, Clocks: FIRC on, XOSC on, PLL

on, SIRC on, no 32KHz crystal

8. e200Z4 core, 160MHz, cache enabled; e200Z4 core, 80MHz; HSM fully operational (Z0 core @80MHz) FlexRay, 5x CAN,

5x LINFlexD, 2x SPI, 1x ADC used constantly, 1xeMIOS (5 ch), Memory: 3M flash, 384K RAM, Clocks: FIRC on, XOSC

on, PLL on, SIRC on, no 32KHz crystal

9. Assuming Ta=Tj, as the device is in Stop mode. Assumes maximum θJA of 2s2p board. SeeThermal attributes.

10. Internal structures hold the input voltage less than V_{DD_HV_ADC_REF}+ 1.0 V on all pads powered by V_DDAsupplies, if the

maximum injection current specification is met (3 mA for all pins) and V_DDAis within the operating voltage specifications.

11. This value is the total current for two ADCs.Each ADC might consume upto 2mA at max.

12. This assumes the default configuration of flash controller register. For more details, refer to Flash memory program and

erase specifications

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

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General

Table 12. Low Power Unit (LPU) Current consumption characteristics

Symbol

Parameter

Conditions¹

Min Typ

Max Unit

LPU_RUN

with 256K RAM

T_a= 25 °C

—

10

10.5

11

—

26

mA

SYS_CLK = 16MHz

ADC0 = OFF, SPI0 = OFF, LIN0 = OFF, CAN0 = OFF

T_a= 85 °C

—

SYS_CLK = 16MHz

ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON

T_a= 105 °C

—

SYS_CLK = 16MHz

ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON

T_a= 125 °C^{, 2}

—

SYS_CLK = 16MHz

ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON

LPU_STOP

with 256K RAM

T_a= 25 °C

T_a= 85 °C

T_a= 105 °C

T_a= 125 °C ²

—

0.18

0.60

1.00

—

mA

—

10.6

1. The content of the Conditions column identifies the components that draw the specific current.

2. Assuming Ta=Tj, as the device is in static (fully clock gated) mode. Assumes maximum θJA of 2s2p board. SeeThermal

attributes

Table 13. STANDBY Current consumption characteristics

Symbol

Parameter

Conditions¹

Min Typ

Max Unit

STANDBY0

STANDBY with

8K RAM

T_a= 25 °C

T_a= 85 °C

T_a= 105 °C

T_a= 125 °C ^{, 2}

T_a= 25 °C

T_a= 85 °C

T_a= 105 °C

T_a= 125 °C ²

T_a= 25 °C

T_a= 85 °C

T_a= 105 °C

T_a= 125 °C ²

T_a= 25 °C

T_a= 85 °C

T_a= 105 °C

T_a= 125 °C ²

T_a= 25 °C

—

71

125

195

314

72

—

700

1225

2100

—

µA

—

STANDBY1

STANDBY2

STANDBY3

STANDBY with

64K RAM

—

140

225

358

75

715

1275

2250

—

STANDBY with

128K RAM

—

155

255

396

80

730

1350

2600

—

STANDBY with

256K RAM

—

180

290

465

500

800

1425

2900

—

STANDBY3

FIRC ON

—

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

21

General

1. The content of the Conditions column identifies the components that draw the specific current.

2. Assuming Ta=Tj, as the device is in static (fully clock gated) mode. Assumes maximum θJA of 2s2p board. SeeThermal

attributes

NOTE

For the Precision channel Analog inputs, SIUL2_MSCRn[PUS]

must be configured to 0 before entering STANDBY. An

increase in current would be observed when

SIUL2_MSCRn[PUS] is configured to be 1, irrespective of the

state of IBE or PUE. The current numbers would increase

irrespective of whether the pad is pulled low/high externally.

4.6 Electrostatic discharge (ESD) characteristics

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This

test conforms to the AEC-Q100-002/-003/-011 standard.

NOTE

A device will be defined as a failure if after exposure to ESD

pulses the device no longer meets the device specification

requirements. Complete DC parametric and functional testing

shall be performed per applicable device specification at room

temperature followed by hot temperature, unless specified

otherwise in the device specification.

Table 14. ESD ratings

Symbol

Parameter

Electrostatic discharge

(Human Body Model)

Conditions¹

Class

Max value²

Unit

V_ESD(HBM)

T_A= 25 °C

H1C

2000

V

conforming to AEC-

Q100-002

V_ESD(CDM)

Electrostatic discharge

(Charged Device Model)

T_A= 25 °C

C3A

500

V

conforming to AEC-

Q100-011

750 (corners)

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2. Data based on characterization results, not tested in production.

4.7 Electromagnetic Compatibility (EMC) specifications

EMC measurements to IC-level IEC standards are available from NXP on request.

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

22

NXP Semiconductors

I/O parameters

5 I/O parameters

5.1 AC specifications @ 3.3 V Range

Table 15. Functional Pad AC Specifications @ 3.3 V Range

Symbol

Prop. Delay (ns)¹

Rise/Fall Edge (ns)

Drive Load

(pF)

SIUL2_MSCRn[SRC 1:0]

L>H/H>L

Min

Max

6/6

Min

Max

1.9/1.5

3.25/3

12/12

3.9/3.5

1.1

MSB,LSB

pad_sr_hv

(output)

25

50

11

2.5/2.5

6.4/5

8.25/7.5

19.5/19.5

8/8

0.8/0.6

3.5/2.5

0.55/0.5

0.035

1/1

200

2.2/2.5

0.090

2.9/3.5

11/8

25

10

1.1

asymmetry²

12.5/11

35/31

45/45

65/65

75/75

100/100

2/2

7/6

50

7.7/5

25/21

25/25

30/30

40/40

51/51

0.5/0.5

200

8.3/9.6

13.5/15

13/13

21/22

4/3.5

50

01

00³

NA

6.3/6.2

6.8/6

200

50

11/11

200

pad_i_hv/

pad_sr_hv

0.5

(input)⁴

1. As measured from 50% of core side input to Voh/Vol of the output

2. This row specifies the min and max asymmetry between both the prop delay and the edge rates for a given PVT and 25pF

load. Required for the Flexray spec.

3. Slew rate control modes

4. Input slope = 2ns

NOTE

The specification given above is based on simulation data into

an ideal lumped capacitor. Customer should use IBIS models

for their specific board/loading conditions to simulate the

expected signal integrity and edge rates of their system.

NOTE

The specification given above is measured between 20% / 80%.

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

23

I/O parameters

5.2 DC electrical specifications @ 3.3V Range

Table 16. DC electrical specifications @ 3.3V Range

Symbol

Parameter

Value

Unit

Min

Max

Vih (pad_i_hv)

Vil (pad_i_hv)

Vhys (pad_i_hv)

Vih_hys

Pad_I_HV Input Buffer High Voltage

Pad_I_HV Input Buffer Low Voltage

Pad_I_HV Input Buffer Hysteresis

0.72*VDD_HV_ VDD_HV_x +

V

x

0.3

VDD_HV_x -

0.3

0.45*VDD_HV_

x

0.11*VDD_HV_

x

CMOS Input Buffer High Voltage (with hysteresis

enabled)

0.67*VDD_HV_ VDD_HV_x +

x

0.3

Vil_hys

CMOS Input Buffer Low Voltage (with hysteresis

enabled)

VDD_HV_x -

0.3

0.35*VDD_HV_

x

Vih

CMOS Input Buffer High Voltage (with hysteresis

disabled)

0.57 *

VDD_HV_x¹+

0.3

VDD_HV_x¹

Vil

CMOS Input Buffer Low Voltage (with hysteresis

disabled)

VDD_HV_x -

0.3

0.4 *

VDD_HV_x¹

Vhys

CMOS Input Buffer Hysteresis

0.09 *

VDD_HV_x¹

Pull_IIH (pad_i_hv) Weak Pullup Current²Low

Pull_IIH (pad_i_hv) Weak Pullup Current³High

Pull_IIL (pad_i_hv) Weak Pulldown Current³Low

Pull_IIL (pad_i_hv) Weak Pulldown Current²High

15

28

µA

V

55

85

50

2.5

—

Pull_Ioh

Pull_Iol

Iinact_d

Voh

Weak Pullup Current⁴

Weak Pulldown Current⁵

15

Digital Pad Input Leakage Current (weak pull inactive)

Output High Voltage⁶

-2.5

0.8

*VDD_HV_x¹

Vol

Output Low Voltage⁷

Output Low Voltage⁸

—

0.2

V

*VDD_HV_x¹

0.1 *VDD_HV_x

Ioh_f

Iol_f

Full drive Ioh⁹(SIUL2_MSCRn.SRC[1:0] = 11)

Full drive Iol⁹(SIUL2_MSCRn.SRC[1:0] = 11)

Half drive Ioh⁹(SIUL2_MSCRn.SRC[1:0] = 10)

Half drive Iol⁹(SIUL2_MSCRn.SRC[1:0] = 10)

18

21

70

120

35

mA

Ioh_h

Iol_h

9

10.5

60

1. VDD_HV_x = VDD_HV_A, VDD_HV_B, VDD_HV_C

2. Measured when pad=0.69*VDD_HV_x

3. Measured when pad=0.49*VDD_HV_x

4. Measured when pad = 0 V

5. Measured when pad = VDD_HV_x

6. Measured when pad is sourcing 2 mA

7. Measured when pad is sinking 2 mA

8. Measured when pad is sinking 1.5 mA

9. Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test.

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

24

NXP Semiconductors

I/O parameters

5.3 AC specifications @ 5 V Range

Table 17. Functional Pad AC Specifications @ 5 V Range

Symbol

Prop. Delay (ns)¹

Rise/Fall Edge (ns)

Drive Load (pF)

SIUL2_MSCRn[SRC 1:0]

L>H/H>L

Min

Max

4.5/4.5

6/6

Min

Max

1.3/1.2

2.5/2

9/9

MSB,LSB

pad_sr_hv

(output)

25

50

11

13/13

5.25/5.25

9/8

200

25

3/2

10

5/4

50

22/22

27/27

40/40

65/65

1.5/1.5

18/16

13/13

24/24

40/40

0.5/0.5

200

50

01²

00²

NA

200

50

200

0.5

pad_i_hv/

pad_sr_hv

(input)

1. As measured from 50% of core side input to Voh/Vol of the output

2. Slew rate control modes

NOTE

The above specification is based on simulation data into an

ideal lumped capacitor. Customer should use IBIS models for

their specific board/loading conditions to simulate the expected

signal integrity and edge rates of their system.

NOTE

The above specification is measured between 20% / 80%.

5.4 DC electrical specifications @ 5 V Range

Table 18. DC electrical specifications @ 5 V Range

Symbol

Parameter

Value

Unit

Min

Max

Vih (pad_i_hv)

pad_i_hv Input Buffer High Voltage

0.7*VDD_HV_x VDD_HV_x +

0.3

V

Table continues on the next page...

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

25

I/O parameters

Symbol

Table 18. DC electrical specifications @ 5 V Range (continued)

Parameter

Value

Unit

Min

Max

Vil (pad_i_hv)

Vhys (pad_i_hv)

Vih_hys

Vil_hys

pad_i_hv Input Buffer Low Voltage

pad_i_hv Input Buffer Hysteresis

VDD_HV_x -

0.3

0.45*VDD_HV_

x

V

0.09*VDD_HV_

x

CMOS Input Buffer High Voltage (with hysteresis

enabled)

0.65*

VDD_HV_x

VDD_HV_x +

0.3

CMOS Input Buffer Low Voltage (with hysteresis

enabled)

VDD_HV_x -

0.3

0.35*VDD_HV_

x

VDD_HV_x¹+

0.3

Vih

CMOS Input Buffer High Voltage (with hysteresis

disabled)

0.55 *

VDD_HV_x¹

Vil

CMOS Input Buffer Low Voltage (with hysteresis

disabled)

VDD_HV_x -

0.3

0.40 *

VDD_HV_x¹

Vhys

CMOS Input Buffer Hysteresis

0.09 *

VDD_HV_x¹

Pull_IIH (pad_i_hv) Weak Pullup Current²Low

Pull_IIH (pad_i_hv) Weak Pullup Current³High

Pull_IIL (pad_i_hv) Weak Pulldown Current³Low

Pull_IIL (pad_i_hv) Weak Pulldown Current²High

23

40

µA

V

82

130

80

Pull_Ioh

Pull_Iol

Iinact_d

Voh

Weak Pullup Current⁴

Weak Pulldown Current⁵

30

80

Digital Pad Input Leakage Current (weak pull inactive)

Output High Voltage⁶

-2.5

2.5

—

0.8 *

VDD_HV_x¹

Vol

Output Low Voltage⁷

—

0.2*VDD_HV_x

V

Output Low Voltage⁸

0.1*VDD_HV_x

Ioh_f

Iol_f

Full drive Ioh⁹(SIUL2_MSCRn.SRC[1:0] = 11)

Full drive Iol⁹(SIUL2_MSCRn.SRC[1:0] = 11)

Half drive Ioh⁹(SIUL2_MSCRn.SRC[1:0] = 10)

Half drive Iol⁹(SIUL2_MSCRn.SRC[1:0] = 10)

18

21

70

120

35

mA

Ioh_h

Iol_h

9

10.5

60

1. VDD_HV_x = VDD_HV_A, VDD_HV_B, VDD_HV_C

2. Measured when pad=0.69*VDD_HV_x

3. Measured when pad=0.49*VDD_HV_x

4. Measured when pad = 0 V

5. Measured when pad = VDD_HV_x

6. Measured when pad is sourcing 2 mA

7. Measured when pad is sinking 2 mA

8. Measured when pad is sinking 1.5 mA

9. Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test.

5.5 Reset pad electrical characteristics

The device implements a dedicated bidirectional RESET pin.

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

26

NXP Semiconductors

I/O parameters

V

DD_HV_IOx

A

V

DDMIN

PORST

V

IH

V

IL

device reset forced by PORST

device start-up phase

Figure 3. Start-up reset requirements

V_PORST

hw_rst

‘1’

V

DD_HV_IO

A

V

IH

V

IL

‘0’

filtered by

lowpass filter

unknown reset

state

filtered by

hysteresis

filtered by

lowpass filter

device under hardware reset

W

FRST

W

NFRST

Figure 4. Noise filtering on reset signal

Table 19. Functional reset pad electrical specifications

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

V_IH

CMOS Input Buffer High Voltage

CMOS Input Buffer Low Voltage

—

0.65*V_D

—

V_{DD_HV_x}

+0.3

V

D_HV_x

V_IL

V_{DD_HV_}

_x-0.3

—

0.35*V_{DD_HV}V

_x

Table continues on the next page...

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

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27

Peripheral operating requirements and behaviours

Table 19. Functional reset pad electrical specifications (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

300

Typ

Max

—

V_HYS

V_{DD_POR}

CMOS Input Buffer hysterisis

—

mV

V

Minimum supply for strong pull-down

activation

—

1.2

I_{OL_R}

Strong pull-down current ¹

Device under power-on reset

V_{DD_HV_IO}= V _{DD_POR}

V_OL= 0.35*V_{DD_HV_IO}

Device under power-on reset

3.0 V < V_{DD_HV_IO}< 5.5 V

V_OL= 0.35*V_{DD_HV_IO}

—

0.2

—

mA

11

—

mA

W_FRST

RESET input filtered pulse

—

500

—

ns

µA

W_NFRST

RESET input not filtered pulse

Weak pull-up current absolute value

—

2000

23

|I_WPU

|

RESET pin V_IN= V_DD

82

1. Strong pull-down is active on PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for RESET.

5.6 PORST electrical specifications

Table 20. PORST electrical specifications

Symbol

Parameter

Value

Unit

Min

—

Typ

Max

W_FPORST

W_NFPORST

V_IH

PORST input filtered pulse

PORST input not filtered pulse

Input high level

—

200

—

ns

1000

ns

V

0.65 x

—

V_{DD_HV_A}

V_IL

Input low level

—

0.35 x

V

V_{DD_HV_A}

6 Peripheral operating requirements and behaviours

6.1 Analog

6.1.1 ADC electrical specifications

The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-

Digital Converter.

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Analog

Offset Error OSE Gain Error GE

4095

4094

4093

4092

4091

4090

(2)

1 LSB ideal =(VrefH-VrefL)/ 4096 =

3.3V/ 4096 = 0.806 mV

Total Unadjusted Error

TUE = +/- 6 LSB = +/- 4.84mV

code out₇

(1)

6

5

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer

curve

(5)

4

3

(4)

(3)

2

1

1 LSB (ideal)

0

1

2

3

4

5

6

7

4089 4090 4091 4092 4093 4094 4095

V_in(A)(LSB_ideal

)

Offset Error OSE

Figure 5. ADC characteristics and error definitions

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

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29

Analog

6.1.1.1 Input equivalent circuit and ADC conversion characteristics

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

V

DD_IO

Channel

Sampling

Selection

Source

Filter

Current Limiter

R

S

F

L

SW1

AD

C

V

C

P1

C

S

A

F

P2

R

Source Impedance

Filter Resistance

Filter Capacitance

Current Limiter Resistance

Channel Selection Switch Impedance

Sampling Switch Impedance

S

F

L

R

C

R

C

SW1

AD

P

Pin Capacitance (two contributions, C and C

Sampling Capacitance

)

P1

P2

S

Figure 6. Input equivalent circuit

NOTE

The ADC performance specifications are not guaranteed if two

ADCs simultaneously sample the same shared channel.

Table 21. ADC conversion characteristics (for 12-bit)

Symbol

Parameter

Conditions

Min

Typ¹

Max

Unit

f_CK

ADC Clock frequency (depends on —

ADC configuration) (The duty cycle

depends on AD_CK²frequency)

15.2

80

MHz

f_s

Sampling frequency

Sample time³

80 MHz

—

1.00

—

MHz

ns

t_sample

80 MHz@ 100 ohm source

impedance

250

t_conv

Conversion time⁴

80 MHz

700

1.5⁵

—

ns

µs

t_{total_conv}

Total Conversion time t_sample+

t_conv(for standard and extended

channels)

Total Conversion time t_sample

t_conv(for precision channels)

+

1

—

, 6

C_S

ADC input sampling capacitance

ADC input pin capacitance 1

ADC input pin capacitance 2

—

3

5

pF

kΩ

Ω

6

C_P1

—

6

C_P2

—

0.8

0.3

875

6

R_SW1

Internal resistance of analog

source

V_REFrange = 4.5 to 5.5 V

V_REFrange = 3.15 to 3.6 V

Table continues on the next page...

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Analog

Table 21. ADC conversion characteristics (for 12-bit) (continued)

Symbol

Parameter

Conditions

Min

Typ¹

Max

Unit

6

R_AD

Internal resistance of analog

source

—

825

Ω

INL

Integral non-linearity (precise

channel)

–2

–3

—

2

3

LSB

Integral non-linearity (standard

channel)

DNL

OFS

GNE

Differential non-linearity

Offset error

—

–1

–6

–4

—

1

6

LSB

nA

—

Gain error

—

4

ADC Analog Pad Max leakage (precision channel)

(pad going to one

150 °C

—

250

2500

250

5

Max leakage (standard channel)

—

nA

ADC)

Max leakage (standard channel)

105 °C _TA

5

nA

Max positive/negative injection

–5

–6

—

mA

LSB

µs

TUE_{precision channels}Total unadjusted error for precision Without current injection

+/-4

+/-5

+/-6

+/-8

6

channels

With current injection⁷

TUE_{standard/extended}Total unadjusted error for standard/ Without current injection

–8

8

extended channels

With current injection⁷

channels

t_recovery

STOP mode to Run mode recovery

time

< 1

1. Active ADC input, VinA < [min(ADC_VrefH, ADC_ADV, VDD_HV_IOx)]. VDD_HV_IOx refers to I/O segment supply

voltage. Violation of this condition would lead to degradation of ADC performance. Please refer to Table: 'Absolute

maximum ratings' to avoid damage. Refer to Table: 'Recommended operating conditions (VDD_HV_x = 3.3 V)' for required

relation between IO_supply_A,B,C and ADC_Supply.

2. The internally generated clock (known as AD_clk or ADCK) could be same as the peripheral clock or half of the peripheral

clock based on register configuration in the ADC.

3. During the sample time the input capacitance C_Scan be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within t_sample. After the end of the

sample time t_sample, changes of the analog input voltage have no effect on the conversion result. Values for the sample

clock t_sampledepend on programming.

4. This parameter does not include the sample time t_sample, but only the time for determining the digital result and the time to

load the result register with the conversion result.

5. Apart from tsample and tconv, few cycles are used up in ADC digital interface and hence the overall throughput from the

ADC is lower.

6. See Figure 2.

7. Current injection condition for ADC channels is defined for an inactive ADC channel (on which conversion is NOT being

performed), and this occurs when voltage on the ADC pin exceeds the I/O supply or ground. However, absolute maximum

voltage spec on pad input (VINA, see Table: Absolute maximum ratings) must be honored to meet TUE spec quoted here

Table 22. ADC conversion characteristics (for 10-bit)

Symbol

Parameter

Conditions

Min

Typ¹

Max

Unit

f_CK

ADC Clock frequency (depends on

ADC configuration) (The duty cycle

depends on AD_CK²frequency.)

—

15.2

80

MHz

f_s

Sampling frequency

Sample time³

—

1.00

—

MHz

ns

t_sample

80 MHz@ 100 ohm source

impedance

275

Table continues on the next page...

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31

Analog

Table 22. ADC conversion characteristics (for 10-bit) (continued)

Symbol

Parameter

Conversion time⁴

Conditions

80 MHz

Min

550

1

Typ¹

Max

—

Unit

ns

t_conv

—

t_{total_conv}

Total Conversion time tsample +

tconv (for standard channels)

80 MHz

—

µs

Total Conversion time tsample +

tconv (for extended channels)

1.5

—

C_S

ADC input sampling capacitance

ADC input pin capacitance 1

ADC input pin capacitance 2

—

3

5

pF

kΩ

Ω

5

C_P1

—

5

C_P2

—

0.8

0.3

875

825

5

R_SW1

Internal resistance of analog

source

V_REFrange = 4.5 to 5.5 V

V_REFrange = 3.15 to 3.6 V

—

5

R_AD

Internal resistance of analog

source

Ω

INL

DNL

OFS

GNE

Integral non-linearity

Differential non-linearity

Offset error

—

–2

–1

–4

—

–5

—

–4

—

2

1

LSB

nA

—

4

Gain error

—

4

ADC Analog Pad Max leakage (standard channel)

(pad going to one

150 °C

—

2500

5

Max positive/negative injection

—

mA

nA

ADC)

Max leakage (standard channel)

105 °C _TA

5

250

4

TUE_{standard/extended}Total unadjusted error for standard Without current injection

+/-3

+/-4

LSB

µs

channels

With current injection⁶

channels

t_recovery

STOP mode to Run mode recovery

time

< 1

1. Active ADC Input, VinA < [min(ADC_ADV, IO_Supply_A,B,C)]. Violation of this condition would lead to degradation of ADC

performance. Please refer to Table: 'Absolute maximum ratings' to avoid damage. Refer to Table: 'Recommended

operating conditions' for required relation between IO_supply_A, B, C and ADC_Supply.

2. The internally generated clock (known as AD_clk or ADCK) could be same as the peripheral clock or half of the peripheral

clock based on register configuration in the ADC.

3. During the sample time the input capacitance C_Scan be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within t_sample. After the end of the

sample time t_sample, changes of the analog input voltage have no effect on the conversion result. Values for the sample

clock t_sampledepend on programming.

4. This parameter does not include the sample time t_sample, but only the time for determining the digital result and the time to

load the result register with the conversion result.

5. See Figure 2-1

6. Current injection condition for ADC channels is defined for an inactive ADC channel (on which conversion is NOT being

performed), and this occurs when voltage on the ADC pin exceeds the I/O supply or ground. However, absolute maximum

voltage spec on pad input (VINA, see Table: Absolute maximum ratings) must be honored to meet TUE spec quoted here

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Analog

6.1.2 Analog Comparator (CMP) electrical specifications

Table 23. Comparator and 6-bit DAC electrical specifications

Symbol

I_DDHS

I_DDLS

Description

Min.

—

Typ.

—

Max.

250

11

Unit

Supply current, High-speed mode (EN=1, PMODE=1)

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

μA

V

—

5

V_AIN

V_SS

—

V_{IN1_CMP_RE}

F

V_AIO

V_H

Analog input offset voltage ¹

Analog comparator hysteresis ²

• CR0[HYSTCTR] = 00

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

-47

—

47

mV

—

1

25

50

mV

20

40

60

70

105

t_DHS

t_DLS

Propagation Delay, High Speed Mode (Full Swing) ^{1, 3}

Propagation Delay, Low power Mode (Full Swing) ^{1, 3}

—

5

250

21

ns

μs

Analog comparator initialization delay, High speed

mode⁴

4

Analog comparator initialization delay, Low speed

mode ⁴

—

100

μs

I_DAC6b

6-bit DAC current adder (when enabled)

3.3V Reference Voltage

—

6

9

μA

LSB⁵

5V Reference Voltage

10

—

16

0.5

0.8

INL

6-bit DAC integral non-linearity

6-bit DAC differential non-linearity

–0.5

–0.8

DNL

LSB

1. Measured with hysteresis mode of 00

2. Typical hysteresis is measured with input voltage range limited to 0.6 to V_{DD_HV_A}-0.6V

3. Full swing = VIH, VIL

4. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,

VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.

5. 1 LSB = V_reference/64

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33

Clocks and PLL interfaces modules

6.2 Clocks and PLL interfaces modules

6.2.1 Main oscillator electrical characteristics

This device provides a driver for oscillator in pierce configuration with amplitude

control. Controlling the amplitude allows a more sinusoidal oscillation, reducing in this

way the EMI. Other benefits arises by reducing the power consumption. This Loop

Controlled Pierce (LCP mode) requires good practices to reduce the stray capacitance of

traces between crystal and MCU.

An operation in Full Swing Pierce (FSP mode), implemented by an inverter is also

available in case of parasitic capacitances and cannot be reduced by using crystal with

high equivalent series resistance. For this mode, a special care needs to be taken

regarding the serial resistance used to avoid the crystal overdrive.

Other two modes called External (EXT Wave) and disable (OFF mode) are provided. For

EXT Wave, the drive is disabled and an external source of clock within CMOS level

based in analog oscillator supply can be used. When OFF, EXTAL is pulled down by 240

Kohms resistor and the feedback resistor remains active connecting XTAL through

EXTAL by 1M resistor.

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

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NXP Semiconductors

Clocks and PLL interfaces modules

Figure 7. Oscillator connections scheme

Table 24. Main oscillator electrical characteristics

Symbol

f_XOSCHS

Parameter

Mode

Conditions

Min

Typ

Max

Unit

Oscillator

frequency

FSP/LCP

8

40

MHz

g_mXOSCHS

Driver

Transconduct

ance

LCP

FSP

23

33

mA/V

V_XOSCHS

Oscillation

Amplitude

LCP^{1, 2}

FSP/LCP¹

FSP

8 MHz

1.0

0.8

2

V_PP

ms

16 MHz

40 MHz

8 MHz

T_XOSCHSSU

Startup time

16 MHz

40 MHz

8 MHz

1

0.5

2.2

Oscillator

Analog Circuit

supply current

mA

16 MHz

Table continues on the next page...

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

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35

Clocks and PLL interfaces modules

Table 24. Main oscillator electrical characteristics (continued)

Symbol

Parameter

Mode

Conditions

40 MHz

Min

Typ

Max

Unit

3.2

LCP

8 MHz

141

252

518

uA

16 MHz

40 MHz

V_IH

V_IL

Input High

level CMOS

Schmitt trigger

EXT Wave

Oscillator

supply=3.3

1.95

V

Input low level EXT Wave

CMOS

Oscillator

supply=3.3

1.25

Schmitt trigger

1. Values are very dependent on crystal or resonator used and parasitic capacitance observed in the board.

2. Typ value for oscillator supply 3.3 V@27 °C

6.2.2 32 kHz Oscillator electrical specifications

Table 25. 32 kHz oscillator electrical specifications

Symbol

f_{osc_lo}

Parameter

Condition

Min

Typ

Max

Unit

Oscillator crystal

or resonator

frequency

32

40

2

KHz

t_cst

Crystal Start-up

Time^{1, 2}

s

1. This parameter is characterized before qualification rather than 100% tested.

2. Proper PC board layout procedures must be followed to achieve specifications.

6.2.3 16 MHz RC Oscillator electrical specifications

Table 26. 16 MHz RC Oscillator electrical specifications

Symbol

Parameter

Conditions

Value

Typ

16

Unit

Min

—

Max

F_Target

PTA

IRC target frequency

—

5

MHz

%

IRC frequency variation after trimming

Startup time

-5

—

T_startup

T_STJIT

T_LTJIT

—

1.5

0.2

us

%

Cycle to cycle jitter

—

Long term jitter

—

%

NOTE

The above start up time of 1 us is equivalent to 16 cycles of 16

MHz.

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NXP Semiconductors

Clocks and PLL interfaces modules

6.2.4 128 KHz Internal RC oscillator Electrical specifications

Table 27. 128 KHz Internal RC oscillator electrical specifications

Symbol

Parameter

Condition

Calibrated

Min

Typ

Max

Unit

1

F_oscu

Oscillator

frequency

119

128

136.5

600

18

KHz

Temperature

dependence

ppm/C

%/V

Supply

dependence

Supply current

Clock running

Clock stopped

2.75

200

µA

nA

1. Vdd=1.2 V, 1.32V, T_a=-40 C, 125 C

6.2.5 PLL electrical specifications

Table 28. PLL electrical specifications

Parameter

Input Frequency

Min

Typ

Max

Unit

MHz

Comments

8

40

VCO Frequency Range

Duty Cycle at pllclkout

600

48%

1280

52%

MHz

This specification is guaranteed

at PLL IP boundary

Period Jitter

TIE

See Table 29

ps

NON SSCG mode

at 960 M Integrated over 1MHz

offset not valid in SSCG mode

Modulation Depth (Center Spread) +/- 0.25%

Modulation Frequency

+/- 3.0%

32

KHz

µs

Lock Time

60

Calibration mode

Table 29. Jitter calculation

Type of jitter

Jitter due to

Supply

Jitter due to

Fractional Mode

J_SSCG(ps) ³

1 Sigma

Total Period Jitter (ps)

Fractional Mode

Random

Jitter J_RJ

(ps) ⁴

2

Noise (ps)

(ps) J_SDM

1

J_SN

Period Jitter

60 ps

3% of pllclkout1,2

Modulation depth

0.1% of

+/-(J_SN+J_SDM+J_SSCG+N^[4]

pllclkout1,2

×J_RJ)

Long Term Jitter

(Integer Mode)

40

+/-(N x J_RJ

)

Long Term jitter

100

+/-(N x J_RJ

(Fractional Mode)

1. This jitter component is due to self noise generated due to bond wire inductances on different PLL supplies. The jitter value

is valid for inductor value of 5nH or less each on VDD_LV and VSS_LV.

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Memory interfaces

2. This jitter component is added when the PLL is working in the fractional mode.

3. This jitter component is added when the PLL is working in the Spread Spectrum Mode. Else it is 0.

4. The value of N is dependent on the accuracy requirement of the application. See Percentage of sample exceeding

specified value of jitter table

Table 30. Percentage of sample exceeding specified value of jitter

N

Percentage of samples exceeding specified value of jitter

(%)

1

2

3

4

5

6

7

31.73

4.55

0.27

6.30 × 1e-03

5.63 × 1e-05

2.00 × 1e-07

2.82 × 1e-10

6.3 Memory interfaces

6.3.1 Flash memory program and erase specifications

NOTE

All timing, voltage, and current numbers specified in this

section are defined for a single embedded flash memory within

an SoC, and represent average currents for given supplies and

operations.

Table 31 shows the estimated Program/Erase times.

Table 31. Flash memory program and erase specifications

Symbol

Characteristic¹

Typ²

Factory

Field Update

Unit

Programming^{3, 4}

Initial

Max

Initial

Max, Full

Temp

Typical

End of

Life⁵

Lifetime Max⁶

20°C ≤T_A-40°C ≤T_J-40°C ≤T_J≤ 1,000 ≤ 250,000

≤30°C ≤150°C ≤150°C cycles cycles

t_dwpgm

Doubleword (64 bits) program time 43

100 150 55 500

μs

t_ppgm

Page (256 bits) program time

73

200

800

300

108

396

500

μs

t_qppgm

Quad-page (1024 bits) program

time

268

1,200

2,000

t_16kers

16 KB Block erase time

168

34

290

45

320

50

250

40

1,000

ms

t_16kpgm

16 KB Block program time

Table continues on the next page...

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Memory interfaces

Table 31. Flash memory program and erase specifications (continued)

Symbol

Characteristic¹

Typ²

Factory

Field Update

Unit

Programming^{3, 4}

Initial

Max

Initial

Max, Full

Temp

Typical

End of

Life⁵

Lifetime Max⁶

20°C ≤T_A-40°C ≤T_J-40°C ≤T_J≤ 1,000 ≤ 250,000

≤30°C

≤150°C

cycles

1,200

1,600

4,000

cycles

t_32kers

t_32kpgm

t_64kers

32 KB Block erase time

32 KB Block program time

64 KB Block erase time

64 KB Block program time

256 KB Block erase time

256 KB Block program time

217

360

390

310

ms

69

100

110

90

315

138

884

552

490

590

420

170

1,080

650

t_64kpgm

t_256kers

t_256kpgm

180

210

1,520

720

2,030

880

—

1. Program times are actual hardware programming times and do not include software overhead. Block program times

assume quad-page programming.

2. Typical program and erase times represent the median performance and assume nominal supply values and operation at

25 °C. Typical program and erase times may be used for throughput calculations.

3. Conditions: ≤ 150 cycles, nominal voltage.

4. Plant Programing times provide guidance for timeout limits used in the factory.

5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations.

6. Conditions: -40°C ≤ T_J≤ 150°C, full spec voltage.

6.3.2 Flash memory Array Integrity and Margin Read specifications

Table 32. Flash memory Array Integrity and Margin Read specifications

Symbol

Characteristic

Min

Typical

Max¹

Units

2

t_ai16kseq

Array Integrity time for sequential sequence on 16 KB block.

—

512 x

Tperiod x

Nread

—

t_ai32kseq

Array Integrity time for sequential sequence on 32 KB block.

Array Integrity time for sequential sequence on 64 KB block.

Array Integrity time for sequential sequence on 256 KB block.

—

1024 x

Tperiod x

Nread

t_ai64kseq

2048 x

Tperiod x

Nread

8192 x

Tperiod x

Nread

tai256kseq

t_mr16kseq

t_mr32kseq

t_mr64kseq

t_mr256kseq

Margin Read time for sequential sequence on 16 KB block.

Margin Read time for sequential sequence on 32 KB block.

Margin Read time for sequential sequence on 64 KB block.

Margin Read time for sequential sequence on 256 KB block.

73.81

128.43

237.65

893.01

—

110.7

192.6

μs

356.5

1,339.5

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

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39

Memory interfaces

1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The

equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and

Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires

6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the

address pipeline set to 2, Nread would equal 4 (or 6 - 2).)

2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the

equation, the results of the equation are also unit accurate.

6.3.3 Flash memory module life specifications

Table 33. Flash memory module life specifications

Symbol

Characteristic

Conditions

Min

Typical

Units

P/E

Array P/E

cycles

Number of program/erase cycles per block

for 16 KB, 32 KB and 64 KB blocks.¹

—

250,000

—

cycles

Number of program/erase cycles per block

for 256 KB blocks.²

1,000

250,000

P/E

cycles

Data

retention

Minimum data retention.

Blocks with 0 - 1,000 P/E 50

cycles.

—

Years

Blocks with 100,000 P/E

cycles.

20

Blocks with 250,000 P/E

cycles.

10

1. Program and erase supported across standard temperature specs.

2. Program and erase supported across standard temperature specs.

6.3.4 Data retention vs program/erase cycles

Graphically, Data Retention versus Program/Erase Cycles can be represented by the

following figure. The spec window represents qualified limits. The extrapolated dotted

line demonstrates technology capability, however is beyond the qualification limits.

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Memory interfaces

6.3.5 Flash memory AC timing specifications

Table 34. Flash memory AC timing specifications

Symbol

Characteristic

Min

Typical

Max

Units

t_psus

Time from setting the MCR-PSUS bit until MCR-DONE bit is set

to a 1.

—

9.4

11.5

μs

plus four

system

clock

plus four

system

clock

periods

t_esus

Time from setting the MCR-ESUS bit until MCR-DONE bit is set

to a 1.

—

16

20.8

μs

plus four

system

clock

plus four

system

clock

periods

t_res

Time from clearing the MCR-ESUS or PSUS bit with EHV = 1

until DONE goes low.

—

16

100

ns

μs

t_done

t_dones

Time from 0 to 1 transition on the MCR-EHV bit initiating a

program/erase until the MCR-DONE bit is cleared.

5

Time from 1 to 0 transition on the MCR-EHV bit aborting a

program/erase until the MCR-DONE bit is set to a 1.

20.8

plus four

system

clock

plus four

system

clock

periods

t_drcv

Time to recover once exiting low power mode.

16

—

45

μs

Table continues on the next page...

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Memory interfaces

Table 34. Flash memory AC timing specifications (continued)

Symbol

Characteristic

Min

Typical

Max

Units

plus seven

system

clock

plus seven

system

clock

periods.

periods

t_aistart

Time from 0 to 1 transition of UT0-AIE initiating a Margin Read

or Array Integrity until the UT0-AID bit is cleared. This time also

applies to the resuming from a suspend or breakpoint by

clearing AISUS or clearing NAIBP

—

5

ns

t_aistop

Time from 1 to 0 transition of UT0-AIE initiating an Array

Integrity abort until the UT0-AID bit is set. This time also applies

to the UT0-AISUS to UT0-AID setting in the event of a Array

Integrity suspend request.

—

80

plus fifteen

system

clock

periods

t_mrstop

Time from 1 to 0 transition of UT0-AIE initiating a Margin Read

abort until the UT0-AID bit is set. This time also applies to the

UT0-AISUS to UT0-AID setting in the event of a Margin Read

suspend request.

10.36

—

20.42

μs

plus four

system

clock

plus four

system

clock

periods

6.3.6 Flash read wait state and address pipeline control settings

The following table describes the recommended RWSC and APC settings at various

operating frequencies based on specified intrinsic flash access times of the flash module

controller array at 125 °C.

Table 35. Flash Read Wait State and Address Pipeline Control Combinations

Flash frequency

0 MHz < fFlash <= 33 MHz

33 MHz < fFlash <= 100 MHz

100 MHz < fFlash <= 133 MHz

133 MHz < fFlash <= 160 MHz

RWSC setting

APC setting

0

2

3

4

0

1

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Communication interfaces

6.4 Communication interfaces

6.4.1 DSPI timing

Table 36. DSPI electrical specifications

No

Symbol

Parameter

Conditions

High Speed Mode¹

low Speed mode

Unit

Min

25

Max

—

Min

50

Max

—

1

t_SCK

DSPI cycle

time

Master

Slave (MTFE = 0)

—

ns

40

—

60

—

2

3

4

5

6

7

8

9

t_CSC

t_ASC

t_SDC

t_A

PCS to SCK

delay

16

—

ns

After SCK

delay

—

16

—

SCK duty

cycle

t_SCK/2 - 10

t_SCK/2 + 10

Slave access SS active to SOUT

time valid

—

13

40

10

—

t_DIS

Slave SOUT _SSinactive to SOUT

disable time

High-Z or invalid

t_PCSC

t_PASC

t_SUI

PCSx to

PCSS time

—

PCSS to

PCSx time

—

Data setup

time for

inputs

Master (MTFE = 0)

Slave

NA

2

—

20

2

8²

—

Master (MTFE = 1,

CPHA = 0)

15

Master (MTFE = 1,

CPHA = 1)

15

—

20

—

10

11

12

t_HI

t_SUO

t_HO

Data hold

time for

inputs

Master (MTFE = 0)

Slave

NA

4

—

–5

4

11²

—

ns

Master (MTFE = 1,

CPHA = 0)

0

Master (MTFE = 1,

CPHA = 1)

0

—

-5

—

Data valid

(after SCK

edge)

Master (MTFE = 0)

Slave

—

NA

15

4

—

4

23

16²

Master (MTFE = 1,

CPHA = 0)

Master (MTFE = 1,

CPHA = 1)

—

4

—

4

Data hold

time for

outputs

Master (MTFE = 0)

NA

—

–2

—

Table continues on the next page...

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Communication interfaces

Table 36. DSPI electrical specifications (continued)

No

Symbol

Parameter

Conditions

High Speed Mode¹

low Speed mode

Unit

Min

4

Max

—

Min

Max

—

Slave

6

Master (MTFE = 1,

CPHA = 0)

-2

—

10²

—

Master (MTFE = 1,

CPHA = 1)

–2

—

–2

—

1. Only one {SIN,SOUT and SCK} group per DSPI/SPI will support high frequency mode. See Table 3.

2. SMPL_PTR should be set to 1

NOTE

Restriction For High Speed modes

• DSPI2, DSPI3, SPI1 and SPI2 will support 40MHz Master

mode SCK

• DSPI2, DSPI3, SPI1 and SPI2 will support 25MHz Slave

SCK frequency

• Only one {SIN,SOUT and SCK} group per DSPI/SPI will

support high frequency mode. See Table 38.

• For Master mode MTFE will be 1 for high speed mode

• For high speed slaves, their master have to be in MTFE=1

mode or should be able to support 15ns tSUO delay

NOTE

For numbers shown in the following figures, see Table 36

Table 37. Continuous SCK timing

Spec

Characteristics

Pad Drive/Load

Value

Min

100 ns

-

Max

tSCK

SCK cycle timing

PCS valid after SCK

strong/50 pF

-

15 ns

-

-4 ns

Table 38. DSPI high speed mode I/Os

DSPI

High speed SCK

GPIO[78]

High speed SIN

GPIO[76]

High speed SOUT

GPIO[77]

DSPI2

DSPI3

SPI1

GPIO[100]

GPIO[173]

GPIO[79]

GPIO[101]

GPIO[175]

GPIO[110]

GPIO[98]

GPIO[176]

GPIO[111]

SPI2

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Communication interfaces

2

3

PCSx

1

4

SCK Output

(CPOL=0)

4

SCK Output

(CPOL=1)

10

9

Last Data

SIN

First Data

Data

12

11

First Data

Last Data

SOUT

Figure 8. DSPI classic SPI timing — master, CPHA = 0

PCSx

SCK Output

(CPOL=0)

10

SCK Output

(CPOL=1)

9

Data

First Data

Last Data

SIN

12

11

SOUT

Last Data

First Data

Figure 9. DSPI classic SPI timing — master, CPHA = 1

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Communication interfaces

3

2

SS

1

4

SCK Input

(CPOL=0)

4

SCK Input

(CPOL=1)

5

11

12

Data

6

First Data

Last Data

SOUT

SIN

9

10

Data

Last Data

First Data

Figure 10. DSPI classic SPI timing — slave, CPHA = 0

SS

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

11

5

6

12

Last Data

Data

SOUT

SIN

First Data

10

9

Last Data

First Data

Figure 11. DSPI classic SPI timing — slave, CPHA = 1

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

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NXP Semiconductors

Communication interfaces

3

PCSx

4

1

2

SCK Output

(CPOL=0)

4

SCK Output

(CPOL=1)

9

10

SIN

First Data

12

Last Data

Data

11

SOUT

First Data

Data

Figure 12. DSPI modified transfer format timing — master, CPHA = 0

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

10

9

SIN

Last Data

First Data

Data

12

Data

11

First Data

Last Data

SOUT

Figure 13. DSPI modified transfer format timing — master, CPHA = 1

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Communication interfaces

3

2

SS

1

SCK Input

(CPOL=0)

4

SCK Input

(CPOL=1)

12

11

6

5

First Data

9

Data

Last Data

10

SOUT

SIN

Last Data

First Data

Figure 14. DSPI modified transfer format timing – slave, CPHA = 0

SS

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

11

5

6

12

Last Data

First Data

10

Data

SOUT

SIN

9

First Data

Last Data

Figure 15. DSPI modified transfer format timing — slave, CPHA = 1

8

7

PCSS

PCSx

Figure 16. DSPI PCS strobe (PCSS) timing

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FlexRay electrical specifications

6.4.2 FlexRay electrical specifications

6.4.2.1 FlexRay timing

This section provides the FlexRay Interface timing characteristics for the input and output

signals. It should be noted that these are recommended numbers as per the FlexRay EPL

v3.0 specification, and subject to change per the final timing analysis of the device.

6.4.2.2 TxEN

TxEN

80 %

20 %

dCCTxEN

FALL

RISE

Figure 17. TxEN signal

Table 39. TxEN output characteristics¹

Name

Description

Min

—

Max

Unit

ns

dCCTxEN_RISE25

dCCTxEN_FALL25

dCCTxEN₀₁

Rise time of TxEN signal at CC

Fall time of TxEN signal at CC

9

—

ns

Sum of delay between Clk to Q of the last FF and the final

output buffer, rising edge

—

25

ns

dCCTxEN₁₀

Sum of delay between Clk to Q of the last FF and the final

output buffer, falling edge

—

25

ns

1. All parameters specified for V_{DD_HV_IOx}= 3.3 V -5%, + 10%, TJ = –40 °C / 150 °C, TxEN pin load maximum 25 pF

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FlexRay electrical specifications

PE_Clk

TxEN

dCCTxEN

10

01

Figure 18. TxEN signal propagation delays

6.4.2.3 TxD

TxD

dCCTxD

50%

80 %

50 %

20 %

dCCTxD

RISE

FALL

Figure 19. TxD Signal

Table 40. TxD output characteristics

Name

Description¹

Min

Max

Unit

dCCT_xAsym

Asymmetry of sending CC @ 25 pF load (=dCCTxD50% - 100

ns)

–2.45

2.45

ns

dCCTxD_RISE25+dCCTx Sum of Rise and Fall time of TxD signal at the output

D_FALL25

—

9²

ns

Table continues on the next page...

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FlexRay electrical specifications

Table 40. TxD output characteristics (continued)

Name

Description¹

Min

Max

Unit

dCCTxD₀₁

Sum of delay between Clk to Q of the last FF and the final

output buffer, rising edge

—

25

ns

dCCTxD₁₀

Sum of delay between Clk to Q of the last FF and the final

output buffer, falling edge

—

25

ns

1. All parameters specified for V_{DD_HV_IOx}= 3.3 V -5%, + 10%, TJ = –40 °C / 150 °C, TxD pin load maximum 25 pF.

2. For 3.3 V 10% operation, this specification is 10 ns.

PE_Clk*

TxD

dCCTxD

10

dCCTxD

01

*FlexRay Protocol Engine Clock

Figure 20. TxD Signal propagation delays

6.4.2.4 RxD

Table 41. RxD input characteristic

Name

Description¹

Min

Max

Unit

C_CCRxD

Input capacitance on

RxD pin

—

7

pF

uCCLogic_1

uCCLogic_0

dCCRxD₀₁

Threshold for detecting

logic high

35

30

—

70

65

10

%

ns

Threshold for detecting

logic low

Sum of delay from

actual input to the D

input of the first FF,

rising edge

dCCRxD₁₀

Sum of delay from

actual input to the D

input of the first FF,

falling edge

—

10

ns

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FlexRay electrical specifications

1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, + 10%, TJ = –40 oC / 150 oC.

6.4.3 Ethernet switching specifications

The following timing specs are defined at the chip I/O pin and must be translated

appropriately to arrive at timing specs/constraints for the physical interface.

6.4.3.1 MII signal switching specifications

The following timing specs meet the requirements for MII style interfaces for a range of

transceiver devices.

Table 42. MII signal switching specifications

Symbol

—

Description

Min.

—

Max.

25

Unit

MHz

RXCLK frequency

RXCLK pulse width high

MII1

35%

65%

RXCLK

period

RXCLK

period

ns

MII2

RXCLK pulse width low

35%

65%

MII3

MII4

—

RXD[3:0], RXDV, RXER to RXCLK setup

RXCLK to RXD[3:0], RXDV, RXER hold

TXCLK frequency

5

—

ns

—

25

MHz

MII5

TXCLK pulse width high

35%

65%

TXCLK

period

TXCLK

period

ns

MII6

TXCLK pulse width low

35%

65%

MII7

MII8

TXCLK to TXD[3:0], TXEN, TXER invalid

TXCLK to TXD[3:0], TXEN, TXER valid

2

—

25

ns

MII6

MII5

MII7

TXCLK (input)

MII8

Valid data

TXD[n:0]

TXEN

Valid data

TXER

Figure 21. RMII/MII transmit signal timing diagram

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FlexRay electrical specifications

MII2

MII3

MII1

MII4

RXCLK (input)

RXD[n:0]

RXDV

Valid data

RXER

Figure 22. RMII/MII receive signal timing diagram

6.4.3.2 RMII signal switching specifications

The following timing specs meet the requirements for RMII style interfaces for a range of

transceiver devices.

Table 43. RMII signal switching specifications

Num

—

Description

Min.

—

Max.

50

Unit

EXTAL frequency (RMII input clock RMII_CLK)

RMII_CLK pulse width high

MHz

RMII1

35%

65%

RMII_CLK

period

RMII2

RMII_CLK pulse width low

35%

65%

RMII_CLK

period

RMII3

RMII4

RMII7

RMII8

RXD[1:0], CRS_DV, RXER to RMII_CLK setup

RMII_CLK to RXD[1:0], CRS_DV, RXER hold

RMII_CLK to TXD[1:0], TXEN invalid

4

2

—

15

ns

4

RMII_CLK to TXD[1:0], TXEN valid

—

6.4.4 SAI electrical specifications

All timing requirements are specified relative to the clock period or to the minimum

allowed clock period of a device

Table 44. Master mode SAI Timing

no

Parameter

Value

Unit

Min

2.7

40

Max

3.6

-

Operating Voltage

V

S1

SAI_MCLK cycle time

ns

Table continues on the next page...

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53

FlexRay electrical specifications

Table 44. Master mode SAI Timing (continued)

no

Parameter

Value

Unit

Min

Max

S2

S3

SAI_MCLK pulse width high/low

SAI_BCLK cycle time

45%

55%

MCLK

period

80

-

BCLK

period

S4

S5

S6

S7

S8

S9

S10

SAI_BCLK pulse width high/low

45%

55%

ns

SAI_BCLK to SAI_FS output valid

SAI_BCLK to SAI_FS output invalid

SAI_BCLK to SAI_TXD valid

-

0

15

-

15

-

SAI_BCLK to SAI_TXD invalid

0

SAI_RXD/SAI_FS input setup before SAI_BCLK

SAI_RXD/SAI_FS input hold after SAI_BCLK

28

0

-

Figure 23. Master mode SAI Timing

Table 45. Slave mode SAI Timing

No

Parameter

Value

Unit

Min

2.7

80

Max

Operating Voltage

3.6

V

S11

S12

S13

S14

SAI_BCLK cycle time (input)

-

ns

SAI_BCLK pulse width high/low (input)

SAI_FS input setup before SAI_BCLK

SAI_FS input hold after SAI_BCLK

45%

10

55%

BCLK period

-

ns

2

Table continues on the next page...

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Debug specifications

Unit

Table 45. Slave mode SAI Timing (continued)

No

Parameter

Value

Min

-

Max

S15

S16

S17

S18

SAI_BCLK to SAI_TXD/SAI_FS output valid

SAI_BCLK to SAI_TXD/SAI_FS output invalid

SAI_RXD setup before SAI_BCLK

28

-

ns

0

10

2

-

SAI_RXD hold after SAI_BCLK

-

Figure 24. Slave mode SAI Timing

6.5 Debug specifications

6.5.1 JTAG interface timing

Table 46. JTAG pin AC electrical characteristics ¹

#

1

Symbol

t_JCYC

Characteristic

Min

62.5

40

—

5

Max

Unit

ns

%

TCK Cycle Time ²

—

60

3

2

t_JDC

TCK Clock Pulse Width

TCK Rise and Fall Times (40% - 70%)

3

t_TCKRISE

ns

4

t_TMSS, t_TDISTMS, TDI Data Setup Time

t_TMSH, t_TDIHTMS, TDI Data Hold Time

—

5

—

20³

6

t_TDOV

t_TDOI

t_TDOHZ

t_BSDV

TCK Low to TDO Data Valid

—

0

7

TCK Low to TDO Data Invalid

TCK Low to TDO High Impedance

TCK Falling Edge to Output Valid

—

8

—

15

600⁴

11

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55

Debug specifications

Table 46. JTAG pin AC electrical characteristics ¹(continued)

#

Symbol

Characteristic

Min

Max

Unit

12

t_BSDVZ

TCK Falling Edge to Output Valid out of High

Impedance

—

600

ns

13

14

15

t_BSDHZ

t_BSDST

t_BSDHT

TCK Falling Edge to Output High Impedance

Boundary Scan Input Valid to TCK Rising Edge

TCK Rising Edge to Boundary Scan Input Invalid

—

15

600

—

ns

—

1. These specifications apply to JTAG boundary scan only.

2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.

Refer to pad specification for allowed transition frequency

3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

TCK

2

3

2

1

3

Figure 25. JTAG test clock input timing

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Debug specifications

TCK

4

5

TMS, TDI

6

8

7

TDO

Figure 26. JTAG test access port timing

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57

Debug specifications

TCK

11

13

Output

Signals

12

Output

Signals

14

15

Input

Signals

Figure 27. JTAG boundary scan timing

6.5.2 Nexus timing

Table 47. Nexus debug port timing ¹

No.

Symbol

Parameter

Condition

s

Min

Max

Unit

1

2

3

4

5

6

7

8

t_MCYC

t_MDC

t_MDOV

t_EVTIPW

MCKO Cycle Time

—

15.6

40

–0.1

4

—

60

0.25

—

ns

%

MCKO Duty Cycle

MCKO Low to MDO, MSEO, EVTO Data Valid²

tMCYC

tTCYC

tMCYC

ns

EVTI Pulse Width

t_EVTOPWEVTO Pulse Width

1

—

t_TCYC

t_TDC

TCK Cycle Time³

62.5

40

8

—

TCK Duty Cycle

60

—

%

t_NTDIS

,

TDI, TMS Data Setup Time

ns

t_NTMSS

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Debug specifications

Table 47. Nexus debug port timing ¹(continued)

No.

Symbol

Parameter

Condition

s

Min

5

Max

—

Unit

ns

9

t_NTDIH

,

TDI, TMS Data Hold Time

TCK Low to TDO/RDY Data Valid

—

t_NTMSH

10

t_JOV

—

0

25

ns

1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured

from 50% of MCKO and 50% of the respective signal.

2. For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.

3. The system clock frequency needs to be four times faster than the TCK frequency.

1

2

MCKO

3

MDO

MSEO

EVTO

Output Data Valid

5

Figure 28. Nexus output timing

4

EVTI

Figure 29. Nexus EVTI Input Pulse Width

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59

Debug specifications

6

7

TCK

8

9

TMS, TDI

10

TDO/RDY

Figure 30. Nexus TDI, TMS, TDO timing

6.5.3 WKPU/NMI timing

Table 48. WKPU/NMI glitch filter

No.

1

Symbol

Parameter

Min

—

Typ

—

Max

20

Unit

ns

W_FNMI

NMI pulse width that is rejected

NMI pulse width that is passed

2

W_NFNMI

D

400

—

ns

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Thermal attributes

6.5.4 External interrupt timing (IRQ pin)

Table 49. External interrupt timing specifications

No.

1

Symbol

t_IPWL

Parameter

Conditions

Min

3

Max

Unit

t_CYC

IRQ pulse width low

IRQ pulse width high

IRQ edge to edge time

—

2

t_IPWH

3

t_ICYC

6

These values applies when IRQ pins are configured for rising edge or falling edge events,

but not both.

IRQ

1

2

3

Figure 31. External interrupt timing

7 Thermal attributes

7.1 Thermal attributes

Board type

Symbol

Description

176LQFP

Unit

Notes

Single-layer (1s)

R_θJA

Thermal

50.7

24.2

38.1

17.8

°C/W

1, 2

resistance, junction

to ambient (natural

convection)

Four-layer (2s2p)

Single-layer (1s)

Four-layer (2s2p)

R_θJA

Thermal

1, 2, 3

1, 3

resistance, junction

to ambient (natural

convection)

R_θJMA

Thermal

resistance, junction

to ambient (200 ft./

min. air speed)

R_θJMA

Thermal

1, 3

resistance, junction

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Thermal attributes

Board type

Symbol

Description

176LQFP

Unit

Notes

to ambient (200 ft./

min. air speed)

—

R_θJB

R_θJC

Ψ_JT

Thermal

resistance, junction

to board

10.9

8.4

°C/W

4

5

6

7

Thermal

resistance, junction

to case

Thermal

resistance, junction

to package top

0.5

Ψ_JB

Thermal

0.3

characterization

parameter, junction

to package bottom

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any

interface resistance. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

7. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JB.

Board type

Symbol

Description

324 MAPBGA

Unit

Notes

Single-layer (1s)

R_θJA

Thermal

31.0

°C/W

1, 2

1,2,3

1, 3

1,3

4

resistance, junction

to ambient (natural

convection)

Four-layer (2s2p)

Single-layer (1s)

Four-layer (2s2p)

—

R_θJA

Thermal

24.3

23.5

20.1

16.8

resistance, junction

to ambient (natural

convection)

R_θJMA

R_θJB

Thermal

resistance, junction

to ambient (200 ft./

min. air speed)

Thermal

resistance, junction

to ambient (200 ft./

min. air speed)

Thermal

resistance, junction

to board

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Thermal attributes

Board type

Symbol

Description

324 MAPBGA

Unit

Notes

—

R_θJC

Thermal

resistance, junction

to case

7.4

°C/W

5

Ψ_JT

Thermal

0.2

7.3

6

7

characterization

parameter, junction

to package top

natural convection

—

Ψ_JB

Thermal

°C/W

characterization

parameter, junction

to package bottom

natural convection

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

3. Per JEDEC JESD51-6 with the board horizontal

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction

temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is

written as Psi-JB.

Board type

Symbol

Description

256 MAPBGA

Unit

Notes

Single-layer (1s)

R_θJA

Thermal

42.6

°C/W

1, 2

1,2,3

1,3

resistance, junction

to ambient (natural

convection)

Four-layer (2s2p)

Single-layer (1s)

Four-layer (2s2p)

R_θJA

Thermal

26.0

31.0

21.3

resistance, junction

to ambient (natural

convection)

R_θJMA

Thermal

resistance, junction

to ambient (200 ft./

min. air speed)

R_θJMA

Thermal

1,3

resistance, junction

to ambient (200 ft./

min. air speed)

—

R_θJB

Thermal

resistance, junction

to board

12.8

7.9

°C/W

4

5

R_θJC

Thermal

resistance, junction

to case

Table continues on the next page...

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63

Thermal attributes

Board type

Symbol

Description

256 MAPBGA

Unit

Notes

—

Ψ_JT

Thermal

0.2

°C/W

6

7

characterization

parameter, junction

to package top

outside center

(natural

convection)

—

R_{θJB_CSB}

Thermal

9.0

characterization

parameter, junction

to package bottom

outside center

(natural

convection)

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JT.

7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction

temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is

written as Psi-JB.

Board type

Symbol

Description

100 MAPBGA

Unit

Notes

Single-layer (1s)

R_θJA

Thermal

50.9

°C/W

1,2

1,2,3

1,3

4

resistance, junction

to ambient (natural

convection)

Four-layer (2s2p)

Single-layer (1s)

Four-layer (2s2p)

—

R_θJA

Thermal

27.0

38.0

22.2

10.8

resistance, junction

to ambient (natural

convection)

R_θJMA

R_θJB

Thermal

resistance, junction

to ambient (200 ft./

min. air speed)

Thermal

resistance, junction

to ambient (200 ft./

min. air speed)

Thermal

resistance, junction

to board

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Dimensions

Notes

Board type

Symbol

Description

100 MAPBGA

Unit

—

R_θJC

Thermal

resistance, junction

to case

8.2

°C/W

5

6

Ψ_JT

Thermal

0.2

characterization

parameter, junction

to package top

outside center

(natural

convection)

—

Ψ_JB

Thermal

7.8

°C/W

7

characterization

parameter, junction

to package bottom

outside center

(natural

convection)

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JT.

7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction

temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is

written as Psi-JB.

8 Dimensions

8.1 Obtaining package dimensions

Package dimensions are provided in package drawing.

To find a package drawing, go to www.nxp.com and perform a keyword search for the

drawing’s document number:

Package

NXP Document Number

100 MAPBGA

176-pin LQFP-EP

256 MAPBGA

324 MAPBGA

98ASA00802D

98ASA00698D

98ASA00346D

98ASA10582D

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Pinouts

9 Pinouts

9.1 Package pinouts and signal descriptions

For package pinouts and signal descriptions, refer to the Reference Manual.

10 Reset sequence

10.1 Reset sequence

This section describes different reset sequences and details the duration for which the

device remains in reset condition in each of those conditions.

10.1.1 Reset sequence duration

Table 50 specifies the reset sequence duration for the five different reset sequences

described in Reset sequence description.

Table 50. RESET sequences

No. Symbol

Parameter

T_Reset

Unit

Min Typ ¹Max

1

2

3

4

5

T_DRB

T_DR

Destructive Reset Sequence, BIST enabled

Destructive Reset Sequence, BIST disabled

6.2

110

6.2

110

7

7.3

182

7.3

182

9

-

ms

us

T_ERLBExternal Reset Sequence Long, Unsecure Boot

ms

us

T_FRL

T_FRS

Functional Reset Sequence Long, Unsecure Boot

Functional Reset Sequence Short, Unsecure Boot

us

1. The Typ value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET_B by

an external reset generator.

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Reset sequence

10.1.2 BAF execution duration

Following table specifies the typical BAF execution time in case BAF boot header is

present at first location (Typical) and last location (worst case). Total Boot time is the

sum of reset sequence duration and BAF execution time.

Table 51. BAF execution duration

BAF execution

duration

Min

Typ

Max

Unit

BAF execution time

(boot header at first

location)

—

200

—

μs

BAF execution time

(boot header at last

location)

—

320

μs

10.1.3 Reset sequence description

The figures in this section show the internal states of the device during the five different

reset sequences. The dotted lines in the figures indicate the starting point and the end

point for which the duration is specified in .

With the beginning of DRUN mode, the first instruction is fetched and executed. At this

point, application execution starts and the internal reset sequence is finished.

The following figures show the internal states of the device during the execution of the

reset sequence and the possible states of the RESET_B signal pin.

NOTE

RESET_B is a bidirectional pin. The voltage level on this pin

can either be driven low by an external reset generator or by the

device internal reset circuitry. A high level on this pin can only

be generated by an external pullup resistor which is strong

enough to overdrive the weak internal pulldown resistor. The

rising edge on RESET_B in the following figures indicates the

time when the device stops driving it low. The reset sequence

durations given in are applicable only if the internal reset

sequence is not prolonged by an external reset generator

keeping RESET_B asserted low beyond the last Phase3.

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67

Reset sequence

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE0

PHASE1,2

PHASE3

BIST

PHASE1,2

PHASE3

DRUN

Establish

IRC and

PWR

Flash

Init

Device

Config

Self Test

Setup

Flash

Init

Device

Config

Application

Execution

MBIST

T

< T

RESET DRB, max

DRB, min

Figure 32. Destructive reset sequence, BIST enabled

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE0

PHASE1,2

PHASE3

DRUN

BAF+

Establish

IRC and

PWR

Flash

Init

Device

Config

Application

Execution

T

< T

RESET DR, max

DR, min

Figure 33. Destructive reset sequence, BIST disabled

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE1,2

PHASE3

BIST

PHASE1,2

PHASE3

DRUN

Device

Config

Flash

Init

Application

Execution

Device

Config

Flash

Init

Self Test

Setup

MBIST

T

< T

RESET

< T

ERLB, max

ERLB, min

Figure 34. External reset sequence long, BIST enabled

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE1,2

PHASE3

DRUN

BAF+

Application

Ex ecut ion

Flash

Init

Device

Config

T

< T

RESET FRL, max

FRL, min

Figure 35. Functional reset sequence long

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Revision History

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE3

DRUN

BAF+

Application

Execution

T

< T

RESET FRS, max

FRS, min

Figure 36. Functional reset sequence short

The reset sequences shown in Figure 35 and Figure 36 are triggered by functional reset

events. RESET_B is driven low during these two reset sequences only if the

corresponding functional reset source (which triggered the reset sequence) was enabled to

drive RESET_B low for the duration of the internal reset sequence. See the RGM_FBRE

register in the device reference manual for more information.

11 Revision History

11.1 Revision History

The following table provides a revision history for this document.

Table 52. Revision History

Rev. No.

Rev 1

Date

Substantial Changes

14 March 2013

7 August 2015

Initial Release

• In features:

Rev 2

• Updated BAF feature with sentence, Boot Assist Flash (BAF) supports internal

flash programming via a serial link (SCI)

• Updated FlexCAN3 with FD support

• Updated number of STMs to two.

• In Block diagram:

• Updated SRAM size from 128 KB to 256 KB.

• In Family Comparison:

• Added note: All optional features (Flash memory, RAM, Peripherals) start with

lowest number or address (e.g. FlexCAN0) and end at highest available number

or address (e.g. MPC574xB/D have 6 CAN, ending with FlexCAN5).

• Revised MPC5746C Family Comparison table.

• In Ordering parts:

• Updated ordering parts diagram to include 100 MAPBGA information and optional

fields.

• In table: Absolute maximum ratings

• Removed entry: 'V_{SS_HV}

• Added spec for 'V_DD12

• Updated 'Max' column for 'V_INA

'

Table continues on the next page...

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Revision History

Rev. No.

Table 52. Revision History (continued)

Date

Substantial Changes

• Updated footnote for V_{DD_HV_ADC1_REF.}

• Added footnote to 'Conditions', All voltages are referred to V_{SS_HV}unless

otherwise specified

• Removed footnote from 'Max', Absolute maximum voltages are currently

maximum burn-in voltages. Absolute maximum specifications for device stress

have not yet been determined.

• In section: Recommended operating conditions

• Added opening text: ''The following table describes the operating conditions ... "

• Added note: "V_{DD_HV_A}, V_{DD_HV_B}and V_{DD_HV_C}are all ... "

• In table: Recommended operating conditions (VDD_HV_x = 3.3 V) and

(VDD_HV_x = 5 V)

• Added footnote to 'Conditions' cloumn, (All voltages are referred to V_{SS_HV}

unless otherwise specified).

• Updated footnote for 'Min' column to Device will be functional down (and

electrical specifications as per various datasheet parameters will be

guaranteed) to the point where one of the LVD/HVD resets the device.

When voltage drops outside range for an LVD/HVD, device is reset.

• Removed footnote for 'V_{DD_HV_A}', 'V_{DD_HV_B}', and 'V_{DD_HV_C}' entry and

updated the parameter column.

• Removed entry : 'V_{SS_HV}

• Updated 'Parameter' column for 'V_{DD_HV_FLA}', 'V_{DD_HV_ADC1_REF}', 'V_{DD_LV}

• Updated 'Min' column for 'V_{DD_HV_ADC0}' 'V_{DD_HV_ADC1}

'

• Updated 'Parameter' 'Min' 'Max' columns for 'V_{SS_HV_ADC0}' and 'V_{SS_HV_ADC1}

• Updated footnote for 'V_{DD_LV}' to V_{DD_LV}supply pins should never be

grounded (through a small impedance). If these are not driven, they should

only be left floating.

'

• Removed row for symbol 'V_{SS_LV}

'

• Removed footnote from 'Max' column of 'V_{DD_HV_ADC0}' and 'V_{DD_HV_ADC1}',

(PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from

V_{DD_HV_B}domain hence V_{DD_HV_ADC1}should be within 100 mV of

V_{DD_HV_B}when these channels are used for ADC_1).

• In table: Recommended operating conditions (V_{DD_HV_x}= 3.3 V)

• Removed footnote from 'V_{IN1_CMP_REF}', (Only applicable when supplying

from external source).

• In table: Recommended operating conditions (V_{DD_HV_x}= 5 V)

• Added spec for 'V_{IN1_CMP_REF}' and corresponding footnotes.

• In section: Voltage monitor electrical characteristics

• Updated description for Low Voltage detector block.

• Added note, BCP56, MCP68 and MJD31 are guaranteed ballasts.

• In table: Voltage regulator electrical specifications

• Added footnote, Ceramic X7R or X5R type with capacitance-temperature

characteristics +/-15% of -55 degC to +125degC is recommended. The

tolerance +/-20% is acceptable.

• Revised table, Voltage monitor electrical characteristics

• In section: Supply current characteristics

• In table: Current consumption characteristics

• I_{DD_BODY_4}: Updated SYS_CLK to 120 MHz.

• I_{DD_BODY_4}: Updated Max for T_a= 105 °C fand 85 °C )

• I_{dd_STOP}: Added condition for T_a= 105 °C and removed Max value for T_a= 85

°C.

• I_{DD_HV_ADC_REF}: Added condition for T_a= 105 °C and 85 °C and removed

Max value for T_a= 25 °C.

• I_{DD_HV_FLASH}: Added condition for T_a= 105 °C and 85 °C

• In table: Low Power Unit (LPU) Current consumption characteristics

• LPU_RUN and LPU_STOP: Added condition for T_a= 105 °C and 85 °C

Table continues on the next page...

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

70

NXP Semiconductors

Revision History

Table 52. Revision History (continued)

Rev. No.

Date

Substantial Changes

• In table: STANDBY Current consumption characteristics

• Added condition for T_a= 105 °C and 85 °C for all entries.

• In section: I/O parameters

• In table: Functional Pad AC Specifications @ 3.3 V Range

• Updated values for 'pad_sr_hv (output)'

• In table: DC electrical specifications @ 3.3V Range

• Updateded Min and Max values for Vih and Vil respectively.

• In table: Functional Pad AC Specifications @ 5 V Range

• Updated values for 'pad_sr_hv (output)'

• In table DC electrical specifications @ 5 V Range

• Updated Min value for Vhys

• In section: Reset pad electrical characteristics

• Revised table, Reset electrical characteristics

• Deleted note, There are some specific ports that supports TTL functionality. These

ports are, PB[4], PB[5], PB[6], PB[7], PB[8], PB[9], PD[0], PD[1], PD[2], PD[3],

PD[4], PD[5], PD[6], PD[7], PD[8], PD[9], PD[10], and PD[11].

• In section: PORST electrical specifications

• In table: PORST electrical specifications

• Updated 'Min' value for W_NFPORST

• In section: Peripheral operating requirements and behaviours

• Changed section title from Input impedance and ADC accuracy to Input equivalent

circuit and ADC conversion characteristics.

• Revised table: ADC conversion characteristics (for 12-bit) and ADC conversion

characteristics (for 10-bit)

• Removed table, ADC supply configurations.

• In section: Analogue Comparator (CMP) electrical specifications

• In table: Comparator and 6-bit DAC electrical specifications

• Updated 'Max' value of I_DDLS

• Updated 'Min' and 'Max' for V_AIOand DNL

• Updated 'Descripton' 'Min' 'Max' od V_H

• Updated row for t_DHS

• Added row for t_DLS

• Removed row for V_CMPOhand V_CMPOl

• In section: Clocks and PLL interfaces modules

• In table: Main oscillator electrical characteristics

• V_XOSCHS: Removed values for 4 MHz.

• T_XOSCHSSU: Updated range to 8-40 MHz.

• In table: 16 MHz RC Oscillator electrical specifications

• Updated 'Max' for T_startupand T_LTJIT

• Removed F_Untrimmedrow

• In table: 128 KHz Internal RC oscillator electrical specifications

• Fosc: Removed Uncaliberated 'Condition' and updated 'Min', 'Typ', and

'Max' for Caliberated condition

• Fosc: Updated 'Temperature dependence' and 'Supply dependence' Max

values

• In table: PLL electrical specifications

• Removed entries for Input Clock Low Level, Input Clock High Level, Power

consumption, Regulator Maximum Output Current, Analog Supply, Digital

Supply (V_{DD_LV}), Modulation Depth (Down Spread), PLL reset assertion

time, and Power Consumption

Table continues on the next page...

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

71

Revision History

Rev. No.

Table 52. Revision History (continued)

Date

Substantial Changes

• Removed 'Typ' value for Duty Cycle at pllclkout

• Removed 'Min' value for Lock Time in calibration mode.

• In table: Jitter calculation

• Added 1 Sigma Random Jitter and Total Period Jitter values for Long Term

Jitter (Interger and Fractional Mode) rows.

• In section Flash read wait state and address pipeline control settings

• In Flash Read Wait State and Address Pipeline Control: Updated APC for 40 MHz.

• Removed section: On-chip peripherals

• In section, Thermal attributes

• Added table for 100 MAPBGA

• In section Obtaining package dimensions

• Updated package details for 100 MAPBGA

• Editoral updates throughtout including correction of various module names.

Rev 3

2 March 2016

• In section, Recommended operating conditions

• Added a new Note

• In section, Voltage regulator electrical characteristics

• In table, Voltage regulator electrical specifications:

• Added a new row for C_{HV_VDD_B}

• Added a footnote on V_{DD_HV_BALLAST}

• Added a new Note at the end of this section

• In section, Voltage monitor electrical characteristics

• In table, Voltage monitor electrical characteristics:

• Removed "V_{LVD_FLASH}" and "V_{LVD_FLASH}during low power mode using

LPBG as reference" rows

• Updated Fall and Rise trimmed Minimum values for V_{HVD_LV_cold}

• In section, Supply current characteristics

• In table, Current consumption characteristics:

• Updated the footnote mentioned in the Condition column of I_{DD_STOP}row

• Updated all TBD values

• In table, Low Power Unit (LPU) Current consumption characteristics:

• Updated the typical value of LPU_STOP to 0.18 mA

• Updated all TBD values

• In table, STANDBY Current consumption characteristics:

• Updated all TBD values

• In section, AC specifications @ 3.3 V Range

• In table, Functional Pad AC Specifications @ 3.3 V Range:

• Updated Rise/Fall Edge values

• In section, DC electrical specifications @ 3.3V Range

• In table, DC electrical specifications @ 3.3V Range:

• Updated Max value for Vol to 0.1 * VDD_HV_x

• In section, AC specifications @ 5 V Range

• In table, Functional Pad AC Specifications @ 5 V Range:

• Updated Rise/Fall Edge values

• In section, DC electrical specifications @ 5 V Range

• In table, DC electrical specifications @ 5 V Range:

Table continues on the next page...

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

72

NXP Semiconductors

Revision History

Table 52. Revision History (continued)

Rev. No.

Date

Substantial Changes

• Updated Min and Max values for Pull_Ioh and Pull_Iol rows

• Updated Max value for Vol to 0.1 * VDD_HV_x

• In section, Reset pad electrical characteristics

• In table, Functional reset pad electrical specifications:

• Updated parameter column for V_IH, V_ILand V_HYSrows

• Updated Min and Max values for V_IHand V_ILrows

• In section, PORST electrical specifications

• In table, PORST electrical specifications:

• Updated Unit and Min/Max values for V_IHand V_ILrows

• In section, Input equivalent circuit and ADC conversion characteristics

• In table, ADC conversion characteristics (for 12-bit):

• Updated "ADC Analog Pad (pad going to one ADC)" row

• In table, ADC conversion characteristics (for 10-bit):

• Updated "ADC Analog Pad (pad going to one ADC)" row

• In section, Analog Comparator (CMP) electrical specifications

• In table, Comparator and 6-bit DAC electrical specifications:

• Updated Min and Max values for V_AIOto 47 mV

• Updated Max value for t_DLSto 21 μs

• In section, Main oscillator electrical characteristics

• In table, Main oscillator electrical characteristics:

• Updated V_IHMin value to 1.95V

• Updated V_ILMax value to 1.25V

• Removed V_IHTyp value

• In section, PLL electrical specifications

• In table, PLL electrical specifications:

• Updated Max value for Modulation Depth (Center Spread) to +/- 3.0%

Rev 4

Rev 5

9 March 2016

• In section, Voltage regulator electrical characteristics

• In table, Voltage regulator electrical specifications:

• Updated the footnote on V_{DD_HV_BALLAST}

27 February

2017

• In Family Comparison section:

• Updated the "MPC5746C Family Comparison" table.

• added "NVM Memory Map 1", "NVM Memory Map 2", and "RAM Memory Map"

tables.

• Updated the product version, flash memory size and optional fields information in

Ordering Information section.

• In Recommended Operating Conditions section, removed the note related to additional

crossover current.

• VDD_HV_C row added in "Voltage regulator electrical specifications" table in Voltage

regulator electrical characteristics section.

• In Voltage Monitor Electrical Characteristics section, updated the "Trimmed" Fall and

Rise specs of VHVD_LV_cold parameter in "Voltage Monitor Electrical Characteristics"

table.

• In AC Electrical Specifications: 3.3 V Range section, changed the occurrences of

“ipp_sre[1:0]” to “SIUL2_MSCRn.SRC[1:0]” in the table.

Table continues on the next page...

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

73

Revision History

Rev. No.

Table 52. Revision History (continued)

Date

Substantial Changes

• In DC Electrical Specifications: 3.3 V Range section, changed the occurrences of

“ipp_sre[1:0]” to “SIUL2_MSCRn.SRC[1:0]” and updated "Vol min and max" values in

the table.

• In AC Electrical Specifications: 5 V Range section, changed the occurrences of

“ipp_sre[1:0]” to “SIUL2_MSCRn.SRC[1:0]” in the table.

• In DC Electrical Specifications: 5 V Range section, changed the occurrences of

“ipp_sre[1:0]” to “SIUL2_MSCRn.SRC[1:0]” and updated "Vol min and max" values in

the table.

• In "Flash memory AC timing specifications" table in Flash memory AC timing

specifications section:

• Updated the "t_psus" typ value from 7 us to 9.4 us.

• Updated the "t_psus" max value from 9.1 us to 11.5 us.

• Added "Continuous SCK Timing" table in DSPI timing section.

• Added "ADC pad leakage" at 105°C TA conditions in "ADC conversion characteristics

(for 12-bit)" table in ADC electrical specifications section.

• In "STANDBY Current consumption characteristics" table in Supply current

characteristics section:

• Updated the Typ and max values of IDD Standby current.

• Added IDD Standby3 current spec for FIRC ON.

• Removed IVDDHV and IVDDLV specs in 16 MHz RC Oscillator electrical specifications

section.

• Added Reset Sequence section, with Reset Sequence Duration, BAF execution duration

section, and Reset Sequence Distribution as its sub-sections.

Rev 5.1

22 May 2017

• Removed the Introduction section from Section 4 "General".

• In AC Specifications@3.3V section, removed note related to Cz results and added two

notes.

• In AC Specifications@5V section, added two notes.

• In ADC Electrical Specifications section, added spec value of "ADC Analog Pad" at Max

leakage (standard channel)@ 105 C T_Ain "ADC conversion characteristics (for 10-bit)"

table.

• In PLL Electrical Specifications section, updated the first footnote of "Jitter calculation"

table.

• In Analog Comparator Electrical Specifications section, updated the TDLS (propagation

delay, low power mode) max value in "Comparator and 6-bit DAC electrical

specifications" table to 21 us.

• In Recommended Operating Conditions section, updated the footnote link to T_Ain

"Recommended operating conditions (V DD_HV_x = 5V)" table.

Rev 6

21 Nov 2018

• In Table 2 changed the Code Flash Block 9 (0x01240000 - 0x0127FFFF) from 'not

available' to 'available' for MPC5746.

• In Table 3 added 32 and 64 KB flash blocks and footnote "Flexible patitions for boot and

EEPROM".

• Added Table 4.

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

74

NXP Semiconductors

Revision History

Table 52. Revision History

Rev. No.

Date

Substantial Changes

• Updated GPIO and added GPI row in Table 1.

• Changed the EEPROM support for MPC574xC devices from Emulated up to"64K" to

"Emulated up to 128K" in Table 1.

• Changed "V_{DD_HV_A}" to "V_{DD_HV_IO}" and changed the condition from "V_{DD_HV_A}

V_{DD_POR}" to "3.0 V < V_{DD_HV_IO}< 5.5 V" in Table 19.

=

• Added the text "For internal ballast configuration the VRC_CTL pin should be left

floating" in existing foot note "Recommended Transistors:MJD31 @ 85°C....." in Table

11.

• Added note "For the Precision channel Analog inputs...pulled low/high externally" after

the table "STANDBY Current consumption characteristics" in Supply current

characteristics.

• In Table 36 :

• Added footnote in "High Speed Mode" column.

• For Parameter "DSPI cycle time" changed the Condition from "Master (MTFE=0)"

to "Master".

• In Voltage monitor electrical characteristics

• Under the column "Reset Type" changed "Destructive" to "POR" throughout the

table "Voltage monitor electrical characteristics".

• Changed the Reset type of "V_{LVD_IO_A_HI}" to "Functional"

MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018

NXP Semiconductors

75

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Document Number MPC5746C

Revision 6, 11/2018


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