935352792528 [NXP]
RISC Microcontroller;
| 型号： | 935352792528 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 外围集成电路 |
| 文件： | 总65页 (文件大小：1159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number MWCT101xSF
NXP Semiconductors
Data Sheet: Advance Information
Rev. 2, 07/2018
MWCT101XSF
MWCT101XS Data Sheet
Key Features
• Memory and memory interfaces
– Up to 2 MB program flash memory with ECC
– 64 KB FlexNVM for data flash memory with ECC
and EEPROM emulation. Note: CSEc (Security) or
EEPROM writes/erase will trigger error flags in
HSRUN mode (112 MHz) because this use case is
not allowed to execute simultaneously. The device
will need to switch to RUN mode (80 MHz) to
execute CSEc (Security) or EEPROM writes/erase.
– Up to 256 KB SRAM with ECC
– Up to 4 KB of FlexRAM for use as SRAM or
EEPROM emulation
– Up to 4 KB Code cache to minimize performance
impact of memory access latencies
• Operating characteristics
– Voltage range: 2.7 V to 5.5 V
– Ambient temperature range: -40 °C to 105 °C for
HSRUN mode, -40 °C to 125 °C for RUN mode
• Arm™ Cortex-M4F core, 32-bit CPU
– Supports up to 112 MHz frequency (HSRUN) with
1.25 Dhrystone MIPS per MHz
– Arm Core based on the Armv7 Architecture and
Thumb®-2 ISA
– Integrated Digital Signal Processor (DSP)
– Configurable Nested Vectored Interrupt Controller
(NVIC)
– Single Precision Floating Point Unit (FPU)
– QuadSPI with HyperBus™ support
• Clock interfaces
• Mixed-signal analog
– 4 - 40 MHz fast external oscillator (SOSC)
– 48 MHz Fast Internal RC oscillator (FIRC)
– 8 MHz Slow Internal RC oscillator (SIRC)
– 128 kHz Low Power Oscillator (LPO)
– Up to 112 MHz (HSRUN) System Phased Lock
Loop (SPLL)
– Up to two 12-bit Analog-to-Digital Converter
(ADC) with up to 32 channel analog inputs per
module
– One Analog Comparator (CMP) with internal 8-bit
Digital to Analog Converter (DAC)
• Debug functionality
– Up to 50 MHz DC external square wave input clock
– Real Time Counter (RTC)
– Serial Wire JTAG Debug Port (SWJ-DP) combines
– Debug Watchpoint and Trace (DWT)
– Instrumentation Trace Macrocell (ITM)
– Test Port Interface Unit (TPIU)
• Power management
– Low-power Arm Cortex-M4F core with excellent
energy efficiency
– Flash Patch and Breakpoint (FPB) Unit
– Power Management Controller (PMC) with multiple
power modes: HSRUN, RUN, STOP, VLPR, and
VLPS. Note: CSEc (Security) or EEPROM writes/
erase will trigger error flags in HSRUN mode (112
MHz) because this use case is not allowed to
execute simultaneously. The device will need to
switch to RUN mode (80 Mhz) to execute CSEc
(Security) or EEPROM writes/erase.
• Human-machine interface (HMI)
– Up to 89 GPIO pins with interrupt functionality
– Non-Maskable Interrupt (NMI)
– Clock gating and low power operation supported on
specific peripherals.
This document contains information on a pre-production product. Specifications
and pre-production information herein are subject to change without notice.
• Communications interfaces
– Up to three Low Power Universal Asynchronous Receiver/Transmitter (LPUART/LIN) modules with DMA support
and low power availability
– Up to three Low Power Serial Peripheral Interface (LPSPI) modules with DMA support and low power availability
– Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support and low power availability
– Up to three FlexCAN modules (with optional CAN-FD support)
– FlexIO module for emulation of communication protocols and peripherals (UART, I2C, SPI, I2S, LIN, PWM, etc).
• Safety and Security
– Cryptographic Services Engine (CSEc) implements a comprehensive set of cryptographic functions as described in the
SHE (Secure Hardware Extension) Functional Specification. Note: CSEc (Security) or EEPROM writes/erase will
trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The
device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.
– 128-bit Unique Identification (ID) number
– Error-Correcting Code (ECC) on flash and SRAM memories
– System Memory Protection Unit (System MPU)
– Cyclic Redundancy Check (CRC) module
– Internal watchdog (WDOG)
– External Watchdog monitor (EWM) module
• Timing and control
– Up eight independent 16-bit FlexTimers (FTM) module, offering up to 64 standard channels (IC/OC/PWM)
– One 16-bit Low Power Timer (LPTMR) with flexible wake up control
– Two Programmable Delay Blocks (PDB) with flexible trigger system
– One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels
– 32-bit Real Time Counter (RTC)
• I/O and package
– 64-pin LQFP, 100-pin LQFP, 100-pin MAPBGA package options
• 16 channel DMA with up to 63 request sources using DMAMUX
MWCT101XS Data Sheet, Rev. 2, 07/2018
2
NXP Semiconductors
Table of Contents
1
2
3
Block diagram.................................................................................... 4
6.2.5 SPLL electrical specifications .....................................27
6.3 Memory and memory interfaces................................................27
6.3.1 Flash memory module (FTFC) electrical
Feature comparison............................................................................ 5
Ordering parts.....................................................................................7
3.1 Determining valid orderable parts ............................................ 7
3.2 Ordering information ................................................................8
General............................................................................................... 9
4.1 Absolute maximum ratings........................................................9
4.2 Voltage and current operating requirements..............................10
4.3 Thermal operating characteristics..............................................11
4.4 Power and ground pins.............................................................. 11
4.5 LVR, LVD and POR operating requirements............................13
4.6 Power mode transition operating behaviors.............................. 13
4.7 Power consumption................................................................... 14
4.8 ESD handling ratings.................................................................17
4.9 EMC radiated emissions operating behaviors........................... 17
I/O parameters....................................................................................17
5.1 AC electrical characteristics...................................................... 17
5.2 General AC specifications......................................................... 18
5.3 DC electrical specifications at 3.3 V Range.............................. 18
5.4 DC electrical specifications at 5.0 V Range.............................. 19
5.5 AC electrical specifications at 3.3 V range .............................. 20
5.6 AC electrical specifications at 5 V range ................................. 21
5.7 Standard input pin capacitance.................................................. 22
5.8 Device clock specifications....................................................... 22
Peripheral operating requirements and behaviors..............................23
6.1 System modules.........................................................................23
6.2 Clock interface modules............................................................ 23
6.2.1 External System Oscillator electrical specifications....23
6.2.2 External System Oscillator frequency specifications . 25
6.2.3 System Clock Generation (SCG) specifications..........26
specifications................................................................27
6.3.1.1
Flash timing specifications —
4
commands................................................ 27
Reliability specifications..........................30
6.3.1.2
6.3.2 QuadSPI AC specifications..........................................31
6.4 Analog modules.........................................................................35
6.4.1 ADC electrical specifications...................................... 35
6.4.1.1
6.4.1.2
12-bit ADC operating conditions.............35
12-bit ADC electrical characteristics....... 37
6.4.2 CMP with 8-bit DAC electrical specifications............ 39
6.5 Communication modules...........................................................43
6.5.1 LPUART electrical specifications............................... 43
6.5.2 LPSPI electrical specifications.................................... 43
6.5.3 LPI2C electrical specifications.................................... 49
6.5.4 FlexCAN electical specifications.................................50
6.5.5 Clockout frequency......................................................50
6.6 Debug modules.......................................................................... 50
6.6.1 SWD electrical specofications .................................... 50
6.6.2 Trace electrical specifications......................................52
6.6.3 JTAG electrical specifications..................................... 53
Thermal attributes.............................................................................. 56
7.1 Description.................................................................................56
7.2 Thermal characteristics..............................................................56
7.3 General notes for specifications at maximum junction
5
7
6
temperature................................................................................ 59
Dimensions.........................................................................................60
8.1 Obtaining package dimensions .................................................60
Pinouts................................................................................................61
9.1 Package pinouts and signal descriptions....................................61
8
9
6.2.3.1
Fast internal RC Oscillator (FIRC)
electrical specifications............................ 26
Slow internal RC oscillator (SIRC)
6.2.3.2
10 Revision History.................................................................................61
electrical specifications ........................... 26
6.2.4 Low Power Oscillator (LPO) electrical specifications
......................................................................................27
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
3
Block diagram
1 Block diagram
The figure below shows a superset high level architecture block diagram of the device.
Other devices within the family have a subset of the features. See Feature comparison for
chip specific values.
Arm Cortex M4F
MCM
Core
Async
Trace
port
TPIU
PPB
NVIC
ITM
AWIC
JTAG &
SWJ-DP
AHB-AP
Serial Wire
FPU
FPB
Clock generation
DSP DWT
DMA
MUX
SOSC
4-40 MHz
FIRC
48 MHz
SIRC
8 MHz
LPO
128 kHz
8-40 MHz
Mux
SPLL
eDMA
TCD
512B
LMEM
2
Main SRAM
LMEM
controller
Upper region
Lower region
EIM
Code Cache
M3
M2
M1
M0
S2
S3
S1
Crossbar switch (AXBS-Lite)
S0
1
1
1
System MPU
System MPU
System MPU
Mux
QuadSPI
GPIO
Flash memory
controller
Peripheral bus controller
FlexRAM/
SRAM
Low Power
Timer
LPIT
WDOG
LPI2C
ERM
12-bit ADC
FlexIO
Code flash
memory
Data flash
memory
CMP
8-bit DAC
FlexTimer
FlexCAN
LPUART
LPSPI
QSPI
EWM
CRC
3
CSEc
RTC
TRGMUX
PDB
1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from
accessing restricted memory regions. This system MPU provides memory protection at the
level of the Crossbar Switch. Each Crossbar master (Core, DMA) can be assigned
different access rights to each protected memory region. The Arm M4 core version in this family
does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.
Device architectural IP
on all MWCT101xS devices
Key:
Peripherals present
on all MWCT101xS devices
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"
chapter of the MWCT101xS Series Reference Manual.
Peripherals present
on selected MWCT101xS devices
(see the "Feature Comparison"
section in the RM)
3: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this
use case is not allowed to execute simultaneously. The device needs to switch to RUN mode (80 MHz) to
execute CSEc (Security) or EEPROM writes/erase.
Figure 1. High-level architecture diagram for the MWCT101xS family
MWCT101XS Data Sheet, Rev. 2, 07/2018
4
NXP Semiconductors
Feature comparison
2 Feature comparison
The following figure summarizes the memory and package options for the MWCT101xS
series and demonstrates where this device fits within the overall series. All devices which
share a common package are pin-to-pin compatible.
NOTE
Availability of peripherals depends on the pin availability in a
particular package. For more information see IO Signal
Description Input Multiplexing sheet(s) attached with
Reference Manual.
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
5
Feature comparison
MWCT101xS
MWCT1014S
Parameter
MWCT1015S
MWCT1016S
®
Core
Arm Cortex™-M4F
Frequency
IEEE-754 FPU
up to 112 MHz (HSRUN)
HW security module (CSEc)1
CRC module
1x
capable up to ASIL-B
ISO 26262
Peripheral speed
Crossbar
up to 112 MHz (HSRUN)
DMA
EWM
Memory protection unit
FIRC CMU
Watchdog
1x
Low power modes
HSRUN mode1
Number of I/Os
Single supply voltage
up to 89
up to 89
2.7 - 5.5 V
up to 89
Operating temperature (T ) Temperature ambient
a
-40 to +105ºC / +125ºC
1 MB
Flash
2 MB2
512 KB
64 KB
Error correction code (ECC)
System RAM (including FlexRAM)
FlexRAM (also available as system RAM)
Cache
128 KB
4 KB
256 KB
4 KB
EEPROM emulated by FlexRAM1
4 KB (up to 64 KB D-Flash)
See footnote 3
QuadSPI incl.
HyperBus™
External memory interface
Low power interrupt timer
1x
FlexTimer (16-bit counter) 8 channels
Low power timer (LPTMR)
4x (32)
8x (64)
6x (48)
1x
1x
2x
Real time counter (RTC)
Programmable delay block (PDB)
Trigger mux (TRGMUX)
1x (73)
2x (24)
1x (64)
2x (16)
1x (81)
2x (32)
12-bit SAR ADC (1 MSPS each)
Comparator with 8-bit DAC
1x
Low power UART/LIN
(Supports LIN protocol versions 1.3, 2.0, 2.1, 2.2A and SAE J2602)
3x
Low power SPI
Low power I2C
3x
2x
1x
FlexCAN
(CAN-FD ISO/CD 11898-1)
3x
(1x with FD)
3x
3x
(2x with FD)
(3x with FD)
FlexIO (8 pins configurable as UART, SPI, I2C, I2S)
1x
SWD, JTAG
(ITM, SWV,
SWO), ETM
Debug & trace
SWD, JTAG4 (ITM, SWV, SWO)
Ecosystem
(IDE, compiler, debugger)
NXP S32 Design Studio + GCC + GHS + Lauterbach
LQFP-100
BGA-100
LQFP-64
LQFP-100
Packages5
BGA-100
LEGEND:
Not implemented
Available on the device
1
No write or erase access to Flash module, including Security (CSEc) and EEPROM commands, are allowed when
device is running at HSRUN mode (112MHz) or VLPR mode.
2
3
Available when EEEPROM, CSEc and Data Flash are not used. Else only up to 1,984 KB is available for Program Flash.
4 KB (up to 512 KB D-Flash as a part of 2M Flash). Up to 64 KB of flash is used as EEPROM backup and the remaining 448 KB
of the last 512 KB block can be used as Data flash or Program flash. See chapter FTFC for details.
Only for Boundary Scan Register
4
5
See Dimensions for package drawing
Figure 2. MWCT101xS product series comparison
MWCT101XS Data Sheet, Rev. 2, 07/2018
6
NXP Semiconductors
Ordering parts
3 Ordering parts
3.1 Determining valid orderable parts
To determine the orderable part numbers for this device, go to www.nxp.com and
perform a part number search.
NOTE
Not all part number combinations exist
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
7
Ordering parts
3.2 Ordering information
M/P WCT 1 0 1 4 S F V LH N R
Product status
Product line
Generation
Config
Power Class
Memory Size
Application
Core Platform
Temperature
Package
Includes stack
Tape and Reel
Product status
P: Pre Qualification
M: Fully Qualified
Package
Memory size (Flash)
LQFP
Pins
64
BGA
-
4
5
6
LH
LL
M4F
512 K
1 M
2 M
Product line
WCT: Wireless Charging
Technology
100
MH
Application
Generation
1: 1st product Gen
2: 2nd product Gen
Blank =Customer
A = Auto/Industr
S = A + AUTOSAR
Includes stack
Blank = No stack
N = NFC
Config
0 = Standard
1 = Premium
Core platform
F: Arm Cortex M4F
Tape and Reel
T: Trays and Tubes
R: Tape and Reel
Power Class
0 = 5 W
Temperature
V: -40C to 105C
1 = 15 W
2 = 60 W
3 =200 W
Figure 3. Ordering information
MWCT101XS Data Sheet, Rev. 2, 07/2018
8
NXP Semiconductors
General
4 General
4.1 Absolute maximum ratings
NOTE
• Functional operating conditions appear in the DC electrical
characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maximum
values is not guaranteed. See footnotes in the following
table for specific conditions.
• Stress beyond the listed maximum values may affect device
reliability or cause permanent damage to the device.
• All the limits defined in the datasheet specification must be
honored together and any violation to any one or more will
not guarantee desired operation.
• Unless otherwise specified, all maximum and minimum
values in the datasheet are across process, voltage, and
temperature.
Table 1. Absolute maximum ratings
Symbol
Parameter
Conditions1
Min
-0.3
-0.3
-3
Max
5.8 3
5.8 3
+3
Unit
V
2
VDD
2.7 V - 5. 5V input supply voltage
3.3 V / 5.0 V ADC high reference voltage
—
—
—
VREFH
V
4
IINJPAD_DC_ABS
Continuous DC input current (positive /
negative) that can be injected into an I/O
pin
mA
VIN_DC
Continuous DC Voltage on any I/O pin
with respect to VSS
—
—
-0.8
—
5.85
30
V
IINJSUM_DC_ABS
Sum of absolute value of injected currents
on all the pins (Continuous DC limit)
mA
6
Tramp
ECU supply ramp rate
MCU supply ramp rate
Ambient temperature
Storage temperature
—
—
—
—
—
0.5 V/min
0.5 V/min
-40
500 V/ms
100 V/ms
125
—
—
°C
°C
V
7
Tramp_MCU
8
TA
TSTG
-55
165
6.8 9
VIN_TRANSIENT
Transient overshoot voltage allowed on
I/O pin beyond VIN_DC limit
—
1. All voltages are referred to VSS unless otherwise specified.
2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the
ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.
3. 60 s lifetime – No restrictions i.e. The part can switch.
10 hours lifetime – Device in reset i.e. The part cannot switch.
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
9
General
4. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.
5. While respecting the maximum current injection limit
6. This is the Electronic Control Unit (ECU) supply ramp rate and not directly the MCU ramp rate. Limit applies to both
maximum absolute maximum ramp rate and typical operating conditions.
7. This is the MCU supply ramp rate, and the ramp rate assumes that the HW design guidelines in AN5426 are followed.
Limit applies to both maximum absolute maximum ramp rate and typical operating conditions.
8. TJ (Junction temperature)=135 °C. Assumes TA=125 °C for RUN mode
TJ (Junction temperature)=125 °C. Assumes TA=105 °C for HSRUN mode
• Assumes maximum θJA for 2s2p board. See Thermal characteristics
9. 60 seconds lifetime; device in reset (no outputs enabled/toggling)
4.2 Voltage and current operating requirements
NOTE
Device functionality is guaranteed up to the LVR assert level;
however, electrical performance of 12-bit ADC, CMP with 8-
bit DAC, IO electrical characteristics, and communication
modules electrical characteristics would be degraded when
voltage drops below 2.7 V
Table 2. Voltage and current operating requirements 1
Symbol
Description
Min.
2.73
0
Max.
5.5
Unit
V
Notes
2
VDD
Supply voltage
4
VDD_OFF
Voltage allowed to be developed on VDD
pin when it is not powered from any
external power supply source.
0.1
V
VDDA
VDD – VDDA
VREFH
Analog supply voltage
2.7
– 0.1
2.7
5.5
0.1
V
V
4
4
5
VDD-to-VDDA differential voltage
ADC reference voltage high
ADC reference voltage low
Open drain pullup voltage level
VDDA + 0.1
0.1
V
VREFL
-0.1
VDD
-3
V
VODPU
VDD
V
6
7
IINJPAD_DC_OP
Continuous DC input current (positive /
negative) that can be injected into an I/O
pin
+3
mA
IINJSUM_DC_OP
Continuous total DC input current that can
be injected across all I/O pins such that
there's no degradation in accuracy of
analog modules: ADC and ACMP (See
section Analog Modules)
—
30
mA
1. Typical conditions assumes VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise
stated.
2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the
ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.
3. MWCT1016S will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged MWCT1016S is
guaranteed to operate from 2.97 V. All other MWCT101xS family devices operate from 2.7 V in all modes.
4. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC
only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for
reference supply design for SAR ADC.
MWCT101XS Data Sheet, Rev. 2, 07/2018
10
NXP Semiconductors
General
5. VREFH should always be equal to or less than VDDA + 0.1 V and VDD + 0.1 V
6. Open drain outputs must be pulled to VDD
.
7. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.
4.3 Thermal operating characteristics
Table 3. Thermal operating characteristics for 64-pin LQFP and 100-pin LQFP and MAPBGA
packages
Symbol
Parameter
Value
Typ.
—
Unit
Min.
−40
−40
−40
−40
−40
−40
Max.
851
TA C-Grade Part
TJ C-Grade Part
TA V-Grade Part
TJ V-Grade Part
TA M-Grade Part
TJ M-Grade Part
Ambient temperature under bias
Junction temperature under bias
Ambient temperature under bias
Junction temperature under bias
Ambient temperature under bias
Junction temperature under bias
℃
℃
℃
℃
℃
℃
—
1051
1051
1251
1252
1352
—
—
—
—
1. Values mentioned are measured at ≤ 112 MHz in HSRUN mode.
2. Values mentioned are measured at ≤ 80 MHz in RUN mode.
4.4 Power and ground pins
C
DEC
VDD
VDD
VDDA
VDD
VDD
VSS
VDDA
64 LQFP
Package
100 LQFP
Package
VREFH
VREFL
VSSA/VSS
VSS
VREFH
VREFL/VSSA/VSS
C
DEC
NOTE: VDD and VDDA must be shorted to a common source on PCB
Figure 4. Pinout decoupling
Table 4. Supplies decoupling capacitors 1, 2
Symbol
Description
Min. 3
Typ.
100
Max.
Unit
, 4
5
CREF
,
ADC reference high decoupling capacitance
70
—
nF
Table continues on the next page...
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
11
General
Table 4. Supplies decoupling capacitors 1, 2 (continued)
Symbol
Description
Min. 3
Typ.
Max.
Unit
CDEC5, 6, 7
Recommended decoupling capacitance
70
100
—
nF
1. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC
only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for
reference supply design for SAR ADC. All VSS pins should be connected to common ground at the PCB level.
2. All decoupling capacitors must be low ESR ceramic capacitors (for example X7R type).
3. Minimum recommendation is after considering component aging and tolerance.
4. For improved performance, it is recommended to use 10 μF, 0.1 μF and 1 nF capacitors in parallel.
5. All decoupling capacitors should be placed as close as possible to the corresponding supply and ground pins.
6. Contact your local Field Applications Engineer for details on best analog routing practices.
7. The filtering used for decoupling the device supplies must comply with the following best practices rules:
• The protection/decoupling capacitors must be on the path of the trace connected to that component.
• No trace exceeding 1 mm from the protection to the trace or to the ground.
• The protection/decoupling capacitors must be as close as possible to the input pin of the device (maximum 2 mm).
• The ground of the protection is connected as short as possible to the ground plane under the integrated circuit.
V
OSC
= 3.3 V nominal
FIRC
SIRC
SPLL
SOSC
ADC
CMP
V
= 1.2 V/1.4 V nominal
CORE
V
Flash
= 3.3 V nominal
PMC
Pads
System RAM
TCD RAM
I/D Cache
EEE RAM
Flash
LV SOG
GPIO
*Note: VSSA and VSS are shorted at package level
Figure 5. Power diagram
MWCT101XS Data Sheet, Rev. 2, 07/2018
12
NXP Semiconductors
General
4.5 LVR, LVD and POR operating requirements
Table 5. VDD supply LVR, LVD and POR operating requirements
Symbol
VPOR
Description
Min.
1.1
Typ.
1.6
Max.
2.0
Unit
V
Notes
Rising and falling VDD POR detect voltage
VLVR
LVR falling threshold (RUN, HSRUN, and
STOP modes)
2.50
2.58
2.7
V
LVR hysteresis
—
45
—
mV
1
VLVR_HYST
VLVR_LP
VLVD
LVR falling threshold (VLPS/VLPR modes)
Falling low-voltage detect threshold
LVD hysteresis
1.97
2.8
—
2.22
2.875
50
2.44
3
V
V
—
mV
1
1
VLVD_HYST
VLVW
VLVW_HYST
VBG
Falling low-voltage warning threshold
LVW hysteresis
4.19
—
4.305
75
4.5
—
V
mV
V
Bandgap voltage reference
0.97
1.00
1.03
1. Rising threshold is the sum of falling threshold and hysteresis voltage.
4.6 Power mode transition operating behaviors
All specifications in the following table assume this clock configuration:
• RUN Mode:
• Clock source: FIRC
• SYS_CLK/CORE_CLK = 48 MHz
• BUS_CLK = 48 MHz
• FLASH_CLK = 24 MHz
• HSRUN Mode:
• Clock source: SPLL
• SYS_CLK/CORE_CLK = 112 MHz
• BUS_CLK = 56 MHz
• FLASH_CLK = 28 MHz
• VLPR Mode:
• Clock source: SIRC
• SYS_CLK/CORE_CLK = 4 MHz
• BUS_CLK = 4 MHz
• FLASH_CLK = 1 MHz
• STOP1/STOP2 Mode:
• Clock source: FIRC
• SYS_CLK/CORE_CLK = 48 MHz
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
13
General
• BUS_CLK = 48 MHz
• FLASH_CLK = 24 MHz
• VLPS Mode: All clock sources disabled.
Table 6. Power mode transition operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
tPOR
After a POR event, amount of time from the point VDD
reaches 2.7 V to execution of the first instruction
across the operating temperature range of the chip.
—
325
—
μs
VLPS → RUN
8
—
0.075
0.075
—
17
0.08
0.08
26
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
STOP1 → RUN
0.07
0.07
19
STOP2 → RUN
VLPR → RUN
VLPR → VLPS
5.1
18.8
0.72
0.3
0.35
0.2
0.3
3.5
105
1
5.7
6.5
VLPS → VLPR
23
27.75
0.77
0.35
0.4
RUN → Compute operation
HSRUN → Compute operation
RUN → STOP1
0.75
0.31
0.38
0.23
0.35
3.8
RUN → STOP2
0.25
0.4
RUN → VLPS
RUN → VLPR
5
VLPS → Asynchronous DMA Wakeup
STOP1 → Asynchronous DMA Wakeup
STOP2 → Asynchronous DMA Wakeup
Pin reset → Code execution
110
1.1
125
1.3
1
1.1
1.3
—
214
—
NOTE
HSRUN should only be used when frequencies in excess of 80
MHz are required. When using 80 MHz and below, RUN mode
is the recommended operating mode.
4.7 Power consumption
The following table shows the power consumption targets for the device in various
modes of operation. Attached MWCT101xS_Power_Modes _Configuration.xlsx details
the modes used in gathering the power consumption data stated in the following table
Table 7. For full functionality refer to table: Module operation in available low power
modes of the Reference Manual.
MWCT101XS Data Sheet, Rev. 2, 07/2018
14
NXP Semiconductors
General
I d d / M ( z
P e e
P
5
P e e
P
P e
P
P e
P
P e e
P
P e e
P
6
A i
C h i p / D e v i
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
15
General
MWCT101XS Data Sheet, Rev. 2, 07/2018
16
NXP Semiconductors
I/O parameters
4.8 ESD handling ratings
Symbol
VHBM
Description
Min.
Max.
Unit
Notes
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
All pins except the corner pins
− 4000
4000
V
1
2
VCDM
− 500
− 750
− 100
500
750
100
V
V
Corner pins only
ILAT
Latch-up current at ambient temperature of 125 °C
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.9 EMC radiated emissions operating behaviors
EMC measurements to IC-level IEC standards are available from NXP on request.
5 I/O parameters
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 6. Input signal measurement reference
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
17
I/O parameters
5.2 General AC specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 8. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous path
50
—
—
ns
3
WFRST
RESET input filtered pulse
10
—
ns
ns
4
5
WNFRST RESET input not filtered pulse
Maximum of
(100 ns, bus
clock period)
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop and VLPS modes, the synchronizer is bypassed so shorter pulses can be recognized in
that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized.
4. Maximum length of RESET pulse which will be filtered by internal filter.
5. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter. This number depends on bus clock
period also. For example, in VLPR mode bus clock is 4 MHz, which make clock period of 250 ns. In this case, minimum
pulse width which will cause reset is 250 ns. For faster bus clock frequencies which have clock period less than 100 ns,
the minimum pulse width not filtered will be 100 ns.
5.3 DC electrical specifications at 3.3 V Range
NOTE
For details on the pad types defined in Table 9 and Table 10,
see Reference Manual section IO Signal Table and IO Signal
Description Input Multiplexing sheet(s) attached with
Reference Manual.
Table 9. DC electrical specifications at 3.3 V Range
Symbol
Parameter
Value
Typ.
3.3
—
Unit
Notes
Min.
2.7
Max.
VDD
Vih
I/O Supply Voltage
4
VDD + 0.3
0.3 × VDD
—
V
V
1
2
3
Input Buffer High Voltage
Input Buffer Low Voltage
Input Buffer Hysteresis
0.7 × VDD
VSS − 0.3
0.06 × VDD
3.5
Vil
—
V
Vhys
IohGPIO
—
V
I/O current source capability measured when
pad Voh = (VDD − 0.8 V)
—
—
mA
Table continues on the next page...
MWCT101XS Data Sheet, Rev. 2, 07/2018
18
NXP Semiconductors
I/O parameters
Table 9. DC electrical specifications at 3.3 V Range (continued)
Symbol
Parameter
Value
Typ.
Unit
Notes
Min.
Max.
IohGPIO-HD_DSE_0
IolGPIO
IolGPIO-HD_DSE_0
IohGPIO-HD_DSE_1
I/O current sink capability measured when
pad Vol = 0.8 V
3
—
—
mA
I/O current source capability measured when
pad Voh = (VDD − 0.8 V)
14
12
—
—
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
4
4
5
5
5
5
IolGPIO-HD_DSE_1
I/O current sink capability measured when
pad Vol = 0.8 V
IohGPIO-FAST_DSE_0 I/O current sink capability measured when
pad Voh=VDD-0.8 V
9.5
10
—
IolGPIO-FAST_DSE_0 I/O current sink capability measured when
pad Vol = 0.8 V
—
IohGPIO-FAST_DSE_1 I/O current sink capability measured when
pad Voh=VDD-0.8 V
16
—
IolGPIO-FAST_DSE_1 I/O current sink capability measured when
pad Vol = 0.8 V
15.5
—
—
IOHT
IIN
Output high current total for all ports
100
Input leakage current (per pin) for full temperature range at VDD = 3.3 V
6
All pins other than high drive port pins
High drive port pins
0.005
0.010
0.5
0.5
60
μA
μA
kΩ
kΩ
RPU
RPD
Internal pullup resistors
20
20
7
8
Internal pulldown resistors
60
1. MWCT1016S will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged MWCT1016S is
guaranteed to operate from 2.97 V. All other MWCT101xS family devices operate from 2.7 V in all modes.
2. For reset pads, same Vih levels are applicable
3. For reset pads, same Vil levels are applicable
4. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard
value given above.
5. For refernce only. Run simulations with the IBIS model and custom board for accurate results.
6. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
other GPIOs are normal drive only. For details refer to MWCT101xS_IO_Signal_Description_Input_Multiplexing.xlsx
attached with the Reference Manual.
7. Measured at input V = VSS
8. Measured at input V = VDD
5.4 DC electrical specifications at 5.0 V Range
Table 10. DC electrical specifications at 5.0 V Range
Symbol
Parameter
Value
Typ.
Unit
Notes
Min.
4
Max.
5.5
VDD
Vih
I/O Supply Voltage
Input Buffer High Voltage
—
—
V
V
0.65 x VDD
VDD + 0.3
1
Table continues on the next page...
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
19
I/O parameters
Symbol
Table 10. DC electrical specifications at 5.0 V Range (continued)
Parameter
Value
Typ.
Unit
Notes
Min.
VSS − 0.3
0.06 x VDD
5
Max.
0.35 x VDD
—
Vil
Input Buffer Low Voltage
Input Buffer Hysteresis
—
—
—
V
V
2
Vhys
Ioh_Standard I/O current source capability
—
mA
measured when pad Voh= (VDD - 0.8
V)
Iol_Standard I/O current sink capability measured
when pad Vol= 0.8 V
5
—
—
—
—
mA
mA
Ioh_Strong I/O current source capability
20
3, 4
4, 5
measured when pad Voh = VDD - 0.8
V
Iol_Strong I/O current sink capability measured
when pad Vol = 0.8 V
20
—
—
—
—
mA
mA
IOHT
IIN
Output high current total for all ports
100
Input leakage current (per pin) for full temperature range at VDD = 5.5 V
6
All pins other than high drive port
pins
0.005
0.5
μA
High drive port pins
0.010
0.5
50
50
μA
kΩ
kΩ
RPU
RPD
Internal pullup resistors
Internal pulldown resistors
20
20
7
8
1. For reset pads, same Vih levels are applicable
2. For reset pads, same Vil levels are applicable
3. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard
value given above.
4. The strong pad I/O pin is capable of switching a 50 pF load at up to 40 MHz.
5. The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_Standard value
given above.
6. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
other GPIOs are normal drive only. For details refer to MWCT101xS_IO_Signal_Description_Input_Multiplexing.xlsx
attached with the Reference Manual.
7. Measured at input V = VSS
8. Measured at input V = VDD
5.5 AC electrical specifications at 3.3 V range
Table 11. AC electrical specifications at 3.3 V Range
Symbol
DSE
Rise time (nS) 1
Fall time (nS) 1
Capacitance (pF) 2
Min.
Max.
14.5
23.7
80.0
14.5
Min.
Max.
15.7
26.2
88.4
15.7
tRFGPIO
NA
3.2
5.7
3.4
6.0
25
50
20.0
3.2
20.8
3.4
200
25
tRFGPIO-HD
0
Table continues on the next page...
MWCT101XS Data Sheet, Rev. 2, 07/2018
20
NXP Semiconductors
I/O parameters
Table 11. AC electrical specifications at 3.3 V Range (continued)
Symbol
DSE
Rise time (nS) 1
Fall time (nS) 1
Capacitance (pF) 2
Min.
Max.
23.7
80.0
5.8
Min.
Max.
26.2
88.4
6.1
5.7
20.0
1.5
2.4
6.3
0.6
3.0
12.0
0.4
1.5
7.4
6.0
20.8
1.7
50
200
25
1
0
1
8.0
2.6
8.3
50
22.0
2.8
6.0
23.8
2.8
200
25
tRFGPIO-FAST
0.5
7.1
2.6
7.5
50
27.0
1.3
10.3
0.38
1.4
26.8
1.3
200
25
3.8
3.9
50
14.9
7.0
15.3
200
1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be
different, for example for QSPI etc. . For protocol specific AC specifications, see respective sections.
5.6 AC electrical specifications at 5 V range
Table 12. AC electrical specifications at 5 V Range
Symbol
DSE
Rise time (nS)1
Fall time (nS) 1
Capacitance (pF) 2
Min.
Max .
9.4
Min.
Max.
10.7
17.4
59.7
10.7
17.4
59.7
5.0
tRFGPIO
NA
2.8
5.0
2.9
5.1
25
50
15.7
54.8
9.4
17.3
2.8
17.6
2.9
200
25
tRFGPIO-HD
0
1
0
1
5.0
15.7
54.8
4.6
5.1
50
17.3
1.1
17.6
1.1
200
25
2.0
5.7
2.0
5.8
50
5.4
16.0
2.2
5.0
16.0
2.2
200
25
tRFGPIO-FAST
0.42
2.0
0.37
1.9
5.0
5.2
50
9.3
18.8
0.9
8.5
19.3
0.9
200
25
0.37
1.2
0.35
1.2
2.7
2.9
50
6.0
11.8
6.0
12.3
200
1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be
different, for example for QSPI etc. . For protocol specific AC specifications, see respective sections.
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
21
I/O parameters
5.7 Standard input pin capacitance
Table 13. Standard input pin capacitance
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance: digital pins
—
7
pF
NOTE
Please refer to External System Oscillator electrical
specifications for EXTAL/XTAL pins.
5.8 Device clock specifications
Table 14. Device clock specifications 1
Symbol
Description
Min.
Max.
Unit
High Speed run mode2
Normal run mode (MWCT101xS series) 3
VLPR mode5
fSYS
fBUS
System and core clock
Bus clock
—
—
—
112
56
MHz
MHz
MHz
fFLASH
Flash clock
28
fSYS
fBUS
System and core clock
Bus clock
—
—
—
80
404
MHz
MHz
MHz
fFLASH
Flash clock
26.67
fSYS
fBUS
fFLASH
fERCLK
System and core clock
Bus clock
—
—
—
—
4
4
MHz
MHz
MHz
MHz
Flash clock
1
External reference clock
16
1. Refer to the section Feature comparison for the availability of modes and other specifications.
2. Only available on some devices. See section Feature comparison.
3. With SPLL as system clock source.
4. 48 MHz when fSYS is 48 MHz
5. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
MWCT101XS Data Sheet, Rev. 2, 07/2018
22
NXP Semiconductors
Peripheral operating requirements and behaviors
6 Peripheral operating requirements and behaviors
6.1 System modules
There are no electrical specifications necessary for the device's system modules.
6.2 Clock interface modules
6.2.1 External System Oscillator electrical specifications
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
23
Clock interface modules
Single input comparator
(EXTAL WAVE)
ref_clk
Mux
Differential input comparator
(HG/LP mode)
Peak detector
LP mode
Driver
(HG/LP mode)
Pull down resistor (OFF)
ESD PAD
280 ohms
ESD PAD
40 ohms
XTAL pin
EXTAL pin
Series resistor for current
limitation
1M ohms Feedback Resistor
Crystal or resonator
C1
C2
Figure 7. Oscillator connections scheme
Table 15. External System Oscillator electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
gmXOSC Crystal oscillator transconductance
4-8 MHz
2.2
16
—
—
—
—
13.7
47
mA/V
mA/V
V
8-40 MHz
VIL
VIH
Input low voltage — EXTAL pin in external clock mode
VSS
0.35 * VDD
VDD
Input high voltage — EXTAL pin in external clock
mode
0.7 * VDD
V
C1
C2
RF
EXTAL load capacitance
XTAL load capacitance
Feedback resistor
—
—
—
—
—
—
1
1
2
Low-gain mode (HGO=0)
—
—
—
MΩ
Table continues on the next page...
MWCT101XS Data Sheet, Rev. 2, 07/2018
24
NXP Semiconductors
Clock interface modules
Table 15. External System Oscillator electrical specifications
(continued)
Symbol Description
High-gain mode (HGO=1)
Series resistor
Min.
Typ.
Max.
Unit
Notes
—
1
—
MΩ
RS
Low-gain mode (HGO=0)
—
—
0
0
—
—
kΩ
kΩ
High-gain mode (HGO=1)
Vpp
Peak-to-peak amplitude of oscillation (oscillator mode)
Low-gain mode (HGO=0)
3
—
—
1.0
3.3
—
—
V
V
High-gain mode (HGO=1)
1. Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as:
gm_crit = 4 * ESR * (2πF)2 * (C0 + CL)2
where:
• gmXOSC is the transconductance of the internal oscillator circuit
• ESR is the equivalent series resistance of the external crystal
• F is the external crystal oscillation frequency
• C0 is the shunt capacitance of the external crystal
• CL is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)]
• Cs is stray or parasitic capacitance on the pin due to any PCB traces
• C1, C2 external load capacitances on EXTAL and XTAL pins
See manufacture datasheet for external crystal component values
2.
• When low-gain is selected, internal RF will be selected and external RF should not be attached.
• When high-gain is selected, external RF (1 M Ohm) needs to be connected for proper operation of the crystal. For
external resistor, up to 5% tolerance is allowed.
3. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.2.2 External System Oscillator frequency specifications
Table 16. External System Oscillator frequency specifications
Symbol Description
Min.
4
Typ.
—
Max.
40
Unit
MHz
MHz
%
Notes
fosc_hi
fec_extal
tdc_extal
tcst
Oscillator crystal or resonator frequency
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
Crystal Start-up Time
—
—
50
1
1
48
50
52
8 MHz low-gain mode (HGO=0)
8 MHz high-gain mode (HGO=1)
40 MHz low-gain mode (HGO=0)
40 MHz high-gain mode (HGO=1)
—
—
—
—
1.5
2.5
2
—
—
—
—
ms
2
2
1. Frequencies below 40 MHz can be used for degraded duty cycle up to 40-60%
2. Proper PC board layout procedures must be followed to achieve specifications.
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
25
System Clock Generation (SCG) specifications
6.2.3 System Clock Generation (SCG) specifications
6.2.3.1 Fast internal RC Oscillator (FIRC) electrical specifications
Table 17. Fast internal RC Oscillator electrical specifications
Symbol
Parameter1
Value
Typ.
48
Unit
Min.
Max.
FFIRC
FIRC target frequency
—
—
MHz
ΔF
Frequency deviation across process, voltage, and
temperature < 105°C
—
—
0.5
0.5
1
%FFIRC
ΔF125
Frequency deviation across process, voltage, and
temperature < 125°C
1.1
%FFIRC
TStartup
Startup time
3.4
250
0.04
5
µs2
ps
, 3
TJIT
Cycle-to-Cycle jitter
Long term jitter over 1000 cycles
—
—
500
0.1
3
TJIT
%FFIRC
1. With FIRC regulator enable
2. Startup time is defined as the time between clock enablement and clock availability for system use.
3. FIRC as system clock
NOTE
Fast internal RC Oscillator is compliant with CAN and LIN
standards.
6.2.3.2 Slow internal RC oscillator (SIRC) electrical specifications
Table 18. Slow internal RC oscillator (SIRC) electrical specifications
Symbol
Parameter
Value
Typ.
8
Unit
Min.
—
Max.
—
FSIRC
SIRC target frequency
MHz
ΔF
Frequency deviation across process, voltage, and
temperature < 105°C
—
—
3
%FSIRC
ΔF125
Frequency deviation across process, voltage, and
temperature < 125°C
—
—
—
9
3.3
%FSIRC
µs1
TStartup
Startup time
12.5
1. Startup time is defined as the time between clock enablement and clock availability for system use.
MWCT101XS Data Sheet, Rev. 2, 07/2018
26
NXP Semiconductors
Memory and memory interfaces
6.2.4 Low Power Oscillator (LPO) electrical specifications
Table 19. Low Power Oscillator (LPO) electrical specifications
Symbol
FLPO
Parameter
Internal low power oscillator frequency
Startup Time
Min.
113
—
Typ.
128
—
Max.
139
20
Unit
kHz
µs
Tstartup
6.2.5 SPLL electrical specifications
Table 20. SPLL electrical specifications
Symbol
Parameter
PLL Reference Frequency Range
PLL Input Frequency
Min.
8
Typ.
—
Max.
Unit
1
2
FSPLL_REF
16
40
MHz
MHz
MHz
MHz
FSPLL_Input
FVCO_CLK
FSPLL_CLK
JCYC_SPLL
8
—
VCO output frequency
180
90
—
320
160
PLL output frequency
PLL Period Jitter (RMS)3
—
at FVCO_CLK 180 MHz
—
—
120
75
—
—
ps
ps
at FVCO_CLK 320 MHz
JACC_SPLL
PLL accumulated jitter over 1µs (RMS)3
at FVCO_CLK 180 MHz
—
1350
600
—
—
—
ps
ps
%
s
at FVCO_CLK 320 MHz
—
DUNL
Lock exit frequency tolerance
TSPLL_LOCK Lock detector detection time4
4.47
—
5.97
150 × 10-6
+
—
1075(1/FSPLL_REF
)
1. FSPLL_REF is PLL reference frequency range after the PREDIV. For PREDIV and MULT settings refer SCG_SPLLCFG
register of Reference Manual.
2. FSPLL_Input is PLL input frequency range before the PREDIV must be limited to the range 8 MHz to 40 MHz. This input
source could be derived from a crystal oscillator or some other external square wave clock source using OSC bypass
mode. For external clock source settings refer SCG_SOSCCFG register of Reference Manual.
3. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each
PCB and results will vary
4. Lock detector detection time is defined as the time between PLL enablement and clock availability for system use.
6.3 Memory and memory interfaces
6.3.1 Flash memory module (FTFC) electrical specifications
This section describes the electrical characteristics of the flash memory module.
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
27
Memory and memory interfaces
6.3.1.1 Flash timing specifications — commands
Table 21. Flash command timing specifications
Symbol
Description1
MWCT1014S
Typ Max
MWCT1015S
Typ Max
MWCT1016S
Typ Max
Unit Notes
ms
trd1blk
Read 1 Block
execution time
32 KB flash
64 KB flash
128 KB flash
256 KB flash
512 KB flash
2 KB flash
4 KB flash
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
0.5
—
—
—
—
—
—
—
—
0.5
—
—
—
—
—
—
—
—
—
—
1.8
75
2
trd1sec
Read 1 Section
execution time
75
100
95
75
µs
100
95
100
100
tpgmchk
tpgm8
Program Check
execution time
µs
µs
ms
Program Phrase
execution time
—
90
225
90
225
90
225
tersblk
Erase Flash Block 32 KB flash
execution time
—
30
—
—
—
—
—
—
—
2
2
64 KB flash
550
—
30
—
550
—
—
—
128 KB flash
256 KB flash
—
—
—
—
—
—
—
512 KB flash 250
4250
130
250
12
4250
130
250
12
4250
130
tersscr
Erase Flash Sector —
execution time
12
ms
ms
tpgmsec1k
Program Section
execution time
(1KB flash)
—
5
—
5
—
5
—
trd1all
Read 1s All Block
execution time
—
—
—
—
—
—
2.3
30
—
5.2
30
—
—
—
90
8.2
30
ms
µs
µs
ms
µs
trdonce
tpgmonce
tersall
Read Once
execution time
—
—
Program Once
execution time
90
400
—
—
90
700
—
—
Erase All Blocks
execution time
4900
35
10000 1400
35
17000
35
2
tvfykey
Verify Backdoor
Access Key
—
execution time
tersallu
Erase All Blocks
Unsecure
execution time
—
400
70
4900
—
700
70
10000 1400
17000
—
ms
ms
2
3
tpgmpart
Program Partition 32 KB
for EEPROM
execution time
—
—
—
EEPROM
backup
64 KB
71
—
71
150
—
EEPROM
backup
Table continues on the next page...
MWCT101XS Data Sheet, Rev. 2, 07/2018
28
NXP Semiconductors
Memory and memory interfaces
Table 21. Flash command timing specifications (continued)
Symbol
Description1
MWCT1014S
Typ Max
Control Code 0.08
MWCT1015S
Typ Max
0.08
MWCT1016S
Typ Max
0.08
Unit Notes
tsetram
Set FlexRAM
Function execution 0xFF
—
—
—
—
ms
3
time
32 KB
EEPROM
backup
0.8
1
1.2
0.8
1
1.2
—
48 KB
EEPROM
backup
1.5
1.9
1.5
—
—
64 KB
EEPROM
backup
1.3
385
430
475
385
430
475
360
1.3
385
430
475
385
430
475
360
1.9
1.3
—
1.9
—
teewr8b
Byte write to
32 KB
1700
1850
2000
1700
1850
2000
2000
1700
1850
2000
1700
1850
2000
2000
µs
3,4
FlexRAM execution EEPROM
time
backup
48 KB
EEPROM
backup
—
—
64 KB
EEPROM
backup
475
—
4000
—
teewr16b
16-bit write to
32 KB
µs
3,4
FlexRAM execution EEPROM
time
backup
48 KB
EEPROM
backup
—
—
64 KB
EEPROM
backup
475
360
4000
2000
teewr32bers
32-bit write to
erased FlexRAM
location execution
time
—
µs
µs
teewr32b
32-bit write to
FlexRAM execution EEPROM
time
32 KB
630
720
810
2000
2125
2250
630
720
810
2000
2125
2250
—
—
3,4
backup
48 KB
EEPROM
backup
—
—
64 KB
810
4500
EEPROM
backup
tquickwr
32-bit Quick Write 1st 32-bit write 200
execution time:
Time from CCIF
clearing (start the
write) until CCIF
setting (32-bit write
550
550
200
150
550
550
200
150
1100
550
µs
4,5,6
2nd through
Next to Last
(Nth-1) 32-bit
write
150
Table continues on the next page...
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
29
Memory and memory interfaces
Table 21. Flash command timing specifications (continued)
Symbol
Description1
MWCT1014S
Typ Max
550
MWCT1015S
Typ Max
200 550
MWCT1016S
Typ Max
200 550
Unit Notes
complete, ready for
Last (Nth) 32- 200
bit write (time
next 32-bit write)
for write only,
not cleanup)
tquickwrClnup
Quick Write
Cleanup execution
time
—
—
(# of
—
(# of
—
(# of
ms
7
Quick
Writes ) *
2.0
Quick
Writes )
* 2.0
Quick
Writes )
* 2.0
1. All command times assumes 25 MHz or greater flash clock frequency (for synchronization time between internal/external
clocks).
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred. This may
be verified by executing FCCOB Command 0x77, and checking FCCOB number 5 contents show 0x00 - No EEPROM
issues detected.
4. 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2× the
times shown.
5. Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur
after this point even after a brownout or reset. If power on reset occurs before the Nth write completes, the last valid record
set will still be valid and the new records will be discarded.
6. Quick Write times may take up to 550 µs, as additional cleanup may occur when crossing sector boundaries.
7. Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes,
assuming still powered. Or via SETRAM cleanup execution command is requested at a later point.
NOTE
Under certain circumstances FlexMEM maximum times may be
exceeded. In this case the user or application may wait, or assert
reset to the FTFC macro to stop the operation.
6.3.1.2 Reliability specifications
Table 22. NVM reliability specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
When using as Program and Data Flash
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
20
—
—
—
—
years
1
1 K
cycles
2, 3
When using FlexMemory feature: FlexRAM as Emulated EEPROM
tnvmretee Data retention
5
—
—
years
4
Write endurance
nnvmwree16
5, 6, 7
100 K
1.6 M
—
—
—
—
writes
writes
• EEPROM backup to FlexRAM ratio = 16
nnvmwree256
• EEPROM backup to FlexRAM ratio = 256
1. Data retention period per block begins upon initial user factory programming or after each subsequent erase.
2. Program and Erase for PFlash and DFlash are supported across product temperature specification in Normal Mode (not
supported in HSRUN mode).
3. Cycling endurance is per DFlash or PFlash Sector.
4. Data retention period per block begins upon initial user factory programming or after each subsequent erase. Background
maintenance operations during normal FlexRAM usage extend effective data retention life beyond 5 years.
MWCT101XS Data Sheet, Rev. 2, 07/2018
30
NXP Semiconductors
Memory and memory interfaces
5. FlexMemory write endurance specified for 16-bit and/or 32-bit writes to FlexRAM and is supported across product
temperature specification in Normal Mode (not supported in HSRUN mode). Greater write endurance may be achieved
with larger ratios of EEPROM backup to FlexRAM.
6. For usage of any EEE driver other than the FlexMemory feature, the endurance spec will fall back to the specified
endurance value of the D-Flash specification (1K).
7. FlexMemory calculator tool is available at NXP web site for help in estimation of the maximum write endurance achievable
at specific EEPROM/FlexRAM ratios. The “In Spec” portions of the online calculator refer to the NVM reliability
specifications section of data sheet. This calculator is only applies to the FlexMemory feature.
6.3.2 QuadSPI AC specifications
The following table describes the QuadSPI electrical characteristics.
• Measurements are with maximum output load of 25 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
• Add 50 ohm series termination on board in QuadSPI SCK for Flash A to avoid loop
back reflection when using in Internal DQS (PAD Loopback) mode.
• QuadSPI trace length should be 3 inches.
• For non-Quad mode of operation if external device doesn’t have pull-up feature,
external pull-up needs to be added at board level for non-used pads.
• With external pull-up, performance of the interface may degrade based on load
associated with external pull-up.
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
31
Memory and memory interfaces
1 / f S C K
1 / f S C K
1 / f S C K
1 / f S C K
1 / f S C K
1 / f S C K
MWCT101XS Data Sheet, Rev. 2, 07/2018
32
NXP Semiconductors
Memory and memory interfaces
t S C
t S C 5
t S C
t S C 5
t S C
t S C 5
t -
t -
t S C
t S C 5
t S C
t S C
t S C
t S C 5
t S C
t S C 5
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
33
Memory and memory interfaces
1
2
3
Clock
tSCK
tSDC
tSDC
SCK
CS
tIH
tIS
Data in
Figure 8. QuadSPI input timing (SDR mode) diagram
1
2
3
Clock
SCK
CS
tSCK
tSDC
tSDC
tSCKCS
tCSSCK
tIV
tOV
Invalid
Data out
Figure 9. QuadSPI output timing (SDR mode) diagram
TIS
TIS
TIH
TIH
invalid
invalid
D1
invalid
invalid
D4
D5
D2
D3
TIS– Setup Time
Figure 10. QuadSPI input timing (HyperRAM mode) diagram
MWCT101XS Data Sheet, Rev. 2, 07/2018
34
NXP Semiconductors
Analog modules
CK
tIV
tOV
Output Invalid Data
Figure 11. QuadSPI output timing (HyperRAM mode) diagram
6.4 Analog modules
6.4.1 ADC electrical specifications
6.4.1.1 12-bit ADC operating conditions
Table 24. 12-bit ADC operating conditions
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit Notes
VREFH ADC reference voltage high
See Voltage
and current
operating
VDDA
See Voltage
and current
operating
V
2
requirements
for values
requirements
for values
VREFL ADC reference voltage low
See Voltage
and current
operating
0
See Voltage mV
and current
operating
2
requirements
for values
requirements
for values
VADIN Input voltage
VREFL
—
—
—
VREFH
5
V
RS
Source impedendance
fADCK < 4 MHz
kΩ
kΩ
RSW1
Channel Selection Switch
Impedance
—
0.75
1.2
RAD
CP1
CP2
CS
Sampling Switch Impedance
Pin Capacitance
—
—
—
—
2
10
—
4
5
—
4
kΩ
pF
pF
pF
Analog Bus Capacitance
Sampling capacitance
5
Table continues on the next page...
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
35
ADC electrical specifications
Table 24. 12-bit ADC operating conditions (continued)
Symbol Description
fADCK ADC conversion clock
frequency
fCONV ADC conversion frequency
Conditions
Min.
Typ.1
Max.
Unit Notes
Normal usage
2
40
50
MHz
3, 4
No ADC hardware
averaging.5 Continuous
conversions enabled,
subsequent conversion
time
46.4
1.45
928
29
1160
Ksps
6, 7
ADC hardware averaging
set to 32. 5 Continuous
conversions enabled,
subsequent conversion
time
36.25
Ksps
6, 7
1. Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated.
Typical values are for reference only, and are not tested in production.
2. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSS
.
To get maximum performance, reference supply quality should be better than SAR ADC. See application note AN5032 for
details.
3. Clock and compare cycle need to be set according to the guidelines mentioned in the Reference Manual .
4. ADC conversion will become less reliable above maximum frequency.
5. When using ADC hardware averaging, see the Reference Manual to determine the most appropriate setting for AVGS.
6. Numbers based on the minimum sampling time of 275 ns.
7. For guidelines and examples of conversion rate calculation, see the Reference Manual or download the ADC calculator
tool.
Figure 12. ADC input impedance equivalency diagram
MWCT101XS Data Sheet, Rev. 2, 07/2018
36
NXP Semiconductors
ADC electrical specifications
6.4.1.2 12-bit ADC electrical characteristics
NOTE
• ADC performance specifications are documented using a
single ADC. For parallel/simultaneous operation of both
ADCs, either for sampling the same channel by both ADCs
or for sampling different channels by each ADC, some
amount of decrease in performance can be expected. Care
must be taken to stagger the two ADC conversions, in
particular the sample phase, to minimize the impact of
simultaneous conversions.
• On reduced pin packages where ADC reference pins are
shared with supply pins, ADC analog performance
characteristics may be impacted. The amount of variation
will be directly impacted by the external PCB layout and
hence care must be taken with PCB routing. See AN5426
for details
Table 25. 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL = VSS)
Symbol Description
VDDA Supply voltage
Conditions 1
Min.
2.7
—
Typ.2
Max.
3
Unit
V
Notes
—
IDDA_ADC Supply current per ADC
SMPLTS Sample Time
0.6
—
—
mA
ns
3
275
Refer to
the
Reference
Manual
TUE4
DNL
INL
Total unadjusted error
Differential non-linearity
Integral non-linearity
—
—
—
4
8
—
—
LSB5
LSB5
LSB5
6, 7, 8, 9
6, 7, 8, 9
6, 7, 8, 9
1.0
2.0
1. All accuracy numbers assume the ADC is calibrated with VREFH=VDDA=VDD, with the calibration frequency set to less than
or equal to half of the maximum specified ADC clock frequency.
2. Typical values assume VDDA = 3 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF.
3. The ADC supply current depends on the ADC conversion rate.
4. Represents total static error, which includes offset and full scale error.
5. 1 LSB = (VREFH - VREFL)/2N
6. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device
use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings
for AVGS.
7. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC
performance may be observed.
8. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the
internal analog parameters, assume minor degradation.
9. All the parameters in the table are given assuming system clock as the clocking source for ADC.
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
37
ADC electrical specifications
Table 26. 12-bit ADC characteristics (3 V to 5.5 V)(VREFH = VDDA, VREFL = VSS)
Symbol Description
VDDA Supply voltage
Conditions 1
Min.
3
Typ.2
Max.
5.5
Unit
V
Notes
—
IDDA_ADC Supply current per ADC
SMPLTS Sample Time
—
1
—
mA
ns
3
275
—
Refer to
the
Reference
Manual
TUE4
DNL
INL
Total unadjusted error
Differential non-linearity
Integral non-linearity
—
—
—
4
8
—
—
LSB5
LSB5
LSB5
6, 7, 8, 9
6, 7, 8, 9
6, 7, 8, 9
0.7
1.0
1. All accuracy numbers assume the ADC is calibrated with VREFH=VDDA=VDD, with the calibration frequency set to less than
or equal to half of the maximum specified ADC clock frequency.
2. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated.
3. The ADC supply current depends on the ADC conversion rate.
4. Represents total static error, which includes offset and full scale error.
5. 1 LSB = (VREFH - VREFL)/2N
6. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device
use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings
for AVGS.
7. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC
performance may be observed.
8. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the
internal analog parameters, assume minor degradation.
9. All the parameters in the table are given assuming system clock as the clocking source for ADC.
NOTE
• Due to triple bonding in lower pin packages like the 64-
LQFP, degradation might be seen in ADC parameters.
• When using high speed interfaces such as the QuadSPI,
there may be some ADC degradation on the adjacent
analog input paths. See following table for details.
Pin name
PTE8
TGATE purpose
CMP0_IN3
PTC3
ADC0_SE11/CMP0_IN4
ADC0_SE10/CMP0_IN5
CMP0_IN6
PTC2
PTD7
PTD6
CMP0_IN7
PTD28
PTD27
ADC1_SE22
ADC1_SE21
MWCT101XS Data Sheet, Rev. 2, 07/2018
38
NXP Semiconductors
ADC electrical specifications
6.4.2 CMP with 8-bit DAC electrical specifications
Table 28. Comparator with 8-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
IDDHS
Supply current, High-speed mode1
μA
-40 - 125 ℃
—
230
300
IDDLS
Supply current, Low-speed mode1
-40 - 105 ℃
μA
—
6
6
11
13
-40 - 125 ℃
VAIN
VAIO
Analog input voltage
Analog input offset voltage, High-speed mode
-40 - 125 ℃
0
0 - VDDA
VDDA
V
mV
-25
-40
—
1
4
25
40
VAIO
Analog input offset voltage, Low-speed mode
mV
ns
-40 - 125 ℃
tDHSB
Propagation delay, High-speed mode2
-40 - 105 ℃
35
35
200
300
-40 - 125 ℃
tDLSB
tDHSS
tDLSS
Propagation delay, Low-speed mode2
µs
ns
µs
-40 - 105 ℃
—
—
0.5
0.5
2
3
-40 - 125 ℃
Propagation delay, High-speed mode3
-40 - 105 ℃
—
—
70
70
400
500
-40 - 125 ℃
Propagation delay, Low-speed mode3
-40 - 105 ℃
—
—
1
1
5
5
-40 - 125 ℃
tIDHS
Initialization delay, High-speed mode4
μs
μs
-40 - 125 ℃
—
—
—
1.5
10
0
3
tIDLS
Initialization delay, Low-speed mode4
-40 - 125 ℃
30
—
VHYST0
Analog comparator hysteresis, Hyst0
-40 - 125 ℃
mV
mV
VHYST1
Analog comparator hysteresis, Hyst1, High-speed
mode
-40 - 125 ℃
—
—
—
19
15
34
66
40
Analog comparator hysteresis, Hyst1, Low-speed
mode
-40 - 125 ℃
VHYST2
Analog comparator hysteresis, Hyst2, High-speed
mode
mV
-40 - 125 ℃
133
Table continues on the next page...
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
39
ADC electrical specifications
Table 28. Comparator with 8-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Analog comparator hysteresis, Hyst2, Low-speed
mode
-40 - 125 ℃
—
23
80
VHYST3
Analog comparator hysteresis, Hyst3, High-speed
mode
mV
-40 - 125 ℃
—
46
200
120
Analog comparator hysteresis, Hyst3, Low-speed
mode
-40 - 125 ℃
—
32
IDAC8b
8-bit DAC current adder (enabled)
3.3V Reference Voltage
—
—
6
9
16
μA
μA
LSB6
LSB6
μs
5V Reference Voltage
10
—
—
—
INL5
DNL
tDDAC
8-bit DAC integral non-linearity
8-bit DAC differential non-linearity
Initialization and switching settling time
–0.75
–0.5
—
0.75
0.5
30
1. Difference at input > 200mV
2. Applied (100 mV + VHYST0/1/2/3+ max. of VAIO) around switch point.
3. Applied (30 mV + 2 × VHYST0/1/2/3+ max. of VAIO) around switch point.
4. Applied (100 mV + VHYST0/1/2/3).
5. Calculation method used: Linear Regression Least Square Method
6. 1 LSB = Vreference/256
NOTE
For comparator IN signals adjacent to VDD/VSS or XTAL/
EXTAL or switching pins cross coupling may happen and
hence hysteresis settings can be used to obtain the desired
comparator performance. Additionally, an external capacitor
(1nF) should be used to filter noise on input signal. Also, source
drive should not be weak (Signal with < 50 K pull up/down is
recommended).
MWCT101XS Data Sheet, Rev. 2, 07/2018
40
NXP Semiconductors
ADC electrical specifications
Figure 13. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 0)
Figure 14. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 1)
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
41
ADC electrical specifications
Figure 15. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 0)
Figure 16. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 1)
MWCT101XS Data Sheet, Rev. 2, 07/2018
42
NXP Semiconductors
Communication modules
6.5 Communication modules
6.5.1 LPUART electrical specifications
Refer to General AC specifications for LPUART specifications.
6.5.1.1 Supported baud rate
Baud rate = Baud clock / ((OSR+1) * SBR).
For details, see section: 'Baud rate generation' of the Reference Manual.
6.5.2 LPSPI electrical specifications
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable. The
following tables provide timing characteristics for classic LPSPI timing modes.
• All timing is shown with respect to 20% VDD and 80% VDD thresholds.
• All measurements are with maximum output load of 50 pF, input transition of 1 ns
and pad configured with fastest slew setting ( DSE = 1 ).
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
43
Communication modules
p e r i p h
p e r i p h
- 5 0
- 5 0
( P C S S C K + 1 ) * t
( P C S S C K + 1 ) * t
p e r i p h
- 2 5
- 2 5
( P C S S C K + 1 ) * t
( P C S S C K + 1 ) * t
p e r i p h
p e r i p h
- 2 5
- 2 5
( P C S S C K + 1 ) * t
( P C S S C K + 1 ) * t
p e r i p h
MWCT101XS Data Sheet, Rev. 2, 07/2018
44
NXP Semiconductors
Communication modules
S P S C K
/ 2 + 5 t
p e r i p h
p e r i p h
- 5 0
- 5 0
( / 2 - 5 S t P S C K
S P S C K
/ 2 + 5 t
( / 2 - 5 S t P S C K
S P S C K
/ 2 + 3 t
p e r i p h
- 2 5
- 2 5
( / 2 - 3 S t P S C K
S P S C K
/ 2 + 3 t
p e r i p h
( / 2 - 3 S t P S C K
S P S C K
/ 2 + 3 t
p e r i p h
- 2 5
- 2 5
( / 2 - 3 S t P S C K
S P S C K
/ 2 + 3 t
p e r i p h
( / 2 - 3 S t P S C K
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
45
Communication modules
MWCT101XS Data Sheet, Rev. 2, 07/2018
46
NXP Semiconductors
Communication modules
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
47
Communication modules
1
SS
(OUTPUT)
3
2
12
12
13
13
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
MSB IN
LSB IN
10
11
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. LPSPI master mode timing (CPHA = 0)
1
SS
(OUTPUT)
2
12
12
13
13
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
11
BIT 6 . . . 1
10
MOSI
(OUTPUT)
2
PORT DATA
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. LPSPI master mode timing (CPHA = 1)
MWCT101XS Data Sheet, Rev. 2, 07/2018
48
NXP Semiconductors
Communication modules
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
See
note1
See
note 1
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
Notes:
1. Undefined
Figure 19. LPSPI slave mode timing (CPHA = 0)
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
See
note 1
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
Notes:
1. Undefined
Figure 20. LPSPI slave mode timing (CPHA = 1)
6.5.3 LPI2C electrical specifications
See General AC specifications for LPI2C specifications.
For supported baud rate see section 'Chip-specific LPI2C information' of the Reference
Manual.
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
49
Debug modules
6.5.4 FlexCAN electical specifications
For supported baud rate, see section 'Protocol timing' of the Reference Manual.
6.5.5 Clockout frequency
Maximum supported clock out frequency for this device is 20 MHz
6.6 Debug modules
6.6.1 SWD electrical specofications
MWCT101XS Data Sheet, Rev. 2, 07/2018
50
NXP Semiconductors
Debug modules
S
S
S
S
S
S
S
S
S
S
S
S
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
51
Debug modules
S2
S4
S3
S3
SWD_CLK (input)
S4
Figure 21. Serial wire clock input timing
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
S9
S10
Input data valid
S11
S13
Output data valid
S12
Figure 22. Serial wire data timing
6.6.2 Trace electrical specifications
The following table describes the Trace electrical characteristics.
• Measurements are with maximum output load of 50 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
Table 31. Trace specifications
Symbol
Description
RUN Mode
HSRUN Mode
112 80
VLPR
Mode
Unit
—
Fsys
System frequency
80
48
40
4
MHz
Table continues on the next page...
MWCT101XS Data Sheet, Rev. 2, 07/2018
52
NXP Semiconductors
Debug modules
Table 31. Trace specifications (continued)
Symbol
Description
RUN Mode
HSRUN Mode
VLPR
Unit
Mode
fTRACE
Max Trace frequency
Data Output Valid
Data Output Invalid
80
48
4
40
4
74.667
80
4
4
MHz
ns
tDVO
tDIV
4
4
20
-2
-2
-2
-2
-2
-10
ns
fTRACE
tDVO
tDIV
Max Trace frequency
Data Output Valid
Data Output Invalid
22.86
24
8
20
8
22.4
8
22.86
8
4
MHz
ns
8
20
-10
-4
-4
-4
-4
-4
ns
Figure 23. TRACE CLKOUT specifications
6.6.3 JTAG electrical specifications
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
53
Debug modules
J
J -
J
J -
J
J -
J
J -
J
J -
J
J -
MWCT101XS Data Sheet, Rev. 2, 07/2018
54
NXP Semiconductors
Debug modules
J2
J4
J3
J3
TCLK (input)
J4
Figure 24. Test clock input timing
TCLK
J5
J6
Input data valid
Data inputs
J7
J8
Output data valid
Data outputs
Data outputs
J9
Figure 25. Boundary scan (JTAG) timing
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
55
Thermal attributes
TCLK
J10
J11
Input data valid
TDI/TMS
J12
J13
Output data valid
TDO
TDO
J14
Figure 26. Test Access Port timing
7 Thermal attributes
7.1 Description
The tables in the following sections describe the thermal characteristics of the device.
NOTE
Junction temperature is a function of die size, on-chip power
dissipation, package thermal resistance, mounting side (board)
temperature, ambient temperature, air flow, power dissipation
or other components on the board, and board thermal resistance.
7.2 Thermal characteristics
MWCT101XS Data Sheet, Rev. 2, 07/2018
56
NXP Semiconductors
Thermal attributes
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
57
Thermal attributes
MWCT101XS Data Sheet, Rev. 2, 07/2018
58
NXP Semiconductors
Thermal attributes
7.3 General notes for specifications at maximum junction
temperature
An estimation of the chip junction temperature, TJ, can be obtained from this equation:
where:
• TA = ambient temperature for the package (°C)
• RθJA = junction to ambient thermal resistance (°C/W)
• PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by
a factor of two. Which value is closer to the application depends on the power dissipated
by other components on the board. The value obtained on a single layer board is
appropriate for the tightly packed printed circuit board. The value obtained on the board
with the internal planes is usually appropriate if the board has low power dissipation and
the components are well separated.
When a heat sink is used, the thermal resistance is expressed in the following equation as
the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:
where:
• RθJA = junction to ambient thermal resistance (°C/W)
• RθJC = junction to case thermal resistance (°C/W)
• RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal
environment to change the case to ambient thermal resistance, RθCA. For instance, the
user can change the size of the heat sink, the air flow around the device, the interface
material, the mounting arrangement on printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device.
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
59
Dimensions
To determine the junction temperature of the device in the application when heat sinks
are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using this equation:
where:
• TT = thermocouple temperature on top of the package (°C)
• ΨJT = thermal characterization parameter (°C/W)
• PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a
40 gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
8 Dimensions
8.1 Obtaining package dimensions
Package dimensions are provided in the package drawings.
To find a package drawing, go to http://www.nxp.com and perform a keyword search for
the drawing’s document number:
Package option
64-pin LQFP
Document Number
98ASS23234W
98ASS23308W
98ASA00802D
100-pin LQFP
100-pin MAPBGA
MWCT101XS Data Sheet, Rev. 2, 07/2018
60
NXP Semiconductors
Pinouts
9 Pinouts
9.1 Package pinouts and signal descriptions
For package pinouts and signal descriptions, refer to the Reference Manual.
10 Revision History
The following table provides a revision history for this document.
Table 35. Revision History
Rev. No.
Rev. 0
Date
Substantial Changes
May 2017
Dec 2017
• Initial release.
Rev. 1
• In "Feature comparison" section, updated the "MWCT101xS product
series comparison" figure.
• In Table 1,
• Updated note 'All the limits defined ... '
• Updated parameter 'IINJPAD_DC_ABS', 'VIN_DC', IINJSUM_DC_ABS
• In Table 2,
.
• Updated min. value of VDD_OFF
• Added parameter IINJPAD_DC_OP and IINJSUM_DC_OP
.
• Updated footnote to TSPLL_LOCK and removed IDDSPLL in "SPLL
electrical specifications" table.
• In "12-bit ADC electrical characteristics" section,
• Updated table: 12-bit ADC characteristics (2.7 V to 3 V)
(VREFH = VDDA, VREFL = VSS)
• Added typ. value to IDDA_ADC, TUE, DNL, and INL
• Added min. value to SMPLTS
• Removed footnote 'All the parameters in this table ... '
• Updated table: 12-bit ADC characteristics (3 V to 5.5 V)
(VREFH = VDDA, VREFL = VSS)
• Added typ. value to IDDA_ADC
• Removed footnote 'All the parameters in this table ... '
• In "Flash command timing specifications" table, updated Max. value
of tvfykey to 35 μs
• Updated "MWCT101xS product series comparison" figure.
• In Table 5, updated TBDs for VLVR_HYST, VLVD_HYST, and VLVW_HYST
• In Power mode transition operating behaviors,
• Added VLPR → VLPS
• Added VLPS → VLPR
• Updated TBDs for VLPS → Asynchronous DMA Wakeup,
STOP1 → Asynchronous DMA Wakeup, and STOP2 →
Asynchronous DMA Wakeup
• In Table 7, updated the specifications for MWCT1014S.
• Updated the attachment MWCT101xS_Power_Modes
_Configuration.xlsx.
• In "Standard input pin capacitance" table, removed CIN_A
.
• In "External System Oscillator electrical specifications" table,
Table continues on the next page...
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
61
Revision History
Rev. No.
Table 35. Revision History (continued)
Date
Substantial Changes
• Updated specifications for gmXOSC
• Removed IDDOSC
.
• In "Fast internal RC Oscillator (FIRC) electrical specifications"
section,
• Added parameter ΔF125.
• Removed IDDFIRC
• In "Slow internal RC oscillator (SIRC) electrical specifications"
section,
• Added parameter ΔF125.
• Removed IDDSIRC
• In "Low Power Oscillator (LPO) electrical specifications" section,
removed ILPO
• Updated section: "Flash memory module (FTFC) electrical
specifications"
• In section: "12-bit ADC electrical characteristics",
• Updated TBDs in Table 25.
• Updated TBDs in Table 26.
• In section: QuadSPI AC specifications, updated figure 'QuadSPI
output timing (HyperRAM mode) diagram'.
• In section: "ADC electrical specifications", updated Table 24.
• In section: "CMP with 8-bit DAC electrical specifications", added
note 'For comparator IN signals adjacent ... '
• In table: "LPSPI electrical specifications", minor update in footnote 6.
• In table: Table 33, updated specifications for MWCT1015S.
Rev. 2
July 2018
• Global update: removed Ethernet and SAI
• Updated the attachment MWCT101xS_Power_Modes
_Configuration.xlsx
• In 'Key features':
• Added a note under 'Power management', 'Memory and
memory interfaces', and 'Safety and security'
• Updated FlexIO under Communications interfaces
• Updated Cryptographic Services Engine (CSEc) under 'Safety
and security'
• Updated package information
• In High-level architecture diagram for the MWCT101xS family,
added footnote 3
• In "Feature comparison" section, updated the "MWCT101xS product
series comparison" figure:
• Updated the "System RAM" row
• Added support for LIN protocol version 2.2 A
• Updated the Ecosystem information
• Updated the Package information
• Updated the Legend notes
• Updated Ordering information
• In Absolute maximum ratings :
• Updated the NOTE section
• Added parameter 'Tramp_MCU
• Updated footnote for 'Tramp
'
'
• Updated Voltage and current operating requirements
• In Power and ground pins
• Removed the 144-pin LQFP package
• Updated footnote 'VDD and VDDA must be shorted ...'
• Updated the "Power diagram" figure
• In Power mode transition operating behaviors updated numbers for:
• VLPR → VLPS
MWCT101XS Data Sheet, Rev. 2, 07/2018
62
NXP Semiconductors
Revision History
Table 35. Revision History
Rev. No.
Date
Substantial Changes
• VLPS → VLPR
• RUN → VLPS
• RUN → VLPR
• In Power consumption :
• Updated specs
• Removed section 'Modes configuration', amd moved its
content under the fisrt paragraph.
• Updated footnote 'Typical current numbers are indicative ...'
• Updated footnote 'The MWCT1016S data ...'
• Removed footnote 'Above MWCT1016S data is preliminary
targets only'
• In General AC specifications :
• Updated max value and footnote of WFRST
• Updated symbol for not filtered pulse to 'WNFRST', updated
min value, removed max. value, and added footnote
• Fixed naming conventions to align with DS in DC electrical
specifications at 3.3 V Range and DC electrical specifications at 5.0
V Range
• Updated specs for AC electrical specifications at 3.3 V range and
AC electrical specifications at 5 V range
• In Device clock specifications :
• Added footnote to fBUS
• In External System Oscillator frequency specifications :
• Updated 'tdc_extal
'
• Added footnote 'Frequecies below ... ' to 'fec_extal' and 'tdc_extal
• Updated Flash timing specifications — commands
• In Reliability specifications :
'
• Updated footnotes
• In QuadSPI AC specifications :
• Updated 'MCR[SCLKCFG[5]]' value to 0
• Updated 'Data Input Setup Time' HSRUN Internal DQS PAD
Loopback value to 1.6
• Updated 'Data Input Setup Time' DDR External DQS min.
value to 2
• Updated 'Data Input Hold Time' DDR External DQS min. value
to 20
• Updated tIV
• Upadted figure 'QuadSPI output timing (SDR mode) diagram'
and 'QuadSPI input timing (HyperRAM mode) diagram'
• In 12-bit ADC operating conditions :
• Fixed the typo in RSW1
• Removed parameter 'ΔVDDA
'
• In 12-bit ADC electrical characteristics :
• Added note 'On reduced pin packages where ... '
• Removed max. value of 'IDDA_ADC
• Added note 'Due to triple ... '
'
• In CMP with 8-bit DAC electrical specifications :
• Updated Typ. and Max. values of 'IDDLS
• Upadted Typ. value of 'tDHSB
'
'
• Updated Typ. value of 'VHYST1' , 'VHYST2', and 'VHYST3
• In LPSPI electrical specifications :
'
• Updated 'fperiph' and 'fop', and 'tSPSCK
'
• Updated 3.3 V numbers and added footnote against fop, tSU
ans tV in HSRUN Mode
,
• Added footnote to 'tWSPSCK
'
MWCT101XS Data Sheet, Rev. 2, 07/2018
NXP Semiconductors
63
Revision History
Rev. No.
Table 35. Revision History
Date
Substantial Changes
• Updated tLead and tLag
• Added footnote in Figure: LPSPI slave mode timing (CPHA =
0) and Figure: LPSPI slave mode timing (CPHA = 1)
• In Thermal characteristics :
• Updated table name for the LQFP packages
• Added table for the BGA package
• Updated Obtaining package dimensions
MWCT101XS Data Sheet, Rev. 2, 07/2018
64
NXP Semiconductors
How to Reach Us:
Information in this document is provided solely to enable system and software implementers to use
NXP products. There are no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits based on the information in this document. NXP reserves the right to
make changes without further notice to any products herein.
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any
particular purpose, nor does NXP assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets
and/or specifications can and do vary in different applications, and actual performance may vary over
time. All operating parameters, including “typicals,” must be validated for each customer application
by customerʼs technical experts. NXP does not convey any license under its patent rights nor the
rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions.
While NXP has implemented advanced security features, all products may be subject to unidentified
vulnerabilities. Customers are responsible for the design and operation of their applications and
products to reduce the effect of these vulnerabilities on customer's applications and products, and
NXP accepts no liability for any vulnerability that is discovered. Customers should implement
appropriate design and operating safeguards to minimize the risks associated with their applications
and products.
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX,
EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE, JCOP, LIFE VIBES, MIFARE, MIFARE
CLASSIC, MIFARE DESFire, MIFARE PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT,
MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET,
TRENCHMOS, UCODE, Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior,
ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, Layerscape, MagniV,
mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, Ready Play, SafeAssure,
the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast, BeeKit, BeeStack, CoreNet,
Flexis, MXC, Platform in a Package, QUICC Engine, SMARTMOS, Tower, TurboLink, and UMEMS
are trademarks of NXP B.V. All other product or service names are the property of their respective
owners. Arm, AMBA, Artisan, Cortex, Jazelle, Keil, SecurCore, Thumb, TrustZone, and μVision are
registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. Arm7, Arm9,
Arm11, big.LITTLE, CoreLink, CoreSight, DesignStart, Mali, Mbed, NEON, POP, Sensinode,
Socrates, ULINK and Versatile are trademarks of Arm Limited (or its subsidiaries) in the EU and/or
elsewhere. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its
affiliates. The Power Architecture and Power.org word marks and the Power and Power.org logos
and related marks are trademarks and service marks licensed by Power.org.
© 2017–2018 NXP B.V.
Document Number MWCT101xSF
Revision 2, 07/2018
相关型号：
©2020 ICPDF网 联系我们和版权申明