935363184528 [NXP]
Wide Band Low Power Amplifier;
| 型号： | 935363184528 |
| 厂家： | 
NXP |
| 描述： | Wide Band Low Power Amplifier 射频 微波 |
| 文件： | 总19页 (文件大小：541K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: A2I09VD015N
Rev. 0, 06/2018
NXP Semiconductors
Technical Data
RF LDMOS Wideband Integrated
Power Amplifiers
A2I09VD015NR1
A2I09VD015GNR1
The A2I09VD015N wideband integrated circuit is designed with on--chip
matching that makes it usable from 575 to 960 MHz. This multi--stage
structure is rated for 48 to 55 V operation and covers all typical cellular base
station modulation formats.
575–960 MHz, 2 W AVG., 48 V
AIRFAST RF LDMOS WIDEBAND
INTEGRATED POWER AMPLIFIERS
900 MHz
Typical Single--Carrier W--CDMA Characterization Performance:
DD = 48 Vdc, IDQ1(A+B) = 16 mA, IDQ2(A+B) = 84 mA, Pout = 2 W Avg., Input
Signal PAR = 9.9 dB @ 0.01% Probability on CCDF.(1)
V
G
PAE
(%)
ACPR
(dBc)
ps
Frequency
920 MHz
940 MHz
960 MHz
(dB)
32.9
33.0
32.8
19.3
19.7
19.6
–45.9
–45.5
–44.9
TO--270WB--15
PLASTIC
A2I09VD015NR1
Features
On--chip matching (50 ohm input, DC blocked)
Integrated quiescent current temperature compensation with
enable/disable function (2)
TO--270WBG--15
PLASTIC
A2I09VD015GNR1
Designed for digital predistortion error correction systems
Optimized for Doherty applications
V
DS1A
V
V
1
2
DS1A
GS2A
RF
RF /V
out1 DS2A
inA
15
V
3
GS1A
RF
4
RF /V
out1 DS2A
inA
N.C.
N.C.
N.C.
N.C.
5
V
V
GS1A
GS2A
Quiescent Current
Temperature Compensation
6
14
13
N.C.
RF /V
(2)
(2)
7
8
V
V
RF
9
GS1B
GS2B
inB
GS1B
GS2B
Quiescent Current
Temperature Compensation
out2 DS2B
V
V
V
10
11
12
DS1B
RF
inB
RF /V
out2 DS2B
(Top View)
Note: Exposed backside of the package is
the source terminal for the transistor.
V
DS1B
Figure 1. Functional Block Diagram
Figure 2. Pin Connections
1. All data measured in fixture with device soldered to heatsink.
2. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current
Control for the RF Integrated Circuit Device Family. Go to http://www.nxp.com/RF and search for AN1977 or AN1987.
2018 NXP B.V.
Table 1. Maximum Ratings
Rating
Symbol
Value
–0.5, +105
–0.5, +10
55, +0
Unit
Vdc
Vdc
Vdc
C
Drain--Source Voltage
V
DSS
Gate--Source Voltage
V
GS
DD
Operating Voltage
V
Storage Temperature Range
Case Operating Temperature Range
T
stg
–65 to +150
–40 to +150
–40 to +225
20
T
C
C
(1,2)
Operating Junction Temperature Range
Input Power
T
J
C
P
dBm
in
Table 2. Thermal Characteristics
(2,3)
Characteristic
Symbol
Value
Unit
Thermal Resistance, Junction to Case
R
C/W
JC
Case Temperature 74C, 2 W, 940 MHz
Stage 1, 48 Vdc, I
Stage 2, 48 Vdc, I
16 mA
78 mA
7.2
3.1
DQ1(A+B)
DQ2(A+B)
Table 3. ESD Protection Characteristics
Test Methodology
Class
1B
Human Body Model (per JS--001--2017)
Charge Device Model (per JS--002--2014)
C0B
Table 4. Moisture Sensitivity Level
Test Methodology
Rating
Package Peak Temperature
Unit
Per JESD22--A113, IPC/JEDEC J--STD--020
3
260
C
1. Continuous use at maximum temperature will affect MTTF.
2. MTTF calculator available at http://www.nxp.com/RF/calculators.
3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.nxp.com/RF and search for AN1955.
A2I09VD015NR1 A2I09VD015GNR1
RF Device Data
NXP Semiconductors
2
Table 5. Electrical Characteristics (T = 25C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
(1)
Stage 1 -- Off Characteristics
Zero Gate Voltage Drain Leakage Current
I
I
—
—
—
—
—
—
10
1
Adc
Adc
Adc
DSS
DSS
GSS
(V = 105 Vdc, V = 0 Vdc)
DS
GS
Zero Gate Voltage Drain Leakage Current
(V = 55 Vdc, V = 0 Vdc)
DS
GS
Gate--Source Leakage Current
(V = 1.2 Vdc, V = 0 Vdc)
I
1
GS
DS
Stage 1 -- On Characteristics
(1)
Gate Threshold Voltage
V
V
1.3
2.2
4.4
1.8
2.4
4.8
2.3
2.6
5.2
Vdc
Vdc
Vdc
GS(th)
GS(Q)
GG(Q)
(V = 10 Vdc, I = 1 Adc)
DS
D
Gate Quiescent Voltage
(V = 48 Vdc, I
= 16 mAdc)
DQ1(A+B)
DS
Fixture Gate Quiescent Voltage
V
(V = 48 Vdc, I
DD
= 16 mAdc, Measured in Functional Test)
DQ1(A+B)
(1)
Stage 2 -- Off Characteristics
Zero Gate Voltage Drain Leakage Current
(V = 105 Vdc, V = 0 Vdc)
I
—
—
—
—
—
—
10
1
Adc
Adc
Adc
DSS
DSS
GSS
DS
GS
Zero Gate Voltage Drain Leakage Current
(V = 55 Vdc, V = 0 Vdc)
I
DS
GS
Gate--Source Leakage Current
(V = 1.2 Vdc, V = 0 Vdc)
I
1
GS
DS
Stage 2 -- On Characteristics
(1)
Gate Threshold Voltage
V
V
1.3
2.0
4.0
0.1
1.8
2.2
4.4
0.3
2.3
2.4
4.8
0.5
Vdc
Vdc
Vdc
Vdc
GS(th)
GS(Q)
GG(Q)
DS(on)
(V = 10 Vdc, I = 6 Adc)
DS
D
Gate Quiescent Voltage
(V = 48 Vdc, I
= 78 mAdc)
DQ2(A+B)
DS
Fixture Gate Quiescent Voltage
(V = 48 Vdc, I = 78 mAdc, Measured in Functional Test)
V
DD
DQ2(A+B)
(1)
Drain--Source On--Voltage
(V = 10 Vdc, I = 60 mAdc)
V
GS
D
1. Each side of device measured separately.
(continued)
A2I09VD015NR1 A2I09VD015GNR1
RF Device Data
NXP Semiconductors
3
Table 5. Electrical Characteristics (T = 25C unless otherwise noted) (continued)
A
Characteristic
Symbol
Min
Typ
= 16 mA, I = 78 mA,
DQ2(A+B)
Max
Unit
(1,2)
Functional Tests
(In NXP Production Test Fixture, 50 ohm system) V = 48 Vdc, I
DD
DQ1(A+B)
P
= 2 W Avg., f = 920 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF.
out
ACPR measured in 3.84 MHz Channel Bandwidth @ 5 MHz Offset.
Power Gain
G
31.0
18.0
—
32.8
18.8
34.0
—
dB
%
ps
Power Added Efficiency
PAE
ACPR
Adjacent Channel Power Ratio
–43.9
18.5
–41.0
—
dBc
W
P
@ 3 dB Compression Point, CW
P3dB
16.6
out
Load Mismatch (In NXP Production Test Fixture, 50 ohm system) I
= 16 mA, I
= 78 mA, f = 940 MHz
DQ2(A+B)
DQ1(A+B)
VSWR 10:1 at 55 Vdc, 24 W CW Output Power
(3 dB Input Overdrive from 19 W CW Rated Power)
No Device Degradation
(3)
Typical Performance (In NXP Characterization Test Fixture, 50 ohm system) V = 48 Vdc, I
= 16 mA, I
= 78 mA,
DD
DQ1(A+B)
DQ2(A+B)
920–960 MHz Bandwidth
P
P
@ 1 dB Compression Point, CW
P1dB
P3dB
—
17.7
18.5
–9
—
—
—
W
W
out
out
(4)
@ 3 dB Compression Point
—
—
AM/PM
(Maximum value measured at the P3dB compression point across
the 920–960 MHz frequency range.)
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
VBW
—
270
—
MHz
%
res
(5)
Quiescent Current Accuracy over Temperature
I
QT
with 2 k Gate Feed Resistors (--30 to 85C) Stage 1
with 2 k Gate Feed Resistors (--30 to 85C) Stage 2
—
—
2.9
3.2
—
—
Gain Flatness in 40 MHz Bandwidth @ P = 2 W Avg.
G
—
—
0.2
—
—
dB
out
F
Gain Variation over Temperature
G
0.036
dB/C
(–30C to +85C)
Output Power Variation over Temperature
P1dB
—
0.007
—
dB/C
(–30C to +85C)
Table 6. Ordering Information
Device
Tape and Reel Information
Package
A2I09VD015NR1
A2I09VD015GNR1
TO--270WB--15
R1 Suffix = 500 Units, 44 mm Tape Width, 13--inch Reel
TO--270WBG--15
1. Part internally input and output matched.
2. Measurements made with device in straight lead configuration before any lead forming operation is applied. Lead forming is used for gull
wing (GN) parts.
3. All data measured in fixture with device soldered to heatsink.
4. P3dB = P
+ 7.0 dB where P
is the average output power measured using an unclipped W--CDMA single--carrier input signal where
avg
avg
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
5. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current
Control for the RF Integrated Circuit Device Family. Go to http://www.nxp.com/RF and search for AN1977 or AN1987.
A2I09VD015NR1 A2I09VD015GNR1
RF Device Data
NXP Semiconductors
4
V
DS2
V
GS2
A2I09VD015N
C8
V
DS1
V
R1
GS1
C7
R2
C1
C2
C15
C24
C23
C3
Rev. 2
C11
C19
C12
Z1
C17
R7
C25
R8
C21
R5
Z2
R10
R9
C22
C28
R6
C18
C14
C26
C27
C16
C13
C20
C4
C5
C6
C10
R4
C9
V
GS3
V
DS1
R3
GS4
V
V
DS2
Figure 3. A2I09VD015NR1 Production Test Circuit Component Layout
Table 7. A2I09VD015NR1 Production Test Circuit Component Designations and Values
Part
Description
Part Number
C5750X7SA106M230KB
C3225X7S1H106M250AB
C0805C103K5RAC
ATC600S470JT250XT
CRCW08052K20JNEA
C8A50Z4A
Manufacturer
TDK
C1, C2, C3, C4, C5, C6, C7, C8, C9, C10
10 F Chip Capacitor
C11, C12, C13, C14
10 F Chip Capacitor
TDK
C15, C16, C17, C18
10 nF Chip Capacitor
Kemet
ATC
C19, C20, C21, C22, C23, C24, C25, C26, C27, C28
47 pF Chip Capacitor
R1, R2, R3, R4
2.2 k, 1/8 W Chip Resistor
50 , 8 W Termination Chip Resistor
50 , 20 W Termination Chip Resistor
10 , 1/8 W Chip Resistor
Vishay
Anaren
Anaren
Vishay
Anaren
MTL
R5
R6
C20A50Z4
R7, R8, R9, R10
Z1, Z2
CRCW080510R0FKEA
X3C09P1-03
800--1000 MHz, 90, 3 dB Hybrid Coupler
PCB
Rogers RO4350B, 0.020, = 3.66
—
r
A2I09VD015NR1 A2I09VD015GNR1
RF Device Data
NXP Semiconductors
5
D99736
V
DS2
V
GS2
A2I09VD015N
V
DS1
V
GS1
R1
C8
C7
R2
C1
C2
C15
C24
C23
C3
Rev. 2
C11
C19
C12
Z1
C17
R7
C25
R8
C21
R5
Q1
Z2
R10
R9
C22
C28
R6
C18
C14
C26
C27
C16
C13
C20
C4
C5
C6
C10
R4
C9
V
GS3
V
DS1
R3
GS4
V
V
DS2
Note: All data measured in fixture with device soldered to heatsink. Production fixture does not include device
soldered to heatsink.
Figure 4. A2I09VD015NR1 Characterization Test Circuit Component Layout — 920–960 MHz
Table 8. A2I09VD015NR1 Characterization Test Circuit Component Designations and Values — 920–960 MHz
Part
Description
Part Number
C5750X7SA106M230KB
C3225X7S1H106M250AB
C0805C103K5RAC
ATC600S470JT250XT
A2I09VD015N
Manufacturer
TDK
C1, C2, C3, C4, C5, C6, C7, C8, C9, C10
10 F Chip Capacitor
C11, C12, C13, C14
10 F Chip Capacitor
TDK
C15, C16, C17, C18
10 nF Chip Capacitor
Kemet
ATC
C19, C20, C21, C22, C23, C24, C25, C26, C27, C28
47 pF Chip Capacitor
Q1
RF Power LDMOS Amplifier
2.2 k, 1/8 W Chip Resistor
50 , 8 W Termination Chip Resistor
50 , 20 W Termination Chip Resistor
10 , 1/8 W Chip Resistor
NXP
R1, R2, R3, R4
CRCW08052K20JNEA
C8A50Z4A
Vishay
Anaren
Anaren
Vishay
Anaren
MTL
R5
R6
C20A50Z4
R7, R8, R9, R10
Z1, Z2
CRCW080510R0FKEA
X3C09P1-03
800--1000 MHz, 90, 3 dB Hybrid Coupler
PCB
Rogers RO4350B, 0.020, = 3.66
D99736
r
A2I09VD015NR1 A2I09VD015GNR1
RF Device Data
NXP Semiconductors
6
TYPICAL CHARACTERISTICS — 920–960 MHz
20
33.5
D
V
= 48 Vdc, P = 2 W (Avg.)
out
DD
33
32.5
32
18
I
= 16 mA
= 84 mA
DQ1(A+B)
I
DQ2(A+B)
16
G
ps
14
31.5
31
12
PARC
–.3
–43
–44
–45
–46
–47
–48
–.6
30.5
30
ACPR
–.9
–1.2
–1.5
–1.8
29.5
29
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF
28.5
820
840
860
880
900
920
940
960
980
f, FREQUENCY (MHz)
Figure 5. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 2 Watts Avg.
–15
V
DD
= 48 Vdc, P = 8 W (PEP), I
= 16 mA
out
DQ1(A+B)
I
= 84 mA
DQ2(A+B)
IM3--U
IM3--L
–30
–45
–60
–75
–90
IM5--L
IM5--U
IM7--L
IM7--U
Two--Tone Measurements, (f1 + f2)/2 = Center Frequency of 940 MHz
1
10
100
400
TWO--TONE SPACING (MHz)
Figure 6. Intermodulation Distortion Products
versus Two--Tone Spacing
32.9
40
35
–30
–33
–36
–39
–42
–45
–48
1
0
V
= 48 Vdc, I
= 16 mA, I
= 84 mA
DD
DQ1(A+B)
DQ2(A+B)
f = 940 MHz, Single--Carrier W--CDMA
32.8
32.7
ACPR
–1
–2
–3
–4
–5
30
25
20
15
–1 dB = 2.3 W
–2 dB = 3.1 W
32.6
32.5
32.4
32.3
G
PARC
ps
D
–3 dB = 4.1 W
3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF
10
1
2
3
4
5
6
P
, OUTPUT POWER (WATTS)
out
Figure 7. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2I09VD015NR1 A2I09VD015GNR1
RF Device Data
NXP Semiconductors
7
TYPICAL CHARACTERISTICS — 920–960 MHz
–20
–25
–30
–35
–40
–45
–50
35
60
50
40
30
20
10
V
= 48 Vdc, I
= 16 mA, I
= 84 mA
DD
DQ1(A+B)
DQ2(A+B)
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
34
33
32
31
30
29
D
960 MHz
940 MHz
920 MHz
G
ps
920 MHz
940 MHz 960 MHz
ACPR
960 MHz
940 MHz
920 MHz
0
20
1
10
, OUTPUT POWER (WATTS) AVG.
P
out
Figure 8. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
36
34
32
30
28
26
24
V
P
= 48 Vdc
= 0 dBm
DD
in
I
I
= 16 mA
= 84 mA
DQ1(A+B)
DQ2(A+B)
Gain
750
800
850
900
950
1000 1050
1100 1150
f, FREQUENCY (MHz)
Figure 9. Broadband Frequency Response
A2I09VD015NR1 A2I09VD015GNR1
RF Device Data
NXP Semiconductors
8
Table 9. Load Pull Performance — Maximum Power Tuning
V
= 48 Vdc, I
= 8 mA, I = 39 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQ1
DQ2
Max Output Power
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
59.5
59.6
58.7
Gain (dB)
31.6
(dBm)
40.2
(W)
10
(MHz)
920
940
960
51.0 – j3.11
49.2 + j1.23
50.9 + j2.55
65.8 + j7.62
35.3 + j33.2
32.5 + j32.9
29.7 + j32.1
–2
–3
–4
60.4 + j2.53
54.2 + j0.33
31.5
40.2
11
31.3
40.2
10
Max Output Power
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
62.1
61.5
61.1
Gain (dB)
29.6
(dBm)
41.1
(W)
13
(MHz)
920
51.0 – j3.11
66.2 + j7.48
33.7 + j31.8
31.3 + j31.1
28.8 + j30.7
–3
–4
–5
940
960
49.2 + j1.23
50.9 + j2.55
60.0 + j2.49
52.8 + j1.10
29.5
41.1
13
29.3
41.0
13
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Note: Measurement made on a per side basis.
Table 10. Load Pull Performance — Maximum Efficiency Tuning
V
= 48 Vdc, I
= 8 mA, I = 39 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
DD
DQ1
DQ2
Max Drain Efficiency
P1dB
(1)
Z
AM/PM
()
f
Z
Z
in
()
load
()
D
source
()
(%)
70.0
68.8
67.5
Gain (dB)
33.7
(dBm)
38.5
(W)
7
(MHz)
920
940
960
51.0 – j3.11
49.2 + j1.23
50.9 + j2.55
67.5 + j6.05
18.5 + j45.3
14.3 + j44.7
18.0 + j40.8
–4
–5
–4
60.9 + j1.05
54.3 + j0.28
33.8
37.5
6
32.9
38.8
8
Max Drain Efficiency
P3dB
(2)
Z
()
AM/PM
()
f
Z
Z
()
load
D
source
()
in
(%)
71.1
69.9
69.4
Gain (dB)
31.7
(dBm)
39.4
(W)
9
(MHz)
920
51.0 – j3.11
67.3 + j4.87
18.5 + j45.7
13.0 + j46.5
18.3 + j40.8
–3
–4
–2
940
960
49.2 + j1.23
50.9 + j2.55
59.2 – j0.18
53.5 – j0.45
32.0
38.1
6
30.9
39.8
10
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Z
Z
Z
= Measured impedance presented to the input of the device at the package reference plane.
= Impedance as measured from gate contact to ground.
= Measured impedance presented to the output of the device at the package reference plane.
source
in
load
Note: Measurement made on a per side basis.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Z
Z
in
Z
load
source
A2I09VD015NR1 A2I09VD015GNR1
RF Device Data
NXP Semiconductors
9
P1dB – TYPICAL LOAD PULL CONTOURS — 940 MHz
55
50
45
40
35
30
25
20
15
55
39
38.5
39.5
50
45
40
35
30
25
20
15
66
38
64
68
62
E
E
40
36
60
58
56
P
P
54
40
52
37
38
38.5
39.5
39
39
5
10 15 20 25 30 35 40 45 50 55 60
5
10 15 20 25 30 35 40 45 50 55 60
REAL ()
REAL ()
Figure 10. P1dB Load Pull Output Power Contours (dBm)
Figure 11. P1dB Load Pull Efficiency Contours (%)
55
55
–2
50
50
45
40
35
30
25
20
15
–4
E
30.5
45
40
35
30
25
20
15
E
34
31
31.5
–10
–8
–6
33.5
32
33
32.5
P
P
–4
–4
5
10 15 20 25 30 35 40 45 50 55 60
5
10 15 20 25 30 35 40 45 50 55 60
REAL ()
REAL ()
Figure 12. P1dB Load Pull Gain Contours (dB)
Figure 13. P1dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
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RF Device Data
NXP Semiconductors
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P3dB – TYPICAL LOAD PULL CONTOURS — 940 MHz
55
50
45
40
35
30
25
20
15
55
39 39.5
38.5
40
38
50
68
66
64
E
E
40.5
41
62
45
40
35
30
25
20
15
37
60
58
56
54
P
P
38
39
40.5
40
39.5
40
5
10 15 20 25 30 35 40 45 50 55 60
5
10 15 20 25 30 35 40 45 50 55 60
REAL ()
REAL ()
Figure 14. P3dB Load Pull Output Power Contours (dBm)
Figure 15. P3dB Load Pull Efficiency Contours (%)
55
50
55
50
45
40
35
30
25
20
15
0
E
E
28.5
45
29
32
29.5
40
35
30
25
20
15
–2
–14
30
31.5
–12
–10
–8
31
30.5
–4
P
P
–6
5
10 15 20 25 30 35 40 45 50 55 60
5
10 15 20 25 30 35 40 45 50 55 60
REAL ()
REAL ()
Figure 16. P3dB Load Pull Gain Contours (dB)
Figure 17. P3dB Load Pull AM/PM Contours ()
NOTE:
P
E
= Maximum Output Power
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
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RF Device Data
NXP Semiconductors
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PACKAGE DIMENSIONS
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RF Device Data
NXP Semiconductors
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RF Device Data
NXP Semiconductors
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NXP Semiconductors
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NXP Semiconductors
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PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
AN1907: Solder Reflow Attach Method for High Power RF Devices in Over--Molded Plastic Packages
AN1955: Thermal Measurement Methodology of RF Power Amplifiers
AN1977: Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family
AN1987: Quiescent Current Control for the RF Integrated Circuit Device Family
Engineering Bulletins
EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
Electromigration MTTF Calculator
RF High Power Model
.s2p File
Development Tools
Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to http://www.nxp.com/RF
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
Description
0
June 2018
Initial release of data sheet
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RF Device Data
NXP Semiconductors
18
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright licenses
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E 2018 NXP B.V.
Document Number: A2I09VD015N
Rev. 0, 06/2018
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