935377783557 [NXP]
Multifunction Peripheral;
| 型号： | 935377783557 |
| 厂家： | 
NXP |
| 描述： | Multifunction Peripheral |
| 文件： | 总100页 (文件大小：1832K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: IMX8MDQLQCEC
Rev. 1.1, 07/2019
NXP Semiconductors
Data Sheet: Technical Data
MIMX8MQ7DVAJZAA MIMX8MQ7DVAJZAB
MIMX8MQ6DVAJZAA MIMX8MQ6DVAJZAB
MIMX8MD7DVAJZAA MIMX8MD7DVAJZAB
MIMX8MD6DVAJZAA MIMX8MD6DVAJZAB
MIMX8MQ5DVAJZAA MIMX8MQ5DVAJZAB
i.MX 8M Dual / 8M
QuadLite / 8M Quad
Applications Processors
Data Sheet for Consumer
Products
Package Information
Bare Die Package
FBGA 17 x 17 mm, 0.65 mm pitch
Ordering Information
See Table 2 on page 6
1 i.MX 8M Dual / 8M QuadLite
/ 8M Quad introduction
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors
represent NXP’s latest market of connected streaming
audio/video devices, scanning/imaging devices, and
various devices requiring high-performance, low-power
processors.
1. i.MX 8M Dual / 8M QuadLite / 8M Quad introduction . . . 1
1.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6
2. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1. Recommended connections for unused interfaces 12
3. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 13
3.2. Power supplies requirements and restrictions . . . 25
3.3. PLL electrical characteristics . . . . . . . . . . . . . . . . 27
3.4. On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5. I/O DC parameters . . . . . . . . . . . . . . . . . . . . . . . 30
3.6. I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . 32
3.7. Output buffer impedance parameters . . . . . . . . . 35
3.8. System modules timing . . . . . . . . . . . . . . . . . . . . 37
3.9. External peripheral interface parameters . . . . . . 38
4. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 74
4.1. Boot mode configuration pins . . . . . . . . . . . . . . . 74
4.2. Boot device interface allocation . . . . . . . . . . . . . . 75
5. Package information and contact assignments . . . . . . . 76
5.1. 17 x 17 mm package information . . . . . . . . . . . . 76
5.2. DDR pin function list for 17 x 17 mm package . . 96
6. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors
®
feature advanced implementation of a quad Arm
®
Cortex -A53 core, which operates at speeds of up to
®
1.5 GHz. A general purpose Cortex -M4 core processor
is for low-power processing. The DRAM controller
supports 32-bit/16-bit LPDDR4, DDR4, and DDR3L
memory. There are a number of other interfaces for
connecting peripherals, such as WLAN, Bluetooth, GPS,
displays, and camera sensors. The i.MX 8M Quad and
i.MX 8M Dual processors have hardware acceleration
for video playback up to 4K, and can drive the video
outputs up to 60 fps. Although the i.MX 8M QuadLite
processor does not have hardware acceleration for video
decode, it allows for video playback with software
decoders if needed.
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction
Table 1. Features
Subsystem
Feature
Quad symmetric Cortex-A53 processors:
Arm Cortex-A53 MPCore platform
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• Support L1 cache RAMs protection with parity/ECC
Support of 64-bit Armv8-A architecture:
• 1 MB unified L2 cache
• Support L2 cache RAMs protection with ECC
• Frequency of 1.5 GHz
Arm Cortex-M4 core platform
Connectivity
16 KB L1 Instruction Cache
16 KB L1 Data Cache
256 KB tightly coupled memory (TCM)
Two PCI Express Gen2 interfaces
Two USB 3.0/2.0 controllers with integrated PHY interfaces
Two Ultra Secure Digital Host Controller (uSDHC) interfaces
One Gigabit Ethernet controller with support for EEE, Ethernet AVB, and IEEE 1588
Four Universal Asynchronous Receiver/Transmitter (UART) modules
Four I2C modules
Three SPI modules
External memory interface
32/16-bit DRAM interface: LPDDR4-3200, DDR4-2400, DDR3L-1600
8-bit NAND-Flash
eMMC 5.0 Flash
SPI NOR Flash
QuadSPI Flash with support for XIP
GPIO and pin multiplexing
On-chip memory
GPIO modules with interrupt capability
Input/output multiplexing controller (IOMUXC) to provide centralized pad control
Boot ROM (128 KB)
On-chip RAM (128 KB + 32 KB)
Power management
Temperature sensor with programmable trip points
Flexible power domain partitioning with internal power switches to support efficient
power management
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors
2
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction
Table 1. Features (continued)
Feature
Subsystem
Multimedia
Video Processing Unit:
• 4Kp60 HEVC/H.265 main, and main 10 decoder
• 4Kp60 VP9 decoder
• 4Kp30 AVC/H.264 decoder
• 1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder
Graphic Processing Unit:
• 4 shader
• 267 million triangles/sec
• 1.6 Giga pixel/sec
• 32 GFLOPs 32-bit or 64 GFLOPs 16-bit
• Support OpenGL ES 1.1, 2.0, 3.0, 3.1, Open CL 1.2, and Vulkan
HDMI Display Interface:
• HDMI 2.0a supporting one display: resolution up to 4096 x 2160 at 60 Hz, support
HDCP 2.2 and HDCP 1.41
• 20+ Audio interfaces 32-bit @ 384 kHz fs, with Time Division Multiplexing (TDM)
support
• S/PDIF input and output
• Audio Return Channel (ARC) on HDMI
• Upscale HD graphics to 4K for display
• Downscale 4K video to HD for display
• Display Port
• Embedded Display Port
MIPI-DSI Display Interface:
• MIPI-DSI 4 channels supporting one display, resolution up to 1920 x 1080 at 60 Hz
• LCDIF display controller
• Output can be LCDIF output or DC display controller output
Audio:
• S/PDIF input and output
• Five synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and
codec/DSP interfaces, including one SAI with 16 Tx and 16 Rx channels, one SAI
with 8 Tx and 8 Rx channels, and three SAI with 2 Tx and 2 Rx channels
• One SAI for 8 Tx channels for HDMI output audio
• One S/PDIF input for HDMI ARC input
Camera inputs:
• Two MIPI-CSI2 camera inputs (4-lane each)
Security
Resource Domain Controller (RDC) supports four domains and up to eight regions
Arm TrustZone (TZ) architecture
On-chip RAM (OCRAM) secure region protection using OCRAM controller
High Assurance Boot (HAB)
Cryptographic acceleration and assurance (CAAM) module
Secure non-volatile storage (SNVS): Secure real-time clock (RTC)
Secure JTAG controller (SJC)
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors
3
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction
Table 1. Features (continued)
Subsystem
System debug
Feature
Arm CoreSight debug and trace architecture
TPIU to support off-chip real-time trace
ETF with 4 KB internal storage to provide trace buffering
Unified trace capability for Quad Cortex-A53 and Cortex-M4 CPUs
Cross Triggering Interface (CTI)
Support for 5-pin (JTAG) debug interface
1
Please contact the NXP sales and marketing team for order details on HDCP enable parts.
NOTE
The actual feature set depends on the part numbers as described in Table 2.
Functions such as display and camera interfaces, and connectivity
interfaces, may not be enabled for specific part numbers.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors
4
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction
1.1
Block diagram
Figure 1 shows the functional modules in the i.MX 8M Dual / 8M QuadLite / 8M Quad processor system.
Security
Main CPU Platform
Connectivity and I/O
1 GB Ethernet
TrustZone
Quad Cortex-A53
(IEEE1588, EEE, and AVB)
DRM Ciphers
Secure Clock
32 KB I-cache
NEON
32 KB D-cache
FPU
S/PDIF Rx and Tx,
I2S/SAI x6
PCIe 2.0 x2 (1-lane, each)
USB 3.0/2.0 OTG x2
eFuse Key Storage
Random Number
1 MB L2 Cache
Low Power, Security CPU
32 KB Secure RAM
UART x4, 5 Mbps
I2C x4, SPI x3
Cortex-M4
System Control
16 KB D-cache
256 KB TCM
16 KB I-cache
HDMI 2.0a output
HDCP 2.2
Smart DMA x2
Timer x3
MIPI DSI Display x1
MIPI CSI2 Capture x2
Multimedia
3D Graphics: 4 Shader
OpenGL/ES 3.1, CL 1.2, Vulkan
PWM x4
External Memory
LPDDR4-3200
DDR4-2400
DDR3L-1600
4Kp60 HEVC/H.265
4Kp60 VP9
4Kp30 H.264 Decoder and VP9
Watchdog x3
Temp Monitor
Secure JTAG
1080p60 MPEG-2, MPEG-4p2,
VC-1, VP8, RV9, AVS,
2x eMMC 5/SD 3
NAND CTL (BCH62)
MJPEG, H.263 Decoder
4Kp60 Display
Temperature Sensor
QuadSPI (XIP)
Figure 1. i.MX 8M Dual / 8M QuadLite / 8M Quad system block diagram
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors
5
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction
1.2
Ordering information
Table 2 shows examples of orderable sample part numbers covered by this data sheet. This table does not
include all possible orderable part numbers. If your desired part number is not listed in the table, or you
have questions about available parts, contact your NXP representative.
Table 2. Orderable part numbers
Cortex-A53
CPU speed
grade
Qualification Temperature
Part number
Options
Package
tier
Tj (C)
MIMX8MQ7DVAJZAA1
MIMX8MQ7DVAJZAB1
8M Quad
1.5 GHz
1.5 GHz
1.5 GHz
1.5 GHz
1.5 GHz
Consumer
0 to +95
17 x 17 mm,
0.65 mm pitch,
FBGA
MIMX8MQ6DVAJZAA
MIMX8MQ6DVAJZAB
8M Quad
8M Dual
Consumer
Consumer
Consumer
Consumer
0 to +95
0 to +95
0 to +95
0 to +95
17 x 17 mm,
0.65 mm pitch,
FBGA
MIMX8MD7DVAJZAA1
MIMX8MD7DVAJZAB1
17 x 17 mm,
0.65 mm pitch,
FBGA
MIMX8MD6DVAJZAA
MIMX8MD6DVAJZAB
8M Dual
17 x 17 mm,
0.65 mm pitch,
FBGA
MIMX8MQ5DVAJZAA
MIMX8MQ5DVAJZAB
8M Quad Lite
17 x 17 mm,
0.65 mm pitch,
FBGA
1
Part number requires a Dolby VisionTM license from Dolby.
Figure 2 describes the part number nomenclature so that the users can identify the characteristics of the
specific part number.
Contact an NXP representative for additional details.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
6
NXP Semiconductors
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction
+
A
M
IMX8MQ
@
VN
$$
%
Silicon Rev
Rev. 1.0
A
A
B
Qualification Level
M
Samples
P
M
S
Rev. 1.1
Mass Production
Special
Fusing
%
-
A
D
HDCP customer
programmable
i.MX 8 Family Part # Series
i.MX 8MQ
Description
Quad core
Dual core
HDCP NXP programmed
C
i.MX 8MD
Frequency
1.5 GHz
$$
JZ
1.3 GHz
HZ
Part Differentiator
@
7
VPU decode + Dolby Vision + HDR10 + GPU
VPU decode + HDR10 + GPU
GPU, No VPU
ROHS
Package Type
17 x 17 mm, 0.65 mm pitch, FCBGA bare die
package
6
VA
5
Temperature (Tj)
+
D
C
Commercial: 0 to + 95 °C
Industrial: -40 to +105 °C
Figure 2. Part number nomenclature—i.MX 8M Dual / 8M QuadLite / 8M Quad processors
*Please contact the NXP sales and marketing team for order details on HDCP enable parts.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors
7
Modules list
2 Modules list
The i.MX 8M Dual / 8M QuadLite / 8M Quad of processors contain a variety of digital and analog
modules. Table 3 describes these modules in alphabetical order.
Table 3. i.MX 8M Dual / 8M QuadLite / 8M Quad modules list
Block mnemonic
Block name
Brief description
APBH-DMA
NAND Flash and BCH ECC
DMA Controller
DMA controller used for GPMI2 operation.
Arm
Arm Platform
The Arm Core Platform includes a quad Cortex-A53 core and a
Cortex-M4 core. The Cortex-A53 core includes associated
sub-blocks, such as the Level 2 Cache Controller, Snoop Control
Unit (SCU), General Interrupt Controller (GIC), private timers,
watchdog, and CoreSight debug modules. The Cortex-M4 core is
used as a customer microcontroller.
BCH
Binary-BCH ECC Processor The BCH module provides up to 62-bit ECC encryption/decryption
for NAND Flash controller (GPMI)
CAAM
Cryptographic accelerator and CAAM is a cryptographic accelerator and assurance module. CAAM
assurance module
implements several encryption and hashing functions, a run-time
integrity checker, entropy source generator, and a Pseudo Random
Number Generator (PRNG). The PRNG is certifiable by the
Cryptographic Algorithm Validation Program (CAVP) of the National
Institute of Standards and Technology (NIST).
CAAM also implements a Secure Memory mechanism. In i.MX 8M
Dual / 8M QuadLite / 8M Quad processors, the secure memory
provided is 32 KB.
CCM
GPC
SRC
Clock Control Module, General These modules are responsible for clock and reset distribution in the
PowerController, SystemReset system, and also for the system power management.
Controller
CSU
Central Security Unit
The Central Security Unit (CSU) is responsible for setting
comprehensive security policy within the i.MX 8M Dual / 8M
QuadLite / 8M Quad platform.
CTI-0
CTI-1
CTI-2
CTI-3
CTI-4
Cross Trigger Interface
Cross Trigger Interface (CTI) allows cross-triggering based on inputs
from masters attached to CTIs. The CTI module is internal to the
Cortex-A53 core platform.
DAP
Debug Access Port
Display Controller
The DAP provides real-time access for the debugger without halting
the core to access:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan chains.
DC
Dual display controller
DDRC
Double Data Rate Controller The DDR Controller has the following features:
• Supports 32/16-bit LPDDR4-3200, DDR4-2400, and
DDR3L-1600
• Supports up to 8 Gbyte DDR memory space
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors
8
Modules list
Table 3. i.MX 8M Dual / 8M QuadLite / 8M Quad modules list (continued)
Block mnemonic
Block name
Brief description
eCSPI1
eCSPI2
eCSPI3
Configurable SPI
Full-duplex enhanced Synchronous Serial Interface, with data rate
up to 52 Mbit/s. Configurable to support Master/Slave modes, only
one chip select is supported.
EIM
NOR-Flash / PSRAM interface The EIM NOR-FLASH / PSRAM provides:
• Support for 16-bit (in Muxed I/O mode only) PSRAM memories
(sync and async operating modes), at slow frequency
• Support for 16-bit (in muxed and non muxed I/O modes)
NOR-Flash memories, at slow frequency
• Multiple chip selects
ENET1
Ethernet Controller
The Ethernet Media Access Controller (MAC) is designed to support
10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external
transceiver interface and transceiver function are required to
complete the interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the ENET chapter
of the i.MX 8M Dual / 8M QuadLite / 8M Quad Applications
Processor Reference Manual (IMX8MDQLQRM) for details.
GIC
Generic Interrupt Controller
The GIC handles all interrupts from the various subsystems and is
ready for virtualization.
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
General Purpose I/O Modules Used for general purpose input/output to external ICs. Each GPIO
module supports up to 32 bits of I/O.
GPMI
General Purpose Memory
Interface
The GPMI module supports up to 8x NAND devices and 62-bit ECC
encryption/decryption for NAND Flash Controller (GPMI2). GPMI
supports separate DMA channels for each NAND device.
GPT1
GPT2
GPT3
GPT4
GPT5
GPT6
General Purpose Timer
Each GPT is a 32-bit “free-running” or “set-and-forget” mode timer
with programmable prescaler and compare and capture register. A
timer counter value can be captured using an external event and can
be configured to trigger a capture event on either the leading or
trailing edges of an input pulse. When the timer is configured to
operate in “set-and-forget” mode, it is capable of providing precise
interrupts at regular intervals with minimal processor intervention.
The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either on
an external clock or on an internal clock.
GPU3D
Graphics Processing Unit-3D The GPU3D provides hardware acceleration for 3D graphics
algorithms with sufficient processor power to run desktop quality
interactive graphics applications on displays.
HDMI Tx
HDMI Tx interface
I2C Interface
The HDMI module provides an HDMI standard interface port to an
HDMI 2.0a-compliant display.
I2C1
I2C2
I2C3
I2C4
I2C provides serial interface for external devices.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors
9
Modules list
Table 3. i.MX 8M Dual / 8M QuadLite / 8M Quad modules list (continued)
Block mnemonic
Block name
Brief description
IOMUXC
IOMUX Control
This module enables flexible I/O multiplexing. Each IO pad has a
default as well as several alternate functions. The alternate functions
are software configurable.
LCDIF
LCD interface
The LCDIF is a general purpose display controller used to drive a
wide range of display devices varying in size and capability.
MIPI CSI2 (four-lane)
MIPI DSI (four-lane)
OCOTP_CTRL
MIPI Camera Serial Interface This module provides two four-lane MIPI camera serial interfaces,
each of them can operate up to a maximum bit rate of 1.5 Gbps.
MIPI Display Serial Interface This module provides a four-lane MIPI display serial interface
operating up to a maximum bit rate of 1.5 Gbps.
OTP Controller
The On-Chip OTP controller (OCOTP_CTRL) provides an interface
for reading, programming, and/or overriding identification and control
information stored in on-chip fuse elements. The module supports
electrically programmable poly fuses (eFUSEs). The OCOTP_CTRL
also provides a set of volatile software-accessible signals that can be
used for software control of hardware elements, not requiring non
volatility. The OCOTP_CTRL provides the primary user-visible
mechanism for interfacing with on-chip fuse elements. Among the
uses for the fuses are unique chip identifiers, mask revision
numbers, cryptographic keys, JTAG secure mode, boot
characteristics, and various control signals requiring permanent non
volatility.
OCRAM
On-Chip Memory controller
The On-Chip Memory controller (OCRAM) module is designed as an
interface between the system’s AXI bus and the internal (on-chip)
SRAM memory module.
In i.MX 8M Dual / 8M QuadLite / 8M Quad processors, the OCRAM
is used for controlling the 128 KB multimedia RAM through a 64-bit
AXI bus.
PCIe1
PCIe2
2x PCI Express 2.0
Power Management Unit
Pulse Width Modulation
The PCIe IP provides PCI Express Gen 2.0 functionality.
PMU
Integrated power management unit. Used to provide power to
various SoC domains.
PWM1
PWM2
PWM3
PWM4
The pulse-width modulator (PWM) has a 16-bit counter and is
optimized to generate sound from stored sample audio images. It
can also generate tones. It uses 16-bit resolution and a 4x16 data
FIFO to generate sound.
QSPI
Quad SPI
The Quad SPI module acts as an interface to external serial flash
devices. This module contains the following features:
• Flexible sequence engine to support various flash vendor devices
• Single pad/Dual pad/Quad pad mode of operation
• Single Data Rate/Double Data Rate mode of operation
• Parallel Flash mode
• DMA support
• Memory mapped read access to connected flash devices
• Multi master access with priority and flexible and configurable
buffer for each master
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
10 NXP Semiconductors
Modules list
Table 3. i.MX 8M Dual / 8M QuadLite / 8M Quad modules list (continued)
Block name Brief description
Block mnemonic
SAI1
SAI2
SAI3
SAI4
SAI5
SAI6
Synchronous Audio Interface The SAI module provides a synchronous audio interface (SAI) that
supports full duplex serial interfaces with frame synchronization,
such as I2S, AC97, TDM, and codec/DSP interfaces.
SDMA
Smart Direct Memory Access The SDMA is a multichannel flexible DMA engine. It helps in
maximizing system performance by offloading the various cores in
dynamic data routing. It has the following features:
• Powered by a 16-bit Instruction-Set micro-RISC engine
• Multi channel DMA supporting up to 32 time-division multiplexed
DMA channels
• 48 events with total flexibility to trigger any combination of
channels
• Memory accesses including linear, FIFO, and 2D addressing
• Shared peripherals between Arm and SDMA
• Very fast Context-Switching with 2-level priority based preemptive
multi tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers (increment,
decrement, and no address changes on source and destination
address)
• DMA ports can handle unidirectional and bidirectional flows (Copy
mode)
• Up to 8-word buffer for configurable burst transfers for EMIv2.5
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available
SJC
Secure JTAG Controller
The SJC provides JTAG interface (designed to be compatible with
JTAG TAP standards) to internal logic. The i.MX 8M Dual / 8M
QuadLite / 8M Quad of processors use JTAG port for production,
testing, and system debugging. Additionally, the SJC provides BSR
(Boundary Scan Register) standard support, designed to be
compatible with IEEE 1149.1 and IEEE 1149.6 standards.
The JTAG port must be accessible during platform initial laboratory
bring-up, for manufacturing tests and troubleshooting, as well as for
software debugging by authorized entities. The SJC of the i.MX 8M
Dual / 8M QuadLite / 8M Quad incorporates three security modes for
protecting against unauthorized accesses. Modes are selected
through eFUSE configuration.
SNVS
Secure Non-Volatile Storage Secure Non-Volatile Storage, including Secure Real Time Clock,
Security State Machine, and Master Key Control.
SPDIF1
SPDIF2
Sony Philips Digital
Interconnect Format
A standard audio file transfer format, developed jointly by the Sony
and Phillips corporations. It supports Transmitter and Receiver
functionality.
TEMPSENSOR
TZASC
Temperature Sensor
Temperature sensor
Trust-Zone Address Space
Controller
The TZASC (TZC-380 by Arm) provides security address region
control functions required for intended application. It is used on the
path to the DRAM controller.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 11
Modules list
Table 3. i.MX 8M Dual / 8M QuadLite / 8M Quad modules list (continued)
Block mnemonic
Block name
Brief description
UART1
UART2
UART3
UART4
UART Interface
Each of the UARTv2 modules supports the following serial data
transmit/receive protocols and configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even,
odd, or none)
• Programmable baud rates up to 4 Mbps. This is a higher max
baud rate relative to the 1.875 MHz, which is stated by the
TIA/EIA-232-F standard.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting
auto-baud
uSDHC1
uSDHC2
SD/MMC and SDXC
The i.MX 8M Dual / 8M QuadLite / 8M Quad SoC characteristics:
Enhanced Multi-Media Card / All the MMC/SD/SDIO controller IPs are based on the uSDHC IP.
Secure Digital Host Controller They are designed to support:
• SD/SDIO standard, up to version 3.0.
• MMC standard, up to version 5.0.
• 1.8 V and 3.3 V operation, but do not support 1.2 V operation.
• 1-bit/4-bit SD and SDIO modes, 1-bit/4-bit/8-bit MMC mode.
One uSDHC controller (SD1) can support up to an 8-bit interface, the
other controller (SD2) can only support up to a 4-bit interface.
USB 3.0/2.0
VPU
2x USB 3.0/2.0 controllers and Two USB controllers and PHYs that support USB 3.0 and USB 2.0.
PHYs
Each USB instance contains:
• USB 3.0 core, which can operate in both 3.0 and 2.0 mode
Video Processing Unit
A high performing video processing unit (VPU), which covers many
SD-level and HD-level video decoders. See the i.MX 8M Dual / 8M
QuadLite / 8M Quad Applications Processor Reference Manual
(IMX8MDQLQRM) for a complete list of the VPU’s decoding and
encoding capabilities.
WDOG1
WDOG2
WDOG3
Watchdog
The watchdog (WDOG) timer supports two comparison points
during each counting period. Each of the comparison points is
configurable to evoke an interrupt to the Arm core, and a second
point evokes an external event on the WDOG line.
XTALOSC
Crystal Oscillator interface
The XTALOSC module enables connectivity to an external crystal
oscillator device.
2.1
Recommended connections for unused interfaces
The recommended connections for unused analog interfaces can be found in the Section, “Unused
Input/Output Terminations,” in the hardware development guide for the device.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
12
NXP Semiconductors
Electrical characteristics
3 Electrical characteristics
This section provides the device and module-level electrical characteristics for the i.MX 8M Dual / 8M
QuadLite / 8M Quad processors.
3.1
Chip-level conditions
This section provides the device-level electrical characteristics for the IC. See Table 4 for a quick reference
to the individual tables and sections.
Table 4. i.MX 8M Dual / 8M QuadLite / 8M Quad chip-level conditions
For these characteristics, …
Absolute maximum ratings
Topic appears …
on page 13
on page 15
on page 15
on page 18
on page 19
on page 20
on page 23
FPBGA package thermal resistance
Operating ranges
External clock sources
Maximum supply currents
Power modes
USB PHY Suspend current consumption
3.1.1
Absolute maximum ratings
CAUTION
Stresses beyond those listed under Table 5 may affect reliability or cause
permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions beyond those
indicated in the operating ranges or parameters tables is not implied.
Table 5. Absolute maximum ratings
Parameter description
Symbol
Min
Max
Unit
Notes
Core supply voltages
VDD_ARM
VDD_SOC
0
1.1
V
1.1 V is for
VDD_ARM
overdrive
Power supply for GPU
Power supply for VPU
VDD_GPU
VDD_VPU
0
0
0
1.1
1.1
1.1
V
V
V
1.1 V is for
overdrive
Nominal
mode
Overdrive
mode
Core voltage
VDD_DRAM
0
0
1.05
1.42
V
V
—
—
DDR I/O supply voltage
NVCC_DRAM
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 13
Electrical characteristics
Parameter description
Table 5. Absolute maximum ratings (continued)
Symbol
Min
Max
Unit
Notes
Power supply for analog domain
GPIO supply voltage
VDDA_1P8
0
0
1.98
3.6
V
V
—
NVCC_JTAG, NVCCGPIO1,
NVCC_ENT, NVCC_SD1,
NVCC_SD2, NVCC_NAND,
NVCC_SA1, NVCC_SAI2,
NVCC_SAI3, NVCC_SAI5,
NVCC_ECSPI, NVCC_I2C,
NVCC_UART
1.8 V
mode/3.3 V
mode
SNVS IO supply voltage
NVCC_SNVS
0
3.6
V
3.3 V mode
only
VDD_SNVS supply voltage
PLL 1.8 V supply voltage
Supply for 25 MHz crystal
Supply for 27 MHz crystal
HDMI supply voltage
VDD_SNVS
VDDA_DRAM
VDDA_1P8_XTAL_25M
VDDA_1P8_XTAL_27M
HDMI_AVDDCLK
HDMI_AVDDIO
HDMI_AVDDCORE
PCIE_VP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.99
1.89
1.98
1.98
0.99
1.90
0.99
0.99
3.63
0.99
1.1
V
V
V
V
—
—
—
—
—
—
—
—
—
—
—
—
—
PCIe PHY supply voltage
MIPI supply voltage
V
V
V
V
V
V
V
V
PCIE_VPH
PCIE_VPTX
MIPI_VDDA
MIPI_VDDHA
1.98
1.1
MIPI_VDD
MIPI_VDDPLL
1.1
USB high supply voltage
USB_VBUS input detected
USB1_VDD33, USB1_VPH,
USB2_VDD33, USB2_VPH
3.63
—
—
—
USB1_VBUS,
USB2_VBUS
0
0
5.25
V
V
Input voltage on USB*_DP,
USB*_DN pins
USB1_DP/USB1_DN
USB2_DP/USB2_DN
USB1_VDD33
USB2_VDD33
Temperature sensor
Fuse power
VDD_1P8_TSENSOR
EFUSE_VQPS
Vin/Vout
0
0
0
1.98
1.98
V
V
V
—
—
—
—
Input/output voltage range
ESD damage immunity:
OVDD1+0.3
Vesd
V
• Human Body Model (HBM)
• Charge Device Model (CDM)
—
—
2000
500
Storage temperature range
TSTORAGE
–40
150
oC
—
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
14 NXP Semiconductors
Electrical characteristics
1
OVDD is the I/O supply voltage.
3.1.2
Thermal resistance
3.1.2.1
FPBGA package thermal resistance
Table 6 displays the thermal resistance data.
Table 6. Thermal resistance data
17 x 17
Unit
Rating
Test conditions
Symbol
pkg value
Junction to Ambient1
Single-layer board (1s); natural convection2
Four-layer board (2s2p); natural convection2
RJA
RJA
oC/W
Bare die: 16.4
oC/W
Junction to Ambient1
Single-layer board (1s); airflow 200 ft/min2,3
Four-layer board (2s2p); airflow 200 ft/min2,3
RJA
RJA
oC/W
oC/W
Bare die: 13.9
Bare die: 4.6
Bare die: 0.1
Junction to Board1,4
Junction to Case1,5
—
—
RJB
RJC
oC/W
oC/W
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
Per JEDEC JESD51-2 with the single layer board horizontal. Thermal test board meets JEDEC specification for the specified
package.
3
4
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
3.1.3
Operating ranges
Table 7 provides the operating ranges of the i.MX 8M Dual / 8M QuadLite / 8M Quad processors. For
details on the chip's power structure, see the “Power Management Unit (PMU)” chapter of the i.MX 8M
Dual / 8M QuadLite / 8M Quad Applications Processor Reference Manual (IMX8MDQLQRM).
Table 7. Operating ranges
Parameter description
Symbol
Min
Typ
Max1
Unit
Comment
Power supply for Quad-A53
VDD_ARM
0.81
0.9
1.05
V
Nominalmode—themaximum
Arm core frequency supported
in this mode is 1000 MHz.
0.9
1.0
0.9
1.05
0.99
V
V
Overdrive mode—the
maximum Arm core frequency
supported in this mode is
defined in Table 2.
Power supply for SoC logic
VDD_SOC
0.81
—
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 15
Electrical characteristics
Table 7. Operating ranges (continued)
Parameter description
Symbol
Min
Typ
Max1
Unit
Comment
Power supply for GPU
VDD_GPU
0.81
0.9
1.05
V
Nominalmode—themaximum
GPU frequency supported in
this mode is 800 MHz.
0.9
0.81
0.9
1.0
0.9
1.0
1.05
1.05
1.05
V
V
V
Overdrive mode—the
maximum GPU frequency
supported in this mode is 1
GHz.
Power supply for VPU
VDD_VPU
Nominalmode—themaximum
VPU frequency supported in
this mode is 550/500/588
MHz.
Overdrive mode—the
maximum VPU G2/G1/AXI
Bus frequency supported in
this mode is 660/600/800
MHz.
Core voltage
VDD_DRAM
0.81
0.99
1.62
0.9
1.0
1.8
1.05
1.05
1.98
V
V
V
Nominalmode—themaximum
DRAM working frequency
supported in this mode is 933
MHz.
Overdrive mode—the
maximum DRAM working
frequency supported in this
mode is 1600 MHz
Power Supply Analog
Domain
VDDA_1P8
Power for internal analog
blocks—must match the range
of voltages that the
rechargeable backup battery
supports.
PLL 1.8 V supply voltage
VDDA_DRAM
VDD_SNVS
1.71
0.81
1.8
0.9
1.89
0.99
V
V
—
—
Backup battery supply
range
Supply for 25 MHz crystal
Supply for 27 MHz crystal
Temperature sensor
VDD_1P8_XTAL_25M
VDD_1P8_XTAL_27M
VDD_1P8_TSENSOR
1.6
1.6
1.6
1.8
1.8
1.8
1.98
1.98
1.98
V
V
V
—
—
—
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
16 NXP Semiconductors
Electrical characteristics
Table 7. Operating ranges (continued)
Parameter description
Symbol
Min
Typ
Max1
Unit
Comment
USB supply voltages
USB1_VDD33/
USB1_VPH
3.069
3.3
3.63
V
This rail is for USB
USB2_VDD33/
USB2_VPH
3.069
0.837
0.837
3.3
3.63
0.990
0.990
V
V
V
This rail is for USB
USB1/2_DVDD
0.900
0.900
0.9 V supply for USB high
speed operation
USB1/2_VP
0.9 V supply for USB super
speed operation
USB1/2_VPTX
0.837
0.8
0.900
1.4
0.990
5.25
V
V
0.9 V supply for PHY transmit
—
USB1_VBUS/
USB2_VBUS
DDR I/O supply voltage
NVCC_DRAM
DRAM_VREF
1.06
1.14
1.10
1.2
1.17
1.26
V
V
V
V
LPDDR4
DDR4
1.28
1.35
1.42
DDR3L
0.49 x
0.5 x
0.51 x
Set to one-half NVCC_DRAM
NVCC_D NVCC_D NVCC_D
RAM
RAM
RAM
GPIO supply voltages
NVCC_JTAG,
NVCC_SD1,
NVCC_SD2,
NVCC_NAND,
NVCC_SAI1,
NVCC_SAI2,
NVCC_SAI3,
NVCC_SAI5,
NVCC_ECSPI,
NVCC_I2C,
1.65,
3.0
1.8,
3.3
1.95,
3.6
V
—
NVCC_UART
NVCC_ENET
1.65,
2.25
3.0
1.8,
2.5
3.3
1.95,
2.75
3.6
V
V
—
NVCC_GPIO1
1.65
3.0
1.8,
3.3
1.95,
3.6
Power for GPIO1_IO00 ~
GPIO1_IO15
NVCC_SNVS
3.0
3.3
3.6
V
V
Power for 3.3 V only
HDMI supply voltage
HDMI_AVDDCLK
0.850
0.900
0.990
0.9 V supply for HDMI high
speed clock
HDMI_AVDDIO
1.700
0.850
1.800
0.900
1.900
0.990
V
V
1.8 V supply for HDMI bias
and PLL
HDMI_AVDDCORE
0.9 V supply for HDMI analog
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 17
Electrical characteristics
Table 7. Operating ranges (continued)
Parameter description
Symbol
Min
Typ
Max1
Unit
Comment
MIPI supply voltage
MIPI_VDDA
MIPI_VDDHA
MIPI_VDD
0.81
1.62
0.81
0.81
0.9/1.0
1.8
1.1
1.98
1.1
V
V
V
V
V
Analog core power supply
Analog IO power supply
Digital core power supply
Analog supply for MIPI PLL
Supplied from PMIC
0.9/1.0
0.9/1.0
MIPI_VDDPLL
PCIE_VPH
1.1
Voltage rails supplied from
1.8 V PHY
1.674
3.069
1.8
3.3
1.98
3.63
PCIE_VP, PCIE_VPTX
Tdelta
0.837
—
0.9
3
0.99
—
V
Supplied from PMIC
Temperature sensor
accuracy
°C Typical accuracy over the
range –40°C to 125°C
Fuse power
EFUSE_VQPS
1.71
0
1.8
—
1.98
+95
V
Power supply for internal use
T
J
Junction temperature,
consumer
oC See Table 2 forcompletelistof
junction temperature
capabilities.
1
Applying the maximum voltage results in maximum power consumption and heat generation. A voltage set point = (Vmin + the
supply tolerance) is recommended. This result in an optimized power/speed ratio.
3.1.4
External clock sources
A 25 MHz oscillator is used as the primary clock source for the PLLs to generate the clock for CPU, BUS,
and high-speed interfaces. For fractional PLLs, the 25 MHz clock from the oscillator can be directly used
as the PLL reference clock.
A 27 MHz oscillator is used as the reference clock for HDMI PHY. Also it can be used as the alternative
source for the fractional PLLs.
A 32 kHz clock input pin is used as the RTC clock source. It is expected to be supplied by an external
32.768 kHz oscillator.
Two pairs of differential clock inputs, named as CLK1P and CLK1N, can be used as the reference clock
for the PLL. This is mainly used for a high-speed clock input during testing.
Four clock inputs to the CCM from normal GPIO pads via IOMUX can be used as the clock sources in the
CCM.
Table 8 shows the interface frequency requirements.
Table 8. External input clock frequency
Parameter description
Symbol
Min
Typ
Max
Unit
RTC1,2
fckil
fxtal
fxtal
—
20
20
32.7683
25
—
40
40
kHz
MHz
MHz
XTALI_25M/XTALO_25M2
XTALI_27M/XTALO_27M2
27
1
External oscillator or a crystal with internal oscillator amplifier.
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18 NXP Semiconductors
Electrical characteristics
2
3
The required frequency stability of this clock source is application dependent.
Recommended nominal frequency 32.768 kHz.
The typical values shown in Table 8 are required for use with NXP BSPs to ensure precise time keeping
and USB operation. For RTC operation, two clock sources are available.The decision of choosing a clock
source should be made based on real-time clock use and precision timeout.
3.1.5
Maximum supply currents
Power consumption is highly dependent on the application. Estimating the maximum supply currents
required for power supply design is difficult because the use cases that requires maximum supply current
is not a realistic use cases.
To help illustrate the effect of the application on power consumption, data was collected while running
consumer standard benchmarks that are designed to be compute and graphic intensive. The results pro-
vided are intended to be used as guidelines for power supply design.
1
Table 9. Maximum supply currents
Power rail
Max current
Unit
VDD_ARM
384 to 24101
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD_SOC
1400 to 18701
VDD_GPU
0 to 20401
VDD_VPU
0 to 6101
VDD_DRAM
VDDA_0P9
VDDA_1P8
VDDA_DRAM
VDD_SNVS
NVCC_SNVS
NVCC_<XXX>
600 to 8701
50
20
30
5
5
Imax = N x C x V x (0.5 x F)
Where:
N—Number of IO pins supplied by the power line
C—Equivalent external capacitive load
V—IO voltage
(0.5 x F)—Data change rate. Up to 0.5 of the clock
rate (F).
In this equation, Imax is in Amps, C in Farads, V in
Volts, and F in Hertz.
NVCC_DRAM
DRAM_VFEF
USB1_DVDD
USB2_DVDD
USB1_VP
375 to 7501
mA
mA
mA
mA
mA
10
9.2
9.2
35.7
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 19
Electrical characteristics
1
Table 9. Maximum supply currents (continued)
Power rail Max current
Unit
USB2_VP
35.7
21.2
21.2
24.5
24.5
20.3
20.3
38.1
38.1
43
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
USB1_VPTX
USB2_VPTX
USB1_VDD33
USB2_VDD33
USB1_VPH
USB2_VPH
PCIE_VP (PCIE1)
PCIE_VP (PCIE2)
PCIE_VPH (PCIE1)
PCIE_VPH (PCIE2)
PCIE_VPTX (PCIE1)
PCIE_VPTX (PCIE2)
HDMI_AVDDCLK
HDMI_AVDDCORE
HDMI_AVDDIO
MIPI_VDDA (DSI)
MIPI_VDDHA (DSI)
MIPI_VDD (DSI)
MIPI_VDDPLL (DSI)
MIPI_VDDA (CSI1/2)
MIPI_VDDHA (CSI1/2)
EFUSE_VQPS
43
14.3
14.3
95.89
6.551
17.1
4.2
mA
mA
mA
mA
mA
mA
mA
mA
14.4
3.8
18.79
2.97
96.35
1
Use case dependent
3.1.6
Power modes
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors support the following power modes:
•
RUN Mode: All external power rails are on, CPU is active and running; other internal modules can
be on/off based on application.
•
IDLE Mode: When there is no thread running and all high-speed devices are not active, the CPU
can automatically enter this mode. The CPU can be in the power-gated state but with L2 data
retained, DRAM and the bus clock are reduced. Most of the internal logic is clock gated but still
remains powered. The M4 core can remain running. Compared with RUN mode, all the external
power rails from the PMIC remain the same, and most of the modules still remain in their state.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
20 NXP Semiconductors
Electrical characteristics
•
•
•
Deep Sleep Mode (DSM): The most efficient power saving mode where all the clocks are off and
all the unnecessary power supplies are off.
SNVS Mode: This mode is also called RTC mode. Only the power for the SNVS domain remains
on to keep RTC and SNVS logic alive.
OFF Mode: All power rails are off.
Table 10. Chip power in different LP mode
Mode
Supply
VDD_SNVS (1.0 V)
Max.1
Unit
SNVS
1.39
mA
NVCC_SNVS (3.6 V)
Total2
4.25
17
mW
mA
Deep Sleep Mode (DSM)
VDD_SOC (1.0 V)
VDDA_1P8 (2.0 V)
VDDA_0P9 (1.0 V)
VDDA_DRAM (1.8 V)
VDD_SNVS (1.0 V)
NVCC_SNVS (3.3 V)
NVCC_DRAM (1.17 V)
Total2
148.50
12.82
0.30
0.50
0.25
4.80
4.51
197
mW
mA
IDLE
VDD_ARM (1.0 V)
VDD_SOC (1.0 V)
VDD_DRAM (1.0 V)
VDDA_1P8 (2.0 V)
VDDA_0P9 (1.0 V)
VDDA_DRAM (1.8 V)
VDD_SNVS (1.0 V)
NVCC_SNVS (3.3 V)
NVCC_DRAM (1.17 V)
Total2
152.10
132.90
44.10
13.53
0.30
1.32
0.25
4.34
13.12
389
mW
W
RUN
Total
1 to 4
1
2
All the power numbers defined in the table are based on typical silicon at 25oC. Use case dependent
Sum of the listed supply rails.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 21
Electrical characteristics
Table 11 summarizes the external power supply states in all the power modes.
Table 11. The power supply states
Power rail
VDD_ARM
OFF
SNVS
SUSPEND
OFF
IDLE
RUN
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
VDD_SOC
ON
VDD_GPU
OFF
OFF
OFF
ON
ON/OFF
ON/OFF
ON
VDD_VPU
VDD_DRAM
VDDA_0P9
VDDA_1P8
VDDA_DRAM
VDD_SNVS
NVCC_SNVS
NVCC_<XXX>
NVCC_DRAM
DRAM_VREF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
ON
ON
ON
ON
OFF
ON
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
22 NXP Semiconductors
Electrical characteristics
3.1.7
USB PHY Suspend current consumption
Low power Suspend Mode
3.1.7.1
The VBUS Valid comparators and their associated bandgap circuits are enabled by default. Table 12
shows the USB interface current consumption in Suspend mode with default settings.
1
Table 12. USB PHY current consumption in Suspend mode
USB1_VDD33
USB2_VDD33
154
154
Current
1
Low Power Suspend is enabled by setting USBx_PORTSC1 [PHCD]=1 [Clock Disable (PLPSCD)].
3.1.7.2
Power-Down modes
Table 13 shows the USB interface current consumption with only the OTG block powered down.
1
Table 13. USB PHY current consumption in Sleep mode
USB1_VDD33
USB2_VD33
520
520
Current
1
VBUS Valid comparators can be disabled through software by setting USBNC_OTG*_PHY_CFG2[OTGDISABLE0] to 1. This
signal powers down only the VBUS Valid comparator, and does not control power to the Session Valid Comparator, ADP
Probe and Sense comparators, or ID detection circuitry.
In Power-Down mode, everything is powered down, including the USB_VBUS valid comparators and
their associated bandgap circuity in typical condition. Table 14 shows the USB interface current
consumption in Power-Down mode.
1
Table 14. USB PHY current consumption in Power-Down mode
USB1_VDD33
USB2_VDD33
146
146
Current
1
The VBUS Valid Comparators and their associated bandgap circuits can be disabled through software by setting
USBNC_OTG*_PHY_CFG2[OTGDISABLE0] to 1 and USBNC_OTG*_PHY_CFG2[DRVVBUS0] to 0, respectively.
3.1.8
PCIe PHY 2.1 DC electrical characteristics
Table 15. PCIe recommended operating conditions
Parameter
Description
Min
Max
Unit
PCIE_VP
PCIE_VPTX
PCIE_VPH
Low Power Supply Voltage for PHY Core
PHY transmit supply
—
—
0.837
0.837
1.674
3.069
0.99
0.99
1.98
3.63
V
High Power Supply Voltage for PHY Core
1.8
3.3
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 23
Electrical characteristics
Parameter
Table 15. PCIe recommended operating conditions (continued)
Description
Min
Max
Unit
TA
TJ
Commercial Temperature Range
0
70
°C
°C
Simulation Junction Temperature Range
-40
125
Note: VDD should have no more than 40 mVpp AC power supply noise superimposed on the high power supply voltage for the
PHY core (1.8 V nominal DC value). At the same time, VDD should have no more than 20 mVpp AC power supply noise
superimposed on the low power supply voltage for the PHY core (1.0 V nominal value or 1.1 V overdrive DC value).
The power supply voltage variation for the PHY core should have less than 5% including the board-level power supply variation
and on-chip power supply variation due to the finite impedances in the package.
Table 16. PCIe DC electrical characteristics
Parameter
Description
Min
Typ
Max
Unit
PCIE1_VP, Power Supply Voltage
PCIE2_VP
0.9 - 7%
0.9
0.9 + 10%
V
PD
Power Consumption
Normal
—
—
—
—
40
27
7
—
—
—
—
mW
mW
mW
mW
Partial Mode
Slumber Mode
Full Powerdown
0.2
Table 17. PCIe PHY high-speed characteristics
High Speed I/O Characteristics
Description
Symbol
Speed
Min.
Typ.
Max.
Unit
Unit Interval
UI
2.5 Gbps
5.0 Gbps
2.5 Gbps
5.0 Gbps
2.5 Gbps
5.0 Gbps
2.5 Gbps
5.0 Gbps
2.5 Gbps
5.0 Gbps
2.5 Gbps
5.0 Gbps
—
—
400
200
—
—
—
ps
TX Serial output rise time (20% to 80%)
TX Serial output fall time (80% to 20%)
TX Serial data output voltage (Differential, pk–pk)
PCIe Tx deterministic jitter < 1.5 MHz
PCIe Tx deterministic jitter > 1.5 MHz
TTXRISE
TTXFALL
VTX
TRJ
100
100
100
100
800
600
3
—
ps
—
—
—
—
ps
—
—
—
1100
900
—
mVp–p
ps, rms
—
—
3
—
—
TDJ
—
—
20
10
ps, pk–pk
—
—
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24 NXP Semiconductors
Electrical characteristics
Table 17. PCIe PHY high-speed characteristics (continued)
High Speed I/O Characteristics
Description
Symbol
Speed
Min.
Typ.
Max.
Unit
RX Serial data input voltage (Differential pk–pk)
VRX
2.5 Gbps
5.0 Gbps
120
120
—
—
1200
1200
mVp–p
Table 18. PCIe PHY reference clock timing requirements (vp is PIE_VP, 0.9 V power supply)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
FREF_OFFSET
DJREF_CLK
Reference clock frequency offset
Reference clock cycle to cycle jitter
Duty cycle
-300
—
—
—
—
—
—
—
30
35
ppm
ps
—
DJ across all frequencies
—
DCREF_CLK
VCMREF_CLK
VDREF_CLK
VOLREF_CLK
40
60
%
Common mode input level
Differential input swing
0
vp
V
Differential inputs
Differential inputs
-0.3
-0.3
—
VPP
V
Single-ended input logic low
-0.3
If single-ended input is
used.
VOHREF_CLK
Single-ended input logic high
vp - 0.3
—
vp + 0.3
V
If single-ended input is
used.
SWREF_CLK
Input edge rate
—
—
—
—
—
V/ns
ps
—
—
REF_CLK_SKEW
Reference clock skew ( )
200
PCIe PHY interface is compliant with PCIe Express GEN2.
3.2
Power supplies requirements and restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation
from these sequences may result in the following situations:
•
•
•
Excessive current during power-up phase
Prevention of the device from booting
Irreversible damage to the processor (worst-case scenario)
3.2.1
Power-up sequence
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors have the following power-up sequence
requirements:
•
•
•
Turn on NVCC_SNVS
Turn on VDD_SNVS
RTC_RESET_B release (after 32K clock stable and before POR_B release, no constraint with any
other power supplies)
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NXP Semiconductors 25
Electrical characteristics
•
•
Turn on VDD_SOC and VDDA_0P9
Turn on VDD_ARM, VDD_GPU, VDD_VPU, and VDD_DRAM (no sequence between these
four rails)
•
•
•
Turn on VDDA_1P8_XXX, VDDA_DRAM (no sequence between these rails)
Turn on NVCC_XXX and NVCC_DRAM (no sequence between these rails)
POR_B release (it should be asserted during the entire power up sequence)
If the GPU/VPU is not used during the ROM boot sequence, VDD_GPU/VDD_VPU can stay off to reduce
the power during boot, and then turned on by software afterwards.
During the chip power up, the power of the PCIe PHY, USB PHY, HDMI PHY, and MIPI PHY could stay
off. After chip power up, the power of these PHys should be turned on. If any of the PHY power are turned
on during the power up sequence, the POR_B can be released after the PHY power is stable.
3.2.2
Power-down sequence
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors have the following power-down sequence
requirements:
•
•
•
Turn off NVCC_SNVS and VDD_SNVS last
Turn off VDD_SOC after the other power rails or at the same time as other rails
No sequence for other power rails during power down
3.2.3
Power supplies usage
I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This
can cause internal latch-up and malfunctions due to reverse current flows. For information about the I/O
power supply of each pin, see “Power Rail” columns in the pin list tables of Section 5, Package
information and contact assignments.”
Table 19 lists the modules in each power domain.
Table 19. The modules in the power domains
Power Domain
Modules in the domain
Arm A53
VDD_ARM
VDD_GPU
VDD_VPU
VDD_DRAM
VDD_SNVS
VDD_SOC
GC7000L GPU
G1 and G2 VPU
DRAM controller and PHY
SNVS_LP
All the other modules
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26 NXP Semiconductors
Electrical characteristics
3.3
PLL electrical characteristics
Table 20. PLL electrical parameters
PLL type
Parameter
Value
AUDIO_PLL1
Clock output range
Reference clock
Lock time
650 MHz ~ 1.3 GHz
25 MHz
50 s
Jitter
1% of output period, 50 ps
650 MHz ~ 1.3 GHz
25 MHz
AUDIO_PLL2
Clock output range
Reference clock
Lock time
50 s
Jitter
1% of output period, 50 ps
650 MHz ~ 1.3 GHz
25 MHz
VIDEO_PLL1
VIDEO_PLL2
SYS_PLL1
SYS_PLL2
SYS_PLL3
ARM_PLL
Clock output range
Reference clock
Lock time
50 s
Clock output range
Reference clock
Lock time
650 MHz ~ 1.3 GHz
25 MHz
70 s
Clock output range
Reference clock
Lock time
800 MHz
25 MHz
70 s
Clock output range
Reference clock
Lock time
1 GHz
25 MHz
70 s
Clock output range
Reference clock
Lock time
600 MHz ~ 1GHz
25 MHz
70 s
Clock output range
Reference clock
Lock time
800 MHz ~1.6 GHz
25 MHz
50 s
DRAM_PLL
Clock output range
Reference clock
Lock time
400 MHz–800 MHz
25 MHz
70 s
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NXP Semiconductors 27
Electrical characteristics
Table 20. PLL electrical parameters (continued)
Parameter
PLL type
Value
GPU_PLL
Clock output range
Reference clock
Lock time
800 MHz ~1.6 GHz
25 MHz
50 s
VPU_PLL
Clock output range
Reference clock
Lock time
400 MHz ~ 800 MHz
25 MHz
50 s
3.4
On-chip oscillators
3.4.1
OSC25M and OSC27M
A 25 MHz oscillator is used as the primary clock source for the PLLs to generate the clock for the CPU,
BUS, and high-speed interfaces. For fractional PLLs, the 25 MHz clock from the oscillator can be used as
the PLL reference clock directly.
A 27 MHz oscillator is used as the reference clock for HDMI PHY. It can also be used as the alternative
source for the fractional PLLs.
Table 21 lists the electrical specifications of this oscillator when loaded with an NX5032GA 40 MHz
crystal unit at 40 MHz frequency. All values are valid only for the device TJ operating specification of -40
o
o
C to 125 C.
Table 21. Electrical specification of oscillator @ 1.8 V
Parameter
Min
Typ
Max
Unit
Voltage swing on external pin1
250
—
—
—
800
4
mV
mA
Power consumption (analog
supply RMS current in OSC
mode)2, 3
Start-up time1, 2
—
—
2
ms
1
The start-up time is dependent upon crystal characteristics, board leakage, etc.; high ESR and excessive capacitive loads can
cause long start-up time.
2
3
Electrical parameters are subject to change.
Maximum current is observed during startup. After oscillation is stable, the current from HV supply comes down.
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28 NXP Semiconductors
Electrical characteristics
Table 22 shows the transconductance specification of the oscillator (in mA/V).
Table 22. Transconductance specification of oscillator
GM_sel
Min
Max
111
10
25
Table 23 shows the input clock specifications.
Table 23. Input clock specification
Parameter
Min
Typ
Max
Unit
Clock Frequency in OSC mode
20
—
—
—
40
50
MHz
MHz
Input Clock Frequency in Bypass
mode
Input Clock Rise/Fall Time in
Bypass mode
—
—
1
ns
%
Input Clock Duty Cycle in Bypass
mode
47.50
50
52.50
Table 24 shows core output clock specification.
Table 24. Core output clock specification
Parameter
Min
Typ
Max
Unit
20
—
40
MHz
Output Clock Frequency in
OSC mode
45
50
55
%
Output Clock Duty Cycle in
OSC mode
OutputClockFrequencyinBypass
mode
—
—
—
40
—
150
0.1
50
50
500
0.5
60
MHz
fF
Capacitive Loading on Outputs
Clock
Output Clock Rise/Fall Time in
Bypass mode
ns
Output Clock Duty Cycle in
Bypass mode
%
Table 25 shows VIL/VIH specification at EXTAL.
Table 25. Transconductance specification of oscillator
Parameter
Condition
Min
Max
Unit
VILEXTAL
VIHEXTAL
VREF = 0.5 x avdd
(xosc HV supply)
0
VREF - 0.5
avdd
V
VREF + 0.5
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NXP Semiconductors 29
Electrical characteristics
3.5
I/O DC parameters
This section includes the DC parameters of the following I/O types:
•
•
•
General Purpose I/O (GPIO)
Double Data Rate I/O (DDR) for LPDDR4, DDR4, and DDR3L modes
Differential I/O (CLKx)
3.5.1
General purpose I/O (GPIO) DC parameters
Table 26 shows DC parameters for GPIO pads. The parameters in Table 26 are guaranteed per the
operating ranges in Table 7, unless otherwise noted.
Table 26. GPIO DC parameters
Parameter
Symbol
Test Conditions
Min VDD
Min
Typ
Max
Unit
High-level output voltage VOH (1.8 V)
,
V
DD - 0.2,
—
—
V
IOH = –100 A,
VDD - 0.45
IOH = –2 mA
VOH (3.3 V)
VDD - 0.2
2.4
—
—
—
—
V
V
V
Low-level output voltage
High-level input voltage
VOL (1.8 V)
Min VDD
,
—
0.2
0.2 x VDD
IOH = 100 A,
IOH = 3 mA
VOL (3.3 V)
—
0.2
0.4
VIH (1.8 V)
VIH (3.3 V)
ipp_lvttl_en = 0
ipp_lvttl_en = 1
ipp_lvttl_en = 0
0.7 x VDD
2
—
—
—
VDD
VDD
VDD
V
V
V
VIH_1VCOMS
0.7 x VDD
(3.3 V)
Low-level input voltage
VIL (1.8 V)
ipp_lvttl_en = 0
ipp_lvttl_en = 0
0
0
—
—
0.2 x VDD
V
V
VIL_emmc
(1.8 V)
0.35 x VDD
VIL (3.3 V)
ipp_lvttl_en = 1
ipp_lvttl_en = 0
0
0
—
—
0.8
V
V
VIL_emmc
(3.3 V)
0.25 x VDD
VIL_1vcmos
(3.3 V)
ipp_lvttl_en = 0
0
—
0.2 x VDD
V
Input hysteresis
VHYS (1.8 V)
ipp_hys = 1
—
—
0.15
0.2
30
—
—
V
VHYS (3.3 V)
ipp_hys = 1
V
Pull-up resistor
Pull-down resistor
—
—
IIH
IIL
—
—
—
—
30 x 0.75
95 x 0.75
-50
30 x 1.25
95 x 1.25
50
K
K
A
A
95
High level input current1
Low level input current1
—
-50
—
50
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30 NXP Semiconductors
Electrical characteristics
1
The leakage limit for the following pins: HDMI_TX (several) is 200 A; HDMI_AUX_N/P is 65 A; PMIC_ON_REQ is 60
A; PMIC_STBY_REQ is 80 A; RTC_RESET_B is 60 A; ONOFF is 60 A; POR_B is 60 A; and SD2_CD_B is 60
A.
3.5.2
DDR I/O DC electrical characteristics
The DDR I/O pads support LPDDR 4, DDR4, and DDR3L operational modes. The DDR Memory
Controller (DDRMC) is designed to be compatible with JEDEC-compliant SDRAMs.
DDRMC operation is contingent upon the board’s DDR design adherence to the DDR design and layout
requirements stated in the hardware development guide for the i.MX 8M Dual / 8M QuadLite / 8M Quad
application processor.
Table 27. DC input logic level
Characteristics
Symbol
VIH(DC)
VIL(DC)
Min
VREF +100
—
Max
—
Unit
1
mV
DC input logic high
DC input logic low
VREF –100
1
It is the relationship of the VDDQ of the driving device and the VREF of the receiving device that determines noise margins.
However, in the case of VIH(DC) max (that is, input overdrive), it is the VDDQ of the receiving device that is referenced.
Table 28. Output DC current drive
Characteristics
Symbol
OH(DC)
Min
Max
Unit
Output minimum source DC current1
Output minimum sink DC current
I
–4
—
mA
mA
V
IOL(DC)
VOH
4
0.9 x VDDQ
—
—
—
DC output high voltage(IOH = –0.1mA),2
DC output low voltage(IOL = 0.1mA),
VOL
0.1 x VDDQ
V
1
When DDS = [111] and without ZQ calibration.
2
The values of VOH and VOL are valid only for 1.2 V range.
1
Table 29. Input DC current
Characteristics
High level input current2,3
Low level input current,
Symbol
Min
–40
–40
Max
40
Unit
A
IIH
IIL
40
A
1
The leakage limit for the following pins: DRAM_AC00, DRAM_AC01, DRAM_AC20, and DRAM_AC21 are 300 A;
DRAM_RESET_N is 200 A.
The values of VOH and VOL are valid only for 1.2 V range.
Driver Hi-Z and input power-down (PD = High)
2
3
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NXP Semiconductors 31
Electrical characteristics
3.5.2.1
LPDDR4 mode I/O DC parameters
Table 30. LPDDR4 I/O DC electrical parameters
Test
Symbol
Parameters
Min
Max
Unit
Conditions
High-level output voltage
VOH
VOL
Ioh= -0.1 mA
0.9 x OVDD
—
—
V
V
Low-level output voltage
Iol= 0.1 mA
0.1 x OVDD
Input Reference Voltage
Vref
—
—
—
—
—
—
—
0.49 x OVDD 0.51 x OVDD
V
DC High-Level input voltage
DC Low-Level input voltage
Differential Input Logic High
Differential Input Logic Low
Pull-up/Pull-down Impedance Mismatch
240 unit calibration resolution
Vih_DC
Vil_DC
Vih_diff
Vil_diff
Mmpupd
Rres
VRef + 0.100
OVSS
0.26
OVDD
VRef – 0.100
See note1
-0.26
V
V
—
—
%
K
A
See note
–15
15
—
10
Keeper Circuit Resistance
Rkeep
Iin
—
110
-2.5
175
2.5
Input current (no pull-up/down)
VI = 0, VI = OVDD
1
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
3.5.3
Differential I/O port (CLKx_P/N)
The clock I/O interface is designed to be compatible with TIA/EIA 644-A standard. See TIA/EIA
STANDARD 644-A, Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface
Circuits (2001), for details.
The CLK1_P/CLK1_N is input only, while CLK2_P/CLK2_N is output only.
3.6
I/O AC parameters
This section includes the AC parameters of the following I/O types:
•
•
•
General Purpose I/O (GPIO)
Double Data Rate I/O (DDR) for DDR3L/DDR4/LPDDR4 modes
Differential I/O (CLKx)
The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 3 and
Figure 4.
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NXP Semiconductors
Electrical characteristics
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 3. Load circuit for output
OVDD
80%
80%
20%
0 V
20%
tr
Output (at pad)
tf
Figure 4. Output transition time waveform
3.6.1
General purpose I/O AC parameters
This section presents the I/O AC parameters for GPIO in different modes. Note that the fast or slow I/O
behavior is determined by the appropriate control bits in the IOMUXC control registers.
Table 31. Maximum input cell delay time
Max Delay PAD Y (ns)
Cell name
VDD = 1.62 V
T = 125°C
WCS model
VDD = 3.0V
T = 125°C
WCS model
—
—
PBIJGTOV36PUD_MCLAMP_LVGPIO_EW
1.54
1.3
Table 32. Output cell delay time for fixed load
Simulated Cell Delay A PAD (ns)
Parameter
VDD = 1.62 V, T = 125°C VDD = 2.97 V, T = 125°C
dse[2:0]
fsel[1:0]
Driver Type
CL = 15 pF
CL = 15 pF
011
011
100
100
101
101
00
11
00
11
00
11
3 x Slow Slew
3 x Fast Slew
4 x Slow Slew
4 x Fast Slew
5 x Slow Slew
5 x Fast Slew
3.1
2.1
3.7
2.3
3.1
2.1
3.3
2.6
3.9
2.8
3.5
2.5
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NXP Semiconductors 33
Electrical characteristics
Table 32. Output cell delay time for fixed load (continued)
Simulated Cell Delay A PAD (ns)
VDD = 1.62 V, T = 125°C VDD = 2.97 V, T = 125°C
Parameter
dse[2:0]
fsel[1:0]
Driver Type
CL = 15 pF
CL = 15 pF
111
111
00
11
7 x Slow Slew
7 x Fast Slew
2.9
1.8
3.1
2.3
Table 33. Maximum frequency of operation for input
Maximum frequency (MHz)
VDD = 1.8 V, CL = 15 pF, fast
—
—
VDD = 3.3 V, CL = 20 pF, fast
200
160
3.6.2
Clock I/O AC parameters—CLKx_N/CLKx_P
The differential output transition time waveform is shown in Figure 5.
vddi
50%
50%
ipp_do
0 V
Voh
Vol
Tphld
Tplhd
padn
70%
70%
30%
30%
Tthl
padp
Ttlh
Vod = padp - padn
0 V
0 V (differential)
Figure 5. Differential LVDS driver transition time waveform
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34 NXP Semiconductors
Electrical characteristics
Table 34 shows the AC parameters for clock I/O.
Table 34. I/O AC parameters of LVDS pad
Symbol
Parameter Test conditions
Min Typ Max Unit Notes
1
Tphld
Tplhd
Ttlh
Output Differential propagation delay high to low Rload = 100 between padp
—
—
—
—
—
—
—
—
—
—
—
—
0.92 ns
0.92
and padn,
Output Differential propagation delay low to high
Cload =2pF, at125°C, TYP, 1.62
2
3
V OVDD, and 0.9 V VDDI
Output Transition time low to high
0.58
Tthl
Output Transition time high to low
0.73
Tphlr
Tplhr
Input Differential propagation delay high to low
Input Differential propagation delay low to high
Rload = 100 between padp
and padn, at 125 °C, TYP, 1.62 V
OVDD, and 0.9 V VDDI
0.83 ns
0.83
4
Ttx
F
Transmitter startup time (ipp-obe low to high)
Operating frequency
—
—
—
—
—
40
ns
600 1000 MHz
—
1
At TYP, 125 °C, 1.62 V OVDD, and 0.9 V VDDI. Measurement levels are 50 - 50%. Output differential signal measured.
At TYP, 125 °C, 1.62 V OVDD, and 0.9 V VDDI. Measurement levels are 20 - 80%. Output differential signal measured.
At TYP, 125 °C, 1.62 V OVDD, and 0.9 V VDDI. Measurement levels are 50 - 50%.
2
3
4
TX startup time is defined as the time taken by transmitter for settling after its ipp_obe has been asserted. It is to stabilize the
current reference. Functionality is guaranteed only after the startup time.
3.7
Output buffer impedance parameters
This section defines the I/O impedance parameters of the i.MX 8M Dual / 8M QuadLite / 8M Quad
processors for the following I/O types:
•
•
•
Double Data Rate I/O (DDR) for LPDDR4, DDR4, and DDR3L modes
Differential I/O (CLKx)
USB battery charger detection open-drain output (USB_OTG1_CHD_B)
NOTE
DDR I/O output driver impedance is measured with “long” transmission
line of impedance Ztl attached to I/O pad and incident wave launched into
transmission line. Rpu/Rpd and Ztl form a voltage divider that defines
specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see Figure 6).
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NXP Semiconductors 35
Electrical characteristics
OVDD
PMOS (Rpu)
Ztl W, L = 20 inches
ipp_d
pad
predriver
Cload = 1p
NMOS (Rpd)
OVSS
U,(V)
VDD
(do)
Vin
t,(ns)
0
U,(V)
Vout (pad)
OVDD
Vref2
Vref1
Vref
t,(ns)
0
Vovdd - Vref1
Vref1
Rpu =
x Ztl
x Ztl
Vref2
Rpd =
Vovdd - Vref2
Figure 6. Impedance matching load for measurement
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
36 NXP Semiconductors
Electrical characteristics
3.7.1
DDR I/O output buffer impedance
Table 35 shows DDR I/O output buffer impedance of i.MX 8M Dual / 8M QuadLite / 8M Quad
processors.
Table 35. DDR I/O output buffer impedance
Typical
Test Conditions
Parameter
Symbol
DSE
(Drive Strength)
Unit
NVCC_DRAM = 1.35
V (DDR3L)
NVCC_DRAM = 1.1 V
(LPDDR4)
NVCC_DRAM = 1.2 V
(DDR4)
DDR_SEL = 11
DDR_SEL = 10
Output Driver
Impedance
Rdrv
000000
Hi-Z
240
120
80
Hi-Z
240
120
80
Hi-Z
240
120
80
000010
000110
001010
001110
011010
011110
111010
60
60
60
48
48
48
40
40
40
34
34
34
Note:
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.
2. Calibration is done against 240 external reference resistor.
3. Output driver impedance deviation (calibration accuracy) is 5% (max/min impedance) across PVTs.
3.7.2
Differential I/O output buffer impedance
The Differential CCM interface is designed to be compatible with TIA/EIA644-Astandard. See, TIA/EIA
STANDARD 644-A, Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface
Circuits (2001) for details.
3.7.3
USB battery charger detection driver impedance
The USB_OTG1_CHD_B open-drain output pin can be used to signal to power management and
monitoring device results of USB Battery Charger detection routines for the USB_OTG1 PHY instance.
Use of this pin requires an external pullup resistor, for more information see Table 5.
3.8
System modules timing
This section contains the timing and electrical parameters for the modules in each i.MX 8M Dual / 8M
QuadLite / 8M Quad processor.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors
37
Electrical characteristics
3.8.1
Reset timings parameters
Figure 7 shows the reset timing and Table 36 lists the timing parameters.
POR_B
(Input)
CC1
Figure 7. Reset timing diagram
Table 36. Reset timing parameters
ID
Parameter
Min Max
Unit
CC1
Duration of POR_B to be qualified as valid.
1
—
RTC_XTALI cycle
3.8.2
WDOG Reset timing parameters
Figure 8 shows the WDOG reset timing and Table 37 lists the timing parameters.
WDOGx_B
(Output)
CC3
Figure 8. WDOGx_B timing diagram
Table 37. WDOGx_B timing parameters
ID
Parameter
Duration of WDOG1_B Assertion
Min
Max
Unit
CC3
1
—
RTC_XTALI cycle
NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30 ms.
NOTE
WDOGx_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the
IOMUXC chapter of the i.MX 8M Dual / 8M QuadLite / 8M Quad
Applications Processor Reference Manual (IMX8MDQLQRM) for detailed
information.
3.9
External peripheral interface parameters
The following subsections provide information on external peripheral interfaces.
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38
NXP Semiconductors
Electrical characteristics
3.9.1
ECSPI timing parameters
This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing
parameters for master and slave modes.
3.9.1.1
ECSPI Master mode timing
Figure 9 depicts the timing of ECSPI in master mode. Table 38 lists the ECSPI master mode timing
characteristics.
ECSPIx_RDY_B
ECSPIx_SS_B
CS10
CS5
CS2
CS6
CS3
CS1
CS4
ECSPIx_SCLK
ECSPIx_MOSI
ECSPIx_MISO
CS2
CS3
CS7
CS9
CS8
Figure 9. ECSPI Master mode timing diagram
Table 38. ECSPI Master mode timing parameters
ID
Parameter
Symbol
Min
Max Unit
CS1 ECSPIx_SCLK Cycle Time–Read
ECSPIx_SCLK Cycle Time–Write
tclk
43
15
—
—
ns
ns
CS2 ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
tSW
21.5
7
CS3 ECSPIx_SCLK Rise or Fall1
tRISE/FALL
tCSLH
tSCS
—
—
—
—
—
1
ns
ns
ns
ns
ns
ns
ns
ns
CS4 ECSPIx_SS_B pulse width
Half ECSPIx_SCLK period
CS5 ECSPIx_SS_B Lead Time (CS setup time)
CS6 ECSPIx_SS_B Lag Time (CS hold time)
CS7 ECSPIx_MOSI Propagation Delay (CLOAD = 20 pF)
CS8 ECSPIx_MISO Setup Time
Half ECSPIx_SCLK period - 4
tHCS
Half ECSPIx_SCLK period - 2
tPDmosi
tSmiso
tHmiso
tSDRY
-1
18
0
—
—
—
CS9 ECSPIx_MISO Hold Time
CS10 RDY to ECSPIx_SS_B Time2
5
1
2
See specific I/O AC parameters Section 3.6, I/O AC parameters.”
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 39
Electrical characteristics
3.9.1.2
ECSPI Slave mode timing
Figure 10 depicts the timing of ECSPI in Slave mode. Table 39 lists the ECSPI Slave mode timing
characteristics.
ECSPIx_SS_B
CS5
CS6
CS2
CS1
CS4
ECSPIx_SCLK
ECSPIx_MISO
CS2
CS9
CS8
CS7
ECSPIx_MOSI
Figure 10. ECSPI Slave mode timing diagram
Table 39. ECSPI Slave mode timing parameters
ID
Parameter
Symbol
Min
Max Unit
CS1 ECSPIx_SCLK Cycle Time–Read
ECSPI_SCLK Cycle Time–Write
tclk
15
43
—
—
ns
ns
CS2 ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
tSW
7
21.5
CS4 ECSPIx_SS_B pulse width
tCSLH
tSCS
Half ECSPIx_SCLK period
—
—
—
—
—
19
ns
ns
ns
ns
ns
ns
CS5 ECSPIx_SS_B Lead Time (CS setup time)
CS6 ECSPIx_SS_B Lag Time (CS hold time)
CS7 ECSPIx_MOSI Setup Time
5
5
4
4
4
tHCS
tSmosi
tHmosi
tPDmiso
CS8 ECSPIx_MOSI Hold Time
CS9 ECSPIx_MISO Propagation Delay (CLOAD = 20 pF)
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40 NXP Semiconductors
Electrical characteristics
3.9.2
Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC
timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (single data
rate) timing, eMMC4.4/4.41 (dual data rate) timing and SDR104/50 (SD3.0) timing.
3.9.2.1
SD/eMMC4.3 (single data rate) AC timing
Figure 11 depicts the timing of SD/eMMC4.3, and Table 40 lists the SD/eMMC4.3 timing characteristics.
SD4
SD2
SD1
SD5
SDx_CLK
SD3
SD6
Output from uSDHC to card
SDx_DATA[7:0]
SD7
SD8
Input from card to uSDHC
SDx_DATA[7:0]
Figure 11. SD/eMMC4.3 timing
Table 40. SD/eMMC4.3 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
1
SD1 Clock Frequency (Low Speed)
fPP
0
0
400
25/50
20/52
400
—
kHz
MHz
MHz
kHz
ns
2
Clock Frequency (SD/SDIO Full Speed/High Speed)
Clock Frequency (MMC Full Speed/High Speed)
Clock Frequency (Identification Mode)
fPP
3
fPP
0
fOD
tWL
100
7
SD2 Clock Low Time
SD3 Clock High Time
SD4 Clock Rise Time
SD5 Clock Fall Time
tWH
tTLH
tTHL
7
—
ns
—
—
3
ns
3
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6 uSDHC Output Delay tOD 6.6
3.6
ns
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 41
Electrical characteristics
Table 40. SD/eMMC4.3 interface timing specification (continued)
Parameter Symbols Min
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
ID
Max
Unit
SD7 uSDHC Input Setup Time
SD8 uSDHC Input Hold Time4
tISU
tIH
2.5
1.5
—
—
ns
ns
1
2
In Low-Speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In Normal (Full) -Speed mode for SD/SDIO card, clock frequency can be any value between 0 – 25 MHz. In High-speed mode,
clock frequency can be any value between 0 – 50 MHz.
3
4
In Normal (Full) -Speed mode for MMC card, clock frequency can be any value between 0 – 20 MHz. In High-speed mode,
clock frequency can be any value between 0 – 52 MHz.
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
3.9.2.2
eMMC4.4/4.41 (dual data rate) AC timing
Figure 12 depicts the timing of eMMC4.4/4.41. Table 41 lists the eMMC4.4/4.41 timing characteristics.
Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).
SD1
SDx_CLK
SD2
SD2
Output from eSDHCv3 to card
SDx_DATA[7:0]
......
......
SD3
SD4
Input from card to eSDHCv3
SDx_DATA[7:0]
Figure 12. eMMC4.4/4.41 timing
Table 41. eMMC4.4/4.41 interface timing specification
ID
Parameter
Symbols
Card Input Clock
Min
Max
Unit
SD1
SD1
Clock Frequency (eMMC4.4/4.41 DDR)
Clock Frequency (SD3.0 DDR)
fPP
fPP
0
0
52
50
MHz
MHz
uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
uSDHC Output Delay tOD 2.7
uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
SD2
6.9
ns
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42 NXP Semiconductors
Electrical characteristics
Table 41. eMMC4.4/4.41 interface timing specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
SD3
SD4
uSDHC Input Setup Time
uSDHC Input Hold Time
tISU
tIH
2.4
1.3
—
—
ns
ns
3.9.2.3
HS400 DDR AC timing—eMMC5.0 only
Figure 13 depicts the timing of HS400 mode, and Table 42 lists the HS400 timing characteristics. Be
aware that only data is sampled on both edges of the clock (not applicable to CMD). The CMD
input/output timing for HS400 mode is the same as CMD input/output timing for SDR104 mode. Check
SD5, SD6, and SD7 parameters in Table 44 SDR50/SDR104 Interface Timing Specification for CMD
input/output timing for HS400 mode.
SD1
SD3
SD2
SCK
SD4
SD5
SD5
SD4
DAT0
Output from
uSDHC to eMMC
DAT1
...
DAT7
Strobe
DAT0
SD6
SD7
Input from
eMMC to uSDHC
DAT1
...
DAT7
Figure 13. HS400 Mode timing
Table 42. HS400 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
SD2
SD3
Clock frequency
Clock low time
Clock high time
fPP
tCL
tCH
0
200
MHz
ns
0.46 x tCLK
0.46 x tCLK
0.54 x tCLK
0.54 x tCLK
ns
uSDHC Output/Card Inputs DAT (Reference to SCK)
Output skew from data of edge of SCK
Output skew from edge of SCk to data
tOSkew1
tOSkew2
0.45
0.45
—
—
ns
ns
SD4
SD5
uSDHC Input/Card Outputs DAT (Reference to Strobe)
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 43
Electrical characteristics
Table 42. HS400 interface timing specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
uSDHC input skew
uSDHC hold skew
tRQ
—
0.45
ns
SD6
SD7
tRQH
—
0.45
ns
3.9.2.4
HS200 Mode timing
Figure 14 depicts the timing of HS200 mode, and Table 43 lists the HS200 timing characteristics.
SD1
SD2
SD3
SCK
SD4/SD5
8-bit output from uSDHC to eMMC
8-bit input from eMMC to uSDHC
SD8
Figure 14. HS200 mode timing
iti
Table 43. HS200 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1 Clock Frequency Period
SD2 Clock Low Time
tCLK
tCL
5
—
ns
ns
ns
0.3 x tCLK 0.7 x tCLK
0.3 x tCLK 0.7 x tCLK
SD3 Clock High Time
tCH
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
SD5 uSDHC Output Delay
tOD
-1.6
1
ns
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1
SD8 uSDHC Output Data Window
tODW
0.5 x tCLK
—
1
HS200 is for 8 bits while SDR104 is for 4 bits.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
44 NXP Semiconductors
Electrical characteristics
3.9.2.5
SDR50/SDR104 AC timing
Figure 15 depicts the timing of SDR50/SDR104, and Table 44 lists the SDR50/SDR104 timing
characteristics.
SD1
SD2
SD3
SCK
SD4/SD5
8-bit output from uSDHC to eMMC
8-bit input from eMMC to uSDHC
SD6
SD7
SD8
Figure 15. SDR50/SDR104 timing
Table 44. SDR50/SDR104 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1 Clock Frequency Period
SD2 Clock Low Time
tCLK
tCL
5
—
ns
ns
ns
0.46 x tCLK 0.54 x tCLK
0.46 x tCLK 0.54 x tCLK
SD3 Clock High Time
tCH
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD4 uSDHC Output Delay tOD -3
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)
SD5 uSDHC Output Delay tOD -1.6
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in DDR50 (Reference to CLK)
1
1
ns
ns
SD6 uSDHC Input Setup Time
SD7 uSDHC Input Hold Time
tISU
tIH
2.4
1.4
—
—
ns
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1
SD8 uSDHC Output Data Window
tODW
0.5 x tCLK
—
ns
1
Data window in SDR100 mode is variable.
3.9.2.6
Bus operation condition for 3.3 V and 1.8 V signaling
Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50
mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2 and NVCC_SD3 supplies are
identical to those shown in Table 26, "GPIO DC parameters," on page 30.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors
45
Electrical characteristics
3.9.3
Ethernet controller (ENET) AC electrical specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive
at timing specs/constraints for the physical interface.
3.9.3.1
RMII mode timing
Figure 16 shows RMII mode timings. Table 45 describes the timing parameters (M16–M21) shown in the
figure.
M16
M17
ENET_CLK (input)
M18
ENET_TX_DATA (output)
ENET_TX_EN
M19
ENET_RX_EN (input)
ENET_RX_DATA[1:0]
ENET_RX_ER
M20
M21
Figure 16. RMII mode signal timing diagram
Table 45. RMII signal timing
ID
M16
Characteristic
Min.
Max.
Unit
ENET_CLK pulse width high
ENET_CLK pulse width low
35%
35%
4
65%
65%
—
ENET_CLK period
M17
M18
M19
M20
ENET_CLK period
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid
ns
ns
ns
—
15
ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to
ENET_CLK setup
4
—
M21
ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER hold
2
—
ns
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
46 NXP Semiconductors
Electrical characteristics
Comment
Table 46. RMII signal mapping
Pad name
Description
Mode
Alt Mode
Direction
ENET_MDC
ENET_MDIO
ENET_TD3
ENET_TD2
enet1.MDC
enet1.MDIO
RGMII.TD3
RMII/RGMII
RMII/RGMII
RGMII
ALT0
ALT0
ALT0
ALT0
O
I/O
O
—
—
Only used for RGMII
RMII.CLK;
RGMII.TD2
RMII/RGMII
I/O
Used as RMII clock and RGMII data, there
are two RGMII clock schemes.
• MAC generate output 50M reference
clock for PHY, and MAC also uses this
50M clock.
• MAC uses external 50M clock.
ENET_TD1
ENET_TD0
RMII and
RGMII.TD1
RMII/RGMII
RMII/RGMII
RMII/RGMII
RGMII
ALT0
ALT0
O
O
O
O
—
—
—
RMII and
RGMII.TD0
ENET_TX_CTL
ENET_TXC
RMII.TX_EN;
RGMII.TX_CTL
ALT0
RMII.TX_ERR;
RGMII.TX_CLK
ALT0/ALT1
For RMII, ENET_TXC works as
RMII.TX_ERR, need to work in the ALT1
mode.
For RGMII, ENET_TXC works as
RGMII_TX_CLK, need to work in the ALT0
mode.
ENET_RX_CTL
ENET_RXC
RMII.RX_EN
(CRS_DV);
RGMII.RX_CTL
RMII/RGMII
RGMII
ALT0
I
I
—
RMII.RX_ERR;
RGMII.RX_CLK
ALT0/ALT1
For RMII, ENET_RXC works as
RMII.RX_ERR, need to work in the ALT1
mode.
For RGMII, ENET_RXC works as
RGMII_RX_CLK, need to work in the ALT0
mode.
ENET_RD0
ENET_RD1
RMII and
RGMII.RD0
RMII/RGMII
RMII/RGMII
ALT0
ALT0
I
I
—
RMII and
—
RGMII.RD1
ENET_RD2
ENET_RD3
GPIO1_IO06
GPIO1_IO07
RGMII RD2
RGMII RD3
enet1.MDC
enet1.MDIO
RGMII
RGMII
ALT0
ALT0
ALT1
ALT1
I
I
—
—
—
—
RMII/RGMII
RMII/RGMII
O
I/O
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 47
Electrical characteristics
Table 46. RMII signal mapping (continued)
Pad name
Description
Mode
Alt Mode
Direction
Comment
I2C1_SCL
I2C1_SDA
enet1.MDC
enet1.MDIO
RMII/RGMII
RMII/RGMII
ALT1
ALT1
ALT1
O
I/O
I
—
—
GPIO1_IO08
enet1.1588_EVE RMII/RGMII
NT0_IN
Capture/compare block input/output event
bus signal. When configured for capture and
a rising edge is detected, the current timer
value is latched and transferred into the
corresponding ENET_TCCRn register for
inspection by software. When configured for
comparison, the corresponding signal
1588_EVENT is asserted for one cycle
when the timer reaches the comparsion
value programmed in the register
ENET_TCCRn. An interrupt or DMA request
can be triggered if the corresponding bit in
the ENET_TCSRn[TIE] or
ENET_TCSRn[TDRE] is set.
GPIO1_IO00
ENET_PHY_REF
_CLK_ROOT
RGMII
ALT1
O
Reference clock is for PHY.
3.9.3.2
RGMII signal switching specifications
The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver
devices.
1
Table 47. RGMII signal switching specifications
Symbol
Description
Min.
Max.
Unit
2
Tcyc
Clock cycle duration
7.2
-500
1
8.8
500
2.6
85
ns
ps
ns
%
3
TskewT
Data to clock output skew at transmitter
Data to clock input skew at receiver
Duty cycle for Gigabit
3
TskewR
Duty_G4
Duty_T4
Tr/Tf
45
Duty cycle for 10/100T
40
90
%
Rise/fall time (20–80%)
—
0.98
ns
1
The timings assume the following configuration:
DDR_SEL = (11)b
DSE (drive-strength) = (111)b
2
3
For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns 40 ns and 40 ns 4 ns respectively.
For all versions of RGMII prior to 2.0; this implies that PC board design will require clocks to be routed such that an additional
trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value
is unspecified.
4
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long
as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned
between.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
48 NXP Semiconductors
Electrical characteristics
2'-))?48# ꢀAT TRANSMITTERꢁ
2'-))?48$N ꢀN ꢂ ꢃ TO ꢄ ꢁ
4SKEW4
2'-))?48?#4,
48%.
48%22
4SKEW2
2'-))?48# ꢀAT RECEIVERꢁ
Figure 17. RGMII transmit signal timing diagram original
2'-))?28# ꢀAT TRANSMITTERꢁ
4SKEW4
2'-))?28$N ꢀN ꢂ ꢃ TO ꢄ ꢁ
2'-))?28?#4,
28$6
28%22
4SKEW2
2'-))?28# ꢀAT RECEIVERꢁ
Figure 18. RGMII receive signal timing diagram original
)NTERNAL DELAY
2'-))?28# ꢀSOURCE OF DATAꢁ
4SETUP 4
4 HOLD 4
2'-))?28$N ꢀN ꢂ ꢃ TO ꢄ ꢁ
28$6
28%22
2'-))?28?#4,
4 SETUP 2
4 HOLD 2
2'-))?28# ꢀAT RECEIVERꢁ
Figure 19. RGMII receive signal timing diagram with internal delay
3.9.4
General-purpose media interface (GPMI) timing
The GMPI controller of the i.MX 8M Dual / 8M QuadLite / 8M Quad processor is a flexible interface
NAND Flash controller with 8-bit data width, up to 200 MB/s I/O speed and individual chip select.
It supports Asynchronous Timing mode, Source Synchronous Timing mode and Toggle Timing mode
separately, as described in the following subsections.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors
49
Electrical characteristics
3.9.4.1
Asynchronous mode AC timing (ONFI 1.0 compatible)
Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The
maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 20 through Figure 23
depicts the relative timing between GPMI signals at the module level for different operations under
Asynchronous mode. Table 48 describes the timing parameters (NF1–NF17) that are shown in the figures.
NF2
NF1
.!.$?#,%
NF3
NF4
.!.$?#%ꢃ?"
.!.$?7%?"
NF5
.!.$?!,%
NF6
NF8
Command
NF7
NF9
.!.$?$!4!XX
Figure 20. Command Latch cycle timing diagram
NF1
.!.$?#,%
NF3
.!.$?#%ꢃ?"
.!.$?7%?"
NF10
NF5
NF11
NF7
.!.$?!,%
NF6
NF8
Address
NF9
NAND_DATAxx
Figure 21. Address Latch cycle timing diagram
NF1
.!.$?#,%
.!.$?#%ꢃ?"
.!.$?7%?"
NF3
NF10
NF5
NF11
NF7
NF6
NF8
Data to NF
.!.$?!,%
NF9
.!.$?$!4!XX
Figure 22. Write Data Latch cycle timing diagram
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
50
NXP Semiconductors
Electrical characteristics
.!.$?#,%
.!.$?#%ꢃ?"
.!.$?2%?"
NF14
NF13
NF15
.!.$?2%!$9?"
NF12
NF16
NF17
Data from NF
.!.$?$!4!XX
Figure 23. Read Data Latch cycle timing diagram (Non-EDO Mode)
.!.$?#,%
.!.$?#%ꢃ?"
NF14
NF13
NF15
.!.$?2%?"
.!.$?2%!$9?"
NF12
NF17
NF16
NAND_DATAxx
Data from NF
Figure 24. Read Data Latch cycle timing diagram (EDO mode)
1
Table 48. Asynchronous mode timing parameters
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
(AS + DS) T - 0.12 [see notes2,3
DH T - 0.72 [see note2]
Max.
NF1
NF2
NF3
NF4
NF5
NF6
NF7
NF8
NF9
NAND_CLE setup time
NAND_CLE hold time
NAND_CE0_B setup time
NAND_CE0_B hold time
NAND_WE_B pulse width
NAND_ALE setup time
NAND_ALE hold time
Data setup time
tCLS
tCLH
tCS
]
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(AS + DS + 1) T [see notes3,2
(DH+1) T - 1 [see note2]
DS T [see note2]
]
tCH
tWP
tALS
tALH
tDS
(AS + DS) T - 0.49 [see notes3,2
DH T - 0.42 [see note2]
DS T - 0.26 [see note2]
DH T - 1.37 [see note2]
(DS + DH) T [see note2]
DH T [see note2]
]
Data hold time
tDH
NF10 Write cycle time
tWC
tWH
tRR4
tRP
NF11 NAND_WE_B hold time
NF12 Ready to NAND_RE_B low
NF13 NAND_RE_B pulse width
NF14 READ cycle time
(AS + 2) T [see 3,2
]
—
DS T [see note2]
(DS + DH) T [see note2]
DH T [see note2]
tRC
NF15 NAND_RE_B high hold time
tREH
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 51
Electrical characteristics
1
Table 48. Asynchronous mode timing parameters (continued)
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
Max.
NF16 Data setup on read
NF17 Data hold on read
tDSR
tDHR
—
(DS T -0.67)/18.38 [see
ns
ns
notes5,6
—
]
0.82/11.83 [see notes5,6
]
1
GPMI’s Asynchronous mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
2
3
4
5
6
AS minimum value can be 0, while DS/DH minimum value is 1.
T = GPMI clock period -0.075 ns (half of maximum p-p jitter).
NF12 is guaranteed by the design.
Non-EDO mode.
EDO mode, GPMI clock 100 MHz
(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).
In EDO mode (Figure 23), NF16/NF17 are different from the definition in non-EDO mode (Figure 22).
They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical values for them
are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI samples
NAND_DATAxx at the rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay
value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 8M Dual /
8M QuadLite / 8M Quad Applications Processor Reference Manual [IMX8MDQLQRM]). The typical
value of this control register is 0x8 at 50 MT/s EDO mode. But if the board delay is big enough and cannot
be ignored, the delay value should be made larger to compensate the board delay.
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52
NXP Semiconductors
Electrical characteristics
3.9.4.2
Source synchronous mode AC timing (ONFI 2.x compatible)
Figure 25 to Figure 27 show the write and read timing of Source Synchronous mode.
NF19
NF18
.!.$?#%?"
NF23
NAND_CLE
NF26
NF25
NF24
NAND_ALE
NF25 NF26
NAND_WE/RE_B
NF22
NAND_CLK
NAND_DQS
NAND_DQS
Output enable
NF20
NF20
NF21
NF21
CMD
ADD
NAND_DATA[7:0]
NAND_DATA[7:0]
Output enable
Figure 25. Source Synchronous mode command and address timing diagram
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 53
Electrical characteristics
NF19
NF18
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.!.$?#,%
NF23
NF23
NF24
NF24
NF25
NF25
NF26
NF26
.!.$?!,%
NAND_WE/RE_B
NF22
.!.$?#,+
.!.$?$13
NF27
NF27
.!.$?$13
Output enable
NF29
NF29
.!.$?$1;ꢅꢆꢃ=
NF28
NF28
.!.$?$1;ꢅꢆꢃ=
Output enable
Figure 26. Source Synchronous mode data write timing diagram
NF18
NF19
.!.$?#%?"
.!.$?#,%
NF24
NF24
NF23
NF23
NF26
NF26
NF25
NF25
NAND_ALE
NF25
.!.$?7%ꢇ2%
NF25
NF22
NF26
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.!.$?$13
.!.$?$13
/UTPUT ENABLE
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/UTPUT ENABLE
Figure 27. Source Synchronous mode data read timing diagram
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
54 NXP Semiconductors
Electrical characteristics
.!.$?$13
NF30
.!.$?$!4!;ꢅꢆꢃ=
D0
D1
D2
D3
NF30
NF31
NF31
Figure 28. NAND_DQS/NAND_DQ read valid window
1
Table 49. Source Synchronous mode timing parameters
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
Max.
NF18 NAND_CE0_B access time
NF19 NAND_CE0_B hold time
tCE
tCH
CE_DELAY T - 0.79 [see note2]
0.5 tCK - 0.63 [see note2]
0.5 tCK - 0.05
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
NF20 Command/address NAND_DATAxx setup time
NF21 Command/address NAND_DATAxx hold time
NF22 clock period
tCAS
tCAH
tCK
0.5 tCK - 1.23
—
NF23 preamble delay
tPRE
tPOST
tCALS
tCALH
tDQSS
—
PRE_DELAY T - 0.29 [see note2]
POST_DELAY T - 0.78 [see note2]
0.5 tCK - 0.86
NF24 postamble delay
NF25 NAND_CLE and NAND_ALE setup time
NF26 NAND_CLE and NAND_ALE hold time
NF27 NAND_CLK to first NAND_DQS latching transition
NF28 Data write setup
0.5 tCK - 0.37
T - 0.41 [see note2]
0.25 tCK - 0.35
NF29 Data write hold
—
0.25 tCK - 0.85
NF30 NAND_DQS/NAND_DQ read setup skew
NF31 NAND_DQS/NAND_DQ read hold skew
—
—
—
2.06
1.95
—
1
GPMI’s Source Synchronous mode output timing can be controlled by the module’s internal registers
GPMI_TIMING2_CE_DELAY,GPMI_TIMING_PREAMBLE_DELAY,GPMI_TIMING2_POST_DELAY.ThisACtimingdepends
on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.
2
T = tCK(GPMI clock period) –0.075 ns (half of maximum p-p jitter).
For DDR Source Synchronous mode, Figure 28 shows the timing diagram of
NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 0.85 ns (max) and 1 ns
(max) for tQHS at 200 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of an
delayed NAND_DQS signal, which can be provided by an internal DPLL. The delay value can be
controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI
chapter of the i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processor Reference Manual
[IMX8MDQLQRM]). Generally, the typical delay value of this register is equal to 0x7 which means 1/4
clock cycle delay expected. But if the board delay is big enough and cannot be ignored, the delay value
should be made larger to compensate the board delay.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors
55
Electrical characteristics
3.9.4.3
ONFI NV-DDR2 mode (ONFI 3.2 compatible)
Command and address timing
3.9.4.3.1
ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing.
See Section 3.9.4.1, Asynchronous mode AC timing (ONFI 1.0 compatible),” for details.
3.9.4.3.2
Read and write timing
ONFI 3.2 mode read and write timing is the same as Toggle mode AC timing. See Section 3.9.4.4, Toggle
mode AC Timing,” for details.
3.9.4.4
Toggle mode AC Timing
3.9.4.4.1
Command and address timing
NOTE
Toggle mode command and address timing is the same as ONFI 1.0
compatible Asynchronous mode AC timing. See Section 3.9.4.1,
Asynchronous mode AC timing (ONFI 1.0 compatible),” for details.
3.9.4.4.2
Read and write timing
Figure 29. Toggle mode data write timing
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56 NXP Semiconductors
Electrical characteristics
DEV?CLK
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ꢈ T #+
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Figure 30. Toggle mode data read timing
1
Table 50. Toggle mode timing parameters
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
Max.
NF1 NAND_CLE setup time
NF2 NAND_CLE hold time
NF3 NAND_CE0_B setup time
NF4 NAND_CE0_B hold time
NF5 NAND_WE_B pulse width
NF6 NAND_ALE setup time
NF7 NAND_ALE hold time
tCLS
tCLH
tCS
(AS + DS) T - 0.12 [see note2s,3]
DH T - 0.72 [see note2]
(AS + DS) T - 0.58 [see notes,2]
DH T - 1 [see note2]
tCH
tWP
tALS
tALH
DS T [see note2]
(AS + DS) T - 0.49 [see notes,2]
DH T - 0.42 [see note2]
DS T - 0.26 [see note2]
DH T - 1.37 [see note2]
NF8 Command/address NAND_DATAxx setup time tCAS
NF9 Command/address NAND_DATAxx hold time
NF18 NAND_CEx_B access time
NF22 clock period
tCAH
tCE
CE_DELAY T [see notes4,2
]
—
ns
ns
ns
tCK
—
—
—
NF23 preamble delay
tPRE PRE_DELAY T [see notes5,2
]
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 57
Electrical characteristics
1
Table 50. Toggle mode timing parameters (continued)
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
Max.
NF24 postamble delay
tPOST POST_DELAY T +0.43 [see
—
ns
note2]
NF28 Data write setup
NF29 Data write hold
tDS6
tDH6
tDQSQ7
tQHS7
0.25 tCK - 0.32
—
—
ns
ns
ns
ns
0.25 tCK - 0.79
NF30 NAND_DQS/NAND_DQ read setup skew
NF31 NAND_DQS/NAND_DQ read hold skew
—
—
3.18
3.27
1
The GPMI toggle mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these register’s settings. In the table, AS/DS/DH represents each of these settings.
2
3
4
AS minimum value can be 0, while DS/DH minimum value is 1.
T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter).
CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started
with enough time of ALE/CLE assertion to low level.
5
6
7
PRE_DELAY+1 (AS+DS)
Shown in Figure 29.
Shown in Figure 30.
For DDR Toggle mode, Figure 28 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid
window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI
samples NAND_DATA[7:0] at both the rising and falling edges of a delayed NAND_DQS signal, which
is provided by an internal DPLL. The delay value of this register can be controlled by the GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 8M Dual / 8M
QuadLite / 8M Quad Applications Processor Reference Manual [IMX8MDQLQRM]). Generally, the
typical delay value is equal to 0x7, which means a 1/4 clock cycle delay is expected. But if the board delay
is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay.
3.9.5
HDMI 2.0 Tx module timing parameters
See the following specifications:
•
•
HDMI 2.0a specification (HDMI.org)
DisplayPort 1.3 standard (VESA.org)
— DP supports 1.6 GHz (RBR), 2.7 GHz (HBR), and 5.4 GHz (HBR2) rates. Those rates are
managed in API (Host).
— RBR supports 1080p60 (RGB 8b), HBR supports 4kp30 (RGB 8b) and HBR2 supports 4kp60
(RGB 8b).
See bandwidth details below.
Effective bandwidth per rate with 4 lanes:
— RBR: 1.62 x 4 x 8 / 10 = 5.184 Gbps
— HBR: 2.7 x 4 x 8 / 10 = 8.64 Gbps
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58 NXP Semiconductors
Electrical characteristics
— HBR2: 1.62 x4 x 8 / 10 = 17.28 Gbps
Bandwidth required per resolution (CEA-861-F):
— 1920 x 1080 (24 b/px) 60 fps: 3.56 Gbps
— 3840 x 2160 (24 b/px) 30 fps: 7.13 Gbps
— 3840 x 2160 (24 b/px) 30 fps: 14.26 Gbps
Embedded DisplayPort 1.4 standard (VESA.org)
•
— eDP link rates: R216 (2.16 Gbps), R243 (2.43 Gbps), R324 (3.24 Gbps), and R432 (4.32 Gbps)
— Fast Link Training is also supported
DDC link requires external pull-up resistors to be connected to a 5 V supply. The following table provides
the range for those pull-ups.
Table 51. Pull-up resistors for DDC link
Ball Name
Min
Typ
Max
Unit
HDMI_TX0_DDC_SCL
HDMI_TX0_DDC_SDA
1.5
1.5
—
—
2
2
K
K
3.9.6
I2C bus characteristics
The Inter-Integrated Circuit (I2C) provides functionality of a standard I2C master and slave. The I2C is
designed to be compatible with the I2C Bus Specification, version 2.1, by Philips Semiconductor (now
NXP Semiconductors).
3.9.7
MIPI D-PHY timing parameters
This section describes MIPI D-PHY electrical specifications.
3.9.7.1 MIPI HS-TX specifications
Table 52. MIPI high-speed transmitter DC specifications
Symbol
Parameter
Min
Typ
Max
Unit
1
VCMTX
High Speed Transmit Static Common Mode Voltage
VCMTX mismatch when Output is Differential-1 or Differential-0
High Speed Transmit Differential Voltage
150
—
200
—
250
3
mV
mV
mV
mV
mV
|VCMTX (1,0)
|
1
|VOD
|
140
—
200
—
270
12
|VOD
|
VOD mismatch when Output is Differential-1 or Differential-0
High Speed Output High Voltage
1
VOHHS
ZOS
—
—
360
62.5
Single Ended Output Impedance
40
50
ZOS
Single Ended Output Impedance Mismatch
—
—
10
%
1
Value when driving into load impedance anywhere in the ZID range.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 59
Electrical characteristics
Symbol
Table 53. MIPI high-speed transmitter AC specifications
Parameter
Min
Typ
Max
Unit
VCMTX(HF)
VCMTX(LF)
Common-level variations above 450 MHz
Common-level variation between 50-450 MHz
Rise Time and Fall Time (20% to 80%)
—
—
—
—
—
8
mVRMS
mVPEAK
ps
10
1
tR and tF
160
0.3 UI
1
UI is the long-term average unit interval.
3.9.7.2
MIPI LP-TX specifications
Table 54. MIPI low-power transmitter DC specifications
Symbol
Parameter
Thevenin Output High Level
Min
Typ
Max
Unit
1
VOH
1.1
-50
110
1.2
—
1.3
50
—
V
mV
VOL
Thevenin Output Low Level
2
ZOLP
Output Impedance of Low Power Transmitter
—
1
2
This specification can only be met when limiting the core supply variation from 1.1 V to 1.3 V.
Although there is no specified maximum for ZOLP, the LP transmitter output impedance ensures the TRLP/TFLP specification
is met.
Table 55. MIPI low-power transmitter AC specifications
Symbol
Parameter
Min
Typ
Max
Unit
1
TRLP /TFLP
15% to 85% Rise Time and Fall Time
30% to 85% Rise Time and Fall Time
—
—
40
—
—
—
25
35
—
ns
ns
ns
1,2,3
TREOT
TLP-PULSE-TX
4
Pulse width of the LP exclusive-OR clock: First LP exclusive-OR
clock pulse after Stop state or last pulse before Stop state
Pulse width of the LP exclusive-OR clock: All other pulses
Period of the LP exclusive-OR clock
Slew Rate @ CLOAD = 0 pF
20
90
30
30
30
30
0
—
—
—
—
—
—
—
—
—
ns
TLP-PER-TX
ns
1,5,6,7
V/tSR
500
200
150
100
70
mV/ns
mV/ns
mV/ns
mV/ns
pF
Slew Rate @ CLOAD = 5 pF
Slew Rate @ CLOAD = 20 pF
Slew Rate @ CLOAD = 70 pF
CLOAD
Load Capacitance
1
2
CLOAD includes the low equivalent transmission line capacitance of TX and RX are assumed to always be < 10 pF. The
distributed line capacitance can be up to 50 pF for a transmission line with 2 ns delay.
The rise-time of TREOT starts from the HS common-level at the moment when the differential amplitude drops below 70 mV,
due to stopping of the differential drive.
3
4
With an additional load capacitance CCM between 0 to 60 pF on the termination center, tap at RX side of the lane.
This parameter value can be lower than TLPX, due to differences in rise vs. fall signal slopes, trip levels, and mismatches
between Dp and Dn LP transmitters. Any LP exclusive-OR pulse observed during HS EoT (transition from HS level to LP-11)
is glitch behavior as described in Low-Power Receiver section.
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60 NXP Semiconductors
Electrical characteristics
5
6
7
When the output voltage is between 15% and 85% of the fully settled LP signal levels.
Measured as average across any 50 mV segment of the output signal transition.
This value represents a corner point in a piecewise linear curve.
3.9.7.3
MIPI LP-RX specifications
Table 56. MIPI low power receiver DC specifications
Symbol
Parameter
Min
Typ
Max
Unit
VIH
VIL
Logic 1 input voltage
880
—
—
—
—
—
1.3
550
300
—
mV
mV
mV
mV
Logic 0 input voltage, not in ULP state
Logic 0 input voltage, ULP state
Input hysteresis
VIL-ULPS
VHYST
—
25
Table 57. MIPI low power receiver AC specifications
Symbol
Parameter
Min
Typ
Max
Unit
1,2
eSPIKE
Input pulse rejection
—
20
—
0
300
0
V.ps
ns
3
TMIN-RX
Minimum pulse width response
Peak Interference amplitude
Interference frequency
VINT
fINT
—
—
—
200
—
mV
450
MHz
1
2
3
Time-voltage integration of a spike above VIL when in LP-0 state or below VIH when in LP-1 state.
An impulse below this value will not change the receiver state.
An input pulse greater than this value shall toggle the output.
3.9.7.4
MIPI LP-CD specifications
Table 58. MIPI contention detector DC specifications
Symbol
Parameter
Min
Typ
Max
Unit
VIHCD
VILCD
Logic 1 contention threshold
Logic 0 contention threshold
450
—
—
—
—
mV
mV
200
3.9.7.5
MIPI DC specifications
Table 59. MIPI input characteristics DC specifications
Symbol
Parameter
Min
Typ
Max
Unit
VPIN
Pad signal voltage range
Pin leakage current
Ground shift
-50
-30
-50
—
—
—
1350
30
mV
A
mV
1
ILEAK
VGNDSH
50
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NXP Semiconductors 61
Electrical characteristics
Table 59. MIPI input characteristics DC specifications (continued)
2
VPIN(absmax)
Maximum pin voltage level
-0.15
—
—
—
1.45
20
V
3
TVPIN(absmax)
Maximum transient time above VPIN(max) or below VPIN(min)
ns
1
When the pad voltage is within the signal voltage range between VGNDSH(min) to VOH + VGNDSH(max) and the Lane Module is
in LP receive mode.
2
3
This value includes ground shift.
The voltage overshoot and undershoot beyond the VPIN is only allowed during a single 20 ns window after any LP-0 to LP-1
transition or vice versa. For all other situations it must stay within the VPIN range.
3.9.8
PCIe PHY parameters
The PCIe interface is designed to be compatible with PCIe specification Gen2 x1 lane and supports the
PCI Express 1.1/2.0 standard.
3.9.8.1
PCIEx_RESREF reference resistor connection
The impedance calibration process requires connection of reference resistor 200 1% precision resistor
on PCIEx_RESREF pads to ground. It is used for termination impedance calibration.
3.9.9
Pulse width modulator (PWM) timing parameters
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
Figure 31 depicts the timing of the PWM, and Table 60 lists the PWM timing parameters.
0ꢈ
0ꢊ
07-N?/54
Figure 31. PWM timing
Table 60. PWM output timing parameters
ID
Parameter
Min
Max
Unit
PWM Module Clock Frequency
PWM output pulse width high
PWM output pulse width low
0
ipg_clk (66 MHz)
MHz
ns
P1
P2
15
15
—
—
ns
3.9.10 Quad SPI (QSPI) timing parameters
This section describes the electrical information for QSPI.
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62 NXP Semiconductors
Electrical characteristics
Measurement is with a load of 35 pF on SCK and SIO pins and an input slew rate of 1 V/ns.
3.9.10.1 SDR Mode
QSPIx_SCLK
TIS
TIH
TIS
TIH
QSPIx_DATA[0:3]
Figure 32. QuadSPI input/read timing (SDR mode with internal sampling)
Table 61. QuadSPI input timing (SDR mode with internal sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
TIH
Setup time for incoming data
8.67
0
—
—
ns
ns
Hold time requirement for incoming data
1
2
3
4
QSPIx_SCLK
QSPIx_DATA[0:3]
QSPIx_DQS
TIS
TIH
TIS
TIH
Figure 33. QuadSPI input/read timing (SDR mode with loopback DQS sampling)
Table 62. QuadSPI input/read timing (SDR mode with loopback DQS sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
TIH
Setup time for incoming data
2
1
—
—
ns
ns
Hold time requirement for incoming data
NOTE
•
For internal sampling, the timing values assume using sample point 0,
that is QuadSPIx_SMPR[SDRSMP] = 0.
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NXP Semiconductors 63
Electrical characteristics
•
For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
QSPIx_SCLK
QSPIx_CS
TCSH
TCSS
TCK
TDVO
TDVO
QSPIx_SIO
TDHO
TDHO
Figure 34. QuadSPI output/write timing (SDR mode)
Table 63. QuadSPI output/write timing (SDR mode)
Value
Symbol
Parameter
Unit
Min
Max
TDVO
TDHO
TCK
TCSS
TCSH
Output data valid time
—
-0.5
10
3
2
ns
ns
ns
ns
ns
Output data hold time
—
—
—
—
SCK clock period
Chip select output setup time
Chip select output hold time
3
NOTE
and T are configured by the QuadSPIx_FLSHCR register; the default
T
css
csh
value of 3 is shown on the timing. See the i.MX 8M Dual / 8M QuadLite /
8M Quad Applications Processor Reference Manual (IMX8MDQLQRM)
for more details.
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Electrical characteristics
3.9.10.2 DDR mode
QSPIx_SCLK
TIS
TIH
TIS
TIH
QSPIx_DATA[0:3]
Figure 35. QuadSPI input/read timing (DDR mode with internal sampling)
Table 64. QuadSPI input/read timing (DDR mode with internal sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
TIH
Setup time for incoming data
8.67
0
—
—
ns
ns
Hold time requirement for incoming data
1
2
3
4
QSPIx_SCLK
QSPIx_DATA[0:3]
QSPIx_DQS
TIS
TIH
TIS
TIH
Figure 36. QuadSPI input/read timing (DDR mode with loopback DQS sampling)
Table 65. QuadSPI input/read timing (DDR mode with loopback DQS sampling)
Value
Symbol
Parameter
Unit
Min
Max
TIS
TIH
Setup time for incoming data
2
1
—
—
ns
ns
Hold time requirement for incoming data
NOTE
•
For internal sampling, the timing values assume using sample point 0,
that is QuadSPIx_SMPR[SDRSMP] = 0.
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NXP Semiconductors 65
Electrical characteristics
•
For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
1
2
QSPIx_SCLK
QSPIx_CS
TCSS
TCK
TCSH
TDVO
TDVO
QSPIx_SIO
TDHO
TDHO
Figure 37. QuadSPI output/write timing (DDR mode)
Table 66. QuadSPI output/write timing (DDR mode)
Value
Symbol
Parameter
Unit
Min
Max
(0.25 x TSCLK) + 2 ns
TDVO
TDHO
TCK
TCSS
TCSH
Output data valid time
Output data hold time
SCK clock period
—
(0.25 x TSCLK) - 0.5
—
—
—
—
ns
ns
20
3
Chip select output setup time
Chip select output hold time
SCK cycle(s)
ns
3
NOTE
and T are configured by the QuadSPIx_FLSHCR register; the default value of 3 is shown on the
T
css
csh
timing. See the i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processor Reference Manual
(IMX8MDQLQRM) for more details.
3.9.11 SAI/I2S switching specifications
This section provides theAC timings for the SAI in Master (clocks driven) and Slave (clocks input) modes.
All timings are given for non inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 67. Master mode SAI timing
Num
Characteristic
SAI_MCLK cycle time
Min
Max
Unit
S1
S2
S3
20
—
ns
SAI_MCLK pulse width high/low
SAI_BCLK cycle time
40%
40
60%
—
MCLK period
ns
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Electrical characteristics
Table 67. Master mode SAI timing (continued)
Characteristic Min
SAI_BCLK pulse width high/low
Num
Max
Unit
S4
S5
S6
S7
S8
S9
S10
40%
—
0
60%
15
—
BCLK period
SAI_BCLK to SAI_FS output valid
SAI_BCLK to SAI_FS output invalid
SAI_BCLK to SAI_TXD valid
ns
ns
ns
ns
ns
ns
—
0
15
—
SAI_BCLK to SAI_TXD invalid
SAI_RXD/SAI_FS input setup before SAI_BCLK
SAI_RXD/SAI_FS input hold after SAI_BCLK
15
0
—
—
Figure 38. SAI timing—Master modes
Table 68. Slave mode SAI timing
Num
Characteristic
SAI_BCLK cycle time (input)
Min
Max
Unit
S11
S12
S13
S14
S15
S16
S17
S18
40
40%
10
2
—
ns
SAI_BCLK pulse width high/low (input)
SAI_FS input setup before SAI_BCLK
SAI_FA input hold after SAI_BCLK
60%
—
BCLK period
ns
ns
ns
ns
ns
ns
—
SAI_BCLK to SAI_TXD/SAI_FS output valid
SAI_BCLK to SAI_TXD/SAI_FS output invalid
SAI_RXD setup before SAI_BCLK
—
0
20
—
10
2
—
SAI_RXD hold after SAI_BCLK
—
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NXP Semiconductors 67
Electrical characteristics
Figure 39. SAI Timing — Slave Modes
3.9.12 SPDIF timing parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 69 and Figure 40 and Figure 41 show SPDIF timing parameters for the Sony/Philips Digital
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Table 69. SPDIF timing parameters
Timing Parameter Range
Parameter
Symbol
Unit
Min
Max
SPDIF_IN Skew: asynchronous inputs, no specs apply
—
—
0.7
ns
ns
SPDIF_OUT output (Load = 50 pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
24.2
31.3
SPDIF_OUT output (Load = 30 pf)
• Skew
• Transition rising
• Transition falling
1.5
13.6
18.0
—
—
—
—
—
—
ns
Modulating Rx clock (SPDIF_SR_CLK) period
SPDIF_SR_CLK high period
srckp
srckph
srckpl
stclkp
stclkph
stclkpl
40.0
16.0
16.0
40.0
16.0
16.0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
SPDIF_SR_CLK low period
Modulating Tx clock (SPDIF_ST_CLK) period
SPDIF_ST_CLK high period
SPDIF_ST_CLK low period
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Electrical characteristics
srckp
srckpl
VM
srckph
VM
SPDIF_SR_CLK
(Output)
Figure 40. SPDIF_SR_CLK timing diagram
stclkp
stclkpl
VM
stclkph
VM
SPDIF_ST_CLK
(Input)
Figure 41. SPDIF_ST_CLK timing diagram
3.9.13 UART I/O configuration and timing parameters
3.9.13.1 UART RS-232 I/O configuration in different modes
The UART interfaces of the i.MX 8M Dual / 8M QuadLite / 8M Quad processors can serve both as DTE
or DCE device. This can be configured by the DCEDTE control bit (default 0—DCE mode). Table 70
shows the UART I/O configuration based on the enabled mode.
Table 70. UART I/O configuration vs. mode
DTE Mode
Description
DCE Mode
Description
Port
Direction
Direction
UARTx_RTS_B
UARTx_CTS_B
Output
Input
UARTx_RTS_B from DTE to DCE
UARTx_CTS_B from DCE to DTE
Serial data from DCE to DTE
Serial data from DTE to DCE
Input
Output
Output
Input
UARTx_RTS_B from DTE to DCE
UARTx_CTS_B from DCE to DTE
Serial data from DCE to DTE
Serial data from DTE to DCE
UARTx_TX_DATA
UARTx_RX_DATA
Input
Output
3.9.13.2 UART RS-232 Serial mode timing
This section describes the electrical information of the UART module in the RS-232 mode.
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Electrical characteristics
3.9.13.2.1 UART transmitter
Figure 42 depicts the transmit timing of UART in the RS-232 Serial mode, with 8 data bit/1 stop bit
format. Table 71 lists the UART RS-232 Serial mode transmit timing characteristics.
Possible
UA1
UA1
Bit 3
Parity
Bit
Next
Start
Bit
Start
Bit
UARTx_TX_DATA
(output)
STOP
BIT
Bit 7
Bit 0
Bit 1
Bit 2
Bit 4
Bit 5
Bit 6
Par Bit
UA1
UA1
Figure 42. UART RS-232 Serial mode transmit timing diagram
Table 71. RS-232 Serial mode transmit timing parameters
ID
Parameter
Symbol
Min
Max
1/Fbaud_rate + Tref_clk
Unit
2
UA1 Transmit Bit Time
tTbit
1/Fbaud_rate1 - Tref_clk
—
1
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
3.9.13.2.2
UART receiver
Figure 43 depicts the RS-232 Serial mode receive timing with 8 data bit/1 stop bit format. Table 72 lists
Serial mode receive timing characteristics.
Possible
Parity
UA2
UA2
Bit 3
Bit
Next
Start
Bit
Start
Bit
UARTx_RX_DATA
(output)
STOP
BIT
Bit 7
Bit 0
Bit 1
Bit 2
Bit 4
Bit 5
Bit 6
Par Bit
UA2
UA2
Figure 43. UART RS-232 Serial mode receive timing diagram
Table 72. RS-232 Serial mode receive timing parameters
ID
Parameter
Symbol
Min
Max
Unit
UA2
Receive Bit Time1
tRbit
1/Fbaud_rate2 - 1/(16
1/Fbaud_rate
+
—
x Fbaud_rate
)
1/(16 x Fbaud_rate)
1
2
The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 x Fbaud_rate).
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
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Electrical characteristics
3.9.14 USB PHY parameters
This section describes the USB-OTG PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision
3.0 OTG, USB Host with the amendments below (On-The-Go and Embedded Host Supplement to the USB
Revision 3.0 Specification is not applicable to Host port):
•
USB ENGINEERING CHANGE NOTICE
— Title: 5V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Pull-up/Pull-down resistors
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Suspend Current Limit Changes
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
— Title: USB 2.0 Phase Locked SOFs
— Applies to: Universal Serial Bus Specification, Revision 2.0
On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
— Revision 2.0, version 1.1a, July 27, 2010
•
•
Battery Charging Specification (available from USB-IF)
— Revision 1.2, December 7, 2010
3.9.14.1 USB_OTG*_REXT reference resistor connection
The bias generation and impedance calibration process for the USB OTG PHYs requires connection of
reference resistors 200 1% precision on each of USB_OTG1_REXT and USB_OTG2_REXT pads to
ground.
3.9.14.2 USB_OTG_CHD_B USB battery charger detection external pullup
resistor connection
The usage and external resistor connection for the USB_OTG_CHD_B pin are described in Table 5, and
Section 3.7.3, USB battery charger detection driver impedance.”
3.9.15 USB 2.0 PHY parameters
USB 2.0 PHY parameters are compatible with USB 3.0 PHY. See Section 3.9.16, USB 3.0 PHY
parameters for more detailed information.
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Electrical characteristics
3.9.16 USB 3.0 PHY parameters
This section describes the electrical information about USB 3.0 PHY.
Table 73 shows the USB 3.0 PHY junction temperature.
Table 73. USB 3.0 PHY junction temperature
Min
Max
-40 C
125 C
Table 74 shows the USB 3.0 PHY power dissipation of SuperSpeed 5-Gbps operation.
Table 74. USB 3.0 PHY power dissipation: SuperSpeed 5-Gbps operation (unit: for current is mA, for power
is mW)
Current from
USB1/2_VP
Current from
USB1/2_VPTX USB1/2_VPH
Current from
Mode
Conditions
Total Current
Total Power
U0
TT/WC
25.700/35.700
0.318/2.550
15.000/21.200 14.000/20.300 54.700/77.200 82.800/130.000
0.012/0.184 0.012/0.030 0.34/2.764 0.337/2.816
Power-Down
TT/WC
Table 75 shows the USB 3.0 PHY power dissipation: HS/FS/LS operation.
Table 75. USB 3.0 PHY power dissipation: HS/FS/LS operations (unit: for current is mA, for power is mW)
Current from
USB1/2_DVDD
Current from
USB1/2_VDD33
Mode
Conditions
Total Current
Total Power
HS TX
FS TX
TT/WC
TT/WC
TT/WC
TT/WC
TT/WC
TT/WC
4.800/9.200
2.800/6.800
3.500/7.700
0.048/3.690
0.047/3.690
0.122/3.760
24.000/24.400
22.100/24.500
19.300/20.400
0.065/0.146
28.800/33.600
24.900/31.200
22.800/28.100
0.112/3.386
83.500/97.700
75.400/95.500
66.900/81.700
0.257/4.182
LS TX
Power-Down
Suspend
0.066/0.154
0.113/3.844
0.261/4.213
Battery Charging
6.350/5.780
6.472/9.540
21.065/24.704
Table 76 shows the worst-case maximum current.
Table 76. Worst-Case maximum current
USB1/2_VPH
USB1/2_VP
USB1/2_VPTX
USB1/2_VDD33
USB1/2_DVDD
Unit
20.3
35.7
21.2
24.5
9.2
mA
Table 77 shows the USB power pin supplies.
Table 77. USB power pin supplies
Description
Pin Name
Value
USB1/2_VDD
USB1/2_VP
PHY analog and digital high-speed supply
PHY analog and digital SuperSpeed supply
0.9 V (+22.2%, -7%)
0.9 V (+22.2%, -7%)
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Electrical characteristics
Value
Table 77. USB power pin supplies (continued)
Description
Pin Name
USB1/2_VPTX
PHY transmit supply
0.9 V (+22.2%, -7%)
USB1/2_VDD33
USB1/2_VPH
High supply for high-speed operation IO
High supply for SuperSpeed operation IO
3.3 V (+10%, -7%)
3.3 V (+10%, -7%)
Table 78 shows the external component values.
Table 78. External component values
Component
Pin Name
Value
External resistor (resref)
USB1_RESREF/USB2_RESREF
200 ( 1%)
Table 79 shows the minimum ESD protection target levels.
Table 79. Minimum ESD protection target levels
ESD Category
Minimum Protection Level
JEDEC Class
Human Body Model (HBM) (JS-001-2014)
Charged Device Model (CDM) (JESD22-C101F)
Machine Model (MM) (JESD22_A115C)
2 KV
6 A peak discharge current
100 V
2
C2/C1 (500 V/ 250 V)1
N/A
1
Support for either 500 V or 250 V CDM target level is dependent on maximum discharge current generated in final
SoC/package implementation.
Table 80 shows the supply impedance requirements.
Table 80. Supply impedance requirements
LVSSA<#> +
LDVDD(nH)
LVSSA<#> + LVDD33
<#>(nH)
Lgd + Lvp(nH)
Lgd + Lvptx<#>(nH)
L
gd + Lvph(nH)
< 2.4
< 2.4
< 2.4
< 2.8
< 2.8
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NXP Semiconductors 73
Boot mode configuration
4 Boot mode configuration
This section provides information on Boot mode configuration pins allocation and boot devices interfaces
allocation.
4.1
Boot mode configuration pins
Table 81 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed Boot mode options configured by the Boot mode pins, see the “System Boot,
Fusemap, and eFuse” chapter in the i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processor
Reference Manual (IMX8MDQLQRM).
Table 81. Fuses and associated pins used for boot
State during reset
(POR_B
State after reset
(POR_B
deasserted)
Direction
at Reset
Pin
eFuse name
Details
asserted)
BOOT_MODE0
BOOT_MODE1
Input
Input
N/A
N/A
Input with 95 K pull down Input with 95 K pull down Boot mode
selection
Input with 95 K pull down Input with 95 K pull down Boot mode
selection
SAI1_RXD0
SAI1_RXD1
SAI1_RXD2
SAI1_RXD3
SAI1_RXD4
SAI1_RXD5
SAI1_RXD6
SAI1_RXD7
SAI1_TXD0
SAI1_TXD1
SAI1_TXD2
SAI1_TXD3
SAI1_TXD4
SAI1_TXD5
SAI1_TXD6
SAI1_TXD7
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
BOOT_CFG[0] Input with 95 K pull down Input with 95 K pull down Boot options pin
value overrides
BOOT_CFG[1] Input with 95 K pull down Input with 95 K pull down
fuse settings for
BT_FUSE_SEL =
“0“. Signal
BOOT_CFG[2] Input with 95 K pull down Input with 95 K pull down
BOOT_CFG[3] Input with 95 K pull down Input with 95 K pull down
BOOT_CFG[4] Input with 95 K pull down Input with 95 K pull down
BOOT_CFG[5] Input with 95 K pull down Input with 95 K pull down
BOOT_CFG[6] Input with 95 K pull down Input with 95 K pull down
BOOT_CFG[7] Input with 95 K pull down Input with 95 K pull down
BOOT_CFG[8] Input with 95 K pull down Input with 95 K pull down
BOOT_CFG[9] Input with 95 K pull down Input with 95 K pull down
BOOT_CFG[10] Input with 95 K pull down Input with 95 K pull down
BOOT_CFG[11] Input with 95 K pull down Input with 95 K pull down
BOOT_CFG[12] Input with 95 K pull down Input with 95 K pull down
BOOT_CFG[13] Input with 95 K pull down Input with 95 K pull down
BOOT_CFG[14] Input with 95 K pull down Input with 95 K pull down
BOOT_CFG[15] Input with 95 K pull down Input with 95 K pull down
configuration as
fuse override input
at power up. These
are special I/O lines
that control the boot
configurationduring
product
development. In
production, theboot
configuration can
be controlled by
fuses.
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Boot mode configuration
4.2
Boot device interface allocation
Table 82 lists the interfaces that can be used by the boot process in accordance with the specific Boot
mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,
which are configured during boot when appropriate.
Table 82. Interface allocation during boot
Interface
IP Instance
Allocated Pads During Boot
Comment
NAND Flash
GPMI
NAND_ALE, NAND_CE0_B, NAND_CLE,
NAND_DATA00, NAND_DATA01, NAND_DATA02,
NAND_DATA03, NAND_DATA04, NAND_DATA05,
NAND_DATA06, NAND_DATA07, NAND_DQS,
NAND_RE_B, NAND_READY_B, NAND_WE_B,
NAND_WP_B
8-bit, only CS0 is supported.
SD/MMC
USDHC-1
GPIO1_IO03, GPIO1_IO06, GPIO1_IO07,
SD1_RESET_B, SD1_CLK, SD1_CMD,
SD1_STROBE, SD1_DATA0, SD1_DATA1,
SD1_DATA2,SD1_DATA3,SD1_DATA4,SD1_DATA5,
SD1_DATA6, SD1_DATA7
1, 4, or 8-bit
SD/MMC
USB
USDHC-2
GPIO1_IO04, GPIO1_IO08, GPIO1_IO07,
SD2_RESET_B, SD2_CD_B, SD2_WP, SD2_CLK,
SD2_CMD,SD2_DATA0,SD2_DATA1,SD2_DATA2,
SD2_DATA3
1 or 4-bit
USB_OTG PHY
—
—
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Package information and contact assignments
5 Package information and contact assignments
This section includes the contact assignment information and mechanical package drawing.
5.1
17 x 17 mm package information
5.1.1
17 x 17 mm, 0.65 mm pitch, ball matrix
Figure 44 shows the top, bottom, and side views of the 17 × 17 mm BGA package.
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NXP Semiconductors
Package information and contact assignments
Figure 44. 17 x 17 mm BGA, package top, bottom, and side Views
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NXP Semiconductors 77
Package information and contact assignments
5.1.2
17 x 17 mm supplies contact assignments and functional contact
assignments
Table 83 shows supplies contact assignments for the 17 x 17 mm package.
Table 83. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm supplies contact assignments
Supply Rail Name
EFUSE_VQPS
Ball(s) Postion(s)
Remark
R17
Supply for eFuse Programming
Supply for HDMI PHY
Supply for HDMI PHY
Supply for HDMI PHY
Supply for MIPI PHY
HDMI_AVDDCLK
HDMI_AVDDCORE
HDMI_AVDDIO
MIPI_VDD
V3
U3, U4
P2
E15, F15
MIPI_VDDA
E17, E18, F17, F18
C18, D17, D18
F19
Supply for MIPI PHY
MIPI_VDDHA
MIPI_VDDPLL
NVCC_DRAM
Supply for MIPI PHY
Supply for MIPI PHY
Y12, Y14, AA10, AA15, AB3, AB8, AB17,
AB23, AC3, AC6, AC8, AC14, AC17, AC20,
AC23, AD5, AD18, AD21
Supply for DRAM Interface
NVCC_ECSPI
NVCC_ENET
NVCC_GPIO1
NVCC_I2C
F5
Supply for ESCPI Interface
Supply for ENET Interface
Supply for GPIO1 Interface
Supply for I2C Interface
Supply for JTAG Interface
Supply for NAND Interface
Supply for SAI Interface
Supply for SAI Interface
Supply for SAI Interface
Supply for SAI Interface
Supply for SD Interface
Supply for SD Interface
Supply for SNVS Interface
Supply for UART Interface
Supply for PCIe PHY
T18
R5, R6
H7
NVCC_JTAG
NVCC_NAND
NVCC_SAI1
NVCC_SAI2
NVCC_SAI3
NVCC_SAI5
NVCC_SD1
NVCC_SD2
NVCC_SNVS
NVCC_UART
PCIE_VP
W4
L18, M18
K3, L3
J7
E3
M3
L23, M23
N23
W18
D8
F22, G22
H23, J23
F23, G23
E12
PCIE_VPH
Supply for PCIe PHY
PCIE_VPTX
USB1_DVDD
USB1_VDD33
Supply for PCIe PHY
Supply for USB PHY
G12
Supply for USB PHY
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
78 NXP Semiconductors
Package information and contact assignments
Table 83. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm supplies contact assignments (continued)
USB1_VP
D12
F12
C12
E11
G11
D11
F11
C11
Supply for USB PHY
Supply for USB PHY
Supply for USB PHY
Supply for USB PHY
Supply for USB PHY
Supply for USB PHY
Supply for USB PHY
Supply for USB PHY
USB1_VPH
USB1_VPTX
USB2_DVDD
USB2_VDD33
USB2_VP
USB2_VPH
USB2_VPTX
VDD_ARM
G14, G15, G16, H14, H15, H16, J15, J16, K15, Supply for Arm Core
K16, L15, L16, M15, M16
VDD_DRAM
U10, U11, U12, U13, U14, V9, V10, V11, V12, Supply for DRAM Module
V13, V14, V15, Y6, Y8, Y10, Y16, Y18, Y20
VDD_GPU
VDD_SNVS
VDD_SOC
J9, J10, K9, K10, L9, L10, M9, M10
R18
Supply for GPU
Supply for SNVS Logic
K12, L12, L13, M12, M13, N13, P12, P13, P15, Supply for SOC Logic
P16, R8, R9, R10, R11, R12, R13, R14, R15,
R16, T8, T17
VDD_VPU
N8, N9, N10, P9, P10
Supply for VPU
VDDA_0P9
V18
U17
K14
U23
W17
T15
Supply for SOC Logic
Supply for Frac PLL
Supply for Arm PLL
VDDA_1P8_FPLL
VDDA_1P8_FPLL_ARM
VDDA_1P8_LVDS
VDDA_1P8_SPLL
VDDA_1P8_SPLL_DRAM
Supply for LVDS Interface
Supply for SSCG PLL
Supply for DRAM PLL
Supply for VIDEO PLL2
Supply for temperature sensor
Supply for XTAL
VDDA_1P8_SPLL_VIDEO2 N11
VDDA_1P8_TSENSOR
VDDA_1P8_XTAL_25M
VDDA_1P8_XTAL_27M
VDDA_DRAM
T16
W24
W23
AA11
Supply for XTAL
Supply for DRAM Module
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 79
Package information and contact assignments
Table 83. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm supplies contact assignments (continued)
VSS
A2, A24, B1, B25, C8, C10, C13, C15, C24,
D10, D13, D15, D23, E4, E10, E13, E14, E16,
E19, E20, E21, E22, E23, F10, F13, F14, F16,
F20, G9, G10, G13, G17, G18, G24, H8, H9,
H10, H11, H12, H13, H17, H18, J3, J8, J11,
J12, J13, J14, J17, J18, J19, K8, K11, K17,
K18, K23, L8, L11, L14, L17, M8, M11, M14,
M17, N3, N14, N15, N16, N17, N18, P6, P8,
P11, P14, P17, P18, P23, R7, T3, T4, T9, T10,
T11, T12, T13, U8, U9, U15, U18, V4, V8, V16,
W1, W7, W8, W9, W10, W11, W12, W13,
W14, W15, W16, W25, Y2, Y3, Y4, Y5, Y7, Y9,
Y11, Y13, Y15, Y17, Y19, Y21, Y22, Y23, Y24,
AA5, AA16, AA21, AB2, AB9, AB11, AB18,
AB24, AC4, AC19, AC22, AD1, AD7, AD9,
AD11, AD13, AD16, AD25, AE2, AE5, AE21,
AE24
—
VSSA_FPLL
U16
K13
V17
T14
N12
V23
W22
Return path of VDDA_1P8_FPLL
VSSA_FPLL_ARM
VSSA_SPLL
Return path of VDDA_1P8_FPLL_ARM
Return path of VDDA_1P8_SPLL
VSSA_SPLL_DRAM
VSSA_SPLL_VIDEO2
VSSA_XTAL_25M
VSSA_XTAL_27M
Return path of VDDA_1P8_SPLL_DRAM
Return path of VDDA_1P8_SPLL_VIDEO2
Return path of VDDA_1P8_XTAL_25M
Return path of VDDA_1P8_XTAL_27M
Table 84 shows an alpha-sorted list of functional contact assignments for the 17 x 17 mm package.
Table 84. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments
Reset condition2
Default
Ball name
Ball
Power group
Ball type1
mode
(Reset
mode)
Default function
(Signal name)
Input/
Output
Value
BOOT_MODE0
BOOT_MODE1
W6
V6
NVCC_JTAG
NVCC_JTAG
GPIO
GPIO
ALT0 ccmsrcgpcmix.BOOT_
MODE[0]
Input
Input
PD (90 K)
PD (90 K)
ALT0 ccmsrcgpcmix.BOOT_
MODE[1]
CLK1_P
CLK1_N
R23
T23
VDDA
VDDA
LVDS
LVDS
LVDS
LVDS
DDR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLK2_P
T22
VDDA
CLK2_N
U22
AC16
VDDA
DRAM_AC00
NVCC_DRAM
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
80 NXP Semiconductors
Package information and contact assignments
Table 84. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued)
Reset condition2
Default
Ball name
Ball
Power group
Ball type1
mode
(Reset
mode)
Default function
(Signal name)
Input/
Output
Value
DRAM_AC01
DRAM_AC02
DRAM_AC03
DRAM_AC04
DRAM_AC05
DRAM_AC06
DRAM_AC07
DRAM_AC08
DRAM_AC09
DRAM_AC10
DRAM_AC11
DRAM_AC12
DRAM_AC13
DRAM_AC14
DRAM_AC15
DRAM_AC16
DRAM_AC17
DRAM_AC19
DRAM_AC20
DRAM_AC21
DRAM_AC22
DRAM_AC23
DRAM_AC24
DRAM_AC25
DRAM_AC26
DRAM_AC27
DRAM_AC28
DRAM_AC29
DRAM_AC30
DRAM_AC31
AE17
AE18
AC18
AD14
AE14
AE13
AB15
AD17
AE16
AD20
AE20
AD19
AE19
AB16
AC15
AE15
AD15
AB14
AD10
AE10
AD8
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AC9
AD12
AE12
AB12
AA12
AC7
AE7
AE6
AD6
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 81
Package information and contact assignments
Table 84. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued)
Reset condition2
Default
Ball name
Ball
Power group
Ball type1
mode
(Reset
mode)
Default function
(Signal name)
Input/
Output
Value
DRAM_AC32
DRAM_AC33
DRAM_AC34
DRAM_AC35
DRAM_AC36
DRAM_AC37
DRAM_AC38
AE8
AE9
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AC10
AB10
AC12
AE11
AC11
DRAM_ALERT_N AC13
DRAM_DM0
DRAM_DM1
DRAM_DM2
DRAM_DM3
DRAM_DQ00
DRAM_DQ01
DRAM_DQ02
DRAM_DQ03
DRAM_DQ04
DRAM_DQ05
DRAM_DQ06
DRAM_DQ07
DRAM_DQ08
DRAM_DQ09
DRAM_DQ10
DRAM_DQ11
DRAM_DQ12
DRAM_DQ13
DRAM_DQ14
DRAM_DQ15
DRAM_DQ16
DRAM_DQ17
AD23
AB20
AD3
AB6
AE23
AD24
AE22
AD22
AA24
Y25
AA25
AB25
AB22
AA22
AA23
AA20
AA18
AB19
AA19
AA17
AE3
AD2
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
82 NXP Semiconductors
Package information and contact assignments
Table 84. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued)
Reset condition2
Default
Ball name
Ball
Power group
Ball type1
mode
(Reset
mode)
Default function
(Signal name)
Input/
Output
Value
DRAM_DQ18
DRAM_DQ19
DRAM_DQ20
DRAM_DQ21
DRAM_DQ22
DRAM_DQ23
DRAM_DQ24
DRAM_DQ25
DRAM_DQ26
DRAM_DQ27
DRAM_DQ28
DRAM_DQ29
DRAM_DQ30
DRAM_DQ31
DRAM_DQS0_N
DRAM_DQS0_P
DRAM_DQS1_N
DRAM_DQS1_P
DRAM_DQS2_N
DRAM_DQS2_P
DRAM_DQS3_N
DRAM_DQS3_P
AE4
AD4
AA2
Y1
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_ECSPI
NVCC_ECSPI
NVCC_ECSPI
NVCC_ECSPI
NVCC_ECSPI
DDR
DDR
—
—
—
—
—
—
—
—
DDR
—
—
—
—
DDR
—
—
—
—
AA1
AB1
AB4
AA4
AA3
AA6
AA8
AB7
AA7
AA9
AC25
AC24
AC21
AB21
AC1
AC2
AC5
AB5
DDR
—
—
—
—
DDR
—
—
—
—
DDR
—
—
—
—
DDR
—
—
—
—
DDR
—
—
—
—
DDR
—
—
—
—
DDR
—
—
—
—
DDR
—
—
—
—
DDR
—
—
—
—
DDR
—
—
—
—
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DRAM_RESET_N AB13
—
—
—
—
DRAM_VREF
DRAM_ZN
AA14
AA13
B4
DDR
—
—
—
—
DDR
—
—
—
—
ECSPI1_MISO
ECSPI1_MOSI
ECSPI1_SCLK
ECSPI1_SS0
ECSPI2_MISO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO5.IO[8]
GPIO5.IO[7]
GPIO5.IO[6]
GPIO5.IO[9]
GPIO5.IO[12]
Input
Input
Input
Input
Input
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
A4
GPIO
D5
GPIO
D4
GPIO
B5
GPIO
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 83
Package information and contact assignments
Table 84. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued)
Reset condition2
Default
Ball name
Ball
Power group
Ball type1
mode
(Reset
mode)
Default function
(Signal name)
Input/
Output
Value
ECSPI2_MOSI
ECSPI2_SCLK
ECSPI2_SS0
ENET_MDC
ENET_MDIO
ENET_RD0
E5
C5
NVCC_ECSPI
NVCC_ECSPI
NVCC_ECSPI
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_ENET
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
GPIO5.IO[11]
GPIO5.IO[10]
GPIO5.IO[13]
GPIO1.IO[16]
GPIO1.IO[17]
GPIO1.IO[26]
GPIO1.IO[27]
GPIO1.IO[28]
GPIO1.IO[29]
GPIO1.IO[25]
GPIO1.IO[24]
GPIO1.IO[21]
GPIO1.IO[20]
GPIO1.IO[19]
GPIO1.IO[18]
GPIO1.IO[23]
GPIO1.IO[22]
GPIO1.IO[0]
GPIO1.IO[1]
GPIO1.IO[2]
GPIO1.IO[3]
GPIO1.IO[4]
GPIO1.IO[5]
GPIO1.IO[6]
GPIO1.IO[7]
GPIO1.IO[8]
GPIO1.IO[9]
GPIO1.IO[10]
GPIO1.IO[11]
GPIO1.IO[12]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (27 K)
PD (90 K)
PD (90 K)
PU (27 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
A5
N20
N19
U19
U21
U20
V19
T20
T21
R20
R21
R19
P20
T19
P19
T6
ENET_RD1
ENET_RD2
ENET_RD3
ENET_RXC
ENET_RX_CTL
ENET_TD0
ENET_TD1
ENET_TD2
ENET_TD3
ENET_TXC
ENET_TX_CTL
GPIO1_IO00
GPIO1_IO013
GPIO1_IO02
GPIO1_IO03
GPIO1_IO04
GPIO1_IO054
GPIO1_IO06
GPIO1_IO07
GPIO1_IO08
GPIO1_IO09
GPIO1_IO10
GPIO1_IO11
GPIO1_IO12
T7
R4
P4
P5
P7
N5
N6
N7
M6
M7
L6
L7
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
84 NXP Semiconductors
Package information and contact assignments
Table 84. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued)
Reset condition2
Default
Ball name
Ball
Power group
Ball type1
mode
(Reset
mode)
Default function
(Signal name)
Input/
Output
Value
GPIO1_IO13
GPIO1_IO14
K6
K7
J6
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
HDMI_AVDDIO
NVCC_I2C
GPIO
GPIO
GPIO
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT0
ALT0
ALT0
—
GPIO1.IO[13]
Input
Input
Input
—
PD (90 K)
GPIO1.IO[14]
PD (90 K)
GPIO1_IO15
GPIO1.IO[15]
PD (90 K)
HDMI_AUX_N
HDMI_AUX_P
HDMI_CEC
V2
V1
W3
R3
P3
W2
R1
R2
P1
T2
U1
N1
M2
T1
U2
N2
M1
E7
E8
G7
F7
G8
E9
F8
F9
U7
T5
—
—
—
—
—
—
—
—
—
—
HDMI_DDC_SCL
HDMI_DDC_SDA
HDMI_HPD
—
—
—
—
—
—
—
—
—
—
—
—
HDMI_REFCLK_N
HDMI_REFCLK_P
HDMI_REXT
—
—
—
—
—
—
—
—
—
—
—
—
HDMI_TX_M_LN_0
HDMI_TX_M_LN_1
HDMI_TX_M_LN_2
HDMI_TX_M_LN_3
HDMI_TX_P_LN_0
HDMI_TX_P_LN_1
HDMI_TX_P_LN_2
HDMI_TX_P_LN_3
I2C1_SCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
ALT0
GPIO5.IO[14]
GPIO5.IO[15]
GPIO5.IO[16]
GPIO5.IO[17]
GPIO5.IO[18]
GPIO5.IO[19]
GPIO5.IO[20]
GPIO5.IO[21]
cjtag_wrapper.MOD
cjtag_wrapper.TCK
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PU 27 K)
I2C1_SDA
NVCC_I2C
I2C2_SCL
NVCC_I2C
I2C2_SDA
NVCC_I2C
I2C3_SCL
NVCC_I2C
I2C3_SDA
NVCC_I2C
I2C4_SCL
NVCC_I2C
I2C4_SDA
NVCC_I2C
JTAG_MOD
NVCC_JTAG
NVCC_JTAG
JTAG_TCK
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 85
Package information and contact assignments
Table 84. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued)
Reset condition2
Default
Ball name
Ball
Power group
Ball type1
mode
(Reset
mode)
Default function
(Signal name)
Input/
Output
Value
JTAG_TDI
JTAG_TDO
W5
U5
V5
U6
NVCC_JTAG
NVCC_JTAG
NVCC_JTAG
NVCC_JTAG
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
GPIO
GPIO
GPIO
GPIO
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
PHY
ALT0
ALT0
ALT0
cjtag_wrapper.TDI
cjtag_wrapper.TDO
cjtag_wrapper.TMS
Input
Input
Input
Input
—
PU (27 K)
PU (27 K)
JTAG_TMS
PU (27 K)
JTAG_TRST_B
ALT0 cjtag_wrapper.TRST_B
PU (27 K)
—
MIPI_CSI1_CLK_N A22
MIPI_CSI1_CLK_P B22
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MIPI_CSI1_D0_N
MIPI_CSI1_D0_P
MIPI_CSI1_D1_N
MIPI_CSI1_D1_P
MIPI_CSI1_D2_N
MIPI_CSI1_D2_P
MIPI_CSI1_D3_N
MIPI_CSI1_D3_P
A23
B23
C22
D22
B24
C23
C21
D21
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MIPI_CSI2_CLK_N A19
MIPI_CSI2_CLK_P B19
—
—
—
—
MIPI_CSI2_D0_N
MIPI_CSI2_D0_P
MIPI_CSI2_D1_N
MIPI_CSI2_D1_P
MIPI_CSI2_D2_N
MIPI_CSI2_D2_P
MIPI_CSI2_D3_N
MIPI_CSI2_D3_P
MIPI_DSI_CLK_N
MIPI_DSI_CLK_P
MIPI_DSI_D0_N
MIPI_DSI_D0_P
MIPI_DSI_D1_N
MIPI_DSI_D1_P
C20
D20
A20
B20
A21
B21
C19
D19
C16
D16
A17
B17
A16
B16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
86 NXP Semiconductors
Package information and contact assignments
Table 84. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued)
Reset condition2
Default
Ball name
Ball
Power group
Ball type1
mode
(Reset
mode)
Default function
(Signal name)
Input/
Output
Value
MIPI_DSI_D2_N
MIPI_DSI_D2_P
MIPI_DSI_D3_N
MIPI_DSI_D3_P
MIPI_DSI_REXT
NAND_ALE
A18
B18
A15
B15
C17
G19
H19
G21
F21
H20
H21
G20
J20
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
MIPI_VDDHA
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_NAND
NVCC_SNVS
PCIE_VPH
PHY
PHY
—
—
—
—
—
—
—
—
PHY
—
—
—
—
PHY
—
—
—
—
PHY
—
—
—
—
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PHY
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
—
GPIO3.IO[0]
GPIO3.IO[1]
GPIO3.IO[2]
GPIO3.IO[3]
GPIO3.IO[4]
GPIO3.IO[5]
GPIO3.IO[6]
GPIO3.IO[7]
GPIO3.IO[8]
GPIO3.IO[9]
GPIO3.IO[10]
GPIO3.IO[11]
GPIO3.IO[12]
GPIO3.IO[13]
GPIO3.IO[14]
GPIO3.IO[15]
GPIO3.IO[16]
GPIO3.IO[17]
GPIO3.IO[18]
snvsmix.ONOFF
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
—
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PU (27 K)
—
NAND_CE0_B
NAND_CE1_B
NAND_CE2_B
NAND_CE3_B
NAND_CLE
NAND_DATA00
NAND_DATA01
NAND_DATA02
NAND_DATA03
NAND_DATA04
NAND_DATA05
NAND_DATA06
NAND_DATA07
NAND_DQS
H22
J21
L20
J22
L19
M19
M20
K19
K20
K22
K21
W21
NAND_RE_B
NAND_READY_B
NAND_WE_B
NAND_WP_B
ONOFF
PCIE1_REF_PAD_C K24
LK_N
PCIE1_REF_PAD_C K25
LK_P
PCIE_VPH
PCIE_VPH
PHY
PHY
—
—
—
—
—
—
—
—
PCIE1_RESREF
G25
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 87
Package information and contact assignments
Table 84. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued)
Reset condition2
Default
Ball name
Ball
Power group
Ball type1
mode
(Reset
mode)
Default function
(Signal name)
Input/
Output
Value
PCIE1_RXN_N
PCIE1_RXN_P
PCIE1_TXN_N
PCIE1_TXN_P
H24
H25
J24
J25
PCIE_VPH
PCIE_VPH
PCIE_VPH
PCIE_VPH
PCIE_VPH
PHY
PHY
PHY
PHY
PHY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PCIE2_REF_PAD_C F24
LK_N
PCIE2_REF_PAD_C F25
LK_P
PCIE_VPH
PHY
—
—
—
—
PCIE2_RESREF
PCIE2_RXN_N
PCIE2_RXN_P
PCIE2_TXN_N
PCIE2_TXN_P
PMIC_ON_REQ
C25
D24
D25
E24
E25
V20
PCIE_VPH
PCIE_VPH
PCIE_VPH
PCIE_VPH
PCIE_VPH
NVCC_SNVS
PHY
PHY
PHY
PHY
PHY
GPIO
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ALT0 snvsmix.PMIC_ON_RE
Q
Output
Open-Drain
PU (27 K)
PMIC_STBY_REQ
V21
NVCC_SNVS
GPIO
ALT0 ccmsrcgpcmix.PMIC_S
TBY_REQ
Output
Low
POR_B
RTC
W20
V22
W19
A3
NVCC_SNVS
NVCC_SNVS
NVCC_SNVS
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT0
ALT0
ALT0
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
snvsmix.POR_B
snvsmix.RTC
snvsmix.RTC_POR_B
GPIO4.IO[20]
GPIO4.IO[1]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
PU (27 K)
PD (90 K)
PU (27 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
RTC_RESET_B
SAI1_MCLK
SAI1_RXC
K1
SAI1_RXD05
SAI1_RXD15
SAI1_RXD25
SAI1_RXD35
SAI1_RXD45
SAI1_RXD55
SAI1_RXD65
SAI1_RXD75
SAI1_RXFS
K2
GPIO4.IO[2]
L2
GPIO4.IO[3]
H2
J2
GPIO4.IO[4]
GPIO4.IO[5]
J1
GPIO4.IO[6]
F1
GPIO4.IO[7]
G2
G1
L1
GPIO4.IO[8]
GPIO4.IO[9]
GPIO4.IO[0]
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
88 NXP Semiconductors
Package information and contact assignments
Table 84. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued)
Reset condition2
Default
Ball name
Ball
Power group
Ball type1
mode
(Reset
mode)
Default function
(Signal name)
Input/
Output
Value
SAI1_TXC
SAI1_TXD05
SAI1_TXD15
SAI1_TXD25
SAI1_TXD35
SAI1_TXD45
SAI1_TXD55
SAI1_TXD65
SAI1_TXD75
SAI1_TXFS
SAI2_MCLK
SAI2_RXC
E1
F2
E2
B2
D1
D2
C2
B3
C1
H1
H5
H3
H6
J4
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI1
NVCC_SAI2
NVCC_SAI2
NVCC_SAI2
NVCC_SAI2
NVCC_SAI2
NVCC_SAI2
NVCC_SAI2
NVCC_SAI3
NVCC_SAI3
NVCC_SAI3
NVCC_SAI3
NVCC_SAI3
NVCC_SAI3
NVCC_SAI3
NVCC_SAI5
NVCC_SAI5
NVCC_SAI5
NVCC_SAI5
NVCC_SAI5
NVCC_SAI5
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO4.IO[11]
GPIO4.IO[12]
GPIO4.IO[13]
GPIO4.IO[14]
GPIO4.IO[15]
GPIO4.IO[16]
GPIO4.IO[17]
GPIO4.IO[18]
GPIO4.IO[19]
GPIO4.IO[10]
GPIO4.IO[27]
GPIO4.IO[22]
GPIO4.IO[23]
GPIO4.IO[21]
GPIO4.IO[25]
GPIO4.IO[26]
GPIO4.IO[24]
GPIO5.IO[2]
GPIO4.IO[29]
GPIO4.IO[30]
GPIO4.IO[28]
GPIO5.IO[0]
GPIO5.IO[1]
GPIO4.IO[31]
GPIO3.IO[25]
GPIO3.IO[20]
GPIO3.IO[21]
GPIO3.IO[22]
GPIO3.IO[23]
GPIO3.IO[24]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
SAI2_RXD0
SAI2_RXFS
SAI2_TXC
J5
SAI2_TXD0
SAI2_TXFS
SAI3_MCLK
SAI3_RXC
G5
H4
D3
F4
F3
G4
C4
C3
G3
K4
L5
SAI3_RXD
SAI3_RXFS
SAI3_TXC
SAI3_TXD
SAI3_TXFS
SAI5_MCLK
SAI5_RXC
SAI5_RXD0
SAI5_RXD1
SAI5_RXD2
SAI5_RXD3
M5
L4
M4
K5
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 89
Package information and contact assignments
Table 84. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued)
Reset condition2
Default
Ball name
Ball
Power group
Ball type1
mode
(Reset
mode)
Default function
(Signal name)
Input/
Output
Value
SAI5_RXFS
SD1_CLK
N4
L25
L24
M25
M24
N25
P25
N24
P24
R25
T25
R24
T24
L21
L22
M22
N22
N21
P22
P21
R22
M21
E6
NVCC_SAI5
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SAI3
NVCC_SAI3
NVCC_SAI3
NVCC_JTAG
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
ALT5
ALT5
ALT5
ALT5
GPIO3.IO[19]
GPIO2.IO[0]
GPIO2.IO[1]
GPIO2.IO[2]
GPIO2.IO[3]
GPIO2.IO[4]
GPIO2.IO[5]
GPIO2.IO[6]
GPIO2.IO[7]
GPIO2.IO[8]
GPIO2.IO[9]
GPIO2.IO[10]
GPIO2.IO[11]
GPIO2.IO[12]
GPIO2.IO[13]
GPIO2.IO[14]
GPIO2.IO[15]
GPIO2.IO[16]
GPIO2.IO[17]
GPIO2.IO[18]
GPIO2.IO[19]
GPIO2.IO[20]
GPIO5.IO[5]
GPIO5.IO[4]
GPIO5.IO[3]
tcu.TEST_MODE
GPIO5.IO[22]
GPIO5.IO[23]
GPIO5.IO[24]
GPIO5.IO[25]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
PD (90 K)
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SD1_DATA4
SD1_DATA5
SD1_DATA6
SD1_DATA7
SD1_RESET_B
SD1_STROBE
SD2_CD_B
SD2_CLK
SD2_CMD
SD2_DATA0
SD2_DATA1
SD2_DATA2
SD2_DATA3
SD2_RESET_B
SD2_WP
SPDIF_EXT_CLK
SPDIF_RX
G6
SPDIF_TX
F6
TEST_MODE
UART1_RXD
UART1_TXD
UART2_RXD
UART2_TXD
V7
C7
A7
B6
D6
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
90 NXP Semiconductors
Package information and contact assignments
Table 84. i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm functional contact assignments (continued)
Reset condition2
Default
Ball name
Ball
Power group
Ball type1
mode
(Reset
mode)
Default function
(Signal name)
Input/
Output
Value
UART3_RXD
UART3_TXD
UART4_RXD
UART4_TXD
USB1_DN
A6
B7
NVCC_UART
NVCC_UART
NVCC_UART
NVCC_UART
USB1_VDD33
USB1_VDD33
USB1_VDD33
USB1_VPH
USB1_VPH
USB1_VPH
USB1_VPH
USB1_VPH
USB1_VDD33
USB2_VDD33
USB2_VDD33
USB2_VDD33
USB2_VPH
USB2_VPH
USB2_VPH
USB2_VPH
USB2_VPH
USB2_VDD33
VDDA
GPIO
GPIO
GPIO
GPIO
PHY
ALT5
ALT5
ALT5
ALT5
—
GPIO5.IO[26]
Input
Input
Input
Input
—
PD (90 K)
GPIO5.IO[27]
PD (90 K)
C6
GPIO5.IO[28]
PD (90 K)
D7
GPIO5.IO[29]
PD (90 K)
—
B14
A14
C14
A11
B12
A12
B13
A13
D14
B10
A10
C9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
USB1_DP
PHY
—
—
—
USB1_ID
PHY
—
—
—
USB1_RESREF
USB1_RX_N
USB1_RX_P
USB1_TX_N
USB1_TX_P
USB1_VBUS
USB2_DN
PHY
—
—
—
PHY
—
—
—
PHY
—
—
—
PHY
—
—
—
PHY
—
—
—
PHY
—
—
—
PHY
—
—
—
USB2_DP
PHY
—
—
—
USB2_ID
PHY
—
—
—
USB2_RESREF
USB2_RX_N
USB2_RX_P
USB2_TX_N
USB2_TX_P
USB2_VBUS
XTALI_25M
XTALI_27M
XTALO_25M
XTALO_27M
B11
B8
PHY
—
—
—
PHY
—
—
—
A8
PHY
—
—
—
B9
PHY
—
—
—
A9
PHY
—
—
—
D9
PHY
—
—
—
U25
V25
U24
V24
ANALOG
ANALOG
ANALOG
ANALOG
—
—
—
VDDA
—
—
—
VDDA
—
—
—
VDDA
—
—
—
1
2
3
4
5
The state immediately after RESET and before ROM firmware or software has executed.
The state during, after RESET and before ROM firmware or software has executed.
Jtag Active output during reset
INT_BOOT output (High) during reset
Boot Configure Input
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 91
Package information and contact assignments
5.1.3
i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm 0.65 mm pitch ball
map
Table 85 shows the i.MX 8M Dual / 8M QuadLite / 8M Quad 17 x 17 mm, 0.65 mm pitch ball map.
Table 85. 17 x 17 mm, 0.65 mm pitch ball map
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
92 NXP Semiconductors
Package information and contact assignments
Table 85. 17 x 17 mm, 0.65 mm pitch ball map (continued)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1
2
3
4
5
6
7
8
9
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 93
Package information and contact assignments
Table 85. 17 x 17 mm, 0.65 mm pitch ball map (continued)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1
2
3
4
5
6
7
8
9
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
94 NXP Semiconductors
Package information and contact assignments
Table 85. 17 x 17 mm, 0.65 mm pitch ball map (continued)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1
2
3
4
5
6
7
8
9
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NXP Semiconductors 95
Package information and contact assignments
5.2
DDR pin function list for 17 x 17 mm package
Table 86 shows the DDR pin function list for 17 x 17 mm package.
Table 86. DDR pin function list for 17 x 17 mm package
Die level pin name
LPDDR4
DDR4
DDR3L
BALL
DRAM_DQS0_P
DRAM_DQS0_N
DRAM_DM0
DQS0_t_A
DQS0_C_A
DMI0_A
DQ0_A
DQSL_t_A
DQSL_C_A
DML_N_A / DBIL_n_A
DQL0_A
DQSL_A
DQSL#_A
DML_A
AC24
AC25
AD23
AE23
AD24
AE22
AD22
AA24
Y25
DRAM_DQ00
DRAM_DQ01
DRAM_DQ02
DRAM_DQ03
DRAM_DQ04
DRAM_DQ05
DRAM_DQ06
DRAM_DQ07
DRAM_DQS1_P
DRAM_DQS1_N
DRAM_DM1
DQL0_A
DQL1_A
DQL2_A
DQL3_A
DQL4_A
DQL5_A
DQL6_A
DQL7_A
DQSU_A
DQSU#_A
DMU_A
DQ1_A
DQL1_A
DQ2_A
DQL2_A
DQ3_A
DQL3_A
DQ4_A
DQL4_A
DQ5_A
DQL5_A
DQ6_A
DQL6_A
AA25
AB25
AB21
AC21
AB20
AB22
AA22
AA23
AA20
AA18
AB19
AA19
AA17
AC2
DQ7_A
DQL7_A
DQS1_t_A
DQS1_c_A
DMI1_A
DQ08_A
DQ09_A
DQ10_A
DQ11_A
DQ12_A
DQ13_A
DQ14_A
DQ15_A
DQS0_t_B
DQS0_c_B
DMI0_B
DQ0_B
DQSU_t_A
DQSU_c_A
DMU_n_A / DBIU_n_A
DQU0_A
DRAM_DQ08
DRAM_DQ09
DRAM_DQ10
DRAM_DQ11
DRAM_DQ12
DRAM_DQ13
DRAM_DQ14
DRAM_DQ15
DRAM_DQS2_P
DRAM_DQS2_N
DRAM_DM2
DQU0_A
DQU1_A
DQU2_A
DQU3_A
DQU4_A
DQU5_A
DQU6_A
DQU7_A
DQSL_B
DQSL#_B
DML_B
DQU1_A
DQU2_A
DQU3_A
DQU4_A
DQU5_A
DQU6_A
DQU7_A
DQSL_t_B
DQSL_c_B
DML_n_B / DBIL_n_B
DQL0_B
AC1
AD3
DRAM_DQ16
DRAM_DQ17
DRAM_DQ18
DRAM_DQ19
DRAM_DQ20
DRAM_DQ20
DQL0_B
DQL1_B
DQL2_B
DQL3_B
DQL4_B
DQL4_B
AE3
DQ1_B
DQL1_B
AD2
DQ2_B
DQL2_B
AE4
DQ3_B
DQL3_B
AD4
DQ4_B
DQL4_B
AA2
DQ4_B
DQL4_B
AA2
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
96 NXP Semiconductors
Package information and contact assignments
Table 86. DDR pin function list for 17 x 17 mm package (continued)
DRAM_DQ21
DRAM_DQ22
DRAM_DQ23
DRAM_DQS3_P
DRAM_DQS3_N
DRAM_DM3
DQ5_B
DQ6_B
DQ7_B
DQS1_t_B
DQS1_c_B
DMI1_B
DQ08_B
DQ09_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B
RESET_N
MTEST1
CKE0_A
CKE1_A
CS0_A
CS1_A
CK_t_A
CK_c_A
—
DQL5_B
DQL6_B
DQL7_B
DQSU_t_B
DQSU_c_B
DMU_n_B / DBIU_n_B
DQU0_B
DQU1_B
DQU2_B
DQU3_B
DQU4_B
DQU5_B
DQU6_B
DQU7_B
RESET_N
ALERT_n / MTEST1
CKE0
DQL5_B
DQL6_B
DQL7_B
DQSU_B
DQSU#_B
DMU_B
DQU0_B
DQU1_B
DQU2_B
DQU3_B
DQU4_B
DQU5_B
DQU6_B
DQU7_B
RESET#
MTEST1
CKE0
Y1
AA1
AB1
AB5
AC5
AB6
DRAM_DQ24
DRAM_DQ25
DRAM_DQ26
DRAM_DQ27
DRAM_DQ28
DRAM_DQ29
DRAM_DQ30
DRAM_DQ31
DRAM_RESET_N
DRAM_ALERT_N
DRAM_AC00
DRAM_AC01
DRAM_AC02
DRAM_AC03
DRAM_AC04
DRAM_AC05
DRAM_AC06
DRAM_AC07
DRAM_AC08
DRAM_AC09
DRAM_AC10
DRAM_AC11
DRAM_AC12
DRAM_AC13
DRAM_AC14
DRAM_AC15
DRAM_AC16
DRAM_AC17
AB4
AA4
AA3
AA6
AA8
AB7
AA7
AA9
AB13
AC13
AC16
AE17
AE18
AC18
AD14
AE14
AE13
AB15
AD17
AE16
AD20
AE20
AD19
AE19
AB16
AC15
AE15
AD15
CKE1
CKE1
CS0_n
CS0#
C0
—
BG0
BA2
BG1
A14
ACT_n
A15
—
A9
A9
CA0_A
CA1_A
CA2_A
CA3_A
CA4_A
CA5_A
—
A12
A12 / BC#
A11
A11
A7
A7
A8
A8
A6
A6
A5
A5
A4
A4
—
A3
A3
—
CK_t_A
CK_c_A
CK_A
—
CK#_A
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors 97
Package information and contact assignments
Table 86. DDR pin function list for 17 x 17 mm package (continued)
DRAM_AC19
DRAM_AC20
DRAM_AC21
DRAM_AC22
DRAM_AC23
DRAM_AC24
DRAM_AC25
DRAM_AC26
DRAM_AC27
DRAM_AC28
DRAM_AC29
DRAM_AC30
DRAM_AC31
DRAM_AC32
DRAM_AC33
DRAM_AC34
DRAM_AC35
DRAM_AC36
DRAM_AC37
DRAM_AC38
DRAM_ZN
MTEST
CKE0_B
CKE1_B
CS1_B
CS0_B
CK_t_B
CK_c_B
—
MTEST
CK_t_B
CK_c_B
—
MTEST
CK_B
CK#_B
—
AB14
AD10
AE10
AD8
—
—
AC9
A2
A2
AD12
AE12
AB12
AA12
AC7
A1
A1
BA1
BA1
—
PARITY
A13
—
CA2_B
CA3_B
CA4_B
CA5_B
CA0_B
CA1_B
—
A13
BA0
BA0
AE7
A10 / AP
A0
A10 / AP
A0
AE6
AD6
C2
—
AE8
CAS_n / A15
WE_n / A14
RAS_n / A16
ODT0
ODT1
CS1_n
ZQ
CAS#
WE#
RAS#
ODT0
ODT1
CS1#
ZQ
AE9
AC10
AB10
AC12
AE11
AC11
AA13
AA14
—
—
—
—
ZQ
DRAM_VREF
VREF
VREF
VREF
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
98 NXP Semiconductors
Revision history
6 Revision history
Table 87 provides a revision history for this data sheet.
Table 87. Revision history
Rev.
number
Date
Substantive change(s)
Rev. 1.1 05/2019 • Updated the package type information in the Figure 2, "Part number nomenclature—i.MX 8M Dual / 8M
QuadLite / 8M Quad processors"
• Updated eCSPI description in the Table 3, "i.MX 8M Dual / 8M QuadLite / 8M Quad modules list"
• Added the core voltage, analog domain voltage, PLL 1.8 V voltage, 25 MHz crystal voltage, 27 MHz
crystal voltage, DDR I/O voltage, HDMI voltage, MIPI voltage, PCIe voltage, temperature sensor
voltage, and fuse power in the Table 5, "Absolute maximum ratings"
• Updated the Table 6, "Thermal resistance data"
• Updated the RUN mode unit in the Table 10, "Chip power in different LP mode"
Rev. 1 10/2018 • Updated the Table 2, "Orderable part numbers"
• Updated the Figure 2, "Part number nomenclature—i.MX 8M Dual / 8M QuadLite / 8M Quad
processors"
Rev. 0.2 08/2018 • Updated the Table 7, "Operating ranges"
• Updated the Section 3.1.4, External clock sources
• Updated the Section 3.1.5, Maximum supply currents
• Updated the Section 3.2.1, Power-up sequence
• Updated the Figure 5, "Differential LVDS driver transition time waveform"
• Updated the Section 3.9.3.1, RMII mode timing
• Updated the Section 5.1.2, 17 x 17 mm supplies contact assignments and functional contact
assignments
• Fixed a typo in the Table 85, "17 x 17 mm, 0.65 mm pitch ball map"
Rev. 0.1 05/2018 • Added a note in the Table 2, "Orderable part numbers"
• Updated the Table 3, "i.MX 8M Dual / 8M QuadLite / 8M Quad modules list"
• Updated the Table 7, "Operating ranges"
• Updated the Table 9, "Maximum supply currents"
• Updated the Table 10, "Chip power in different LP mode"
• Added the Table 11, "The power supply states"
• Updated the PCIe parameters in the Table 15, "PCIe recommended operating conditions"
• Updated and added a leakage limit note in the Table 26, "GPIO DC parameters"
• Added a leakage limit note in the Table 29, "Input DC current"
• Updated the timing parameters in the Table 38, "ECSPI Master mode timing parameters" and Table 39,
"ECSPI Slave mode timing parameters"
• Updated the Section 3.9.8.1, PCIEx_RESREF reference resistor connection
• Updated the Table 59, "MIPI input characteristics DC specifications"
• Removed the SPI interfaces from the Table 82, "Interface allocation during boot"
• Updated the PCIe and MIPI power group in the Table 84, "i.MX 8M Dual / 8M QuadLite / 8M Quad
17 x 17 mm functional contact assignments"
• Updated the Table 85, "17 x 17 mm, 0.65 mm pitch ball map"
Rev. 0 01/2018 • Initial version
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1.1, 07/2019
NXP Semiconductors
99
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Document Number: IMX8MDQLQCEC
Rev. 1.1
07/2019
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