ABT22V10A7A-T [NXP]
OT PLD, 8ns, PQCC28;
| 型号： | ABT22V10A7A-T |
| 厂家： | 
NXP |
| 描述： | OT PLD, 8ns, PQCC28 时钟 输入元件 信息通信管理 可编程逻辑 |
| 文件： | 总18页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
ABT22V10A5, A7
5V high-speed universal PLD device
with live insertion capability
Product specification
IC13 Data Handbook
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
DESCRIPTION
PIN CONFIGURATIONS
The ABT22V10A is a versatile PAL device fabricated on Philips
BiCMOS process known as QUBiC.
A Package
The QUBiC process produces very high speed, 5 volt devices
(5.0ns) which have excellent noise immunity. The ground bounce of
an output held low while the 9 remaining outputs are switching is
less than 1.0V (typical).
CLK/
I2 I1
F9 F8
V
I0
V
CC CC
1
4
3
2
28 27 26
I3
I4
5
6
25
24
23
22
F7
F6
The ABT22V10A outputs are designed to support Live
Insertion/Extraction into powered-up systems. The output is
I5
7
F5
specially designed so that during V ramp, the output remains
CC
GND
GND
8
3-Stated until V ≈ 2.1V. At that time, the outputs become fully
CC
I6
9
21 F4
functional, depending upon device inputs. (See DC Electrical
Characteristics, Symbol I
, Page 4).
PU/PD
10
11
20
19
I7
I8
F3
F2
The ABT family of devices have virtually no ground bounce— less
than 1.0 volts V , measured on an unswitched output (9 remaining
outputs switching, each with a 50pF load tied to ground).
OLP
12 13 14 15 16 17 18
I9 I10 GNDGND I11 F0 F1
The ABT family of devices has been designed with high drive
outputs (48mA sink and 16mA source currents), which allow for
direct connection to a backplane bus. This feature eliminates the
need for additional, standalone bus drivers, which are traditionally
required to boost the drive of a standard 16/–4mA PLDs.
A = Plastic Leaded Chip Carrier
SP00367
PIN LABEL DESCRIPTIONS
Philips has developed a new means of testing the integrity of fuses,
both blown and intact fuses, which insures that all the fuses have
been correctly programmed and that each and every fuse—whether
“blown” or “intact”—is at the appropriate and optimal fuse resistance.
This dual verify scheme represents a significant improvement over
single reference voltage comparison schemes that have been used
for bipolar devices since the late 1980’s.
SYMBOL
FUNCTION
Dedicated Input
I1 – I11
F0 – F9
CLK/I0
Macro Cell Input/Output
Clock Input/Dedicated Input
Supply Voltage
V
CC
The ABT22V10A uses the familiar AND/OR logic array structure,
which allows direct implementation of sum-of-products equations.
GND
Ground
This device has a programmable AND array, which drives a fixed
OR array. The OR sum-of-products feeds an “Output Macro Cell”
(OMC) that can be individually configured as a dedicated input, a
combinatorial output, or a registered output with internal feedback.
FEATURES
• Fastest 5V 22V10
• Low ground bounce (<1.0V typical)
• Live insertion/extraction permitted
• High output drive capability: 48mA/–16mA
• Varied product term distribution with up to 16 product terms per
output for complex functions
• Metastable hardened flip-flops
• Programmable output polarity
• Design support provided for third party CAD development and
programming hardware
• Improved fuse verification circuitry increases reliability
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
DRAWING NUMBER
ABT22V10A5A
ABT22V10A7A
(5ns device)
28-Pin Plastic Leaded Chip Carrier
SOT261-3
(7.5ns device)
PAL is a registered trademark of Advanced Micro Devices, Inc.
2
1996 Dec 16
853–1795 17606
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
1
ABSOLUTE MAXIMUM RATINGS
RATINGS
UNIT
SYMBOL
PARAMETER
MIN
MAX
2
V
V
V
Supply voltage
–0.5
–1.2
–0.5
–30
+7.0
V
V
V
CC
DC
DC
DC
2
Input voltage
V
V
+ 0.5
IN
CC
CC
Output voltage
Input currents
+ 0.5
OUT
I
I
+30
mA
mA
°C
IN
OUT
Output currents
+100
+150
T
stg
Storage temperature range
–65
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at
these or any other condition above those indicated in the operational and programming specification of the device is not implied.
2. Except in programming mode.
OPERATING RANGES
RATINGS
SYMBOL
PARAMETER
UNIT
MIN
+4.75
0
MAX
+5.25
+75
V
Supply voltage
V
DC
CC
T
amb
Operating free-air temperature
°C
THERMAL RATINGS
TEMPERATURE
Maximum junction
150°C
75°C
75°C
Maximum ambient
Allowable thermal rise ambient to junction
VOLTAGE WAVEFORM
TEST LOAD CIRCUIT
V
+5V
S
1
CC
+3.0V
90%
C
C
2
R
1
1
I
0
F
0
10%
0V
C
R
L
2
DUT
t
R
t
F
INPUTS
1.5ns
1.5ns
F
I
n
n
OE
CK
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
GND
NOTE:
and C are to bypass V to GND.
C
1
2
CC
Input Pulses
SP00368
SP00369
3
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
DC ELECTRICAL CHARACTERISTICS
Over operating ranges.
LIMITS
UNIT
1
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
Input voltage
V
IL
V
IH
V
I
Low
V
= MIN
0.8
V
V
V
CC
High
V
= MAX
2.0
CC
Clamp
V
CC
= MIN, I = –18mA
–1.2
IN
Output voltage
I
I
= –32mA
= –16mA
2.0
2.4
V
V
OH
V
= MIN
IH
CC
V
High-level output voltage
Low-level output voltage
OH
V = V or V
I
IL
OH
V
CC
= MIN
IH
V
OL
I
OL
= 48mA
0.5
V
V = V or V
I
IL
Input current
I
IL
I
IH
I
I
Low
V
= MAX, V = 0.4V
–10
10
µA
µA
µA
CC
CC
CC
IN
High
V
V
= MAX, V = 2.7V
IN
Max input current
= MAX, V = 5.5V
20
IN
Output current
Power-up/down 3-State
output current
V
<2.1V; V = 0.5V to V
;
CC
I
O
CC
I
50
µA
PU/PD
4
V = GND or V ; OE/OE = X
CC
V
CC
= MAX
2
I
I
I
I
Output leakage
V
= V or V , V
= 2.7V
= V or V , V =0.4V
OUT
20
µA
µA
OZH
OZL
SC
IN
IL
IH
OUT
2
Output leakage
V
–20
IN
IL
IH
3
Short circuit
V
OUT
= 0.5V
–30
–220
200
mA
V
CC
supply current
V
CC
= MAX, Outputs enabled, V = V or GND; I = 0
mA
CC
I
CC
O
Ground Bounce
Minimum dynamic V
TYP
MAX
UNIT
V
= MAX, 25°C
CC
5
V
OLP
1.0
1.2
V
OH
C = 50pF (including jig capacitance)
L
NOTES:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I or I (where X = H or L).
OZX
IX
3. No more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. V
chosen to avoid test problems caused by tester ground degradation.
= 0.5V has been
OUT
4. This parameter is valid for any V between 0V and 1.2 V with a transition time up to 10 mS. From V = 1.2 to V = 5.0V ±0.25V a
CC
CC
CC
transition time of 100 µS is permitted. X = Don’t care.
5. Guaranteed by design, but not tested. Measured holding one output (the output under test) Low and simultaneously switching all remianing
output from a High to a Low state. Switch S1 is closed; 50pF load.
4
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
1
AC ELECTRICAL CHARACTERISTICS
4.75V ≤ V ≤ 5.25V; 0_C ≤ T
≤ +75_C
CC
amb
LIMITS
TEST
CONDITIONS
ABT22V10A5
ABT22V10A7
SYMBOL
PARAMETER
UNIT
MIN
2.0
TYP
4.5
MAX
MIN
2.0
TYP
6.0
MAX
7.5
Active-LOW
Active-HIGH
5.0
5.0
ns
ns
Input or feedback to
non-registered output
t
t
PD
2
2.0
4.5
2.0
6.0
7.5
Setup time from input or SP
to Clock
2.0
1.3
1.5
3.5
3.0
3.0
ns
S
Setup time from feedback
to Clock
t
t
t
2.25
0
3.5
0
ns
ns
ns
SIO
Hold time
H
Skew between registered
1.0
1.0
SKEWR
4, 7
outputs
t
t
Clock to output
2.0
3.5
2.0
4.0
4.0
2.0
4.5
3.0
5.5
5.0
ns
ns
CO
3
Clock to feedback
CF
Asynchronous Reset to
registered output
t
t
t
10.0
10.0
ns
ns
ns
AR
Asynchronous Reset width
6.0
4.0
7.5
5.5
ARW
ARR
Asynchronous Reset
recovery time
Synchronous Preset
recovery time
t
4.5
5.0
ns
SPR
t
t
Width of Clock LOW
Width of Clock HIGH
Maximum frequency;
2.0
2.0
3.0
3.0
ns
ns
WL
WH
External feedback
167
167
208
303
111
125
133
166
MHz
MHz
4
1/(t + t
)
CO
S
f
MAX
Maximum frequency;
Internal feedback
4
1/(t + t
)
S
CF
5
Input to Output Enable
8.0
7.5
8.0
7.5
ns
ns
t
t
EA
5
Input to Output Disable
ER
6
Capacitance
Input Capacitance (Pin 2)
V
V
= 2.0V
8
4
8
8
4
8
pF
pF
pF
IN
V
= 5.0V
= 25°C
CC
C
C
IN
T
Input Capacitance (Others)
Output Capacitance
= 2.0V
= 2.0V
amb
IN
f = 1MHz
V
OUT
OUT
NOTES:
1. Test Conditions: R = 300Ω, R =390Ω
1
2
2. t
is tested with switch S closed and C = 50pF (including jig capacitance). V = 3V, V = 0V, V = 1.5V.
PD
1 L IH IL T
3. Calculated from measured f
internal.
MAX
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency
may be affected.
5. For 3-State output; output enable times are tested with C = 50pF to the 1.5V level, and S is open for high-impedance to High tests and
L
1
closed for high-impedance to Low tests. Output disable times are tested with C 5pF. High-to-High impedance tests are made to an output
L =
voltage of V = (V – 0.5V) with S open, and Low-to-High impedance tests are made to the V = (V + 0.5V) level with S closed.
T
OH
1
T
OL
1
6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
7. Skew is measured with all outputs switching in the same direction.
5
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
PRODUCT FEATURES
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable system
initialization. Outputs of the ABT22V10A will depend on the
Low Ground Bounce
The Philips Semiconductors BiCMOS QUBiC process produces
exceptional noise immunity. The typical ground bounce, with 9
outputs simultaneously switching and the 10th output held low, is
programmed output polarity. The V rise must be monotonic and
the reset delay time is 1–10µs maximum.
CC
less than 1.0V. V
is tested by holding one output (the output
Security Fuse
OLP
uncer test) in the Low state and then simultaneously switching all
remaining outputs from a High to a Low state (each output is loaded
with 50pF). The maximum peak voltage on the output under test is
guaranteed to be less than 1.2 Volts.
After programming and verification, ABT22V10A designs can be
secured by programming the security fuse link. Once programmed,
this fuse defeats readback of the internal programmed pattern by a
device programmer, securing proprietary designs from competitors.
When the security fuse is programmed, the array will read as if
every fuse is programmed.
Live Insertion/Extraction Capability
There are some inherent problems associated with inserting or
extracting an unpowered module from a powered-up, active system.
The ABT22V10A outputs have been designed such that any chance
of bus contention, glitching or clamping is eliminated.
Quality and Testability
The ABT22V10A offers a very high level of built-in quality. Extra
programmable fuses provide a means of verifying performance of all
AC and DC parameters. In addition, this verifies programmability
and functionality of the device to provide the highest programming
and post-programming functional yields.
Detailed information on this feature is provided in an application note
AN051: Philips PLDs Support Live Insertion Applications.
Improved Fuse Verification Circuitry Increases
Reliability
Technology
The BiCMOS ABT22V10A is fabricated with the Philips
Semiconductors process known as QUBiC. QUBiC combines an
advanced, state-of-the-art 1.0µm (drawn feature size) CMOS
process with an ultra fast bipolar process to achieve superior speed
and drive capabilities. QUBiC incorporates three layers of Al/Cu
interconnects for reduced chip size, and our proven Ti-W fuse
technology ensures highest programming yields.
Philips has developed a new means of testing the integrity of fuses,
both blown and intact fuses, which insures that all the fuses have
been correctly programmed and that each and every fuse – whether
“blown” or “intact” – is at the appropriate and optimal fuse
resistance. This dual verify scheme represents a significant
improvement over single reference voltage comparisons schemes
that have been used for bipolar devices since the late 1980s.
Detailed information on this feature is provided in an application note
entitled Dual Verify Technique Increases Reliability of PLDs.
Programming
The ABT22V10A is fully supported by industry standard (JEDEC
compatible) PLD CAD tools, including Philips Semiconductors
SNAP design software package. ABEL CUPL and PALASM 90
design software packages also support the ABT22V10A
architecture.
Programmable 3-stage Outputs
Each output has a 3-Stage output buffer with 3-State control. A
product term controls the buffer, allowing enable and disable to be a
function of any product of device inputs or output feedback. The
combinatorial output provides a bidirectional I/O pin, and may be
configured as a dedicated input if the buffer is always disabled.
All packages allow Boolean and state equation entry formats, SNAP,
ABEL and CUPL also accept, as input, schematic capture format.
Programmable Output Polarity
Output Register Preload
The polarity of each macro cell output can be Active-HIGH or
Active-LOW, either to match output signal needs or to reduce
product terms. Programmable polarity allows Boolean expressions
to be written in their most compact form (true or inverted), and the
output can still be of the desired polarity. It can also save
“DeMorganizing” efforts.
The register on the ABT22V10A can be preloaded from the output
pins to facilitate functional testing of complex state machine designs.
This feature allows direct loading of arbitrary states, making it
unnecessary to cycle through long test vector sequences to reach a
desired state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper recovery. The
procedure for preloading follows:
Selection is controlled by programmable bit S in the Output Macro
0
1. Raise V to 5.0V ± 0.25V.
Cell, and affects both registered and combinatorial outputs.
Selection is automatic, based on the design specification and pin
definitions. If the pin definition and output equation have the same
CC
2. Set pin 2 or 3 to V to disable outputs and enable preload.
HH
3. Apply the desired value (V /V ) to all registered output pins.
ILP IHP
polarity, the output is programmed to be Active-HIGH (S = 1).
0
Leave combinatorial output pins floating.
4. Clock Pin 1 from V to V
.
ILP
IHP
Preset/Reset
5. Remove V /V
from all registered output pins.
For initialization, the ABT22V10A has additional Preset and Reset
product terms. These terms are connected to all registered outputs.
When the Synchronous Preset (SP) product term is asserted high,
the output registers will be loaded with a HIGH on the next
LOW-to-HIGH clock transition. When the Asynchronous Reset (AR)
product term is asserted high, the output registers will be
immediately loaded with a LOW, independent of the clock.
ILP IHP
6. Lower pin 2 or 3 to V
.
ILP
7. Enable the output registers according to the programmed
pattern.
8. Verify V /V at all registered output pins. Note that the output
OL OH
pin signal will depend on the output polarity.
Note that Preset and Reset control the flip-flop, not the output pin.
The output level is determined by the output polarity selected.
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
PALASM is a registered trademark of AMD Corp.
6
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
In this formula, F is the frequency of the clock, F is the average
Metastable Characteristics
C
1
input event frequency, and tȀ is the time after the clock pulse that the
Philips provides complete data on the ABT22V10A5’s metastable
characteristics. While the ABT22V10A5 does not employ Philips
patented metastable immune flip-flop, its metastabel characteristics
are still quite favorable relative to competitive devices. For
information on metastable immune PLDs, refer to the datasheets for
the ABT22V10-7 for 5V applications or the LVT22V10-7 for 3.3V
designs.
output is sampled (tȀ > T ). T and τ are device parameters
CO
0
provided by the semiconductor manufacturer (refer to Table 1 for the
ABT22V10A5 metastability specifications). T and τ are derived
0
from tests and can be most nearly be defined as follows: τ is a
function of the rate at which a latch in a metastable state resolves
that condition. T is a function of the measurement of the propensity
0
of a latch to enter a metastable state. T is also a normalization
constant which is a very strong function of the normal propagation
dely of the device.
0
Design Example
Suppose a designer wants to use the ABT22V10A5 for
synchronizing asynchronous data that is arriving at 10MHz (as
measured by a frequency counter), in a 5V system that has a clock
frequency of 50MHz, at an ambient temperature of 25°C. The next
device in the sytem samples the output fo the ABT22V10A5 5.5ns
after the clock edge to ensure that any metastable conditions that
occur have time to resolve to the correct state. The MTBF for this
situatio can be calcuclated by using the equation below:
In this situation, the F will be twice that data frequency, or 20MHz,
1
because input events consist of both low and high transitions. Thus
in this case F is 50MHz, F is 20MHz, τ is 85.6ps, tȀ is 5.5ns, and
C
1
T is 4.55 seconds. Using the above formula, the actual MTBF for
0
12
this situation is 1.76 × 10 seconds, or 55,889 years for the
ABT22V10A5.
MTBF = e(tȀ/τ)/T0FCF1
Table 1. Typical Values for τ and T at various V ’s and Temperatures
0
CC
0°C
+25°C
+75°C
τ
T
0
τ
T
0
τ
T
0
V
CC
5.25V
5.00V
4.75V
72.00ps
72.80ps
68.70ps
7.20E+01
2.06E+02
9.97E+03
96.70ps
85.60ps
81.70ps
4.59E–01
4.55E+00
4.85E+01
105.00ps
100.00ps
99.80ps
1.43E–01
8.37E–01
1.29E+00
7
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
LOGIC DIAGRAM
CLK/I0
2
1, 28
V
CC
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
AR
0
1
1
1
0
0
0
1
0
1
AR
D
27 F9
26 F8
25 F7
24 F6
23 F5
21 F4
20 F3
19 F2
18 F1
17 F0
Q
Q
9
SP
0
1
10
20
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
0
1
I1
I2
I3
I4
I5
I6
3
4
5
6
7
9
21
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
33
34
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
48
49
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
65
66
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
82
83
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
97
98
0
1
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
110
0
1
I7 10
111
121
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
0
1
I8 11
122
130
1
1
0
0
0
1
0
1
AR
D
Q
Q
SP
0
1
I9 12
SP
131
16 I11
I10 13
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
GND 14, 15, 8, 22
NOTE:
SP00390
Programmable connection.
8
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
FUNCTIONAL DIAGRAM
CLK/I0
I1 – I11
1
11
PROGRAMMABLE AND ARRAY
(44 × 132)
8
10
12
14
16
16
14
12
10
8
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
RESET
PRESET
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
SP00060
Figure 1. Functional Diagram
registered output or combinatorial I/O, Active-HIGH or Active-LOW
(see Figure 2). The configuration choice is made according to the
user’s design specification and corresponding programming of the
FUNCTIONAL DESCRIPTION
The ABT22V10A allows the systems engineer to implement the
design on-chip, by opening fuse links to configure AND and OR
gates within the device, according to the desired logic function.
configuration bits S –S . Multiplexer controls are connected to
0
1
ground (0) through a programmable fuse link, selecting the “0” path
through the multiplexer. Programming the fuse disconnects the
Product terms with all fuses opened assume the logical HIGH state;
product terms connected to both True and Complement of any
single input assume the logical LOW state.
control line from GND and it floats to V (1), selecting the “1” path.
CC
The ABT22V10A has 12 inputs and 10 I/O Macro Cells (Figure 1).
The Macro Cell allows one of four potential output configurations,
9
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
OUTPUT MACRO CELL
S
S
OUTPUT CONFIGURATION
Registered/Active-LOW
1
0
1
1
0
0
0
1
0
1
0
0
1
1
0
AR
1
0
1
Registered/Active-HIGH
Combinatorial/Active-LOW
Combinatorial/Active-HIGH
D
Q
F
CLK
Q
0 = Unprogrammed fuse
1 = Programmed fuse
SP
S
1
S
0
0
1
SP00375
Figure 2. Output Macro Cell Logic Diagram
S
S
= 0
= 0
S
S
= 0
= 1
0
1
0
1
AR
D
Q
F
F
CLK
Q
SP
a. Registered/Active-LOW
c. Combinatorial/Active-LOW
S
S
= 1
= 0
S
S
= 1
= 1
0
1
0
1
AR
D
Q
Q
F
F
CLK
SP
b. Registered/Active-HIGH
d. Combinatorial/Active-HIGH
Figure 3. Output Macro Cell Configurations
SP00376
Registered Output Configuration
Variable Input/Output Pin Ratio
Each Macro Cell of the ABT22V10A includes a D-type flip-flop for
data storage and synchronization. The flip-flop is loaded on the
LOW-to-HIGH transition of the clock input. In the registered
The ABT22V10A has twelve dedicated input lines, and each Macro
Cell output can be an I/O pin. Buffers for device inputs have
complementary outputs to provide user-programmable input signal
polarity.
configuration (S = 0), the array feedback is from Q of the flip-flop.
1
Combinatorial I/O Configuration
Any Macro Cell can be configured as combinatorial by selecting the
multiplexer path that bypasses the flip-flop (S = 1). In the
1
combinatorial configuration, the feedback is from the pin.
10
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
SWITCHING WAVEFORMS
V = 1.5V.
T
Input pulse amplitude 0V to 3.0V.
Input rise and fall times 1.5ns max.
INPUT OR
FEEDBACK
INPUT OR
FEEDBACK
V
V
T
T
t
t
t
H
PD
S
COMBINATORIAL
OUTPUT
CLOCK
V
V
T
T
t
CO
REGISTERED
OUTPUT
V
T
Combinatorial Output
Registered Output
CLK
t
+ t
CF
S
t
S
LOGIC
REGISTER
CLOCK
V
T
t
CF
Clock to Feedback (f
Internal)
MAX
(See Path at Right)
Clock to Feedback
INPUT
V
T
t
WH
t
t
EA
ER
CLOCK
V
T
V
– 0.5V
+ 0.5V
OH
OUTPUT
V
T
V
OL
t
WL
Clock Width
Input to Output Disable/Enable
t
ARW
INPUT ASSERTING
ASYNCHRONOUS
RESET
INPUT ASSERTING
SYNCHRONOUS
PRESET
V
T
V
T
t
t
t
t
SPR
AR
S
H
REGISTERED
OUTPUT
CLOCK
V
V
V
T
T
T
t
t
ARR
CO
REGISTERED
OUTPUT
CLOCK
V
V
T
T
Asynchronous Reset
Synchronous Preset
SP00377
11
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
“AND” ARRAY – (I, B)
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
I, B
P, D
P, D
P, D
P, D
STATE
CODE
STATE
CODE
STATE
COMPLEMENT
CODE
STATE
CODE
1
O
TRUE
H
L
DON’T CARE
—
INACTIVE
SP00008
NOTE:
1. This is the initial state.
PRELOAD SET-UP
SYMBOL
LIMITS
REC
9.5
PARAMETER
UNIT
MIN
MAX
10
V
V
V
Super-level input voltage
9.5
0
V
V
HH
ILH
IHP
Low-level input voltage
High-level input voltage
Delay time
0
0.8
2.4
100
100
5.0
5.5
V
t
t
200
1000
ns
ns
D
I/O valid after Pin 2 or 3 drops from V to V
ILP
I/O
HH
V
V
HH
ILP
PINS 2, 3
t
I/O
t
D
t
D
V
V
V
V
IHP
OH
OL
REGISTERED
OUTPUTS
DATA IN
DATA OUT
ILP
t
D
t
D
V
V
IHP
ILP
CLOCK
t
D
Output Register Preload Waveform
SP00373
12
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
of the power-up reset and the wide range of ways V can rise to its
steady state, two conditions are required to ensure a valid power-up
reset. These conditions are:
POWER-UP RESET
CC
The power-up reset feature ensures that all flip-flops will be reset to
LOW after the device has been powered up. The output state will
depend on the programmed pattern. This feature is valuable in
simplifying state machine initialization. A timing diagram and
parameter table are shown below. Due to the synchronous operation
1. The V rise must be monotonic.
CC
2. Following reset, the clock input must not be driven from LOW to
HIGH until all applicable input and feedback setup times are met.
LIMITS
UNIT
SYMBOL
PARAMETER
MIN
MAX
t
t
t
Power-up Reset Time
1
µs
PR
Input or Feedback Setup Time
Clock Width LOW
S
See AC Electrical Characteristics
WL
V
CC
4V
POWER
t
PR
REGISTERED
ACTIVE-LOW
OUTPUT
t
S
CLOCK
t
WL
Power-Up Reset Waveform
SP00066
OTHER PHILIPS 22V10 DEVICES
Philips offers a complete family of 22V10 devices, addressing a wide
variety of design applications. This Features Matrix summarizes the
basic features of each specific device.
PHILIPS 22V10 FEATURES MATRIX
PL22V10-10/-15
LVT22V10-7
ABT22V10-7
+4.75 to +5.25V
No
ABT22V10A5
ABT22V10A7
1
Operating supply voltage
Live Insertion
+4.75 to +5.25V
+3.0 to +3.6V
Yes
+4.75 to +5.25V
+4.75 to +5.25V
No
No
Yes
Yes
Yes
Yes
Dual Verify
Yes
No
Metastability
No
Hardened
Immune
No
No
Source Drive Capability
4mA
(V = 2.4V)
OH
16mA
(V = 2.0V)
OH
16mA
(V = 2.4V)
OH
16mA
(V = 2.4V)
OH
16mA
(V = 2.4V)
OH
Sink Drive Capability
16mA
(V = 0.5V)
OL
32mA
(V = 0.5V)
OL
48mA
(V = 0.5V)
OL
48mA
(V = 0.5V)
OL
48mA
(V = 0.5V)
OL
Low Ground Bounce
No
Yes
Yes
Yes
Yes
Package Availability:
Plastic Dual In-Line (N)
Plastic Leaded Chip Carrier (A)
24-Pin
24-Pin
24-Pin
24-Pin
28-Pin
24-Pin
24-Pin
28-Pin
not available
28-Pin
not available
28-Pin
Plastic Small Outline Large (D)
not available
not available
not available
NOTE:
1. 5 volt compatible I/O. Inputs are capable of handling 7V and the outputs can also be pulled up to 7 volts.
13
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
ABT22V10A5 TIMING CHARACTERIZATION
Normalized t
vs Temperature
Normalized t vs Temperature
PD
(V = 5.0V, output capacitance = 50pF, 5 outputs switching)
CC
CO
(V = 5.0V, output capacitance = 50pF, 5 outputs switching)
CC
1.10
1.10
1.00
1.00
0.90
0.90
RISE
FALL
RISE
FALL
0.80
0.80
0
25
50
75
0
25
50
75
Temperature (°C)
Temperature (°C)
Normalized tCO vs VCC
(temp = 25°C, output capacitance = 50pF, 5 outputs switching)
Normalized tPD vs VCC
(temp = 25°C, output capacitance = 50pF, 5 outputs switching)
1.10
1.10
1.05
1.00
0.95
1.05
1.00
0.95
RISE
FALL
RISE
FALL
0.90
0.90
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
Supply Voltage (V)
Supply Voltage (V)
The timing characterization represents the average values of a representative sample for each parameter.
The data can be used to derate the MAX AC CHARACTERIZATION based upon the specific user design.
Philips guarantees the MAX AC CHARACTERIZATION specifications.
SP00370
14
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
ABT22V10A5 TIMING CHARACTERIZATION
Delta t vs Number of Outputs Switching
(V = 5.0V, temp = 25°C, output capacitance = 50pF)
Delta t vs Number of Outputs Switching
PD
(V = 5.0V, temp = 25°C, output capacitance = 50pF)
CO
CC
CC
0.20
0.20
0.0
0.0
–0.20
–0.20
–0.40
–0.60
–0.40
–0.60
–0.80
–1.00
–0.80
–1.00
–1.20
–1.20
–1.40
–1.60
–1.80
–1.40
–1.60
–1.80
RISE
FALL
RISE
FALL
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
Number of Outputs Switching
Number of Outputs Switching
Delta t vs Output Capacitance
(V = 5.0V, temp = 25°C, 5 Outputs Switching)
Delta t vs Output Capacitance
PD
(V = 5.0V, temp = 25°C, 5 Outputs Switching)
CO
CC
CC
4.50
3.50
4.50
3.50
2.50
1.50
0.50
2.50
1.50
0.50
–0.50
–1.50
–0.50
–1.50
RISE
FALL
RISE
FALL
10
50
100
200
400
10
50
100
200
400
Output Capacitance
Output Capacitance
The timing characterization represents the average values of a representative sample for each parameter.
The data can be used to derate the MAX AC CHARACTERIZATION based upon the specific user design.
Philips guarantees the MAX AC CHARACTERIZATION specifications.
SP00371
15
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
PLCC28: plastic leaded chip carrer; 28 leads; pedestal
SOT261-3
16
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
NOTES
17
1996 Dec 16
Philips Semiconductors
Product specification
5V high-speed universal PLD device
with live insertion capability
ABT22V10A5, A7
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.
Philips
Semiconductors
相关型号：
ABT6F150C0
Mains Power Connector, 10/15A, 125/250VAC, Male, Solder Terminal, ROHS COMPLIANT
SCHURTER
ABT6FC00C0
Mains Power Connector, 10/15A, 125/250VAC, Male, Solder Terminal, ROHS COMPLIANT
SCHURTER
©2020 ICPDF网 联系我们和版权申明