ADC0804-1LCN_技术文档

INTEGRATED CIRCUITS

ADC0803/0804

CMOS 8-bit A/D converters

Product data

2002 Oct 17

Supersedes data of 2001 Aug 03

Philips

Semiconductors

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

DESCRIPTION

PIN CONFIGURATION

The ADC0803 family is a series of three CMOS 8-bit successive

approximation A/D converters using a resistive ladder and

capacitive array together with an auto-zero comparator. These

converters are designed to operate with microprocessor-controlled

buses using a minimum of external circuitry. The 3-State output data

lines can be connected directly to the data bus.

D

N PACKAGES

,

1

2

20

19

18

17

16

15

CS

RD

V

CC

CLK R

D0

3

WR

4

The differential analog voltage input allows for increased

common-mode rejection and provides a means to adjust the

zero-scale offset. Additionally, the voltage reference input provides a

means of encoding small analog voltages to the full 8 bits of

resolution.

CLK IN

D1

D2

D3

5

INTR

6

V

(+)

(–)

IN

7

14 D4

D5

13

8

A GND

9

12 D6

V

/2

REF

FEATURES

D7

11

10

D GND

• Compatible with most microprocessors

TOP VIEW

• Differential inputs

SL00016

• 3-State outputs

Figure 1. Pin configuration

• Logic levels TTL and MOS compatible

• Can be used with internal or external clock

APPLICATIONS

• Analog input range 0 V to V

CC

• Transducer-to-microprocessor interface

• Digital thermometer

• Single 5 V supply

• Guaranteed specification with 1 MHz clock

• Digitally-controlled thermostat

• Microprocessor-based monitoring and control systems

ORDERING INFORMATION

TEMPERATURE

DESCRIPTION

RANGE

ORDER CODE

ADC0803CD, ADC0804CD

TOPSIDE MARKING

DWG #

20-pinplastic small outline (SO) package

20-pin plastic dual in-line package (DIP)

0 to 70 °C

–40 to 85 °C

0 to 70 °C

ADC0803-1CD, ADC0804-1CD

SOT163-1

ADC0803LCD, ADC0804LCD ADC0803-1LCD, ADC0804-1LCD SOT163-1

ADC0803CN, ADC0804CN ADC0803-1CN, ADC0804-1CN SOT146-1

ADC0803LCN, ADC0804LCN ADC0803-1LCN, ADC0804-1LCN SOT146-1

–40 to +85 °C

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

CONDITIONS

RATING

6.5

UNIT

V

CC

Supply voltage

V

Logic control input voltages

All other input voltages

Operating temperature range

–0.3 to +16

–0.3 to (V +0.3)

CC

T

amb

ADC0803LCD/ADC0804LCD

ADC0803LCN/ADC0804LCN

ADC0803CD/ADC0804CD

ADC0803CN/ADC0804CN

–40 to +85

0 to +70

°C

0 to +70

T

Storage temperature

–65 to +150

230

°C

stg

T

sld

Lead soldering temperature (10 seconds)

1

P

D

Maximum power dissipation

T

amb

= 25 °C (still air)

N package

D package

1690

1390

mW

NOTE:

1. Derate above 25 °C, at the following rates: N package at 13.5 mW/°C; D package at 11.1 mW/°C.

2

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

BLOCK DIAGRAM

V

(+)

6

V

(–)

7

IN

+

–

+

9

V

/2

REF

AUTO ZERO

COMPARATOR

LADDER AND

DECODER

8

A GND

–

20

D7 (MSB) (11)

V

CC

D6

D5

D4

(12)

(13)

(14)

OUTPUT

LATCHES

D3

D2

D1

(15)

(16)

(17)

SAR

D0 (LSB) (18)

10

3

D GND

WR

LE

OE

8–BIT

SHIFT REGISTER

CLOCK

1

2

CS

RD

S

INTR

FF

R

Q

5

4

CLK IN

19

INTR

CLK R

SL00017

Figure 2. Block diagram

3

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

DC ELECTRICAL CHARACTERISTICS

V

CC

= 5.0 V, f

= 1 MHz, T

≤ T

, unless otherwise specified.

CLK

min

amb

max

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

Min

Typ

Max

0.50

1

ADC0803 relative accuracy error (adjusted)

Full-Scale adjusted

LSB

Ω

ADC0804 relative accuracy error (unadjusted)

V

REF

/2 = 2.500 V

DC

3

2

R

V

REF

/2 input resistance

V = 0 V

CC

400

680

IN

3

Analog input voltage range

DC common-mode error

Power supply sensitivity

–0.05

V

CC

+0.05

V

Over analog input voltage range

1/16

1/8

LSB

1

V

CC

= 5V ±10%

Control inputs

V

Logical “1” input voltage

Logical “0” input voltage

Logical “1” input current

Logical “0” input current

V

= 5.25 V

= 4.75 V

2.0

–1

15

0.8

1

V

IH

IL

CC

DC

V

CC

DC

I

IH

I

IL

V

= 5 V

= 0 V

0.005

µA

IN

DC

–0.005

DC

Clock in and clock R

V +

Clock in positive-going threshold voltage

Clock in negative-going threshold voltage

2.7

1.5

0.6

3.1

1.8

1.3

3.5

2.1

2.0

0.4

V

T

DC

V –

T

V

Clock in hysteresis (V +)–(V –)

T T

H

Logical “0” clock R output voltage

Logical “1” clock R output voltage

I

= 360 µA, V = 4.75 V

OL

OH

OL CC DC

I

= –360 µA, V = 4.75 V

DC

2.4

OH

CC

Data output and INTR

V

OL

Logical “0” output voltage

Data outputs

I

= 1.6 mA, V = 4.75 V

0.4

V

OL

CC

DC

INTR outputs

= 1.0 mA, V = 4.75 V

CC DC

OL

DC

= –360 µA, V = 4.75 V

2.4

4.5

–3

OH

CC

DC

V

OH

Logical “1” output voltage

V

DC

I

= –10 µA, V = 4.75 V

CC

OH

I

3-State output leakage

V

= 0 V , CS = logical “1”

µA

OZL

OZH

SC

OUT

DC

3-State output leakage

= 5 V , CS = logical “1”

3

DC

+Output short-circuit current

–Output short-circuit current

V

= 0 V, T

= 25 °C

4.5

9.0

12

30

mA

OUT

amb

DC

V

= V , T

CC amb

mA

SC

OUT

f

= 1 MHz, V

/2 = OPEN,

REF

CLK

I

Power supply current

3.0

3.5

mA

CC

CS = Logical “1”, T

= 25 °C

amb

NOTES:

1. Analog inputs must remain within the range: –0.05 ≤ V ≤ V + 0.05 V.

IN

CC

2. See typical performance characteristics for input resistance at V = 5 V.

CC

3. V

/2 and V must be applied after the V has been turned on to prevent the possibility of latching.

REF

IN CC

4

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

AC ELECTRICAL CHARACTERISTICS

LIMITS

UNIT

SYMBOL

PARAMETER

TO

FROM

TEST CONDITIONS

Min

66

Typ

Max

1

Conversion time

f

= 1 MHz

73

µs

MHz

%

CLK

1

f

Clock frequency

0.1

40

1.0

3.0

60

CLK

Clock duty cycle

CS = 0, f

INTR tied to WR

= 1 MHz

CLK

CR

Free-running conversion rate

13690 conv/s

ns

t

WR)L

Start pulse width

Access time

CS = 0

30

W(

Output

RD

CS = 0, C = 100 pF

75

70

100

ns

ACC

L

C = 10 pF, R = 10 kΩ

L

t , t

1H 0H

3-State control

INTR delay

100

ns

See 3-State test circuit

WD

or RD

t

, t

INTR

100

150

ns

W1 R1

C

Logic input=capacitance

5

7.5

pF

IN

3-State output capacitance

OUT

NOTE:

1. Accuracy is guaranteed at f

= 1 MHz. Accuracy may degrade at higher clock frequencies.

CLK

FUNCTIONAL DESCRIPTION

ANALOG OPERATION

Analog Input Current

These devices operate on the Successive Approximation principle.

Analog switches are closed sequentially by successive

approximation logic until the input to the auto-zero comparator

[ V (+)–V (–) ] matches the voltage from the decoder. After all bits

The analog comparisons are performed by a capacitive charge

summing circuit. The input capacitor is switched between V

4

IN(+)

IN

and V

, while reference capacitors are switched between taps on

are tested and determined, the 8-bit binary code corresponding to

the input voltage is transferred to an output latch. Conversion begins

with the arrival of a pulse at the WR input if the CS input is low. On

the High-to-Low transition of the signal at the WR or the CS input,

the SAR is initialized, the shift register is reset, and the INTR output

is set high. The A/D will remain in the reset state as long as the CS

and WR inputs remain low. Conversion will start from one to eight

clock periods after one or both of these inputs makes a Low-to-High

transition. After the conversion is complete, the INTR pin will make a

High-to-Low transition. This can be used to interrupt a processor, or

otherwise signal the availability of a new conversion result. A read

(RD) operation (with CS low) will clear the INTR line and enable the

output latches. The device may be run in the free-running mode as

described later. A conversion in progress can be interrupted by

issuing another start command.

IN(–)

the reference voltage divider string. The net charge corresponds to

the weighted difference between the input and the most recent total

value set by the successive approximation register.

The internal switching action causes displacement currents to flow

at the analog inputs. The voltage on the on-chip capacitance is

switched through the analog differential input voltage, resulting in

proportional currents entering the V

input. These transient currents occur at the leading edge of the

internal clock pulses. They decay rapidly so do not inherently cause

errors as the on-chip comparator is strobed at the end of the clock

period.

input and leaving the V

IN(–)

IN(+)

Input Bypass Capacitors and Source Resistance

Bypass capacitors at the input will average the charges mentioned

above, causing a DC and an AC current to flow through the output

resistance of the analog signal sources. This charge pumping action

Digital Control Inputs

The digital control inputs (CS, WR, RD) are compatible with

standard TTL logic voltage levels. The required signals at these

inputs correspond to Chip Select, START Conversion, and Output

Enable control signals, respectively. They are active-Low for easy

interface to microprocessor and microcontroller control buses. For

applications not using microprocessors, the CS input (Pin 1) can be

grounded and the A/D START function is achieved by a

negative-going pulse to the WR input (Pin 3). The Output Enable

function is achieved by a logic low signal at the RD input (Pin 2),

which may be grounded to constantly have the latest conversion

present at the output.

is worse for continuous conversions with the V

scale. This current can be a few microamps, so bypass capacitors

should NOT be used at the analog inputs of the V /2 input for

high resistance sources (> 1 kΩ). If input bypass capacitors are

desired for noise filtering and a high source resistance is desired to

minimize capacitor size, detrimental effects of the voltage drop

across the input resistance can be eliminated by adjusting the full

scale with both the input resistance and the input bypass capacitor

in place. This is possible because the magnitude of the input current

is a precise linear function of the differential voltage.

input at full

IN(+)

REF

5

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

Large values of source resistance where an input bypass capacitor

is not used will not cause errors as the input currents settle out prior

to the comparison time. If a low pass filter is required in the system,

use a low valued series resistor (< 1 kΩ) for a passive RC section or

add an op amp active filter (low pass). For applications with source

resistances at or below 1 kΩ, a 0.1 µF bypass capacitor at the inputs

will prevent pickup due to series lead inductance or a long wire. A

100 Ω series resistor can be used to isolate this capacitor (both the

resistor and capacitor should be placed out of the feedback loop)

from the output of the op amp, if used.

Reference Voltage Span Adjust

Note that the Pin 9 (V

/2) voltage is either 1/2 the voltage applied

REF

to the V supply pin, or is equal to the voltage which is externally

CC

forced at the V

/2 pin. In addition to allowing for flexible

REF

references and full span voltages, this also allows for a ratiometric

voltage reference. The internal gain of the V /2 input is 2, making

the full-scale differential input voltage twice the voltage at Pin 9.

REF

For example, a dynamic voltage range of the analog input voltage

that extends from 0 to 4 V gives a span of 4 V (4–0), so the V

voltage can be made equal to 2 V (half of the 4 V span) and full

scale output would correspond to 4 V at the input.

/2

REF

Analog Differential Voltage Inputs and

Common-Mode Rejection

On the other hand, if the dynamic input voltage had a range of

0.5 to 3.5 V, the span or dynamic input range is 3 V (3.5–0.5). To

encode this 3 V span with 0.5 V yielding a code of zero, the

These A/D converters have additional flexibility due to the analog

differential voltage input. The V

input (Pin 7) can be used to

IN(–)

minimum expected input (0.5 V, in this case) is applied to the V (–)

subtract a fixed voltage from the input reading (tare correction). This

is also useful in a 4/20 mA current loop conversion. Common-mode

noise can also be reduced by the use of the differential input.

IN

pin to account for the offset, and the V /2 pin is set to 1/2 the 3 V

REF

span, or 1.5 V. The A/D converter will now encode the V (+) signal

IN

between 0.5 and 3.5 V with 0.5 V at the input corresponding to a

code of zero and 3.5 V at the input producing a full scale output

code. The full 8 bits of resolution are thus applied over this reduced

input voltage range. The required connections are shown in

Figure 7.

The time interval between sampling V

periods. The maximum error due to this time difference is given by:

and V

is 4.5 clock

IN(–)

IN(+)

V(max) = (V ) (2f ) (4.5/f ),

P

CM

CLK

where:

V = error voltage due to sampling delay

Operating Mode

These converters can be operated in two modes:

V

P

= peak value of common-mode voltage

1) absolute mode

2) ratiometric mode

f

= common mode frequency

CM

In absolute mode applications, both the initial accuracy and the

temperature stability of the reference voltage are important factors in

For example, with a 60 Hz common-mode frequency, f , and a

cm

1 MHz A/D clock, f

, keeping this error to 1/4 LSB (about 5 mV)

CLK

the accuracy of the conversion. For V /2 voltages of 2.5 V, initial

REF

would allow a common-mode voltage, V , which is given by:

P

errors of ±10 mV will cause conversion errors of ±1 LSB due to the

gain of 2 at the V /2 input. In reduced span applications, the initial

[V(max) (f_CLK

(2f_CM)(4.5)

)

V_P

+

REF

value and stability of the V /2 input voltage become even more

REF

important as the same error is a larger percentage of the V

nominal value. See Figure 8.

/2

REF

or

(5 x 10^*3) (10⁴)

(6.28) (60) (4.5)

V_P

+

+ 2.95V

In ratiometric converter applications, the magnitude of the reference

voltage is a factor in both the output of the source transducer and

the output of the A/D converter, and, therefore, cancels out in the

final digital code. See Figure 9.

The allowed range of analog input voltages usually places more

severe restrictions on input common-mode voltage levels than this,

however.

Generally, the reference voltage will require an initial adjustment.

Errors due to an improper reference voltage value appear as

full-scale errors in the A/D transfer function.

An analog input span less than the full 5 V capability of the device,

together with a relatively large zero offset, can be easily handled by

use of the differential input. (See Reference Voltage Span Adjust).

ERRORS AND INPUT SPAN ADJUSTMENTS

There are many sources of error in any data converter, some of

which can be adjusted out. Inherent errors, such as relative

accuracy, cannot be eliminated, but such errors as full-scale and

zero scale offset errors can be eliminated quite easily. See Figure 7.

Noise and Stray Pickup

The leads of the analog inputs (Pins 6 and 7) should be kept as

short as possible to minimize input noise coupling and stray signal

pick-up. Both EMI and undesired digital signal coupling to these

inputs can cause system errors. The source resistance for these

inputs should generally be below 5 kΩ to help avoid undesired noise

pickup. Input bypass capacitors at the analog inputs can create

errors as described previously. Full scale adjustment with any input

bypass capacitors in place will eliminate these errors.

Zero Scale Error

Zero scale error of an A/D is the difference of potential between the

ideal 1/2 LSB value (9.8 mV for V /2=2.500 V) and that input

REF

voltage which just causes an output transition from code 0000 0000

to a code of 0000 0001.

Reference Voltage

If the minimum input value is not ground potential, a zero offset can

be made. The converter can be made to output a digital code of

0000 0000 for the minimum expected input voltage by biasing the

For application flexibility, these A/D converters have been designed

to accommodate fixed reference voltages of 5V to Pin 20 or 2.5 V to

Pin 9, or an adjusted reference voltage at Pin 9. The reference can

V

IN

(–) input to that minimum value expected at the V (–) input to

IN

be set by forcing it at V /2 input, or can be determined by the

REF

that minimum value expected at the V (+) input. This uses the

IN

supply voltage (Pin 20). Figure 6 indicates how this is accomplished.

differential mode of the converter. Any offset adjustment should be

done prior to full scale adjustment.

6

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

Full Scale Adjustment

DRIVING THE DATA BUS

Full scale gain is adjusted by applying any desired offset voltage to

This CMOS A/D converter, like MOS microprocessors and

memories, will require a bus driver when the total capacitance of the

data bus gets large. Other circuitry tied to the data bus will add to

the total capacitive loading, even in the high impedance mode.

1

V

IN

(–), then applying the V (+) a voltage that is 1- / LSB less than

IN

2

the desired analog full-scale voltage range and then adjusting the

magnitude of V /2 input voltage (or the V supply if there is no

REF

CC

V

/2 input connection) for a digital output code which just

REF

There are alternatives in handling this problem. The capacitive

loading of the data bus slows down the response time, although DC

specifications are still met. For systems with a relatively low CPU

clock frequency, more time is available in which to establish proper

logic levels on the bus, allowing higher capacitive loads to be driven

(see Typical Performance Characteristics).

changes from 1111 1110 to 1111 1111. The ideal V (+) voltage for

this full-scale adjustment is given by:

IN

V_MAX* V_MIN

V_IN()) + V_IN(*) * 1.5 x

255

where:

At higher CPU clock frequencies, time can be extended for I/O

reads (and/or writes) by inserting wait states (8880) or using

clock-extending circuits (6800, 8035).

V

MAX

V

MIN

= high end of analog input range (ground referenced)

= low end (zero offset) of analog input (ground referenced)

Finally, if time is critical and capacitive loading is high, external bus

drivers must be used. These can be 3-State buffers (low power

Schottky is recommended, such as the N74LS240 series) or special

higher current drive products designed as bus drivers. High current

bipolar bus drivers with PNP inputs are recommended as the PNP

input offers low loading of the A/D output, allowing better response

time.

CLOCKING OPTION

The clock signal for these A/Ds can be derived from external

sources, such as a system clock, or self-clocking can be

accomplished by adding an external resistor and capacitor, as

shown in Figure 11.

Heavy capacitive or DC loading of the CLK R pin should be avoided

as this will disturb normal converter operation. Loads less than 50pF

are allowed. This permits driving up to seven A/D converter CLK IN

pins of this family from a single CLK R pin of one converter. For

larger loading of the clock line, a CMOS or low power TTL buffer or

PNP input logic should be used to minimize the loading on the CLK

R pin.

POWER SUPPLIES

Noise spikes on the V line can cause conversion errors as the

CC

internal comparator will respond to them. A low inductance filter

capacitor should be used close to the converter V pin and values

of 1 µF or greater are recommended. A separate 5 V regulator for

the converter (and other 5 V linear circuitry) will greatly reduce

CC

digital noise on the V supply and the attendant problems.

CC

Restart During a Conversion

WIRING AND LAYOUT PRECAUTIONS

A conversion in process can be halted and a new conversion began

by bringing the CS and WR inputs low and allowing at least one of

them to go high again. The output data latch is not updated if the

conversion in progress is not completed; the data from the

previously completed conversion will remain in the output data

latches until a subsequent conversion is completed.

Digital wire-wrap sockets and connections are not satisfactory for

breadboarding this (or any) A/D converter. Sockets on PC boards

can be used. All logic signal wires and leads should be grouped or

kept as far as possible from the analog signal leads. Single wire

analog input leads may pick up undesired hum and noise, requiring

the use of shielded leads to the analog inputs in many applications.

Continuous Conversion

A single-point analog ground separate from the logic or digital

ground points should be used. The power supply bypass capacitor

and the self-clocking capacitor, if used, should be returned to digital

To provide continuous conversion of input data, the CS and RD

inputs are grounded and INTR output is tied to the WR input. This

INTR/WR connection should be momentarily forced to a logic low

upon power-up to insure circuit operation. See Figure 10 for one

way to accomplish this.

ground. Any V /2 bypass capacitor, analog input filter capacitors,

REF

and any input shielding should be returned to the analog ground

point. Proper grounding will minimize zero-scale errors which are

present in every code. Zero-scale errors can usually be traced to

improper board layout and wiring.

7

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

the NE5521 data sheet for a complete description of the operation of

that part.

APPLICATIONS

Microprocessor Interfacing

Circuit Adjustment

This family of A/D converters was designed for easy microprocessor

interfacing. These converters can be memory mapped with

appropriate memory address decoding for CS (read) input. The

active-Low write pulse from the processor is then connected to the

WR input of the A/D converter, while the processor active-Low read

pulse is fed to the converter RD input to read the converted data. If

the clock signal is derived from the microprocessor system clock,

the designer/programmer should be sure that there is no attempt to

read the converter until 74 converter clock pulses after the start

pulse goes high. Alternatively, the INTR pin may be used to interrupt

the processor to cause reading of the converted data. Of course, the

converter can be connected and addressed as a peripheral (in I/O

space), as shown in Figure 12. A bus driver should be used as a

buffer to the A/D output in large microprocessor systems where the

data leaves the PC board and/or must drive capacitive loads in

excess of 100 pF. See Figure 14.

To adjust the full scale and zero scale of the A/D, determine the range

of voltages that the transducer interface output will take on. Set the

LVDT core for null and set the Zero Scale Scale Adjust Potentiometer

for a digital output from the A/D of 1000 000. Set the LVDT core for

maximum voltage from the interface and set the Full Scale Adjust

potentiometer so the A/D output is just barely 1111 1111.

A Digital Thermostat

Circuit Description

The schematic of a Digital Thermostat is shown in Figure 16. The

A/D digitizes the output of the LM35, a temperature transducer IC

with an output of 10 mV per °C. With V

/2 set for 2.56 V, this

REF

10 mV corresponds to 1/2 LSB and the circuit resolution is 2 °C.

Reducing V /2 to 1.28 yields a resolution of 1 °C. Of course, the

REF

lower V /2 is, the more sensitive the A/D will be to noise.

REF

Interfacing the SCN8048 microcomputer family is pretty simple, as

shown in Figure 13. Since the SCN8048 family has 24 I/O lines, one

of these (shown here as bit 0 or port 1) can be used as the chip

select signal to the converter, eliminating the need for an address

decoder. The RD and WR signals are generated by reading from

and writing to a dummy address.

The desired temperature is set by holding either of the set buttons

closed. The SCC80C451 programming could cause the desired

(set) temperature to be displayed while either button is depressed

and for a short time after it is released. At other times the ambient

temperature could be displayed.

The set temperature is stored in an SCN8051 internal register. The

A/D conversion is started by writing anything at all to the A/D with

port pin P10 set high. The desired temperature is compared with the

digitized actual temperature, and the heater is turned on or off by

clearing setting port pin P12. If desired, another port pin could be

used to turn on or off an air conditioner.

Digitizing a Transducer Interface Output

Circuit Description

Figure 15 shows an example of digitizing transducer interface output

voltage. In this case, the transducer interface is the NE5521, an

LVDT (Linear Variable Differential Transformer) Signal Conditioner.

The diode at the A/D input is used to insure that the input to the A/D

does not go excessively beyond the supply voltage of the A/D. See

The display drivers are NE587s if common anode LED displays are

used. Of course, it is possible to interface to LCD displays as well.

8

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

TYPICAL PERFORMANCE CHARACTERISTICS

Power Supply Current vs

Temperature

Clock Frequency vs

Clock Capacitor

Input Current vs

Applied Voltage at V

REF/2

3.2

3.0

10.0

5

8.0

6.0

V

T

= 5.0 V

CC

o

4

3

f

= 1 MHz

= 25

C

CLK

amb

CS = H

4.0

2.8

2.6

2.4

2

1

2.0

MAX.

5.5 V

5.0 V

4.5 V

1.0

0.8

0.6

0

–1

–2

–3

–4

0.4

2.2

2.0

TYP.

0.2

MIN.

–5

0.1

1.8

10

20

40 60 80100 200 400 6001000

CLOCK CAP (pF)

5

–50 –25

0

25 50 75 100 125

0

1

2

3

4

APPLIED V

(V)

AMBIENT TEMPERATURE (°C)

REF/2

Output Current vs

Temperature

Logic Input Threshold

Voltage vs Supply Voltage

CLK–IN Threshold Voltage vs

Supply Voltage

4.5

4.0

18

–55 °C ≤ T

≤ 125 °C

amb

V

= 5.0 V

1.70

CC

–55 °C

16

14

3.5

V

+25 °C

1.60

1.50

T+

3.0

2.5

2.0

+125 °C

V

= 2.5 V

12

10

O

V

T

1.40

1.30

V

= 0.4 V

O

8

6

1.5

1.0

4.50

4.75

5.00

5.25

5.50

–50 –25

0

25

50

75 100 125

o

4.50

4.75

V

5.00

5.25

5.50

AMBIENT TEMPERATURE ( C)

V

SUPPLY VOLTAGE (V)

CC

Delay From RD Falling

Edge to Data Valid vs

Load Capacitance

Full Scale Error vs

Conversion Time

4

350

V

= 5.0 V

V

= 5.0 V

CC

300

o

V

T

= 25 C

REF/2 = 2.5 V

amb

3

2

250

200

150

100

50

0

1

0

200

400

600

800

1000

0

20

40

60

80

100 120

CONVERSION TIME (µs)

LOAD CAPACITANCE (pF)

SL00018

Figure 3. Typical Performance Characteristics

9

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

3-STATE TEST CIRCUITS AND WAVEFORMS (ADC0801-1)

20ns

V

CC

V

CC

t

r

t

r

V

CC

90%

RD

50%

10%

50%

RD

DATA

OUTPUT

GND

10%

CS

GND

10 kΩ

t

1H

t

0H

RD

DATA

OUTPUT

C

V

10 kΩ

V

L

OH

CS

OH

90%

10 pF

DATA

OUTPUT

DATA

OUTPUT

C

L

10%

10 pF

GND

t

1H

t

OH

SL00019

Figure 4. 3-State Test Circuits and Waveforms (ADC0801-1)

TIMING DIAGRAMS (All timing is measured from the 50% voltage points)

START

CONVERSION

CS

WR

t

WI

t

W(WR)L

”BUSY”

DATA IS VALID IN

OUTPUT LATCHES

ACTUAL INTERNAL

STATUS OF THE

CONVERTER

”NOT BUSY”

1 TO 8 X 1/f

INTERNAL T

C

(LAST DATA WAS READ)

CLK

INTR

(LAST DATA WAS NOT READ)

INT ASSERTED

1/2 T

CLK

INTR RESET

INTR

CS

t

RI

RD

NOTE

DATA

THREE–STATE

OUTPUTS

t

ACC

t

1H, 0H

Output Enable and Reset INTR

) after assertion of interrupt to guarantee reset of INTR.

Figure 5. Timing Diagrams

NOTE:

Read strobe must occur 8 clock periods (8/f

SL00020

CLK

10

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

V

CC

(5V)

V

20

REF

R

9

–

+

V

/2

REF

330 Ω

TO V

/2

REF

FS

OFFSET

ADJUST

0.1 µF

DIGITAL

CIRCUITS

ZS

OFFSET

ADJUST

ANALOG

CIRCUITS

TO V (–)

IN

R

SL00022

Figure 7. Offsetting the Zero Scale and Adjusting the Input

Range (Span)

8

10

NOTE:

The V

/2 voltage is either 1/2 the V voltage or is that which is forced at Pin 9.

CC

REF

SL00021

Figure 6. Internal Reference Design

+5V

V

CC

+

V

(+)

(–)

IN

V

CC

10 µF

2 kΩ

+

V

(+)

IN

A/D

10 µF

2 kΩ

100 Ω

2 kΩ

A/D

V

/2

REF

IN

VOLTAGE

REFERENCE

/2

V

/2

REF

V

(–)

V

IN

REF

a. Fixed Reference

b. Fixed Reference Derived from V

CC

c. Optional Full

Scale Adjustment

SL00023

Figure 8. Absolute Mode of Operation

11

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

V

CC

V

(+)

V

CC

IN

+

TRANSDUCER

10µF

2 kΩ

A/D

FULL SCALE

OPTIONAL

100 Ω

V

/2

REF

V

(–)

IN

2 kΩ

SL00024

Figure 9. Ratiometric Mode of Operation with Optional Full

Scale Adjustment

10k

+5 V

V

CC

20

CS

RD

1

2

19 CLK R

18 D0

WR

3

DB0

10 kΩ

17 D1

16 D2

2.7 kΩ

CLK IN

INTR

4

5

DB1

DB2

A/D

6

7

8

15 D3

14 D4

V

(+)

IN

DB3

DB4

10 kΩ

47 µF TO

100 µF

V

(–)

IN

56 pF

13 D5

12 D6

11 D7

A GND

/2

DB5

DB6

DB7

V

9

REF

D GND 10

SL00025

Figure 10. Connection for Continuous Conversion

INT

CLK R

R

19

I/O WR

I/O RD

CLK IN 4

+5 V

10 kΩ

CLK

f

= 1/1.7 R C

C

CLK

R = 10 kΩ

V

20

CS

1

2

CC

A/D

RD

19 CLK R

18 D0

SL00026

WR

3

DB0

17 D1

16 D2

CLK IN

INTR

4

5

Figure 11. Self-Clocking the Converter

DB1

DB2

A/D

15 D3

6

7

8

V

(+)

IN

DB3

DB4

ANALOG

INPUTS

14 D4

13 D5

12 D6

V

(–)

IN

A GND

DB5

DB6

DB7

56 pF

V

/2

9

REF

D GND 10

11 D7

ADDRESS

DECODE

LOGIC

SL00027

Figure 12. Interfacing to 8080A Microprocessor

12

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

+5 V

18 D0

17 D1

16 D2

15 D3

V

8–BIT

BUFFER

V

CC

40

20

19 CLK R

DATA

BUS

1

2

3

4

P1.0

P1.1

P1.2

P1.3

D0 18

D1 17

D2 16

D3 15

14 D4

13 D5

12 D6

11 D7

A/D

N74LS241

N74LS244

N74LS541

10 kΩ

4

CLK IN

5

6

7

8

P1.4

P1.5

P1.6

P1.7

D4 14

D5 13

D6 12

D7 11

56 pF

OE

SCN8051

OR

SCN80C51

A/D

V

(+)

IN

6

7

SL00029

ANALOG

INPUTS

V

/2

Figure 14. Buffering the A/D Output to Drive High Capacitance

Loads and for Driving Off-Board Loads

REF

17 RD

RD

WR

2

3

5

1

16 WR

12 INTO

39 P0.0

12 A GND

11 D GND

INTR

CS

SL00028

+5 V

Figure 13. SCN8051 Interfacing

C

t

18 kΩ

820 Ω

4.7 kΩ

1.5 kΩ

LVDT

NE5521

1µF

0.47 µF

4.7 kΩ

22 kΩ

+5 V

470 Ω

IN4148

V

CC

V

(+)

(–)

IN

3.3 kΩ

2 kΩ

100 Ω

2 kΩ

A/D

V

/2

REF

FULL SCALE

ADJUST

V

2 kΩ

IN

SL00030

Figure 15. Digitizing a Transducer Interface Output

13

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

5

RBI

6

2

1

7

3

7

8

NE587

1/4

HEF4071

RBO

RBI

4

5

10 kΩ

6

2

1

7

3

7

8

NE587

1/4

HEF4071

10 kΩ

LOWER

13

14

P15

RAISE

P16

18

17

16

15

DB0

DB1

DB2

DB3

D0 18

D1 17

D2 16

D3 15

+5 V

V

20

CC

+

10 µF

19 CLK R

14

13

12

11

DB4

DB5

DB6

DB7

D4 14

D5 13

10 kΩ

SCC80C51

D6 12

D7 11

A/D

4

CLK IN

56 pF

8

10

6

RD

WR

INT

P10

RD

WR

2

3

5

1

V

(+)

(–)

6

7

IN

INTR

CS

LM35

27

D GND 10

8

AGND

29 P12 20 GND

+V

2N3906

1N4148

TO HEATER

SL00031

Figure 16. Digital Thermostat

14

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

15

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

DIP20: plastic dual in-line package; 20 leads (300 mil)

SOT146-1

16

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

REVISION HISTORY

Rev

Date

Description

_3

20021017

Product data; third version; supersedes data of 2001 Aug 03.

Engineering Change Notice 853–0034 28949 (date: 20020916).

Modifications:

• Add “Topside Marking” column to Ordering Information table.

_2

_1

20010803

19940831

Product data; second version (9397 750 08926).

Engineering Change Notice 853–0034 26832 (date: 20010803).

Product data; initial version.

Engineering Change Notice 853–0034 13721 (date: 19940831).

17

2002 Oct 17

Philips Semiconductors

Product data

CMOS 8-bit A/D converters

ADC0803/0804

Data sheet status

Product

status

Definitions

[1]

Level

Data sheet status

[2] [3]

I

Objective data

Development

Qualification

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

II

Preliminary data

Product data

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys

nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,

copyright, or mask work right infringement, unless otherwise specified.

Koninklijke Philips Electronics N.V. 2002

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 10-02

9397 750 10538

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

18

2002 Oct 17


型号：	ADC0804-1LCN
厂家：	NXP
描述：	CMOS 8-bit A/D converters CMOS 8位A / D转换器转换器模数转换器光电二极管
文件：	总18页 (文件大小：151K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC0804-1LCN [NXP]

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