ADC1115S125 [NXP]
Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs; 单11位ADC ; 125 Msps的与输入缓冲器; CMOS或DDR LVDS数字输出型号: | ADC1115S125 |
厂家: | NXP |
描述: | Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs |
文件: | 总35页 (文件大小:267K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADC1115S125
Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS
DDR digital outputs
Rev. 01 — 12 April 2010
Preliminary data sheet
1. General description
The ADC1115S125 is a single channel 11-bit Analog-to-Digital Converter (ADC) optimized
for high dynamic performances and low power consumption at sample rates up to
125 Msps. Pipelined architecture and output error correction ensure the ADC1115S125 is
accurate enough to guarantee zero missing codes over the entire operating range.
Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in
CMOS mode, thanks to a separate digital output supply.
The ADC1115S125 supports the Low Voltage Differential Signalling (LVDS) Double Data
Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the
user to easily configure the ADC.
The device also includes a SPI programmable full-scale to allow flexible input voltage
range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the
baseband to input frequencies of 170 MHz or more, the ADC1115S125 is ideal for use in
communications, imaging and medical applications - especially in high Intermediate
Frequency (IF) applications thanks to the integrated input buffer. The input buffer ensures
that the input impedance remains constant and low and the performance consistent over
a wide frequency range.
2. Features and benefits
SNR, 66.5 dBFS / SFDR, 86 dBc
Input bandwidth, 600 MHz
Power dissipation, 840 mW including
analog input buffer
Sample rate up to 125 Msps
11-bit pipelined ADC core
Clock input divider by 2 for less jitter
contribution
SPI
Duty cycle stabilizer
Integrated input buffer
Fast OuT of Range (OTR) detection
Flexible input voltage range: 1 V (p-p) to INL ±1.25 LSB, DNL ±0.25 LSB
2 V (p-p)
CMOS or LVDS DDR digital outputs
Offset binary, two’s complement, gray
code
Pin compatible with the ADC1415S
series, the ADC1215S series and the
ADC1015S series
Power-down and Sleep modes
HVQFN40 package
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
3. Applications
Wireless and wired broadband
communications
Spectral analysis
Portable instrumentation
Imaging systems
Ultrasound equipment
Software defined radio
Digital predistortion loop, power
amplifier linearization
4. Ordering information
Table 1.
Ordering information
Type number
fs (Msps) Package
Name
Description
Version
ADC1115S125HN/C1 125
HVQFN40 plastic thermal enhanced very thin quad flat package;
SOT618-6
no leads; 40 terminals; body 6 × 6 × 0.85 mm
5. Block diagram
SDIO/ODS
SCLK/DFS
CS
ADC1115S
ERROR
CORRECTION AND
DIGITAL
SPI
PROCESSING
OTR
CMOS:
D10 to D0
or
LVDS/DDR:
D10P, D10M
to D0P, D0M
INP
INM
S/H
INPUT
STAGE
ADC CORE
11-BIT
PIPELINED
INPUT
BUFFER
OUTPUT
DRIVERS
CMOS:
DAV
or
OUTPUT
DRIVERS
LVDS/DDR:
DAVP
DAVM
SYSTEM
REFERENCE AND
POWER
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
PWD
OE
MANAGEMENT
VREF
REFB
CLKP CLKM
VCM SENSE REFT
005aaa146
Fig 1. Block diagram
ADC1115S125_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
2 of 35
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
6. Pinning information
6.1 Pinning
terminal 1
index area
terminal 1
index area
1
2
30
29
28
27
26
25
24
23
22
21
REFB
REFT
n.c.
1
2
30
29
28
27
26
25
24
23
22
21
REFB
REFT
n.c.
n.c.
n.c.
D0
D1
D2
D3
D4
D5
D6
n.c.
3
AGND
VCM
LOW_D0_P
LOW_D0_M
D1_D2_P
D1_D2_M
D3_D4_P
D3_D4_M
D5_D6_P
D5_D6_M
3
4
AGND
VCM
4
5
VDDA5V
AGND
INM
ADC1115S
HVQFN40
5
6
VDDA5V
AGND
INM
ADC1115S
HVQFN40
6
7
7
8
INP
8
9
INP
AGND
VDDA3V
9
10
AGND
VDDA3V
10
005aaa148
005aaa147
Transparent top view
Transparent top view
Fig 2. Pin configuration with CMOS digital outputs
selected
Fig 3. Pin configuration with LVDS/DDR digital
outputs selected
6.2 Pin description
Table 2.
Symbol
REFB
REFT
AGND
VCM
Pin description (CMOS digital outputs)
Pin
1
Type [1]
Description
O
O
G
O
P
G
I
bottom reference
2
top reference
3
analog ground
4
common-mode output voltage
analog power supply 5 V
analog ground
VDDA5V
AGND
INM
5
6
7
complementary analog input
analog input
INP
8
I
AGND
VDDA3V
VDDA3V
CLKP
CLKM
DEC
9
G
P
P
I
analog ground
10
11
12
13
14
15
16
analog power supply 3 V
analog power supply 3 V
clock input
I
complementary clock input
regulator decoupling node
output enable, active LOW
power down, active HIGH
O
I
OE
PWD
I
ADC1115S125_1
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
3 of 35
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 2.
Pin description (CMOS digital outputs)
Symbol
D10
Pin
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Type [1]
Description
O
O
O
O
O
O
O
O
O
O
O
-
data output bit 10 (MSB)
data output bit 9
D9
D8
data output bit 8
D7
data output bit 7
D6
data output bit 6
D5
data output bit 5
D4
data output bit 4
D3
data output bit 3
D2
data output bit 2
D1
data output bit 1
D0
data output bit 0 (LSB)
not connected
n.c.
n.c.
-
not connected
n.c.
-
not connected
DAV
n.c.
O
-
data valid output clock
not connected
VDDO
OGND
OTR
SCLK/DFS
SDIO/ODS
CS
P
G
O
I
output power supply
output ground
out of range
SPI clock / data format select
SPI data IO / output data standard
SPI chip select
I/O
I
SENSE
VREF
I
reference programming pin
voltage reference input/output
I/O
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
Table 3.
Pin description (LVDS/DDR) digital outputs)
Symbol
Pin[1]
17
Type [2] Description
D9_D10_M
D9_D10_P
D7_D8_M
D7_D8_P
D5_D6_M
D5_D6_P
D3_D4_M
D3_D4_P
D1_D2_M
D1_D2_P
O
O
O
O
O
O
O
O
O
O
O
O
-
differential output data D9 and D10 multiplexed, complement
18
differential output data D9 and D10 multiplexed, true
differential output data D7 and D8 multiplexed, complement
differential output data D7 and D8 multiplexed, true
differential output data D5 and D6 multiplexed, complement
differential output data D5 and D6 multiplexed, true
differential output data D3 and D4 multiplexed, complement
differential output data D3 and D4 multiplexed, true
differential output data D1 and D2 multiplexed, complement
differential output data D1 and D2 multiplexed, true
differential output data D0 multiplexed, complement
differential output data D0 multiplexed, true
19
20
21
22
23
24
25
26
LOW_D0_M 27
LOW_D0_P 28
n.c.
29
not connected
ADC1115S125_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
4 of 35
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 3.
Pin description …continued (LVDS/DDR) digital outputs)
Symbol
n.c.
Pin[1]
30
Type [2] Description
-
not connected
DAVM
DAVP
31
O
O
data valid output clock, complement
data valid output clock, true
32
[1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2)
[2] P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VO
output voltage
pins D10 to D0 or
−0.4
+3.9
V
pins D10P to D0P and
pins D10M to D0M
VDDA(3V)
VDDA(5V)
VDDO
ΔVCC
Tstg
analog supply voltage 3 V
analog supply voltage 5 V
output supply voltage
supply voltage difference
storage temperature
on pin VDDA3V
on pin VDDA5V
−0.5
−0.5
−0.5
+4.6
+6.0
+4.6
V
V
V
VDDA(3V) − VDDO
<tbd> <tbd>
V
−55
−40
-
+125
+85
°C
°C
°C
Tamb
ambient temperature
junction temperature
Tj
125
8. Thermal characteristics
Table 5.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ
Unit
[1]
[1]
thermal resistance from junction to ambient
thermal resistance from junction to case
30.5
13.3
K/W
K/W
Rth(j-c)
[1] Value for six layers board in still air with a minimum of 25 thermal vias.
9. Static characteristics
Table 6.
Symbol
Supplies
VDDA(5V)
VDDA(3V)
VDDO
Static characteristics[1]
Parameter
Conditions
Min
Typ
Max
Unit
analog supply voltage 5 V
analog supply voltage 3 V
output supply voltage
4.75
2.85
1.65
2.85
-
5.0
3.0
1.8
3.0
46
5.25
3.4
3.6
3.6
-
V
V
CMOS mode
V
LVDS DDR mode
V
IDDA(5V)
analog supply current 5 V
fclk = 125 Msps;
fi =70 MHz
mA
ADC1115S125_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
5 of 35
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 6.
Symbol
IDDA(3V)
Static characteristics[1] …continued
Parameter
Conditions
Min
Typ
Max
Unit
analog supply current 3 V
fclk = 125 Msps;
fi =70 MHz
-
205
-
mA
IDDO
output supply current
CMOS mode;
fclk = 125 Msps;
fi =70 MHz
-
-
11
39
-
-
mA
mA
LVDS DDR mode:
fclk = 125 Msps;
fi =70 MHz
P
power dissipation
analog supply only
Power-down mode
Standby mode
-
-
-
840
2
-
-
-
mW
mW
mW
40
Clock inputs: pins CLKP and CLKM
LVPECL
Vi(clk)dif
LVDS
differential clock input voltage
peak-to-peak
peak-to-peak
peak-to-peak
-
±1.6
±0.70
±3.0
-
-
-
V
V
V
Vi(clk)dif
SINE wave
Vi(clk)dif
LVCMOS
VIL
differential clock input voltage
differential clock input voltage
-
±0.8
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.3VDDA(3V)
-
V
V
VIH
0.7VDDA(3V)
Logic inputs: pins PWD and OE
VIL
VIH
IIL
LOW-level input voltage
0
-
-
-
-
0.8
V
HIGH-level input voltage
LOW-level input current
HIGH-level input current
2
VDDA(3V)
<tbd>
+10
V
<tbd>
−10
μA
μA
IIH
Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input capacitance
0
-
0.3VDDA(3V)
V
0.7VDDA(3V)
-
VDDA(3V)
+10
+50
-
V
−10
−50
-
-
μA
μA
pF
IIH
CI
-
4
Digital outputs, CMOS mode: pins D10 to D0, OTR, DAV
Output levels, VDDO = 3 V
VOL
VOH
IOL
LOW-level output voltage
HIGH-level output voltage
LOW-level output current
IOL = <tbd>
IOH = <tbd>
OGND
0.8VDDO
-
-
0.2VDDO
V
-
VDDO
-
V
3-state;
<tbd>
μA
output level = 0 V
IOH
CO
HIGH-level output current
output capacitance
3-state;
output level = VDDA(3V)
-
-
<tbd>
3
-
-
μA
high impedance;
OE = HIGH
pF
Output levels, VDDO = 1.8 V
ADC1115S125_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
6 of 35
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 6.
Symbol
VOL
Static characteristics[1] …continued
Parameter
Conditions
IOL = <tbd>
IOH = <tbd>
Min
Typ
Max
Unit
V
LOW-level output voltage
HIGH-level output voltage
OGND
0.8VDDO
-
-
0.2VDDO
VDDO
VOH
V
Digital outputs, LVDS mode: pins D10P to D0P, D10M to D0M, DAVP and DAVM
Output levels, VDDO = 3 V only, Rload = 100 Ω
VO(offset)
VO(dif)
CO
output offset voltage
differential output voltage
output capacitance
output buffer current
set to 3.5 mA
-
-
-
1.2
-
-
-
V
output buffer current
set to 3.5 mA
350
mV
pF
<tbd>
Analog inputs: pins INP and INM
II
input current
−5
-
-
+5
-
μA
Ω
RI
input resistance
550
1.3
1.5
600
CI
input capacitance
common-mode input voltage
input bandwidth
-
-
pF
V
VI(cm)
Bi
VINP = VINM
0.9
-
2
-
MHz
V
VI(dif)
differential input voltage
peak-to-peak
1
2
Common mode output voltage: pin VCM
VO(cm)
IO(cm)
common-mode output voltage
common-mode output current
-
-
0.5VDDA(3V)
<tbd>
-
-
V
μA
I/O reference voltage: pin VREF
VVREF
voltage on pin VREF
output
input
-
0.5 to 1
-
-
V
V
0.5
1
Accuracy
INL
integral non-linearity
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
LSB
LSB
DNL
differential non-linearity
guaranteed no
missing codes
Eoffset
EG
offset error
gain error
-
-
±2
-
-
mV
±0.5
%FS
Supply
PSRR
power supply rejection ratio
100 mV (p-p) on
VDDA(3V)
-
35
-
dBc
[1] Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; minimum and maximum values
are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP − VINM = −1 dBFS;
internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
ADC1115S125_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
7 of 35
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
10. Dynamic characteristics
10.1 Dynamic characteristics
Table 7.
Symbol
Dynamic characteristics[1]
Parameter
Conditions
ADC1115S125
Typ
Unit
Min
Max
Analog signal processing
α2H
second harmonic level
fi = 3 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
88
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
87
85
83
α3H
third harmonic level
87
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
86
84
82
THD
ENOB
SNR
SFDR
IMD
total harmonic distortion
effective number of bits
signal-to-noise ratio
86
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
85
83
81
10.7
10.7
10.7
10.6
66.2
66.2
66.0
65.8
87
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
bits
bits
bits
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
spurious-free dynamic
range
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
86
84
82
Intermodulation distortion fi = 3 MHz
fi = 30 MHz
89
88
fi = 70 MHz
86
fi = 170 MHz
84
[1] Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; minimum and maximum values
are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP − VINM = −1 dBFS;
internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
ADC1115S125_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
8 of 35
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
10.2 Clock and digital output timing
Table 8.
Symbol
Clock and digital output timing characteristics[1]
Parameter
Conditions
ADC1115S125
Typ
Unit
Min
Max
Clock timing input: pins CLKP and CLKM
fclk
clock frequency
data latency time
100
-
125
MHz
tlat(data)
-
14
-
clock
cycles
δclk
clock duty cycle
DCS_EN = 1
DCS_EN = 0
30
45
-
50
70
55
-
%
%
ns
ns
50
td(s)
sampling delay time
wake-up time
0.8
tbd
twake
-
-
CMOS mode timing output: pins D10 to D0 and DAV
tPD
propagation delay
DATA
DAV
-
3.9
4.2
4.3
3.5
-
-
ns
ns
ns
ns
ns
ns
ns
-
-
tsu
th
tr
set-up time
hold time
rise time[2]
-
-
-
-
DATA
DAV
0.5
0.5
0.5
2.4
2.4
2.4
-
tf
fall time[2]
DATA
-
LVDS DDR mode timing output: pins D10P to D0P, D10M to D0M, DAVP and DAVM
tPD
propagation delay
DATA
DAV
-
3.9
-
ns
ns
ns
ns
ps
ps
ps
ps
-
4.2
-
tsu
th
tr
set-up time
hold time
rise time[3]
-
1.4
-
-
2.0
-
DATA
DAV
50
50
50
50
100
100
100
100
200
200
200
200
tf
fall time[3]
DATA
DAV
[1] Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; minimum and maximum values
are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP − VINM = −1 dBFS;
internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
[2] Measured between 20 % to 80 % of VDDO
.
[3] Rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV.
ADC1115S125_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
9 of 35
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
N
N + 1
t
d(s)
N + 2
t
clk
CLKP
CLKM
t
PD
(N − 14)
(N − 13)
(N − 12)
(N − 11)
DATA
DAV
t
PD
t
su
t
h
t
clk
005aaa060
Fig 4. CMOS mode timing
N
N + 1
t
d(s)
N + 2
t
clk
CLKP
CLKM
t
PD
(N − 14)
(N − 13)
(N − 12)
(N − 11)
D _D
_P
x
x + 1
D
x
D
x + 1
D
x
D
x + 1
D
x
D
x + 1
D
x
D
x + 1
D
x
D
x + 1
D _D
_M
x
x + 1
t
su
t
t
t
h
su h
t
PD
DAVP
DAVM
t
clk
005aaa061
Fig 5. LDVS DDR mode timing
ADC1115S125_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 12 April 2010
10 of 35
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
10.3 SPI timings
Table 9.
Symbol
Characteristics
Parameter
Conditions
Min Typ
Max
Unit
SPI timings
tw(SCLK)
tw(SCLKH)
tw(SCLKL)
tsu
SCLK pulse width
SCLK pulse width HIGH
SCLK pulse width LOW
set-up time
40
16
16
5
-
-
-
-
-
-
-
-
-
ns
-
ns
-
ns
data to SCLKH
CS to SCLKH
data to SCLKH
CS to SCLKH
-
ns
5
-
ns
th
hold time
2
-
ns
2
-
ns
fclk(max)
maximum clock frequency
-
25
MHz
[1] Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF;
minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at
VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP − VINM = −1 dBFS; internal reference mode; applied to
CMOS and LVDS interface; unless otherwise specified
t
t
su
w(SCLKL)
t
h
t
h
su
t
t
w(SCLKH)
t
w(SCLK)
CS
SCLK
SDIO
W1
W0
A12
A11
D2
D1
D0
R/W
005aaa065
Fig 6. SPI timing
11. Application information
11.1 Device control
The ADC1115S125 can be controlled via the Serial Peripheral Interface (SPI control
mode) or directly via the I/O pins (Pin control mode).
11.1.1 SPI and Pin control modes
The device enters Pin control mode at power-up, and remains in this mode as long as pin
CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins.
SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been
enabled, the device will remain in this mode. The transition from Pin control mode to SPI
control mode is illustrated in Figure 7.
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
CS
Pin control mode
SPI control mode
SCLK/DFS
SDIO/ODS
Data format
offset binary
Data format
two's complement
LVDS DDR
R/W
W1
W0
A12
CMOS
005aaa039
Fig 7. Control mode selection
When the device enters SPI control mode, the output data standard and data format are
determined by the level on pin SDIO as soon as a transition is triggered by a falling edge
on CS.
11.1.2 Operating mode selection
The active ADC1115S125 operating mode (Power-up, Power-down or Sleep) can be
selected via the SPI interface (see Table 19) or using pins PWD and OE in Pin control
mode, as described in Table 10.
Table 10. Operating mode selection via pin PWD and OE
Pin PWD
Pin OE
Operating mode
Power-up
Output high-Z
0
0
1
1
0
1
0
1
no
Power-up
yes
yes
yes
Sleep
Power-down
11.1.3 Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see Table 23) or using pin ODS in Pin control mode. LVDS DDR is selected when ODS is
HIGH, otherwise CMOS is selected.
11.1.4 Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, two’s
complement or gray code; see Table 23) or using pin DFS in Pin control mode (offset
binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, two’s complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1115S125 supports differential or single-ended input drive.
Optimal performance is achieved using differential inputs. The ADC inputs are internally
biased and need to be decoupled.
The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.3 and Table 21 further details).
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
The equivalent circuit of the input buffer followed by the Sample and Hold (S/H) input
stage, including ElectroStatic Discharge (ESD) protection and circuit and package
parasitics, is shown in Figure 8.
package
ESD
parasitics
switch
R
= 15 Ω
on
4 pF
8
7
INP
INM
sampling
capacitor
internal
clock
INPUT
BUFFER
switch
R
= 15 Ω
on
4 pF
sampling
capacitor
internal
clock
005aaa107
Fig 8. Input sampling circuit and input buffer
The integrated input buffer offers the following advantages:
• The kickback effect is avoided - the charge injection and glitches generated by the
S/H input stage are isolated from the input circuitry. So there’s no need for additional
filtering.
• The input capacitance is very low and constant over a wide frequency range, which
makes the ADC1115S125 easy to drive.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
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11.2.2 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 9 would be suitable for a baseband application.
ADT1-1WT
100 nF
100 nF
100 nF
INP
Analog
input
50 Ω
100 nF
INM
VCM
100 nF
100 nF
005aaa108
Fig 9. Single transformer configuration suitable for baseband applications
The configuration shown in Figure 10 is recommended for high frequency applications. In
both cases, the choice of transformer will be a compromise between cost and
performance.
ADT1-1WT
ADT1-1WT
100 nF
100 nF
INP
100 nF
50 Ω
50 Ω
Analog
input
100 Ω
INM
VCM
100 nF
100 nF
100 nF
005aaa109
Fig 10. Dual transformer configuration suitable for high intermediate frequency
application
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.3 System reference and power management
11.3.1 Internal/external references
The ADC1115S125 has a stable and accurate built-in internal reference voltage to adjust
the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF
and SENSE (programmable in 1 dB steps between 0 dB and −6 dB via control bits
INTREF[2:0] when bit INTREF_EN = 1; see Table 21). See Figure 12, Figure 13,
Figure 14 and Figure 15. The equivalent reference circuit is shown in Figure 11. External
reference is also possible by providing a voltage on pin VREF as described in Figure 14.
REFT
REFERENCE
REFB
AMP
VREF
EXT_ref
EXT_ref
BANDGAP
REFERENCE
BUFFER
ADC CORE
SENSE
SELECTION
LOGIC
005aaa164
Fig 11. Reference equivalent schematic
If bit INTREF_EN is set to 0, the reference voltage will be determined either internally or
externally as detailed in Table 11.
Table 11. Reference selection
Selection
SPI bit
SENSE pin
VREF pin
full scale (p-p)
INTREF_EN
internal
(Figure 12)
0
0
0
1
AGND
330 pF capacitor to AGND 2 V
internal
(Figure 13)
pin VREF connected to pin SENSE and
via a 330 pF capacitor to AGND
1 V
external
(Figure 14)
VDDA(3V)
external voltage between
0.5 V and 1 V[1]
1 V to 2 V
1 V to 2 V
internal via SPI
(Figure 15)
pin VREF connected to pin SENSE and
via 330 pF capacitor to AGND
[1] The voltage on pin VREF is doubled internally to generate the internal reference voltage.
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Figure 12 to Figure 15 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
VREF
VREF
330
pF
330 pF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
005aaa116
005aaa117
Fig 12. Internal reference, 2 V (p-p) full scale
Fig 13. Internal reference, 1 V (p-p) full scale
VREF
VREF
0.1 μF
V
330 pF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
VDDA
005aaa119
005aaa118
Fig 14. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
Fig 15. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
11.3.2 Reference gain control
The reference gain is programmable between 0 dB to −6 dB in 1 dB steps via the SPI (see
Table 21). The corresponding full-scale input voltage range varies between 2 V (p-p) and
1 V (p-p), as shown in Table 12:
Table 12. Reference SPI gain control
INTREF
000
Gain
full scale (p-p)
2 V
0 dB
001
−1 dB
−2 dB
−3 dB
−4 dB
−5 dB
−6 dB
reserved
1.78 V
1.59 V
1.42 V
1.26 V
1.12 V
1 V
010
011
100
101
110
111
x
11.3.3 Common-mode output voltage (VO(cm)
)
A 0.1 μF filter capacitor should be connected between pin VCM and ground.
11.3.4 Biasing
The common-mode input voltage (VI(cm)) on pins INP and INM is set internally. The input
buffer bias current can be set to one of three levels (high, medium or low) via the SPI
(see Table 22).
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.4 Clock input
11.4.1 Drive modes
The ADC1115S125 can be driven differentially (SINE, LVPECL or LVDS) with little or no
degradation on dynamic performances. It can also be driven by a single-ended LVCMOS
signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or
CLKM (CLKP should be connected to ground via a capacitor).
CLKP
CLKM
LVCMOS
clock input
CLKP
CLKM
LVCMOS
clock input
005aaa174
005aaa053
a. Rising edge LVCMOS
b. Falling edge LVCMOS
Fig 16. LVCMOS single-ended clock input
CLKP
CLKM
Sine
clock input
CLKP
Sine
clock input
CLKM
005aaa173
005aaa054
a. Sine clock input
b. Sine clock input (with transformer)
CLKP
CLKP
LVPECL
clock input
LVDS
clock input
CLKM
CLKM
005aaa172
005aaa055
c. LVDS clock input
d. LVPECL clock input1
Fig 17. Differential clock input
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode
voltage of the differential input stage is set via internal 5 kΩ resistors.
PACKAGE
ESD
PARASITICS
CLKP
CLKM
V
cm(clk)
SE_SEL SE_SEL
5 kΩ
5 kΩ
005aaa056
Fig 18. Equivalent input circuit
Single-ended or differential clock inputs can be selected via the SPI interface (see
Table 20). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control
bit SE_SEL.
If single-ended is implemented without setting SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
11.4.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = 1; see Table 20), the circuit can handle signals with duty cycles of
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN =
0), the input clock signal should have a duty cycle of between 45% and 55%.
11.4.4 Clock input divider
The ADC1115S125 contains an input clock divider that divides the incoming clock by a
factor of 2 (when bit CLKDIV = 1; see Table 20). This feature allows the user to deliver a
higher clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
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11.5 Digital outputs
11.5.1 Digital output buffers: CMOS mode
The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0
(see Table 23).
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in Figure 19. The buffer is powered by a separate
OGND/VDDO to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core.
Each buffer can be loaded by a maximum of 10 pF.
VDDO
PARASITICS
ESD
PACKAGE
50 Ω
Dx
LOGIC
DRIVER
OGND
005aaa057
Fig 19. CMOS digital output buffer
The output resistance is 50 Ω and is the combination of the an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both data and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see Table 30):
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1
(see Table 23).
VCCO
3.5 mA
typ
−
+
D P/D
P
n
n + 1
RECEIVER
100 Ω
D M/D
n
M
n + 1
+
−
OGND
005aaa058
Fig 20. LVDS DDR digital output buffer - externally terminated
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side (Figure 20) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 21 and
Table 32).
VCCO
3.5 mA
typ
−
+
D P/D
P
x
x + 1
100 Ω
RECEIVER
D M/D
x
M
x + 1
+
−
OGND
005aaa059
Fig 21. LVDS DDR digital output buffer - internally terminated
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31) in order to adjust the output logic
voltage levels.
Table 13. LVDS DDR output register 2
LVDS_INT_TER[2:0]
Resistor value (Ω)
000
001
010
011
100
no internal termination
300
180
110
150
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 13. LVDS DDR output register 2 …continued
LVDS_INT_TER[2:0]
Resistor value (Ω)
101
110
111
100
81
60
11.5.3 Data valid (DAV) output clock
A data valid output clock signal (DAV) is provided that can be used to capture the data
delivered by the ADC1115S125. Detailed timing diagrams for CMOS and LVDS DDR
modes are provided in Figure 4 and Figure 5 respectively.
11.5.4 Out-of-Range (OTR)
An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock
cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = 1;
see Table 29). In this mode, the latency of OTR is reduced to only four clock cycles. The
Fast OTR detection threshold (below full scale) can be programmed via bits
FASTOTR_DET[2:0].
Table 14. Fast OTR register
FASTOTR_DET[2:0]
Detection level (dB)
−20.56
000
001
010
011
100
101
110
111
−16.12
−11.02
−7.82
−5.49
−3.66
−2.14
−0.86
11.5.5 Digital offset
By default, the ADC1115S125 delivers output code that corresponds to the analog input.
However it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET[5:0]; see Table 25).
11.5.6 Test patterns
For test purposes, the ADC1115S125 can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26). A custom test pattern
can be defined by the user (TESTPAT_USER; see Table 27 and Table 28) and is selected
when TESTPAT_SEL[2:0] = 101. The selected test pattern will be transmitted regardless
of the analog input.
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.5.7 Output codes versus input voltage
Table 15. Output codes
VINP − VINM
< −1
Offset binary
Two’s complement
100 0000 0000
100 0000 0000
100 0000 0001
100 0000 0010
100 0000 0011
100 0000 0100
....
OTR pin
000 0000 0000
000 0000 0000
000 0000 0001
000 0000 0010
000 0000 0011
000 0000 0100
....
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
−1.0000000
−0.9990234
−0.9980469
−0.9970703
−0.996093
....
−0.0019531
−0.0009766
0.0000000
+0.0009766
+0.0019531
....
011 1111 1110
011 1111 1111
100 0000 0000
100 0000 0001
100 0000 0010
....
111 1111 1110
111 1111 1111
000 0000 0000
000 0000 0001
000 0000 0010
....
+0.9960938
+0.9970703
+0.9980469
+0.9990234
+1.0000000
> +1
111 1111 1011
111 1111 1100
111 1111 1101
111 1111 1110
111 1111 1111
111 1111 1111
011 1111 1011
011 1111 1100
011 1111 1101
011 1111 1110
011 1111 1111
011 1111 1111
11.6 Serial Peripheral Interface (SPI)
11.6.1 Register description
The ADC1115S125 serial interface is a synchronous serial communications port that
allows for easy interfacing with many commonly-used microprocessors. It provides access
to the registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin)
Pin SCLK is the serial clock input and CS is the chip select pin.
Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes will
be transmitted (two instruction bytes and at least one data byte). The number of data
bytes is determined by the value of bits W1 and W2 (see Table 17).
Table 16. Instruction bytes for the SPI
MSB
LSB
0
Bit
7
6
5
4
3
2
1
Description
R/W[1]
A7
W1[2]
W0[2]
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
A6
A5
[1] Bit R/W indicates whether it is a read (1) or a write (0) operation.
[2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 17).
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 17. Number of data bytes to be transferred after the instruction bytes
W1
0
W0
0
Number of bytes transmitted
1 byte
0
1
2 bytes
1
0
3 bytes
1
1
4 bytes or more
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. A falling edge on CS in combination with a rising edge on SCLK determine the start of
communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but will always
be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on CS indicates the end on data transmission.
CS
SCLK
SDIO
W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
R/W
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa062
Fig 22. SPI mode timing
11.6.2 Default modes at start-up
During circuit initialization, it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on CS will trigger a transition to SPI control mode. When the ADC1115S125
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see Figure 23). Once in SPI control mode, the output data standard
can be changed via bit LVDS/CMOS in Table 23.
When the ADC1115S125 enters SPI control mode, the output data format (two’s
complement or offset binary) is determined by the level on pin SCLK (gray code can only
be selected via the SPI). Once in SPI control mode, the output data format can be
changed via bit DATA_FORMAT[1:0] in Table 23.
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ADC1115S125
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
CS
SCLK
(Data fo
rmat)
SDIO
(CMOS LVDS DDR)
Offset binary, LVDS DDR
default mode at start-up
005aaa063
Fig 23. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
CS
SCLK
(Data fo
rmat)
SDIO
(CMOS LVDS DDR)
two's complement, CMOS
default mode at start-up
005aaa064
Fig 24. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
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11.6.3 Register allocation map
Table 18. Register allocation map
Addr.
Hex
Register name
R/W
Bit definition
Default
Bin
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0005
0006
0008
0010
0011
0012
0013
0014
0015
0016
0017
0020
0021
0022
Reset and
operating mode
R/W
R/W
SW_RST
RESERVED[2:0]
-
-
-
OP_MODE[1:0]
0000
0000
Clock
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SE_SEL
DIFF_SE
CLKDIV
DCS_EN 0000
0001
Internal reference R/W
-
-
INTREF_EN
-
INTREF[2:0]
0000
0000
Input buffer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
IB_IBIAS[1:0
]
-
0000
0011
Output data
standard.
LVDS_
CMOS
OUTBUF
DAVINV
OUTBUS_SWAP
DATA_FORMAT[1:0]
0000
0000
Output clock
-
-
DAVPHASE[2:0]
0000
1110
Offset
DIG_OFFSET[5:0]
0000
0000
Test pattern 1
Test pattern 2
Test pattern 3
Fast OTR
-
-
TESTPAT_SEL[2:0]
0000
0000
TESTPAT_USER[10:3]
0000
0000
TESTPAT_USER[2:0]
-
-
-
-
-
-
-
0000
0000
-
-
-
-
-
-
-
-
-
FASTOTR
FASTOTR_DET[2:0]
0000
0000
CMOS output
-
DAV_DRV[1:0]
DATA_DRV[1:0]
DATAI[1:0]
0000
1110
LVDS DDR O/P 1 R/W
LVDS DDR O/P 2 R/W
DAVI_x2_EN
-
DAVI[1:0]
BIT_BYTE_WISE
DATAI_x2_EN
0000
0000
-
LVDS_INT_TER[2:0]
0000
0000
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 19. Reset and operating mode control register (address 0005h) bit description
Bit
Symbol
Access
Value
Description
7
SW_RST
R/W
reset digital section
no reset
0
1
performs a reset on SPI registers
reserved
6 to 4
3 to 2
1 to 0
RESERVED[2:0]
000
00
-
not used
OP_MODE[1:0]
R/W
operating mode
normal (Power-up)
Power-down
00
01
10
11
Sleep
normal (Power-up)
Table 20. Clock control register (address 0006h) bit description
Bit
7 to 5
4
Symbol
-
Access
Value
Description
000
not used
SE_SEL
R/W
single-ended clock input pin select
0
CLKM
1
CLKP
3
DIFF_SE
R/W
differential/single ended clock input select
0
1
0
fully differential
single-ended
not used
2
1
-
CLKDIV
R/W
R/W
clock input divide by 2
disabled
0
1
enabled
0
DCS_EN
duty cycle stabilizer
disabled
0
1
enabled
ADC1115S125_1
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Preliminary data sheet
Rev. 01 — 12 April 2010
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ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 21. Internal reference control register (address 0008h) bit description
Bit
7 to 4
3
Symbol
Access
Value
Description
-
0000
not used
INTREF_EN
R/W
programmable internal reference enable
disable
0
1
active
2 to 0
INTREF[2:0]
R/W
programmable internal reference
0 dB (FS = 2 V)
000
001
010
011
100
101
110
111
−1 dB (FS = 1.78 V)
−2 dB (FS = 1.59 V)
−3 dB (FS = 1.42 V)
−4 dB (FS = 1.26 V)
−5 dB (FS = 1.12 V)
−6 dB (FS = 1 V)
reserved
Table 22. Input buffer control register (address 0010h) bit description
Bit
Symbol
Access
Value
Description
not used
7 to 2
1 to 0
-
000000
IB_IBIAS[1:0]
R/W
input buffer bias current
not used
00
01
10
11
medium
low
high
Table 23. Output data standard control register (address 0011h) bit description
Bit
7 to 5
4
Symbol
Access
Value
Description
-
000
not used
LVDS_CMOS
R/W
output data standard: LVDS DDR or CMOS
0
CMOS
1
LVDS DDR
3
OUTBUF
R/W
R/W
output buffers enable
output enabled
0
1
output disabled (high Z)
output bus swapping
no swapping
2
OUTBUS_SWAP
0
1
output bus is swapped (MSB becomes LSB and vice versa)
output data format
offset binary
1 to 0
DATA_FORMAT[1:0] R/W
00
01
10
11
two’s complement
gray code
offset binary
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Preliminary data sheet
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ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 24. Output clock register (address 0012h) bit description
Bit
7 to 4
3
Symbol
-
Access
Value
Description
0000
not used
DAVINV
R/W
output clock data valid (DAV) polarity
normal
0
1
inverted
2 to 0
DAVPHASE[2:0]
R/W
DAV phase select
000
001
010
011
100
101
110
111
output clock shifted (ahead) by 3 ns
output clock shifted (ahead) by 2.5 ns
output clock shifted (ahead) by 2 ns
output clock shifted (ahead) by 1.5 ns
output clock shifted (ahead) by 1 ns
output clock shifted (ahead) by 0.5 ns
default value as defined in timing section
output clock shifted (delayed) by 0.5 ns
Table 25. Offset register (address 0013h) bit description
Bit
Symbol
Access
Value
Description
7 to 6
5 to 0
-
00
not used
DIG_OFFSET[5:0]
R/W
digital offset adjustment
011111
...
+31 LSB
...
000000
...
0
...
100000
−32 LSB
Table 26. Test pattern register 1 (address 0014h) bit description
Bit
Symbol
Access
Value
Description
7 to 3
2 to 0
-
00000
not used
TESTPAT_SEL[2:0]
R/W
digital test pattern select
000
001
010
011
100
101
110
111
off
mid scale
−FS
+FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern
‘1010..1010.’
‘010..1010’
Table 27. Test pattern register 2 (address 0015h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
TESTPAT_USER[10:3]
R/W
00000000 custom digital test pattern (bits 10 to 3)
ADC1115S125_1
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Preliminary data sheet
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ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 28. Test pattern register 3 (address 0016h) bit description
Bit
Symbol
Access
Value
000
Description
7 to 5
4 to 0
TESTPAT_USER[2:0]
-
R/W
custom digital test pattern (bits 2 to 0)
not used
00000
Table 29. Fast OTR register (address 0017h) bit description
Bit
7 to 4
3
Symbol
-
Access
Value
Description
not used
0000
FASTOTR
R/W
fast Out-of-Range (OTR) detection
disabled
0
1
enabled
2 to 0
FASTOTR_DET[2:0] R/W
set fast OTR detect level
−20.56 dB
000
001
010
011
100
101
110
111
−16.12 dB
−11.02 dB
−7.82 dB
−5.49 dB
−3.66 dB
−2.14 dB
−0.86 dB
Table 30. CMOS output register (address 0020h) bit description
Bit
Symbol
Access
Value
Description
7 to 4
3 to 2
-
0000
not used
DAV_DRV[1:0]
R/W
drive strength for DAV CMOS output buffer
00
01
10
11
low
medium
high
very high
1 to 0
DATA_DRV[1:0] R/W
drive strength for DATA CMOS output buffer
00
01
10
11
low
medium
high
very high
ADC1115S125_1
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ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 31. LVDS DDR output register 1 (address 0021h) bit description
Bit
7 to 6
5
Symbol
Access
Value
Description
-
00
not used
DAVI_x2_EN
R/W
double LVDS current for DAV LVDS buffer
0
disabled
1
enabled
4 to 3
DAVI[1:0]
R/W
LVDS current for DAV LVDS buffer
00
01
10
11
3.5 mA
4.5 mA
1.25 mA
2.5 mA
2
DATAI_x2_EN
DATAI[1:0]
R/W
R/W
double LVDS current for DATA LVDS buffer
0
disabled
1
enabled
1 to 0
LVDS current for DATA LVDS buffer
00
01
10
11
3.5 mA
4.5 mA
1.25 mA
2.5 mA
Table 32. LVDS DDR output register 2 (address 0022h) bit description
Bit
7 to 4
3
Symbol
Access
Value
Description
-
0000
not used
BIT/BYTE_WISE
R/W
DDR mode for LVDS output
0
bit wise (even data bits output on DAV rising edge / odd data bits
output on DAV falling edge)
1
byte wise (MSB data bits output on DAV rising edge / LSB data
bits output on DAV falling edge)
2 to 0
LVDS_INTTER[2:0]
R/W
internal termination for LVDS buffer (DAV and DATA)
000
001
010
011
100
101
110
111
no internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
ADC1115S125_1
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Rev. 01 — 12 April 2010
30 of 35
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
12. Package outline
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm
SOT618-6
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
1/2 e
C
v
w
C A
C
B
e
b
y
1
y
C
11
20
L
21
10
e
E
h
e
2
1/2 e
1
30
terminal 1
index area
40
31
X
D
h
0
2.5
scale
5 mm
v
Dimensions
Unit
(1)
(1)
(1)
A
A
1
b
c
D
D
h
E
E
h
e
e
e
2
L
w
y
y
1
1
max 1.00 0.05 0.30
6.1 4.55 6.1 4.55
0.5
mm nom 0.85 0.02 0.21 0.2 6.0 4.40 6.0 4.40 0.5 4.5 4.5 0.4 0.1 0.05 0.05 0.1
min 0.80 0.00 0.18 5.9 4.25 5.9 4.25 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot618-6_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
- - -
09-02-23
09-03-04
SOT618-6
MO-220
Fig 25. Package outline SOT618-6 (HVQFN40)
ADC1115S125_1
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ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
13. Revision history
Table 33. Revision history
Document ID
Release date
20100412
Data sheet status
Change Supersedes
notice
ADC1115S125_1
Preliminary data sheet -
-
ADC1115S125_1
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Preliminary data sheet
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32 of 35
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
14.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
14.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
ADC1115S125_1
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Preliminary data sheet
Rev. 01 — 12 April 2010
33 of 35
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Rev. 01 — 12 April 2010
34 of 35
ADC1115S125
NXP Semiconductors
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
16. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
12
13
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 31
Revision history . . . . . . . . . . . . . . . . . . . . . . . 32
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
14
Legal information . . . . . . . . . . . . . . . . . . . . . . 33
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 33
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 34
14.1
14.2
14.3
14.4
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
15
16
Contact information . . . . . . . . . . . . . . . . . . . . 34
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Clock and digital output timing . . . . . . . . . . . . . 9
SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10.1
10.2
10.3
11
11.1
Application information. . . . . . . . . . . . . . . . . . 11
Device control. . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI and Pin control modes. . . . . . . . . . . . . . . 11
Operating mode selection. . . . . . . . . . . . . . . . 12
Selecting the output data standard. . . . . . . . . 12
Selecting the output data format. . . . . . . . . . . 12
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 14
System reference and power management . . 15
Internal/external references . . . . . . . . . . . . . . 15
Reference gain control . . . . . . . . . . . . . . . . . . 16
Common-mode output voltage (VO(cm)) . . . . . 16
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 17
Equivalent input circuit . . . . . . . . . . . . . . . . . . 18
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 18
Clock input divider . . . . . . . . . . . . . . . . . . . . . 18
Digital outputs. . . . . . . . . . . . . . . . . . . . . . . . . 19
Digital output buffers: CMOS mode . . . . . . . . 19
Digital output buffers: LVDS DDR mode. . . . . 20
Data valid (DAV) output clock. . . . . . . . . . . . . 21
Out-of-Range (OTR). . . . . . . . . . . . . . . . . . . . 21
Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output codes versus input voltage . . . . . . . . . 22
Serial Peripheral Interface (SPI). . . . . . . . . . . 22
Register description . . . . . . . . . . . . . . . . . . . . 22
Default modes at start-up . . . . . . . . . . . . . . . . 23
Register allocation map . . . . . . . . . . . . . . . . . 25
11.1.1
11.1.2
11.1.3
11.1.4
11.2
11.2.1
11.2.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.6
11.6.1
11.6.2
11.6.3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 April 2010
Document identifier: ADC1115S125_1
相关型号:
ADC1115S125HN-C1
Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
IDT
ADC1115S125HN/C1
Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
NXP
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