ADC1213D125HN/C1 [NXP]
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; 双通道12位ADC ; 65 MSPS， 80 MSPS， 105 Msps的或125 MSPS
| 型号： | ADC1213D125HN/C1 |
| 厂家： | 
NXP |
| 描述： | Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps |
| 文件： | 总41页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC1213D series
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps
Rev. 05 — 23 April 2010
Preliminary data sheet
1. General description
The ADC1213D is a dual-channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1213D is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V
source for analog and a 1.8 V source for the output driver, it embeds two serial outputs.
Each lane is differential and complies with the JESD204A standard. An integrated Serial
Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC
configurations is also available via the binary level control pins taken, which are used at
power-up. The device also includes a SPI programmable full-scale to allow flexible input
voltage range from 1 V to 2 V (peak-to-peak).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1213D ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
SNR, 70 dBFS; SFDR, 86 dBc
Input bandwidth, 600 MHz
Sample rate up to 125 Msps
Power dissipation, 995 mW at 80 Msps
SPI register programming
Clock input divider by 2 for less jitter
contribution
3 V, 1.8 V single supplies
Duty cycle stabilizer
High IF capability
Flexible input voltage range:
1 V to 2 V (peak-to-peak)
Two configurable serial outputs
Offset binary, two’s complement, gray
code
INL ± 1 LSB; DNL ± 0.5 LSB
Pin compatible with the ADC1213D
series
Power-down mode and Sleep mode
Compliant with JESD204A serial
transmission standard
HVQFN56 package
3. Applications
Wireless and wired broadband
Portable instrumentation
communications
Spectral analysis
Imaging systems
Ultrasound equipment
Software defined radio
ADC1213D series
NXP Semiconductors
ADC1213D series
4. Ordering information
Table 1.
Ordering information
Type number
Sampling
frequency
(Msps)
Package
Name
Description
Version
ADC1213D125HN/C1 125
ADC1213D105HN/C1 105
ADC1213D080HN/C1 80
ADC1213D065HN/C1 65
HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
5. Block diagram
SDIO/DCS
SCLK/DCS
CFG (0 to 3)
CS
ERROR
CORRECTION AND
DIGITAL
SPI
SYNCP
SYNCN
PROCESSING
INAP
INAM
SWING_n
T/H
INPUT
STAGE
ADCA CORE
12-BIT
PIPELINED
D11 to D0
OTR
SERIALIZER A
CMLPA
CMLNA
8-bit
8-bit
10-bit
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
OUTPUT
BUFFER A
CLKP
CLKM
DLL
PLL
ERROR
CORRECTION AND
DIGITAL
CMLPB
CMLNB
SERIALIZER B
8-bit
8-bit
10-bit
PROCESSING
OUTPUT
BUFFER B
OTR
INBP
INBM
T/H
INPUT
STAGE
ADCB CORE
12-BIT
PIPELINED
D11 to D0
SWING_n
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ADC1213D
REFBT
REFBB
VCMB
SENSE VREF
REFAB
REFAT
VCMA
SCRAMBLER RESET
005aaa120
Fig 1. Block diagram
ADC1213D_SER_5
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 05 — 23 April 2010
2 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
6. Pinning information
6.1 Pinning
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
INAP
INAM
DGND
DGND
VDDD
CMLPA
CMLNA
VDDD
DGND
DGND
VDDD
CMLNB
CMLPB
VDDD
DGND
DGND
3
VCMA
REFAT
REFAB
AGND
CLKP
4
5
6
7
ADC1213D
8
CLKN
AGND
REFBB
REFBT
VCMB
INBM
9
10
11
12
13
14
INBP
005aaa121
Transparent top view
Fig 2. Pinning diagram
6.2 Pin description
Table 2.
Symbol
INAP
Pin description
Pin
1
Type [1]
Description
I
channel A analog input
INAM
2
I
channel A complementary analog input
channel A output common voltage
channel A top reference
channel A bottom reference
analog ground
VCMA
REFAT
REFAB
AGND
CLKP
3
O
O
O
G
I
4
5
6
7
clock input
CLKM
AGND
REFBB
REFBT
VCMB
8
I
complementary clock input
analog ground
9
G
O
O
O
10
11
12
channel B bottom reference
channel B top reference
channel B output common voltage
ADC1213D_SER_5
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 05 — 23 April 2010
3 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 2.
Pin description …continued
Symbol
INBM
Pin
13
14
15
16
17
Type [1]
Description
I
channel B complementary analog input
channel B analog input
analog power supply 3 V
analog power supply 3 V
SPI clock
INBP
I
VDDA
P
P
I
VDDA
SCLK/DCS
data format select
SDIO/DCS
18
I/O
SPI data input/output
duty cycle stabilizer
CS
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
I
chip select bar
AGND
RESET
SCRAMBLER
CFG0
G
I
analog ground
JEDEC digital IP reset
scrambler enable and disable
see Table 28 (input) or OTRA (output)[2]
see Table 28 (input) or OTRB (output)[2]
see Table 28 (input)
I
I/O
I/O
I/O
I/O
P
G
G
G
P
O
O
P
G
G
P
O
O
P
G
G
I
CFG1
CFG2
CFG3
see Table 28 (input)
VDDD
DGND
DGND
DGND
VDDD
CMLPB
CMLNB
VDDD
DGND
DGND
VDDD
CMLNA
CMLPA
VDDD
DGND
DGND
SYNCP
SYNCN
DGND
VDDD
SWING_0
SWING_1
DNC
digital power supply 1.8 V
digital ground
digital ground
digital ground
digital power supply 1.8 V
channel B output
channel B complementary output
digital power supply 1.8 V
digital ground
digital ground
digital power supply 1.8 V
channel A complementary output
channel A output
digital power supply 1.8 V
digital ground
digital ground
synchronization from FPGA
synchronization from FPGA
digital ground
I
G
P
I
digital power supply 1.8 V
JESD204 serial buffer programmable output swing
JESD204 serial buffer programmable output swing
do not connect
I
O
P
G
VDDA
analog power supply 3 V
analog ground
AGND
ADC1213D_SER_5
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 05 — 23 April 2010
4 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 2.
Pin description …continued
Symbol
AGND
VDDA
SENSE
VREF
Pin
52
53
54
55
56
Type [1]
Description
G
P
analog ground
analog power supply 3 V
reference programming pin
voltage reference input/output
analog power supply 3 V
I
I/O
P
VDDA
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
[2] OTRA stands for “OuT of Range” A. OTRB stands for “OuT of Range” B
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDDA
VDDD
ΔVCC
Tstg
Parameter
Conditions
Min
−0.4
−0.4
Max
+4.6
+2.5
Unit
V
[1]
[2]
analog supply voltage
digital supply voltage
supply voltage difference
storage temperature
ambient temperature
junction temperature
V
VDDA − VDDD
<tbd> <tbd>
V
−55
−40
-
+125
+85
°C
°C
°C
Tamb
Tj
125
[1] The supply voltage VDDA may have any value between −0.5 V and +7.0 V provided that the supply voltage
differences ΔVCC are respected.
[2] The supply voltage VDDD may have any value between −0.5 V and +5.0 V provided that the supply voltage
differences ΔVCC are respected.
8. Thermal characteristics
Table 4.
Thermal characteristics
Symbol
Rth(j-a)
Parameter
Conditions
Typ
17.8
6.8
Unit
K/W
K/W
[1]
[1]
thermal resistance from junction to ambient
thermal resistance from junction to case
Rth(j-c)
[1] Value for six layers board in still air with a minimum of 25 thermal vias.
9. Static characteristics
Table 5.
Symbol
Supplies
VDDA
Characteristics[1]
Parameter
Conditions
Min
Typ
Max
Unit
analog supply voltage
digital supply voltage
analog supply current
2.85
1.65
-
3.0
1.8
343
3.4
V
VDDD
1.95
-
V
IDDA
fclk = 125 Msps;
fi =70 MHz
mA
ADC1213D_SER_5
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 05 — 23 April 2010
5 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 5.
Symbol
IDDD
Characteristics[1] …continued
Parameter
Conditions
Min
Typ
Max
Unit
digital supply current
fclk = 125 Msps;
fi = 70 MHz
-
150
-
mA
Ptot
total power dissipation
power dissipation
fclk = 125 Msps
fclk = 105 Msps
fclk = 80 Msps
fclk = 65 Msps
-
-
-
-
-
-
1270
1150
995
885
30
-
-
-
-
-
-
mW
mW
mW
mW
mW
mW
P
power-down mode
standby mode
200
Digital inputs
Clock inputs: pins CLKP and CLKM, AC coupled
LVPECL
Vi(clk)dif
differential clock input
voltage
peak-to-peak
peak-to-peak
peak-to-peak
-
±0.8
±0.4
±1.5
-
-
-
V
V
V
LVDS
Vi(clk)dif
differential clock input
voltage
-
SINE wave
Vi(clk)dif
differential clock input
voltage
±0.8
LVCMOS mode
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.3VDDA
-
V
V
0.7VDDA
Logic inputs, Power-down: pins CFG0 to CFG3, SCRAMBLER, SWING_0, and SWING_1
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
-
0
-
V
-
0.66VDDD
-
V
−6
−30
-
-
+6
+30
μA
μA
IIH
SPI: pins CS, SDIO/DCS, and SCLK/DCS
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input capacitance
0
-
0.3VDDA
VDDA
+10
V
0.7VDDA
−10
−50
-
-
V
-
μA
μA
pF
IIH
CI
-
+50
4
-
ADC1213D_SER_5
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 05 — 23 April 2010
6 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 5.
Symbol
Characteristics[1] …continued
Parameter
Conditions
Min
Typ
Max
Unit
Analog inputs: pins INAP, INAM, INBP, and INBM
II
input current
track mode
track mode
track mode
track mode
−5
-
-
+5
-
μA
Ω
RI
input resistance
input capacitance
15
5
CI
-
-
pF
V
VI(cm)
common-mode input
voltage
0.9
1.5
2
Bi
input bandwidth
-
600
-
-
MHz
V
VI(dif)
differential input voltage peak-to-peak
1
2
Voltage controlled regulator output: pins VCMA and VCMB
VO(cm)
common-mode output
voltage
-
-
0.5VDDA
<tbd>
-
-
V
IO(cm)
common-mode output
current
μA
Reference voltage input/output: pin VREF
VVREF
voltage on pin VREF
output
input
0.5
0.5
-
-
1
1
V
V
Reference mode selection: pin SENSE
VSENSE voltage on pin SENSE
-
pin AGND;
-
V
VVREF; VDDA
Data outputs: CMLPA, CMLNA
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 000
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.5
-
-
-
-
V
V
V
V
1.65
1.8
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
1.35
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 001
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.45
1.625
1.8
-
-
-
-
V
V
V
V
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
1.275
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 010
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.4
1.6
1.8
1.2
-
-
-
-
V
V
V
V
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 011
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.35
1.575
1.8
-
-
-
-
V
V
V
V
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
1.125
ADC1213D_SER_5
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 05 — 23 April 2010
7 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Table 5.
Symbol
Characteristics[1] …continued
Parameter
Conditions
Min
Typ
Max
Unit
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 100
VOL
LOW-level output
voltage
DC coupled; output
AC coupled
-
-
-
-
1.3
-
-
-
-
V
V
V
V
1.55
1.8
VOH
HIGH-level output
voltage
DC coupled; output
AC coupled
1.05
Serial configuration: SYNCCP, SYNCCN
VIL
LOW-level input voltage differential; input
High-level input voltage differential; input
-
-
0.95
1.47
-
-
V
V
VIH
Accuracy
INL
integral non-linearity
−5
±1
+5
LSB
LSB
DNL
differential non-linearity no missing codes
guaranteed
−0.95
±0.5
+0.95
Eoffset
EG
offset error
-
-
-
±2
-
-
-
mV
%
gain error
full-scale
± 0.5
<tbd>
MG(CTC)
channel-to-channel gain
matching
%
Supply
PSRR
power supply rejection
ratio
100 mV (p-p) on VDDA
-
35
-
dBc
[1] Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature
range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode;
100 Ω differential applied to serial outputs; unless otherwise specified.
ADC1213D_SER_5
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 05 — 23 April 2010
8 of 41
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10. Dynamic characteristics
Table 6.
Characteristics[1]
Symbol Parameter
Conditions
ADC1213D065
Min Typ
ADC1213D080
Max Min Typ
ADC1213D105
Max Min Typ
ADC1213D125
Max Min Typ
Unit
Max
Analog signal processing
α2H
second harmonic level
fi = 3 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
87
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
87
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
86
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
88
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
86
86
86
87
85
85
84
85
82
82
81
83
α3H
third harmonic level
86
86
85
87
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
85
85
85
86
84
84
83
84
81
81
80
82
THD
ENOB
SNR
SFDR
total harmonic distortion fi = 3 MHz
fi = 30 MHz
85
85
84
86
84
84
84
85
fi = 70 MHz
83
83
82
83
fi = 170 MHz
80
80
79
81
effective number of bits
signal-to-noise ratio
fi = 3 MHz
11.3
11.3
11.2
11.1
70.0
69.5
69.2
68.8
86
11.3
11.3
11.2
11.1
69.9
69.5
69.2
68.8
86
11.3
11.3
11.2
11.1
69.8
69.5
69.1
68.7
85
11.3
11.2
11.2
11.1
69.6
69.4
69.0
68.6
87
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
bits
bits
bits
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
spurious-free dynamic
range
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
85
85
85
86
84
84
83
84
81
81
80
82
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Table 6.
Characteristics[1] …continued
Symbol Parameter
Conditions
ADC1213D065
Min Typ
ADC1213D080
Max Min Typ
ADC1213D105
Max Min Typ
ADC1213D125
Max Min Typ
Unit
Max
IMD
intermodulation distortion fi = 3 MHz
fi = 30 MHz
-
-
-
-
-
89
-
-
-
-
-
-
-
-
-
-
89
88
87
85
-
-
-
-
-
-
-
-
-
-
88
88
86
83
100
-
-
-
-
-
-
-
-
-
-
89
88
86
84
100
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
88
fi = 70 MHz
87
fi = 170 MHz
84
αct(ch)
crosstalk between
channels
fi = 70 MHz
100
100
[1] Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V,
DDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless otherwise specified.
V
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11. Clock and digital output timing
Table 7.
Symbol Parameter
Characteristics[1]
Conditions
ADC1213D065
ADC1213D080
ADC1213D105
ADC1213D125
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Clock timing input: pins CLKP and CLKM
fclk
clock frequency
data latency time
clock duty cycle
20
-
65
60
-
80
75
-
105
226
70
100
160
30
-
125
170
70
Msps
ns
tlat(data)
δclk
clock cycles
307
30
-
850
70
250
30
-
283
70
190
30
-
-
DCS_EN = 1:
en
50
50
50
50
%
DCS_EN = 0:
dis
45
50
55
45
50
55
45
50
55
45
50
55
%
td(s)
sampling delay time
wake-up time
-
-
0.8
-
-
-
-
0.8
-
-
-
-
0.8
-
-
-
-
0.8
-
-
ns
ns
twake
<tbd>
<tbd>
<tbd>
<tbd>
[1] Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V,
DDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode; 100 W differential applied to serial outputs; unless otherwise specified.
V
ADC1213D series
NXP Semiconductors
ADC1213D series
12. Serial output timings
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
• 3.125 Gbps data rate
• Tamb = 25 °C
• DC coupling with two different receiver common-mode voltages
005aaa088
Fig 3. Eye diagram at 1 V receiver common-mode
005aaa089
Fig 4. Eye diagram at 2 V receiver common-mode
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ADC1213D series
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13. SPI timing
Table 8.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Serial Peripheral Interface timings
tw(SCLK)
tw(SCLKH)
tw(SCLKL)
tsu
SCLK pulse width
SCLK HIGH pulse width
SCLK LOW pulse width
set-up time
40
16
16
5
-
-
-
-
-
-
-
-
-
ns
-
ns
-
ns
data to SCLKH
CS to SCLKH
data to SCLKH
CS to SCLKH
-
ns
5
-
ns
th
hold time
2
-
ns
2
-
ns
fclk(max)
maximum clock frequency
-
25
MHz
[1] Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature
range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM,INBM) = −1 dBFS; internal reference mode;
100 Ω differential applied to serial outputs; unless otherwise specified.
t
t
su
w(SCLKL)
t
h
t
h
su
t
t
w(SCLKH)
t
w(SCLK)
CS
SCLK
SDIO
W1
W0
A12
A11
D2
D1
D0
R/W
005aaa065
Fig 5. SPI timings
14. Application information
14.1 Analog inputs
14.1.1 Input stage description
The analog input of the ADC1213D supports differential or single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (VI(cm)) on pins INxP and INxM set to 0.5VDDA
.
The full scale analog input voltage range is configurable between ± 1 V (p-p) and
± 2 V (p-p) via a programmable internal reference (see Section 14.2 and Table 21 for
further details).
Figure 6 shows the equivalent circuit of the sample and hold input stage, including
ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
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ADC1213D series
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ADC1213D series
Package
ESD
Parasitics
Switch
R
= 15 Ω
on
4 pF
1, 14
INAP
INBP
C
s
Internal
clock
Switch
on
R
= 15 Ω
4 pF
2, 13
INAM
INBM
C
s
Internal
clock
005aaa069
Fig 6. Input sampling circuit
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
14.1.2 Anti-kickback circuitry
Anti-kickback circuitry (RC filter in Figure 7) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
R
INP
C
R
INM
005aaa073
Fig 7. Anti-kickback circuit
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
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ADC1213D series
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ADC1213D series
Table 9.
RC coupling versus input frequency - typical values
Input frequency
3 MHz
R
C
25 Ω
12 Ω
12 Ω
12 pF
8 pF
8 pF
70 MHz
170 MHz
14.1.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 8 would be suitable for a baseband application.
100 nF
25 Ω
INAP
100 nF
ADT1-1WT
Analog
INBP
input
25 Ω
12 pF
100 nF
25 Ω
100 nF
25 Ω
INAM
INBM
VCM
100 nF
100 nF
005aaa070
Fig 8. Single transformer configuration
ADT1-1WT
ADT1-1WT
12 Ω
12 Ω
INAP
INBP
100 nF
50 Ω
50 Ω
50 Ω
Analog
input
8.2 pF
50 Ω
INAM
INBM
100 nF
VCM
100 nF
100 nF
005aaa071
Fig 9. Dual transformer configuration
The configuration shown in Figure 9 is recommended for high frequency applications. In
both cases, the choice of transformer will be a compromise between cost and
performance.
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ADC1213D series
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ADC1213D series
14.2 System reference and power management
14.2.1 Internal/external reference
The ADC1213D has a stable and accurate built-in internal reference voltage to adjust the
ADC full-scale. This reference voltage can be set internally via SPI or with pin VREF an
SENSE (see Figure 11, Figure 12, Figure 13 and Figure 14), in 1 dB steps between 0 dB
and −6 dB, via SPI control bits INTREF[2:0] (when bit INTREF_EN = 1; see Table 21).
The equivalent reference circuit is shown in Figure 10. External reference is also possible
by providing a voltage on pin VREF as described in Figure 13.
REFT
REFERENCE
REFB
AMP
VREF
EXT_ref
EXT_ref
BANDGAP
REFERENCE
BUFFER
ADC CORE
SENSE
SELECTION
LOGIC
005aaa164
Fig 10. Reference equivalent schematic
Table 10 shows how to choose between the different internal/external modes:
Table 10. Reference modes
Mode
SPI bit, “Internal
reference”
SENSE pin
VREF pin
Full Scale,
V (p-p)
Internal (Figure 11)
Internal (Figure 12)
External (Figure 13)
0
0
0
1
GND
330 pF capacitor
to GND
2
VREF pin = SENSE pin and
330 pF capacitor to GND
1
VDDA
External voltage 1 to 2
from 0.5 V to 1 V
Internal, SPI mode
(Figure 14)
VREF pin = SENSE pin and
330 pF capacitor to GND
1 to 2
Figure 11 to Figure 14 indicate how to connect the SENSE and VREF pins.
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ADC1213D series
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ADC1213D series
VREF
VREF
330 pF
330
pF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
005aaa116
005aaa117
Fig 11. Internal reference, 2 V (p-p) full-scale
Fig 12. Internal reference, 1 V (p-p) full-scale
VREF
VREF
330 pF
0.1 μF
V
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
VDDA
005aaa119
005aaa118
Fig 13. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
Fig 14. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
14.2.2 Reference gain control
The reference gain is programmable between 0 dB to −6 dB in steps of 1 dB via the SPI
(see Table 21). The corresponding full scale input voltage range varies between 2 V (p-p)
and 1 V (p-p), as shown in Table 11:
Table 11. Reference SPI gain control
INTREF[2:0]
000
Level
0 dB
Full Scale, V (p-p)
2
001
−1 dB
−2 dB
−3 dB
−4 dB
−5 dB
−6 dB
not used
1.78
1.59
1.42
1.26
1.12
1
010
011
100
101
110
111
x
14.2.3 Common-mode output voltage (VI(cm)
)
An 0.1 μF filter capacitor should be connected between on the one hand the pins VCMA
and VCMB and on the other hand ground to ensure a low-noise common-mode output
voltage. When AC-coupled, these pins can be used to set the common-mode reference
for the analog inputs, for instance via a transformer middle point.
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ADC1213D series
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ADC1213D series
PACKAGE
ESD
PARASITICS
COMMON MODE
REFERENCE
1.5 V
VCMA
VCMB
0.1 μF
ADC CORE
005aaa077
Fig 15. Reference equivalent schematic
14.2.4 Biasing
The common-mode output voltage, VO(cm), should be set externally to 1.5 V (typical). The
common-mode input voltage, VI(cm), at the inputs to the sample and hold stage
(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal
performance.
14.3 Clock input
14.3.1 Drive modes
The ADC1213D can be driven differentially (SINE, LVPECL or LVDS) with little or no
influence on dynamic performances. It can also be driven by a single-ended LVCMOS
signal connected to pin CLKP (CLKM should be connected to ground via a capacitor).
CLKP
CLKM
LVCMOS
clock input
CLKP
CLKM
LVCMOS
clock input
005aaa174
005aaa053
a. Rising edge LVCMOS
b. Falling edge LVCMOS
Fig 16. LVCMOS single-ended clock input
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ADC1213D series
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ADC1213D series
CLKP
CLKM
Sine
clock input
CLKP
CLKM
Sine
clock input
005aaa173
005aaa054
a. Sine clock input
b. Sine clock input (with transformer)
CLKP
CLKP
LVPECL
clock input
LVDS
clock input
CLKM
CLKM
005aaa055
005aaa172
c. LVDS clock input
d. LVPECL clock input
Fig 17. Differential clock input
14.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode
voltage of the differential input stage is set via internal resistors of 5 kΩ resistors.
Package
ESD
Parasitics
CLKP
CLKM
V
cm(clk)
SE_SEL SE_SEL
5 kΩ
5 kΩ
005aaa081
Fig 18. Equivalent input circuit
Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If
single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit
SE_SEL.
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ADC1213D series
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ADC1213D series
If single-ended is implemented without setting SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
14.3.3 Clock input divider
The ADC1413D contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = 1; see Table 20). This feature allows the user to deliver a higher
clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
14.3.4 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = 1; see Table 20), the circuit can handle signals with duty cycles of between
30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the
input clock signal should have a duty cycle of between 45 % and 55 %.
Table 12. Duty cycle stabilizer
DCS_enable SPI
Description
0
1
duty cycle stabilizer disable
duty cycle stabilizer enable
14.4 Digital outputs
14.4.1 Serial output equivalent circuit
The JESD204A standard specify that in case of connecting the receiver and the
transmitter in DC coupling, both of them need to be provided by the same supply.
VDDD
50 Ω
CMLPA/CLMPB
100 Ω
RECEIVER
CMLNA/CLMNB
AGND
+
−
12 mA to 26 mA
005aaa082
Fig 19. CML output connection to the receiver in DC coupling
The output should be terminated when 100 Ω (typical) has been reached at the receiver
side.
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ADC1213D series
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ADC1213D series
VDDD
50 Ω
CMLPA/CMLPB
10 nF
100 Ω
RECEIVER
CMLNA/CMLNB
10 nF
+
−
12 mA to 26 mA
005aaa083
Fig 20. CML output connection to the receiver in AC coupling
14.5 JESD204A serializer
14.5.1 Digital JESD204A formatter
The block placed after the ADC cores is used to implement all functionalities of the
JESD204A standard. This ensures signal integrity and guarantees the clock and the data
recovery at the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
M CONVERTERS
L LANES
FRAME
TO
OCTETS
ALIGNMENT
CHARACTER
GENERATOR
N bits from Cr
CS bits for control
+
8-bit/
10-bit
0
F octets
SCRAMBLER
SER
LANE0
TX transport layer
SYNC~
TX CONTROLLER
samples stream to
lane stream mapping
FRAME
TO
OCTETS
ALIGNMENT
CHARACTER
GENERATOR
N bits from Cr
CS bits for control
+
8-bit/
10-bit
M−1
F octets
SCRAMBLER
SER
LANE1
N' = N+CS
S samples per frame cycle
CF: position of controls bits
HD: frame boundary break
Padding with Tails bits (TT)
005aaa084
Mx(N'xS) bits
Lx(F) octets
L octets
Fig 21. General overview of the JESD204A serializer
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ADC1213D series
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ADC1213D series
ADC_MODE[1:0]
SCRAMB_IN_MODE[1:0]
PRBS
11
N
&
CS
LANE_MODE[1:0]
8-bit/
DUMMY
12 + 1 10
12 + 1
N + CS
8
00
01
SCR
10 00
10-bit
PRBS
LANE_POLARITY
ADC_PD
ADCA
'0'
01
SER
12 + 1 00
'0/1'
10
PRBS
11
× 1
× F
frame CLK
char CLK
PLL
AND
DLL
FSM (f assy,
char repl, ILA,
test mode)
FRAME
ASSEMBLY
SWING_SEL[2:0]
× 10F bit CLK
PRBS
'0/1'
'0'
11
10
SER
ADCB
12 + 1 00
01
ADC_D
LANE_POLARITY
PRBS
8
01
00
8-bit/
10-bit
10 00
SCR
N
&
CS
12 + 1 10
11
12 + 1
N + CS
DUMMY
PRBS
LANE_MODE[1:0]
SCAMB_IN_MODE[1:0]
ADC_MODE[1:0]
005aaa175
sync_request
Fig 22. Detailed view of the JESD204A serializer with debug functionality
14.5.2 ADC core output codes versus input voltage
Table 13 shows the data output codes for a given analog input voltage.
Table 13. Output codes versus input voltage
INP-INM (V)
< −1
Offset binary
0000 0000 0000
0000 0000 0000
0000 0000 0001
0000 0000 0010
0000 0000 0011
0000 0000 0100
....
Two’s complement
1000 0000 0000
1000 0000 0000
1000 0000 0001
1000 0000 0010
1000 0000 0011
1000 0000 0100
....
OTR
1
0
0
0
0
0
0
0
0
0
0
0
−1.0000000
−0.9995117
−0.9990234
−0.9985352
−0.9980469
....
−0.0009766
−0.0004883
0.0000000
+0.0004883
+0.0009766
0111 1111 1110
0111 1111 1111
1000 0000 0000
1000 0000 0001
1000 0000 0010
1111 1111 1110
1111 1111 1111
0000 0000 0000
0000 0000 0001
0000 0000 0010
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ADC1213D series
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ADC1213D series
Table 13. Output codes versus input voltage …continued
INP-INM (V)
Offset binary
....
Two’s complement
....
OTR
....
0
0
0
0
0
0
1
+0.9980469
+0.9985352
+0.9990234
+0.9995117
+1.0000000
> +1
1111 1111 1011
1111 1111 1100
1111 1111 1101
1111 1111 1110
1111 1111 1111
1111 1111 1111
0111 1111 1011
0111 1111 1100
0111 1111 1101
0111 1111 1110
0111 1111 1111
0111 1111 1111
14.6 Serial Peripheral Interface (SPI)
14.6.1 Register description
The ADC1213D serial interface is a synchronous serial communications port allowing for
easy interfacing with many industry microprocessors. It provides access to the registers
that control the operation of the chip in both read and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
SCLK acts as the serial clock, and CS acts as the serial chip select bar.
Each read/write operation is sequenced by the CS signal and enabled by a LOW level to
to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte
(see Table 14).
Table 14. Instruction bytes for the SPI
MSB
LSB
0
Bit
7
6
5
4
3
2
1
Description
R/W[1]
A7
W1
A6
W0
A5
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
[1] R/W indicates whether a read or write transfer occurs after the instruction byte
Table 15. Read or Write mode access description
R/W[1]
Description
0
1
Write mode operation
Read mode operation
[1] Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
Table 16. Number of bytes to be transferred
W1
0
W0
0
Number of bytes
1 byte transferred
2 bytes transferred
3 bytes transferred
0
1
1
0
1
1
4 or more bytes transferred
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ADC1213D series
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ADC1213D series
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. The falling edge on CS in combination with a rising edge on SCLK determine the start
of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can be vary in length but will
always be a multiple of 8 bits. The MSB is always sent first (for instruction and data
bytes):
CSB
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa086
Fig 23. Transfer diagram for two data bytes (3-wire type)
14.6.2 Channel control
The two ADC channels can be configured at the same time or separately. By using the
register “Channel index”, the user can choose which ADC channel will receive the next
SPI-instruction. By default the channel A and B will receive the same instructions in write
mode. In read mode only A is active.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 17. Register allocation map
Addr
Hex
Register name
R/W[1] Bit definition
Default[2]
Bin
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC control register
0003
0005
Channel index
R/W
R/W
RESERVED[5:0]
ADCB
ADCA
1111 1111
Reset and
Operating modes
SW_
RST
RESERVED[2:0]
-
-
-
PD[1:0]
0000 0000
0006
0008
Clock
R/W
R/W
-
-
-
-
-
SE_SEL
-
DIFF_SE
CLKDIV2_
SEL
DCS_EN
0000
000X
Vref
-
INTREF_
EN
INTREF[2:0]
0000 0000
0013
0014
0015
0016
Offset
R/W
R/W
R/W
R/W
-
-
-
-
DIG_OFFSET[5:0]
-
0000 0000
0000 0000
0000 0000
0000 0000
Test pattern 1
Test pattern 2
Test pattern 3
-
-
TESTPAT_1[2:0]
-
TESTPAT_2[13:6]
TESTPAT_3[5:0]
-
-
JESD204A control
0801
Ser_Status
R
RXSYNC_
ERROR
RESERVED[2:0]
0
0
0
POR_TST
0
RESERVED 0000 0000
0802
Ser_Reset
R/W
SW_
RST
0
0
0
0
0
0
FSM_SW_
RST
0
0000 0000
0803
0805
Ser_Cfg_Setup
Ser_Control1
R/W
R/W
0
0
CFG_SETUP[3:0]
0000 ****
TriState_
CFG_PAD
SYNC_
POL
SYNC_SING
LEENDED
1
0
RESERVED[2:0]
0100 1001
0806
Ser_Control2
R/W
0
0
0
0
0
0
SWAP_
LANE_1_2
SWAP_
0000 00**
ADC_0_1
0808
0809
080A
080B
0820
0821
0822
0823
0824
0825
Ser_Analog_Ctrl R/W
Ser_ScramblerA R/W
Ser_ScramblerB R/W
0
0
0
0
0
SWING_SEL[2:0]
0000 00**
0000 0000
1111 1111
0000 0000
1110 1101
0000 1010
*000 000*
0000 0***
000* ****
LSB_INIT[6:0]
MSB_INIT[7:0]
Ser_PRBS_Ctrl
Cfg_0_DID
Cfg_1_BID
Cfg_3_SCR_L
Cfg_4_F
R/W
0
0
0
0
0
0
0
PRBS_TYPE[1:0]
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
DID[7:0]
0
SCR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BID[3:0]
0
0
0
L
F[2:0]
0
Cfg_5_K
0
K[4:0]
0
Cfg_6_M
0
0
0
M
0000 000*
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 17. Register allocation map …continued
Addr
Hex
Register name
R/W[1] Bit definition
Default[2]
Bin
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0826
0827
0828
0829
082C
082D
084C
084D
0870
Cfg_7_CS_N
Cfg_8_Np
R/W*
R
0
CS[0]
0
0
N[3:0]
0100 0***
0000 1111
0000 0000
*000 0000
0001 1011
0001 1100
**** ****
0
0
0
0
0
0
0
0
0
0
0
0
NP[4:0]
Cfg_9_S
R/W*
R/W*
R/W*
R/W*
R
0
0
0
0
0
0
S
Cfg_10_HD_CF
Cfg_01_2_LID
Cfg_02_2_LID
Cfg01_13_FCHK
Cfg02_13_FCHK
LaneA_0_Ctrl
HD
0
0
CF[1:0]
LID[4:0]
LID[4:0]
0
FCHK[7:0]
FCHK[7:0]
0
R
**** ****
R/W
0
0
SCR_IN_
MODE
LANE_MODE[1:0]
LANE_MODE[1:0]
LANE_
POL
LANE_CLK_
POS_EDGE
LANE_PD
LANE_PD
0000 000*
0871
LaneB_0_Ctrl
R/W
SCR_IN_
MODE
0
LANE_
POL
LANE_CLK_
POS_EDGE
0000 000*
0890
0891
ADCA_0_Ctrl
ADCB_0_Ctrl
R/W
R/W
0
0
0
0
ADC_MODE[1:0]
ADC_MODE[1:0]
0
0
0
0
0
0
ADC_PD
ADC_PD
0000 000*
0000 000*
[1] an "*" in the Access column means that this register is subject to control access conditions in Write mode.
[2] an "*" in the Default column replaces a bit of which the value depends on the binary level of external pins (e.g. CFG[3:0], Swing[1:0], Scrambler).
ADC1213D series
NXP Semiconductors
ADC1213D series
14.6.3 Register description
14.6.3.1 ADC control register
Table 18. Register channel Index (address 0003h)
Bit
Symbol
Access Value
Description
7 to 2 RESERVED[5:0]
-
111111
reserved
1
0
ADCB
ADCA
R/W
ADCB will get the next SPI command:
ADCB not selected
0
1
ADCB selected
R/W
ADCA will get the next SPI command:
ADCA not selected
0
1
ADCA selected
Table 19. Register reset and Power-down mode (address 0005h)
Bit
Symbol
Access Value
Description
7
SW_RST
R/W
reset digital part:
no reset
0
1
performs a reset of the digital part
reserved
6 to 4 RESERVED[2:0]
3 to 2
1 to 0 PD[1-0]
-
000
-
-
00
not used
R/W
power-down mode:
normal (power-up)
full power-down
sleep
00
01
10
11
normal (power-up)
Table 20. Register clock (address 0006h)
Bit
7 to 5
4
Symbol
-
Access Value
Description
-
000
not used
SE_SEL
R/W
select SE clock input pin:
0
Select CLKM input
1
Select CLKP input
3
DIFF_SE
R/W
differential/single ended clock input select:
0
1
0
Fully differential
Single-ended
2
1
-
-
not used
CLKDIV2_SEL
R/W
select clock input divider by 2:
0
disable
1
active
0
DCS_EN
R/W
duty cycle stabilizer enable:
0
1
disable
active
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Table 21. Register Vref (address 0008h)
Bit
7 to 4
3
Symbol
Access Value
Description
-
-
0000
not used
INTREF_EN
R/W
enable internal programmable VREF mode:
disable
0
1
active
2 to 0 INTREF[2:0]
R/W
programmable internal reference:
0 dB (FS=2 V)
000
001
010
011
100
101
110
111
−1 dB (FS=1.78 V)
−2 dB (FS=1.59 V)
−3 dB (FS=1.42 V)
−4 dB (FS=1.26 V)
−5 dB (FS=1.12 V)
−6 dB (FS=1 V)
not used
Table 22. Digital offset adjustment (address 0013h)
Register offset: (address 0013h)
Decimal
DIG_OFFSET[5:0]
+31
...
011111
...
+31 LSB
...
0
000000
...
0
...
...
−32
100000
−32 LSB
Table 23. Register test pattern 1 (address 0014h)
Bit
Symbol
Access Value
Description
7 to 3
-
-
00000
not used
2 to 0 TESTPAT_1[2:0]
R/W
digital test pattern:
000
001
010
011
100
101
110
111
off
mid-scale
− FS
+ FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern, to be written in register 0015h and 0016h
‘010101...’
‘101010...’
Table 24. Register test pattern 2 (address 0015h)
Bit
Symbol
Access Value
Description
7 to 0
TESTPAT_2[13:6]
R/W
00000000 custom digital test pattern (bit 13 to 6)
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Table 25. Register test pattern 3 (address 0016h)
Bit
7 to 3 TESTPAT_3[5:0]
2 to 0
Symbol
Access Value
Description
R/W
-
00000
custom digital test pattern (bit 5 to 0)
-
000
not used
14.6.4 JESD204A digital control registers
Table 26. SER status (address 0801h)
Bit
Symbol
Access Value
Description
7
RXSYNC_ERROR R/W
0
set to 1 when a synchronization error occurs
6 to 4 RESERVED[2:0]
-
010
0
reserved
3 to 2
-
-
not used
1
0
POR_TST
RESERVED
R
-
1
power-on-reset
reserved
-
Table 27. SER reset (address 0802h)
Bit
7
Symbol
SW_RST
-
Access Value
Description
R/W
-
0
initiates a software reset of the JEDEC204A unit
not used
6 to 4
3
000
0
FSM_SW_RST
R/W
initiates a software reset of the internal state machine of JEDEC204A
unit
2 to 0
-
-
000
not used
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Table 28. SER cfg set-up (address 0803h)[1]
Bit
Symbol
Access Value
Description
7 to 4
-
R
0000
not used
3 to 0 CFG_SETUP[3:0]
R/W
0000
(reset)
defines quick JESD204A configuration. These settings overrule the
CFG_PAD configuration
0000
ADC0: ON; ADC1: ON; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9;
M = 2; L = 2[2]
0001
ADC0: ON; ADC1: ON; Lane0: ON; Lane1: OFF; F = 4; HD = 0; K = 5;
M = 2; L = 1[2]
0010
0011
ADC0: ON; ADC1: ON; Lane0: OFF[2]
ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17;
M = 1; L = 2[2]
0100
0101
0110
0111
1000
ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17;
M = 1; L = 2; SWAP_ADC_0_1 = 1[2]
ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9;
M = 1; L = 1[2]
ADC0: ON; ADC1: OFF; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9;
M = 1; L = 1; SWAP_LANE_1_2 = 1[2]
ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9;
M = 1; L = 1; SWAP_ADC_0_1 = 1[2]
ADC0: OFF; ADC1: ON; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9;
M = 1; L = 1; SWAP_ADC_0_1[2]
1001 to
1101
reserved
1110
ADC0: OFF; ADC1: OFF; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9;
M = 2; L = 2; loop alignment = 1[2]
1111
ADC0: OFF; ADC1: OFF; Lane0: OFF; Lane1: OFF; F = 2; HD = 0;
K = 9; M = 2; L = 2 → PD[2]
[1] The default value for this register depends on the external pull-up/pull-down on CFG0, CFG1, CFG2 or CFG3. Writing to the register
overwrites this value.
[2] F: number of byte per frame; HD: High density; K: number of frames per multi frame; M: number of converters; L: number of lanes
See the information about the JESD204A standard on the JEDEC web site.
Table 29. SER control1 (address 0805h)
Bit
7
Symbol
Access Value
Description
-
R
0
not used
6
TRISTATE_CFG_PAD
R/W
1
CFG pads (3 to 0) are set to high-impedance. Switch to 0
automatically after start-up or reset.
5
4
3
SYNC_POL
R/W
defines the sync signal polarity:
0
synchronization signal is active low
synchronization signal is active high
defines the input mode of the sync signal:
synchronization input mode is set in Differential mode
synchronization input mode is set in Single-ended mode
not used
1
SYNC_SINGLE_ENDED R/W
0
1
1
-
R
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Table 29. SER control1 (address 0805h) …continued
Bit
Symbol
Access Value
Description
2
REV_SCR
-
enables swapping bits at the scrambler input
0
1
-
LSB are swapped to MSB at the scrambler input
1
0
REV_ENCODER
REV_SERIAL
enables swapping bits at the 8b/10b encoder input:
0
1
-
LSB are swapped to MSB at the 8b/10b encoder input
enables swapping bits at the lane input (before serializer):
0
1
LSB are swapped to MSB at the lane input
Table 30. SER control2 (address 0806h)
Bit
7 to 2
1
Symbol
Access Value
Description
-
R
000000
not used
SWAP_LANE_1_2
R/W
controls the JESD204A output multiplexer:
0
1
outputs of the JESD204A unit are swapped. (Output0 is
connected to Lane1, Output1 is connected to Lane0)
0
SWAP_ADC_0_1
R/W
controls the JESD204A input multiplexer:
0
1
inputs of the JESD204A unit are swapped. (ADC0 output is
connected to Input1, ADC1 is connected to Input0)
Table 31. SER analog ctrl (address 0808h)
Bit
Symbol
Access Value
Description
7 to 3
-
R
00000
not used
2 to 0 SWING_SEL[2:0]
R/W
0**
defines the swing output for the lane pads
Table 32. SER scramblerA (address 0809h)
Bit
Symbol
Access Value
Description
7
-
R
0
not used
6 to 0 LSB_INIT[6:0]
R/W
0000000 defines the initialization vector for the scrambler polynomial
(lower)
Table 33. SER scramblerB (address 080Ah)
Bit Symbol Access Value
Description
7 to 0 MSB_INIT[7:0]
R/W
11111111 defines the initialization vector for the scrambler polynomial
(upper)
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Table 34. SER PRBS Ctrl (address 080Bh)
Bit
Symbol
Access Value
Description
7 to 2
-
R
000000
not used
1 to 0 PRBS_TYPE[1:0]
R/W
defines the type of Pseudo-Random Binary Sequence (PRBS)
generator to be used:
00 (reset)
PRBS-7
PRBS-7
PRBS-23
PRBS-31
01
10
11
Table 35. Cfg_0_DID (address 0820h)
Bit Symbol Access Value
7 to 0 DID[7:0]
Description
R
11101101 defines the device (= link) identification number
Table 36. Cfg_1_BID (address 0821h)
Bit
Symbol
Access Value
Description
7 to 4
-
R
0000
not used
3 to 0 BID[3:0]
R/W
1010
defines the bank ID – extension to DID
Table 37. Cfg_3_SCR_L (address 0822h)
Bit
7
Symbol
Access Value
Description
SCR
R/W
R
*
scrambling enabled
6 to 1
0
-
000000
not used
L
R/W
*
defines the number of lanes per converter device, minus 1
Table 38. Cfg_4_F (address 0823h)
Bit
Symbol
Access Value
Description
7 to 3
-
R
00000
not used
2 to 0 F[2:0]
R/W
***
defines the number of octets per frame, minus 1
Table 39. Cfg_5_K (address 0824h)
Bit
Symbol
Access Value
Description
7 to 5
-
R
000
not used
4 to 0 K[4:0]
R/W
*****
defines the number of frames per multiframe, minus 1
Table 40. Cfg_6_M (address 0825h)
Bit
7 to 1
0
Symbol
Access Value
Description
-
R
0000000 not used
M
R/W
*
defines the number of converters per device, minus 1
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Table 41. Cfg_7_CS_N (address 0826h)
Bit
7
Symbol
Access Value
Description
-
R
0
not used
6
CS[0]
-
R/W
R
*
defines the number of control bits per sample, minus 1
not used
5 to 4
00
****
3 to 0 N[3:0]
R/W
defines the converter resolution
Table 42. Cfg_8_Np (address 0827h)
Bit
Symbol
Access Value
Description
7 to 5
-
R
000
not used
4 to 0 NP[4:0]
R/W
*****
defines the total number of bits per sample, minus 1
Table 43. Cfg_9_S (address 0828h)
Bit
7 to 1
0
Symbol
Access Value
Description
-
R
0000000 not used
S
R/W
1
defines number of samples per converter per frame cycle
Table 44. Cfg_10_HD_CF (address 0829h)
Bit
7
Symbol
Access Value
Description
HD
-
R/W
R
*
defines high density format
6 to 2
00000
not used
1 to 0 CF[1:0]
R/W
**
defines number of control words per frame clock cycle per link.
Table 45. Cfg01_2_LID (address 082Ch)
Bit
Symbol
Access Value
Description
7 to 5
-
R
000
not used
4 to 0 LID[4:0]
R/W
11011
defines lane1 identification number
Table 46. Cfg02_2_LID (address 082Dh)
Bit
Symbol
Access Value
Description
7 to 5
-
R
000
not used
4 to 0 LID[4:0]
R/W
11100
defines lane2 identification number
Table 47. Cfg02_13_fchk (address 084Ch)
Bit Symbol Access Value
********
Description
7 to 0 FCHK[7:0]
R
defines the checksum value for lane1
checksum corresponds to the sum of all the link configuration
parameters modulo 256 (as defined in JEDEC Standard
No.204A)
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Table 48. Cfg01_13_fchk (address 084Dh)
Bit
Symbol
Access Value
********
Description
7 to 0 FCHK[7:0]
R
defines the checksum value for lane1
checksum corresponds to the sum of all the link configuration
parameters module 256 (as defined in JEDEC Standard
No.204A)
Table 49. LaneA_0_ctrl (address 0870h)
Bit
7
Symbol
Access Value
Description
-
R
0
not used
6
SCR_IN_MODE
R/W
defines the input type for scrambler and 8-bit/10-bit units:
0 (reset)
(normal mode) = Input of the scrambler and 8-bit/10-bit units is
the output of the frame assembly unit.
1
input of the scrambler and 8-bit/10-bit units is the PRSB
generator (PRBS type is defined with “PRBS_TYPE”
(Ser_PRBS_ctrl register)
5 to 4 LANE_MODE[1:0]
R/W
defines output type of Lane output unit:
00 (reset)
normal mode: Lane output is the 8-bit/10-bit output unit
constant mode: Lane output is set to a constant (0 × 0)
toggle mode: Lane output is toggling between 0 × 0 and 0 × 1
01
10
11
PRBS mode: Lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_ctrl register)
3
2
-
R
0
not used
LANE_POL
R/W
defines lane polarity:
0
lane polarity is normal
1
lane polarity is inverted
1
0
LANE_CLK_POS_EDGE R/W
defines lane clock polarity:
0
lane clock provided to the serializer is active on positive edge
lane clock provided to the serializer is active on negative edge
lane power-down control:
1
Lane_PD
R/W
0
1
lane is operational
lane is in Power-down mode
Table 50. LaneB_0_ctrl (address 0871h)
Bit
7
Symbol
Access Value
Description
-
R
0
not used
6
SCR_IN_MODE
R/W
defines the input type for scrambler and 8b/10b units:
0 (reset)
(normal mode) = Input of the scrambler and 8b/10b units is the
output of the Frame Assembly unit.
1
input of the scrambler and 8b/10b units is the PRBS generator
(PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_ctrl
register)
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Table 50. LaneB_0_ctrl (address 0871h) …continued
Bit
Symbol
Access Value
Description
5 to 4 LANE_MODE[1:0]
R/W
defines output type of lane output unit:
00 (reset)
normal mode: Lane output is the 8b/10b output unit
constant mode: Lane output is set to a constant (0x0)
toggle mode: Lane output is toggling between 0x0 and 0x1
01
10
11
PRBS mode: Lane output is the PRSB generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_ctrl register)
3
2
-
R
0
not used
LANE_POL
R/W
defines lane polarity:
0
lane polarity is normal
1
lane polarity is inverted
1
0
LANE_CLK_POS_EDGE R/W
defines lane clock polarity:
0
lane clock provided to the serializer is active on positive edge
lane clock provided to the serializer is active on negative edge
lane power-down control:
1
Lane_PD
R/W
0
1
lane is operational
lane is in Power-down mode
Table 51. ADCA_0_ctrl (address 0890h)
Bit
Symbol
Access Value
Description
7 to 6
-
R
00
not used
5 to 4 ADC_MODE[1:0]
R/W
defines input type of JESD204A unit:
ADC output is connected to the JESD204A input
not used
00 (reset)
01
10
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[11:0] = “100110111010”
11
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE” (Ser_PRBS_ctrl register)
3 to 1
0
-
R
000
not used
ADC_PD
R/W
ADC power-down control:
ADC is operational
ADC is in Power-down mode
0
1
Table 52. ADCB_0_ctrl (address 0891h)
Bit
Symbol
Access Value
Description
7 to 6
-
R
00
not used
5 to 4 ADC_MODE[1:0]
R/W
defines input type of JESD204A unit
00 (reset) ADC output is connected to the JESD204A input
01
10
not used
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[11:0] = “100110111010”
11
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE” (Ser_PRBS_ctrl register)
3 to 1
-
R
000
not used
ADC1213D_SER_5
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ADC1213D series
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Table 52. ADCB_0_ctrl (address 0891h) …continued
Bit
Symbol
Access Value
Description
0
ADC_PD
R/W
ADC power-down control:
ADC is operational
0
1
ADC is in Power-down mode
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15. Package outline
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;
56 terminals; body 8 x 8 x 0.85 mm
SOT684-7
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
C
e
v
w
C A
B
C
1/2 e
b
L
y
C
1
y
15
28
14
29
e
E
h
e
2
1/2 e
1
42
terminal 1
index area
56
43
X
D
h
0
2.5
5 mm
scale
Dimensions
Unit
(1)
(1)
(1)
E
A
A
1
b
c
D
D
h
E
h
e
e
1
e
2
L
v
w
y
y
1
max 1.00 0.05 0.30
mm nom 0.85 0.02 0.21 0.2 8.0 5.80 8.0 6.40 0.5 6.5 6.5 0.4 0.1 0.05 0.05 0.1
min 0.80 0.00 0.18 7.9 5.65 7.9 6.25 0.3
8.1 5.95 8.1 6.55
0.5
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot684-7_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
08-11-19
09-03-04
SOT684-7
MO-220
Fig 24. Package outline SOT684-7 (HVQFN56)
ADC1213D_SER_5
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 05 — 23 April 2010
37 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
16. Revision history
Table 53. Revision history
Document ID
Release date
Data sheet status
Change Supersedes
notice
ADC1213D_SER_5
Modifications:
20100423
Preliminary data sheet
-
ADC1213D_SER_4
• Product status changed from Objective to Preliminary
ADC1213D_SER_4
20100412
Objective data sheet
Objective data sheet
Objective data sheet
Objective data sheet
-
-
-
-
ADC1213D065_080_105_125_3
ADC1213D065_080_105_125_2
ADC1213D065_080_105_125_1
-
ADC1213D065_080_105_125_3 20090617
ADC1213D065_080_105_125_2 20090604
ADC1213D065_080_105_125_1 20090528
ADC1213D_SER_5
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 05 — 23 April 2010
38 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
17.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
ADC1213D_SER_5
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 05 — 23 April 2010
39 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
ADC1213D_SER_5
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 05 — 23 April 2010
40 of 41
ADC1213D series
NXP Semiconductors
ADC1213D series
19. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
17.2
17.3
17.4
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
18
19
Contact information . . . . . . . . . . . . . . . . . . . . 40
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Clock and digital output timing . . . . . . . . . . . 11
Serial output timings . . . . . . . . . . . . . . . . . . . 12
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8
9
10
11
12
13
14
14.1
Application information. . . . . . . . . . . . . . . . . . 13
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input stage description . . . . . . . . . . . . . . . . . . 13
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 14
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 15
System reference and power management . . 16
Internal/external reference . . . . . . . . . . . . . . . 16
Reference gain control . . . . . . . . . . . . . . . . . . 17
Common-mode output voltage (VI(cm)) . . . . . . 17
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Equivalent input circuit . . . . . . . . . . . . . . . . . . 19
Clock input divider . . . . . . . . . . . . . . . . . . . . . 20
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 20
Digital outputs. . . . . . . . . . . . . . . . . . . . . . . . . 20
Serial output equivalent circuit . . . . . . . . . . . . 20
JESD204A serializer. . . . . . . . . . . . . . . . . . . . 21
Digital JESD204A formatter . . . . . . . . . . . . . . 21
ADC core output codes versus input voltage . 22
Serial Peripheral Interface (SPI). . . . . . . . . . . 23
Register description . . . . . . . . . . . . . . . . . . . . 23
Channel control . . . . . . . . . . . . . . . . . . . . . . . 24
Register description . . . . . . . . . . . . . . . . . . . . 27
14.1.1
14.1.2
14.1.3
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.3
14.3.1
14.3.2
14.3.3
14.3.4
14.4
14.4.1
14.5
14.5.1
14.5.2
14.6
14.6.1
14.6.2
14.6.3
14.6.3.1 ADC control register . . . . . . . . . . . . . . . . . . . . 27
14.6.4
JESD204A digital control registers . . . . . . . . . 29
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 38
Legal information. . . . . . . . . . . . . . . . . . . . . . . 39
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 39
15
16
17
17.1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 April 2010
Document identifier: ADC1213D_SER_5
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