ADC1415S105 [NXP]
Single 14-bit ADC 65, 80, 105 or 125 Msps with Input Buffer CMOS or LVDS DDR digital outputs; 单14位ADC 65 ， 80 ， 105或125 MSPS ，具有输入缓冲器CMOS或DDR LVDS数字输出
| 型号： | ADC1415S105 |
| 厂家： | 
NXP |
| 描述： | Single 14-bit ADC 65, 80, 105 or 125 Msps with Input Buffer CMOS or LVDS DDR digital outputs |
| 文件： | 总33页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC1415S065/080/105/125
Single 14-bit ADC 65, 80, 105 or 125 Msps with Input Buffer
CMOS or LVDS DDR digital outputs
Rev. 02 — 4 June 2009
Objective data sheet
1. General description
The ADC1415S is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1415S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,
thanks to a separate digital output supply.
The ADC1415S supports the LVDS (Low Voltage Differential Signalling) DDR (Double
Data Rate) output standard. An integrated SPI (Serial Peripheral Interface) allows the user
to easily configure the ADC.
The device also includes a programmable gain amplifier with a flexible input voltage
range. With excellent dynamic performance from the baseband to input frequencies of
170 MHz or more, the ADC1415S is ideal for use in communications, imaging and
medical applications - especially in high Intermediate Frequency (IF) applications thanks
to the integrated input buffer. The input buffer ensures that the input impedance remains
constant and low and the performance consistent over a wide frequency range.
2. Features
I SNR, 73 dB / SFDR, 90 dBc
I Pin compatible with the
ADC1410S065/080/105/125
I Sample rate up to 125 Msps
I 14-bit pipelined ADC core
I Integrated input buffer
I Input bandwidth, 600 MHz
I Power dissipation, 587 mW at 80 Msps,
including analog input buffer
I SPI Interface
I Duty cycle stabilizer
I Fast OTR detection
I Flexible input voltage range: 1 V (p-p) to I Offset binary, 2’s complement, gray
2 V (p-p) with 6 dB programmable
fine gain
code
I CMOS or LVDS DDR digital outputs
I INL ±1 LSB, DNL ±0.5 LSB (typical)
I Power-down and Sleep modes
I HVQFN40 package
3. Applications
I Wireless and wired broadband communications
I Spectral analysis
I Ultrasound equipment
I Portable instrumentation
I Imaging systems
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
4. Ordering information
Table 1.
Ordering information
Type number
fs (Msps) Package
Name
Description
Version
ADC1415S125HN/C1 125
ADC1415S105HN/C1 105
ADC1415S080HN/C1 80
ADC1415S065HN/C1 65
HVQFN40 plastic thermal enhanced very thin quad flat package; no
SOT618-1
leads; 40 terminals; body 6 × 6 × 0.85 mm
HVQFN40 plastic thermal enhanced very thin quad flat package; no
SOT618-1
SOT618-1
SOT618-1
leads; 40 terminals; body 6 × 6 × 0.85 mm
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6 × 6 × 0.85 mm
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6 × 6 × 0.85 mm
5. Block diagram
ADC1415S
ERROR
CORRECTION AND
DIGITAL
SPI INTERFACE
OTR
PROCESSING
PGA
CMOS:
DAV
or
LVDS/DDR:
DAVP
DAVM
CMOS:
D13 to D0
or
LVDS/DDR:
D13P, D13M
to D0P, D0M
INP
INM
S/H
INPUT
STAGE
ADC CORE
14-BIT
PIPELINED
INPUT
BUFFER
OUTPUT
DRIVERS
SYSTEM
REFERENCE AND
POWER
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
PWD
OE
MANAGEMENT
005aaa101
Fig 1. Block diagram
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
2 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
6. Pinning information
6.1 Pinning
terminal 1
index area
terminal 1
index area
1
2
30
29
28
27
26
25
24
23
22
21
REFB
REFT
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
1
2
30
29
28
27
26
25
24
23
22
21
REFB
REFT
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
3
AGND
VCM
4
3
AGND
VCM
5
VDDA5V
AGND
INM
ADC1415S
HVQFN40
4
6
5
VDDA5V
AGND
INM
7
ADC1415S
HVQFN40
6
8
INP
7
9
AGND
VDDA3V
8
INP
10
9
AGND
VDDA3V
10
005aaa103
Transparent top view
Transparent top view
005aaa102
Fig 2. Pin configuration with CMOS digital outputs
selected
Fig 3. Pin configuration with LVDS/DDR digital
outputs selected
6.2 Pin description
Table 2.
Symbol
REFB
REFT
AGND
VCM
Pin description (CMOS digital outputs)
Pin
1
Type[2]
Description
O
O
G
O
P
G
I
bottom reference
2
top reference
3
analog ground
4
common-mode output voltage
5 V analog power supply
analog ground
VDDA5V
AGND
INM
5
6
7
complementary analog input
analog input
INP
8
I
AGND
VDDA3V
VDDA3V
CLKP
CLKM
DEC
9
G
P
P
I
analog ground
10
11
12
13
14
15
16
3 V analog power supply
3 V analog power supply
clock input
I
complementary clock input
regulator decoupling node
output enable, active LOW
power down, active HIGH
O
I
OE
PWD
I
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
3 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
Table 2.
Pin description (CMOS digital outputs)
Symbol
D13
Pin
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Type[2]
Description
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
data output bit 13 (MSB)
data output bit 12
data output bit 11
data output bit10
D12
D11
D10
D9
data output bit 9
D8
data output bit 8
D7
data output bit 7
D6
data output bit 6
D5
data output bit 5
D4
data output bit 4
D3
data output bit 3
D2
data output bit 2
D1
data output bit 1
D0
data output bit 0 (LSB)
data valid output clock
not connected
DAV
n.c.
VDDO
OGND
OTR
SCLK/DFS
SDIO/ODS
CS
P
output power supply
output ground
G
O
I
out of range
SPI clock / data format select
SPI data IO / output data standard
SPI chip select
I/O
I
SENSE
VREF
I
reference programming pin
voltage reference input/output
I/O
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
Table 3.
Symbol
Pin description (LVDS/DDR) digital outputs)
Pin[1] Type[2] Description
D12_D13_M 17
D12_D13_P 18
D10_D11_M 19
D10_D11_P 20
O
O
O
O
O
O
O
O
O
O
O
O
O
differential output data D12 and D13 multiplexed, complement
differential output data D12 and D13 multiplexed, true
differential output data D10 and D11 multiplexed, complement
differential output data D10 and D11 multiplexed, true
differential output data D8 and D9 multiplexed, complement
differential output data D8 and D9 multiplexed, true
differential output data D6 and D7 multiplexed, complement
differential output data D6 and D7 multiplexed, true
differential output data D4 and D5 multiplexed, complement
differential output data D4 and D5 multiplexed, true
differential output data D2 and D3 multiplexed, complement
differential output data D2 and D3 multiplexed, true
differential output data D0 and D1 multiplexed, complement
D8_D9_M
D8_D9_P
D6_D7_M
D6_D7_P
D4_D5_M
D4_D5_P
D2_D3_M
D2_D3_P
D0_D1_M
21
22
23
24
25
26
27
28
29
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
4 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
Table 3.
Pin description …continued (LVDS/DDR) digital outputs)
Symbol
D0_D1_P
DAVM
Pin[1]
30
Type[2] Description
O
O
O
differential output data D0 and D1 multiplexed, true
31
data valid output clock, complement
data valid output clock, true
DAVP
32
[1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2)
[2] P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDDA(3V)
VDDA(5V)
VDDO
∆VCC
Tstg
Parameter
Conditions
Min
Max
Unit
V
3 V analog supply voltage
5 V analog supply voltage
output supply voltage
supply voltage difference
storage temperature
ambient temperature
junction temperature
on pin VDDA3V
on pin VDDA5V
<tbd> <tbd>
<tbd> <tbd>
<tbd> <tbd>
<tbd> <tbd>
V
V
VDDA(3V) − VDDO
V
−55
−40
-
+125
+85
°C
°C
°C
Tamb
Tj
<tbd>
8. Thermal characteristics
Table 5.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ
Unit
[1]
[1]
thermal resistance from junction to ambient
thermal resistance from junction to case
<tbd>
<tbd>
K/W
K/W
Rth(j-c)
[1] In compliance with JEDEC test board, in free air.
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
5 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
9. Static characteristics
Table 6.
Static characteristics
Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; min and max values
are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V,
VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDDA(5V)
VDDA(3V)
VDDO
5 V analog supply voltage
3 V analog supply voltage
output supply voltage
4.75
2.85
1.65
2.85
-
5.0
3.0
1.8
3.0
39
5.25
3.4
3.6
3.6
-
V
V
CMOS mode
V
LVDS DDR mode
V
IDDA(5V)
IDDA(3V)
IDDO
5 V analog supply current
3 V analog supply current
output supply current
fclk = 125 Msps;
fi =70 MHz
mA
fclk = 125 Msps;
fi =70 MHz
-
-
185
20
-
-
mA
mA
CMOS mode;
fclk = 125 Msps;
fi =70 MHz
LVDS DDR mode:
fclk = 125 Msps;
fi =70 MHz
-
35
-
mA
P
power dissipation
ADC1415S125
ADC1415S105
ADC1415S080
ADC1415S065
Power-down mode
Standby mode
-
-
-
-
-
-
758
688
587
536
2
-
-
-
-
-
-
mW
mW
mW
mW
mW
mW
40
Clock inputs: pins CLKP and CLKM
AC coupled; LVPECL, LVDS and sine wave
Vi(clk)dif
LVCMOS
VI
differential clock input voltage
peak-to-peak
0.2
0.8
-
<tbd>
V
V
input voltage
0.3VDDA(3V)
0.7VDDA(3V)
Logic Inputs: pins PWD and OE
VIL
VIH
IIL
LOW-level input voltage
0
-
-
-
-
0.8
V
HIGH-level input voltage
LOW-level input current
HIGH-level input current
2
VDDA(3V)
<tbd>
+10
V
<tbd>
−10
µA
µA
IIH
Serial Peripheral Interface: pins CS, SDIO/ODS, SCLK/DFS
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input capacitance
0
-
0.3VDDA(3V)
V
0.7VDDA(3V)
-
VDDA(3V)
+10
+50
-
V
−10
−50
-
-
µA
µA
pF
IIH
CI
-
4
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
6 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
Table 6.
Static characteristics …continued
Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; min and max values
are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V,
VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Digital Outputs: CMOS mode - pins D13 to D0, OTR, DAV
Output levels, VDDO = 3 V
VOL
VOH
IOL
LOW-level output voltage
HIGH-level output voltage
LOW-level output current
IOL = <tbd>
IOH = <tbd>
OGND
0.8VDDO
-
-
0.2VDDO
V
-
VDDO
-
V
3-state;
<tbd>
µA
output level = 0 V
IOH
CO
HIGH-level output current
output capacitance
3-state;
output level = VDDA(3V)
-
-
<tbd>
3
-
-
µA
high impedance;
OE = HIGH
pF
Output levels, VDDO = 1.8 V
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
IOL = <tbd>
IOH = <tbd>
OGND
-
-
0.2VDDO
VDDO
V
V
0.8VDDO
Digital Outputs, LVDS mode - pins D13P, D13M to D0P, D0M, DAVP and DAVM
Output levels, VDDO = 3 V only, Rload = 100 Ω
VO(offset)
VO(dif)
CO
output offset voltage
differential output voltage
output capacitance
output buffer current
set to 3.5 mA
-
-
-
1.2
-
-
-
V
output buffer current
set to 3.5 mA
350
mV
pF
<tbd>
Analog inputs: pins INP and INM
II
input current
−5
-
-
+5
-
µA
Ω
RI
input resistance
550
1.3
1.5
600
CI
input capacitance
common-mode input voltage
input bandwidth
-
-
pF
V
VI(cm)
Bi
VINP = VINM
0.9
-
2
-
MHz
V
VI(dif)
differential input voltage
peak-to-peak
1
2
Common mode output voltage: pin VCM
VO(cm)
IO(cm)
common-mode output voltage
common-mode output current
-
-
0.5VDDA(3V)
<tbd>
-
-
V
µA
I/O reference voltage: pin VREF
VVREF
voltage on pin VREF
output
input
-
0.5 to 1
-
-
V
V
0.5
1
Accuracy
INL
integral non-linearity
−5
±1
+5
LSB
LSB
DNL
differential non-linearity
guaranteed no
missing codes
−0.95
±0.5
+0.95
Eoffset
offset error
-
±2
-
mV
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
7 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
Table 6.
Static characteristics …continued
Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; min and max values
are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V,
VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
EG
gain error
±0.5
%FS
Supply
PSRR
power supply rejection ratio
100 mV (p-p) on
VDDA(3V)
35
dBc
10. Dynamic characteristics
10.1 Dynamic Characteristics
Table 7.
Dynamic characteristics
Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, Tamb = 25 °C and CL = 5 pF; min and max values are
across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V; VDDA(5V) = 5 V, VINP − VINM = −1
dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
Symbol Parameter Conditions
ADC1415S065
ADC1415S080
ADC1415S105
ADC1415S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Analog signal processing
α2H
second
harmonic
level
fi = 3 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
94
93
90
88
92
91
90
88
88
87
86
83
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
94
93
91
88
93
92
90
87
88
87
86
83
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
96
92
91
85
91
91
90
88
87
87
85
82
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
96
93
91
85
90
89
87
87
87
86
84
82
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
α3H
third
harmonic
level
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
THD
ENOB
SNR
SFDR
total
harmonic
distortion
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
effective
number of
bits
11.9 -
11.7 -
11.6 -
11.6 -
73.2 -
72.4 -
71.8 -
71.3 -
11.9 -
11.7 -
11.6 -
11.5 -
73.1 -
72.3 -
71.8 -
71.2 -
11.8 -
11.7 -
11.6 -
11.5 -
72.9 -
72.3 -
71.7 -
71.1 -
11.8 -
11.7 -
11.6 -
11.5 -
72.5 -
72.2 -
71.6 -
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
bits
bits
bits
signal-to-
noise ratio
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
71
90
89
87
85
-
-
-
-
-
spurious-
free
dynamic
range
91
90
89
86
-
-
-
-
91
90
89
86
-
-
-
-
90
90
88
85
-
-
-
-
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
8 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
Table 7.
Dynamic characteristics …continued
Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, Tamb = 25 °C and CL = 5 pF; min and max values are
across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V; VDDA(5V) = 5 V, VINP − VINM = −1
dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
Symbol Parameter Conditions
ADC1415S065
ADC1415S080
ADC1415S105
ADC1415S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
IMD
Intermodul- fi = 3 MHz
-
-
-
-
94
93
92
89
-
-
-
-
-
-
-
-
94
93
92
89
-
-
-
-
-
-
-
-
93
93
91
88
-
-
-
-
-
-
-
-
93
92
90
88
-
-
-
-
dBc
dBc
dBc
dBc
ation
distortion
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
10.2 Clock and Digital Output Timing
Table 8.
Clock and digital output timing characteristics
Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, Tamb = 25 °C and CL = 5 pF; min and max values are
across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V; VDDA(5V) = 5 V, VINP − VINM = −1
dBFS; unless otherwise specified.
Symbol Parameter Conditions
ADC1415S065
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Clock timing input: pins CLKP and CLKM
ADC1415S080
ADC1415S105
ADC1415S125 Unit
fclk
clock
20
-
65
60
-
80
60
-
105 60
-
125 MHz
frequency
tlat(data)
δclk
datalatency
time
-
14
50
50
0.8
tbd
-
-
14
50
50
0.8
tbd
-
-
14
50
50
0.8
tbd
-
-
14
50
50
0.8
tbd
-
clk/cy
%
clock duty
cycle
DCS_EN = 30
1
70
55
-
30
45
-
70
55
-
30
45
-
70
55
-
30
45
-
70
55
-
DCS_EN = 45
0
%
td(s)
sampling
delay time
-
ns
twake
wake-up
time
-
-
-
-
-
-
-
-
ns
CMOS Mode Timing output: pins D13 to D0 and DAV
tPD
propagation DATA
-
3.9
4.2
7.7
6.7
-
-
-
-
-
-
-
-
-
3.9
4.2
6.5
5.5
-
-
-
-
-
-
-
-
-
3.9
4.2
4.7
3.8
-
-
-
-
-
-
-
-
-
3.9
4.2
4.3
3.5
-
-
-
-
-
ns
ns
ns
ns
delay
DAV
-
tsu
th
tr
set-up time
hold time
rise time[1] DATA
-
-
0.5
0.5
0.5
2.4 0.5
2.4 0.5
2.4 0.5
2.4 0.5
2.4 0.5
2.4 0.5
2.4 0.5
2.4 0.5
2.4 0.5
2.4 ns
2.4 ns
2.4 ns
DAV
-
-
-
-
tf
fall time[1]
DATA
-
-
-
-
LVDS DDR mode timing output: pins D13P, D13M to D0P, D0M, DAVP and DAVM
tPD
propagation DATA
3.9
4.2
3.9
4.2
3.9
4.2
3.9
4.2
ns
ns
delay
DAV
[1] Measured between 20 % to 80 % of VDDO; rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV.
ADC1415S065_080_105_125_2
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NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
10.3 SPI Timings
Table 9.
Characteristics
Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, Tamb = 25 °C and CL = 5 pF; min and max values are
across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V; VDDA(5V) = 5 V,
Symbol
SPI timings
tw(SCLK)
tw(SCLKH)
tw(SCLKL)
tsu
Parameter
Conditions
Min
Typ
Max
Unit
SCLK pulse width
SCLK pulse width HIGH
SCLK pulse width LOW
set-up time
40
16
16
5
-
-
-
-
-
-
-
-
-
ns
-
ns
-
ns
data to SCLKH
CS to SCLKH
data to SCLKH
CS to SCLKH
-
ns
5
-
ns
th
hold time
2
-
ns
2
-
ns
fclk(max)
maximum clock frequency
-
25
MHz
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Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
11. Application information
11.1 Device control
The ADC1415S can be controlled via the Serial Peripheral Interface (SPI control mode) or
directly via the I/O pins (PIN control mode).
11.1.1 SPI and PIN control modes
The device enters PIN control mode at power-up, and remains in this mode as long as pin
CS is held HIGH. In PIN control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins. SPI settings are ignored.
SPI control mode is enabled by forcing pin CS LOW. It is not possible to toggle between
PIN control and SPI control modes. Once SPI control mode has been enabled, the device
will remain in this mode until it is powered down. The transition from PIN control mode to
SPI control mode is illustrated in Figure 4.
CS
PIN control mode
SPI control mode
SCLK/DFS
SDIO/ODS
Data Format
offset binary
Data Format
2's complement
LVDS DDR
R/W
W1
W0
A12
CMOS
005aaa039
Fig 4. Control mode selection.
When the device enters SPI control mode, the output data standard (CMOS or LVD DDR)
is not determined by the state of the relevant SPI control bit (LVDS/CMOS; see Table 21),
but by the level on pin SDIO at the instant a transition is triggered by a falling edge on CS
(SDIO = LOW = CMOS).
11.1.2 Operating mode selection
The active ADC1415S operating mode (Power-up, Power-down or Sleep) can be selected
via the SPI interface (see Table 17) or using pins PWD and OE in PIN control mode, as
described in Table 10.
Table 10. Operating mode selection via pin PWD and OE
Pin PWD
Pin OE
Operating mode
Power-up
Output high-Z
0
0
1
1
0
1
0
1
no
Power-up
yes
yes
yes
Sleep
Power-down
11.1.3 Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see Table 21) or using pin ODS in PIN control mode. LVDS DDR is selected when ODS is
HIGH, otherwise CMOS is selected.
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Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
11.1.4 Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, 2’s
complement or gray code; see Table 21) or using pin DFS in PIN control mode (offset
binary or 2’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, 2’s complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1415S supports differential or single-ended input drive.
Optimal performance is achieved using differential inputs. The ADC inputs are internally
biased and need to be decoupled.
The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.3 and Table 19 further details).
The equivalent circuit of the input buffer followed by the Sample and Hold (S/H) input
stage, including ESD protection and circuit and package parasitics, is shown in Figure 5.
Package
ESD
Parasitics
Switch
Ron = 14 Ω
4 pF
8
7
INP
Sampling
Capacitor
internal
clock
INPUT
BUFFER
Switch
Ron = 14 Ω
4 pF
INM
Sampling
Capacitor
internal
clock
005aaa107
Fig 5. Input sampling circuit and input buffer
The integrated input buffer offers the following advantages:
• The kickback effect is avoided - the charge injection and glitches generated by the
S/H input stage are isolated from the input circuitry. So there’s no need for additional
filtering.
• The input capacitance is very low and constant over a wide frequency range, which
makes the ADC1415S easy to drive.
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Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.2.2 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 6 would be suitable for a baseband application.
ADT1-1WT
100 nF
INP
100 nF
Analog
lnput
50 Ω
100 nF
100 nF
INM
VCM
100 nF
100 nF
005aaa108
Fig 6. Single transformer configuration suitable for baseband applications
The configuration shown in Figure 7 is recommended for high frequency applications. In
both cases, the choice of transformer will be a compromise between cost and
performance.
ADT1-1WT
ADT1-1WT
100 nF
INP
100 nF
50 Ω
50 Ω
Analog
lnput
100 Ω
100 nF
INM
100 nF
VCM
100 nF
100 nF
005aaa109
Fig 7. Dual transformer configuration suitable for high frequency application
11.3 System reference and power management
11.3.1 Internal/external references
The ADC1415S has a stable and accurate built-in internal reference voltage. This
reference voltage can be set internally, externally or via the SPI (programmable in 1 dB
steps between 0 dB and −6 dB via control bits INTREF when bit INTREF_EN = 1; see
Table 19). The equivalent reference circuit is shown in Figure 8.
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Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
REFT
REFERENCE
REFB
AMP
BANDGAP
REFERENCE
VREF
BUFFER
ADC CORE
SENSE
SELECTION
LOGIC
005aaa046
Fig 8. Single transformer configuration suitable for baseband applications
If bit INTREF_EN is set to 0, the reference voltage will be determined either internally or
externally as detailed in Table 11.
Table 11. Reference selection
Selection
SPI bit
SENSE pin VREF pin
full scale (p-p)
INTREF_EN
internal
internal
0
0
AGND
330 pF capacitor to AGND 2 V
pin VREF connected to pin SENSE and
via a 330 pF capacitor to AGND
1 V
external
0
1
VDDA(3V)
external voltage between
0.5 V and 1 V[1]
1 V to 2 V
1 V to 2 V
internal via SPI
pin VREF connected to pin SENSE and
via 330 pF capacitor to AGND
[1] The voltage on pin VREF is doubled internally to generate the internal reference voltage.
Figure 9 to Figure 12 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
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Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
VREF
REFT
REFB
VREF
330 pF
REFT
REFB
330 pF
SENSE
SENSE
005aaa047
005aaa048
Fig 9. Internal reference, 2 V (p-p) full scale
Fig 10. Internal reference, 1 V (p-p) full scale
VREF
REFT
VREF
REFT
330 pF
0.1 µF
V
SPI SETTINGS
INTREF_EN = 1, active
INTREF = XXX
SENSE
REFB
SENSE
REFB
V
DDA(5V)
005aaa049
005aaa115
Fig 11. Internal reference via SPI, 1 V (p-p) to
2 V (p-p) full scale
Fig 12. External reference, 1 V (p-p) to 2 V (p-p)
full scale
11.3.2 Gain control
The gain is programmable between 0 dB to −6 dB in 1 dB steps via the SPI (see
Table 19). This makes it possible to improve the Spurious-Free Dynamic Range (SFDR) of
the ADC1415S. The corresponding full scale input voltage range varies between 2 V (p-p)
and 1 V (p-p), as shown in Table 12:
Table 12. Reference SPI Gain Control
INTREF
000
Gain
full scale (p-p)
2 V
0 dB
001
−1 dB
−2 dB
−3 dB
−4 dB
−5 dB
−6 dB
reserved
1.78 V
1.59 V
1.42 V
1.26 V
1.12 V
1 V
010
011
100
101
110
111
x
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Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
11.3.3 Common-mode output voltage (VO(cm)
)
A 0.1 µF filter capacitor should be connected between pin VCM and ground.
11.3.4 Biasing
The common-mode input voltage (VI(cm)) on pins INP and INM is set internally. The input
buffer bias current can be set to one of three levels (high, medium or low) via the SPI (see
Table 20).
11.4 Clock input
11.4.1 Drive modes
The ADC1415S can be driven differentially (SINE, LVPECL or LVDS) without the
performance being affected by the choice of configuration. It can also be driven by a
single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to
ground via a capacitor) or CLKM (CLKP should be connected to ground via a capacitor).
CLKP
CLKM
CLKP
CLKM
LVCMOS
Clock lnput
LVCMOS
Clock lnput
005aaa053
Fig 13. LVCMOS Single-ended clock input
CLKP
CLKP
Sine
Clock lnput
Sine
Clock lnput
CLKM
CLKM
005aaa054
Fig 14. Sine differential clock input
CLKP
LVDS
Clock lnput
CLKM
005aaa055
Fig 15. LVDS differential clock input
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Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 16. The common-mode
voltage of the differential input stage is set via internal 5 kΩ resistors.
PACKAGE
ESD
PARASITICS
CLKP
Vcm(clk)
SE_SEL SE_SEL
5 k
5 k
CLKM
005aaa056
Fig 16. Equivalent Input circuit
Single-ended or differential clock inputs can be selected via the SPI interface (see
Table 18). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control
bit SE_SEL.
If single-ended is implemented without setting SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
11.4.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = 1; see Table 18), the circuit can handle signals with duty cycles of
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN =
0), the input clock signal should have a duty cycle of between 45% and 55%.
11.4.4 Clock input divider
The ADC1415S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = 1; see Table 18). This feature allows the user to deliver a higher
clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
11.5 Digital outputs
11.5.1 Digital output buffers: CMOS mode
The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0 (see
Table 21).
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Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in Figure 17. The buffer is powered by a separate
OGND/VDDO to ensure 1.8 V to 3.4 V compatibility and is isolated from the ADC core.
Each buffer can be loaded by a maximum of 10 pF.
VDDO
PARASITICS
ESD
PACKAGE
50 Ω
Dx
LOGIC
DRIVER
OGND
005aaa057
Fig 17. CMOS digital output buffer
The output resistance is 50 Ω and is the combination of the an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both data and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see Table 28):
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1
(see Table 21).
VCCO
3.5 mA
typ
−
+
D P/D
P
n
n + 1
100 Ω RECEIVER
D M/D
n
M
n + 1
−
+
OGND
005aaa058
Fig 18. LVDS DDR digital output buffer - externally terminated
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side (Figure 18) or internally via SPI control bits LVDS_INTTER (see Figure 19 and
Table 30).
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Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
VCCO
3.5 mA
typ
−
+
D P/D
x x + 1
P
100 Ω
RECEIVER
D M/D
x
M
x + 1
−
+
OGND
005aaa059
Fig 19. LVDS DDR digital output buffer - internally terminated
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI and DATAI; see Table 29) in order to adjust the output logic voltage
levels.
11.5.3 Data valid (DAV) output clock
A data valid output clock signal (DAV) is provided that can be used to capture the data
delivered by the ADC1415S. Detailed timing diagrams for CMOS and LVDS DDR modes
are provided in Figure 20 and Figure 21 respectively.
11.5.4 Out-of-Range (OTR)
An out-of-range signal is provided on pin OTR. By default, pin OTR goes HIGH fourteen
clock cycles after an OTR event has occurred. The OTR response can be speeded up by
enabling Fast OTR (bit FASTOTR = 1; see Table 27). When Fast OTR is enabled, OTR
goes HIGH four clock cycles after the OTR event. The Fast OTR detection threshold
(below full scale) can be programmed via bits FASTOTR_DET.
11.5.5 Digital offset
By default, the ADC1415S delivers output code that corresponds to the analog input.
However it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET; see Table 23).
11.5.6 Test patterns
For test purposes, the ADC1415S can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL; see Table 24). A custom test pattern can
be defined by the user (TESTPAT_USER; see Table 25 and Table 26) and is selected
when TESTPAT_SEL = 101. The selected test pattern will be transmitted regardless of the
analog input.
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ADC1415S065/080/105/125
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Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
11.5.7 Output codes versus input voltage
Table 13. Output codes
V
INP − VINM
Offset binary
Two’s complement
10 0000 0000 0000
10 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0010
10 0000 0000 0011
10 0000 0000 0100
....
OTR pin
< −1
00 0000 0000 0000
00 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0010
00 0000 0000 0011
00 0000 0000 0100
....
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
−1
−0.9998779
−0.9997559
−0.9996338
−0.9995117
....
−0.0002441
−0.0001221
0
01 1111 1111 1110
01 1111 1111 1111
10 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0010
....
11 1111 1111 1110
11 1111 1111 1111
00 0000 0000 0000
00 0000 0000 0001
00 0000 0000 0010
....
+0.0001221
+0.0002441
....
+0.9995117
+0.9996338
+0.9997559
+0.9998779
+1
11 1111 1111 1011
11 1111 1111 1100
11 1111 1111 1101
11 1111 1111 1110
11 1111 1111 1111
11 1111 1111 1111
01 1111 1111 1011
01 1111 1111 1100
01 1111 1111 1101
01 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
> +1
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ADC1415S065/080/105/125
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Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
11.6 Timings summary
11.6.1 CMOS mode timings
N
N + 1
t
d(s)
N + 2
t
clk
CLKP
CLKM
t
PD
(N − 14)
(N − 13)
(N − 12)
(N − 11)
DATA
DAV
t
PD
t
t
h
su
t
clk
005aaa060
Fig 20. CMOS mode timing
11.6.2 LVDS DDR mode timing
N
N + 1
t
d(s)
N + 2
t
clk
CLKP
CLKM
t
PD
(N − 14)
(N − 13)
(N − 12)
(N − 11)
D _D
_P
x
x + 1
D
x
D
x + 1
D
x
D
x + 1
D
x
D
x + 1
D
x
D
x + 1
D
x
D
x + 1
D _D
_M
x
x + 1
t
t
t
t
su h
su
h
t
PD
DAVP
DAVM
t
clk
005aaa061
Fig 21. LDVS DDR mode timing
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Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
11.7 Serial Peripheral Interface (SPI)
11.7.1 Register Description
The ADC1415S serial interface is a synchronous serial communications port that allows
for easy interfacing with many commonly-used microprocessors. It provides access to the
registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin)
Pin SCLK is the serial clock input and CS is the chip select pin.
Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes will
be transmitted (two instruction bytes and at least one data byte). The number of data
bytes is determined by the value of bits W1 and W2 (see Table 15).
Table 14. Instruction bytes for the SPI
MSB
LSB
0
Bit
7
6
5
4
3
2
1
Description
R/W[1]
A7
W1[2]
W0[2]
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
A6
A5
[1] Bit R/W indicates whether it is a read (1) or a write (0) operation.
[2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 15).
Table 15. Number of data bytes to be transferred after the instruction bytes
W1
0
W0
0
Number of bytes transmitted
1 byte
0
1
2 bytes
1
0
3 bytes
1
1
4 bytes or more
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incriminated to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. A falling edge on CS in combination with a rising edge on SCLK determine the start of
communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but will always
be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on CS indicates the end on data transmission.
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ADC1415S065/080/105/125
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Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
CS
SCLK
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDIO
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa062
Fig 22. SPI mode timing
11.7.2 Default modes at start-up
During circuit initialization, it doesn’t matter which output data standard has been
selected. At power-up, the device defaults to PIN control mode.
A falling edge on CS will trigger a transition to SPI control mode. When the ADC1415S
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see Figure 23). Once in SPI control mode, the output data standard
can be changed via bit LVDS/CMOS in Table 21.
When the ADC1415S enters SPI control mode, the output data format (2’s complement or
offset binary) is determined by the level on pin SCLK (grey code can only be selected via
the SPI). Once in SPI control mode, the output data format can be changed via bit
DATA_FORMAT in Table 21.
CS
SCLK
(Data Fo
rmat)
SDIO
(CMOS LVDS DDR)
Offset binary, LVDS DDR
default mode at startup
005aaa063
Fig 23. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
CS
SCLK
(Data Fo
rmat)
SDIO
(CMOS LVDS DDR)
2's complement, CMOS
default mode at startup
005aaa064
Fig 24. Default mode at start-up: SCLK HIGH = 2’s complement; SDIO LOW = CMOS
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
23 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
11.7.3 Register allocation map
Table 16. Register allocation map
Addr Register name
Hex
R/W Bit definition
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bin
0005 Reset and
operating mode
R/W SW_
RST
-
-
-
-
-
OP_MODE
0000
0000
0006 Clock
R/W -
-
-
-
-
-
-
-
-
-
-
-
-
SE_SEL DIFF/SE
-
CLKDIV
DCS_EN 0000
0001
0008 Internal reference R/W
-
-
-
-
-
-
-
INTREF_ INTREF
EN
0000
0000
0010 Input buffer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
IB_IBIAS
0000
0011
0011 Output data
standard.
LVDS/
CMOS
OUTBUF
DAVINV
-
DATA_FORMAT
0000
0000
0012 Output clock
-
DAVPHASE
0000
1110
0013 Offset
DIG_OFFSET
0000
0000
0014 Test pattern 1
0015 Test pattern 2
0016 Test pattern 2
0017 Fast OTR
-
-
-
TESTPAT_SEL
0000
0000
TESTPAT_USER
0000
0000
TESTPAT_USER
-
-
0000
0000
-
-
-
-
-
-
-
-
-
-
-
-
FASTOTR FASTOTR_DET
0000
0000
0020 CMOS output
DAV_DRV
DATA_DRV
0000
1110
0021 LVDS DDR O/P 1 R/W
0022 LVDS DDR O/P 2 R/W
DAVI_
x2_EN
DAVI
-
DATAI_x DATAI
2_EN
0000
0000
-
BIT/BYTE_ LVDS_INTTER
WISE
0000
0000
Table 17. Reset and operating mode control register (address 0005h) bit description
Bit
Symbol
Access Value
Description
7
SW_RST
R/W
reset digital section
no reset
0
1
performs a reset of the digital section
6 to 2 reserved
1 to 0 OP_MODE
R/W
00
operating mode
normal (Power-up)
Power-down
01
10
Sleep
11
normal (Power-up)
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
24 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
Table 18. Clock control register (address 0006h)bit description
Bit
Symbol
Access Value
Description
7 to 5 reserved
4
3
SE_SEL
DIFF/SE
R/W
0
single-ended clock input pin select
CLKM
1
CLKP
R/W
0
differential/single ended clock input select
fully differential
1
single-ended
2
1
reserved
CLKDIV
R/W
0
clock input divide by 2
disabled
1
enabled
0
DCS_EN
R/W
0
duty cycle stabilizer
disabled
1
enabled
Table 19. Internal reference control register (address 0008h) bit description
Bit
Symbol
Access Value
Description
7 to 4 reserved
3
INTREF_EN R/W
programmable internal reference enable
disable
0
1
active
2 to 0 INTREF
R/W
000
programmable internal reference
0 dB (FS = 2 V)
001
−1 dB (FS = 1.78 V)
−2 dB (FS = 1.59 V)
−3 dB (FS = 1.42 V)
−4 dB (FS = 1.26 V)
−5 dB (FS = 1.12 V)
−6 dB (FS = 1 V)
010
011
100
101
110
111
reserved
Table 20. Input buffer control register (address 0010h) bit description
Bit
Symbol
Access Value
Description
7 to 2 reserved
1 to 0 IB_IBIAS
R/W
00
input buffer bias current
not used
medium
low
01
10
11
high
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
25 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
Table 21. Output data standard control register (address 0011h) bit description
Bit
Symbol
Access Value
Description
7 to 5 reserved
4
3
2
LVDS/CMOS
R/W
output data standard: LVDS DDR or CMOS
CMOS
0
1
LVDS DDR
OUTBUF
R/W
output buffers enable
output enabled
0
1
output disabled (high Z)
reserved
1 to 0 DATA_FORMAT R/W
output data format
offset binary
00
01
10
11
2’s complement
gray code
offset binary
Table 22. Output clock register (address 0012h) bit description
Bit Symbol Access Value Description
7 to 4 reserved
DAVINV
3
R/W
output clock data valid (DAV) polarity
0
1
normal
inverted
2 to 0 DAVPHASE
R/W
DAV phase select
000
001
010
011
100
101
110
111
output clock shifted (ahead) by 3 ns
output clock shifted (ahead) by 2.5 ns
output clock shifted (ahead) by 2 ns
output clock shifted (ahead) by 1.5 ns
output clock shifted (ahead) by 1 ns
output clock shifted (ahead) by 0.5 ns
default value as defined in timing section
output clock shifted (delayed) by 0.5 ns
Table 23. Offset register (address 0013h) bit description
Bit
Symbol
Access Value
Description
7 to 6 reset
5 to 0 DIG_OFFSET
R/W
digital offset adjustment
011111
...
+31 LSB
...
000000
...
0
...
100000
−32 LSB
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
26 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
Table 24. Test pattern register 1 (address 0014h) bit description
Bit
Symbol
Access Value Description
7 to 3 reserved
2 to 0 TESTPAT_SEL
R/W
digital test pattern select
000
001
010
011
100
101
110
111
off
mid scale
−FS
+FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern
‘1010..1010.’
‘010..1010’
Table 25. Test pattern register 2 (address 0015h) bit description
Bit Symbol Access Value Description
7 to 0 TESTPAT_USER R/W custom digital test pattern (bits 13 to 6)
Table 26. Test pattern register 3 (address 0016h) bit description
Bit Symbol Access Value Description
R/W custom digital test pattern (bits 5 to 0)
7 to 2 TESTPAT_USER
1 to 0 reserved
Table 27. Fast OTR register (address 0017h) bit description
Bit
7 to 4 reset
FASTOTR
Symbol
Access Value
Description
3
R/W
fast Out-of-Range (OTR) detection
disabled
0
1
enabled
2 to 0 FASTOTR_DET R/W
set fast OTR detect level
−20.56 dB
000
001
010
011
100
101
110
111
−16.12 dB
−11.02 dB
−7.82 dB
−5.49 dB
−3.66 dB
−2.14 dB
−0.86 dB
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
27 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
Table 28. CMOS output register (address 0020h) bit description
Bit
Symbol
Access Value Description
7 to 4 reserved
3 to 2 DAV_DRV
R/W
drive strength for DAV CMOS output buffer
00
01
10
11
low
medium
high
very high
1 to 0 DATA_DRV
R/W
drive strength for DATA CMOS output buffer
00
01
10
11
low
medium
high
very high
Table 29. LVDS DDR output register 1 (address 0021h) bit description
Bit
7 to 6
5
Symbol
Access Value Description
DAVI_x2_EN R/W
double LVDS current for DAV LVDS buffer
0
1
disabled
enabled
4 to 3 DAVI
R/W
LVDS current for DAV LVDS buffer
00
01
10
11
3.5 mA
4.5 mA
1.25 mA
2.5 mA
2
DATAI_x2_EN R/W
double LVDS current for DATA LVDS buffer
0
1
disabled
enabled
1 to 0 DATAI
R/W
LVDS current for DATA LVDS buffer
00
01
10
11
3.5 mA
4.5 mA
1.25 mA
2.5 mA
Table 30. LVDS DDR output register 2 (address 0022h) bit description
Bit Symbol Access Value Description
7 to 4 reserved
BIT/BYTE_WISE R/W
3
DDR mode for LVDS output
0
bit wise (even data bits output on DAV rising edge /
odd data bits output on DAV falling edge)
1
byte wise (MSB data bits output on DAV rising
edge / LSB data bits output on DAV falling edge)
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
28 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
Table 30. LVDS DDR output register 2 (address 0022h) bit description …continued
Bit Symbol Access Value Description
2 to 0 LVDS_INTTER R/W internal termination for LVDS buffer (DAV and DATA)
000
001
010
011
100
101
110
111
no internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
11.7.4 Serial timing interface
SPI timing is shown in Figure 25.
t
t
w(SCLKL)
su
t
t
h
h
su
t
t
w(SCLKH)
t
w(SCLK)
CS
SCLK
SDIO
W1
W0
A12
A11
D2
D1
D0
R/W
005aaa065
Fig 25. SPI timing
SPI timing characteristics are detailed in Table 9.
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
29 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
12. Package outline
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm
SOT618-1
D
B
A
terminal 1
index area
A
A
E
1
c
detail X
C
e
1
y
y
1/2 e
e
v
M
M
C
b
C
C
A
B
1
11
20
w
L
21
10
e
e
E
h
2
1/2 e
1
30
terminal 1
index area
40
31
D
X
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
e
2
y
D
D
E
L
v
w
y
1
h
h
max.
0.05 0.30
0.00 0.18
6.1
5.9
4.25
3.95
6.1
5.9
4.25
3.95
0.5
0.3
mm
0.05 0.1
1
0.2
0.5
4.5
4.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-08-08
02-10-22
SOT618-1
- - -
MO-220
- - -
Fig 26. Package outline SOT618-1 (HVQFN40)
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
30 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
13. Revision history
Table 31. Revision history
Document ID
Release date
Data sheet status
Change Supersedes
notice
ADC1415S065_080_105_125_2 20090604
Modifications:
Objective data sheet
-
ADC1415S065_080_105_125_1
• Values in Table 7 have been updated.
ADC1415S065_080_105_125_1 20090528
Objective data sheet
-
-
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
31 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
14.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
ADC1415S065_080_105_125_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 4 June 2009
32 of 33
ADC1415S065/080/105/125
NXP Semiconductors
Single 14-bit ADC 65, 80, 105 or 125 Msps with input buffer
16. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
11.7.1
11.7.2
11.7.3
11.7.4
Register Description. . . . . . . . . . . . . . . . . . . . 22
Default modes at start-up. . . . . . . . . . . . . . . . 23
Register allocation map . . . . . . . . . . . . . . . . . 24
Serial timing interface. . . . . . . . . . . . . . . . . . . 29
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
12
13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . 31
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
14
Legal information . . . . . . . . . . . . . . . . . . . . . . 32
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 32
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 32
14.1
14.2
14.3
14.4
7
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal characteristics. . . . . . . . . . . . . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
15
16
Contact information . . . . . . . . . . . . . . . . . . . . 32
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Dynamic Characteristics. . . . . . . . . . . . . . . . . . 8
Clock and Digital Output Timing . . . . . . . . . . . . 9
SPI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . 10
10.1
10.2
10.3
11
11.1
Application information. . . . . . . . . . . . . . . . . . 11
Device control. . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI and PIN control modes . . . . . . . . . . . . . . 11
Operating mode selection. . . . . . . . . . . . . . . . 11
Selecting the output data standard. . . . . . . . . 11
Selecting the output data format. . . . . . . . . . . 12
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transformer. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
System reference and power management . . 13
Internal/external references . . . . . . . . . . . . . . 13
Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Common-mode output voltage (VO(cm)) . . . . . 16
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Equivalent input circuit . . . . . . . . . . . . . . . . . . 17
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 17
Clock input divider . . . . . . . . . . . . . . . . . . . . . 17
Digital outputs. . . . . . . . . . . . . . . . . . . . . . . . . 17
Digital output buffers: CMOS mode . . . . . . . . 17
Digital output buffers: LVDS DDR mode . . . . . 18
Data valid (DAV) output clock . . . . . . . . . . . . . 19
Out-of-Range (OTR). . . . . . . . . . . . . . . . . . . . 19
Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Test patterns. . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output codes versus input voltage . . . . . . . . . 20
Timings summary . . . . . . . . . . . . . . . . . . . . . . 21
CMOS mode timings. . . . . . . . . . . . . . . . . . . . 21
LVDS DDR mode timing . . . . . . . . . . . . . . . . . 21
Serial Peripheral Interface (SPI) . . . . . . . . . . . 22
11.1.1
11.1.2
11.1.3
11.1.4
11.2
11.2.1
11.2.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.6
11.6.1
11.6.2
11.7
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 June 2009
Document identifier: ADC1415S065_080_105_125_2
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IDT
ADC1415S125HN/C1
Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
NXP
ADC1415S_10
Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Mspswith input buffer; CMOS or LVDS DDR digital outputs
NXP
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