ADC1613S080C1 [NXP]
Single 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps serial JESD204A interface; 一个16位ADC ; 65 MSPS, 80 MSPS, 105 Msps的或125 MSPS JESD204A串行接口型号: | ADC1613S080C1 |
厂家: | NXP |
描述: | Single 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps serial JESD204A interface |
文件: | 总39页 (文件大小:699K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADC1613S series
Single 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
serial JESD204A interface
Rev. 2 — 9 June 2011
Product data sheet
1. General description
The ADC1613S is a single channel 16-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performance and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1613S is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V source
for analog and a 1.8 V source for the output driver, it outputs data in serial mode via a
single differential lane, which complies with the JESD204A standard. The integration of
Serial Peripheral Interface allows the user to easily configure the ADCs and the serial
output modes. The device also includes a programmable full-scale SPI to allow a flexible
input voltage range from 1 V (p-p) to 2 V (p-p).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1613S ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
SNR, 72.3 dBFS; SFDR, 88 dBc
Input bandwidth, 600 MHz
Sample rates up to 125 Msps
Single channel, 16-bit pipelined ADC
core
Power dissipation, 550 mW at 80 Msps
SPI register programming
3 V, 1.8 V power supplies
Flexible input voltage range:
1 V (p-p) to 2 V (p-p)
Duty cycle stabilizer
High Intermediate Frequency (IF)
capability
Serial output
Offset binary, two’s complement, gray
code
Power-down mode and Sleep mode
Compliant with JESD204A serial
transmission standard
Pin compatible with ADC1413S series, HVQFN32 package
ADC1213S series, and ADC1113S125
3. Applications
Wireless and wired broadband
Portable instrumentation
Imaging systems
communications
Spectral analysis
Ultrasound equipment
ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
4. Ordering information
Table 1.
Ordering information
Type number
Sampling
frequency
(Msps)
Package
Name
Description
Version
ADC1613S125HN/C1 125
ADC1613S105HN/C1 105
ADC1613S080HN/C1 80
ADC1613S065HN/C1 65
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; body 7 7 0.8 mm
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; body 7 7 0.8 mm
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; body 7 7 0.8 mm
HVQFN32R plastic thermal enhanced very thin quad flat package; SOT1152-1
no leads; 32 terminals; body 7 7 0.8 mm
ADC1613S_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
2 of 39
ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
5. Block diagram
SDIO
CS
SCLK
SPI
SYNCP
SYNCN
CLKP
DLL
PLL
CLKM
ERROR
CORRECTION AND
DIGITAL
PROCESSING
INP
OTR
SERIALIZER A
CMLP
CMLN
T/H
INPUT
STAGE
ADC CORE
16-BIT
PIPELINED
8-bit
8-bit
10-bit
D15 to D0
OUTPUT
BUFFER A
INM
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ADC1613S
OTR
SENSE
VDDD
AGND
DGND
VDDA
001aam779
Fig 1. Block diagram
ADC1613S_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
3 of 39
ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
6. Pinning information
6.1 Pinning
terminal 1
index area
CLKP
CLKM
AGND
REFB
REFT
VCM
1
2
3
4
5
6
7
8
24 n.c.
23 DGND
22 DGND
21 VDDD
ADC1613S
20 CMLN
19 CMLP
18 VDDD
17 DGND
INM
INP
001aam781
Transparent top view
Fig 2. Pinning diagram
6.2 Pin description
Table 2.
Symbol
CLKP
CLKM
AGND
REFB
REFT
VCM
Pin description
Pin
1
Type [1]
Description
I
clock input
2
I
complementary clock input
analog ground
3
G
O
O
O
I
4
ADC bottom reference
ADC top reference
ADC output common voltage
ADC complementary analog input
ADC analog input
5
6
INM
7
INP
8
I
VDDA
VDDA
SCLK
SDIO
9
P
P
I
analog power supply 3 V
analog power supply 3 V
SPI clock
10
11
12
I/O
SPI data input/output
ADC1613S_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
4 of 39
ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
Table 2.
Pin description …continued
Type [1]
Symbol
CS
Pin
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Description
I
chip select
OTR
O
P
G
G
P
O
O
P
G
G
-
out-of-range information
digital power supply 1.8 V
digital ground
VDDD
DGND
DGND
VDDD
CMLP
CMLN
VDDD
DGND
DGND
n.c.
digital ground
digital power supply 1.8 V
serial output
serial complementary output
digital power supply 1.8 V
digital ground
digital ground
not connected
SYNCP
SYNCN
VDDD
DGND
VDDA
AGND
SENSE
VREF
I
positive synchronization signal from the receiver
negative synchronization signal from the receiver
digital power supply 1.8 V
digital ground
I
P
G
P
G
I
analog power supply 3 V
analog ground
reference programming pin
voltage reference input/output
I/O
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDDA
VDDD(1V8)
Tstg
Parameter
Conditions
Min
0.4
0.4
55
40
-
Max
+4.6
+2.5
+125
+85
Unit
V
analog supply voltage
digital supply voltage (1.8 V)
storage temperature
ambient temperature
junction temperature
V
C
C
C
Tamb
Tj
125
8. Thermal characteristics
Table 4.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ
Unit
[1]
[1]
thermal resistance from junction to ambient
thermal resistance from junction to case
25.6
8.6
K/W
K/W
Rth(j-c)
[1] Value for six layers board in still air with a minimum of 25 thermal vias.
ADC1613S_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
5 of 39
ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
9. Static characteristics
Table 5.
Symbol
Supplies
VDDA
Static characteristics [1]
Parameter
Conditions
Min
Typ
Max
Unit
analog supply voltage
2.85
1.65
3.0
1.8
3.4
V
V
VDDD(1V8)
digital supply voltage
(1.8 V)
1.95
IDDA
analog supply current
fclk = 125 Msps;
fi = 70 MHz
-
-
185
75
-
-
mA
mA
IDDD(1V8)
Ptot
digital supply current
(1.8 V)
fclk = 125 Msps;
fi = 70 MHz
total power dissipation
fclk = 125 Msps
fclk = 105 Msps
fclk = 80 Msps
fclk = 65 Msps
-
-
-
-
-
-
690
625
550
495
30
-
-
-
-
-
-
mW
mW
mW
mW
mW
mW
P
power dissipation
Power-down mode
Standby mode
150
Digital inputs
Clock inputs: pins CLKP and CLKM (AC-coupled)
Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
Vi(clk)dif
differential clock input
voltage
peak-to-peak
-
1.6
-
-
V
V
Sine
Vi(clk)dif
differential clock input
voltage
peak
0.8
3.0
Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.3VDDA
-
V
V
0.7VDDA
SPI: pins CS, SDIO, and SCLK
VIL
VIH
IIL
LOW-level input voltage
0
-
0.3VDDA
VDDA
+10
V
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input capacitance
0.7VDDA
10
50
-
-
V
-
A
A
pF
IIH
CI
-
+50
4
-
Analog inputs: pins INP and INM
II
input current
track mode
track mode
track mode
track mode
5
-
-
+5
-
A
RI
input resistance
input capacitance
15
5
CI
-
-
pF
V
VI(cm)
common-mode input
voltage
1.1
1.5
2
Bi
input bandwidth
-
600
-
-
MHz
V
VI(dif)
differential input voltage peak-to-peak
1
2
ADC1613S_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
6 of 39
ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
[1]
Table 5.
Symbol
Static characteristics …continued
Parameter
Conditions
Min
Typ
Max
Unit
Voltage controlled regulator output: pin VCM
VO(cm)
common-mode output
voltage
-
-
0.5VDDA
4
-
-
V
IO(cm)
common-mode output
current
mA
Reference voltage input/output: pin VREF
VVREF
voltage on pin VREF
output
input
0.5
0.5
-
-
1
1
V
V
Data outputs: CMLP, CMLN
Output levels, VDDD(1V8) = 1.8 V; SWING_SEL[2:0] = 000
VOL
LOW-level output
voltage
DC-coupled; output
AC-coupled
-
-
-
-
1.5
-
-
-
-
V
V
V
V
1.35
1.8
VOH
HIGH-level output
voltage
DC-coupled; output
AC-coupled
1.65
Output levels, VDDD(1V8) = 1.8 V; SWING_SEL[2:0] = 001
VOL
LOW-level output
voltage
DC-coupled; output
AC-coupled
-
-
-
-
1.45
1.275
1.8
-
-
-
-
V
V
V
V
VOH
HIGH-level output
voltage
DC-coupled; output
AC-coupled
1.625
Output levels, VDDD(1V8) = 1.8 V; SWING_SEL[2:0] = 010
VOL
LOW-level output
voltage
DC-coupled; output
AC-coupled
-
-
-
-
1.4
1.2
1.8
1.6
-
-
-
-
V
V
V
V
VOH
HIGH-level output
voltage
DC-coupled; output
AC-coupled
Output levels, VDDD(1V8) = 1.8 V; SWING_SEL[2:0] = 011
VOL
LOW-level output
voltage
DC-coupled; output
AC-coupled
-
-
-
-
1.35
1.125
1.8
-
-
-
-
V
V
V
V
VOH
HIGH-level output
voltage
DC-coupled; output
AC-coupled
1.575
Output levels, VDDD(1V8) = 1.8 V; SWING_SEL[2:0] = 100
VOL
LOW-level output
voltage
DC-coupled; output
AC-coupled
-
-
-
-
1.3
-
-
-
-
V
V
V
V
1.05
1.8
VOH
HIGH-level output
voltage
DC-coupled; output
AC-coupled
1.55
Serial configuration: SYNCP, SYNCN
VIL
LOW-level input voltage differential; input
HIGH-level input voltage differential; input
-
-
0.95
1.47
-
-
V
V
VIH
Accuracy
INL
integral non-linearity
5
-
+5
LSB
LSB
DNL
differential non-linearity guaranteed no missing
codes
0.95
0.5
+0.95
Eoffset
offset error
-
2
-
mV
ADC1613S_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
7 of 39
ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
[1]
Table 5.
Symbol
EG
Static characteristics …continued
Parameter
Conditions
Min
Typ
Max
Unit
gain error
full-scale
-
0.5
-
%
Supply
PSRR
power supply rejection
ratio
200 mV (p-p) on
pin VDDA; fi = DC
-
54
-
dB
[1] Typical values measured at VDDA = 3 V, VDDD(1V8) = 1.8 V, Tamb = 25 C. Minimum and maximum values are across the full temperature
range Tamb = 40 C to +85 C at VDDA = 3 V, VDDD(1V8) = 1.8 V; Vi(INP) Vi(INM) = 1 dBFS; internal reference mode; 100 differential
applied to serial outputs; unless otherwise specified.
ADC1613S_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
8 of 39
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10. Dynamic characteristics
10.1 Dynamic characteristics
Table 6.
Symbol
Dynamic characteristics [1]
Parameter
Conditions
ADC1613S065
ADC1613S080
ADC1613S105
ADC1613S125
Unit
Min
Typ
89
Max
Min
Typ
89
Max
Min
Typ
88
Max Min Typ Max
2H
second harmonic
level
fi = 3 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
90
89
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
88
88
88
87
87
86
87
84
84
83
85
3H
third harmonic level
88
88
87
89
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
87
87
87
88
86
86
85
86
83
83
82
84
THD
ENOB
SNR
SFDR
total harmonic
distortion
85
85
84
86
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 3 MHz
84
84
84
85
83
83
82
83
80
80
79
81
effective number of
bits
11.7
11.6
11.5
11.4
72.3
71.5
70.9
70.4
88
11.7
11.6
11.5
11.4
72.2
71.4
70.9
70.3
88
11.7
11.6
11.5
11.4
72.0
71.4
70.8
70.2
87
11.6
11.6
11.5
11.4
71.6
71.3
70.7
70.1
89
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
bits
bits
bits
signal-to-noise ratio fi = 3 MHz
fi = 30 MHz
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
fi = 70 MHz
fi = 170 MHz
spurious-free
dynamic range
fi = 3 MHz
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
87
87
87
88
86
86
85
86
83
83
82
84
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[1]
Table 6.
Symbol
Dynamic characteristics …continued
Parameter
Conditions
ADC1613S065
ADC1613S080
ADC1613S105
ADC1613S125
Unit
Min
Typ
89
Max
Min
Typ
89
Max
Min
Typ
88
Max Min Typ Max
IMD
intermodulation
distortion
fi = 3 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
89
88
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 70 MHz
88
88
88
87
87
86
86
84
85
83
84
ct(ch)
channel crosstalk
100
100
100
100
[1] Typical values measured at VDDA = 3 V, VDDD(1V8) = 1.8 V, Tamb = 25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at
V
DDA = 3 V, VDDD(1V8) = 1.8 V; Vi(INP) Vi(INM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified.
10.2 Clock and digital output timing
Table 7.
Symbol
Clock and digital output characteristics [1]
Parameter
Conditions
ADC1613S065
ADC1613S080
ADC1613S105
ADC1613S125
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
pins CLKP and CLKM
fclk
clock frequency
45
307
30
-
-
65
850
70
60
250
30
-
-
80
283
70
75
190
30
-
-
105
226
70
100
160
30
-
-
125 Msps
170 ns
tlat(data)
clk
data latency time
clock duty cycle
clock cycles
DCS_EN = 1:
en
50
50
50
50
70
%
td(s)
sampling delay time
wake-up time
-
-
0.8
76
-
-
-
-
0.8
76
-
-
-
-
0.8
76
-
-
-
-
0.8
76
-
-
ns
ns
twake
[1] Typical values measured at VDDA = 3 V, VDDD(1V8) = 1.8 V, Tamb = 25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at
VDDA = 3 V, VDDD(1V8) = 1.8 V; Vi(INP) Vi(INM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified.
ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
10.3 Serial output timing
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
• 3.125 Gbps data rate
• Tamb = 25 °C
• DC-coupling with two different receiver common-mode voltages
005aaa088
Fig 3. Eye diagram at 1 V receiver common-mode
005aaa089
Fig 4. Eye diagram at 2 V receiver common-mode
ADC1613S_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
11 of 39
ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
10.4 SPI timing
Table 8.
Symbol
tw(SCLK)
tw(SCLKH)
SPI timing characteristics [1]
Parameter
Conditions
Min
Typ
40
Max
Unit
ns
SCLK pulse width
-
-
-
-
SCLK HIGH pulse
width
16
ns
tw(SCLKL)
tsu
SCLK LOW pulse
width
-
-
-
-
-
-
16
5
-
-
-
-
-
-
ns
set-up time
data to
SCLK HIGH
ns
CS to
SCLK HIGH
5
ns
th
hold time
data to
SCLK HIGH
2
ns
CS to
SCLK HIGH
2
ns
fclk(max)
maximum clock
frequency
25
MHz
[1] Typical values measured at VDDA = 3 V, VDDD(1V8) = 1.8 V, Tamb = 25 C. Minimum and maximum values
are across the full temperature range Tamb = 40 C to +85 C at VDDA = 3 V, VDDD(1V8) = 1.8 V;
Vi(INP) Vi(INM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless
otherwise specified.
t
t
w(SCLKL)
t
su
t
t
h
h
su
t
w(SCLKH)
t
w(SCLK)
CS
SCLK
SDIO
W1
W0
A12
A11
D2
D1
D0
R/W
005aaa065
Fig 5. SPI timing
ADC1613S_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
12 of 39
ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
11. Application information
11.1 Analog inputs
11.1.1 Input stage description
The analog input of the ADC1613S supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (VI(cm)) on pins INP and INM set to 0.5VDDA
.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.2 and Table 21).
Figure 6 shows the equivalent circuit of the sample-and-hold input stage, including
ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
package
ESD
parasitics
switch
on
R
= 15 Ω
8
7
INP
INM
C
C
s
s
internal
clock
switch
R
= 15 Ω
on
internal
clock
005aaa185
Fig 6. Input sampling circuit
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.1.2 Anti-kickback circuitry
Anti-kickback circuitry (RC filter in Figure 7) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
ADC1613S_SER
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Single 16-bit ADC; serial JESD204A interface
R
INP
C
R
INM
005aaa073
Fig 7. Anti-kickback circuit
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
Table 9.
RC coupling versus input frequency, typical values
Input frequency (MHz)
Resistance ()
Capacitance (pF)
3
25
12
12
12
8
70
170
8
11.1.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 8 would be suitable for a baseband application.
ADT1-1WT
100 nF
25 Ω
INP
100 nF
analog
input
25 Ω
25 Ω
12 pF
100 nF
25 Ω
100 nF
INM
VCM
100 nF
100 nF
005aaa044
Fig 8. Single transformer configuration
ADC1613S_SER
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ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
The configuration shown in Figure 9 is recommended for high frequency applications. In
both cases, the choice of transformer is a compromise between cost and performance.
ADT1-1WT
ADT1-1WT
12 Ω
INP
100 nF
50 Ω
50 Ω
50 Ω
50 Ω
analog
input
8.2 pF
12 Ω
INM
100 nF
VCM
100 nF
100 nF
005aaa045
Fig 9. Dual transformer configuration
11.2 System reference and power management
11.2.1 Internal/external reference
The ADC1613S has a stable and accurate built-in internal reference voltage to adjust the
ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF an
SENSE (see Figure 11 to Figure 14), in 1 dB steps between 0 dB and 6 dB, via SPI
control bits INTREF[2:0] (when bit INTREF_EN = logic 1; see Table 21). The equivalent
reference circuit is shown in Figure 10. External reference is also possible by providing a
voltage on pin VREF as described in Figure 14.
ADC1613S_SER
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ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
REFT
REFERENCE
AMP
REFB
VREF
EXT_ref
BANDGAP
REFERENCE
EXT_ref
BUFFER
ADC CORE
SENSE
SELECTION
LOGIC
005aaa164
Fig 10. Reference equivalent schematic
Table 10 shows how to choose between the different internal/external modes:
Table 10. Reference modes
Mode
SPI bit, “Internal
reference”
SENSE pin
VREF pin
Full-scale,
(V (p-p))
Internal (Figure 11)
Internal (Figure 12)
0
0
1
0
GND
330 pF capacitor
to GND
2
VREF pin = SENSE pin and
330 pF capacitor to GND
1
Internal, SPI mode
(Figure 13)
VREF pin = SENSE pin and
330 pF capacitor to GND
1 to 2
External (Figure 14)
VDDA
External voltage 1 to 2
from 0.5 V to 1 V
Figure 11 to Figure 14 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
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ADC1613S series
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Single 16-bit ADC; serial JESD204A interface
VREF
VREF
330 pF
330
pF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
005aaa116
005aaa117
Fig 11. Internal reference, 2 V (p-p) full-scale
Fig 12. Internal reference, 1 V (p-p) full-scale
VREF
VREF
330 pF
0.1 μF
V
REFERENCE
REFERENCE
EQUIVALENT
SCHEMATIC
EQUIVALENT
SCHEMATIC
SENSE
SENSE
VDDA
005aaa118
005aaa119
Fig 13. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
Fig 14. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
11.2.2 Programmable full-scale
The full-scale is programmable between 1 V (p-p) to 2 V (p-p) (see Table 11).
Table 11. Reference modes
INTREF[2:0]
000
Level
0 dB
Full-scale (V (p-p))
2
001
1 dB
2 dB
3 dB
4 dB
5 dB
6 dB
not used
1.78
1.59
1.42
1.26
1.12
1
010
011
100
101
110
111
x
11.2.3 Common-mode output voltage (VO(cm)
)
An 0.1 F filter capacitor should be connected between pin VCM and ground to ensure a
low-noise common-mode output voltage. When AC-coupled, these pins can be used to
set the common-mode reference for the analog inputs, for instance via a transformer
middle point.
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ADC1613S series
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Single 16-bit ADC; serial JESD204A interface
package
ESD
parasitics
COMMON-MODE
REFERENCE
1.5 V
VCM
0.1 μF
ADC core
005aaa051
Fig 15. Reference equivalent schematic
11.2.4 Biasing
The common-mode input voltage (VI(cm)) on pins INP and INM should be set externally to
0.5VDDA for optimal performance and should always be between 0.9 V and 2 V.
11.3 Clock input
11.3.1 Drive modes
The ADC1613S can be driven differentially (LVPECL). It can also be driven by a
single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to
ground via a capacitor).
CLKP
CLKM
LVCMOS
clock input
CLKP
CLKM
LVCMOS
clock input
005aaa174
005aaa053
a. Rising edge LVCMOS
b. Falling edge LVCMOS
Fig 16. LVCMOS single-ended clock input
ADC1613S_SER
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Single 16-bit ADC; serial JESD204A interface
CLKP
CLKM
Sine
clock input
CLKP
CLKM
Sine
clock input
005aaa173
005aaa054
a. Sine clock input
b. Sine clock input (with transformer)
CLKP
CLKM
LVPECL
clock input
005aaa172
c. LVPECL clock input
Fig 17. Differential clock input
11.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode
voltage of the differential input stage is set via internal 5 k resistors.
package
ESD
parasitics
CLKP
V
cm(clk)
SE_SEL SE_SEL
5 kΩ
5 kΩ
CLKM
005aaa081
Vcm(clk) = common-mode voltage of the differential input stage.
Fig 18. Equivalent input circuit
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Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If
single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit
SE_SEL.
If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
11.3.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = logic 1; see Table 20), the circuit can handle signals with duty cycles of
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
Table 12. Duty cycle stabilizer
bit DCS_EN
Description
0
1
duty cycle stabilizer disable
duty cycle stabilizer enable
11.3.4 Clock input divider
The ADC1613S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV2_SEL = logic 1; see Table 20). This feature allows the user to
deliver a higher clock frequency with better jitter performance, leading to a better SNR
result once acquisition has been performed.
11.4 Digital outputs
11.4.1 Serial output equivalent circuit
The JESD204A standard specifies that if the receiver and the transmitter are DC-coupled,
both must be fed from the same supply.
V
DDD
V
DDD
50 Ω
50 Ω
CMLP
CMLN
100 Ω
RECEIVER
+
-
AGND
12 mA to 26 mA
005aaa197
Fig 19. CML output connection to the receiver in DC-coupling
The output should be terminated when 100 (typical) is reached at the receiver side.
ADC1613S_SER
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Single 16-bit ADC; serial JESD204A interface
V
DDD
50 Ω
50 Ω
10 nF
CMLP
100 Ω
RECEIVER
10 nF
CMLN
+
-
12 mA to 26 mA
005aaa187
Fig 20. CML output connection to the receiver in AC-coupling
11.5 JESD204A serializer
For more information about the JESD204A standard refer to the JEDEC web site.
11.5.1 Digital JESD204A formatter
The block placed after the ADC cores is used to implement all functions of the JESD204A
standard. This ensures signal integrity and guarantees the clock and the data recovery at
the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
M CONVERTERS
N bits from Cr
L LANES
F octets
+
0
CS bits for control
FRAME
TO
OCTETS
ALIGNMENT
CHARACTER
GENERATOR
8-bit/
10-bit
SCRAMBLER
SER
LANE 0
TX transport layer
SYNC~
TX CONTROLLER
N' = N + CS
S samples per frame cycle
CF: position of controls bits
HD: frame boundary break
Padding with Tails bits (TT)
005aaa198
M
×
(N'
×
S) bits
L
×
(F) octets
L octets
Fig 21. General overview of the JESD204A serializer
ADC1613S_SER
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ADC1613S series
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Single 16-bit ADC; serial JESD204A interface
ADC_MODE[1:0]
SCR_IN_MODE
PRBS
11
10
N
LANE_MODE[1:0]
10 00
DUMMY
16
16
16
AND N + CS
CS
8
00
01
8-bit/
10-bit
SCR
PRBS
LANE_POL
ADC_PD
ADC
FSM
(frame assembly,
character
'0'
01
10
11
SER
00
FRAME
'0/1'
ASSEMBLY
replication,
ILA,
test mode)
PRBS
× 1
× F
frame CLK
PLL
AND
DLL
character CLK
SWING_SEL[2:0]
× 10F bit CLK
001aam780
sync_request
Fig 22. Detailed view of the JESD204A serializer with debug functionality
11.5.2 ADC core output codes versus input voltage
Table 13 shows the data output codes for a given analog input voltage.
Table 13. Output codes versus input voltage
INP-INM (V)
Offset binary
Two’s complement
1000 0000 0000 0000
1000 0000 0000 0000
1000 0000 0000 0001
1000 0000 0000 0010
1000 0000 0000 0011
1000 0000 0000 0100
....
OTR
< 1
1
0000 0000 0000 0000
0000 0000 0000 0000
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0.99996948 0000 0000 0000 0001
0.99993896 0000 0000 0000 0010
0.99990845 0000 0000 0000 0011
0.99987793 0000 0000 0000 0100
....
....
0.00006104 0111 1111 1111 1110
0.00003052 0111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0010
....
0
1000 0000 0000 0000
+0.00003052 1000 0000 0000 0001
+0.00006104 1000 0000 0000 0010
....
....
+0.99987793 1111 1111 1111 1011
+0.99990845 1111 1111 1111 1100
+0.99993896 1111 1111 1111 1101
+0.99996948 1111 1111 1111 1110
0111 1111 1111 1011
0111 1111 1111 1100
0111 1111 1111 1101
0111 1111 1111 1110
0111 1111 1111 1111
0111 1111 1111 1111
+1
1111 1111 1111 1111
1111 1111 1111 1111
> +1
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Single 16-bit ADC; serial JESD204A interface
11.6 Serial Peripheral Interface (SPI)
11.6.1 Register description
The ADC1613S serial interface is a synchronous serial communications port allowing
easy interfacing with many industry microprocessors. It provides access to the registers
that control the operation of the chip in both read and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
Pin SCLK acts as the serial clock and pin CS acts as the serial chip select.
Each read/write operation is sequenced by the CS signal and enabled by a LOW level to
to drive the chip with N bytes, depending on the content of the instruction byte
(see Table 14).
Table 14. Instruction bytes for the SPI
MSB
LSB
0
Bit
7
6
5
4
3
2
1
Description
R/W[1]
A7
W1
A6
W0
A5
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
[1] R/W indicates whether a read or write transfer occurs after the instruction byte
Table 15. Read or Write mode access description
R/W[1]
Description
0
1
Write mode operation
Read mode operation
[1] Bits W1 and W0 indicate the number of bytes transferred.
Table 16. Number of bytes to be transferred
W1
0
W0
0
Number of bytes transferred
1 byte
0
1
2 bytes
1
0
3 bytes
1
1
4 or more bytes
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. The falling edge on pin CS in combination with a rising edge on pin SCLK determine
the start of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can be vary in length but is always
a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on pin CS indicates the end of data transmission.
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ADC1613S series
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Single 16-bit ADC; serial JESD204A interface
CS
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa086
Fig 23. Transfer diagram for two data bytes (3-wire type)
ADC1613S_SER
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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11.6.2 Channel control
Table 17. Register allocation map
Address Register name Access[1]
(hex)
Bit definition
Default[2]
(bin)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC control register
0003
0005
SPI control
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
ENABLE
-
1111 1111
Reset and
Operating modes
SW_RST
PD[1:0]
0000
0000
0006
0008
0013
0014
0015
0016
Clock
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
SE_SEL
-
DIFF_SE
-
CLKDIV2_
SEL
DCS_EN
0000
000*
Vref
INTREF_EN
INTREF[2:0]
0000
0000
Offset
DIG_OFFSET[5:0]
-
0000
0000
Test pattern 1
Test pattern 2
Test pattern 3
-
-
TESTPAT_1[2:0]
0000
0000
TESTPAT_2[15:8]
0000
0000
TESTPAT_3[7:0]
0
0000
0000
JESD204A control
0801
0802
0805
Ser_Status
Ser_Reset
Ser_Control1
R
RXSYNC
_ERROR
RESERVED[2:0]
0
0
0
POR_TST RESERVED 0110
0000
R/W
R/W
SW_RST
0
0
FSM_SW_
RST
0
0
0000
0000
0
RESERVED SYNC_POL SYNC_
1
REV_
SCR
REV_
ENCODER
REV_SERIAL 0100
1001
SINGLE_
ENDED
0808
0809
Ser_Analog_Ctrl R/W
Ser_ScramblerA R/W
0
0
0
0
0
0
SWING_SEL[2:0]
0000
0011
LSB_INIT[6:0]
0000
0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 17. Register allocation map …continued
Address Register name Access[1]
(hex)
Bit definition
Default[2]
(bin)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
MSB_INIT[7:0]
0
Bit 2
Bit 1
Bit 0
080A
080B
Ser_ScramblerB R/W
Ser_PRBS_Ctrl R/W
1111 1111
0
0
0
0
0
PRBS_TYPE[1:0]
0000
0000
0820
0821
0822
Cfg_0_DID
Cfg_1_BID
R
DID[7:0]
1110
1101
R/W*
R/W*
0
0
0
0
0
0
0
0
BID[3:0]
0000
1010
Cfg_3_SCR_L
SCR
0
0
0
0
L
0000
0000
0823
0824
0825
Cfg_4_F
Cfg_5_K
Cfg_6_M
R/W*
R/W*
R/W*
0
0
0
0
0
0
0
0
0
F[2:0]
0000 0***
000* ****
K[4:0]
0
0
0
0
0
M
0000
000*
0826
0827
0828
0829
082D
Cfg_7_CS_N
Cfg_8_Np
Cfg_9_S
R/W*
R/W*
R/W*
0
0
CS[0]
0
0
0
0
0
N[3:0]
0100
0110
0
0
0
0
NP[4:0]
0000
1111
0
0
0
0
0
0
0
0
S
0000
0000
Cfg_10_HD_CF R/W*
Cfg_02_2_LID R/W*
Cfg02_13_FCHK R
HD
0
CF[1:0]
*000
0000
LID[4:0]
0001
1100
084D
0871
FCHK[7:0]
**** ****
Lane_0_Ctrl
R/W
0
0
SCR_IN_
MODE
LANE_MODE[1:0]
ADC_MODE[1:0]
0
LANE_
POL
0
0
LANE_PD 0000
0000
0891
ADC_0_Ctrl
R/W
0
0
0
ADC_PD
0000
0000
[1] an "*" in the Access column means that this register is subject to control access conditions in Write mode.
[2] an "*" in the Default column replaces a bit of which the value depends on the binary level of external pins (e.g. CFG[3:0], Swing[1:0], Scrambler).
ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
11.6.3 Register description
11.6.3.1 ADC control registers
Table 18. Register SPI control (address 0003h)
Default values are highlighted.
Bit
7 to 2
1
Symbol
-
Access Value
Description
-
111111
not used
ENABLE
R/W
ADC SPI control enable:
0
1
1
ADC does not get the next SPI command
ADC gets the next SPI command
not used
0
-
-
Table 19. Register Reset and Power-down mode (address 0005h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7
SW_RST
R/W
reset digital part:
no reset
0
1
performs a reset of the digital part
not used
6 to 2
-
-
00000
1 to 0 PD[1:0]
R/W
power-down mode:
normal (power-up)
full power-down
sleep
00
01
10
11
normal (power-up)
Table 20. Register Clock (address 0006h)
Default values are highlighted.
Bit
7 to 5
4
Symbol
-
Access Value
Description
-
000
not used
SE_SEL
R/W
select SE clock input pin:
select CLKM input
select CLKP input
differential/single ended clock input select:
fully differential
single-ended
0
1
3
DIFF_SE
R/W
0
1
0
2
1
-
-
not used
CLKDIV2_SEL
R/W
select clock input divider by 2:
disable
0
1
enable
0
DCS_EN
R/W
duty cycle stabilizer enable:
disable
0
1
enable
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Single 16-bit ADC; serial JESD204A interface
Table 21. Register Vref (address 0008h)
Default values are highlighted.
Bit
7 to 4
3
Symbol
Access Value
Description
-
-
0000
not used
INTREF_EN
R/W
enable internal programmable VREF mode:
disable
0
1
enable
2 to 0 INTREF[2:0]
R/W
programmable internal reference:
0 dB (FS = 2 V)
000
001
010
011
100
101
110
111
1 dB (FS = 1.78 V)
2 dB (FS = 1.59 V)
3 dB (FS = 1.42 V)
4 dB (FS = 1.26 V)
5 dB (FS = 1.12 V)
6 dB (FS = 1 V)
not used
Table 22. Digital offset adjustment (address 0013h)
Default values are highlighted.
Register offset
Decimal
DIG_OFFSET[5:0]
+31
...
011111
...
+31 LSB
...
0
000000
...
0
...
...
32
100000
32 LSB
Table 23. Register Test pattern 1 (address 0014h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 3
-
-
00000
not used
2 to 0 TESTPAT_1[2:0]
R/W
digital test pattern:
000
001
010
011
100
101
110
111
off
mid-scale
FS
+ FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern, to be written in register 0015h and 0016h
‘010101...’
‘101010...’
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Table 24. Register Test pattern 2 (address 0015h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 0
TESTPAT_2[15:8]
R/W 00000000 custom digital test pattern (bit 15 to 8)
Table 25. Register Test pattern 3 (address 0016h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 0 TESTPAT_3[7:0]
R/W 00000000 custom digital test pattern (bit 7 to 0)
11.6.4 JESD204A digital control registers
Table 26. SER_Status (address 0801h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7
RXSYNC_ERROR R/W
0
set to 1 when a synchronization error occurs
6 to 4 RESERVED[2:0]
R
-
110
00
0
reserved
3 to 2
-
not used
1
0
POR_TST
RESERVED
R
-
power-on-reset
reserved
0
Table 27. SER_Reset (address 0802h)
Default values are highlighted.
Bit
7
Symbol
SW_RST
-
Access Value
Description
R/W
-
0
initiates a software reset of the JEDEC204A unit
6 to 4
3
000
0
not used
FSM_SW_RST
R/W
initiates a software reset of the internal state machine of
JEDEC204A unit
2 to 0
-
-
000
not used
Table 28. SER_Control1 (address 0805h)
Default values are highlighted.
Bit
7
Symbol
-
Access Value
Description
-
0
0
not used
6
RESERVED
SYNC_POL
-
reserved
5
R/W
defines the sync signal polarity:
synchronization signal is active LOW
synchronization signal is active HIGH
defines the input mode of the sync signal:
synchronization input mode is set in Differential mode
synchronization input mode is set in Single-ended mode
not used
0
1
4
SYNC_SINGLE_ENDED R/W
0
1
1
3
2
-
-
-
REV_SCR
LSB are swapped to MSB at the scrambler input:
disable
0
1
enable
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Single 16-bit ADC; serial JESD204A interface
Table 28. SER_Control1 (address 0805h) …continued
Default values are highlighted.
Bit
Symbol
Access Value
Description
1
REV_ENCODER
-
LSB are swapped to MSB at the 8-bit/10-bit encoder input:
0
1
-
disable
enable
0
REV_SERIAL
LSB are swapped to MSB at the lane input:
0
1
disable
enable
Table 29. SER_Analog_Ctrl (address 0808h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 3
-
-
00000
not used
2 to 0 SWING_SEL[2:0]
R/W
011
defines the swing output for the lane pads
Table 30. SER_ScramblerA (address 0809h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7
-
-
0
not used
6 to 0 LSB_INIT[6:0]
R/W
0000000 defines the initialization vector for the scrambler polynomial
(lower)
Table 31. SER_ScramblerB (address 080Ah)
Default values are highlighted.
Bit
Symbol
Access Value
R/W
Description
7 to 0 MSB_INIT[7:0]
11111111 defines the initialization vector for the scrambler polynomial
(upper)
Table 32. SER_PRBS_Ctrl (address 080Bh)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 2
-
-
000000
not used
1 to 0 PRBS_TYPE[1:0]
R/W
defines the type of Pseudo-Random Binary Sequence (PRBS)
generator to be used:
00 (reset)
PRBS-7
PRBS-7
PRBS-23
PRBS-31
01
10
11
Table 33. Cfg_0_DID (address 0820h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 0 DID[7:0]
R
11101101 defines the device (= link) identification number
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Single 16-bit ADC; serial JESD204A interface
Table 34. Cfg_1_BID (address 0821h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 4
-
-
0000
not used
3 to 0 BID[3:0]
R/W
1010
defines the bank ID – extension to DID
Table 35. Cfg_3_SCR_L (address 0822h)
Default values are highlighted.
Bit
7
Symbol
Access Value
Description
SCR
R/W
-
0
scrambling enabled
6 to 1
0
-
000000
0
not used
L
R/W
defines the number of lanes per converter device, minus 1
Table 36. Cfg_4_F (address 0823h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 3
-
-
00000
not used
2 to 0 F[2:0]
R/W
***
defines the number of octets per frame, minus 1
Table 37. Cfg_5_K (address 0824h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 5
-
-
000
not used
4 to 0 K[4:0]
R/W
*****
defines the number of frames per multiframe, minus 1
Table 38. Cfg_6_M (address 0825h)
Default values are highlighted.
Bit
7 to 1
0
Symbol
Access Value
Description
-
-
0000000 not used
M
R/W
*
defines the number of converters per device, minus 1
Table 39. Cfg_7_CS_N (address 0826h)
Default values are highlighted.
Bit
7
Symbol
Access Value
Description
-
-
0
not used
6
CS[0]
-
R/W
-
1
defines the number of control bits per sample, minus 1
not used
5 to 4
00
0110
3 to 0 N[3:0]
R/W
defines the converter resolution
Table 40. Cfg_8_Np (address 0827h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 5
-
-
000
not used
4 to 0 NP[4:0]
R/W
01111
defines the total number of bits per sample, minus 1
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Table 41. Cfg_9_S (address 0828h)
Default values are highlighted.
Bit
7 to 1
0
Symbol
Access Value
Description
-
-
0000000 not used
S
R/W
0
defines number of samples per converter per frame cycle
Table 42. Cfg_10_HD_CF (address 0829h)
Default values are highlighted.
Bit
7
Symbol
Access Value
Description
HD
-
R/W
R
*
defines high density format
6 to 2
00000
00
not used
1 to 0 CF[1:0]
R/W
defines number of control words per frame clock cycle per link.
Table 43. Cfg02_2_LID (address 082Dh)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 5
-
-
000
not used
4 to 0 LID[4:0]
R/W
11100
defines lane identification number
Table 44. Cfg01_13_FCHK (address 084Dh)
Default values are highlighted.
Bit
Symbol
Access Value
********
Description
7 to 0 FCHK[7:0]
R
defines the checksum value for lane
checksum corresponds to the sum of all the link configuration
parameters module 256 (as defined in JEDEC Standard
No.204A)
Table 45. Lane_0_ctrl (address 0871h)
Default values are highlighted.
Bit
7
Symbol
Access Value
Description
-
-
0
not used
6
SCR_IN_MODE
R/W
defines the input type for scrambler and 8-bit/10-bit units:
0 (reset)
(normal mode) = input of the scrambler and 8-bit/10-bit
units is the output of the frame assembly unit.
1
input of the scrambler and 8-bit/10-bit units is the PRSB
generator (PRBS type is defined with “PRBS_TYPE[1:0]”
(Ser_PRBS_Ctrl register)
5 to 4 LANE_MODE[1:0]
R/W
defines output type of lane output unit:
00 (reset)
normal mode: lane output is the 8-bit/10-bit output unit
constant mode: lane output is set to a constant (0 0)
toggle mode: lane output is toggling between 0 0 and 0 1
01
10
11
PRBS mode: lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register)
3
-
-
0
not used
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Single 16-bit ADC; serial JESD204A interface
Table 45. Lane_0_ctrl (address 0871h) …continued
Default values are highlighted.
Bit
Symbol
Access Value
Description
2
LANE_POL
R/W
defines lane polarity:
lane polarity is normal
lane polarity is inverted
reserved
0
1
1
0
RESERVED
Lane_PD
R/W
R/W
0
lane power-down control:
lane is operational
lane is in Power-down mode
0
1
Table 46. ADC_0_ctrl (address 0891h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 6
-
-
00
not used
5 to 4 ADC_MODE[1:0]
R/W
defines input type of JESD204A unit
ADC output is connected to the JESD204A input
not used
00 (reset)
01
10
JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[13:0] = “10011011101010”
11
JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE[1:0]” (Ser_PRBS_ctrl register)
3 to 1
0
-
-
000
not used
ADC_PD
R/W
ADC power-down control:
ADC is operational
ADC is in Power-down mode
0
1
ADC1613S_SER
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Single 16-bit ADC; serial JESD204A interface
12. Package outline
HVQFN32R: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; resin based; body 7 x 7 x 0.8 mm
SOT1152-1
D
B
A
terminal 1
index area
A
E
detail X
e
1
∅ v
∅ w
C
C
A
B
e
b
C
y
y
1/2 e
C
1
L
1
9
16
L
8
17
e
e
2
E
h
1/2 e
1
24
terminal 1
index area
32
25
X
D
h
0
2.5
5 mm
scale
Dimensions
Unit
A
b
D
D
h
E
E
h
e
e
1
e
2
L
L
1
v
w
y
y
1
max 0.90 0.28 7.1 4.05 7.1 4.05
mm nom 0.80 0.23 7.0 4.00 7.0 4.00 0.65 4.55 4.55 0.50 0.05 0.1 0.05 0.08 0.1
min 0.75 0.18 6.9 3.95 6.9 3.95
0.45 0.00
0.55 0.10
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included
sot1152-1_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
- - -
JEITA
- - -
09-10-13
09-11-16
SOT1152-1
Fig 24. Package outline SOT1152-1 (HVQFN32)
ADC1613S_SER
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Single 16-bit ADC; serial JESD204A interface
13. Abbreviations
Table 47. Abbreviations
Acronym
ADC
Description
Analog-to-Digital Converter
Duty Cycle Stabilizer
ElectroStatic Discharge
Intermediate Frequency
InterModulation Distortion
Least Significant Bit
DCS
ESD
IF
IMD
LSB
LVCMOS
LVPECL
MSB
OTR
Low-Voltage Complementary Metal-Oxide Semiconductor
Low-Voltage Positive Emitter-Coupled Logic
Most Significant Bit
OuT-of-Range
PRBS
SFDR
SNR
Pseudo-Random Binary Sequence
Spurious-Free Dynamic Range
Signal-to-Noise Ratio
SPI
Serial Peripheral Interface
TX
Transmitter
ADC1613S_SER
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14. Revision history
Table 48. Revision history
Document ID
Release date
Data sheet status
Change Supersedes
notice
ADC1613S_SER v.2
Modifications:
20110609
Product data sheet
-
ADC1613S_SERT v.1
• Section 10.2 “Clock and digital output timing” has been updated.
20110314 Product data sheet
ADC1613S_SER v.1
-
-
ADC1613S_SER
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Single 16-bit ADC; serial JESD204A interface
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
ADC1613S_SER
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Product data sheet
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ADC1613S series
NXP Semiconductors
Single 16-bit ADC; serial JESD204A interface
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Single 16-bit ADC; serial JESD204A interface
17. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
15
Legal information . . . . . . . . . . . . . . . . . . . . . . 37
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38
15.1
15.2
15.3
15.4
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
16
17
Contact information . . . . . . . . . . . . . . . . . . . . 38
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Clock and digital output timing . . . . . . . . . . . . 10
Serial output timing. . . . . . . . . . . . . . . . . . . . . 11
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10.1
10.2
10.3
10.4
11
11.1
Application information. . . . . . . . . . . . . . . . . . 13
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input stage description . . . . . . . . . . . . . . . . . . 13
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 13
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 14
System reference and power management . . 15
Internal/external reference . . . . . . . . . . . . . . . 15
Programmable full-scale. . . . . . . . . . . . . . . . . 17
Common-mode output voltage (VO(cm)) . . . . . 17
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Equivalent input circuit . . . . . . . . . . . . . . . . . . 19
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 20
Clock input divider . . . . . . . . . . . . . . . . . . . . . 20
Digital outputs. . . . . . . . . . . . . . . . . . . . . . . . . 20
Serial output equivalent circuit . . . . . . . . . . . . 20
JESD204A serializer. . . . . . . . . . . . . . . . . . . . 21
Digital JESD204A formatter . . . . . . . . . . . . . . 21
ADC core output codes versus input voltage . 22
Serial Peripheral Interface (SPI). . . . . . . . . . . 23
Register description . . . . . . . . . . . . . . . . . . . . 23
Channel control . . . . . . . . . . . . . . . . . . . . . . . 25
Register description . . . . . . . . . . . . . . . . . . . . 27
11.1.1
11.1.2
11.1.3
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.5
11.5.1
11.5.2
11.6
11.6.1
11.6.2
11.6.3
11.6.3.1 ADC control registers . . . . . . . . . . . . . . . . . . . 27
11.6.4
JESD204A digital control registers . . . . . . . . . 29
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 34
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 36
12
13
14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 June 2011
Document identifier: ADC1613S_SER
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