BA2016AP/1,112_技术文档

UBA2016A/15/15A

600 V fluorescent lamp driver with PFC, linear dimming and

boost function

Rev. 1 — 20 May 2011

Objective data sheet

1. General description

The UBA2016A/15/15A are high voltage Integrated Circuits (IC) intended to drive

fluorescent lamps with filaments such as Tube Lamps (TL) and Compact Fluorescent

Lamps (CFL) in general lighting applications. The IC comprises a fluorescent lamp control

module, half-bridge driver, built-in critical conduction mode Power Factor Correction

(PFC) controller/driver and several protection mechanisms. The IC drives fluorescent

lamp(s) using a half-bridge circuit made of two MOSFETs with a supply voltage of up to

600 V.

The UBA2016A/15/15A are designed to be supplied by a start-up bleeder resistor and a

dV/dt supply from the half-bridge circuit, or any other auxiliary supply derived from the

half-bridge or the PFC. The supply current of the IC is low. An internal clamp limits the

supply voltage.

2. Features and benefits

Power factor correction features:

Integrated 4-pin critical conduction mode PFC controller/driver

Open and short pin-short protection on PFC feedback pin

Overcurrent protection

Overvoltage protection

Half-bridge driver features:

Integrated level-shifter for the high-side driver of the half-bridge

Integrated bootstrap diode for the high-side driver supply of the half-bridge

Independent non-overlap time

Fluorescent lamp controller features:

Linear dimming (UBA2016A and UBA2015A only)

EOL (End-Of-Life) detection (both symmetrical and asymmetrical)

Adjustable preheat time

Adjustable preheat current

Adjustable fixed frequency preheat (UBA2015 and UBA2015A only)

Lamp ignition failure detection

Ignition detection of all lamps fat multiple lamps with separate resonant tanks

Second ignition attempt if first failed

Constant output power independent of mains voltage variations

Automatic restart after changing lamps

Adjustable lamp current boost at start-up (UBA2016A only)

Lamp current control

UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

Enable input (UBA2015 and UBA2015A only)

Protection

Hard switching/capacitive mode protection

Half-bridge overcurrent (coil saturation) protection

Lamp overvoltage (lamp removal) protection

Temperature protection

3. Applications

Intended for fluorescent lamp ballasts with either a dimmable (UBA2016A and

UBA2015A) or a fixed (UBA2015) output and PFC for AC mains voltages of up to

390 V.

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

SO20

DIP20

Description

Version

UBA2016AT/N1

UBA2015T/N1

UBA2015AT/N1

UBA2016AP/N1

UBA2015P/N1

UBA2015AP/N1

plastic small package outline package; 20 leads; body width 7.5 mm

plastic dual in-line package; 20 leads; (300 mil)

SOT163-1

SOT146-1

Table 2.

Functional selection

Type

PFC

dim

Boost

fixed frequency

preheat

UBA2016A

UBA2015

yes

no

yes

no

yes

UBA2015A

yes

no

UBA2016A_15_15A

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Objective data sheet

Rev. 1 — 20 May 2011

2 of 42

UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

5. Block diagram

UBA2016A

VDD

5 μA

14 GPFC

GATE

DRIVE

DEMAG

OVPFC

0.1 V

13

AUXPFC

TEMPERATURE

SENSE

1.39 V

SUPPLY

AND

REFERENCES

S

R

140 °C

80 °C

5

FBPFCOK

PFCOSP

IREF

VDD

PFC

CONTROLLER

Q

1 V

0.25 V

16

PFCOK

11

12

FBPFC

1 mA

restart

t

1.27 V

on

13.4 V

TIMER

COMPPFC

19

FSHB

IC off

brownout

3.0 V

20 GHHB

18 SHHB

UVLO

on: > 12.4 V

off: < 10.0 V

LEVEL

SHIFTER

HIGH-SIDE

GATE DRIVE

EOL

3

end of life

OR

2 x

16 μA

HARD

SWITCHING/

CAPACITIVE

MODE DETECTION

OVextra

OV

5 μA

3.35 V

17 GLHB

NON

OVERLAP

LOW-SIDE

GATE DRIVE

FLUORESCENT

LAMP

CONTROLLER

2.5 V

VDD

ign

VFB

4

OCpreheat

0.5 V

8.5 μA

1 V

1

8

SLHB

CPT

VFBlow

80 mV

OCburn

2.5 V

2.6 μA

LAMP

ON

DETECTION

TIMER

10 BOOST

VCO

100 μA

overcurrent

1 V

3 V

IFB

2

0.5 V

9 μA

not burn

5 V

60 kΩ

26 μA

5 V 1.27 V

5 V

47 μA

9

6

7

DIM

CIFB

CF

001aam531

Fig 1. Block diagram UBA2016A

UBA2016A_15_15A

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Objective data sheet

Rev. 1 — 20 May 2011

3 of 42

UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

VDD

UBA2015

UBA2015A

5 μA

14 GPFC

GATE

DRIVE

DEMAG

OVPFC

0.1 V

13

AUXPFC

TEMPERATURE

SENSE

1.39 V

SUPPLY

AND

REFERENCES

S

R

140 °C

80 °C

5

FBPFCOK

PFCOSP

IREF

VDD

PFC

CONTROLLER

Q

1 V

0.25 V

16

PFCOK

11

12

FBPFC

1 mA

restart

t

1.27 V

on

13.4 V

TIMER

COMPPFC

19

FSHB

IC off

brownout

3.0 V

20 GHHB

18 SHHB

UVLO

on: > 12.4 V

off: < 10.0 V

LEVEL

SHIFTER

HIGH-SIDE

GATE DRIVE

EOL

3

end of life

OR

2 x

16 μA

HARD

SWITCHING/

CAPACITIVE

MODE DETECTION

OVextra

OV

5 μA

3.35 V

17 GLHB

NON

OVERLAP

LOW-SIDE

GATE DRIVE

2.5 V

VDD

FLUORESCENT

LAMP

CONTROLLER

ign

VFB

4

OCpreheat

0.5 V

8.5 μA

1 V

1

8

SLHB

CPT

VFBlow

80 mV

OCburn

2.5 V

2.6 μA

LAMP

ON

TIMER

DETECTION

FIXED

FREQUENCY

PREHEAT

10 PH/EN

VCO

100 μA

overcurrent

1 V

3 V

IFB

2

0.5 V

9 μA

not burn

5 V

60 kΩ

26 μA

5 V

1.27 V

5 V

47 μA

0.25 V

(1)

9

6

7

DIM

CIFB

CF

001aan208

(1) Pin 9 is not connected in the UBA2015.

Fig 2. Block diagram UBA2015A and UBA2015

UBA2016A_15_15A

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Objective data sheet

Rev. 1 — 20 May 2011

4 of 42

UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

6. Pinning information

6.1 Pinning

1

2

20

19

18

17

16

15

14

13

12

11

1

2

20

19

18

17

16

15

14

13

12

11

SLHB

IFB

GHHB

FSHB

SLHB

IFB

GHHB

FSHB

3

EOL

SHHB

GLHB

EOL

VFB

IREF

CIFB

CF

SHHB

GLHB

4

VFB

5

IREF

CIFB

CF

VDD

UBA2016A

UBA2015

6

GND

7

GPFC

AUXPFC

COMPPFC

FBPFC

GPFC

AUXPFC

COMPPFC

FBPFC

8

CPT

n.c.

9

DIM

10

BOOST

PH/EN

001aam532

001aan200

Fig 3. Pin configuration UBA2016A

Fig 4. Pin configuration UBA2015

1

2

20

19

18

17

16

15

14

13

12

11

SLHB

IFB

GHHB

FSHB

3

EOL

VFB

IREF

CIFB

CF

SHHB

GLHB

4

5

VDD

UBA2015A

6

GND

7

GPFC

AUXPFC

COMPPFC

FBPFC

8

CPT

DIM

9

10

PH/EN

001aan199

Fig 5. Pin configuration UBA2015A

6.2 Pin description

Table 3.

Symbol

Pin description

Pin Description

SLHB

IFB

1

half-bridge (HB) low-side switch current sense input

lamp current feedback input

2

3

4

5

6

7

8

9

EOL

VFB

IREF

CIFB

CF

end-of-life sensing input

lamp voltage feedback input

reference current setting

lamp current feedback compensation

high frequency (HF) oscillator timing capacitor

preheat and fault timing capacitor

dimming function input UBA2016A and UBA2015A

UBA2015

CPT

DIM

n.c.

UBA2016A_15_15A

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Objective data sheet

Rev. 1 — 20 May 2011

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UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

Table 3.

Pin description …continued

Symbol

BOOST

PH/EN

10

11

Description

boost function input UBA2016A

preheat frequency setting combined with enable UBA2015 and UBA2015A

PFC feedback input

FBPFC

COMPPFC 12

PFC output voltage feedback compensation

PFC auxiliary winding input

AUXPFC

GPFC

GND

13

14

15

16

17

18

19

20

PFC gate driver output

ground

VDD

supply

GLHB

SHHB

FSHB

GHHB

HB low-side switch gate driver output

HB high-side source connection

HB floating supply connection

HB high-side switch gate driver output

7. Functional description

7.1 Introduction

The UBA2016A/15/15A is an integrated circuit for electronically ballasted fluorescent

lamps. It provides a critical conduction mode Power Factor Correction (PFC)

controller/driver and a half-bridge controller/driver with all the necessary functions for

correct preheat, ignition and on-state operation of the lamp. Several protection

mechanisms are incorporated to ensure the safe operation of the fluorescent lamp or a

shut down of the complete ballast under any abnormal operating conditions or lamp

failure.

7.2 Power Factor Correction (PFC)

The PFC is a boundary conduction mode, on-time controlled system. The basic

application diagram can be found in Figure 6. This type of PFC operates at the boundary

between continuous and discontinuous mode. Energy is stored in the inductor L_PFCeach

period that switch Q_PFCis on. When the input current I_i(PFC)is zero at the moment that

Q_PFCis switched on, the amplitude of the current build up in L_PFCwill be proportional to

V

_i(PFC)and the time t_on(PFC)that Q_PFCis on. This current continues to flow as output

current I_o(PFC)via D_PFCinto C_BUSafter Q_PFCis switched off. In this phase I_o(PFC)is equal to

_i(PFC). A new cycle is started when I_o(PFC)reaches zero. I_i(PFC)consists of a sequence of

triangular pulses, each having an amplitude proportional to the input voltage and t_on(PFC)

I

.

If t_on(PFC)is kept constant, the first harmonic of the input current is proportional to the input

voltage. The PFC output voltage V_o(PFC)is controlled by t_on(PFC). As t_on(PFC)is more slowly

regulated than the mains frequency it will not disturb the power factor.

UBA2016A_15_15A

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Objective data sheet

Rev. 1 — 20 May 2011

6 of 42

UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

D

bypass

V

DSRmains

V

o(PFC)

D

PFC

l

o(PFC)

i(PFC)

I

switch(PFC)

L

PFC

R1

Q

PFC

C

BUS

mains

R3

R2

GPFC

FBPFC

AUXPFC

UBA2016A

UBA2015

UBA2015A

VDD

C1

C2

COMPPFC

R4

GND

001aam533

Fig 6. Basic PFC application diagram

7.2.1 Regulation loop

The control loop senses the PFC output voltage via resistors R1, R2 and the feedback

input FBPFC. The frequency compensation network C1, C2 and R4 sets the response

time and stability of the loop. The voltage at pin FBPFC is regulated to V_reg(FBPFC). When

voltage on pin FBPFC is above the regulation voltage, pin COMPPFC is charged and

when voltage on pin FBPFC is lower, pin COMPPFC is discharged. Current flow through

pin COMPPFC is controlled by the PFC Operational Transconductance Amplifier (OTA)

and its transconductance g_m(PFC). The voltage on pin COMPPFC controls the PFC

on-time, t_on(PFC). So when the voltage at pin FBPFC is too high, t_on(PFC)is reduced and

less energy is transferred. When voltage at pin FBPFC is too low, t_on(PFC)is increased and

more energy is transferred.

The voltage on pin FBPFC is sampled at the rising edge of pin GPFC and held internally

during the leading edge blanking time t_leb(FBPPC)before going to the OTA to prevent

disturbance of the regulation level due to transition effects when the PFC external power

switch is turned on

The maximum t_on(PFC)is set when the voltage at pin COMPPFC is clamped to

V

_{clamp(COMPPFC)}to limit the dead time in recovering regulation after a regulation range

overshoot. The t_on(PFC)time can be regulated down to zero. The moment at which the

gate is turned on is determined by pin AUXPFC. When this pin is below demagnetization

detection voltage V_{det(demag)AUXPFC}and the low PFC off-time t_off(PFC)lowtimer is finished,

the next cycle starts.

During start-up, the capacitor connected to pin COMPPFC is connected by an internal

switch to pin FBPFC which allows it to partially charge before the PFC starts. This reduces

the start-up time.

UBA2016A_15_15A

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Objective data sheet

Rev. 1 — 20 May 2011

7 of 42

UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

7.2.2 Protection

The PFC incorporates the following protection mechanisms:

• When voltage on pin FBPFC drops below open/short protection threshold voltage

V_{th(osp)(FBPFC)}, the gate is turned off and the start of a new cycle is inhibited. A small

internal filter prevents this protection reacting to a negative spike.

• When pin FBPFC is left open, a pull-down bias current I_bias(FBPFC)ensures that the pin

voltage drops below V_{th(osp)(FBPFC)}

.

• When voltage at pin FBPFC rises above overvoltage threshold voltage V_{th(ov)(FBPFC)}

the gate immediately turns off. A new cycle will not start while V_FBPFCremains above

V

_{th(ov)(FBPFC)}. This limits the PFC output voltage. This protection is disabled during the

leading edge blanking time t_leb(FBPFC)after GPFC goes high.

• When the t_off(PFC)lowtimer sequence has ended with no demagnetization detected

(V_AUXPFChas not risen above V_det(demag)) the on-time of the next cycle will be the no

demagnetization detected PFC on-time t_{on(PFC)nodemag}to prevent excessive current

build up in the coil.

• Bias current I_bias(AUXPFC)ensures that pin AUXPFC is HIGH when not connected

ensuring pin GPFC stays LOW.

7.3 Half-bridge driver

The IC incorporates drivers for the half-bridge switches and all related circuits such as

non-overlap, high voltage level shifter, bootstrap circuit for the floating supply and hard

switching and capacitive mode detection.

The UBA2016A/15/15A is designed to drive a half-bridge inverter with an inductive load.

The load consists typically of an inductor with a resonant capacitor and a TL or CFL. A

basic half-bridge application circuit driving a TL is shown in Figure 7 which also shows a

typical IC supply configuration with a start-up bleeder resistor and a dV/dt supply.

V

BUS

VDD

GHHB

SHHB

FSHB

GLHB

UBA2016A

UBA2015

UBA2015A

GND

001aam534

Fig 7. Basic half-bridge and IC supply connection diagram

UBA2016A_15_15A

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Objective data sheet

Rev. 1 — 20 May 2011

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UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

7.3.1 VDD supply

The UBA2016A/15/15A is intended to be supplied by a start-up bleeder resistor

connected between the bus voltage V_BUSand VDD and a dV/dt supply from the

half-bridge point at pin SHHB.

The IC starts up when the voltage at pin VDD rises above start-up voltage V_startup(VDD)and

locks out (stops oscillating) when the voltage at pin VDD drops below stop voltage

V

_stop(VDD). The hysteresis between the start and stop levels allows the IC to be supplied

by a buffer capacitor until the dV/dt supply is settled. The UBA2016A/15/15A has an

internal VDD clamp. This is an internal active Zener (or shunt regulator) that limits the

voltage on the VDD supply pin to clamp voltage V_clamp(VDD). No external Zener diode is

needed in the dV/dt supply circuit if the maximum current of the dV/dt supply minus the

current consumption of the IC (mainly determined by the gate drivers’ load) is below

I_clamp(VDD)

.

7.3.2 Low- and high-side drivers

The low- and high-side drivers are identical. The output of each driver is connected to the

equivalent gate of an external power MOSFET. The high-side driver is supplied by the

bootstrap capacitor, which is charged from the VDD supply voltage via an internal diode

when the low-side power MOSFET is on. The low-side driver is directly supplied by the

VDD supply voltage.

7.3.3 Non-overlap

During each transition between the two states GLHB HIGH/GHHB LOW and

GLHB LOW/GHHB HIGH, GLHB and GHHB will both be LOW for a fixed non-overlap time

t_noto allow the half-bridge point to be charged or discharged by the load current

(assuming the load always has an inductive behavior), and enabling zero voltage

switching; see Figure 8.

UBA2016A_15_15A

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Objective data sheet

Rev. 1 — 20 May 2011

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UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

t

no

V

CF

0

time

V

SHHB

+ V

VDD

V

GHHB

V

SHHB

V

VDD

V

GLHB

0

V

BUS

V

SHHB

0

time

001aam537

Fig 8. Oscillator, driver and half-bridge voltages

7.4 Fluorescent lamp control

The IC incorporates all the regulation and control needed for the fluorescent lamp(s), such

as filament preheat, ignition frequency sweep, lamp voltage limitation, lamp current

control, start-up boost, dimming, end-of-life detection, overcurrent protection and hard

switching limiting.

In the UBA2016A/15/15A, 7 different operating states can be distinguished. In each state

the IC acts in a specific way, as described in the next paragraphs. Figure 9 shows the

possible transitions between the states with their conditions.

UBA2016A_15_15A

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Objective data sheet

Rev. 1 — 20 May 2011

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UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

Power on

Supply voltage definitions

reset = (V

< V

)

DD

rst(VDD)

Reset state

GLHB low

stop latch and ignition

attempt counter are reset

restart = (V

< V

(VDD))

DD

restart

reset OR disable

V

low = (V

< V

)

DD

stop(VDD)

V

high = (V > V

)

DD

startup(VDD)

GLHB AND

(reset OR disable)

reset NOT(reset)

GLHB AND

(V low

OR overtemp)

Auto-restart

state

GLHB low

Stop state

GLHB low

Standby state

GLHB high

restart

DD

Non oscillating states

(IC is off)

Low power consumption

GHHB and GPFC low

V

high AND

DD

enable AND

NOT(overtemp)

Oscillating states

(IC is on)

Preheat state

BOOST and EOL disabled

frequency is decreased

until HB preheat current or

the set value for the

preheat frequency

(UBA2015(A) only) is reached

fast fault

fault timeout

AND

(ignition attempts = 1)

Preheat time completed

Ignition state

BOOST and EOL disabled

frequency is decreased

as long as no lamp overvoltage

or HB overcurrent or

fault timeout

fault definitions:

overtemp = {set} T > T

AND

(1)

hardswitching is detected

(ignition attempts = 2)

th(act)otp

(1)

(UBA2016(A) only)

{reset} T < T

th(rel)otp

fast fault = over voltage extra OR

(1)

capacitive mode OR

(over current lamp AND f high)

f low OR

ignition detected

(2)

coil saturation

slow fault = CPT low OR

VFB low OR

Burn state

NOT(PFC OK) OR

ignition attempt counter is reset

BOOST function enabled

EOL protection enabled

Frequency determined by lamp

current regulation loop

over voltage OR

(over voltage end of life AND

NOT (deep dimming)) OR

coil saturation OR

hardswitching OR

brownout OR

(2)

fault timeout

(2)

asymetrical end of life

the fault timer is started by slow fault and runs as

long as slow fault continues. NOT(slow fault) resets

the fault timer.

Other definitions:

(1)

enable = (V

> V

)

(except for UBA2016A in IGNITION state after ZVS

has been seen)

(BURN state only)

FFPRHT

th(en)(FFPRHT)

disable = NOT(enable)

(2)

ignition detected = (V

> V

) AND (V

< V

)

IFB

th(lod)(IFB)

VFB

th(lod)(VFB)

001aam538

Fig 9. State diagram

UBA2016A_15_15A

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Objective data sheet

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UBA2016A/15/15A

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7.4.1 Reset

600 V fluorescent lamp driver

When voltage on pin VDD is below the reset voltage V_rst(VDD), both gates of the half-bridge

driver are LOW. All internal latches are reset. When voltage on pin VDD rises above

V

_rst(VDD), the IC will enter STANDBY state.

7.4.2 Standby

In STANDBY state the low-side gate driver is on (GLHB is HIGH).The floating supply

capacitor C_FSHBis then charged. When the VDD voltage rises above V_startup(VDD), the

Preheat state is entered.

7.4.3 Oscillating states (Preheat, Ignition and Burn)

The highest and lowest oscillation frequency can be set with capacitor C_CFconnected to

the CF pin. The oscillator is implemented in such a way that the lowest frequency f_sw(low)is

the most accurate. In any oscillating state (Preheat, Ignition or Burn), when VDD voltage

drops below V_stop(VDD)or overtemperature is detected, the half-bridge stops oscillation

when GLHB is HIGH and enters the STANDBY state.

7.4.4 Preheat

The oscillating frequency starts at f_sw(high)(see Figure 10 “Resonance curve application

with UBA2015A” or Figure 11 “Resonance curve application with UBA2016A” point A) and

remains at that frequency until the PFC output is sufficient (the voltage at pin FBPFC rises

above the PFC voltage OK threshold voltage on pin FBPFC, V_{th(VPFCok)FBPFC}) and the

voltages at pins CPT and VFB settle above their pin short protection levels

(V_VFB> V_th(osp)(VFB)and V_CPT> V_th(scp)(CPT)). The half-bridge current is regulated when in

the Preheat state; see Figure 10 “Resonance curve application with UBA2015A” or Figure

11 “Resonance curve application with UBA2016A” point B. Pin CIFB supplies a current

I_ch(CIFB)to the externally connected compensation network on this pin and its voltage will

rise. This will cause the switching frequency to decrease (pin CIFB is the input for the

voltage controlled oscillator). This will cause an increase in half-bridge current (assuming

the switching frequency is higher than the load resonance frequency). This current is

measured via pin SLHB using a resistor connected between the source of the low-side

switch and ground. When the voltage on pin SLHB rises above the preheat current control

voltage V_crtl(ph)SLHB, discharge current I_dch(CIFB)to pin CIFB and the frequency is

increased. When the voltage drops below V_th(ocp)SLHB, current I_ch(CIFB)from pin CIFB

causes the frequency to decrease.

UBA2016A_15_15A

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Objective data sheet

Rev. 1 — 20 May 2011

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UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

(1)

V

lamp

(1)

(2)

I

lamp

(2)

C

V

ign

E

D

I

lamp(nominal)

B

A

H

f

sw(ph)

f

sw(reg)

f

sw(dim)

f

sw(high)

sw(low)

sw(ign)

001aan202

(1) Lamp voltage when lamp is off (not ignited yet).

(2) Lamp current when lamp is on.

Fig 10. Resonance curve application with UBA2015A

(1)V

lamp

(1)

(2)

I

(2)

G

C

V

ign

F

E

D

I

lamp(nominal)

B

A

H

f

sw(high)

f

sw(bst)(reg)

sw(reg)

sw(dim)

f

sw(ph)

sw(bst)(low)

sw(low)

sw(ign)

001aan204

(1) Lamp voltage when lamp is off (not ignited yet).

(2) Lamp current when lamp is on.

Fig 11. Resonance curve application with UBA2016A

UBA2016A_15_15A

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Objective data sheet

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13 of 42

UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

The preheat frequency for UBA2015 and UBA2015A can also be regulated via pin PH/EN.

UBA2015 and UBA2015A support current controlled preheat and fixed frequency preheat.

During preheat the output voltage of pin PH/EN is V_ph(PH/EN). The output current that an

external resistor R_ext(PH/EN)connected to this pin sinks is compared to ⁴⁄₅of the output

current of the VCO (the current at pin CF with no fault condition present and the capacitor

at that pin being charged minus the same current at f_sw(low)). As long as the output current

of the VCO is bigger the frequency is being decreased (by charging pin CIFB with

I_ch(CIFB)). If the current through the external resistor is bigger the frequency will be

increased (by discharging pin CIFB with I_dch(CIFB)).

Current and fixed frequency control mechanisms are active at the same time. For fixed

frequency preheat using pin PH/EN, the half-bridge current sense resistor connected to

pin SLHB should be small enough not the activate the current control mechanism. If

current controlled preheat is used, pin PH/EN should be left open (except of course for the

open collector or open drain that drives the enable function). The preheat time t_to(ph)can

be set with capacitor C_CPTon pin CPT.

7.4.5 Ignition

After the Preheat state the IC enters the Ignition state. During the Ignition state the

switching frequency is decreased by charging pin CIFB with I_ch(CIFB). This will result in

increasing lamp voltage until the lamp ignites (see point C in Figure 10 “Resonance curve

application with UBA2015A” or Figure 11 “Resonance curve application with UBA2016A”)

and lamp-on or f_sw(low)(lowest frequency) is detected. Lamp-on detection occurs when the

average absolute voltage on pin IFB is above lamp-on detection threshold V_th(lod)(IFB)and

the voltage on pin VFB is more then 50 % of each clock cycle below the lamp-on detection

threshold V_th(lod)(VFB)and after a delay t_d(lod)

.

If either saturation, overvoltage or hard switching regulation (UBA2016A only) is triggered

it will overrule the frequency sweep down and hold the frequency at the border where the

fault appeared and start the fault timer. When the fault timeout t_to(fault)is reached the IC

enters Auto-restart state if it was the first ignition attempt, otherwise it will go to the Stop

state; see Figure 9 “State diagram”.

7.4.6 Auto-restart

The Auto-restart state is entered after a fault time out in the Ignition state during the first

ignition attempt. See Figure 9 “State diagram”. When the IC is in Auto-restart state, it

draws supply current I_restart(VDD). This will slowly discharge the buffer capacitor on pin

VDD until the voltage on this pin drops below V_restart(VDD). The IC then enters the Standby

state. Here the VDD capacitor will be charged again to start a second ignition attempt. The

bleeder current must be between standby current I_stb(VDD)and I_restart(VDD). A time delay

can be set between the two ignition attempts with the capacitor at pin VDD to reduce

stress on the HB components.

7.4.7 Burn

In Burn state the lamp current regulation and all protection circuits are active. The boost

function (available in UBA2016A only) is also enabled.

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7.4.7.1 Lamp current control and dimming

The AC lamp current is sensed by an external resistor connected to pin IFB. The resulting

AC voltage on pin IFB is internally Double-Side Rectified (DSR), and compared to a

reference level by an OTA. This reference level is determined by the internal reference

regulation level V_reg(ref)and the voltage on the DIM input (UBA2015A and UBA2016A

only), as shown in Figure 12 “Lamp current control”.

Definition: the regulation voltage on pin IFB (V_reg(IFB)) is the level seen from outside the IC

to which the IC will try to regulate the average absolute voltage on pin IFB.

If the DIM input is not present or not connected or V_DIM> V_reg(ref)then V_reg(IFB)is

V

_reg(ref)+ non-idealities from the OTA and the DSR else V_reg(IFB)= V_DIM+ non-idealities

from OTA and DSR.

For the UBA2016A V_reg(IFB)also depends on the input current on pin BOOST (I_BOOST).

The boost current is multiplied and added to the OTA output current which translates to an

extra voltage being added to V_reg(ref). See Section 7.4.7.3 “Boost” for further detail about

the boost function. For the remainder of this Section we will assume I_BOOST= 0.

For the UBA2015A and UBA2016A the DIM input controls the lamp current set point. The

DIM input level is internally clamped to V_reg(ref). The lowest possible DIM input level is set

by the bias current on pin DIM I_bias(DIM)and the external resistance on the pin. If no

dimming is required, pin DIM can be left open or connected via a capacitor to ground. The

internal current source I_bias(DIM)will then charge the pin until it is internally clamped to

V_reg(ref)

.

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OTA

DOUBLE SIDE

RECTIFIER

VDD

I

lamp

g

m(IFB)

CIFB

IFB

C

ext(CIFB)

R

i(IFB)

ext(IFB)

VOLTAGE

CONTROLLED

OSCILLATOR

VDD

I

bias(DIM)

DIM

V

reg(ref)

VDD

VOLTAGE

I

ch(low)(CF)

CONTROLLED

CURRENT SOURCE

VDD

3.5

1

BOOST

I

BOOST

V

high(CF)

clock

1

7.8

÷ 2

001aan205

CF

grey circuit parts are not present in some types

C

ext(CF)

Fig 12. Lamp current control

The output of the OTA is connected to pin CIFB. The external capacitor C_ext(CIFB)is

charged and discharged according to the voltage on the OTA inputs and the

transconductance of the OTA, g_m(IFB)according to the formula:

I_CIFB= g_m(IFB)× (V_IFB− V_reg(IFB).

More components can be connected to pin CIFB to improve the response time and

stability of the lamp current control loop.

Pin CIFB is connected to the input of the VCO (Voltage Controlled Oscillator) that

determines the frequency of the IC. Pin CIFB voltage is inversely proportional to the

switching frequency. When the load is inductive, an increase in frequency decreases the

lamp current, and a decrease in frequency increases the lamp current. With the closed

loop for the lamp current in place, the IC will regulate to the required frequency for the

desired lamp current. So when the IC enters Burn state it will go to either point D or H

shown in Figure 10 (UBA2015A) or Figure 11 (UBA2016A) depending on the DIM input

voltage.

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However, the switching frequency can never go below f_sw(low)(unless for UBA2016A when

the boost function is active, see Section 7.4.7.3). If the regulation level is not reached at

f_sw(low)the IC will stay at f_sw(low)(point E in Figure 10 and Figure 11).

7.4.7.2 Operation without lamp current control

To operate the lamp without current control the lamp current sense pin IFB must be

connected to ground. The lamp now operates at the lowest frequency f_sw(low)(point E in

Figure 10 or Figure 11). Dimming is not supported in this case.

7.4.7.3 Boost

The boost feature is available only in the UBA2016A to support shorter run up times. The

boost function changes the half-bridge switching frequency by lowering the lowest

possible switching frequency from f_sw(low)to f_sw(bst)(low)and increasing the lamp current set

point V_reg(IFB)by adding a multiple of the boost current to the OTA output current which

translates to an extra voltage being added to V_reg(ref). During boost time, the frequency is

lowered, and as a consequence of the inductive load the lamp current is increased.

The implementation of the boost function is shown in Figure 12 “Lamp current control”.

The boost input is a current input with an input range of 0 to I_sat(BOOST). The input current

is internally clamped at I_sat(BOOST). If the input current at the pin is above I_sat(BOOST)the

effect will not become bigger. The voltage on the pin is determined by the voltage drop

across the internal current mirror input and limited by an internal clamp circuit if the input

current at the pin rises above I_sat(BOOST). For maximum current allowed into the pin; see

Table 4. An example of how boost function can be implemented is shown in Figure 13.

V

o(PFC)

R

hv

C

hv

UBA2016A

BUS

R

BOOST

R

D

C

boost

bias

reset

001aam539

Fig 13. Boost application example; UBA2016A

The boost current is determined by resistor R_BOOST. R_biasprovides a small threshold for

the boost function and with capacitor C_BOOSTkeeps the BOOST pin at a defined (inactive)

level (0 V) during normal lamp operation (after the boost period). The boost time constant

is reflected by the sum of capacitors C_hvand C_BOOSTand R_BOOST. Resistor R_hvand

capacitor C_BOOSTfilter out the ripple on V_o(PFC)

.

An example of component values for V_o(PFC)= 430 V is:

R

_hv= 22 MΩ (500 V); C_hv= 100 nF (500 V); D_reset= 1N4148; C_BOOST= 150 nF (63 V);

_BOOST= 10 MΩ and R_bias= 10 MΩ.

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The amount of boost depends on the current into the BOOST pin and the lamp current

control. If the application does not use lamp current control, the switching frequency will

go down to the lowest possible boost switching frequency f_sw(bst)(low)(point G in Figure 11

“Resonance curve application with UBA2016A”) that is determined by Equation 1 or

Equation 2, depending on the value of I_BOOST

.

0 ≤ I_BOOST≤ I_sat(BOOST)→ f_sw(bst)(low)= f_sw(low)(1 – I_BOOST⋅ N_f(bst)(low)

)

(1)

(2)

I_BOOST> I_sat(BOOST)→ f_sw(bst)(low)= f_sw(low)(1 – I_sat(BOOST)⋅ N_f(bst)(low)

)

If the application uses lamp current control, the switching frequency is regulated to boost

regulation voltage on pin IFB, V_{reg(bst)(IFB)}(point F in Figure 11 “Resonance curve

application with UBA2016A”) that can be calculated by Equation 3 or Equation 4,

(depending on the value of I_BOOST) if the switching frequency remains above f_sw(bst)(low)

,

otherwise the switching frequency is f_sw(bst)(low); see Equation 1 or Equation 2.

0 ≤ I_BOOST≤ I_sat(BOOST)→ V_reg(IFB)(I_BOOST) = V_reg(IFB)(1 + I_BOOST⋅ N_l(bst)reg

I_BOOST> I_sat(BOOST)→ V_{reg(bst)(IFB)}= V_reg(IFB)+ I_sat(BOOST)⋅ N_Vreg(bst)

)

(3)

(4)

7.4.8 Stop state

When in Stop state the IC is off and all driver outputs are low. The IC will remain in Stop

state until the voltage on pin VDD drops below V_rst(VDD)or it is disabled, in which case it

will go to Reset state.

The sequence of events for entering the Stop state are shown in Figure 9 “State diagram”.

7.5 Enable and Disable

The enable function is only available in the UBA2015 and UBA2015A and works via pin

PH/EN. If this pin is pulled below the enable voltage V_en(PH/EN)then the IC goes into the

Standby state (immediately if GLHB is high, otherwise it will continue its normal clock

cycle until GLHB is high and then go to the Standby state).

The external interface with pin PH/EN for the enable signal should be an open collector or

open drain type driver. To enable the IC the open collector or open drain should be open

(high ohmic) to not disturb the fixed frequency preheat setting function of pin PH/EN.

In Restart, Standby and Stop states the standby pull-up current source I_{pu(stb)(PH/EN)}will

pull the voltage at pin PH/EN above V_en(PH/EN). In Preheat, Ignition and Burn states the

normal output voltage driver of the IC will pull the pin high. In those cases the external

driver must draw a current I_clamp(PH/EN)from the pin to disable the IC.

7.6 Protection circuits

7.6.1 End-of-life rectifying lamp detection

If voltage on pin EOL is below low threshold voltage V_th(low)EOLor above V_th(high)EOLthe

fault timer will start. These threshold voltage levels are related to pin FBPFC voltage

according to the formula: V_th(low)EOL= V_FBPFC= V_th(high)EOL/ 2. The FBPFC voltage is

sampled during GPFC low and hold during GPFC high periods to prevent disturbance of

the EOL levels due to the switching of the PFC.

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A programmable end-of-life window is achieved by the internal bias current sink I_bias(EOL)

.

The effective relative size of the EOL window will decrease in line with the increasing

series resistance connected to pin EOL.

The end-of-life lamp rectifying detection is only active during the Burn state.

7.6.2 End-of-life overvoltage detection

This protection is intended to protect against symmetrical lamp aging. When in Burn state

the voltage on pin VFB exceeds the overvoltage end-of-life threshold voltage V_{th(oveol)(VFB)}

by more then 50 % of each switching cycle the fault timer will start. V_{th(oveol)(VFB)}is related

to the regulation voltage on pin IFB V_reg(IFB)that itself is dependent on the voltage on pin

DIM (see Section 7.4.7.1 “Lamp current control and dimming”) according to the formula:

V

_{th(oveol)(VFB)}= a − b × V_reg(IFB)

Parameters a and b can be calculated from the V_{th(oveol)(VFB)}values given in Table 6.

The end-of-life overvoltage protection is only active during Burn state and (for UBA2015A

and UBA2016A) if the voltage at pin DIM is above the overvoltage end-of-life enable

voltage V_{en(oveol)(DIM)}

.

7.6.3 Capacitive mode detection

Under all normal operating conditions the half-bridge switching frequency should be

higher than the load resonance frequency. The load then shows an inductive behavior in

that the load current I_loadlags behind the half-bridge voltage V_SHHB. If the amplitude and

the phase difference are large enough, the load current will charge any capacitance on pin

SHHB during the non-overlap time t_no(LH), and discharge it during the other non-overlap

time t_no(HL). As a result the voltage across the switches is almost zero at the moment they

turn on. This is called zero voltage switching; see Figure 14 “Switching”. Zero voltage

switching provides the highest switching efficiency and the least Electromagnetic

Emission (EME).

Capacitive mode switching can occur when, due to any abnormal condition, the switching

frequency is below the load resonance frequency. This can happen when the lamp is

removed. The load current will then keep the backgate diode of the switch that is switched

off conducting during the non-overlap time, and if the other switch is turned on, a sudden

step of the half-bridge voltage to the other supply rail takes place (which causes huge

current spikes). Also cross conduction between the switches can occur during the reverse

recovery of the backgate diode. These effects put huge stress on the power switches,

most of which can only handle capacitive mode switching a few times before they break

down.

To protect against capacitive mode switching the IC monitors pin SHHB during the

non-overlap time t_no(LH)between switching off of the low-side switch and switching on of

the high-side switch. If a rise of V_SHHB(dV_SHHB/dt > V_th(cm)(SHHB)) during t_no(LH)is not

detected then the IC will conclude that capacitive mode switching is occurring during the

next full cycle. If capacitive mode is detected longer than the fault activation delay time

t_det(fault)then the IC will enter Stop state.

Capacitive mode detection is active in all oscillating states for all ICs except in the Ignition

state of the UBA2016A if zero voltage switching has been observed. In that case the

UBA2016A switches to hard switching regulation, see Section 7.6.4 “Hard switching

regulation (UBA2016A)”.

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During ignition a situation may occur where the amplitude of the load current is high and

the half-bridge is at the boundary of capacitive mode switching; see Figure 14 “Switching”.

The load current crosses zero during the non-overlap time. If the amplitude of the load

current is large enough, the UBA2015 and UBA2015A might not detect capacitive mode

because V_SHHBdid rise before going down again. The backgate diode of one switch is

conducting again when the other switch switches on. Since this can only happen if the

load current crosses zero during the non-overlap time, the momentary value of the load

current at the end of the non-overlap time will be not so big, and will not necessarily

damage the switches.

Depending on the topology used, the DC blocking capacitor might be charged via the

lamp(s) at the moment the lamp(s) ignite. This will cause a temporary DC current addition

to the load current that might be interpreted by the UBA2015 and UBA2015A as

capacitive mode switching. If this happens the DC blocking capacitor must be reduced or

pre-charged. The UBA2016A does not have this problem.

7.6.4 Hard switching regulation (UBA2016A)

In Ignition state the UBA2016A capacitive mode detection is disabled and replaced by

hard switching regulation. This enables ignition without voltage feedback.

The hard switching regulation measures the voltage step on pin SHHB at the end of the

non-overlap time t_no(LH)(V_step(SHHB)in Figure 14 “Switching”) and increases the switching

frequency by discharging pin CIFB with a current according to the formula:

I_{dch(hswr)CIFB}= (V_step(SHHB)− V_th(hswr)SHHB) × g_m(hswr)

In this way the IC keeps the switching frequency during ignition at the point where there is

still a small phase difference between the load current and the half-bridge voltage, and the

switching losses due to hard switching are limited. This is assuming that it is not already

held at the higher frequency by the overvoltage protection or coil saturation protection.

As Figure 14 “Switching” shows, hard switching also occurs when the amplitude of the

load current is to small. This might happen when the IC enters Ignition state at the end of

preheat and the frequency is still relatively high. To prevent the IC from getting stuck at

f_highthe hard switching regulation is disabled until zero voltage switching has been

observed, that is if V_step(SHHB)< V_th(zvs)SHHB

.

7.6.5 Hard switching protection

The hard switching level V_step(SHHB)step is measured via pin SHHB. The hard switching

level is determined by measuring the voltage step on pin SHHB on the rising edge of pin

GHHB; see Figure 14 “Switching”. When V_step(SHHB)is above the hard switching

protection threshold voltage on pin SHHB (V_th(hswp)SHHB) the fault timer is activated.

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7.6.6 Coil saturation protection

When the peak voltage on pin SLHB exceeds saturation threshold voltage V_th(sat)SLHB, an

additional current I_add(CF)is sourced to pin CF to shorten the running oscillator cycle. In

Ignition state the fault timer is started and a discharge current I_dch(CIFB)is drawn from pin

CIFB during the next cycle to increase the switching frequency.

In Burn state the IC will go to Stop state if coil saturation is detected longer than the

saturation detection delay time t_d(det)sat

.

Current I_bias(SLHB)is sourced to pin SLHB which will force the controller into coil saturation

protection if pin SLHB is left open.

7.6.7 Lamp overcurrent protection

If voltage on pin IFB exceeds the overcurrent detection threshold voltage V_th(ocd)(IFB), and

the oscillator is running at f_sw(high), an overcurrent is detected and the IC will immediately

enter the Stop state.

7.6.8 Lamp overvoltage protection

When the peak voltage on pin VFB exceeds V_th(ov)(VFB), the fault timer is started and a

discharge current I_dch(CIFB)is drawn from pin CIFB during the next cycle to increase the

switching frequency.

When V_VFB> V_{th(ovextra)(VFB)}for longer than the fault activation delay time t_det(fault)then the

IC will enter the Stop state.

7.6.9 Lamp removal detection

Removing the lamp from applications that have the resonant capacitor connected via the

lamp filaments, will result in hard switching because current cannot flow through the

ballast inductor.

If hard switching is detected during Ignition or Burn state the fault timer will be started.

For applications with the resonant capacitor connected directly to the ballast inductor,

capacitive mode, coil saturation or over voltage will be detected. Capacitive mode is

activated if the switching frequency ends up below the resonance frequency due to

removal of the lamp. If the switching frequency is near or above the resonance frequency,

the lamp (or rather the lamp socket) voltage and half-bridge current will be very high due

to the unloaded resonant circuit (lamp inductor and lamp capacitor) which activates the

coil saturation protection or the overvoltage protection.

7.6.10 Temperature protection

When the temperature is above T_th(act)otpand GLHB is high, the IC enters Standby state.

The IC cannot exit the Standby state until the temperature drops below T_th(rel)otp

.

7.6.11 Fault timer

Any fault that starts the fault timer must be detected for longer than the fault activation

delay time t_d(act)faultto actually start the timer. When the timer is started, the capacitor at

pin CPT is alternately being charged and discharged. After 8 charging and 7 discharging

cycles the fault time-out period t_to(fault)is reached and the IC enters either the Stop state or

the Auto-restart state, depending on the fault detected, the current state of the timer and

the number of ignition attempts; see Figure 9 “State diagram”. If the fault that started the

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timer is no longer detected for a period longer than the fault release delay time t_d(rel)fault

,

the fault timer will be reset and at any new occurance of the fault, the timer will start from

zero.

Faults which activate the fault timer are shown as SlowFault in Figure 9 “State diagram”.

The fault timer uses the same pin (CPT) to set the time with an external capacitor C_ext(CPT)

as the preheat timer. The ratio between the preheat time-out time t_to(ph)and the fault

time-out time t_to(fault)can be changed by adding an external series resistor R_s(ext)(CPT)or

an external parallel resistor R_p(ext)(CPT)to the external capacitor C_ext(CPT); see Figure 15

“CPT connections”.

CPT

R

s(ext)(CPT)

C

R

C

ext(CPT)

p(ext)(CPT)

C

ext(CPT)

smaller ratio

/t

default ratio

/t

larger ratio

t /t

t

to(ph) to(fault)

001aan210

Fig 15. CPT connections

The fault timer incorporates a protection that ensures safe operation conditions if the CPT

pin voltage is below V_th(scp)(CPT)(shorted to GND) by holding the oscillation frequency at

f_sw(high)

.

7.6.12 Brownout protection

Brownout protection is designed to maintain stable and safe lamp operation during dips in

mains supply. Without this protection the current demand from the bus voltage to maintain

constant lamp power would increase upon a drop in bus voltage. This creates an unstable

situation with the mains input voltage dropping and the PFC reaching its regulation range

limit.

Brownout protection reduces the lamp power when the PFC is out of regulation. This

situation is only allowed for a limited time to prevent excessive component stress.

When the PFC is outside its regulation range and the bus voltage is still too low

(V_COMPPFC= V_{clamp(COMPPFC)}and V_FBPFC< V_reg(FBPFC)), a brownout current I_bo(CF)is

added to the charge current at pin CF, thus increasing the f_sw(low). A discharge brownout

current I_{dch(bo)(CIFB)}is also drawn from pin CIFB. Both I_bo(CF)and I_{dch(bo)(CIFB)}are

proportional to the difference between V_FBPFCand V_reg(FBPFC). If V_FBPFC< V_{th(bo)(FBPFC)}

the fault timer will start.

The start-up bleeder resistor and the regulation range of the PFC should be dimensioned

in such a way that if the fault timer times out on brownout protection and the IC enters

Stop state, the input mains voltage is too low to support the standby current of the IC via

the bleeder resistor. The IC will then automatically reset and start-up in normal mode (and

reignite the lamps) when the mains voltage has returned to normal.

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8. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages referenced to signal ground (GND

pin 15); current flow into the IC is positive.

Symbol

General

R_ref(IREF)

Parameter

Conditions

Min

Max

Unit

reference resistance on

pin IREF

30

36

+4

kΩ

SR

slew rate

pins FSHB, GHHB and SHHB

−4

V/ns

T_amb

T_j

ambient temperature

junction temperature

storage temperature

−40

−55

+125 °C

+150 °C

T_stg

Voltage

V_FSHB

voltage on pin FSHB

continuous

0

570

630

+14

+9

V

t < 0.5 s

0

with respect to V_SHHB

−0.3

−9

V_GHHB

V_GLHB

V_GPFC

V_VDD

voltage on pin GHHB

voltage on pin GLHB

voltage on pin GPFC

voltage on pin VDD

voltage on pin AUXPFC

voltage on pin EOL

voltage on pin SLHB

voltage on pin IFB

V_AUXPFC

V_EOL

−9

+9

V_SLHB

V_IFB

−9

+9

−5

+5

V_DIM

voltage on pin DIM

voltage on pin FBPFC

voltage on pin BOOST

voltage on pin PH/EN

voltage on pin VFB

−0.1

−0.3

−0.1

+5

V_FBPFC

V_BOOST

V_PH/EN

V_VFB

+5

+2.2

+5

Current

I_VDD

current on pin VDD

current on pin EOL

-

50

mA

μA

I_EOL

−1

−50

−1

+1

+50

+1

I_SLHB

current on pin SLHB

current on pin BOOST

current on pin AUXPFC

I_BOOST

I_AUXPFC

mA

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Table 4.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages referenced to signal ground (GND

pin 15); current flow into the IC is positive.

Symbol

Parameter

Conditions

Min

Max

Unit

ElectroStatic Discharge (ESD)

V_ESD

electrostatic discharge

voltage

Human Body Model (HBM)

JEDEC Class 2 for pins: SLHB, IFB, EOL, CIFB,

CPT, IREF, VFB, CF, DIM, BOOST, PH/EN, FBPFC,

COMPPFC, AUXPFC, GPFC, VDD and GLHB

−2

−1

+2

+1

kV

JEDEC Class 1C for pins: GHHB, FSHB and SHHB

Charge Device Model (CDM)

JEDEC Class 2 for pins: SHHB, FSHB, GHHB

−200 +200

−500 +500

V

JEDEC Class 3 for pins: SLHB, IFB, EOL, VFB,

IREF, CIFB, CF, CPT, DIM, BOOST, PH/EN, FBPFC,

COMPPFC, AUXPFC, GPFC, VDD, GLHB

Latch-up

[1]

I_lu

latch-up current

−100 +100 mA

[1] Positive and negative latch-up currents tested at T_j= 150 °C by discharging a 22 μF capacitor though a 50 Ω series resistor with a

350 μH series inductor. Latch-up current values are in accordance with the general quality specification.

9. Thermal characteristics

Table 5.

Symbol

R_th(j-a)

Thermal characteristics

Parameter

Conditions

Typ

Unit

thermal resistance from junction to

ambient

in free air; mounted on a single-sided PCB;

SO20 package

100

K/W

in free air; mounted on a single-sided PCB;

DIP20 package

90

K/W

10. Characteristics

Table 6.

Characteristics

T_amb= 25 °C; settings according to default setting^[1]; all voltages referenced to GND; current flow into the IC is positive;

unless otherwise specified.

Symbol

High voltage

I_leak

Parameter

Conditions

Min

Typ

Max Unit

leakage current

V_FSHB= 630 V;

-

2

μA

V_GHHB= 630 V;

V_SHHB= 630 V; V_VDD= 0 V

Start-up

V_startup(VDD)

V_stop(VDD)

V_hys(VDD)

I_stb(VDD)

start-up voltage on pin VDD

stop voltage on pin VDD

11.9 12.4 12.9

V

9.6

2.1

10.0 10.4

2.4 2.7

hysteresis voltage on pin VDD

standby current on pin VDD

standby pull-up current on pin PH/EN

V_VDD= 11.5 V

0.20 0.24 0.28 mA

I_{pu(stb)(PH/EN)}

Standby or Stop state;

V_PH/EN= 0.25 V

7.7

9

10.3 μA

V_rst(VDD)

reset voltage on pin VDD

3.6

4.2

4.8

V

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UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

Table 6.

Characteristics …continued

T_amb= 25 °C; settings according to default setting^[1]; all voltages referenced to GND; current flow into the IC is positive;

unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

6.8

V_restart(VDD)

I_restart(VDD)

V_clamp(VDD)

I_clamp(VDD)

I_VDD

restart voltage on pin VDD

restart current on pin VDD

clamp voltage on pin VDD

clamp current on pin VDD

current on pin VDD

6.2

6.5

V

V_VDD= 9 V

0.85 1.10 1.35 mA

IC off; I_VDD= 0.33 mA

IC off; V_VDD= 14.0 V

V_FBPFC= 1.2 V;

13.0 13.4 13.8

V

25

45

-

mA

1.2

1.7

2.2

V_COMPPFC= 1 V

PFC normal operation

t_on(PFC)

PFC on-time

V_COMPPFC= 350 mV

0.70 1.05 1.40 μs

t_on(PFC)high

t_off(PFC)low

t_leb(FBPFC)

high PFC on-time

low PFC off-time

V_COMPPFC= V_{high(COMPPFC)}

24

28

32

μs

ns

1.7

260

2.0

330

2.3

400

leading edge blanking time on pin

FBPFC

from the start of rising edge on

pin GPFC

V_reg(FBPFC)

regulation voltage on pin FBPFC

V_COMPPFC= 1.6 V

V_COMPPFC= 200 mV

V_FBPFC= 1.27 V

1.23 1.27 1.31

1.23 1.28 1.33

V

I_bias(FBPFC)

g_m(PFC)

bias current on pin FBPFC

PFC transconductance

4.5

25

5.0

30

5.5

35

μA

μA/V

V_COMPPFC= 1.5 V;

1.2 V < V_FBPFC< 1.34 V

V_{th(VPFCok)FBPFC}PFC voltage OK threshold voltage on

pin FBPFC

0.95 1.00 1.05

V

V_det(demag)

demagnetization detection voltage

on pin AUXPFC

V_FBPFC= 1 V

50

100

150

mV

V

V_{clamp(COMPPFC)}clamp voltage on pin COMPPFC

2.85 3.00 3.15

PFC protection

t_{on(PFC)nodemag}

V_{th(osp)(FBPFC)}

V_{th(ov)(FBPFC)}

no demagnetization detected PFC

on-time

1.0

1.3

1.6

μs

V

open/short protection threshold voltage

on pin FBPFC

0.20 0.25 0.30

1.34 1.39 1.43

overvoltage threshold voltage on pin

FBPFC

V

I_bias(AUXPFC)

PFC driver

I_source(GPFC)

R_sink(GPFC)

HB preheat

R_ext(PH/EN)

t_to(ph)

bias current on pin AUXPFC

V_AUXPFC= 0.1 V

−6

−5

−4

μA

source current on pin GPFC

sink resistance on pin GPFC

V_GPFC= 4 V; V_VDD= 12 V

V_GPFC= 2 V; V_VDD= 12 V

−105 −90

−75

mA

13.5 16.0 18.5

Ω

external resistor on pin PH/EN

preheat time-out time

38.6

-

kΩ

s

C_CPT= 100 nF

0.80 0.94 1.08

1.78 1.84 1.90

0.44 0.48 0.52

V_O(ph)(PH/EN)

V_ctrl(ph)SLHB

preheat output voltage on pin PH/EN

Preheat or Ignition state

V

overcurrent protection threshold voltage preheat

on pin SLHB

V

I_ch(CIFB)

charge current on pin CIFB

no fault detected;

−10.3 −9.0 −7.7 μA

Preheat and Ignition states

only; V_CIFB= 1.5 V

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UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

Table 6.

Characteristics …continued

T_amb= 25 °C; settings according to default setting^[1]; all voltages referenced to GND; current flow into the IC is positive;

unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

I_dch(CIFB)

discharge current on pin CIFB

preheat overcurrent detected;

7.7

9.0

10.3 μA

V_CIFB= 1.5 V

f_sw(ph)

preheat switching frequency

UBA2015; UBA2015A

R_ext(PH/EN)= 40 kΩ;

C_ext(CF)= 200 pF

93

62

97.7 102.4 kHz

R_ext(PH/EN)= 100 kΩ;

66

70

kHz

C_ext(CF)= 200 pF

HB lamp ignition

f_sw(high)/f_sw(low)

high switching frequency to low

switching frequency ratio

2.2

-

2.4

3.0

2.6

-

V_{fsw(low)(CIFB)}

V_th(lod)(IFB)

V_th(lod)(VFB)

V_{(Vreg−Vth(lod))}

t_d(lod)

low switching frequency voltage on pin

CIFB

V

lamp on detection threshold voltage on

pin IFB

1.00 1.11

1.22

1.1

220

4

V

lamp on detection threshold voltage on

pin VFB

0.9

40

2

1.0

160

3

V

regulation voltage to lamp-on-detect

threshold voltage difference

pin IFB

mV

ms

lamp on detection delay time

HB normal operation

f_sw(low)

low switching frequency

C_CF= 200 pF

41

20

-

43

-

45

80

-

kHz

V

V_high(CF)

V_reg(IFB)

high voltage on pin CF

2.5

regulation voltage on pin IFB

V_CIFB= 2 V; V_IFB> 0 V

1.22 1.27 1.32

77 127 177

V

V_CIFB= 2 V; V_DIM= 127 mV;

V_IFB> 0 V

mV

V_CIFB= 2 V; V_IFB< 0 V

−1.34 −1.27 −1.2

−197 −127 −57

V

V_CIFB= 2 V; V_DIM= 127 mV;

V_IFB< 0 V

mV

I_ch(low)(CF)

V_i(IFB)

low charge current on pin CF

input voltage range on pin IFB

input resistance on pin IFB

-

47

-

μA

V

V_CIFB= 2 V

V_IFB= 1 V

V_IFB= −1 V

−3.1

+3.1

R_i(IFB)

-

60

30

-

kΩ

V

V_en(PH/EN)

enable voltage on pin PH/EN

0.21 0.25 0.29

1.21 1.27 1.33

V_{O(burn)(PH/EN)}

g_m(IFB)

burn state output voltage on pin PH/EN Burn state

V

IFB transconductance

V_CIFB= 2 V

14

-

16.5 19

μA/V

I_{O(clamp)(PH/EN)}

output current clamp on pin PH/EN

Preheat, Ignition or Burn

states; V_PH/EN= 0.2 V

-

0.16 mA

HB driver

I_source(GLHB)

R_sink(GLHB)

I_source(GHHB)

source current on pin GLHB

sink resistance on pin GLHB

source current on pin GHHB

V_GLHB= 4 V

−105 −90

13.5 16

−105 −90

−75

18.5

−75

mA

Ω

V_GLHB= 2 V

V_SHHB= 0 V; V_GHHB= 4 V

mA

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NXP Semiconductors

600 V fluorescent lamp driver

Table 6.

Characteristics …continued

T_amb= 25 °C; settings according to default setting^[1]; all voltages referenced to GND; current flow into the IC is positive;

unless otherwise specified.

Symbol

R_sink(GHHB)

t_no

Parameter

Conditions

Min

13.5 16

1.25 1.50 1.75 μs

Typ

Max Unit

sink resistance on pin GHHB

non-overlap time

V_SHHB= 0 V; V_GHHB= 2 V

18.5

Ω

V_Fd(bs)

bootstrap diode forward voltage

I_FS= 5 mA

1.0

1.5

2.0

V

Dimming

I_bias(DIM)

R_i(DIM)

bias current on pin DIM

V_DIM= 1 V

−28

−26

−24

μA

kΩ

input resistance on pin DIM

V_DIM= 2.5 V

-

30

-

HB protection

V_{th(sat)(SLHB)}

saturation threshold voltage on pin

SLHB

2.35 2.50 2.65

V

t_d(det)sat

saturation detection delay time

leading edge blanking time on pin SLHB

additional current on pin CF

Burn state

-

0.3

-

μs

ns

μA

V

t_leb(SLHB)

I_add(CF)

I_bias(SLHB)

V_th(ocd)(IFB)

260

340

420

−85

V_SLHB> V_th(sat)SLHB; V_CF= 2 V

V_SLHB= 2.5 V

−107 −96

bias current on pin SLHB

−10

−8.5 −7

overcurrent detection threshold voltage

on pin IFB

2.8

3.0

3.2

120

2.6

V_th(osp)(VFB)

V_th(ov)(VFB)

t_det(fault)

open/short protection threshold voltage

on pin VFB

40

80

mV

V

overvoltage threshold voltage on pin

VFB

2.4

2.5

fault detection time

-

125

50

-

μs

overvoltage extra or capacitive

mode during burn state

t_rel(fault)

fault release time

-

1

-

ms

V

V_{th(ovextra)(VFB)}

overvoltage extra threshold voltage on

pin VFB

3.2

3.35 3.5

I_bias(VFB)

bias current on pin VFB

2.3

2.6 2.9

μA

V

V_th(low)EOL

V_th(high)EOL

I_bias(EOL)

low threshold voltage on pin EOL

high threshold voltage on pin EOL

bias current on pin EOL

V_FBPFC= 1.27 V

V_EOL= 1.9 V

1.21 1.27 1.33

2.39 2.54 2.69

V

15.2 16.0 16.8 μA

V_{th(oveol)(VFB)}

overvoltage end-of-life threshold voltage pin DIM open

on pin VFB

0.8

0.88 0.96

V

UBA2015A; UBA2016A

V_DIM= 1.0 V

0.92 1.0

1.08

V

UBA2015A; UBA2016A

V_DIM= 0.5 V

1.15 1.23 1.31

0.21 0.25 0.29

V

V_{en(oveol)(DIM)}

V_th(hswp)SHHB

V_th(zvs)SHHB

V_th(hswr)SHHB

overvoltage end-of-life enable voltage

on pin DIM

UBA2015A; UBA2016A

hard switching protection threshold

voltage on pin SHHB

f_sw= 50 kHz

-

100

30

-

V

zero voltage switching detection

threshold voltage on pin SHHB

hard switching regulation threshold

voltage on pin SHHB

100

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NXP Semiconductors

600 V fluorescent lamp driver

Table 6.

Characteristics …continued

T_amb= 25 °C; settings according to default setting^[1]; all voltages referenced to GND; current flow into the IC is positive;

unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

V_th(cm)SHHB

capacitive mode detection threshold

voltage on pin SHHB

t_no(LH)

-

30

-

V/μs

g_m(hswr)

hard switching regulation

transconductance

UBA2016A; Ignition state

hard switching step on pin

SHHB above V_{th(hswr)(SHHB)}

per extra volt step at

-

18

-

μA/V

f

_sw= 50 kHz

V_th(scp)(CPT)

short-circuit protection threshold voltage

on pin CPT

80

120

160

mV

R_{par(ext)(CPT)}

R_s(ext)(CPT)

t_to(fault)

external parallel resistance on pin CPT

external series resistance on pin CPT

fault time-out time

700

-

kΩ

s

40

C_CPT= 100 nF

0.16 0.19 0.22

t_to(ph)/t_to(fault)

ratio between preheat time-out time and R_par(ext)= 700 kΩ;

3

3.4

5.2

11.5

17

3.8

5.7

14

22

50

22

fault time-out time

R_s(ext)not connected (short)

R_par(ext)not connected (open);

R_s(ext)not connected (short)

4.7

9

R_par(ext)not connected (open);

R_s(ext)= 40 kΩ

I_bo(CF)

brownout current on pin CF

V_COMPPFC= V_{high(COMPPFC)}

;

12

10

14

μA

mV

μA

V_FBPFC= 1.0 V; V_CF= 1.5 V

[2]

V_{(Vreg-Vth(bo))}

I_dch(bo)CIFB

regulation voltage to brownout threshold V_COMPPFC= V_{high(COMPPFC)}

voltage difference on pin FBPFC

30

brownout discharge current on pin CIFB V_COMPPFC= V_{high(COMPPFC)}

;

18

V_FBPFC= 1.0 V; V_CIFB= 2.0 V

Boost

f_sw(bst)(low)

low boost switching frequency

I

≥ I_sat(

;

21

24

27

kHz

)

BOOST

C_ext(CF)= 200 pF

N_f(bst)low

V_{reg(bst)(IFB)}

N_Vreg(bst)

I_sat(

low boost frequency constant

boost regulation voltage on pin IFB

boost regulation voltage constant

saturation current on pin BOOST

voltage on pin BOOST

0.14 0.165 0.19 1/μA

1.75 1.84 1.93

0.180 0.21 0.24 V/μA

I

≥ I_sat(

V

BOOST

2.3

2.7

1

3.1

-

μA

V

)

BOOST

V_BOOST

I

= 1 μA

= 5 μA

= 50 μA

-

BOOST

1.4

-

V

2.2

V

Temperature protection

T_th(act)otpovertemperature protection activation

120

65

140

80

160

95

°C

threshold temperature

T_th(rel)otp

overtemperature protection release

threshold temperature

[1] Default setting; see Table 7.

[2] The threshold for the brownout protection is slightly below the normal regulation level on pin FBPFC. The design guarantees that it will

always be below this level because the clamp current from the PFC OTA is used as a signal.

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UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

Table 7.

Default settings for characteristics

Pin name

SLHB

IFB

1

Application

connected to ground

2

connected to ground

EOL

3

connected to a 2 V test supply

connected via a 33 kΩ resistor to ground

connected via a 100 nF capacitor to ground

connected via a 200 pF C0G (NP0) capacitor to ground

connected via a 100 nF capacitor to ground

connected via a 100 pF capacitor to ground

connected to ground; UBA2016A

not connected; UBA2015 and UBA2015A

connected to a 1.27 V test supply

connected via a 100 nF capacitor to ground

connected to ground

VFB

4

IREF

5

CIFB

6

CF

7

CPT

8

DIM

9

BOOST

PH/EN

FBPFC

COMPPFC

AUXPFC

GPFC

GND

10

11

12

13

14

15

16

17

18

19

20

not connected (open)

connected to ground

VDD

connected to a 13 V test supply

not connected (open)

GLHB

SHHB

FSHB

GHHB

connected to ground

connected to a 13 V test supply

not connected (open)

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NXP Semiconductors

600 V fluorescent lamp driver

11. Application information

11.1 Connecting the IC in an application

A 33 kΩ resistor must be connected between pin IREF and GND. The tolerance of this

resistor adds to any current related tolerances of the IC, including f_sw(low). No other

components can be connected to pin IREF.

Tolerance and temperature dependency of the capacitor connected between pin CF and

GND will add to the tolerance on f_sw(low)

.

Small decoupling capacitors (about 100 pF) are recommended on pins FBPFC and IFB

close to the IC.

Normal sized decoupling capacitors (about 10 nF) are recommended on pins DIM and

EOL.

The capacitors at pins CF, COMPPFC, CPT, FSHB and VDD should also be placed close

to the IC.

A capacitor between pin CIFB and GND of at least 470 pF is needed for stability of the low

switching frequency.

A capacitor between pin VDD and GND of at least 10 nF is needed for stability of the

internal VDD voltage clamp. However, for reliable operation of the IC a low ESR type of at

least 470 nF is recommended.

A capacitor between pin FSHB and SHHB is needed to supply the high-side driver. The

recommended value for this capacitor is ¹⁄₅of the value of the capacitor at VDD.

A series resistor of at least 1 kΩ is recommended on pins AUXPFC and SLHB.

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NXP Semiconductors

600 V fluorescent lamp driver

12. Package outline

DIP20: plastic dual in-line package; 20 leads (300 mil)

SOT146-1

D

M

E

A

2

A

1

L

c

e

w M

Z

b

1

(e )

1

b

M

H

20

11

pin 1 index

E

1

10

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

A

(1)

Z

1

2

UNIT

mm

b

c

D

E

e

1

L

M

H

w

1

E

max.

min.

max.

1.73

1.30

0.53

0.38

0.36

0.23

26.92

26.54

6.40

6.22

3.60

3.05

8.25

7.80

10.0

8.3

4.2

0.51

3.2

2.54

0.1

7.62

0.3

0.254

0.01

2

0.068

0.051

0.021

0.015

0.014

0.009

1.060

1.045

0.25

0.24

0.14

0.12

0.32

0.31

0.39

0.33

inches

0.17

0.02

0.13

0.078

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-13

SOT146-1

MS-001

SC-603

Fig 21. Package outline SOT146-1 (DIP20)

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NXP Semiconductors

600 V fluorescent lamp driver

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

D

E

A

X

c

y

H

E

v

M

A

Z

20

11

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

13.0

12.6

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25

0.01

0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.51

0.014 0.009 0.49

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT163-1

075E04

MS-013

Fig 22. Package outline SOT163-1 (SO20)

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NXP Semiconductors

600 V fluorescent lamp driver

13. Revision history

Table 8.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

UBA2016A_15_15A v.1

20110520

Objective data sheet

-

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600 V fluorescent lamp driver

14. Legal information

14.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

14.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

14.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

UBA2016A_15_15A

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 20 May 2011

40 of 42

UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

UBA2016A_15_15A

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 20 May 2011

41 of 42

UBA2016A/15/15A

NXP Semiconductors

600 V fluorescent lamp driver

16. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

11

Application information . . . . . . . . . . . . . . . . . 31

Connecting the IC in an application . . . . . . . . 31

Without lamp current regulation or dimming . 32

With lamp current regulation and dimming . . 36

11.1

11.2

11.3

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

12

13

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 37

Revision history . . . . . . . . . . . . . . . . . . . . . . . 39

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

14

Legal information . . . . . . . . . . . . . . . . . . . . . . 40

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 40

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 41

14.1

14.2

14.3

14.4

7

7.1

7.2

Functional description . . . . . . . . . . . . . . . . . . . 6

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Power Factor Correction (PFC) . . . . . . . . . . . . 6

Regulation loop. . . . . . . . . . . . . . . . . . . . . . . . . 7

Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Half-bridge driver . . . . . . . . . . . . . . . . . . . . . . . 8

VDD supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Low- and high-side drivers . . . . . . . . . . . . . . . . 9

Non-overlap . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Fluorescent lamp control . . . . . . . . . . . . . . . . 10

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Oscillating states (Preheat, Ignition and Burn) 12

Preheat. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Ignition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Auto-restart. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Burn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Lamp current control and dimming. . . . . . . . . 15

Operation without lamp current control. . . . . . 17

Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Stop state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Enable and Disable . . . . . . . . . . . . . . . . . . . . 18

Protection circuits . . . . . . . . . . . . . . . . . . . . . . 18

End-of-life rectifying lamp detection . . . . . . . . 18

End-of-life overvoltage detection . . . . . . . . . . 19

Capacitive mode detection . . . . . . . . . . . . . . . 19

Hard switching regulation (UBA2016A) . . . . . 20

Hard switching protection . . . . . . . . . . . . . . . . 20

Coil saturation protection . . . . . . . . . . . . . . . . 22

Lamp overcurrent protection. . . . . . . . . . . . . . 22

Lamp overvoltage protection . . . . . . . . . . . . . 22

Lamp removal detection . . . . . . . . . . . . . . . . . 22

Temperature protection. . . . . . . . . . . . . . . . . . 22

Fault timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Brownout protection . . . . . . . . . . . . . . . . . . . . 23

15

16

Contact information . . . . . . . . . . . . . . . . . . . . 41

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.2.1

7.2.2

7.3

7.3.1

7.3.2

7.3.3

7.4

7.4.1

7.4.2

7.4.3

7.4.4

7.4.5

7.4.6

7.4.7

7.4.7.1

7.4.7.2

7.4.7.3

7.4.8

7.5

7.6

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

7.6.6

7.6.7

7.6.8

7.6.9

7.6.10

7.6.11

7.6.12

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 24

Thermal characteristics . . . . . . . . . . . . . . . . . 25

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 25

9

10

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 20 May 2011

Document identifier: UBA2016A_15_15A


型号：	BA2016AP/1,112
厂家：	NXP
描述：	BA2016AP/1,112
文件：	总42页 (文件大小：363K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BA2016AP/1,112 [NXP]

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