BF1109,215 [NXP]
TRANSISTOR UHF BAND, Si, N-CHANNEL, RF SMALL SIGNAL, MOSFET, ROHS COMPLIANT, PLASTIC, SOT-4, 4 PIN, FET RF Small Signal;
| 型号： | BF1109,215 |
| 厂家： | 
NXP |
| 描述： | TRANSISTOR UHF BAND, Si, N-CHANNEL, RF SMALL SIGNAL, MOSFET, ROHS COMPLIANT, PLASTIC, SOT-4, 4 PIN, FET RF Small Signal 放大器 光电二极管 晶体管 |
| 文件： | 总15页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
BF1109; BF1109R; BF1109WR
N-channel dual-gate MOS-FETs
Product specification
1997 Dec 08
Supersedes data of 1997 Sep 03
NXP Semiconductors
Product specification
BF1109; BF1109R;
BF1109WR
N-channel dual-gate MOS-FETs
FEATURES
PINNING
Short channel transistor with high
forward transfer admittance to input
capacitance ratio
PIN
1
DESCRIPTION
source
3
4
2
drain
Low noise gain controlled amplifier
up to 1 GHz
3
gate 2
gate 1
2
1
4
Internal self-biasing circuit to
ensure good cross-modulation
performance during AGC and good
DC stabilization.
Top view
MSB035
BF1109R marking code: NBp.
Fig.2 Simplified outline
(SOT143R).
APPLICATIONS
VHF and UHF applications with 9 V
supply voltage, such as television
tuners and professional
communications equipment.
4
3
3
4
k, halfpage
DESCRIPTION
Enhancement type N-channel
field-effect transistor with source and
substrate interconnected. Integrated
diodes between gates and source
protect against excessive input
voltage surges. The BF1109,
BF1109R and BF1109WR are
encapsulated in the SOT143B,
SOT143R and SOT343R plastic
packages respectively.
1
2
2
1
Top view
MSB014
Top view
MSB842
BF1109 marking code: NFp.
BF1109WR marking code: NB.
Fig.1 Simplified outline
(SOT143B).
Fig.3 Simplified outline
(SOT343R).
QUICK REFERENCE DATA
SYMBOL
PARAMETER
drain-source voltage
CONDITIONS
MIN.
TYP. MAX. UNIT
VDS
ID
11
V
drain current (DC)
30
200
mA
mW
mS
pF
Ptot
yfs
Cig1-ss
Crss
F
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
Tamb 80 C
30
2.2
25
1.5
2.7
40
2.5
f = 1 MHz
fF
f = 800 MHz
dB
Xmod
Tj
cross-modulation
input level for k = 1% at 40 dB AGC 100
dBV
C
operating junction temperature
150
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling.
1997 Dec 08
2
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
drain-source voltage
CONDITIONS
MIN.
MAX.
11
UNIT
VDS
ID
V
drain current (DC)
gate 1 current
30
mA
mA
mA
mW
C
IG1
IG2
Ptot
Tstg
Tj
10
10
200
+150
+150
gate 2 current
total power dissipation
storage temperature
operating junction temperature
Tamb 80 C; note 1
65
C
Note
1. Device mounted on a printed-circuit board.
MGM243
250
handbook, halfpage
P
tot
(mW)
200
150
100
50
0
0
40
80
120
160
(°C)
T
amb
Fig.4 Power derating curve.
1997 Dec 08
3
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
CONDITIONS
VALUE
350
UNIT
K/W
K/W
thermal resistance from junction to ambient in free air note 1
thermal resistance from junction to soldering point
Rth j-s
200
Note
1. Device mounted on a printed-circuit board.
STATIC CHARACTERISTICS
Tj = 25 C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
V(BR)DSS
drain-source breakdown voltage
VG1-S = VG2-S = 0; ID = 10 A
VG2-S = 0; IG1-S = 10 A; ID = 0
VG1-S = VDS = 0; IG2-S = 10 A
VG1-S = 9 V; VDS = 9 V; ID = 20 A
VG2-S = 4 V; VDS = 9 V
11
11
11
0.3
8
V
V(BR)G1-SS gate 1-source breakdown voltage
V(BR)G2-SS gate 2-source breakdown voltage
V
V
VG2-S (th)
IDSX
IG1-SS
IG2-SS
gate 2-source threshold voltage
self-biasing drain current
gate 1 cut-off current
1.2
16
20
20
V
mA
nA
nA
VG1-S = 9 V; VG2-S = 0; ID = 0
VG1-S = VDS = 0; VG2-S = 9 V
gate 2 cut-off current
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 9 V; self-biasing current; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
24
TYP. MAX. UNIT
yfs
Cig1-ss
Cig2-ss
Coss
Crss
F
forward transfer admittance pulsed; Tj = 25 C
30
mS
pF
pF
pF
fF
input capacitance at gate 1
input capacitance at gate 2
output capacitance
f = 1 MHz
f = 1 MHz
f = 1 MHz
2.2
1.5
1.3
25
2.7
reverse transfer capacitance f = 1 MHz
40
2.5
noise figure
power gain
f = 800 MHz; YS = YS opt
1.5
38
dB
dB
Gp
GS = 2 mS; BS = BS opt; GL = 0.5 mS;
BL = BL opt; f = 200 MHz; see Fig.16
GS = 3.3 mS; BS = BS opt; GL = 1 mS;
BL = BL opt; f = 800 MHz; see Fig.17
20
dB
Xmod
cross-modulation
input level for k = 1% at 0 dB AGC;
fw = 50 MHz; funw = 60 MHz; see Fig.18
85
100
dBV
dBV
input level for k = 1% at 40 dB AGC;
fw = 50 MHz; funw = 60 MHz; see Fig.18
1997 Dec 08
4
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
MDA614
MDA613
40
25
handbook, halfpage
handbook, halfpage
I
D
I
D
(mA)
(mA)
20
V
= 1.6 V
G1
30
3.5 V
3 V
V
= 4 V
G2-S
1.5 V
1.4 V
15
10
20
10
2.5 V
2 V
1.3 V
1.2 V
1.1 V
1 V
5
0
1.5 V
1 V
0
0
0.5
1
1.5
2
2.5
(V)
0
2
4
6
8
10
(V)
V
DS
V
G1
VG2-S = 4 V.
VDS = 9 V.
Tj = 25 C.
Tj = 25 C.
Fig.5 Output characteristics; typical values.
Fig.6 Transfer characteristics; typical values.
MDA615
MDA616
16
40
handbook, halfpage
handbook, halfpage
I
y
D
fs
(mS)
V
= 4 V
G2-S
(mA)
3.5 V
12
30
(1) (2) (3)
3 V
8
4
0
20
10
0
(4)
2.5 V
I
2 V
0
1
2
3
4
V
5
(V)
0
10
20
30
D (mA)
G2-S
(1) VDS = 9 V.
(2) VDS = 7 V.
(3)
V
DS = 5 V.
VDS = 9 V.
(4) VDS = 3 V.
Tj = 25 C.
Fig.7 Forward transfer admittance as a function
of drain current; typical values.
Fig.8 Drain current as a function of gate 2
voltage; typical values.
1997 Dec 08
5
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
MDA617
MDA618
16
16
handbook, halfpage
handbook, halfpage
I
I
D
D
(mA)
(mA)
12
12
8
4
0
8
4
0
−8
−6
−4
−2
0
0
2
4
6
8
10
(V)
I
(μA)
V
G1
DS
VG2-S = 4 V.
VDS = 9 V; VG2-S = 4 V; Tj = 25 C.
Tj = 25 C.
Fig.9 Drain current as a function of drain-source
voltage; typical values.
Fig.10 Drain current as a function of gate 1 current;
typical values.
MDA619
120
handbook, halfpage
V
unw
(dBμV)
110
100
90
80
0
20
40
60
gain reduction (dB)
VDS = 9 V; VG2nom = 4 V; IDnom = 12 mA; fw = 50 MHz;
funw = 60 MHz; Tamb = 25 C.
Fig.11 Unwanted voltage for 1% cross-modulation
as a function of gain reduction;
typical values (see Fig.18).
1997 Dec 08
6
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
MDA621
MDA620
2
3
3
10
−10
10
handbook, halfpage
handbook, halfpage
y
is
|y
|
ϕ
(deg)
rs
(mS)
rs
(mS)
10
|y
|
rs
2
2
10
−10
b
is
1
ϕ
rs
−10
10
g
is
−1
10
−2
10
−1
1
10
10
3
3
2
10
2
10
10
10
f (MHz)
f (MHz)
VDS = 9 V; VG2-S = 4 V.
VDS = 9 V; VG2-S = 4 V.
ID = 12 mA; Tamb = 25 C.
ID = 12 mA; Tamb = 25 C.
Fig.12 Input admittance as a function of frequency;
typical values.
Fig.13 Reverse transfer admittance and phase as
a function of frequency; typical values.
MDA622
MDA623
2
2
10
−10
10
handbook, halfpage
handbook, halfpage
y
|y
|
ϕ
(deg)
os
(mS)
fs
(mS)
fs
|y
|
fs
b
os
1
−10
10
ϕ
fs
−1
10
10
g
os
−2
−1
1
10
3
2
3
2
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 9 V; VG2-S = 4 V.
D = 12 mA; Tamb = 25 C.
VDS = 9 V; VG2-S = 4 V.
D = 12 mA; Tamb = 25 C.
I
I
Fig.14 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.15 Output admittance as a function of
frequency; typical values.
1997 Dec 08
7
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
V
V
AGC
DS
1 nF
2 μH
1 nF
1 nF
1 nF
output
50 Ω
47 kΩ
L2
1 nF
G2
G1
D
BF1109
BF1109R
BF1109WR
5.5 pF
C1
10 pF
S
input
50 Ω
15
pF
BB405
L1
330 kΩ
1 nF
BB405
V
330 kΩ
1 nF
1 nF
input
V
output
tun
tun
MDA624
VDS = 9 V, GS = 2 mS, GL = 0.5 mS, f = 200 MHz.
L1 = 45 nH, 4 turns, internal diameter = 4 mm, 0.8 mm copper wire.
L2 = 160 nH, 3 turns, internal diameter = 8 mm, 0.8 mm copper wire; tapped at approximately half a turn from the cold side, to set GL = 0.5 mS.
C1 adjusted for GS = 2 mS.
Fig.16 Gain test circuit.
V
V
AGC
1 nF
DS
1 nF
47 kΩ
L3
1 nF
1 nF
L2
G2
G1
D
S
output
50 Ω
BF1109
BF1109R
BF1109WR
1 nF
L1
input
0.5 to 3.5 pF
4 to 40 pF
50 Ω
MDA625
2 to 18 pF
0.5 to 3.5 pF
VDS = 9 V, GS = 3.3 mS, GL = 1 mS, f = 800 MHz.
L1 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane.
L2 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane.
L3 = 11 turns 0.5 mm copper wire without spacing, internal diameter = 3 mm, L = approx. 200 nH.
Fig.17 Gain test circuit.
1997 Dec 08
8
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
V
V
G2
DS
4.7 nF
10 kΩ
47 μH
4.7 nF
10 nF
G2
G1
D
BF1109
BF1109R
BF1109WR
10 nF
R1 =
50 Ω
S
R
gen
50 Ω
50 Ω
MDA626
V
i
Fig.18 Cross-modulation test set-up.
Table 1 Scattering parameters: VDS = 9 V; VG2-S = 4 V; ID = 12 mA
S11
S21
S12
S22
f
MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(MHz)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
50
100
200
300
400
500
600
700
800
900
1000
0.995
0.992
0.984
0.973
0.961
0.944
0.926
0.906
0.887
0.868
0.852
3.71
7.29
14.3
21.2
27.9
34.4
40.8
46.9
52.9
58.8
64.3
3.013
3.002
2.967
2.922
2.869
2.793
2.730
2.660
2.605
2.527
2.457
175.0
170.2
160.7
151.3
142.0
132.9
124.1
1115.3
106.5
97.8
0.000
0.001
0.002
0.002
0.003
0.003
0.003
0.003
0.004
0.004
0.004
88.2
83.7
0.998
0.997
0.995
0.992
0.990
0.987
0.985
0.983
0.981
0.977
0.9377
1.8
3.5
86.2
7.0
83.2
10.5
13.9
17.2
20.5
23.7
26.8
30.0
33.1
84.1
85.7
88.4
94.6
107.2
114.9
129.7
89.6
Table 2 Noise data: VDS = 9 V; VG2-S = 4 V; ID = 12 mA
opt
f
Fmin
(dB)
Rn
()
(MHz)
(ratio)
(deg)
40.94
800
1.5
0.684
40.4
1997 Dec 08
9
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
PACKAGE OUTLINES
Plastic surface-mounted package; 4 leads
SOT143B
D
B
E
A
X
y
H
v
M
A
E
e
b
p
w
M
B
4
3
Q
A
A
1
c
1
2
L
p
b
1
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
UNIT
A
b
b
c
D
E
e
e
H
L
p
Q
v
w
y
p
1
1
E
1.1
0.9
0.48
0.38
0.88
0.78
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.45
0.15
0.55
0.45
0.1
mm
1.9
1.7
0.2
0.1
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-16
06-03-16
SOT143B
1997 Dec 08
10
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
Plastic surface-mounted package; reverse pinning; 4 leads
SOT143R
D
B
E
A
X
y
H
v
M
A
E
e
b
w
M
B
p
3
4
Q
A
A
1
c
2
1
L
p
b
1
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
UNIT
A
b
b
c
D
E
e
e
H
L
p
Q
v
w
y
p
1
1
E
1.1
0.9
0.48
0.38
0.88
0.78
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.55
0.25
0.45
0.25
0.1
mm
1.9
1.7
0.2
0.1
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-16
06-03-16
SOT143R
SC-61AA
1997 Dec 08
11
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
Plastic surface-mounted package; reverse pinning; 4 leads
SOT343R
D
B
E
A
X
H
v
M
A
y
E
e
3
4
Q
A
A
1
c
2
1
L
w
M
B
b
b
1
p
p
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
A
UNIT
b
b
c
D
E
e
e
H
E
L
Q
v
w
y
p
p
1
1
0.4
0.3
1.1
0.8
0.7
0.5
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.23
0.13
mm
0.1
1.15
0.2
0.2
0.1
1.3
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
97-05-21
06-03-16
SOT343R
1997 Dec 08
12
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Product data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DEFINITIONS
Right to make changes NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Product specification The information and data
provided in a Product data sheet shall define the
specification of the product as agreed between NXP
Semiconductors and its customer, unless NXP
Semiconductors and customer have explicitly agreed
otherwise in writing. In no event however, shall an
agreement be valid in which the NXP Semiconductors
product is deemed to offer functions and qualities beyond
those described in the Product data sheet.
Suitability for use NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
DISCLAIMERS
Limited warranty and liability Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
Applications Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
1997 Dec 08
13
NXP Semiconductors
Product specification
N-channel dual-gate MOS-FETs
BF1109; BF1109R; BF1109WR
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Export control This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
Quick reference data The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
Terms and conditions of commercial sale NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Semiconductors’ product specifications.
No offer to sell or license Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
1997 Dec 08
14
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R77/02/pp15
Date of release: 1997 Dec 08
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