BF1201WR,135 [NXP]
N-channel dual-gate MOSFET;
| 型号： | BF1201WR,135 |
| 厂家： | 
NXP |
| 描述： | N-channel dual-gate MOSFET |
| 文件： | 总15页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
BF1201; BF1201R; BF1201WR
N-channel dual-gate PoLo
MOS-FETs
Product specification
2000 Mar 29
Supersedes data of 1999 Dec 01
NXP Semiconductors
Product specification
BF1201; BF1201R;
BF1201WR
N-channel dual-gate PoLo MOS-FETs
FEATURES
PINNING
PIN
Short channel transistor with high
forward transfer admittance to input
capacitance ratio
DESCRIPTION
source
3
4
1
2
3
4
drain
Low noise gain controlled amplifier
gate 2
2
1
Partly internal self-biasing circuit to
ensure good cross-modulation
performance during AGC and good
DC stabilization.
gate 1
Top view
MSB035
BF1201R marking code: LBp
APPLICATIONS
Fig.2 Simplified outline
(SOT143R).
VHF and UHF applications with
3 to 9 V supply voltage, such as
digital and analogue television
tuners and professional
communications equipment.
3
4
4
3
page
DESCRIPTION
Enhancement type N-channel
field-effect transistor with source and
substrate interconnected. Integrated
diodes between gates and source
protect against excessive input
voltage surges. The BF1201,
BF1201R and BF1201WR are
encapsulated in the SOT143B,
SOT143R and SOT343R plastic
packages respectively.
1
2
2
1
Top view
MSB842
Top view
MSB014
BF1201 marking code: LAp.
BF1201WR marking code: LA
Fig.1 Simplified outline
(SOT143B).
Fig.3 Simplified outline
(SOT343R).
QUICK REFERENCE DATA
SYMBOL
VDS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
10
UNIT
drain-source voltage
drain current
V
ID
30
200
35
3.1
30
1.8
mA
mW
mS
pF
Ptot
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
yfs
Cig1-ss
Crss
F
23
28
2.6
15
1
f = 1 MHz
fF
f = 400 MHz
dB
Xmod
cross-modulation
input level for k = 1% at
40 dB AGC
105
dBV
Tj
operating junction temperature
150
C
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling.
2000 Mar 29
2
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
drain-source voltage
CONDITIONS
MIN.
MAX.
10
UNIT
VDS
ID
V
drain current (DC)
gate 1 current
30
mA
mA
mA
IG1
IG2
Ptot
10
10
gate 2 current
total power dissipation
BF1201; BF1201R
BF1201WR
Ts 113 C; note 1
Ts 109 C; note 1
200
200
+150
150
mW
mW
C
Tstg
Tj
storage temperature
operating junction temperature
65
C
Note
1. Ts is the temperature of the soldering point of the source lead.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
thermal resistance from junction to soldering point
BF1201; BF1201R
VALUE
UNIT
Rth j-s
185
155
K/W
K/W
BF1201WR
MCD934
250
handbook, halfpage
P
tot
(mW)
200
(1)
(2)
150
100
50
0
0
50
100
150
200
T
(°C)
s
(1) BF1201WR.
(2) BF1201 and BF1201R.
Fig.4 Power derating curve.
2000 Mar 29
3
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
STATIC CHARACTERISTICS
Tj = 25 C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
V(BR)DSS
drain-source breakdown voltage
VG1-S = VG2-S = 0; ID = 10 A
VG2-S = VDS = 0; IG1-S = 10 mA
VG1-S = VDS = 0; IG2-S = 10 mA
VG2-S = VDS = 0; IS-G1 = 10 mA
VG1-S = VDS = 0; IS-G2 = 10 mA
VG2-S = 4 V; VDS = 5 V; ID = 100 A
VG1-S = VDS = 5 V; ID = 100 A
10
6
V
V(BR)G1-SS gate 1-source breakdown voltage
V(BR)G2-SS gate 2-source breakdown voltage
V
6
V
V(F)S-G1
V(F)S-G2
VG1-S(th)
VG2-S(th)
IDSX
forward source-gate 1 voltage
forward source-gate 2 voltage
gate 1-source threshold voltage
gate 2-source threshold voltage
drain-source current
0.5
0.5
0.3
0.3
11
1.5
1.5
1.0
1.2
19
V
V
V
V
VG2-S = 4 V; VDS = 5 V; RG1 = 62 k;
mA
note 1
IG1-SS
IG2-SS
gate 1 cut-off current
gate 2 cut-off current
VG2-S = VDS = 0; VG1-S = 5 V
VG1-S = VDS = 0; VG2-S = 4 V
50
20
nA
nA
Note
1.
RG1 connects G1 to VGG = 5 V.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
23
TYP. MAX. UNIT
yfs
Cig1-ss
Cig2-ss
Coss
Crss
forward transfer admittance pulsed; Tj = 25 C
28
2.6
1.1
0.9
15
5
35
3.1
mS
pF
pF
pF
fF
input capacitance at gate 1
input capacitance at gate 2
output capacitance
f = 1 MHz
f = 1 MHz
f = 1 MHz
reverse transfer capacitance f = 1 MHz
30
7
F
noise figure
f = 10.7 MHz; GS = 20 mS; BS = 0
dB
dB
dB
dB
f = 400 MHz; YS = YS opt
1
1.8
2.5
f = 800 MHz; YS = YS opt
1.9
33.5
Gtr
power gain
f = 200 MHz; GS = 2 mS; BS = BS opt
;
GL = 0.5 mS; BL = BL opt
f = 400 MHz; GS = 2 mS; BS = BS opt
GL = 1 mS; BL = BL opt
f = 800 MHz; GS = 3.3 mS; BS = BS opt
GL = 1 mS; BL = BL opt
;
;
29
24
dB
dB
;
;
;
Xmod
cross-modulation
input level for k = 1%; fw = 50 MHz;
funw = 60 MHz; note 1
at 0 dB AGC
at 10 dB AGC
at 40 dB AGC
90
dBV
dBV
dBV
95
105
Note
1. Measured in Fig.21 test circuit.
2000 Mar 29
4
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
MCD935
MCD936
25
24
handbook, halfpage
handbook, halfpage
3.5 V
V
= 4 V
G2-S
I
D
(mA)
20
3 V
V
= 1.8 V
I
G1-S
D
(mA)
2.5 V
1.7 V
16
1.6 V
1.5 V
1.4 V
15
10
2 V
8
1.3 V
1.2 V
1.5 V
5
0
1 V
0
0
0
0.5
1
1.5
2
2.5
(V)
2
4
6
8
10
(V)
V
V
DS
G1-S
VDS = 5 V.
VG2-S = 4 V.
Tj = 25 C.
Tj = 25 C.
Fig.5 Transfer characteristics; typical values.
Fig.6 Output characteristics; typical values.
MCD937
MCD938
100
40
handbook, halfpage
handbook, halfpage
V
= 4 V
I
G2-S
G1
(μA)
80
3.5 V
3 V
y
fs
V
= 4 V
(mS)
G2-S
30
3.5 V
60
40
20
10
0
2.5 V
3 V
2.5 V
2 V
20
2 V
1.5 V
0
0
0.5
1
1.5
2
2.5
(V)
0
5
10
15
20
I
25
(mA)
V
D
G1-S
VDS = 5 V.
VDS = 5 V.
Tj = 25 C.
Tj = 25 C.
Fig.7 Gate 1 current as a function of gate 1
voltage; typical values.
Fig.8 Forward transfer admittance as a function
of drain current; typical values.
2000 Mar 29
5
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
MCD940
MCD939
20
16
handbook, halfpage
handbook, halfpage
I
D
I
D
(mA)
16
(mA)
12
12
8
8
4
0
4
0
0
1
2
3
4
5
0
10
20
30
40
I
50
(μA)
V
(V)
GG
G1
VDS = 5 V; VG2-S = 4 V.
VDS = 5 V; VG2-S = 4 V; Tj = 25 C.
RG1 = 62 k (connected to VGG); see Fig.21.
Tj = 25 C.
Fig.9 Drain current as a function of gate 1 current;
typical values.
Fig.10 Drain current as a function of gate 1 supply
voltage (= VGG); typical values.
MCD941
MCD942
25
20
handbook, halfpage
68 kΩ
handbook, halfpage
R
= 39 kΩ
I
G1
47 kΩ
56 kΩ
62 kΩ
I
D
(mA)
20
D
(mA)
82 kΩ
V
= 5 V
GG
16
12
8
100 kΩ
4.5 V
15
10
4 V
3.5 V
3 V
5
0
4
0
0
2
4
6
8
10
(V)
0
2
4
6
V
(V)
V
= V
DS
G2-S
GG
VG2-S = 4 V; Tj = 25 C.
RG1 connected to VGG; see Fig.21.
VDS = 5 V; Tj = 25 C.
G1 = 62 k (connected to VGG); see Fig.21.
R
Fig.11 Drain current as a function of gate 1 (= VGG
)
Fig.12 Drain current as a function of gate 2
voltage; typical values.
and drain supply voltage; typical values.
2000 Mar 29
6
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
MCD943
MCD944
60
0
handbook, halfpage
V
= 5 V
handbook, halfpage
GG
gain
reduction
(dB)
I
G1
(μA)
−10
4.5 V
4 V
40
−20
−30
3.5 V
3 V
20
−40
−50
0
0
2
4
6
0
1
2
3
4
V
(V)
V
(V)
G2-S
AGC
VDS = 5 V; Tj = 25 C.
RG1 = 62 k (connected to VGG); see Fig.21.
VDS = 5 V; VGG = 5 V; RG1 = 62 k;
f = 50 MHz; Tamb = 25 C.
Fig.13 Gate 1 current as a function of gate 2
voltage; typical values.
Fig.14 Typical gain reduction as a function of the
AGC voltage; see Fig.21.
MCD945
120
MCD946
handbook, halfpage
20
handbook, halfpage
V
unw
(dBμV)
I
D
(mA)
16
110
12
8
100
90
4
0
80
0
10
20
30
40
50
0
10
20
30
40
50
gain reduction (dB)
gain reduction (dB)
VDS = 5 V; VGG = 5 V; RG1 = 62 k; f = 50 MHz;
unw = 60 MHz; Tamb = 25 C.
f
VDS = 5 V; VGG = 5 V; RG1 = 62 k;
f = 50 MHz; Tamb = 25 C.
Fig.15 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.21.
Fig.16 Drain current as a function of gain
reduction; typical values; see Fig.21.
2000 Mar 29
7
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
MCD947
2
10
MCD948
3
3
handbook, halfpage
10
−10
handbook, halfpage
Y
is
(mS)
ϕ
(deg)
y
rs
rs
(μS)
10
ϕ
rs
2
2
−10
10
b
is
y
rs
g
is
1
−10
−1
10
−1
10
10
2
3
10
10
1
2
3
f (MHz)
10
10
10
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 C.
ID = 15 mA; Tamb = 25 C.
Fig.17 Input admittance as a function of frequency;
typical values.
Fig.18 Reverse transfer admittance and phase as
a function of frequency; typical values.
MCD949
MCD950
2
2
10
−10
10
handbook, halfpage
handbook, halfpage
ϕ
(deg)
y
Y
fs
fs
os
(mS)
(mS)
y
fs
b
os
1
ϕ
fs
10
−10
−1
10
g
os
−2
10
−1
1
10
2
3
2
3
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
I
D = 15 mA; Tamb = 25 C.
ID = 15 mA; Tamb = 25 C.
Fig.19 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.20 Output admittance as a function of
frequency; typical values.
2000 Mar 29
8
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
V
AGC
R1
10 kΩ
C1
4.7 nF
C3
4.7 nF
R
50 Ω
L1
≈2.2 μH
L
C2
DUT
C4
4.7 nF
R
GEN
50 Ω
R2
50 Ω
R
G1
4.7 nF
V
V
V
I
GG
DS
MGS315
Fig.21 Cross-modulation test set-up.
Table 1 Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C
s11
s21
s12
s22
f
MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(MHz)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
50
100
200
300
400
500
600
700
800
900
1000
0.987
0.985
0.978
0.976
0.949
0.928
0.905
0.882
0.860
0.838
0.818
4.72
9.39
2.775
2.774
2.731
2.671
2.599
2.501
2.400
2.297
2.199
2.096
1.997
174.6
169.5
159.1
148.8
138.8
129.1
119.8
110.9
102.4
94.2
0.0006
0.0010
0.0019
0.0026
0.0032
0.0035
0.0035
0.0033
0.0029
0.0024
0.0021
88.8
86.7
79.7
74.2
69.9
65.9
64.6
65.7
69.1
83.3
103.8
0.997
0.997
0.996
0.994
0.992
0.989
0.986
0.982
0.979
0.975
0.971
1.84
3.37
18.59
27.74
36.59
45.08
53.26
61.07
68.48
75.55
82.23
6.72
10.02
13.33
16.55
19.64
22.63
25.54
28.44
31.42
86.3
Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C
opt
f
Fmin
(dB)
Rn
()
(MHz)
(ratio)
0.825
0.753
(deg)
400
800
1
38.93
70.65
50
1.9
38.75
2000 Mar 29
9
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
PACKAGE OUTLINES
Plastic surface-mounted package; 4 leads
SOT143B
D
B
E
A
X
y
H
v
M
A
E
e
b
w
M
B
p
4
3
Q
A
A
1
c
1
2
L
p
b
1
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
UNIT
A
b
b
c
D
E
e
e
H
L
p
Q
v
w
y
p
1
1
E
1.1
0.9
0.48
0.38
0.88
0.78
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.45
0.15
0.55
0.45
0.1
mm
1.9
1.7
0.2
0.1
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-16
06-03-16
SOT143B
2000 Mar 29
10
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
Plastic surface-mounted package; reverse pinning; 4 leads
SOT143R
D
B
E
A
X
y
H
v
M
A
E
e
b
w
M
B
p
3
4
Q
A
A
1
c
2
1
L
p
b
1
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
UNIT
A
b
b
c
D
E
e
e
H
L
p
Q
v
w
y
p
1
1
E
1.1
0.9
0.48
0.38
0.88
0.78
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.55
0.25
0.45
0.25
0.1
mm
1.9
1.7
0.2
0.1
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-16
06-03-16
SOT143R
SC-61AA
2000 Mar 29
11
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
Plastic surface-mounted package; reverse pinning; 4 leads
SOT343R
D
B
E
A
X
H
v
M
A
y
E
e
3
4
Q
A
A
1
c
2
1
L
w
M
B
b
b
1
p
p
e
1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
A
UNIT
b
b
c
D
E
e
e
H
E
L
Q
v
w
y
p
p
1
1
0.4
0.3
1.1
0.8
0.7
0.5
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.23
0.13
mm
0.1
1.15
0.2
0.2
0.1
1.3
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
97-05-21
06-03-16
SOT343R
2000 Mar 29
12
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Product data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
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reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
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provided in a Product data sheet shall define the
specification of the product as agreed between NXP
Semiconductors and its customer, unless NXP
Semiconductors and customer have explicitly agreed
otherwise in writing. In no event however, shall an
agreement be valid in which the NXP Semiconductors
product is deemed to offer functions and qualities beyond
those described in the Product data sheet.
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not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
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accepts no liability for inclusion and/or use of NXP
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applications and therefore such inclusion and/or use is at
the customer’s own risk.
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However, NXP Semiconductors does not give any
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shall have no liability for the consequences of use of such
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warranty that such applications will be suitable for the
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for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
2000 Mar 29
13
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Export control This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
Quick reference data The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
Terms and conditions of commercial sale NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Semiconductors’ product specifications.
No offer to sell or license Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
2000 Mar 29
14
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R77/02/pp15
Date of release: 2000 Mar 29
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