BGU8822 [NXP]
Dual channel low-noise high linearity amplifier with DSA and SPDT;
| 型号： | BGU8822 |
| 厂家： | 
NXP |
| 描述： | Dual channel low-noise high linearity amplifier with DSA and SPDT 光电二极管 |
| 文件： | 总43页 (文件大小：595K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and
SPDT
Rev. 6 — 15 April 2020
Product data sheet
1 General description
The BGU8822/A, also known as the BTS5201M/A, is a highly integrated dual channel
digitally controlled low noise amplifier (LNA) with digital step attenuator (DSA) and a
single-pole double-through (SPDT) switch. The BGU8822/A supports receivers (main
and diversity) in both TDD and FDD systems. It has a first stage LNA optimized for
sensitivity, followed by a DSA and output stage amplifier. To support highly integrated
solutions and reduce platform costs a standalone SPDT switch is included.
The <keyword keyref="btn"/> is optimized for frequency band 1.4 GHz - 2.2 GHz, but
supports 2.2 GHz - 2.7 GHz as well.
The <keyword keyref="btn"/> is controlled via SPI bus, supporting both 3- and 4-wire
configurations. Additionally, in TDD systems the LNAs and DSA can also be controlled
via direct-access pins.
The <keyword keyref="btn"/> is housed in a small footprint (5 x 5 x 0.72 mm) 44-pin
leadless package.
2 Features and benefits
• Dual channel (diversity and main) highly integrated LNA + DSA
• Frequency bands 1.4 GHz - 2.2.GHz and 2.2 GHz - 2.7 GHz
• Noise figure = 0.7 dB
• High linearity: IP3O = 37 dBm
• High input return loss >13 dB
• High output return loss >13 dB
• Unconditionally stable up to 20 GHz
• Digital step attenuator with 31 dB range and 1 dB step
• High linearity SPDT, Pi(1dB) = 35 dBm, IP3i = 51 dBm
• Programmable via 3 wire or 4-wire SPI (Read/write)
• Small 44-terminal leadless package 5 mm × 5 mm × 0.72 mm
• ESD protection on all terminals
• Moisture sensitivity level 3
• +5 V single supply
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
3 Applications
• Wireless infrastructure
• 5G ready
• Low noise and high linearity applications
• LTE, W-CDMA, CDMA, GSM
• General-purpose wireless applications
• TDD or FDD systems
• Suitable for small cells
4 Quick reference data
Table 1.ꢀQuick reference data BGU8822/A LNA1
f = 2200 MHz; VCC = 5 V; Tamb = 25 °C; input and output 50 Ω; unless otherwise specified. All RF parameters are measured
in an application board as shown in Figure 52 with components listed in Table 33 optimized for f = 2200 MHz.
Symbol
Parameter
Conditions
LNA1 enable
Disable
Min Typ Max Unit
ICC
supply current
-
-
54
3
64
-
mA
mA
dB
[1]
[1]
[1]
[1]
Gp
power gain
16.3 18
0.7
17.9 19
34 37
-
NF
noise figure
-
-
dB
PL(1dB)
IP3O
output power at 1 dB gain compression
output third-order intercept point
-
dBm
dBm
2-tone; tone spacing = 1 MHz;
Pi = -15 dBm per tone
-
[1] Connector and Printed-Circuit Board (PCB) losses have been de-embedded for all RF parameters.
Table 2.ꢀQuick reference data BGU8822/A DSA+LNA2
f = 2200 MHz; VCC = 5 V; Tamb = 25 °C; input and output 50 Ω; unless otherwise specified. All RF parameters are measured
in an application board as shown in Figure 52 with components listed in Table 33 optimized for f = 2200 MHz.
Symbol
Parameter
Conditions
LNA2 enable
Disable
Min Typ Max Unit
ICC
supply current
-
-
57
5
67
-
mA
mA
dB
[1]
[1]
[1]
Gp
power gain
noise figure
15.9 17
2.3
17.9 20
-
NF
-
-
dB
PL(1dB)
output power at 1 dB gain
compression
-
dBm
[1]
IP3O
output third-order intercept point
2-tone; tone spacing = 1 MHz;
Pi = -15 dBm per tone
34
37
-
dBm
[1] Connector and Printed-Circuit Board (PCB) losses have been de-embedded for all RF parameters.
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
2 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Table 3.ꢀQuick reference data BGU8822/A SPDT
f = 2200 MHz; VCC = 5 V; Tamb = 25 °C; input and output 50 Ω; unless otherwise specified. All RF parameters are measured
in an application board as shown in Figure 52 with components listed in Table 33 optimized for f = 2200 MHz.
Symbol
ICC
Parameter
Conditions
Min Typ Max Unit
supply current
-
-
-
-
-
2.1
-
mA
[1]
αins
insertion loss
1.25 2.1 dB
RLin
input return loss
all SPDT pins
14
35
51
-
-
-
dB
Pi(1dB)
IP3i
input power at 1 dB gain compression
input third-order intercept point
dBm
dBm
2-tone; tone spacing = 1 MHz;
Pi = +5 dBm per tone
[1] Connector and Printed-Circuit Board (PCB) losses have been de-embedded for all RF parameters.
5 Ordering information
Table 4.ꢀOrdering information
Type
Orderable
Package
number
part number
Name
Description
Version
BGU8822/A BGU8822/AY HVLGA44 plastic thermal enhanced very thin profile land grid array
package; no leads; 44 terminals; body 5 × 5 × 0.72 mm
SOT1431-1
6 Functional diagram
Disable Main Channel
VDD_SPI
RFIN_M
DSA M
LNA1 M
LNA2 M
VDD_SPDT
DSA_0_X dB Main
SW_RF2
SW_RFC
SW_RF1
SCLK
CSB
SDIO
SDO
SPI
GPO/DSA_0_X dB Diversity
LNA2 D
LNA1 D
RFIN_D
DSA D
SPDT
Disable Diversity Channel
aaa-020599
Figure 1.ꢀFunctional diagram
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
3 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
7 Pinning information
7.1 Pinning
terminal 1
index area
34
GND
1
VDD_SPI
RFIN_M
2
3
4
5
6
7
8
9
33 VDD_SPDT
32 GND/Disable Main channel
31 SW_RF2
GND
GND
SCLK
CSB
30 GND
29 GND
exposed die pad
SDIO
28 SW_RFC
SDO
27 GND
DSA_0_X dB Main
26 GND
GND 10
25 SW_RF1
RFIN_D 11
24 GND/Disable Diversity channel
GND 12
23
GPO/DSA_0_X dB Diversity
aaa-020600
Transparent top view
Multiple power and ground pins allows for independent supply domains to improve cross channel isolation and between
blocks in one single channel. In, order to reduce series inductance at all RF ports and RF grounding a small package
footprint was chosen.
Figure 2.ꢀPin configuration
7.2 Pin description
Table 5.ꢀPin description
Symbol
Pin
Description
GND
1, 3, 4, 10, 12,
14,16, 17, 19, 20,
26, 27, 29, 30, 37,
38,40, 41,43
Ground
RFIN_M
2
RF Input to LNA1, main channel. An external DC block is required.
External SMD is required for matching.
SCLK
5
6
7
8
9
Clock input for SPI
CSB
Chip select active low
SDIO
Serial data in/out. Push-Pull pin
Serial data out. Push-Pull pin
SDO
DSA_0_X dB Main
Direct-access DSA setting between minimum attenuation and X dB
attenuation programmed prior to TDD mode, main channel
BGU8822/A
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Product data sheet
Rev. 6 — 15 April 2020
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Symbol
Pin
Description
RFIN_D
11
RF Input to LNA1, diversity channel. An external DC block is required.
External SMD is required for matching.
VDD1_D
13
15
Supply to LNA1, diversity channel. Decoupling capacitors are required
LNA1OUT_D
RF output of LNA1, diversity channel. An external DC block + BIAS
choke are required.
DSAIN_D
LNA2OUT_D
VDD2_D
18
21
22
RF input to DSA, diversity channel. An external DC block + matching
SMD are required.
RF output of LNA2, diversity channel. An external DC block + BIAS
choke are required.
Supply to LNA2, diversity channel. Decoupling capacitors are required.
GPO/DSA_0_X dB Diversity 23
GPO (General Purpose Output). Leave open when not used.
Direct-access DSA setting between minimum attenuation and X dB
attenuation programmed prior to TDD mode diversity channel
GND/Disable Diversity
Channel
24
Ground or Disable Diversity Channel
SW_RF1
25
28
31
32
33
34
35
36
Switch RF path 1. An external DC block is required
Switch RF common. An external DC block is required
Switch RF path 2. An external DC block is required
Ground or Disable Main Channel
SW_RFC
SW_RF2
GND/Disable Main Channel
VDD_SPDT
VDD_SPI
VDD into SPDT, decoupling capacitors are required
VDD into SPI, decoupling capacitors are required
Supply to LNA2, main channel. Decoupling capacitors are required
VDD2_M
LNA2OUT_M
RF output of LNA2, main channel. An external DC block + BIAS choke
are required.
DSAIN_M
39
42
44
RF input to DSA, main channel. An external DC block + matching SMD
are required.
LNA1OUT_M
RF output from LNA1, main channel. An external DC block + BIAS
choke are required.
VDD1_M
GND
Supply to LNA2, diversity channel. Decoupling capacitors are required.
Exposed die pad
Ground
BGU8822/A
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Product data sheet
Rev. 6 — 15 April 2020
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
8 Functional description
8.1 Direct-Access Functionality for Main and Diversity Channels in TDD
Systems
In addition to SPI in TDD systems the LNAs and DSA can also be controlled via direct-
access pins. Pins 32 and 24 are used for Direct Disable mode for Main and Diversity
channels correspondingly.
Pins 9 and 23 are used for Direct DSA Attenuation mode for Main and Diversity channels
correspondingly.
By default, the BGU8822/A starts up in direct-access mode. SPI bus remains fully
functional. <VDD_SPI> pin has to be connected to power supply. Reset command
<SPI_RST> must be applied.
8.1.1 Direct Disable mode
In Direct Disable mode Main and Diversity channels can be disabled independently
without accessing SPI bus.
Pin 32 < Disable Main Channel> shall be set to HIGH to disable Main channel (LNA1_M
and LNA2_M of the Main channel are disabled (set in low current mode).
Pin 24 < Disable Diversity Channel> shall be set to HIGH to disable Diversity channel
(LNA1_D and LNA2_D of the Diversity channel are disabled (set in low current mode).
VIH voltage for those pins is limited to 2.75 V, as indicated in Table 31.
Direct Disable mode functionality has similar effect as if both LNA1 and LNA2 of Main or
Diversity channels have been disabled via LNA Enable bits (register 0x10h, bits [7-6] for
Main channel and bits [5-4] for Diversity channel).
8.1.2 Direct DSA Attenuation mode
In Direct DSA Attenuation mode, Main and Diversity DSAs can be toggled independently
without accessing SPI bus.
Pin 9 <DSA_0_X_dB Main> can be toggled to set DSA_M between Minimum Attenuation
(level LOW) and predefined X dB attenuation (level HIGH). X dB attenuation is defined in
DSA_M_TDD_ATTN (register 0x16h, bits [6-2]). Default reset value is 15 dB.
BGU8822/A
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Product data sheet
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Table 6.ꢀDirect DSA Attenuation mode for Main channel truth table
Legend: * reset value
Pin 9
DIRECT_DSA_M
DSA_M Attenuation
Description
DSA_0_X dB Main
register 0x13h, bit [1]
0
1
0*
0*
Min attenuation IL
IL x X dB Attenuation
X dB is set in register 0x16h,
default value is 15 dB
x
1
SPI setting
DSA_M controlled by SPI
using register 0x11h, default
value is Min attenuation, IL
Pin 23 <GPO/DSA_0_X_dB Diversity> can be toggled to set DSA_M between Minimum
Attenuation (level LOW) and predefined X dB attenuation (level HIGH). X dB attenuation
is defined in DSA_D_TDD_ATTN (register 0x17h, bits [6-2]). Default reset value is 15 dB.
Table 7.ꢀDirect DSA Attenuation mode for Diversity channel truth table
Legend: * reset value
Pin 23
DIRECT_DSA_D
DSA_D Attenuation
Description
DSA_0_X dB Diversity
register 0x13h, bit [2]
0
1
0*
0*
Min attenuation IL
IL x X dB Attenuation
X dB is set in register 0x17h,
default value is 15 dB
GPO functionality
1
SPI setting
DSA_D controlled by SPI
using register 0x12h, default
value is Min attenuation, IL
By default, the BGU8822/A starts up in Direct DSA Attenuation mode. This mode can be
switched off via register 0x13h, bits [1] (for the Main channel) and [2] (for the Diversity
channel). While Direct DSA Attenuation mode for Diversity channel is active, GPO
functionality is not available.
When DIRECT_DSA_D (register 0x13h bit [2]) is set HIGH, Direct DSA Attenuation mode
for Diversity channel is switched off and Pin 23 is used as <GPO> pin.
8.2 Serial Peripheral interface (SPI) Bus
The Serial Peripheral Interface (SPI) bus allows simple interfacing with many industry
microprocessors; it provides access to all the registers that define the operation of the
BGU8822/A.
BGU8822/A
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Product data sheet
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
8.2.1 Hardware Interface description
The SPI functionality includes registers and an address decoder to support both read and
write operations. Register mapping is organized as a 15-bit address register and an 8-bit
data register. In order to avoid register coupling, data should always be sent as an 8-bit
sequence.
Register addresses 0x00h – 0x06h, 0x10h – 0x13h, 0x16h – 0x17h and 0x0Ch –
0x0Fh set the operation of the BGU8822/A. Any other address used does not affect the
behavior of the device (e.g. device does not stall).
The BGU8822/A supports a 3-wire or 4-wire SPI bus operation mode. <SDIO> is used
as a bidirectional pin in 3-wire mode. During the write cycle, it is used as an input pin and
during the read cycle as output pin. In 4-wire bus mode, <SDIO> and <SDO> are used
as unidirectional input and output pins correspondingly. <CLK> acts as the serial clock
input. The status of <CSB> defines whether the SPI interface of the device is enabled
(<CSB> is LOW) or disabled (<CSB> is HIGH). Programming clock edges (rising edges)
at <CLK> input and data at the <SDIO> input are ignored until LOW-level is applied to
the <CSB> input.
When the BGU8822/A is in power-down mode or there is no power supplied, the <SDIO>
and <CSB> pins become high-impedance and do not disturb the SPI bus.
8.2.2 Programming registers
The programming word is set through the input <SDIO> pin and a shift register, while
<CSB> level is LOW. To release the SPI bus, <CSB> is set HIGH again.
The rising edge of the clock pulse <CLK> shifts each data bit value into the shift register.
The BGU8822/A supports single-byte and multi-byte (streaming) read/write access
(register 0x01h bit [7]). In single-byte access, the new settings of the programmed
register are applied on the last rising edge of <CLK> of data byte period. In multi-byte
(streaming) access mode register address is auto-incremented or auto-decremented
(depends on register 0x00h bits [5] and [2]) for the next 8-bit programming word.
By default, the data is entered with the most significant bit (MSB) first and the least
significant bit (LSB) last. Register 0x00h bits [6] and [1] can be used to reverse the order
(LSB bit first).
Figure 3 and Figure 4 illustrate SPI read and write cycles for 3-wire and 4-wire modes.
t
s
t
t
Hi
t
t
C
DS
CLK
t
t
Lo
DH
<CSB>
<SCLK> DC
<SDIO> DC
DC
t
DV
R/W A14 A13 A12 A11 A10 A09 .... A1 A0 D7 D6 D5 .... D1 D0
DC
aaa-020601
Figure 3.ꢀSPI Single byte write 3-wire SPI bus
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
single byte data write
<CSB>
<SCLK> DC
DC
<SDI> DC
R/W A14 A13 A12 A11 A10 A09 .... A1 A0 D7 D6 D5 .... D1 D0
DC
address register Reg(n)
register Reg(n) data
single byte readback
<CSB>
<SCLK> DC
<SDI> DC
DC
DC
R/W A14 A13 A12 A11 A10 A09 .... A1 A0
address register Reg(n)
<SDO> DC
D7 D6 D5 .... D1 D0
register Reg(n) data
DC
aaa-020602
Figure 4.ꢀSPI Single byte write 4-wire SPI bus
8.2.3 Power up Sequence
The BGU8822/A powers-up with the default register list content after supply voltage is
applied to the VDD(SPI) pin.
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
8.2.4 SPI control registers
Register addresses 0x00h to 0x02h and 0x0Fh are dedicated to SPI control settings.
Register 0x00h is mirror register, it will change to level HIGH if both corresponding bits
are set HIGH.
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
SPI_RST
LSB_FIRST
SPI_RST
LSB_FIRST
ADDRESS_INCREMENT
ADDRESS_INCREMENT
4WIRE_MODE
4WIRE_MODE
aaa-026524
Figure 5.ꢀ Register address 0x00h
Table 8.ꢀRegister address 0×00h
Legend: * reset value
Bits
Name
Access
Value
Description
7
SPI_RST
W
SPI reset bit. All registers are reverted to default state when bit is set
HIGH
7
6
SPI_RST
W
0*
1
Normal operation
Reset registers from address 0x02h up to 0x17h to default
states. Bit shall be HIGH together with bit [0]. Bit value
resets back to LOW level after command is executed
LSB_FIRST
R/W
Sets MSB_FIRST (default) or LSB_FIRST mode of operation
0*
MSB first mode. The data is entered with MSB first and LSB
last.
1
LSB first mode. The data is entered with LSB first and MSB
last. Bit shall be set HIGH together with bit [1]
5
4
ADDRESS_INCREMENT
R/W
R/W
Sets register address read/write order for the streaming (multi-byte)
SPI access mode
0*
Auto-decrementing register address order in the streaming
mode
1
Auto-incrementing register address order in the streaming
mode. Bit shall be set HIGH together with bit [2]
4WIRE_MODE
Switches SPI bus between 3-wire and 4-wire modes
0*
3-wire mode with <SDIO> as bidirectional input and output
pin
1
4-wire mode with <SDIO> as unidirectional input and
<SDO> as unidirectional output pins. Bit shall be set HIGH
together with bit [3]
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Bits
Name
Access
Value
Description
3
4WIRE_MODE
R/W
Switches SPI bus between 3-wire and 4-wire modes
0*
1
3-wire mode with <SDIO> as bidirectional input and output
pin
4-wire mode with <SDIO> as unidirectional input and
<SDO> as unidirectional output pins. Bit shall be set HIGH
together with bit [4]
2
ADRESS_INCREMENT
R/W
Sets register address read/write order for the streaming (multi-byte)
SPI access mode
0*
Auto-decrementing register address order in the streaming
mode
1
Auto-incrementing register address order in the streaming
mode. Bit shall be set HIGH together with bit [5]
1
0
LSB_FIRST
SPI_FIRST
R/W
Sets MSB_FIRST (default) or LSB_FIRST mode of operation
0*
MSB_FIRST mode. The data is entered with MSB first and
LSB last
1
LSB_FIRST mode. The data is entered with LSB first and
MSB last. Bit shall be set HIGH together with bit [6]
W
SPI reset bit. All registers are reverted to default state when bit is set
HIGH
0*
1
Normal operation
Resets all registers from address 0x02h up to 0x17h to
default states. Bit shall be set HIGH together with bit [7]. Bit
value resets back to LOW level after command is executed.
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
STREAMING_MODE_DISABLE
NOT_USED
NOT_USED
DOUBLE_BUFFER
aaa-026525
Figure 6.ꢀRegister address 0x01h
Table 9.ꢀRegister address 0×01h
Legend: * reset value
Bits
Name
Access
Value
Description
7
STREAMING_MODE_
DISABLE
R/W
Streaming (multi-byte) read/write access is enabled by default (level
LOW). Addresses will be auto-incremented or auto-decremented,
based on register 0x00h, bit [5] and bit [2]. Setting HIGH disables
streaming mode and switches to single-byte read/write access
0*
Streaming (multi-byte) read/write access
Single-byre read/write access
1
6
NOT_USED
R
Not used
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Bits
Name
Access
Value
Description
5
DOUBLE_BUFFER
R/W
Enables Double-buffer mode for register 0x02h
0*
Read-back from active registers
Read-back from buffer registers
1
4-0
NOT_USED
R
Not used
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
POWER_DOWN
NOT_USED
aaa-026526
Figure 7.ꢀRegister address 0x02h
Table 10.ꢀRegister address 0×02h
Legend: * reset value
Bits
7-2
Name
Access
R
Value
Not used
Description
NOT_USED
POWER_DOWN
1-0
R/W
Sets power-down mode. In power-down mode all LNAs are disabled,
DSA's are in high attenuation mode. SPI bus is accessible and fully
functional. This register is double buffered. Active value is effective
after writing register 0x0Fh, bit [0]. Read value depends on setting of
register 0x01h, bit [5]
00*
01
10
11
Normal operation
Power-down mode
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
NOT_USED
TRANSFER_BIT
aaa-026533
Figure 8.ꢀRegister address 0x0Fh
Table 11.ꢀRegister address 0×0Fh
Legend: * reset value
Bits
7-1
0
Name
Access
Value
Not used
Description
NOT_USED
TRANSFER_BIT
R
W
Transfer bit must be set HIGH to transfer the contents of the buffer
into the active register 0x02h
0*
1
No transfer
Transfer data into active registers. Bit value resets back to
LOW level after command is executed
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
8.2.5 Identification registers
Register addresses 0x03h to 0x06h, 0x0Ch and 0x0Dh are read-only registers and are
used for identification (such as vendor ID, chip ID, chip version, etc).
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
1
DEVICE_TYPE
aaa-026527
Figure 9.ꢀRegister address 0x03h
Table 12.ꢀRegister address 0×03h
Legend: * reset value
Bits
Name
Access
Value
Description
7-0
DEVICE_TYPE
R
Sets device type: RF CHIP
00000001*
Bit 7
0
6
0
5
1
4
0
3
0
2
0
1
1
0
0
CHIP_ID_L
aaa-026528
Figure 10.ꢀRegister address 0x04h
Table 13.ꢀRegister address 0×04h
Legend: * reset value
Bits
Name
Access
Value
Description
7-0
CHIP_ID_L
R
Low byte of Chip ID: 0x8822h
00100010*
Bit 7
1
6
0
5
0
4
0
3
1
2
0
1
0
0
0
CHIP_ID_H
aaa-026529
Figure 11.ꢀRegister address 0x05h
Table 14.ꢀRegister address 0×05h
Legend: * reset value
Bits
Name
Access
Value
Description
7-0
CHIP_ID_H
R
High byte of Chip ID: 0x8822h
10001000*
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Bit 7
0
6
0
5
0
4
0
3
0
2
1
1
0
0
1
CHIP_REV
aaa-026626
Figure 12.ꢀRegister address 0x06h
Table 15.ꢀRegister address 0×06h
Legend: * reset value
Bits
Name
Access
Value
Description
7-0
CHIP_REV
R
Chip Revision: 0x05h
00000101*
Bit 7
0
6
1
5
1
4
1
3
0
2
0
1
0
0
1
VENDOR_ID_L
aaa-026531
Figure 13.ꢀRegister address 0x0Ch
Table 16.ꢀRegister address 0x0Ch
Legend: * reset value
Bits
Name
Access
Value
Description
7-0
VENDOR_ID_L
R
Low byte of Vendor ID: 0x471h - NXP Semiconductors
01110001*
Bit 7
0
6
0
5
0
4
0
3
0
2
1
1
0
0
0
VENDOR_ID_H
aaa-026532
Figure 14.ꢀRegister address 0x0Dh
Table 17.ꢀRegister address 0×0Dh
Legend: * reset value
Bits
Name
Access
Value
Description
7-0
VENDOR_ID_H
R
High byte of Vendor ID: 0x471h - NXP Semiconductors
0000100*
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
8.2.6 Functional registers
Register addresses 0x10h – 0x13h, 0x16h, and 0x17h are used to set BGU8822/A
functionality when accessed in write mode and to provide status update when accessed
in read mode.
Registers 0x10h – 0x13h, 0x16h, and 0x17h are not double buffered. Transfer bit
(register 0×0Fh, bit [0]) is not needed for these registers.
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
(1)
(1)
(1)
LNA1_M_EN
LNA2_M_EN
LNA1_D_EN
(2)
(2)
LNA1_D_CURRENT
(1)
LNA2_D_EN
LNA1_M_CURRENT
aaa-026534
Figure 15.ꢀRegister address 0x10h
Table 18.ꢀRegister address 0×10h
Legend: * reset value
Bits
Name
Access
Value
Description
7
LNA1_M_EN[1]
R/W
Enables LNA1 in Main Channel
0
LNA1_M is disabled (in low current mode)
LNA1_M is enabled
1*
6
LNA2_M_EN[1]
R/W
R/W
R/W
R
Enables LNA2 in Main Channel
0
LNA2_M is disabled (in low current mode)
LNA2_M is enabled
1*
5
LNA1_D_EN[1]
Enables LNA1 in Diversity Channel
0
LNA1_D is disabled (in low current mode)
LNA1_D is enabled
1*
4
LNA2_D_EN[1]
Enables LNA2 in Diversity Channel
0
LNA2_D is disabled (in low current mode)
LNA2_D is enabled
1*
3-2
LNA1_M_CURRENT[2]
LNA1_M current monitor status
00*
10
01
11
Normal operation
N/A
Abnormal low current (min/typ/max => 9/23/33 mA)
Abnormal high current (min/typ/max => 80/100/171 mA)
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Bits
Name
Access
Value
Description
1-0
LNA1_D_CURRENT[2]
R/W
LNA1_D current monitor status
00*
10
01
11
Normal operation
N/A
Abnormal low current (min/typ/max => 9/23/33 mA)
Abnormal high current (min/typ/max => 80/100/171 mA)
[1] After reset/start-up, LNAs are enabled.
[2] Current monitor shall not be used with RF signals above +5 dBm.
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
RESERVED
DSA_M_CONTROL
RESERVED
aaa-026535
Figure 16.ꢀRegister address 0x11h
Table 19.ꢀRegister address 0×11h
Legend: * reset value
Bits
Name
Access
Value
Description
7
RESERVED
R/W
Reserved bit. Shall be kept LOW
0*
6-2
DSA_M_CONTROL
R/W
Main Channel DSA 5-bit attenuation control
00000* Minimum Attenuation, equal to IL
00001
00010
...
IL + 1 dB Attenuation
IL + 2 dB Attenuation
11111
IL + 31 dB Attenuation
1-0
RESERVED
R/W
Reserved bits. Shall be kept LOW
0*
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
RESERVED
DSA_D_CONTROL
RESERVED
aaa-026536
Figure 17.ꢀRegister address 0x12h
Table 20.ꢀRegister address 0×12h
Legend: * reset value
Bits
Name
Access
Value
Description
7
RESERVED
R/W
Reserved bit. Shall be kept LOW
0*
6-2
DSA_D_CONTROL
R/W
Diversity Channel DSA 5-bit attenuation control
00000* Minimum Attenuation, equal to IL
00001
00010
...
IL + 1 dB Attenuation
IL + 2 dB Attenuation
11111
IL + 31 dB Attenuation
1-0
RESERVED
R/W
Reserved bits. Shall be kept LOW
0*
Bit 7
0
6
0
5
1
4
0
3
0
2
0
1
0
0
0
SPDT_CTRL
SPI_LEVEL
NOT_USED
GPO_CTRL
NOT_USED
DIRECT_DSA_M
DIRECT_DSA_D
aaa-026537
Figure 18.ꢀRegister address 0x13h
Table 21.ꢀRegister address 0×13h
Legend: * reset value
Bits
Name
Access
Value
Description
7
SPDT_CTRL
R/W
SPDT control bit. Connects SW_RFC input to SW_RF1 output
(default) or to SW_RF2 output
0*
SW_RFC connected to SW_RF1
SW_RFC connected to SW_RF2
1
6
NOT_USED
R
Not used
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Bits
Name
Access
Value
Description
5
GPO_CTRL
R/W
GPO (pin 23) control bit. GPO functionality is disabled, when device is
in direct-access mode (register 0x13h bit [2] is LOW)
0
GPO LOW
GPO HIGH
1*
4-3
2
NOT_USED
R
Not used
DIRECT_DSA_D
R/W
Disables direct access for DSA_D (DSA in Diversity channel)
0*
1
Direct access is enabled. DSA_D can be toggled between IL
and prior programmed value x dB (set via register 0x17h) by
pin 23. GPO functionality is disabled.
Direct access is disabled. DSA can be set via register
0x12h.
1
0
DIRECT_DSA_M
R/W
R/W
Disables direct access for DSA_M (DSA in Main channel)
0*
Direct access is enabled. DSA_M can be toggled between
IL and prior programmed value x dB (set via register 0x16h)
by pin 9.
1
Direct access is disabled. DSA can be set via register
0x11h.
SPI_LEVEL
Sets the VOH voltage to be used by SPI
0*
1
VOH = 1.8 V
VOH = 3.3 V
Bit 7
0
6
0
5
1
4
1
3
1
2
1
1
0
0
0
RESERVED
DSA_M_TDD_ATTN
RESERVED
aaa-026538
Figure 19.ꢀRegister address 0x16h
Table 22.ꢀRegister address 0×16h
Legend: * reset value
Bits
Name
Access
Value
Description
7
RESERVED
R/W
Reserved bit. Shall be kept LOW
0*
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Bits
Name
Access
Value
Description
6-2
DSA_M_TDD_ATTN
R/W
Main channel DSA attenuation level for direct-access mode in TDD
systems. Attenuation is toggled by pin 9
00000
00001
Minimum Attenuation, equal to IL
IL + 1 dB Attenuation
01111* IL + 15 dB Attenuation
...
11111
IL + 31 dB Attenuation
1-0
RESERVED
R/W
Reserved bits. Shall be kept LOW
0*
Bit 7
0
6
0
5
1
4
1
3
1
2
1
1
0
0
0
RESERVED
DSA_D_TDD_ATTN
RESERVED
aaa-026539
Figure 20.ꢀRegister address 0x17h
Table 23.ꢀRegister address 0×17h
Legend: * reset value
Bits
Name
Access
Value
Description
7
RESERVED
R/W
Reserved bit. Shall be kept LOW
0*
6-2
DSA_D_TDD_ATTN
R/W
Diversity channel DSA attenuation level for direct-access mode in
TDD systems. Attenuation is toggled by pin 23
00000
00001
Minimum Attenuation, equal to IL
IL + 1 dB Attenuation
01111* IL + 15 dB Attenuation
...
11111
IL + 31 dB Attenuation
1-0
RESERVED
R/W
Reserved bits. Shall be kept LOW
0*
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
8.3 Device Functionality
The BGU8822/A supports both main and diversity receiver channels in both TDD and
FDD systems. It has a first stage LNA optimized for sensitivity followed by a digital step
attenuator and output stage amplifier. The first stage LNA output is routed outside the
device, so there is a possibility to use the device in different system configurations (e.g.
connect frequency selective filters in-between output of the first stage LNA and DSA
input, refer to Functional Diagram in Section 6).
Main and Diversity channels are controlled separately, via addressing different registers
in device’s memory. LNAs can be set in power-down mode to save current consumption
depending on system configuration (address 0x10h, refer to Table 18).
Attenuation levels of DSAs can be set with steps of 1 dB and total range of 31 dB.
Attenuation can be written to the address 0x11h for Main channel (Table 19) and the
address 0x12h for Diversity channel (Table 20).
To support highly integrated solutions and reduce platform costs a standalone SPDT
switch is included. Switch is controlled at address 0x13h (refer to Table 21).
All RF inputs and outputs are single-ended and matched to 50 Ω (external matching
components may be required, refer to Application information in Section 14). The
BGU8822/A is controlled via SPI bus, supporting both 3- and 4-wire configurations. Full
description of SPI interface is provided in Section 8.2. In TDD systems, the LNAs and
DSA can also be controlled via direct-access pins. The direct-access functionality is
described in Section 8.1.
BGU8822/A
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20 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
9 Limiting values
Table 24.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
VCC supply voltage
Pi(RF)CW continuous waveform RF input power
Conditions
Min Max Unit
for all supply pins
-
-
6
V
for 2 hrs all RF input pins
at SPDT ports for 2 hrs
20
30
dBm
dBm
Tstg
Tj
storage temperature
junction temperature
power dissipation
-40 +150 °C
-
-
-
-
150
1.7
1.0
0.5
°C
W
[1]
[2]
[3]
P
Tcase ≤ 105 °C
VESD
electrostatic discharge voltage
Human Body Model (HBM)
Charged Device Model (CDM)
kV
kV
[1] Case is ground solder pad.
[2] According to ANSI/ESDA/JEDEC standard JS-001-2010. For pins 2, 11 (RFIN_M, RFIN_D) limiting value is 1 kV, for all other pins limiting value is 2 kV
[3] According to JEDEC standard 22-C101B.
10 Recommended operating conditions
Table 25.ꢀCharacteristics
Symbol Parameter
Conditions
Min
4.75
-
Typ Max Unit
VCC
Z0
supply voltage
5
5.25
-
V
characteristic impedance
case temperature
50
-
Ω
Tcase
-40
+105 °C
11 Thermal characteristics
Table 26.ꢀThermal characteristics
Symbol Parameter
Conditions
Typ
Unit
[1] [2]
Rth(j-case) junction to case thermal resistance
Soldered on NXP evaluation board,
Tamb = 95 °C
29
K/W
[1] Based on simulation, Tcase = 105 °C under the mentioned conditions. Case is the center ground solder pad.
[2] Thermal resistance measured using on die thermal sensing diodes.
BGU8822/A
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Product data sheet
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21 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
12 Characteristics
Table 27.ꢀCharacteristics BGU8822/A LNA1 for Main and Diversity Channel
f = 2200 MHz; VCC = 5 V; Tamb = 25 °C; input and output 50 Ω; unless otherwise specified. All RF parameters are measured
in an application board as shown in Figure 52 with components listed in Table 33 optimized for f = 2200 MHz.
Symbol Parameter
Conditions
LNA1 Enable
Disable
Min
Typ Max Unit
ICC
supply current
-
-
54
3
64
-
mA
mA
dB
[1]
[1]
Gp
power gain
noise figure
16.3 18
0.7
17.9 19
-
NF
At room temperature
-
-
dB
PL(1dB)
output power at 1 dB gain
compression
-
dBm
IP3O
output third-order intercept point 2-tone; tone spacing = 1 MHz;
Pi = -15 dBm per tone
34
37
-
dBm
RLin
input return loss
output return loss
-
-
-
14
-
-
-
dB
dB
ns
RLout
ts(pon)
13
power-on settling time
power-off settling time
Rollett stability factor
Matched conditions; after SPI last raising clock
edge and RF amplitude output 10 % to 90 % of
steady state
925
ts(poff)
Matched conditions; after SPI last raising clock
edge and RF amplitude output 90 % to 10 % of
steady state
-
15
-
-
-
ns
-
K
up to f = 20 GHz
1
[1] Connector and Printed-Circuit Board (PCB) losses have been de-embedded for all RF parameters.
Table 28.ꢀCharacteristics BGU8822/A DSA+LNA2 for Main and Diversity
f = 2200 MHz; VCC = 5 V; Tamb = 25 °C; input and output 50 Ω; unless otherwise specified. All RF parameters are measured
in an application board as shown in Figure 52 with components listed in Table 33 optimized for f = 2200 MHz.
Symbol Parameter
Conditions
Min
Typ
57
5
Max
Unit
mA
mA
dB
ICC
supply
current
DSA + LNA2 Enable
Disable
-
67
-
-
[1]
[1]
Gp
power gain
noise figure
15.9
-
17
2.3
20
-
NF
-
dB
PL(1dB)
output power
at
17.9
-
dBm
1 dB gain
compression
IP3O
output third- 2-tone; tone spacing = 1 MHz;
34
-
37
18
-
-
dBm
dB
order
Pi = -15 dBm per tone
intercept
point
RLin
input return
loss
Over all attenuator settings
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Symbol Parameter
Conditions
Min
Typ
Max
Unit
RLout output return Over all attenuator settings
-
16
-
dB
loss
ts(pon)
power-on
Matched conditions; after SPI
-
-
925
20
-
-
ns
ns
settling time last raising clock edge and RF
amplitude output 10 % to 90 %
of steady state
ts(poff)
power-off
Matched conditions; after SPI
settling time last raising clock edge and RF
amplitude output 90 % to 10 %
of steady state
Grange
Gstep
ΔG
gain range
gain step
Digital step attenuator gain
DSA gain step
-
-
31
1
-
-
dB
dB
gain variation DSA gain variation over
attenuation setting
- (0.3 + 5 % Att) -
(0.3 + 5 % Att) dB
tresp(α)
attenuation
response
LNA enable; RF amplitude
output 10 % delta attenuation
to 90 % delta attenuation of
steady state with max.0.5 dB
overshoot
-
50
- ns
time
[1] Connector and Printed-Circuit Board (PCB) losses have been de-embedded for all RF parameters.
Table 29.ꢀCharacteristics SPDT RF switch
f = 2200 MHz; VCC = 5 V; Tamb = 25 °C; input and output 50 Ω; unless otherwise specified. All RF parameters are measured
in an application board as shown in Figure 52 with components listed in Table 33 optimized for f = 2200 MHz.
Symbol
ICC
Parameter
Conditions
Min
Typ
2.1
Max Unit
supply current
insertion loss
SPDT Supply voltage
-
-
-
-
mA
dB
[1]
αins
1.25
35
2.1
-
Pi(1dB)
input power at
dBm
1 dB gain compression
IP3i
input third-order intercept
point
2-tone; tone spacing = 1 MHz;
Pi = +5 dBm per tone
-
51
-
dBm
RLin
input return loss
port SW_RF1
port SW_RF2
port SW_RFC
-
-
-
-
14
-
-
-
-
dB
dB
dB
ns
RLout
RLout
td(QV)
output return loss
14
output return loss
15
data output valid delay time
From last, SPI data bit is clocked in to
10 % of RF output steady state (pin 28),
ON state
725
From last, SPI data bit is clocked in to
10 % of RF output steady state (pin 28),
OFF state
-
-
50
42
-
-
ns
ISL
isolation
SPDT port
dB
[1] Connector and Printed-Circuit Board (PCB) losses have been de-embedded for all RF parameters.
BGU8822/A
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23 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Table 30.ꢀCharacteristics BGU8822/A port isolation of IC
f = 2200 MHz; VCC = 5 V; Tamb = 25 °C; input and output 50 Ω; unless otherwise specified. All RF parameters are measured
in an application board as shown in Figure 52 with components listed in Table 33 optimized for f = 2200 MHz.
Symbol
Parameter
Conditions
Min Typ Max Unit
αisol(ch-ch)
isolation between channels
Isolation from LNA1 output main (pin 42) to
DSAM (pin 39) input in the main channel.
Likewise for diversity (pin 15) to (pin 18)
-
-
60
81
-
dB
Isolation for LNA2D (pin 32) output to
LNA1M(pin 9) input in the cross channel.
Likewise pin(24) to pin (2)
-
dB
Isolation between main and diversity channels at -
input (pin 2 and pin 9)
79
48
-
-
dB
dB
Isolation between LNA2 main and diversity
output to SW_RF ports
-
Table 31.ꢀCharacteristics BGU8822/A logical inputs/outputs
VDD = 5 V; Typical values at Tamb = 25 °C; Output load 30 pF.
Symbol Parameter
Conditions
Min
4.75
-
Typ
Max Unit
VDD(SPI) SPI supply voltage
5
5.25
10
V
IDD(SPI)
VIL
SPI supply current
pin 34
3.2
-
mA
V
LOW-level input voltage
HIGH-level input voltage
-0.3
1.2
2.6
-
0.4
3.6
3.6
2.75
0.4
VIH
1.8 V mode
1.8
3.3
-
V
3.3 V mode
V
for pin 24 and 32
V
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
SPI (SDO, SDIO, and GPO); For all digital
pins
0
-
V
SPI (SDO, SDIO, and GPO); For all digital
pins and 3.3 V tolerant
1.4
1.8
2.1
V
programmable by register 0×13h bit [0]"0" =
1.8 V default"1" = 3.3 V
IIL
LOW-level input current
HIGH-level input current
LOW-level output current
VIL= 0 V
-150
-150
-
-
-
150
150
-
μA
μA
mA
IIH
IOL
VIH= 1.8 V
for all digital output pins (incl. GPO); Current +4
sourcing from 1.8 V
IOH
HIGH-level output current
output leakage current
for all digital output pins (incl. GPO); Current -
sinking to ground
-
-
-4
mA
μA
ILO
3-state output leakage for all logic levels
-87
30
BGU8822/A
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NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Table 32.ꢀCharacteristics BGU8822/A SPI timing
VDD = 5 V; Typical values at Tamb = 25 °C; Output load 30 pF. Guaranteed by design.
Symbol Parameter
Conditions
Min Typ Max Unit
tsu(SDIO) SDIO set-up time
Serial data IO setup to serial CLK rising
edge setup time
-
5
-
ns
th(SDIO)
SDIO hold time
Serial CLK rising edge to serial data IO
hold time
-
3
-
ns
tSCLKH
tSCLKL
ts
SCLK HIGH time
SCLK LOW time
settling time
Logic "High" time of Serial SPI clock
Logic "Low" time of Serial SPI clock
-
-
-
27
29
4.1
-
-
-
ns
ns
ns
CSB falling edge to serial CLK rising edge
setup time
-
-
3.0
16
-
-
ns
ns
td(DV)
data input valid delay time
clock period
Serial CLK falling edge to validate data in
SDIO/SDO time: To VIH, VIL or 3-state level
[1]
Tclk
SPI SCLK rising edge to rising edge at
write mode
40
-
-
ns
[1] tdv: in case of slave writes to master Tclk 60 ns max.
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
25 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
13 Graphics
All plots are created based on the measurements of a typical sample.
13.1 LNA1 @ primary frequencies
aaa-033847
aaa-033846
25
23
21
19
17
15
0
G
RL
in
(dB)
p
(dB)
-7
(1)
(2)
(3)
(1)
(2)
(3)
-14
-21
-28
-35
1.4
1.6
1.8
2.0
2.2
2.4
2.6
1.4
1.6
1.8
2.0
2.2
2.4
2.6
f (GHz)
f (GHz)
VDD= 5 V; Matched for 1.4 GHz - 2.2 GHz
(1) Tamb= -40 °C
VDD= 5 V; Matched for 1.4 GHz - 2.2 GHz
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
(3) Tamb= +95 °C
Figure 21.ꢀLNA1_M&D Power gain as a function of
frequency, typical values
Figure 22.ꢀLNA1_M&D Input return loss as a function of
frequency, typical values
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
26 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
aaa-033845
aaa-033765
0
40
26
12
-2
RL
(dB)
S
par
(dB)
out
-7
-14
-21
-28
-35
(3)
(2)
(1)
S21
S11
S22
-16
-30
1.4
1.6
1.8
2.0
2.2
2.4
2.6
0
1
2
3
4
5
f (GHz)
f (GHz)
VDD= 5 V; Matched for 1.4 GHz - 2.2 GHz
(1) Tamb= -40 °C
VDD= 5 V; Tamb= 25 °C; Matched for 1.4 GHz - 2.2 GHz
(2) Tamb= +25 °C
(3) Tamb= +95 °C
Figure 23.ꢀLNA1_M&D output return loss as function of Figure 24.ꢀLNA1_M&D S-parameters as a function of
frequency, typical values
frequency, typical values
aaa-033766
aaa-033841
5
10
25
K
P
L(1dB)
(dBm)
23
4
10
(1)
(2)
(3)
3
10
21
19
17
15
(1)
(2)
(3)
2
10
10
1
0
4
8
12
16
f (GHz)
20
1
1.25 1.5 1.75
2
2.25 2.5 2.75
f (GHz)
3
VDD= 5 V; Tamb= 25 °C; Matched for 1.4 GHz - 2.2 GHz
(1) Tamb= -40 °C
VDD= 5 V; Tamb= 25 °C; Matched for 1.4 GHz - 2.2 GHz
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
(3) Tamb= +95 °C
Figure 25.ꢀLNA1 _M&D Rollett stability factor as a
function of frequency, typical values
Figure 26.ꢀLNA1_M&D Output 1 dB compression point,
typical values
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
27 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
aaa-033839
45
aaa-033769
IP3
(dBm)
O
2.5
NF
(dB)
42
2.0
(1)
(2)
39
36
33
30
1.5
(3)
(3)
1.0
(2)
0.5
(1)
1.0
1.4
1.8
2.2
2.6
f (GHz)
3.0
0.0
1.0
1.4
1.8
2.2
2.6
f (GHz)
3.0
VDD= 5 V; Matched for 1.4 GHz - 2.2 GHz; Output tone
power +5 dBm; Delta frequency 1 MHz
VDD= 5 V; Matched for 1.4 GHz - 2.2 GHz
(1) Tamb= -40 °C
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
Figure 27.ꢀLNA1_M&D Output third order intercept
point, typical values
Figure 28.ꢀLNA1_M&D Noise figure as a function of
frequency, typical values
13.2 LNA 1 for extended frequency range
The BGU8822/A is being characterized for the primary frequencies 1.4-2.2GHz with the
use of the application circuit as shown in Figure 52 and the component values given in
Table 33.
To improve the performance of LNA1 in noise figure as well as input return loss for
the extended frequency range (2.2 - 2.7 GHz) the LNA input needs different matching
components. For, both LNA1_M and LNA1_D capacitor C12 and C22 must be removed.
The inductors L11 and L21 should be changed to value 1.3 nH of the LQW15 series. So
input matching circuit looks like.
C11/C21
LNA1_M/D
L11/L21
RFin_M/D
aaa-025025
Figure 29.ꢀInput circuit
Figure 30 to Figure 36 shows the performance with this adapted matching circuit.
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
28 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
aaa-033731
aaa-033770
20
0
G
RL
in
p
(dB)
(dB)
19
18
17
16
15
-7
-14
-21
-28
-35
(1)
(2)
(3)
(1)
(2)
(3)
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
f (GHz)
f (GHz)
VDD= 5 V; Matched for 2.2 GHz - 2.7 GHz
(1) Tamb= -40 °C
VDD= 5 V; Matched for 2.2 GHz - 2.7 GHz
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
(3) Tamb= +95 °C
Figure 30.ꢀLNA1_M&D Power gain as a function of
frequency, typical values
Figure 31.ꢀLNA1_M&D Input return loss as a function of
frequency, typical values
aaa-033771
aaa-033733
0
40
RL
S
par
out
(dB)
(dB)
-8
26
12
-2
-16
-24
-32
-40
S11
S21
S22
-16
-30
(1)
(2)
(3)
2.1
2.2
2.3
2.4
2.5
2.6
2.7
f (GHz)
2.8
0
1
2
3
4
5
f (GHz)
VDD= 5 V; Matched for 2.2 GHz - 2.7 GHz
(1) Tamb= -40 °C
VDD= 5 V; Tamb= 25 °C; Matched for 2.2 GHz - 2.7 GHz
(2) Tamb= +25 °C
(3) Tamb= +95 °C
Figure 32.ꢀLNA1_M&D Output return loss as a function Figure 33.ꢀLNA1_M&D S-parameters as a function of
of frequency, typical values
frequency, typical values
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
29 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
aaa-033773
45.0
aaa-033772
IP3
(dBm)
O
25
P
L(1dB)
42.5
(dBm)
23
40.0
37.5
35.0
32.5
30.0
21
19
17
15
(1)
(1)
(2)
(3)
(2)
(3)
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
f (GHz)
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
f (GHz)
VDD= 5 V; Matched for 2.2 GHz - 2.7 GHz. Output tone
power +5 dBm; Delta frequency 1 MHz
VDD= 5 V; Matched for 2.2 GHz - 2.7 GHz
(1) Tamb= -40 °C
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
Figure 34.ꢀLNA1_M&D Output 1 dB compression point, Figure 35.ꢀLNA1_M&D Output third order intercept
typical values
point, typical values
aaa-033774
2.0
1.5
1.0
0.5
0.0
NF
(dB)
(3)
(2)
(1)
2.0
2.2
2.4
2.6
2.8
3.0
f (GHz)
VDD= 5 V; Matched for 2.2 GHz - 2.7 GHz range
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
Figure 36.ꢀLNA1_M&D Noise figure as a function of frequency, typical values
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
30 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
13.3 DSA + LNA2 @ primary and extended frequencies
aaa-033775
25
22
19
16
13
10
G
p
(dB)
(1)
(2)
(3)
1.4
1.6
1.8
2.0
2.2
2.4
f (GHz)
2.6
VDD= 5 V; minimum attenuation
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
Figure 37.ꢀDSA+LNA2_M&D Power gain as a function of frequency, typical values
aaa-033776
aaa-033835
0
0
RL
RL
out
in
(dB)
(dB)
-7
-7
-14
-21
-28
-35
-14
-21
-28
-35
(1)
(2)
(3)
(1)
(2)
(3)
1.4
1.6
1.8
2.0
2.2
2.4
f (GHz)
2.6
1.4
1.6
1.8
2.0
2.2
2.4
f (GHz)
2.6
VDD= 5 V; minimum attenuation
(1) Tamb= -40 °C
VDD= 5 V; minimum attenuation
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
(3) Tamb= +95 °C
Figure 38.ꢀDSA+LNA2_M&D Input return loss as a
function of frequency, typical values
Figure 39.ꢀDSA+LNA2_M&D Output return loss as a
function of frequency, typical values
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
31 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
aaa-033778
aaa-033779
5
4
3
2
40
10
10
10
10
S
K
par
(dB)
26
12
-2
S21
S11
S22
(1)
(2)
(3)
-16
-30
10
1
0
1
2
3
4
5
0
4
8
12
16
f (GHz)
20
f (GHz)
VDD= 5 V; Tamb= 25 °C; minimum attenuation
VDD= 5 V; minimum attenuation
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
Figure 40.ꢀDSA+LNA2_M&D S-parameters as a function Figure 41.ꢀDSA+LNA2_M&D Rollett stability factor as a
of frequency; typical values
function of frequency; typical values
aaa-033780
aaa-033781
25
45.0
P
L(1dB)
IP3
(dBm)
O
(dBm)
42.5
23
40.0
37.5
35.0
32.5
30.0
(1)
21
19
17
15
(1)
(2)
(3)
(2)
(3)
1
1.4
1.8
2.2
2.6
f (GHz)
3
1
1.4
1.8
2.2
2.6
f (GHz)
3
VDD= 5 V; minimum attenuation
(1) Tamb= -40 °C
VDD= 5 V; Output tone power +5 dBm; Delta frequency
1 MHz; minimum attenuation
(2) Tamb= +25 °C
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
(3) Tamb= +95 °C
Figure 42.ꢀDSA+LNA2_M&D Output 1 dB compression
point; typical values
Figure 43.ꢀDSA+LNA2_M&D Output third order intercept
point; typical values
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
32 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
aaa-033782
aaa-033783
5
NF
(dB)
2
1
ΔG
(dB)
4
3
2
1
0
(3)
0
(2)
(1)
(1)
(2)
(3)
-1
-2
1
1.4
1.8
2.2
2.6
f (GHz)
3
0
5
10
15
20
25
30
35
Attenuation (dB)
VDD= 5 V; minimum attenuation
(1) Tamb= -40 °C
VDD= 5 V
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
Figure 44.ꢀDSA+LNA2_M&D Noise figure as a function
of frequency; typical values
Figure 45.ꢀDSA+LNA2_M&D DSA gain variation versus
attenuation step
13.4 SPDT @ primary and extended frequencies
aaa-033785
0
-1
-2
-3
-4
-5
aaa-033784
α
(dB)
ins
-60
ISL
(dB)
-65
-70
-75
(1)
(2)
(3)
(1) (2) (3)
-80
-85
-90
1.4
1.6
1.8
2.0
2.2
2.4
2.6
f (GHz)
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
f (GHz)
VDD= 5 V
VDD= 5 V
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
Figure 47.ꢀInsertion loss SWRF1/2 to SWRFC as
function of frequency, typical values
Figure 46.ꢀRFin_M to RFin_D channel isolation
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
33 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
aaa-033786
aaa-033787
0
S11
(dB)
0
S11
(dB)
-7
-14
-21
-28
-35
-7
-14
-21
-28
-35
(1)
(2)
(3)
(1)
(2)
(3)
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
f (GHz)
f (GHz)
VDD= 5 V
VDD= 5 V
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
Figure 48.ꢀS11 of SWRFC when switched to SWRF1/2 as Figure 49.ꢀS11 of SWRF1/2 when switched to SWRFC as
function of frequency, typical values
function of frequency, typical values
aaa-033789
aaa-033790
-40
ISL
33
P
(1)
L(1dB)
(dB)
(dBm)
-42
31
-44
(1)
(2)
(2)
(3)
29
27
25
-46
(3)
-48
-50
1.4
1.6
1.8
2.0
2.2
2.4
f (GHz)
2.6
1.2
1.4
1.6
1.8
2.0
f (GHz)
2.2
VDD= 5 V
VDD= 5 V
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
(1) Tamb= -40 °C
(2) Tamb= +25 °C
(3) Tamb= +95 °C
Figure 50.ꢀSPDT isolation SWRF1 to SWRF2 as function Figure 51.ꢀSPDT 1 dB compression point as function of
of frequency, typical values
frequency, typical values
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
34 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
14 Application information
R701, 0 Ω
X3
VDD1_M
VDD2_M
R601, 0 Ω
R501, 0 Ω
R401, 0 Ω
R301, 0 Ω
R201, 0 Ω
1
3
5
7
9
11
13
15
17
2
4
6
8
10
12
14
16
18
VDD_SPI
VDD_SPDT
VDD2_D
J11
J10
J9
C111
C101
C91
390 pF
390 pF
390 pF
VDD1_D
C705
1 µF
C605
1 µF
C505
1 µF
C405
1 µF
C305
1 µF
C205
1 µF
L111
XnH
L91
XnH
VDD1_M
VDD2_M
C112
1 nF
C102
XnF
C92
1 nF
L601
VDD_SPI
10 nH
L101
XnH
C601
1 nF
C602
100 pF
C603
10 nF
C604
10 pF
2
VDD2_M
JP1
1
L701
L501
10 nH
C704
10 pF
C703
10 nF
C702
100 pF
C701
1 nF
10 nH
C501
C502
100 pF
C503
10 nF
C504
10 pF
R910
2.2 kΩ
VDD1_M
VDD_SPI
1 nF
VLH_DSA_dir
VDD_RST
L401
R911
1.1 kΩ
10 nH
C401
1 nF
C402
100 pF
C403
10 nF
C404
10 pF
VDD_SPDT
R912
3.3 kΩ
J15
SMB
U1
C903
10 pF
J14
SMB
44 43 42 41 40 39 38 37 36 35
GND
RFIN_M
GND
VDD_SPI
1
2
3
4
5
6
7
8
9
34
33
32
31
30
29
28
27
26
25
24
23
C11
L11
VDD_SPDT
Disable_M
SW_RF2
GND
J1
J13
SMB
XnH
390 pF
TP3 TP4
C12
XnF
C81
BGU882x
GND
J12
SMB
TP1
1
TP2
X1
J8
J7
J6
1
3
5
7
9
2
1
1
1
SCLK
CSB
390 pF
1
3
5
7
9
2
4
6
8
X2
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
4
GND
VDD_RST
TLMS1000-GS08
D1
VDD_RST
C71
6
SDIO
SDO
SW_RFC
GND
R904
1
2
R901
82 kΩ
8
390 pF
680 Ω
VLH_DSA_dir
DSA_dir_M
TP6
VLH_DSA_dir
DSA_dir_M
C801
10 pF
C802
10 pF
C803
10 pF
C804
10 pF
10
DSA_dir_M
GND
GND
VDD_RST
10
Vcc
6
DSA_dir_M
L21
C904
10 pF
C61
1
1
SW_RF1
Disable_D
D2
SW1
5
2
Y
A
1
10
con 2 x 5
C21
390 pF
R903
4.3 kΩ
RFIN_D
GND
390 pF
U2-1
74LVC2G14GM
KSR223GLFG
J2
11
12
BAS16L
R902
XnH
C22
XnF
DSA_dir_D/GPO
GND
TP5
13 14 15 16 17 18 19 20 21 22
C901
10 pF
C902
10 pF
18 kΩ
C105
1µF
TEMPSENSE
L301
L201
10 nH
10 nH
C204
10 pF
C203
10 nF
C202
100 pF
C201
1 nF
C301
1 nF
C302
100 pF
C303
10 nF
C304
10 pF
VDD2_D
VDD1_D
L41
XnH
C42
L31
L51
XnH
C51
FH1
FH2
FH3
FH4
1
1
1
1
XnH
XnH
C41
390 pF
C32
1 nF
C31
390 pF
C52
1 nF
VDD1_D
VDD2_D
390 pF
J3
J4
J5
aaa-022719
Figure 52.ꢀBGU8822/A application diagram.
Table 33.ꢀList of components
Component
C12, C22
Designation
Value
Manufacturer
Murata
Quantity
GJM1555C1HR70WB01D +/- 0.05 pF 0.7 pF
GJM1555C1HR60WB01D +/- 0.05 pF 0.6 pF
2
C42, C102,
Murata
2
C11, C21, C31, C41, C51, C61, C71,
C81, C91, C101, C111
GRM1555C1E391JA01
390 pF
Murata
11
C105, C205, C305, C405, C505, C605, GRM188R71E105KA
C705
1 μF
Murata
Murata
7
C32, C52, C92, C112, C201, C301,
C401, C501, C601, C701
GRM1555CH101JA01D
1 nF
10
C202, C302, C402, C502, C602, C702 GRM155R71H102KA01D
C203, C303, C403, C503, C603, C703 GRM155R71H103KA88D
100 pF
10 nF
10 pF
Murata
Murata
Murata
6
6
C204, C304, C404, C504, C604, C704, GRM1555C1H100JA01D
C801, C802, C803, C804, C901, C902
13
D1
TLMS1000-GS08
1328308 FARNELL
1
BGU8822/A
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Product data sheet
Rev. 6 — 15 April 2020
35 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Component
Designation
Value
BAS16L NXP
FARNELL
Manufacturer
Quantity
D1
BAS16L
1
J1, J2, J3, J4, J5, J6, J7, J8, J9, J10,
J11
Connector SMA142-0701-841
11
L11, L21
LQP15MN1N8W02D +/- 0.1 nH
LQW15AN1N5B00D +/- 0.1 nH
LQG15HH××NG02 2 %
LQW15AN10NJ00
1.8 nH
1.5 nH
15 nH
10 nH
680 R
0 R
Murata
Murata
Murata
Murata
Murata
4
2
4
2
6
1
6
1
1
1
1
1
1
1
1
1
L41, L101
L31, L51, L91, L111
L201, L301, L401, L501, L601, L701
R904
402
R201, R301, R401, R501, R601, R701 402
R901
R902
R903
R910
R911
R912
SW1
U1
402
82k
402
18k
402
4k3
402
2.2k
402
1.1k
402
3.3k
KSR223GLFG
BGU8822/A
74LVC2G14
2320064 FARNELL
NXP
U2
GM
NXP
X1
WIRE-BOARD CONNECTOR,
HEADER 10POS, 2MM
1835819 FARNELL
X2, X3
TE CONNECTIVITY /
AMP-4-103322-2-BARETTE
SECABLE DOUBLE
1098460 FARNELL
1
1
TP1, TP2, TP3, TP4, TP5, TP6
3 points HEADER, VERTICAL, pitch
2.54 mm
5217805 FARNELL
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
36 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Table 34.ꢀTypical performance BGU8822/A LNA1_M/D application board VCC = 5 V
All RF parameters are measured at the application board as shown in Figure 52 with the components as listed in Table 33
optimized for: f = 1700 MHz to 2200 MHz, VCC = 5 V, Tamb = 25 °C.
Symbol
Parameter
Conditions
Frequency
Unit
1400 1500 1700 1850 1900 1950 2000 2200 MHz
22.2 21.6 20.6 19.9 19.6 19.4 19.1 17.9 dB
13.0 13.3 15.8 23.2 25.3 29.0 23.2 14.3 dB
21.4 24.5 33.0 20.2 18.2 16.6 15.4 13.4 dB
19.6 19.5 19.2 19.1 19.7 18.7 19.0 19.1 dBm
[1]
G
gain
RLin
RLout
PL(1dB)
input return loss
output return loss
[1]
output power at 1 dB
gain compression
[1]
[2]
IP3O
NF
output third-order
intercept point
Δf = 1 MHz
36.7 36.8 36.7 36.5 36.7 36.4 36.7 37.1 dBm
0.54 0.56 0.55 0.62 0.63 0.66 0.67 0.70 dB
[1]
noise figure
[1] Connector and board losses have been de-embedded.
[2] 2-Tone; tone spacing = 1 MHz; Po = 5 dBm per tone
Table 35.ꢀTypical performance BGU8822/A DSA+LNA2_M/D application board VCC = 5 V
All RF parameters are measured at the application board as shown in Figure 52 with the components as listed in Table 33
optimized for: f = 1700 MHz to 2200 MHz, VCC = 5 V, Tamb = 25 °C. DSA in minimum attenuation.
Symbol
Parameter
Conditions
Frequency
Unit
1400 1500 1700 1850 1900 1950 2000 2200 MHz
21.2 20.5 19.4 18.7 18.5 18.2 18.0 18.0 dB
24.0 23.3 21.2 23.3 22.6 23.8 24.5 24.5 dB
23.0 24.7 23.3 21.8 21.1 20.4 19.8 19.8 dB
19.9 20.0 19.5 20.1 20.1 19.8 20.5 20.5 dBm
[1]
[1]
G
gain
RLin
RLout
PL(1dB)
input return loss
output return loss
output power at
1 dB gain compression
[1]
[2]
IP3O
NF
output third-order
intercept point
Δf = 1 MHz
36.6 36.6 36.9 36.9 37.1 36.9 37.2 37.2 dBm
[1]
noise figure
1.8
1.8
1.9
2.0
2.0
2.1
2.1
2.1
dB
[1] Connector and board losses have been de-embedded.
[2] 2-Tone; tone spacing = 1 MHz; Po = 5 dBm per tone
BGU8822/A
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Product data sheet
Rev. 6 — 15 April 2020
37 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Table 36.ꢀTypical performance BGU8822/A SPDT application board VCC = 5 V
All RF parameters are measured at the application board as shown in Figure 52 with the components as listed in Table 33.
Symbol
Parameter
Conditions
Frequency
Unit
Switch position
1400 1500 1700 2200 MHz
[1]
[1] [2]
[1] [3]
[1] [4]
[1] [5]
[1] [6]
[1] [7]
[1]
αins
insertion loss
SWRF1/2 to SWRFC
SW_RF1 to SW_RFC
SW_RF2 to SW_RFC
SW_RF1/2 to SW_RFC
SW_RF1 to SW_RFC
SW_RF1 to SW_RFC
SW_RF2 to SW_RFC
1.0
1.10 1.15 1.24 dB
RLin
input return loss
19.1 17.3 16.3 14.0 dB
19.7 17.6 16.5 13.6 dB
22.2 17.3 16.3 15.2 dB
44.5 43.7 42.4 41.0 dB
54.5 55.0 57.7 53.8 dB
45.4 44.9 44.8 44.2 dB
RLout
ISL
output return loss
isolation
Pi(1dB)
input power at
34.0
36.3 35.0 dBm
1 dB gain compression
[8]
IP3i
input third-order intercept point
Δf = 1 MHz
55.6
55.7 51.0 dBm
[1] Connector and board losses have been de-embedded.
[2] input is SW_RF1.
[3] input is SW_RF2.
[4] output is SW_RFC.
[5] Isolation from SW_RF2 to SW_RFC.
[6] Isolation from SW_RF1 to SW_RF2.
[7] Isolation from SW_RF1 to SW_RFC.
[8] 2-Tone; tone spacing = 1 MHz; Po = 5 dBm per tone
BGU8822/A
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Product data sheet
Rev. 6 — 15 April 2020
38 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
15 Package outline
HVLGA44: plastic thermal enhanced very thin profile land grid array package; 44 terminals;
SOT1431-1
B
A
D
terminal 1
index area
A
1
E
A
detail X
e
e
2
1
b
B
A
v
w
C
C
b
C
1
e
1/2 e
y
1
y
C
L
1
L
L
2
13
23
12
24
1/2 e
e
3
e
4
E
h
e
1
34
44
35
terminal 1
index area
X
D
h
0
3 mm
scale
Dimensions (mm are the original dimensions)
Unit
A
A
b
b
D
D
h
E
E
e
e
e
e
e
4
L
L
L
2
v
w
y
y
1
1
1
h
1
2
3
1
max 0.82 0.50 0.25 0.35 5.1 3.75 5.1 3.75
0.40 0.15 0.35
mm nom
0.4 3.6 4.5 3.6 4.5 0.35 0.10 0.30 0.15 0.05 0.08 0.1
0.30 0.05 0.25
0.72 0.45 0.20 0.30 5.0 3.70 5.0 3.70
0.62 0.40 0.15 0.25 4.9 3.65 4.9 3.65
min
sot1431-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
- - -
JEITA
16-06-28
16-08-12
SOT1431-1
Figure 53.ꢀHVLGA44: plastic thermal enhanced very thin profile land grid array package; no leads; 44 terminals
BGU8822/A
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 6 — 15 April 2020
39 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
16 Abbreviations
Table 37.ꢀAbbreviations
Acronym
CDMA
ESD
Description
code division multiple-access
electrostatic discharge
FDD
frequency-division duplexing
global system for mobile communication
low-noise amplifier
GSM
LNA
LTE
long-term evolution
RF
radio frequency
TDD
time-division duplexing
W-CDMA
wideband code division multiple-access
17 Revision history
Table 38.ꢀRevision history
Document ID
BGU8822/A v.6
modification
Release date
20200415
Data sheet status
Change notice
Supersedes
Product data sheet
-
BGU8822/A v.5
• Security status changed from Company confidential to Public
BGU8822/A v.5
modification
20200409
• changed the R/W into R/
• corrected the title for figure 4
20200218 Product data sheet
Product data sheet
-
BGU8822/A v.4
BGU8822/A v.3
W for both figures in the Programming registers topic
BGU8822/Av.4
modification
-
• changed access value for bit 4-7 to R/W in functional register address 0x 10h
• removed read-back value is always "0"
• adapted the first footnote to: After reset/start-up LNAs are enabled
• corrected conditions on ts(pon), and ts(poff) in Characteristics BGU8822/A LNA1 for Main and
Diversity Channel
BGU8822/A v.3
modification
20190412
• adapted and repaired the graphics
• Inserted orderable part number in Ordering information table
Product data sheet
-
BGU8822/A v.2.1
BGU8822/A v.2.1
modification
20181205
• adapted register address 0x06h
20181129 Product data sheet
Product data sheet
-
BGU8822/A v.2
BGU8822/A v.2
modification
-
BGU8822 v.1
-
• added /A to the name of the product because of updated version
20170223 Product data sheet
BGU8822 v.1
-
BGU8822/A
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Rev. 6 — 15 April 2020
40 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
18 Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
18.2 Definitions
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
BGU8822/A
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Product data sheet
Rev. 6 — 15 April 2020
41 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
18.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
BGU8822/A
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Product data sheet
Rev. 6 — 15 April 2020
42 / 43
NXP Semiconductors
BGU8822/A
Dual channel low-noise high linearity amplifier with DSA and SPDT
Contents
1
2
General description ............................................ 1
Features and benefits .........................................1
3
4
5
6
Applications .........................................................2
Quick reference data .......................................... 2
Ordering information .......................................... 3
Functional diagram .............................................3
Pinning information ............................................ 4
Pinning ...............................................................4
Pin description ...................................................4
Functional description ........................................6
Direct-Access Functionality for Main and
7
7.1
7.2
8
8.1
Diversity Channels in TDD Systems ..................6
Direct Disable mode ..........................................6
Direct DSA Attenuation mode ............................6
Serial Peripheral interface (SPI) Bus .................7
Hardware Interface description ..........................8
Programming registers ...................................... 8
Power up Sequence ..........................................9
SPI control registers ........................................ 10
Identification registers ......................................13
Functional registers ......................................... 15
Device Functionality .........................................20
Limiting values ..................................................21
Recommended operating conditions .............. 21
Thermal characteristics ....................................21
Characteristics .................................................. 22
Graphics .............................................................26
LNA1 @ primary frequencies .......................... 26
LNA 1 for extended frequency range ...............28
DSA + LNA2 @ primary and extended
8.1.1
8.1.2
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
9
10
11
12
13
13.1
13.2
13.3
frequencies ...................................................... 31
SPDT @ primary and extended frequencies ....33
Application information ....................................35
Package outline .................................................39
Abbreviations .................................................... 40
Revision history ................................................ 40
Legal information ..............................................41
13.4
14
15
16
17
18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2020.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 April 2020
Document identifier: BGU8822/A
Document number:
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