BH161543DL [NXP]
16-bit latched transceiver with dual enable and master reset 3-State; 16位锁存收发器与双能和主复位三态
| 型号： | BH161543DL |
| 厂家： | 
NXP |
| 描述： | 16-bit latched transceiver with dual enable and master reset 3-State |
| 文件： | 总12页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ABT161543
74ABTH161543
16-bit latched transceiver with
dual enable and master reset (3-State)
Product specification
1998 Feb 27
Supersedes data of 1995 Sep 18
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable
and master reset (3-State)
74ABT161543
74ABTH161543
FEATURES
DESCRIPTION
The 74ABT161543 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
• Two 8-bit octal transceivers with D-type latch
• Live insertion/extraction permitted
• Power-up 3-State
The 74ABT161543 16-bit registered transceiver contains two sets
of D-type latches for temporary storage of data flowing in either
direction. Separate Latch Enable (nLEAB, nLEBA) and Output
Enable (nOEAB, nOEBA) inputs are provided for each register to
permit independent control of data transfer in either direction. Master
reset (MR) clears all registers simultaneously and sets them Low.
The outputs are guaranteed to sink 64mA.
• Power-up reset
• Multiple V and GND pins minimize switching noise
CC
• Back-to-back registers for storage
• Separate controls for data flow in each direction
• 74ABTH161543 incorporates Bus hold data inputs which eliminate
the need for external pull-up resistors to hold unused inputs
Two options are available, 74ABT161543 which does not have the
Bus hold feature and 74ABTH161543 which inorporates the Bus
hold feature.
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
• Same function as ABT16543 except for additional Master Reset
control pins
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
nAx to nBx
2.5
2.2
PLH
PHL
C = 50pF; V = 5V
ns
L
CC
C
Input capacitance
I/O capacitance
V = 0V or V
CC
3
7
pF
pF
IN
I
C
V
O
= 0V or V
3-State
I/O
CC;
I
Outputs disabled; V = 5.5V
500
9
µA
mA
CCZ
CC
Quiescent supply current
I
Outputs low; V = 5.5V
CC
CCL
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
BT161543DL
DRAWING NUMBER
SOT371-1
56-pin plastic SSOP Type III
56-pin plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
BT161543DGG
SOT364-1
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
SOT371-1
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT161543 DL
74ABT161543 DGG
74ABTH161543 DL
74ABTH161543 DGG
BT161543 DL
BT161543 DGG
BH161543 DL
BH161543 DGG
SOT364-1
SOT371-1
SOT364-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
1A0 – 1A7,
2A0 – 2A7
Data inputs/outputs
Data inputs/outputs
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40,38, 37, 36, 34, 33
1B0 – 1B7,
2B0 – 2B7
1, 56
28, 29
1OEAB, 1OEBA,
2OEAB, 2OEBA
A to B / B to A Output Enable inputs (active-Low)
A to B / B to A Enable inputs (active-Low)
3, 54
26, 31
1EAB, 1EBA,
2EAB, 2EBA
2, 55
27, 30
1LEAB, 1LEBA,
2LEAB, 2LEBA
A to B / B to A Latch Enable inputs (active-Low)
4, 25
MRab, MRba
GND
Master reset
11, 18, 32, 39, 46, 53
7, 22, 35, 50
Ground (0V)
V
CC
Positive supply voltage
2
1998 Feb 27
853-1798 19026
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable
and master reset (3-State)
74ABT161543
74ABTH161543
LOGIC SYMBOL (IEEE/IEC)
PIN CONFIGURATION
1OEAB
1LEAB
1EAB
MRab
1A0
1
2
3
4
5
6
7
8
9
56 1OEBA
55 1LEBA
54 1EBA
53 GND
52 1B0
4
MRab
R6/R12
2EN4
1
1OEAB
3
2
1EAB
G2
1LEAB
2C6
28
26
2OEAB
2EAB
8EN10
G8
1A1
51 1B1
50
V
V
CC
CC
27
25
2LEAB
MRba
8C12
1A2
1A3
49 1B2
48 1B3
47 1B4
46 GND
45 1B5
44 1B6
43 1B7
42 2B0
41 2B1
40 2B2
39 GND
38 2B3
37 2B4
36 2B5
R5/R11
56
54
1A4 10
GND 11
1A5 12
1A6 13
1A7 14
2A0 15
2A1 16
2A2 17
GND 18
2A3 19
2A4 20
2A5 21
1OEBA
1EBA
1EN3
G1
55
29
1LEBA
2OEBA
1C5
7EN9
31
30
2EBA
G7
2LEBA
7C11
5
52
3
1A0
1B0
5D
6D
4
6
51
49
48
47
45
1A1
1A2
1A3
1A4
1A5
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
8
9
10
12
22
35
V
V
CC
CC
2A6 23
2A7 24
34 2B6
13
14
15
44
43
42
1A6
1A7
2A0
33 2B7
MRba 25
2EAB 26
2LEAB 27
2OEAB 28
32 GND
31 2EBA
30 2LEBA
29 2OEBA
9
11D
10
12D
16
17
19
41
40
38
2A1
2A2
2A3
2B1
2B2
2B3
SH00061
20
21
37
36
2A4
2A5
2B4
2B5
23
24
34
33
2A6
2A7
2B6
2B7
SH00060
3
1998 Feb 27
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable
and master reset (3-State)
74ABT161543
74ABTH161543
LOGIC SYMBOL
FUNCTIONAL DESCRIPTION
The 74ABT161543 contains two sets of eight D-type latches, with
separate control pins for each set. Using data flow from A to B as an
example, when the A-to-B Enable (nEAB) input and the A-to-B Latch
Enable (nLEAB) input are Low the A-to-B path is transparent.
A subsequent Low-to-High transition of the nLEAB signal puts the A
data into the latches where it is stored and the B outputs no longer
change with the A inputs. With EAB and nOEAB both Low, the
3-State B output buffers are active and display the data present at
the outputs of the A latches.
5
6
8
9
10 12 13 14
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
3
54
2
1EAB
MRab
1OEAB
1OEBA
MRba
4
Control of data flow from B to A is similar, but using the nEBA,
nLEBA, and nOEBA inputs.
1EBA
1
1LEAB
1LEBA
56
25
55
1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
52 51 49 48 47 45 44 43
15 16 17 19 20 21 23 24
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
26
31
27
30
2EAB
MRab
2OEAB
2OEBA
MRba
4
2EBA
28
29
25
2LEAB
2LEBA
2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
42 41 40 38 37 36 34 33
SH00064
FUNCTION TABLE
INPUTS
OUTPUTS
STATUS
nOEXX
nMRXX
nEXX
nLEXX
nAx or nBx
nBx or nAx
L
H
X
L
X
X
L
X
H
X
X
X
X
X
X
L
Z
Z
Clear
Disabled
Disabled
L
L
H
H
↑
↑
L
L
h
l
Z
Z
Disabled + Latch
Latch + Display
L
L
H
H
L
L
↑
↑
h
l
H
L
L
L
H
H
L
L
L
L
H
L
H
L
Transparent
Hold
L
H
L
H
X
NC
H
h
L
l
X
↑
=
=
=
=
=
=
High voltage level
High voltage level one set-up time prior to the Low-to-High transition of nLEXX or nEXX (XX = AB or BA)
Low voltage level
Low voltage level one set-up time prior to the Low-to-High transition of nLEXX or nEXX (XX = AB or BA)
Don’t care
Low-to-High transition of nLEXX or nEXX (XX = AB or BA)
NC= No change
High impedance or “off” state
Z
=
4
1998 Feb 27
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable
and master reset (3-State)
74ABT161543
74ABTH161543
LOGIC DIAGRAM
DETAIL A
nB0
D
Q
LE
R
nA0
Q
D
R
LE
nA1
nA2
nA3
nA4
nA5
nA6
nA7
nB1
nB2
nB3
nB4
nB5
nB6
nB7
DETAIL A X 7
MRab
MRba
nOEBA
nOEAB
nEBA
nEAB
nLEBA
nLEAB
SH00062
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
–0.5 to +7.0
–18
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
OUT
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
mA
mA
°C
I
DC output current
OUT
output in High state
–64
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5
1998 Feb 27
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable
and master reset (3-State)
74ABT161543
74ABTH161543
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
4.5
0
Max
V
DC supply voltage
5.5
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
10
T
amb
Operating free-air temperature range
–40
+85
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
MIN
TYP
MAX
MIN
MAX
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5V; I = –18mA
–1.2
–1.2
V
V
V
V
V
V
IK
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
3.0
3.6
2.5
3.0
2.0
OH
I
IL
IH
IH
= 5.0V; I = –3mA; V = V or V
V
OH
High-level output voltage
Low-level output voltage
OH
I
IL
= 4.5V; I = –32mA; V = V or V
IH
2.7
OH
I
IL
V
OL
= 4.5V; I = 64mA; V = V or V
IH
0.36
0.13
0.55
0.55
0.55
0.55
OL
I
IL
3
V
RST
Power-up output voltage
= 5.5V; I = 1mA; V = GND or V
O I CC
Input leakage
current
Control
pins
I
I
V
CC
= 5.5V; V = GND or 5.5V
"0.01
±1.0
±1.0
µA
I
V
V
V
V
V
= 4.5V; V = 0.8V
35
35
CC
CC
CC
CC
CC
I
Bus Hold current A or B
Ports 74ABTH161543
= 4.5V; V = 2.0V
–75
–75
I
µA
I
HOLD
5
= 5.5V; V = 0 to 5.5V
±800
I
I
Power-off leakage current
Power-up/down 3-State
= 0.0V; V or V ≤ 4.5V
"1.0
"1.0
±100
±50
±100
±50
µA
µA
OFF
O
I
= 2.1V; V = 0.0V or V
;
CC
O
I
PU/PD
4
output current
V = GND or V ; V = Don’t care
I
CC
OE
I
+ I
+ I
3-State output High current
3-State output Low current
Output High leakage current
V
V
V
V
V
V
V
= 5.5V; V = 5.5V; V = V or V
IH
1.0
–1.0
1.0
50
–50
50
50
–50
50
µA
µA
IH
OZH
OZL
CC
CC
CC
CC
CC
CC
CC
O
I
IL
I
= 5.5V; V = 0.0V; V = V or V
O I IL IH
IL
I
= 5.5V; V = 5.5V; V = GND or V
CC
µA
CEX
O
I
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–100
0.50
9
–200
1.5
19
–50
–200
1.5
19
mA
mA
mA
O
I
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
= 5.5V; Outputs Low, V = GND or V
CCL
I
CC
Quiescent supply current
= 5.5V; Outputs 3–State;
0.50
1.5
1.5
mA
CCZ
V = GND or V
I
CC
Additional supply current
per input pin
74ABT161543
V
= 5.5V; one input at 3.4V,
2
CC
∆I
∆I
5.0
100
100
µA
CC
other inputs at V or GND
CC
Additional supply current
per input pin
74ABTH161543
V
= 5.5V; one input at 3.4V,
2
CC
0.20
1
1
mA
CC
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V, with a transition time of up to 10msec. From V = 2.1V to V = 5V ± 10% a
CC
CC
CC
transition time of up to 100µsec is permitted.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
6
1998 Feb 27
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable
and master reset (3-State)
74ABT161543
74ABTH161543
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
MAX
o
o
T
V
= +25 C
T
V
= –40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
MIN
TYP
MIN
MAX
t
t
Propagation delay
nAx to nBx, nBx to nAx
1.2
1.0
2.5
2.2
3.4
2.9
1.2
1.0
3.9
3.5
PLH
PHL
2
ns
t
t
Propagation delay
LEBA to nAx, LEAB to nBx
1
2
1.2
1.2
3.0
2.6
4.1
3.5
1.2
1.2
5.1
4.1
PLH
PHL
ns
ns
ns
t
MRba to nAx, MRab to nBx
6
1.2
2.6
3.4
1.2
4.2
PHL
t
Output enable time
OEBA to nAx, OEAB to nBx
4
5
1.4
1.4
3.3
3.4
4.4
4.4
1.4
1.4
5.5
5.6
PZH
t
PZL
t
t
Output disable time
OEBA to nAx, OEAB to nBx
4
5
1.4
1.4
3.5
2.7
4.8
3.5
1.4
1.4
5.4
4.0
PHZ
PLZ
ns
ns
ns
t
Output enable time
EBA to nAx, EAB to nBx
4
5
1.4
1.4
3.4
3.5
4.4
4.4
1.4
1.4
5.6
5.7
PZH
t
PZL
t
Output disable time
EBA to nAx, EAB to nBx
4
5
1.3
1.3
3.5
2.7
4.4
3.5
1.3
1.3
5.4
4.0
PHZ
t
PLZ
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
T
V
= –40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
MIN
TYP
MIN
t (H)
t (L)
s
Setup time
nAx to LEAB, nBx to LEBA
1.5
2.0
–0.3
0.1
1.5
2.0
s
3
3
3
3
ns
ns
ns
ns
t (H)
Hold time
nAx to LEAB, nBx to LEBA
1.5
2.0
–0.1
0.1
1.5
2.0
h
t (L)
h
t (H)
Setup time
nAx to EAB, nBx to EBA
1.5
2.0
–0.1
0.2
1.5
2.0
s
t (L)
s
t (H)
Hold time
nAx to EAB, nBx to EBA
1.5
2.0
–0.1
–0.1
1.5
2.0
h
t (L)
h
t (L)
Latch enable pulse width, Low
MR Pulse width, Low
3
6
4.0
3.0
2.0
1.0
4.0
3.0
ns
ns
w
t (L)
w
7
1998 Feb 27
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable
and master reset (3-State)
74ABT161543
74ABTH161543
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
nOEAB, nOEBA,
nEAB, nEBA
V
V
V
IN
M
t
M
V
V
M
M
t
PZH
PHZ
t
t
PHL
PLH
V
OH
V
V
–0.3V
0V
OUT
OH
V
V
V
nAx, nBx
M
M
M
SH00040
SH00043
Waveform 1. Propagation Delay For Inverting Output
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
V
IN
V
V
M
nOEAB, nOEBA,
nEAB, nEBA
M
t
V
V
M
M
t
t
PLH
PHL
t
PZL
PLZ
V
OUT
V
V
M
M
V
nAx, nBx
M
V
V
+0.3V
OL
OL
SH00041
SH00044
Waveform 2. Propagation Delay For Non-Inverting Output
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
nAx, nBx
V
V
V
V
M
M
M
M
t (H)
t (L)
s
MR
t
(H)
t (L)
h
s
h
V
V
M
M
t
nLEAB, nLEBA,
nEAB, nEBA
t
W
(L)
V
V
M
M
t
(L)
PHL
w
nAx, nBx
NOTE: The shaded areas indicate when the input is permitted
V
M
to change for predictable output performance.
SH00042
Waveform 3. Data Setup and Hold Times and Latch Enable
Pulse Width
SH00043
Waveform 6. Master Reset Pulse Width, Master
Reset to Output Delay
8
1998 Feb 27
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable
and master reset (3-State)
74ABT161543
74ABTH161543
TEST CIRCUIT AND WAVEFORMS
t
W
V
AMP (V)
90%
CC
90%
7.0V
NEGATIVE
PULSE
V
V
M
10%
M
10%
R
L
0V
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
(t
)
R
THL
F
TLH
)
(t
)
F
R
R
L
C
TLH
R
THL
T
L
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
Input Pulse Definition
t
closed
PLZ
PZL
t
closed
open
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74ABT/H16
500ns 2.5ns 2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00018
9
1998 Feb 27
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable
and master reset (3-State)
74ABT161543
74ABTH161543
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5mm
SOT371-1
10
1998 Feb 27
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable
and master reset (3-State)
74ABT161543
74ABTH161543
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
11
1998 Feb 27
Philips Semiconductors
Product specification
16-bit latched transceiver with dual enable
and master reset (3-State)
74ABT161543
74ABTH161543
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03497
Document order number:
Philips
Semiconductors
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