BH16260DL [NXP]
12-bit to 24-bit multiplexed D-type latches 3-State; 12位至24位多路D型锁存三态
| 型号： | BH16260DL |
| 厂家： | 
NXP |
| 描述： | 12-bit to 24-bit multiplexed D-type latches 3-State |
| 文件： | 总12页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ABT16260/74ABTH16260
12-bit to 24-bit multiplexed D-type latches
(3-State)
Product specification
1998 Feb 10
Supersedes data of 1996 Nov 20
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
FEATURES
DESCRIPTION
The 74ABT16260/74ABTH16260 is a 12-bit to 24-bit multiplexed
D-type latch used in applications where two separate data paths
must be multiplexed onto, or demultiplexed from, a single data path.
Typical applications include multiplexing and/or demultiplexing of
address and data information in microprocessor or bus-interface
applications. This device is alto useful in memory-interleaving
applications.
• ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;
exceeds 200V using machine model (C = 200pF, R = 0).
• Latch-up performance exceeds 500mA per JEDEC Standard
JESD-17.
• Distributed V and GND pin configuration minimizes high-speed
CC
switching noise.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are
available for address and/or data transfer. The output enable (OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank control in the A to
B direction.
• Flow-through architecture optimizes PCB layout.
• High-drive outputs (–32mA I , 64mA I ).
OH
OL
• 74ABTH16260 incorporates bus-hold inputs which eliminate the
need for external pull-up resistors.
Address and/or data information can be stored using the internal
storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch
enable input is high, the latch is transparent. When the latch enable
input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.
• Package options:
– 56-pin plastic Shrink Small-Outline Package (SSOP)
– 56-pin plastic Thin Shrink Small-Outline Package (TSSOP)
To ensure the high-impedance state during power-up or
power-down, OE should be tied to V through a pull-up resistor;
CC
the minimum value of the resistor is determined by the current
sinking capability of the driver.
The 74ABTH incorporates the bus hold feature. The 74ABT does
not include bus hold feature. Both parts are available in 56-pin
SSOP and TSSOP.
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
Propagation delay
TYPICAL UNIT
T
amb
t
t
2.8
2.5
4
PLH
C = 50 pF
L
ns
nAx to nBx nBx to nAx
Input capacitance
PHL
C
V = 0 V or V
I CC
pF
pF
µA
IN
C
Output capacitance
Total supply current
V
= 0 V or 5.0 V
6
OUT
CCZ
I/O
I
Outputs disabled
100
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
BT16260 DL
DWG NUMBER
SOT371-1
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT16260 DL
74ABT16260 DGG
74ABTH16260 DL
74ABTH16260 DGG
BT16260 DGG
BH16260 DL
SOT364-1
SOT371-1
BH16260 DGG
SOT364-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21
An
Data inputs/outputs (A)
23, 24, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42
6, 5, 3, 54, 52, 51, 49, 48, 47, 45, 44, 43
1, 29, 56
1Bn
2Bn
Data inputs/outputs (B1)
Data inputs/outputs (B2)
Output enable input (active low)
Latch enable inputs
OEA, OE1B, OE2B
LE1B, LE2B, LEA1B, LEA2B
2, 27, 30, 55
2
1998 Feb 10
853-2048-18945
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
PIN CONFIGURATION
FUNCTION TABLES
B to A (OEB = H)
OEA
1
56 OE2B
INPUTS
SEL LE1B LE2B
OUTPUT
LE1B
2B3
2
3
4
5
6
7
8
9
55 LEA2B
54 2B4
53 GND
52 2B5
51 2B6
1B
2B
OEA
A
H
L
X
X
X
H
L
H
H
H
L
H
H
L
X
X
X
H
H
L
L
L
L
L
L
L
H
H
L
GND
2B2
X
X
X
X
X
A0
H
2B1
X
X
X
X
V
50 V
CC
CC
L
L
A1
49 2B7
48 2B8
47 2B9
46 GND
45 2B10
44 2B11
43 2B12
42 1B12
41 1B11
40 1B10
39 GND
38 1B9
37 1B8
36 1B7
X
X
L
A0
Z
A2
X
X
A3 10
A to B (OEA = H)
GND 11
A4 12
INPUTS
LEA1B LEA2B OE1B OE2B
OUTPUT
A5 13
A6 14
A7 15
A
H
L
1B
2B
H
H
H
H
H
L
H
H
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
L
L
H
L
L
A8 16
A9 17
GND 18
A10 19
A11 20
A12 21
H
L
H
2B0
2B0
H
L
L
H
L
H
H
L
1B0
1B0
1B0
Z
L
L
X
X
X
X
X
L
2B0
Z
X
X
X
X
X
X
X
X
V
22
35 V
CC
CC
Active
Z
Z
1B1 23
1B2 24
GND 25
1B3 26
LE2B 27
SEL 28
34 1B6
33 1B5
Active
Active
32 GND
31 1B4
Active
30 LEA1B
29 OE1B
SA00435
3
1998 Feb 10
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
LOGIC DIAGRAM (POSITIVE LOGIC)
2
LE1B
27
LE2B
30
LEA1B
55
LEA2B
56
OE2B
29
OE1B
1
OEA
28
SEL
C1
G1
8
23
A1
1
1
1D
1B1
C1
1D
6
2B1
C1
1D
C1
1D
TO 11 OTHER CHANNELS
SA00436
4
1998 Feb 10
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise specified)
1
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
V
V
V
Supply voltage range
Input voltage range
–0.5
–0.5
–0.5
7
V
V
CC
see Note 2
7
I
Voltage range applied to any output in the high state or power-off state
Current into any output in the low state
Input clamp current
5.5
128
–18
–50
1.4
+150
V
O
I
I
I
mA
mA
mA
W
O
V < 0
I
IK
Output clamp current
V < 0
O
OK
Maximum power dissipation at T
= 55°C (in still air)
see Note 3
amb
T
stg
Storage temperature range
–65
°C
NOTES:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating
Conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
1
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
2
MAX
V
CC
V
IH
V
IL
V
I
Supply voltage
5.5
V
V
High-level input voltage
Low-level input voltage
Input voltage
0.8
V
0
V
CC
V
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
–32
64
mA
mA
ns/V
µs/V
°C
OH
OL
∆t∆/v
∆t∆/V
Outputs enabled
10
200
–40
CC
T
Operating free-air temperature
+85
amb
NOTE:
1. Unused or floating inputs must be held high or low.
5
1998 Feb 10
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
DC ELECTRICAL CHARACTERISTICS
LIMITS
= +25°C
T
= –40°C
to +85°C
amb
T
amb
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
V
V
V
V
= 4.5V; I = –18mA
–0.8
2.9
–1.2
–1.2
V
V
V
V
V
IK
CC
CC
CC
CC
CC
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
IH
V
OH
High-level output voltage
= 5.0V; I = –3mA; V = V or V
3.4
OH
I
IL
= 4.5V; I = –32mA; V = V or V
IH
2.4
OH
I
IL
V
OL
Low-level output voltage
Input leakage current
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.55
±1
0.55
±1
OL
I
IL
Control
pins
V
CC
= 5.5V; V = V or GND
±0.01
µA
µA
I
CC
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5V; V = V or GND
Data pins
±3
±5
I
CC
= 4.5V; V = 0.8V
75
75
I
A or B
ports
I
Bus Hold current
µA
= 4.5V; V = 2.0V
–75
–75
HOLD
I
= 5.5V; V = 0 to 5.5V
±500
±500
I
I
Power-off leakage current
= 0.0V; V or V ≤ 4.5V
±5.0
±60
±100
±200
±100
±200
µA
µA
OFF
O
I
Power-up/down 3-State
output current
= 2.0V; V = 0.5V;
O
I
/I
PU PD
V = GND or V ; V = V
I
CC
OE
CC
I
I
3-State output High current
3-State output Low current
Output high leakage current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
1.0
10
–10
50
10
–10
50
µA
µA
µA
mA
OZH
CC
CC
CC
CC
CC
CC
CC
O
I
IL
IH
IH
I
= 5.5V; V = 0.5V; V = V or V
–1.0
OZL
CEX
O
I
IL
= 5.5V; V = 5.5V; V = GND or V
CC
O
I
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–100
0.2
8
–225
1.5
19
–50
–225
1.5
19
O
= 5.5V; Outputs High, V = GND or V
I
CC
= 5.5V; Outputs Low, V = GND or V
I
CC
I
Quiescent supply current
mA
mA
CC
= 5.5V; Outputs 3-State;
0.1
0.1
1.0
1.5
1.0
1.5
V = GND or V
I
CC
Additional supply current per Outputs enabled, one input at 3.4V, other
∆I
CC
2
input pin
inputs at V or GND; V = 5.5V
CC CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
3. This is the bus hold minimum overdrive current required to force the input to the opposite logic state.
6
1998 Feb 10
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
AC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
V
= 5V, T
= 25°C
T = –40°C to +85°C
amb
CC
amb
SYMBOL
UNIT
FROM (INPUT)
TO (OUTPUT)
MIN
1
TYP
MAX
MIN
MAX
5.6
5.9
5.8
5.3
5.3
6
t
t
t
t
2.8
2.5
3.2
3.2
3.2
2.8
3.0
2.6
2.9
2.2
4.1
3.2
4.8
5
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH
PHL
PLH
PHL
A or B
LE
B or A
1
1
1.1
1.1
1.3
1.1
1.5
1.6
1
4.9
4.9
4.6
4.9
4.4
5.1
4.7
5.1
5.4
4.4
1.1
1.1
1.3
1.1
1.5
1.6
1
A or B
SEL (B1)
SEL (B2)
SEL (B1)
SEL (B2)
A
A
A
A
t
PLH
PHL
4.4
5.9
5.7
5.8
6.4
4.8
t
t
t
t
t
PZH
PZL
PHZ
PLZ
OE
OE
A or B
A or B
1.6
2.2
1.3
1.6
2.2
1.3
AC SETUP CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted)
V
CC
= 5V, T
= 25°C
T
amb
= –40°C to +85°C
amb
SYMBOL
PARAMETER
UNIT
MIN
3.3
1.5
1
MAX
MIN
3.3
MAX
t
w
t
su
t
h
Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high
Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓
Hold time, data after LE1B, LE2B, LEA1B, or LEA2B↓
ns
ns
ns
1.5
1
7
1998 Feb 10
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
AC WAVEFORMS
V
M
= 1.5V for all waveforms
The outputs are measured one at a time with one transition per measurement.
3V
V
M
TIMING INPUT
DATA INPUT
t
w
0V
3V
0V
t
su
t
h
V
V
M
INPUT
M
3V
V
V
M
M
0V
SA00437
SA00439
Figure 1. Pulse duration
Figure 3. Setup and hold times
3V
0V
3V
OUTPUT
CONTROL
V
V
V
V
M
INPUT
M
M
M
0V
t
t
PLZ
t
t
PZL
PLH
PHL
V
V
V
V
3.5V
OH
OL
OH
OL
OUTPUT
WAVEFORM 1
S1 AT 7V
V
V
V
V
V
M
OUTPUT
OUTPUT
M
M
M
M
V
V
+ 0.3V
– 0.3V
OL
V
V
OL
t
t
PHZ
t
t
PZH
PHL
PLH
OH
OUTPUT
WAVEFORM 2
S1 AT OPEN
V
M
OH
≈0V
SA00438
SA00440
All input pulses are supplied by generators having the following
characteristics: PRR ≤ 10MHz, Z = 50Ω, t ≤ 2.5ns, t ≤ 2.5ns.
Waveform 1 is for an output with internal conditions such that the
output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the
output is high except when disabled by the output control.
O
r
f
Figure 2. Propagation delay times;
inverting and non-inverting outputs
Figure 4. Enable and disable times;
low- and high-level enabling
TEST LOAD CIRCUIT
7V
S1
OPEN
GND
500Ω
FROM OUTPUT UNDER TEST
TEST
/t
S1
Open
7V
t
PLH PHL
C
= 50pF
500Ω
L
t
/t
PLZ PZL
(INCLUDES PROBE AND
JIG CAPACITANCE)
t
/t
Open
PHZ PZH
Load Circuit for Outputs
SA00441
Figure 5. Test load circuit
8
1998 Feb 10
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
9
1998 Feb 10
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
10
1998 Feb 10
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
NOTES
11
1998 Feb 10
Philips Semiconductors
Product specification
74ABT16260
74ABTH16260
12-bit to 24-bit multiplexed D-type latches (3-State)
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03339
Document order number:
Philips
Semiconductors
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