BSC9131CLN1HHHB_技术文档

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: BSC9131

Rev. 0, 03/2014

BSC9131

BSC9131 QorIQ Qonverge

Multicore Baseband

Processor

FC-PBGA–520

21 mm x 21 mm

The following list provides an overview of the feature set:

• High-performance 32-bit e500 core built on Power

Architecture® technology:

– TCP/IP acceleration, quality of service, and

classification capabilities

– IEEE Std 1588™ support

– eTSEC1 supports RGMII and RMII interfaces

– eTSEC2 supports an RGMII interface

• High-speed USB controller (USB 2.0)

– Host and device support

– 36-bit physical addressing

– Double-precision floating-point support

– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data

cache

– Enhanced host controller interface (EHCI)

– ULPI interface

– Enhanced hardware and software debug support

– 800 MHz/1 GHz clock frequency

• Enhanced secure digital (SD/MMC) host controller

(eSDHC)

– 256-Kbyte L2 cache with ECC; also configurable as

SRAM and stashing memory

• Integrated Flash controller (IFC), supporting NAND,

NOR, and general ASIC

• One SC3850 core subsystem, which connects to the

following:

• TDM with one TDM port

– 32 Kbyte 8-way level 1 data/instruction cache

(L1 Dcache/ICache)

– 512 Kbyte 8-way level 2 unified instruction/data cache

(L2 cache/M2 memory)

– Memory management unit (MMU)

– Enhanced programmable interrupt controller (EPIC)

– Debug and profiling unit (DPU)

• Antenna interface controller (AIC), supporting three

industry standard JESD/three custom parallel RF interfaces

(two dual and one single port) and three MAXIM's

MaxPHY serial interfaces

• Universal Subscriber Identity Module (USIM) interface

– Facilitates communication to SIM cards or Eurochip

pre-paid phone cards

– Two 32-bit quad timers

• Four enhanced serial peripheral interfaces (eSPI)

• Programmable interrupt controller (PIC) compliant with

OpenPIC standard

• Multi Accelerator Platform Engine for Femto Base Station

Baseband Processing (MAPLE-B2F)

– Supports variable sizes in Fourier Transforms,

Convolution, Filtering, Turbo, Viterbi, Chiprate

– Consists of accelerators for UMTS chip rate processing,

LTE UP/DL channel processing, Matrix Inversion

operations, and CRC algorithms

• One four-channel DMA controller

2

• Two I C interfaces

• Two dual UART (DUART) interfaces

• Two pulse-width modulator (PWM) interfaces

• 96 general-purpose I/O signals

• Eight 32-bit timers

• DDR3/DDR3L SDRAM memory controller supports

32-bit without ECC and 16-bit with ECC

• Integrated security engine (ULE CAAM)

– Protocol support includes DES, AES, RNG, CRC, MDE,

PKE, SHA, and MD5

• Operating temperature (Ta - T ) range: 0–105° C

j

• Secure boot capability

• Two enhanced three-speed Ethernet controllers (eTSECs)

– 10/100/1000 Mbps support

Table of Contents

1

2

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.20 Radio Frequency (RF) Interface . . . . . . . . . . . . . . . . 101

2.21 Universal Subscriber Identity Module (USIM) . . . . . . 108

2.22 Timers and Timers_32b AC Timing Specifications . . 112

Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 113

3.1 Power Architecture System Clocking. . . . . . . . . . . . . 113

3.2 DSP System Clocking . . . . . . . . . . . . . . . . . . . . . . . . 116

3.3 Supply Power Default Setting . . . . . . . . . . . . . . . . . . 117

3.4 PLL Power Supply Design. . . . . . . . . . . . . . . . . . . . . 117

3.5 Decoupling Recommendations . . . . . . . . . . . . . . . . . 118

3.6 Pull-Up and Pull-Down Resistor Requirements. . . . . 119

3.7 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . 119

3.8 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . 120

3.9 JTAG Configuration Signals. . . . . . . . . . . . . . . . . . . . 120

3.10 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

3.11 Security Fuse Processor . . . . . . . . . . . . . . . . . . . . . . 123

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.2 Mechanical Dimensions of the FC-PBGA . . . . . . . . . 125

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

5.1 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

1.1 Ball Layout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.2 Pinout Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .48

2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

2.3 Power-Down Requirements . . . . . . . . . . . . . . . . . . . . .54

2.4 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.5 Power-on Ramp Rate . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.6 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.7 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.8 DDR3 and DDR3L SDRAM Controller . . . . . . . . . . . . .61

2.9 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

2.10 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) .71

2.12 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

2.13 Integrated Flash Controller (IFC) . . . . . . . . . . . . . . . . .82

2.14 Enhanced Secure Digital Host Controller (eSDHC) . . .86

2.15 Programmable Interrupt Controller (PIC) Specifications88

2.16 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

2.17 I²C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

2.18 GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

2.19 TDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

3

4

5

6

7

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

2

Freescale Semiconductor

Pin Assignments

This figure shows the major functional units.

x4

StarCore

SC3850 DSP Core

Power Architecture

e500 Core

32-Kbyte

L1 D-Cache L1 I-Cache

MAPLE-B2F

Baseband

RF Interface:

Parallel &

Serial (MaxPHY)

Accelerator

512-Kbyte

L2 Cache

Coherency 256-Kbyte

Module

32-bit DDR3/3L

Memory

LTE/UMTS/WiMAX

L2 Cache

Controller

Multicore

Fabric

4x eSPI

Ethernet

2x DUART

2

Security

Engine

4.4

IEEE 1588™

DMA

2x I

C

1GE

GPIO

1GE

USIM

IFC

RMII/

RGMII

eSDHC

2x PWM

TDM

BSC9131

Clocks/Reset

Figure 1. BSC9131 Block Diagram

1

Pin Assignments

This section contains a top-level ball layout diagram followed by four detailed quadrant views and a pinout listing table.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

3

Pin Assignments

1.1

Ball Layout Diagrams

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

ANT1_

RX_

FRAME

UART_

RTS_

B00

SCAN_

MODE_

B

A

B

A

B

TDO

TDI

TEST_

SEL_B

UART_

SIN00

READY HRESET

_B

IFC_

AD09

IFC_

AD04

IFC_

AD10

IFC_

IFC_CS_

B00

IFC_

ADDR19

IFC_

WE_B

IFC_

WP_B

IFC_

RB_B

SDHC_ X1VDD

CLK

VSS

ADDR21 ADDR17 ADDR20 ADDR24

IFC_

BCTL

SDHC_

DATA02

VSS

SYSCLK

ANT1_

DIO10

BVDD_

VSEL01

VSS

OVDD

IIC1_

SCL

UART_

SIN01

EE1

RTC

VSS

UDE_

B

IFC_

AD00

VSS

IFC_

AD05

IFC_

AD06

VSS

IFC_

SDHC_

CD

ANT1_

ADDR18 ADDR25

TX_CLK RX_CLK ENABLE

UART_

RTS_

B01

C

D

C

XVDD2_

VSEL

ANT1_

DIO09

XVDD1_ TRST_B

VSEL

IIC1_

SDA

CVDD_

VSEL

TMP_

EE0

IFC_

AD11

IFC_

AD01

IFC_

AD03

IFC_

AD15

IFC_

ADDR16

IFC_

CLE

IFC_

CLK00

IFC_

CS_B01 DATA03

SDHC_

VSS

ANT1_

TXNRX

ANT1_

DIO11

VSS

ADDR23 ADDR22

DETECT

CFG_

1_JTAG

_MODE

ANT1_

TX_

FRAME

MAX_

REF_

CLK

UART_

CTS_

B00

IFC_

VSS

IFC_

D

MCS_B02

MA13

ANT1_

DIO05

VSS

MA15

MA06

TCK

DDRCLK

MA02

TMS

VSS

LVDD_

VSEL

VSS

IFC_

AD12

IFC_

AD02

VSS

IFC_

AD07

IFC_

AD13

SDHC_ SDHC_

WP

X1VDD

ANT1_

DIO06

ANT1_

DIO08

ADDR26 CS_B02

DATA01

CFG_0_

JTAG_

MODE

UART_

CTS_

B01

UART_

SOUT01

E

ANT1_

DIO01

OVDD

DSP_ HRESET_ BVDD

CLKIN REQ_B

IFC_

AD08

IFC_

AD14

BVDD

IFC_OE IFC_AVD

_B

BVDD

SDHC_ SDHC_

DATA00

ANT1_

DIO07

ANT1_

DIO04

ANT1_

DIO03

ANT1_

DIO00

CMD

UART_

SOUT00

F

MA08

MAX2_

TX_I_B

MCS_

B03

MAX1_

RX_Q

ANT1_

DIO02

VSS

MAX2_

TX_I

SEE DETAIL B

SEE DETAIL A

G

H

G

H

MA05

MAX3_

TX_I_B

MA11

VSS

MA09

MA01

MAX1_

RX_Q_B

MAX1_

TX_Q

MAX1_

TX_Q_B

MAX3_

TX_I

AVDD_

DDR

OVDD

BVDD_

VSEL00

BVDD

SENSE

VDD

X1VDD

MAX1_

RX_I_B

MAX2_

RX_I

VSS

RVDD

MAX1_

RX_I

GVDD

MA03

MA14

MBA00

MA12

MA07

MA04

MBA01

VSS

MAX2_

TX_Q_B

J

MAX2_

RX_I_B

MAX3_

TX_Q

MAX3_

TX_Q_B

MAX2_

TX_Q

J

MCKE01

GVDD

VDDC

VSS

VDDC

VSS

VDDC

VSS

VDDC

VSS

VDDC

VSS

VDD

VSS

VDDC

VSS

VDD

VSS

VDD

VSS

VDD

X1VDD

RVDD

NC_

BGA_

K23

K

MAX2_

RX_Q_B

MAX1_

TX_I_B

VSS

MAX2_

RX_Q

MA00

MCS_B01

MA10

VSS

MBA02

MCS_

B00

L

MAX_

TX_CLK_B

L

MAX1_

TX_I

ANT2_

DIO11

ANT2_

DIO09

MAX_

TX_CLK

POVDD2 VDDC

VDDC

VDD

GVDD

MODT01 MODT00 MCKE00

ANT_

REF_

CLK

MDIC00

ANT2_

TX_CLK

MCAS_B MWE_B MCK_B

VSS

ANT2_

AGC

ANT2_

DIO10

VSS

M

N

M

N

MVREF

VSS

VDDC

VSS

VDDC

VSS

VDD

VSS

VDD

VSS

AVDD_

RF

POVDD1 VDDC

VDDC

VDD

AVDD_

DSP

MDIC01

GVDD

ANT2_

DIO04

MDM01

VSS

MCK

MRAS_B

MDQ04

ANT2_

DIO08

VSS

ANT2_

DIO07

ANT2_

DIO05

ANT2_

RX_

FRAME

MDQS01 MDQ15 MDQ06

ANT2_

DIO06

ANT2_

RX_CLK TXNRX

ANT2_

ENABLE

P

GVDD

VSS

VDDC

VSS

VDDC

VSS

VDDC

VSS

VDDC

VSS

X2VDD

VSS

SPI2_

MOSI

ANT2_

DIO02

ANT2_

DIO03

VSS

MDM00

VDDC

R

MDQS_ MDQ12 MDQ00

B01

VSS

ANT2_

TX_

FRAME

T

GVDD

VSS

VDDC

VSS

VDDC

VSS

VDDC

VSS

VDDC

VSS

X2VDD

SPI2_

CS3_B

VSS

SPI2_

CLK

ANT2_

DIO00

MDQ07

GVDD

MDQ08

VSS

MDQS00 MDQ01

ANT2_

DIO01

ANT3_

ENABLE CS1_B

SPI2_

MISO

SPI2_

CS0_B

U

MDQ09 MDQ10 MDQS_

B00

MDQ02

VSS

GVDD

FA_VDD

VDDC

CVDD

VSS

VDDC

CVDD

VSS

VDDC

LVDD

VSS

VDDC

LVDD

X2VDD

ANT3_

MDQ05

ANT3_

AGC

V

MDQ14 MDQ11 MDQ03

ANT3_

RX_

DIO06

X2VDD

SPI2_

CS2_B

AVDD_

PLAT

AVDD_

CORE

LVDD

FRAME

ANT3_

TX_

FRAME

W

Y

W

Y

ANT3_

RX_CLK

MDQ13

VSS

MDQ19

MDM02 MDQ16

ANT3_

DIO05

VSS

ANT3_

TX_CLK

SEE DETAIL C

SEE DETAIL D

GVDD

ANT3_

TXNRX

MDQ30 MDM03 MDQ20

MDQ17

ANT3_

DIO03

ANT3_

DIO09

ANT3_

DIO11

ANT3_

DIO10

TSEC_

1588_ TSEC2_

CLK_IN RXD01

MDQ31

ANT3_

DIO08

MDQ24 MDQ23 MDQS02 MDQ18

SENSE

VSS

CVDD

USB_

STP

CVDD POVDD3

VSS

TSEC1_ TSEC1_

RXD03 RX_CLK

TSEC2_ TSEC2_ TSEC2_ CVDD

VSS

ANT3_

DO08

ANT3_

DIO01

ANT3_

DIO07

VSS

AA

AB

AC

AD

AA

AB

AC

AD

TXD00

TXD01

RXD02

NC_

BGA_

AB11

MDQS03

ANT3_

DIO04

VSS

MDQ21 MDQS_ SENSE

SPI1_

MOSI

SPI1_

CLK

VSS

USB_

D04

USB_

D06

TSEC1_

TX_EN

VSS

CVDD

TSEC2_

TXD03

VSS

TSEC2_ TSEC2_

VSS

ANT3_

DO05

X2VDD

ANT3_

DIO02

ANT3_

DIO00

B02

VDDC

RX_DV

RX_CLK

TSEC_

1588_

CLK_

OUT

TSEC_

1588_

PULSE_

OUT1

NC_

BGA_

AC20

MDQS_

B03

ANT3_

DO10

MDQ28 MDQ25

VSS

SPI1_

MISO

SPI1_

CS0_B

CVDD

USB_

D02

USB_

D03

TSEC1_ CVDD

TXD01

TSEC1_ TSEC1_

TSEC1_ TSEC2_ TSEC2_ TSEC2_

VSS

ANT3_

DO04

ANT3_

DO06

ANT3_

DO11

TXD02

RX_DV

RXD01

TXD02 GTX_CLK RXD03

NC_

BGA_

AD19

NC_

BGA_

AD20

TSEC1_

GTX_

CLK125

TSEC1_

GTX_

CLK

TSEC1_

RXD02

VSS

MDQ26

VSS

ANT3_

DO07

VSS

MDQ22

SPI1_

CS1_B

SPI1_

CS3_B

USB_ USB_CLK USB_

DIR

USB_

D01

EC_

MDIO

TSEC2_

RXD00

VSS

ANT3_

DO01

ANT3_

DO09

VSS

NXT

TSEC_

1588_

TRIG_

IN1

NC_

BGA_

AE20

NC_

BGA_

AE10

NC_

BGA_

AE14

TSEC2_

GTX_

CLK125

MDQ27 MDQ29

VSS

SPI1_

CS2_B

USB_

D05

USB_

D00

USB_

D07

TEMP_

ANODE

TSEC1_

TXD00 CATHODE RXD00

TEMP_ TSEC1_

TSEC1_ TSEC2_

EC_

MDC

X2VDD

ANT3_

DO03

ANT3_

DO02

ANT3_

DO00

VSS

AE

TXD03

TX_EN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Figure 2. Ball Layout Diagram—Top-Level View

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

4

Freescale Semiconductor

Pin Assignments

Figure 3 shows detailed view A.

DETAIL A

1

2

3

4

5

6

7

8

9

10

11

12

13

UART_

RTS_

B00

SCAN_

MODE_

B

A

B

C

D

E

F

TDO

TDI

TEST_

SEL_B

UART_

SIN00

READY HRESET

_B

IFC_

AD09

IFC_

AD04

IFC_

AD10

IFC_

ADDR21

SYSCLK

BVDD_

VSEL01

VSS

OVDD

IIC1_

SCL

UART_

SIN01

EE1

RTC

VSS

UDE_

B

IFC_

AD00

VSS

IFC_

AD05

IFC_

AD06

UART_

RTS_

B01

XVDD2_

VSEL

XVDD1_ TRST_B

VSEL

IIC1_

SDA

CVDD_

VSEL

TMP_

EE0

IFC_

AD11

IFC_

AD01

IFC_

AD03

IFC_

AD15

DETECT

CFG_

1_JTAG

_MODE

MAX_

REF_

CLK

UART_

CTS_

B00

MCS_B02

MA13

VSS

MA15

MA06

TCK

DDRCLK

MA02

TMS

VSS

LVDD_

VSEL

VSS

IFC_

AD12

IFC_

AD02

VSS

CFG_0_

JTAG_

MODE

UART_

CTS_

B01

UART_

SOUT01

OVDD

DSP_ HRESET_ BVDD

CLKIN

IFC_

AD08

REQ_B

UART_

SOUT00

MA08

MCS_

B03

G

H

J

MA05

MA11

VSS

MA09

MA01

AVDD_

DDR

OVDD

BVDD_

VSEL00

BVDD

GVDD

MA03

MA14

MBA00

MA12

MA07

MA04

MBA01

VSS

MCKE01

GVDD

VDDC

VSS

VDDC

VSS

VDDC

VSS

VDDC

VSS

VDDC

VSS

K

L

MA00

MCS_B01

MA10

VSS

MBA02

MCS_

B00

POVDD2 VDDC

VDDC

GVDD

MODT01 MODT00 MCKE00

MDIC00

MCAS_B MWE_B MCK_B

VSS

M

N

MVREF

VSS

VDDC

VSS

VDDC

VSS

POVDD1 VDDC

VDDC

MDIC01

MDM01

VSS

MCK

MRAS_B

Figure 3. Ball Layout Diagram—Detail A

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

5

Pin Assignments

Figure 4 shows detailed view B.

DETAIL B

14

15

16

17

18

19

20

21

22

23

24

25

ANT1_

RX_

FRAME

A

B

C

D

E

F

IFC_

IFC_CS_

B00

IFC_

ADDR19

IFC_

WE_B

IFC_

WP_B

IFC_

RB_B

SDHC_ X1VDD

CLK

VSS

ADDR17 ADDR20 ADDR24

IFC_

BCTL

SDHC_

DATA02

VSS

ANT1_

DIO10

VSS

IFC_

VSS

SDHC_

CD

ANT1_

ADDR18 ADDR25

TX_CLK RX_CLK ENABLE

ANT1_

DIO09

IFC_

ADDR16

IFC_

CLE

IFC_

CLK00

IFC_

CS_B01 DATA03

SDHC_

VSS

ANT1_

TXNRX

ANT1_

DIO11

VSS

ADDR23 ADDR22

ANT1_

TX_

FRAME

IFC_

VSS

IFC_

ANT1_

DIO05

IFC_

AD07

IFC_

AD13

SDHC_ SDHC_

WP

X1VDD

ANT1_

DIO06

ANT1_

DIO08

ADDR26 CS_B02

DATA01

ANT1_

DIO01

IFC_

AD14

BVDD

IFC_OE IFC_AVD

_B

BVDD

SDHC_ SDHC_

DATA00 CMD

ANT1_

DIO07

ANT1_

DIO04

ANT1_

DIO03

ANT1_

DIO00

MAX2_

TX_I_B

MAX1_

RX_Q

ANT1_

DIO02

VSS

MAX2_

TX_I

G

H

J

MAX3_

TX_I_B

MAX1_

RX_Q_B

MAX1_

TX_Q

MAX1_

TX_Q_B

MAX3_

TX_I

BVDD

SENSE

VDD

X1VDD

MAX1_

RX_I_B

MAX2_

RX_I

VSS

RVDD

MAX1_

RX_I

MAX2_

TX_Q_B

MAX2_

RX_I_B

MAX3_

TX_Q

MAX3_

TX_Q_B

MAX2_

TX_Q

VSS

VDD

VSS

VDDC

VSS

VDD

VSS

VDD

VSS

VDD

X1VDD

RVDD

NC_

BGA_

K23

K

L

MAX2_

RX_Q_B

MAX1_

TX_I_B

VSS

MAX2_

RX_Q

MAX_

TX_CLK_B

MAX1_

TX_I

ANT2_

DIO11

ANT2_

DIO09

MAX_

TX_CLK

VDD

ANT_

REF_

CLK

ANT2_

TX_CLK

ANT2_

AGC

ANT2_

DIO10

VSS

M

N

VDD

VSS

VDD

VSS

AVDD_

RF

VDD

AVDD_

DSP

ANT2_

DIO04

ANT2_

DIO08

VSS

ANT2_

DIO07

ANT2_

DIO05

Figure 4. Ball Layout Diagram—Detail B

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

6

Freescale Semiconductor

Pin Assignments

Figure 5 shows detailed view C.

DETAIL C

GVDD

MDQS01 MDQ15 MDQ06

MDQ04

VSS

P

GVDD

VSS

VDDC

VSS

VDDC

VSS

MDM00

GVDD

VDDC

VSS

VDDC

R

MDQS_ MDQ12 MDQ00

B01

T

VSS

VDDC

VSS

VDDC

VSS

MDQ07

GVDD

MDQ08

VSS

MDQS00 MDQ01

U

V

MDQ09 MDQ10 MDQS_

B00

MDQ02

VSS

GVDD

FA_VDD

VDDC

CVDD

VSS

VDDC

CVDD

MDQ05

MDQ14 MDQ11 MDQ03

AVDD_

PLAT

AVDD_

CORE

LVDD

W

MDQ13

VSS

MDQ19

MDM02

MDQ17

MDQ16

GVDD

Y

MDQ30 MDM03 MDQ20

MDQ31

MDQ24 MDQ23 MDQS02 MDQ18

SENSE

VSS

CVDD

USB_

STP

CVDD POVDD3

VSS

TSEC1_ TSEC1_

RXD03 RX_CLK

AA

AB

AC

AD

NC_

BGA_

AB11

MDQS03

VSS

MDQ21 MDQS_ SENSE

SPI1_

MOSI

SPI1_

CLK

VSS

USB_

D04

USB_

D06

TSEC1_

TX_EN

VSS

B02

VDDC

MDQS_

B03

MDQ28 MDQ25

VSS

SPI1_

MISO

SPI1_

CS0_B

CVDD

USB_

D02

USB_

D03

TSEC1_

TXD01

CVDD

TSEC1_ TSEC1_

TXD02

RX_DV

TSEC1_

GTX_

CLK

TSEC1_

RXD02

VSS

MDQ26

VSS

MDQ22

SPI1_

CS1_B

SPI1_

CS3_B

USB_ USB_CLK USB_

DIR

USB_

D01

NXT

NC_

BGA_

AE10

MDQ27 MDQ29

VSS

SPI1_

CS2_B

USB_

D05

USB_

D00

USB_

D07

TEMP_

ANODE

TSEC1_

TXD00 CATHODE RXD00

TEMP_ TSEC1_

AE

1

2

3

4

5

6

7

8

9

10

11

12

13

Figure 5. Ball Layout Diagram—Detail C

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

7

Pin Assignments

Figure 6 shows detailed view D.

DETAIL D

ANT2_

RX_

FRAME

ANT2_

DIO06

ANT2_

RX_CLK TXNRX

ANT2_

ENABLE

P

R

VDDC

VSS

VDDC

VSS

X2VDD

VSS

SPI2_

MOSI

ANT2_

DIO02

ANT2_

DIO03

VSS

VDDC

ANT2_

TX_

FRAME

T

VDDC

VSS

VDDC

VSS

X2VDD

SPI2_

CS3_B

VSS

SPI2_

CLK

ANT2_

DIO00

ANT2_

DIO01

ANT3_

ENABLE CS1_B

SPI2_

MISO

SPI2_

CS0_B

U

VSS

VDDC

LVDD

VSS

VDDC

LVDD

X2VDD

ANT3_

AGC

V

ANT3_

RX_

DIO06

X2VDD

SPI2_

CS2_B

LVDD

FRAME

ANT3_

TX_

FRAME

W

Y

ANT3_

RX_CLK

ANT3_

DIO05

VSS

ANT3_

TX_CLK

ANT3_

TXNRX

ANT3_

DIO03

ANT3_

DIO09

ANT3_

DIO11

ANT3_

DIO10

TSEC_

1588_ TSEC2_

CLK_IN RXD01

ANT3_

DIO08

TSEC2_ TSEC2_ TSEC2_

CVDD

VSS

ANT3_

DO08

ANT3_

DIO01

ANT3_

DIO07

VSS

AA

AB

AC

AD

TXD00

TXD01

RXD02

ANT3_

DIO04

CVDD

TSEC2_

TXD03

VSS

TSEC2_ TSEC2_

VSS

ANT3_

DO05

X2VDD

ANT3_

DIO02

ANT3_

DIO00

RX_DV

RX_CLK

TSEC_

1588_

CLK_

OUT

TSEC_

1588_

PULSE_

OUT1

NC_

BGA_

AC20

ANT3_

DO10

TSEC1_ TSEC2_ TSEC2_ TSEC2_

VSS

ANT3_

DO04

ANT3_

DO06

ANT3_

DO11

RXD01

TXD02 GTX_CLK RXD03

NC_

BGA_

AD19

NC_

BGA_

AD20

TSEC1_

GTX_

CLK125

VSS

ANT3_

DO07

EC_

MDIO

TSEC2_

RXD00

VSS

ANT3_

DO01

ANT3_

DO09

VSS

TSEC_

1588_

TRIG_

IN1

NC_

BGA_

AE20

NC_

BGA_

AE14

TSEC2_

GTX_

CLK125

TSEC1_ TSEC2_

EC_

MDC

X2VDD

ANT3_

DO03

ANT3_

DO02

ANT3_

DO00

VSS

AE

TXD03

TX_EN

14

15

16

17

18

19

20

21

22

23

24

25

Figure 6. Ball Layout Diagram—Detail D

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

8

Freescale Semiconductor

Pin Assignments

1.2

Pinout Assignments

This table provides the pinout listing.

Table 1. BSC9131 Pinout Listing

Signal Description

Number

Type

Power

Note

Signal

Supply

DDR (Power Architecture)

MDQ00

MDQ01

MDQ02

MDQ03

MDQ04

MDQ05

MDQ06

MDQ07

MDQ08

MDQ09

MDQ10

MDQ11

MDQ12

MDQ13

MDQ14

MDQ15

MDQ16

MDQ17

MDQ18

MDQ19

MDQ20

MDQ21

MDQ22

MDQ23

MDQ24

MDQ25

MDQ26

MDQ27

MDQ28

MDQ29

MDQ30

MDQ31

Data

R3

T4

I/O

GVDD

—

U4

V3

P4

V5

P3

T5

T1

U1

U2

V2

R2

W1

V1

P2

W5

Y4

AA5

W3

Y3

AB3

AD3

AA3

AA2

AC3

AD1

AE2

AC2

AE3

Y1

AA1

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

9

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

MDM00

MDM01

MDM02

MDM03

MDQS00

MDQS01

MDQS02

MDQS03

MDQS_B00

MDQS_B01

MDQS_B02

MDQS_B03

MBA00

MBA01

MBA02

MA00

Data Mask

Data Strobe

Bank Select

Address

R5

N1

W4

Y2

T3

O

GVDD

—

O

I/O

O

P1

AA4

AB1

U3

R1

AB4

AC1

H2

H4

K3

K5

G4

F3

O

MA01

Address

O

MA02

Address

O

MA03

Address

J5

O

MA04

Address

J3

O

MA05

Address

G5

F2

O

MA06

Address

O

MA07

Address

H3

F1

O

MA08

Address

O

MA09

Address

G3

L1

O

MA10

Address

O

MA11

Address

G1

J2

O

MA12

Address

O

MA13

Address

E1

H1

E2

M2

N4

M1

K4

K1

O

MA14

Address

O

MA15

Address

O

MWE_B

MRAS_B

MCAS_B

MCS_B00

MCS_B01

Write Enable

O

Row Address Strobe

Column Address Strobe

Chip Select

O

Chip Select

O

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

10

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

Signal Description

Number

Supply

MCS_B02

MCS_B03

MCKE00

MCKE01

MCK

Chip Select

Clock Enable

Clock

D1

F4

L4

J1

O

GVDD

VSS

—

17

O

N3

M3

L3

L2

M5

N5

O

MCK_B

MODT00

MODT01

MDIC00

MDIC01

Clock Complements

O

On Die Termination

O

On Die Termination

O

Driver Impedence Calibration

I/O

GVDD

Ethernet Management

EC_MDC

EC_MDIO

Management Data Clock

Management Data In/Out

AE18

AD16

O

LVDD

2

I/O

18

eTSEC 1 (RGMII)

TSEC1_TXD00

TSEC1_TXD01

TSEC1_TXD02

TSEC1_TXD03

TSEC1_TX_EN

TSEC1_RXD00

TSEC1_RXD01

TSEC1_RXD02

RGMII Transmit Data

RGMII Transmit Enable

RGMII Receive Data

AE11

AC10

AC12

AE15

AB12

AE13

AC14

AD13

AA12

O

I

LVDD

2

—

I

TSEC1_RXD03/

I

TSEC1_RX_ER

TSEC1_RX_DV

TSEC1_RX_CLK

TSEC1_GTX_CLK

RGMII Receive Data Valid

RGMII Receive Clock

AC13

AA13

AD11

AD14

I

LVDD

—

RGMII Transmit Clock Out

RGMII Reference Clock

O

I

TSEC1_GTX_CLK125/

TSEC1_TX_CLK

eTSEC 1 (RMII)

TSEC1_TXD00

TSEC1_TXD01

TSEC1_TX_EN

TSEC1_RXD00

TSEC1_RXD01

RMII Transmit Data

RMII Transmit Data Valid

RMII Receive Data

AE11

AC10

AB12

AE13

AC14

O

I

LVDD

2

—

I

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

11

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

TSEC1_RXD03/

RMII Receive Error

AA12

I

LVDD

—

TSEC1_RX_ER

TSEC1_RX_DV

RMII CRS_DV carrier sense/Data Valid

RMII Transmit Clock feedback

AC13

AD11

AD14

I

O

I

LVDD

—

TSEC1_GTX_CLK

TSEC1_GTX_CLK125/

RMII Reference Transmit/Receive Clock

TSEC1_TX_CLK

eTSEC 2 (RGMII)

TSEC2_TXD00/

DMA_DACK_B00/

USB_NXT

RGMII Transmit Data

AA14

AA15

AC15

I/O

LVDD

—

TSEC2_TXD01/

DMA_DDONE_B00/

USB_D07

RGMII Transmit Data

TSEC2_TXD02/

GPIO04/

IRQ04/

USB_D06

TSEC2_TXD03/

GPIO05/

RGMII Transmit Data

AB15

I/O

LVDD

—

IRQ05/

USB_D05

TSEC2_TX_EN

RGMII Transmit Enable

RGMII Receive Data

AE16

AD17

O

LVDD

—

TSEC2_RXD00/

DMA_DREQ_B00/

USB_D04

I/O

TSEC2_RXD01/

USB_D03

RGMII Receive Data

RGMII Receive Data Valid

RGMII Receive Clock

AA19

AA16

AC17

AB17

AB18

I/O

LVDD

—

TSEC2_RXD02/

USB_D02

TSEC2_RXD03/

USB_D01

TSEC2_RX_DV/

USB_D00

TSEC2_RX_CLK/

GPIO06/

IRQ06/

USB_CLK

TSEC2_GTX_CLK/

USB_STP

RGMII Transmit Clock Out

RGMII Reference Clock

AC16

AE17

O

LVDD

—

TSEC2_GTX_CLK125/

GPIO07/

I/O

IRQ07/

USB_DIR

eTSEC 1588

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

12

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

Signal Description

Number

Supply

TSEC_1588_CLK_IN

1588 Clock In

AA18

AC18

I

LVDD

—

TSEC_1588_CLK_OUT/

1588 Clock Out

O

CLK_OUT

TSEC_1588_TRIG_IN1

1588 Trigger In

1588 Pulse Out

AE19

AC19

I

LVDD

—

2

TSEC_1588_PULSE_OUT1/

O

PPS_OUT

IFC

IFC_AD00

IFC_AD01

IFC_AD02

IFC_AD03

IFC_AD04

IFC_AD05

IFC_AD06

IFC_AD07

IFC Muxed Address, Data

B10

C11

D12

C12

A11

B12

B13

D14

E13

I/O

BVDD

2

IFC_AD08/

—

GPIO34

IFC_AD09/

GPIO35

IFC Muxed Address, Data

A10

A12

C10

I/O

BVDD

—

IFC_AD10/

GPIO36

IFC_AD11/

GPIO37/

IRQ08

IFC_AD12/

GPIO38/

IRQ09

IFC Muxed Address, Data

D11

D15

E14

C13

I/O

BVDD

—

IFC_AD13/

GPIO39/

IRQ07

IFC_AD14/

GPIO40/

IRQ06

IFC_AD15/

GPIO41/

TIMER02

IFC_ADDR16/

GPO08

IFC Address

C14

A14

B15

O

BVDD

2

IFC_ADDR17/

GPO09

IFC_ADDR18/

GPO10

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

13

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

IFC_ADDR19/

GPO11

IFC Address

A18

O

BVDD

2

IFC_ADDR20/

GPO12

A15

A13

C17

C16

A16

B16

D17

2

IFC_ADDR21/

GPO13

IFC_ADDR22/

GPO14

IFC_ADDR23/

GPO15

IFC_ADDR24/

GPO16

IFC_ADDR25/

GPO17

IFC_ADDR26/

GPO18

IFC_AVD

IFC Address Valid

IFC Chip Select

E17

A17

C19

O

BVDD

2

IFC_CS_B00

18

IFC_CS_B01/

GPO64

IFC_CS_B02/

GPO65

IFC Chip Select

D18

A19

C15

E16

O

BVDD

18

2

IFC_WE_B

IFC_CLE

IFC Write Enable/GPCM Write Byte Select0/

Generic ASIC Interface Start of Frame

NAND Command Latch Enable/

GPCM Write Byte Select1

2

IFC_OE_B

NOR Output Enable/NAND Read Enable/

GPCM Output Enable/Generic ASIC Interface

Read-Write Indicator

2

IFC_WP_B/

GPO66/

IFC Write Protect

A20

O

BVDD

3

DSP_TDI

IFC_RB_B

IFC Read Busy/GPCM External Transreciver/

Generic ASIC Interface Ready Indicator

A21

B18

I

BVDD

18

—

IFC_BCTL/

GPO67/

Data Buffer Control

O

DSP_TDO

IFC_CLK00/

GPO68

IFC Clock

C18

O

I

BVDD

—

TDM over ANT3

ANT3_DO00/

TDM_TCK/

GPIO46

TDM Transmit Clock

AE24

X2VDD

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

14

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

Signal Description

Number

Supply

ANT3_DO04/

TDM_RCK/

GPIO50/

TDM Receive Clock

AC22

I/O

X2VDD

—

IRQ00

ANT3_DO01/

TDM_TFS/

GPIO47

TDM Transmit Frame Sync

TDM Receive Frame Sync

AD22

AB21

I/O

X2VDD

—

ANT3_DO05/

TDM_RFS/

GPIO51/

IRQ01

ANT3_DO03/

TDM_TXD/

GPIO49

TDM Transmit Data

TDM Receive Data

AE22

AE23

I/O

X2VDD

—

ANT3_DO02/

TDM_RXD/

GPIO48

TDM over SDHC

SDHC_CD/

TDM_TCK

TDM Transmit Clock

TDM Receive Clock

B21

D20

I

BVDD

—

SDHC_DATA01/

SIM_SVEN/

TDM_RCK/

GPIO77

I/O

SDHC_WP/

TDM_TFS/

TIMER04

TDM Transmit Frame Sync

TDM Receive Frame Sync

TDM Transmit Data

D19

E19

B20

C20

I/O

BVDD

—

SDHC_DATA00/

SIM_TRXD/

TDM_RFS

SDHC_DATA02/

TDM_TXD/

GPIO78

SDHC_DATA03/

TDM_RXD/

GPIO79/

TDM Receive Data

IRQ10

PWM

UART_RTS_B00/

PWM2/

DSP_TCK/

PWM1 Block Output

A6

O

OVDD

CVDD

—

GPO43

SPI1_CS3_B/

ANT_TCXO_PWM/

GPO76

PWM2 Block Output for RF Interface

AD5

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

15

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Timers

Note

Number

USB_DIR/

GPIO02/

TIMER01/

MCP_B

Timer 1

AD6

I/O

CVDD

—

IFC_AD15/

GPIO41/

TIMER02

Timer 2

Timer 3

C13

AD7

I/O

BVDD

CVDD

—

USB_CLK/

UART_SIN02/

GPIO69/

IRQ11/

TIMER03

SDHC_WP/

TDM_TFS/

TIMER04

Timer 4

Timer 5

D19

B23

I/O

BVDD

—

ANT1_RX_CLK/

TIMER05/

X1VDD

TSEC_1588_TRIG_IN2/

GPIO95

ANT1_DIO10/

TIMER06/

ANT2_DO10/

Timer 6

Timer 7

Timer 8

B25

C23

L22

I/O

X1VDD

X2VDD

—

GPIO23

ANT1_DIO11/

TIMER07/

ANT2_DO11/

GPIO24

ANT2_DIO11/

TIMER08/

GPIO61

eSDHC

SDHC_CLK/

SIM_CLK

SDHC Clock

A22

E20

E19

O

BVDD

—

16

SDHC_CMD/

SIM_RST_B

SDHC Command

SDHC Data

I/O

SDHC_DATA00/

SIM_TRXD/

TDM_RFS

SDHC_DATA01/

SIM_SVEN/

TDM_RCK/

GPIO77

SDHC Data

D20

I/O

BVDD

16

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

16

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

SDHC_DATA02/

TDM_TXD/

GPIO78

Signal Description

Number

Supply

SDHC Data

B20

I/O

BVDD

16

SDHC_DATA03/

TDM_RXD/

GPIO79/

C20

I/O

BVDD

16

IRQ10

SDHC_WP/

TDM_TFS/

TIMER04

SDHC Write Protect

SDHC Card Detect

D19

B21

I

BVDD

—

SDHC_CD/

TDM_TCK

USIM

SDHC_DATA01/

SIM_SVEN/

TDM_RCK/

GPIO77

SIM Enable

D20

AB6

O

BVDD

CVDD

15

SPI1_MOSI/

UART_SIN03/

SIM_SVEN

SDHC_CMD/

SIM_RST_B

SIM Reset

E20

AC5

O

BVDD

CVDD

15

SPI1_MISO/

UART_CTS_B03/

SIM_RST_B/

CKSTP_IN_B

SDHC_DATA00/

SIM_TRXD/

TDM_RFS

SIM TX RX Data

E19

AC6

I/O

BVDD

CVDD

14

SPI1_CS0_B/

UART_RTS_B03/

SIM_TRXD

SDHC_CLK/

SIM_CLK

SIM Clock

A22

AB7

D8

O

I

BVDD

CVDD

OVDD

—

15

SPI1_CLK/

SIM_CLK

SIM Clock

UART_CTS_B00/

SIM_PD/

SIM Present Detect

DSP_TMS/

GPIO42/

IRQ04

UART_CTS_B01/

SIM_PD/

SIM Present Detect

E8

I

OVDD

15

SRESET_B/

GPIO44/

IRQ05

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

17

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

USB

Note

Number

USB_CLK/

UART_SIN02/

GPIO69/

ULPI Clock

AD7

I

CVDD

—

IRQ11/

TIMER03

USB_D07/

UART_SOUT02/

GPIO70

ULPI Data

AE8

AB10

AE6

AB9

AC9

AC8

AD9

I/O

CVDD

—

USB_D06/

UART_CTS_B02/

GPIO62

USB_D05/

UART_RTS_B02/

GPIO63

USB_D04/

GPIO00/

IRQ00

USB_D03/

GPIO01/

IRQ01

USB_D02/

IIC2_SDA/

GPIO71

USB_D01/

IIC2_SCL/

GPIO72

USB_D00/

IRQ02

ULPI Data

ULPI Stop

AE7

AA8

I/O

O

CVDD

—

USB_STP/

IRQ_OUT_B/

GPO73

USB_DIR/

GPIO02/

TIMER01/

MCP_B

ULPI Data Direction

AD6

AD8

I

CVDD

—

USB_NXT/

GPIO03/

IRQ03/

ULPI Next Data Throttle Control

TRIG_IN

USB over RF Interface

ANT2_DIO09/

USB_CLK/

GPIO59

ULPI Clock

L23

I/O

X2VDD

—

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

18

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

ANT2_DIO07/

Signal Description

Number

Supply

ULPI Data

ULPI Stop

N23

I/O

O

X2VDD

—

USB_D07/

GPIO32

ANT2_DIO06/

USB_D06/

GPIO31

P21

N24

N25

R23

R22

U25

T24

P24

N21

M23

ANT2_DIO05/

USB_D05/

GPIO30

ANT2_DIO04/

USB_D04/

GPIO29

ANT2_DIO03/

USB_D03/

GPIO28

ANT2_DIO02/

USB_D02/

GPIO27

ANT2_DIO01/

USB_D01/

GPIO26

ANT2_DIO00/

USB_D00/

GPIO25

ANT2_ENABLE/

USB_STP/

GPO92

ANT2_DIO08/

USB_DIR/

GPIO33

ULPI Data Direction

I

ANT2_DIO10/

USB_NXT/

GPIO60

ULPI Next Data Throttle Control

I

USB over TSEC

TSEC2_RX_CLK/

GPIO06/

ULPI Clock

AB18

I

LVDD

—

IRQ06/

USB_CLK

TSEC2_TXD01/

DMA_DDONE_B00/

USB_D07

ULPI Data

AA15

AC15

I/O

LVDD

—

TSEC2_TXD02/

GPIO04/

IRQ04/

USB_D06

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

19

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

TSEC2_TXD03/

GPIO05/

ULPI Data

AB15

I/O

LVDD

—

IRQ05/

USB_D05

TSEC2_RXD00/

DMA_DREQ_B00/

USB_D04

ULPI Data

AD17

I/O

LVDD

—

TSEC2_RXD01/

USB_D03

ULPI Data

ULPI Stop

AA19

AA16

AC17

AB17

AC16

AE17

I/O

O

LVDD

—

TSEC2_RXD02/

USB_D02

TSEC2_RXD03/

USB_D01

TSEC2_RX_DV/

USB_D00

TSEC2_GTX_CLK/

USB_STP

TSEC2_GTX_CLK125/

GPIO07/

ULPI Data Direction

I

IRQ07/

USB_DIR

TSEC2_TXD00/

DMA_DACK_B00/

USB_NXT

ULPI Next Data Throttle Control

AA14

I

LVDD

—

SPI1

SPI1_MOSI/

UART_SIN03/

SIM_SVEN

SPI Master Out Slave In Data

AB6

AC5

O

I

CVDD

—

SPI1_MISO/

SPI Master In Slave Out Data

UART_CTS_B03/

SIM_RST_B/

CKSTP_IN_B

SPI1_CLK/

SIM_CLK

SPI Serial Clock

SPI Slave Select

AB7

AC6

O

CVDD

—

SPI1_CS0_B/

UART_RTS_B03/

SIM_TRXD

14

SPI1_CS1_B/

UART_SOUT03/

GPO74

SPI Slave Select

AD4

AE5

O

CVDD

22

SPI1_CS2_B/

CKSTP_OUT_B/

GPO75

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

20

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

SPI1_CS3_B/

Signal Description

Number

Supply

SPI Slave Select

AD5

O

CVDD

22

ANT_TCXO_PWM/

GPO76

RF Interface SPI2¹⁹

SPI2_CLK

SPI Serial Clock

T23

R21

U23

U24

U22

V24

O

I

X2VDD

—

2

SPI2_MOSI

SPI2_MISO

SPI2_CS0_B

SPI2_CS1_B

SPI Master Out Slave In Data

SPI Master In Slave Out Data

SPI Slave Select

—

22

O

SPI Slave Select

SPI2_CS2_B/

SPI Slave Select

GPO93

SPI2_CS3_B/

SPI Slave Select

T21

O

X2VDD

22

GPO94

SPI3 over RF Interface

ANT1_DIO02/

SPI3_CLK/

ANT2_DO02/

GPIO83

SPI Serial Clock

F22

O

X1VDD

—

ANT1_DIO00/

SPI3_MOSI/

ANT2_DO00/

GPIO81

SPI Master Out Slave In Data

SPI Master In Slave Out Data

SPI Slave Select

E24

E25

E23

O

I

X1VDD

—

22

ANT1_DIO01/

SPI3_MISO/

ANT2_DO01/

GPIO82

ANT1_DIO03/

SPI3_CS0_B/

ANT2_DO03/

GPIO84

O

SPI4 over RF Interface

ANT1_DIO06/

SPI4_CLK/

ANT2_DO06/

GPIO87/

SPI Serial Clock

D23

O

X1VDD

—

IRQ10

ANT1_DIO04/

SPI4_MOSI/

ANT2_DO04/

GPIO85

SPI Master Out Slave In Data

SPI Master In Slave Out Data

E22

D25

O

I

X1VDD

—

ANT1_DIO05/

SPI4_MISO/

ANT2_DO05/

GPIO86

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

21

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

ANT1_DIO07/

SPI4_CS0_B/

ANT2_DO07/

GPIO88/

SPI Slave Select

E21

O

X1VDD

22

IRQ11

DUART 1

UART_SOUT00

UART_SIN00

UART1 Transmit Data

UART1 Receive Data

UART1 Clear to Send

F5

A7

D8

O

I

OVDD

2

—

UART_CTS_B00/

SIM_PD/

I

DSP_TMS/

GPIO42/

IRQ04

UART_RTS_B00/

PWM2/

UART1 Ready to Send

A6

O

OVDD

—

DSP_TCK/

GPO43

UART_SOUT01

UART_SIN01

UART2 Transmit Data

UART2 Receive Data

UART2 Clear to Send

E5

B6

E8

O

I

OVDD

2

—

UART_CTS_B01/

SIM_PD/

I

SRESET_B/

GPIO44/

IRQ05

UART_RTS_B01/

PPS_LED/

UART2 Ready to Send

C6

O

OVDD

—

GPO45

DUART 2

USB_D07/

UART_SOUT02/

GPIO70

UART3 Transmit Data

UART3 Receive Data

AE8

AD7

O

I

CVDD

—

USB_CLK/

UART_SIN02/

GPIO69/

IRQ11/

TIMER03

USB_D06/

UART_CTS_B02/

GPIO62

UART3 Clear to Send

UART3 Ready to Send

UART4 Transmit Data

AB10

AE6

I

CVDD

—

USB_D05/

UART_RTS_B02/

GPIO63

O

SPI1_CS1_B/

UART_SOUT03/

GPO74

AD4

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

22

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

Signal Description

Number

Supply

SPI1_MOSI/

UART4 Receive Data

AB6

I

CVDD

—

UART_SIN03/

SIM_SVEN

SPI1_MISO/

UART4 Clear to Send

UART4 Ready to Send

AC5

AC6

I

CVDD

—

UART_CTS_B03/

SIM_RST_B/

CKSTP_IN_B

SPI1_CS0_B/

UART_RTS_B03/

SIM_TRXD

O

CVDD

—

I²C1

I²C2

IIC1_SDA

IIC1_SCL

Serial Data

Serial Clock

C4

B5

I/O

OVDD

5

USB_D02/

IIC2_SDA/

GPIO71

Serial Data

Serial Clock

AC8

AD9

I/O

CVDD

5

USB_D01/

IIC2_SCL/

GPIO72

System Control/Power Management

Hard Reset

HRESET_B

A9

E11

A8

I

OVDD

—

2, 4

3

HRESET_REQ_B

Hard Reset Request Out

Ready

O

READY/

ASLEEP/

DSP_TRST_B

READY/

Asleep

A8

O

OVDD

3

ASLEEP/

DSP_TRST_B

UDE_B

EE0

Unconditional Debug Event

DSP Debug Request

DSP Debug Acknowledge

Tamper Detect

B9

C9

B7

C8

I

OVDD

—

EE1

O

I

TMP_DETECT

Clocking

SYSCLK

System Clock

B1

E3

I

OVDD

—

DDRCLK

DDR PLL Reference Clock

Real Time Clock

RTC

C7

DSP_CLKIN

MAX_REF_CLK

DSP PLL Reference Clock

MAX PHY PLL Reference Clock

E10

D9

I/O Voltage Select

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

23

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

BVDD_VSEL00

BVDD_VSEL01

CVDD_VSEL

LVDD_VSEL

BVDD Voltage Selection

H11

B2

I

OVDD

—

BVDD Voltage Selection

CVDD Voltage Selection

LVDD Voltage Selection

XVDD 1 Voltage Selection

XVDD 2 Voltage Selection

C5

D6

C2

C1

XVDD1_VSEL

XVDD2_VSEL

Test

SCAN_MODE_B

CFG_0_JTAG_MODE

CFG_1_JTAG_MODE

TEST_SEL_B

Scan Mode

A4

E7

D5

A5

I

OVDD

1

9

JTAG mode selection 0

JTAG mode selection 1

Test Select

9

10

JTAG (Power Architecture)

TCK

Test Clock

D3

A3

A2

D4

C3

I

OVDD

—

3

TDI

Test Data In

Test Data Out

TDO

O

I

—

3

TMS

Test Mode Select

Test Reset

TRST_B

I

3

JTAG (DSP)

UART_RTS_B00/

PWM2/

DSP_TCK/

GPO43

DSP Test Clock

A6

I

OVDD

BVDD

—

3

IFC_WP_B/

GPO66/

DSP Test Data In

A20

DSP_TDI

IFC_BCTL//

DSP_TDO

DSP Test Data Out

B18

D8

O

I

BVDD

OVDD

—

3

UART_CTS_B00/

SIM_PD/

DSP Test Mode Select

DSP_TMS/

GPIO42/

IRQ04

READY/

ASLEEP/

DSP_TRST_B

DSP Test Reset

Transmit Clock

A8

I

OVDD

3

RF Interface 1

ANT1_TX_CLK/

B22

O

X1VDD

—

TSEC_1588_ALARM_OUT2

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

24

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

ANT1_RX_CLK/

Signal Description

Number

Supply

Receive Clock

B23

I

X1VDD

—

TIMER05/

TSEC_1588_TRIG_IN2/

GPIO95

ANT1_TXNRX/

TX_RX Control

C22

O

X1VDD

—

TSEC_1588_PULSE_OUT2/

GPO19

ANT1_ENABLE/

TSEC_1588_ALARM_OUT1

Antenna Enable

Transmit Frame

Receive Frame

B24

D21

A24

O

I

X1VDD

—

4,11

—

ANT1_TX_FRAME/

GPO20

ANT1_RX_FRAME/

MAX3_LOCK/

GPIO80

ANT1_DIO00/

SPI3_MOSI/

ANT2_DO00/

GPIO81

Data

E24

E25

F22

E23

E22

D25

D23

I/O

X1VDD

—

ANT1_DIO01/

SPI3_MISO/

ANT2_DO01/

GPIO82

ANT1_DIO02/

SPI3_CLK/

ANT2_DO02/

GPIO83

ANT1_DIO03/

SPI3_CS0_B/

ANT2_DO03/

GPIO84

ANT1_DIO04/

SPI4_MOSI/

ANT2_DO04/

GPIO85

ANT1_DIO05/

SPI4_MISO/

ANT2_DO05/

GPIO86

ANT1_DIO06/

SPI4_CLK/

ANT2_DO06/

GPIO87/

IRQ10

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

25

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

ANT1_DIO07/

SPI4_CS0_B/

ANT2_DO07/

GPIO88/

Data

E21

I/O

X1VDD

—

IRQ11

ANT1_DIO08/

MAX1_LOCK/

ANT2_DO08/

GPIO21/

D24

C25

—

IRQ08

ANT1_DIO09/

MAX2_LOCK/

ANT2_DO09/

GPIO22/

IRQ09

ANT1_DIO10/

TIMER06/

ANT2_DO10/

GPIO23

Data

B25

C23

I/O

X1VDD

—

ANT1_DIO11/

TIMER07/

ANT2_DO11/

GPIO24

RF Interface 2

ANT_REF_CLK

Parallel Interface Reference Clock

AGC Control

M22

M21

I

X2VDD

—

2

ANT2_AGC/

O

GPO89

ANT2_TX_CLK/

GPO90

Transmit Clock

Receive Clock

TX_RX Control

Antenna Enable

M25

P22

P23

P24

O

I

X2VDD

—

ANT2_RX_CLK/

GPIO91

ANT2_TXNRX/

DMA_DACK_B00

O

ANT2_ENABLE/

USB_STP/

GPO92

ANT2_TX_FRAME/

DMA_DDONE_B00

Transmit Frame

Receive Frame

Data

T25

P25

T24

O

I

X2VDD

4,11

—

ANT2_RX_FRAME/

DMA_DREQ_B00

ANT2_DIO00/

USB_D00/

GPIO25

I/O

—

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

26

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

ANT2_DIO01/

Signal Description

Number

Supply

Data

U25

I/O

X2VDD

—

USB_D01/

GPIO26

ANT2_DIO02/

USB_D02/

GPIO27

R22

R23

N25

N24

P21

N23

N21

L23

M23

L22

ANT2_DIO03/

USB_D03/

GPIO28

ANT2_DIO04/

USB_D04/

GPIO29

ANT2_DIO05/

USB_D05/

GPIO30

ANT2_DIO06/

USB_D06/

GPIO31

ANT2_DIO07/

USB_D07/

GPIO32

ANT2_DIO08/

USB_DIR/

GPIO33

ANT2_DIO09/

USB_CLK/

GPIO59

ANT2_DIO10/

USB_NXT/

GPIO60

ANT2_DIO11/

TIMER08/

GPIO61

RF Interface 3

ANT3_AGC/

AGC Control

V25

O

X2VDD

2

GPO58

ANT3_TX_CLK

ANT3_RX_CLK

ANT3_TXNRX

Transmit Clock

Receive Clock

TX_RX Control

Antenna Enable

Transmit Frame

Receive Frame

Data

W24

W25

Y25

O

I

X2VDD

—

O

I

ANT3_ENABLE

ANT3_TX_FRAME

ANT3_RX_FRAME

ANT3_DIO00

U21

W23

V22

AB24

I/O

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

27

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

ANT3_DIO01

ANT3_DIO02

ANT3_DIO03

ANT3_DIO04

ANT3_DIO05

ANT3_DIO06

ANT3_DIO07

ANT3_DIO08

ANT3_DIO09

ANT3_DIO10

ANT3_DIO11

Data

AA22

AB23

Y21

I/O

O

X2VDD

—

2

AB25

W21

V21

AA23

AA25

Y22

Y24

—

Y23

ANT3_DO00//

AE24

GPIO46

ANT3_DO01/

TDM_TFS/

GPIO47

Data

AD22

AE23

AE22

AC22

O

X2VDD

—

ANT3_DO02/

TDM_RXD/

GPIO48

ANT3_DO03/

TDM_TXD/

GPIO49

ANT3_DO04/

TDM_RCK/

GPIO50/

IRQ00

ANT3_DO05/

TDM_RFS/

GPIO51/

Data

AB21

AC23

AD25

AA21

O

X2VDD

—

IRQ01

ANT3_DO06/

TRIG_IN/

GPIO52/

IRQ02

ANT3_DO07/

SRESET_B/

GPIO53/

IRQ03

ANT3_DO08/

MCP_B/

GPIO54

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

28

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Number

Type

Power

Note

Signal

ANT3_DO09/

CKSTP_IN_B/

GPIO55

Signal Description

Supply

Data

AD23

O

X2VDD

—

ANT3_DO10/

CKSTP_OUT_B/

GPIO56

AC25

AC24

ANT3_DO11/

IRQ_OUT_B/

GPIO57

RF Serial (MaxPHY) Interface

MAX1_TX_I

Data (pos)

Data (neg)

Data (pos)

Data (neg)

Data (pos)

Data (neg)

Data (pos)

Data (neg)

Data (pos)

Data (neg)

Data (pos)

Data (neg)

Data (pos)

Data (neg)

Data (pos)

Data (neg)

Data (pos)

Data (neg)

Data (pos)

Data (neg)

Clock

L21

K21

G22

G23

F24

F25

J24

J25

G24

G25

J22

J23

H24

H25

F21

G21

H21

J21

K24

K25

L24

L25

O

I

RVDD

—

MAX1_TX_I_B

MAX1_TX_Q

MAX1_TX_Q_B

MAX2_TX_I

MAX2_TX_I_B

MAX2_TX_Q

MAX2_TX_Q_B

MAX3_TX_I

MAX3_TX_I_B

MAX3_TX_Q

MAX3_TX_Q_B

MAX1_RX_I

MAX1_RX_I_B

MAX1_RX_Q

MAX1_RX_Q_B

MAX2_RX_I

I

MAX2_RX_I_B

MAX2_RX_Q

MAX2_RX_Q_B

MAX_TX_CLK

MAX_TX_CLK_B

I

O

Clock (complement)

Programmable Interrupt Controller over USB

USB_STP/

IRQ_OUT_B/

GPO73

Interrupt Output

AA8

AB9

O

I

CVDD

—

USB_D04/

GPIO00/

IRQ00

External Interrupt

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

29

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

USB_D03/

GPIO01/

IRQ01

External Interrupt

AC9

I

CVDD

—

USB_D00/

IRQ02

External Interrupt

AE7

AD8

I

CVDD

—

USB_NXT/

GPIO03/

IRQ03/

TRIG_IN

USB_CLK/

UART_SIN02/

GPIO69/

External Interrupt

AD7

I

CVDD

—

IRQ11/

TIMER03

Programmable Interrupt Controller over TSEC2

TSEC2_TXD02/

GPIO04/

IRQ04/

External Interrupt

AC15

I

LVDD

—

USB_D06

TSEC2_TXD03/

GPIO05/

IRQ05/

AB15

AB18

AE17

USB_D05

TSEC2_RX_CLK/

GPIO06/

IRQ06/

I

USB_CLK

TSEC2_GTX_CLK125/

GPIO07/

I/O

IRQ07/

USB_DIR

Programmable Interrupt Controller over IFC

IFC_AD14/

GPIO40/

IRQ06

External Interrupt

E14

D15

C10

D11

I

BVDD

—

IFC_AD13/

GPIO39/

IRQ07

IFC_AD11/

GPIO37/

IRQ08

IFC_AD12/

GPIO38/

IRQ09

Programmable Interrupt Controller over ANT1

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

30

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

ANT1_DIO08/

MAX1_LOCK/

ANT2_DO08/

GPIO21/

Signal Description

Number

Supply

External Interrupt

D24

I

X1VDD

—

IRQ08

ANT1_DIO09/

MAX2_LOCK/

ANT2_DO09/

GPIO22/

External Interrupt

C25

D23

E21

IRQ09

ANT1_DIO06/

SPI4_CLK/

ANT2_DO06/

GPIO87/

IRQ10

ANT1_DIO07/

SPI4_CS0_B/

ANT2_DO07/

GPIO88/

IRQ11

Programmable Interrupt Controller over ANT3

ANT3_DO11/

IRQ_OUT_B/

GPIO57

Interrupt Output

AC24

O

I

X2VDD

—

ANT3_DO04/

TDM_RCK/

GPIO50/

External Interrupt

AC22

IRQ00

ANT3_DO05/

TDM_RFS/

GPIO51/

External Interrupt

AB21

AC23

AD25

AA21

I

X2VDD

—

IRQ01

ANT3_DO06/

TRIG_IN/

GPIO52/

IRQ02

External Interrupt

ANT3_DO07/

SRESET_B/

GPIO53/

External Interrupt

IRQ03

ANT3_DO08/

MCP_B/

Machine check processor

GPIO54

Programmable Interrupt Controller over UART

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

31

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

UART_CTS_B00/

SIM_PD/

External Interrupt

D8

I

OVDD

—

DSP_TMS/

GPIO42/

IRQ04

UART_CTS_B01/

SI\M_PD/

SRESET_B/

GPIO44/

External Interrupt

E8

I

OVDD

—

IRQ05

Programmable Interrupt Controller over SDHC

SDHC_DATA03/

TDM_RXD/

GPIO79/

C20

I

BVDD

IRQ10

DMA over TSEC2

TSEC2_TXD00/

DMA_DACK_B00/

USB_NXT

DMA Acknowledge

DMA Request

DMA Done

AA14

AD17

AA15

O

I

LVDD

—

TSEC2_RXD00/

DMA_DREQ_B00/

USB_D04

TSEC2_TXD01/

DMA_DDONE_B00/

USB_D07

O

DMA over ANT2

ANT2_TXNRX/

DMA_DACK_B00

DMA Acknowledge

DMA Done

P23

P25

T25

O

I

X2VDD

—

ANT2_RX_FRAME/

DMA_DREQ_B00

ANT2_TX_FRAME/

DMA Request

O

DMA_DDONE_B00

GPIO

USB_D04/

GPIO00/

IRQ00

General Purpose I/O

AB9

AC9

AD6

I/O

CVDD

—

USB_D03/

GPIO01/

IRQ01

USB_DIR/

GPIO02/

TIMER01/

MCP_B

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

32

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

Signal Description

Number

Supply

USB_NXT/

GPIO03/

IRQ03/

General Purpose I/O

AD8

I/O

CVDD

LVDD

X1VDD

—

TRIG_IN

TSEC2_TXD02/

GPIO04/

IRQ04/

General Purpose I/O

AC15

AB15

AB18

AE17

D24

USB_D06

TSEC2_TXD03/

GPIO05/

IRQ05/

USB_D05

TSEC2_RX_CLK/

GPIO06/

IRQ06/

USB_CLK

TSEC2_GTX_CLK125/

GPIO07/

IRQ07/

USB_DIR

ANT1_DIO08/

MAX1_LOCK/

ANT2_DO08/

GPIO21/

IRQ08

ANT1_DIO09/

MAX2_LOCK/

ANT2_DO09/

GPIO22/

General Purpose I/O

C25

I/O

X1VDD

—

IRQ09

ANT1_DIO10/

TIMER06/

ANT2_DO10/

GPIO23

General Purpose I/O

B25

C23

I/O

X1VDD

—

ANT1_DIO11/

TIMER07/

ANT2_DO11/

GPIO24

ANT2_DIO00/

USB_D00/

GPIO25

General Purpose I/O

T24

U25

R22

I/O

X2VDD

—

ANT2_DIO01/

USB_D01/

GPIO26

ANT2_DIO02/

USB_D02/

GPIO27

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

33

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

ANT2_DIO03/

USB_D03/

GPIO28

General Purpose I/O

R23

I/O

X2VDD

—

ANT2_DIO04/

USB_D04/

GPIO29

General Purpose I/O

N25

N24

P21

N23

N21

—

ANT2_DIO05/

USB_D05/

GPIO30

ANT2_DIO06/

USB_D06/

GPIO31

ANT2_DIO07/

USB_D07/

GPIO32

ANT2_DIO08/

USB_DIR/

GPIO33

IFC_AD08/

GPIO34

General Purpose I/O

E13

A10

A12

C10

I/O

BVDD

—

IFC_AD09/

GPIO35

IFC_AD10/

GPIO36

IFC_AD11/

GPIO37/

IRQ08

IFC_AD12/

GPIO38/

IRQ09

General Purpose I/O

D11

D15

E14

C13

D8

I/O

BVDD

OVDD

—

IFC_AD13/

GPIO39/

IRQ07

IFC_AD14/

GPIO40/

IRQ06

IFC_AD15/

GPIO41/

TIMER02

UART_CTS_B00/

SIM_PD/

DSP_TMS/

GPIO42/

IRQ04

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

34

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

UART_CTS_B01/

Signal Description

Number

Supply

General Purpose I/O

E8

I/O

OVDD

—

SIM_PD/

SRESET_B/

GPIO44/

IRQ05

ANT3_DO00/

TDM_TCK/

GPIO46

General Purpose I/O

AE24

AD22

AE23

AE22

AC22

I/O

X2VDD

—

ANT3_DO01/

TDM_TFS/

GPIO47

ANT3_DO02/

TDM_RXD/

GPIO48

ANT3_DO03/

TDM_TXD/

GPIO49

ANT3_DO04/

TDM_RCK/

GPIO50/

IRQ00

ANT3_DO05/

TDM_RFS/

GPIO51/

General Purpose I/O

AB21

AC23

AD25

I/O

X2VDD

—

IRQ01

ANT3_DO06/

TRIG_IN/

GPIO52/

IRQ02

ANT3_DO07/

SRESET_B/

GPIO53/

IRQ03

ANT3_DO08/

MCP_B/

GPIO54

General Purpose I/O

AA21

AD23

AC25

AC24

I/O

X2VDD

—

ANT3_DO09/

CKSTP_IN_B/

GPIO55

ANT3_DO10/

CKSTP_OUT_B/

GPIO56

ANT3_DO11/

IRQ_OUT_B/

GPIO57

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

35

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

ANT2_DIO09/

USB_CLK/

GPIO59

General Purpose I/O

L23

I/O

X2VDD

CVDD

—

ANT2_DIO10/

USB_NXT/

GPIO60

General Purpose I/O

M23

L22

—

ANT2_DIO11/

TIMER08/

GPIO61

USB_D06/

UART_CTS_B02/

GPIO62

AB10

AE6

AD7

USB_D05/

UART_RTS_B02/

GPIO63

USB_CLK/

UART_SIN02/

GPIO69/

IRQ11/

TIMER03

USB_D07/

UART_SOUT02/

GPIO70

General Purpose I/O

AE8

AC8

AD9

D20

I/O

CVDD

BVDD

—

USB_D02/

IIC2_SDA/

GPIO71

USB_D01/

IIC2_SCL/

GPIO72

SDHC_DATA01/

SIM_SVEN/

TDM_RCK/

GPIO77

SDHC_DATA02/

TDM_TXD/

GPIO78

General Purpose I/O

B20

C20

I/O

BVDD

—

SDHC_DATA03/

TDM_RXD/

GPIO79/

IRQ10

ANT1_RX_FRAME/

MAX3_LOCK/

GPIO80

General Purpose I/O

A24

E24

I/O

X1VDD

—

ANT1_DIO00/

SPI3_MOSI/

ANT2_DO00/

GPIO81

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

36

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

ANT1_DIO01/

Signal Description

Number

Supply

General Purpose I/O

E25

I/O

X1VDD

—

SPI3_MISO/

ANT2_DO01/

GPIO82

ANT1_DIO02/

SPI3_CLK/

ANT2_DO02/

GPIO83

General Purpose I/O

F22

E23

E22

D25

D23

ANT1_DIO03/

SPI3_CS0_B/

ANT2_DO03/

GPIO84

ANT1_DIO04/

SPI4_MOSI/

ANT2_DO04/

GPIO85

ANT1_DIO05/

SPI4_MISO/

ANT2_DO05/

GPIO86

ANT1_DIO06/

SPI4_CLK/

ANT2_DO06/

GPIO87/

IRQ10

ANT1_DIO07/

SPI4_CS0_B/

ANT2_DO07/

GPIO88/

General Purpose I/O

E21

I/O

X1VDD

—

IRQ11

ANT2_RX_CLK/

GPIO91

General Purpose I/O

J3

I/O

X2VDD

X1VDD

—

ANT1_RX_CLK/

TIMER05/

B23

TSEC_1588_TRIG_IN2/

GPIO95

GPO

IFC_ADDR16/

GPO08

General Purpose Output

C14

A14

B15

A18

O

BVDD

—

IFC_ADDR17/

GPO09

IFC_ADDR18/

GPO10

IFC_ADDR19/

GPO11

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

37

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

IFC_ADDR20/

GPO12

General Purpose Output

A15

O

BVDD

X1VDD

OVDD

—

IFC_ADDR21/

GPO13

General Purpose Output

A13

C17

C16

A16

B16

D17

D21

A6

—

IFC_ADDR22/

GPO14

IFC_ADDR23/

GPO15

IFC_ADDR24/

GPO16

IFC_ADDR25/

GPO17

IFC_ADDR26/

GPO18

ANT1_TX_FRAME/

GPO20

UART_RTS_B00/

PWM2/

DSP_TCK/

GPO43

UART_RTS_B01/

PPS_LED/

General Purpose Output

C6

O

OVDD

—

GPO45

ANT3_AGC/

GPO58

General Purpose Output

V25

C19

D18

A20

O

X2VDD

BVDD

—

IFC_CS_B01/

GPO64

IFC_CS_B02/

GPO65

IFC_WP_B/

GPO66/

DSP_TDI

IFC_BCTL/

GPO67/

General Purpose Output

B18

O

BVDD

—

DSP_TDO

IFC_CLK00/

GPO68

General Purpose Output

C18

AA8

O

BVDD

CVDD

—

USB_STP/

IRQ_OUT_B/

GPO73

SPI1_CS1_B/

UART_SOUT03/

GPO74

General Purpose Output

AD4

O

CVDD

—

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

38

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

SPI1_CS2_B/

Signal Description

Number

Supply

General Purpose Output

AE5

O

CVDD

—

CKSTP_OUT_B/

GPO75

SPI1_CS3_B/

ANT_TCXO_PWM/

GPO76

General Purpose Output

AD5

O

CVDD

—

ANT2_AGC/

GPO89

General Purpose Output

M21

M25

P24

O

X2VDD

—

ANT2_TX_CLK/

GPO90

ANT2_ENABLE/

USB_STP/

GPO92

SPI2_CS2_B/

GPO93

General Purpose Output

V24

T21

O

X2VDD

—

SPI2_CS3_B/

GPO94

Analog

MVREF

DDR Reference Voltage

M8

AE9

AE12

H17

AB5

AA6

I

GVDD/2

—

8

TEMP_ANODE

TEMP_CATHODE

SENSEVDD

SENSEVDDC

SENSEVSS

Temperature Diode Anode

Temperature Diode Cathode

VDD Sensing Pin—MAPLE

VDD Sensing Pin

—

Internal Diode

8

—

13

GND Sensing Pin

Reset Configuration

EC_MDC/cfg_dsp_pll[0]

DSP Subsystem PLL Configurations

AE18

C14

I

LVDD

BVDD

20

IFC_ADDR16/

GPO08/cfg_dsp_pll[1]

IFC_ADDR17/

GPO09/cfg_dsp_pll[2]

DSP Subsystem PLL Configurations

A14

B15

I

BVDD

20

IFC_ADDR18/

GPO10/cfg_dsp_pll[3]

TSEC1_TXD00/cfg_rom_loc[0] Boot ROM Location

TSEC1_TXD01/cfg_rom_loc[1] Boot ROM Location

TSEC1_TXD02/cfg_rom_loc[2] Boot ROM Location

TSEC1_TXD03/cfg_rom_loc[3] Boot ROM Location

AE11

AC10

AC12

AE15

B10

I

LVDD

BVDD

20

21

IFC_AD00/cfg_sys_pll[0]

IFC_AD01/cfg_sys_pll[1]

IFC_AD02/cfg_sys_pll[2]

IFC_AD03/cfg_core_pll[0]

CCB Clock PLL Ratio

e500 Core PLL Ratio

C11

D12

C12

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

39

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

IFC_AD04/cfg_core_pll[1]

IFC_AD05/cfg_core_pll[2]

IFC_AD06/cfg_core_speed

IFC_AD07/cfg_ddr_pll[0]

e500 Core PLL Ratio

A11

B12

B13

D14

C17

I

BVDD

21

20

21

e500 Core PLL Ratio

Core Speed

DDR Complex Clock PLL Ratio

IFC_ADDR22/

GPO14/cfg_ddr_pll[1]

IFC_ADDR19/

GPO11/cfg_boot_seq[0]

Boot Sequencer Configuration

A18

I

BVDD

LVDD

20

TSEC_1588_PULSE_OUT1/

AC19

PPS_OUT/cfg_boot_seq[1]

IFC_OE_B/cfg_cpu_boot

CPU Boot Configuration

DDR Speed

E16

A16

I

BVDD

20

IFC_ADDR24/

GPO16/cfg_ddr_speed[0]

UART_SOUT00/

DDR Speed

F5

I

OVDD

20

cfg_ddr_speed[1]

IFC_AVD/cfg_dram_type

DDR DRAM Type

E17

A19

V25

I

BVDD

20

IFC_WE_B/cfg_ifc_adm_mode IFC Address Shift Mode Configuration

ANT3_AGC/

IFC Flash Mode Configuration

X2VDD

GPO58/cfg_ifc_flash_mode

SPI2_MOSI/cfg_ifc_ecc[0]

IFC ECC Enable Configuration

R21

E5

I

X2VDD

OVDD

BVDD

20

UART_SOUT01/cfg_ifc_ecc[1] IFC ECC Enable Configuration

IFC_ADDR23/

GPO15/cfg_ifc_pb[0]

IFC Pages Per Block

Platform Speed

C16

IFC_ADDR25/

GPO17/cfg_ifc_pb[1]

B16

D17

A15

A13

M21

I

BVDD

X2VDD

20

IFC_ADDR26/

GPO18/cfg_ifc_pb[2]

IFC_ADDR20/

GPO12/cfg_plat_speed

IFC_ADDR21/

GPO13/cfg_sys_speed

System Speed

ANT2_AGC/

Power Architecture DDR Mode

GPO89/

cfg_ddr_half_full_mode

IFC_CLE/cfg_tsec1_prctl

eTSEC1 Protocol

C15

I

BVDD

20

Power Supply

AVDD_PLAT

AVDD_CORE

AVDD_DDR

AVDD_DSP

Platform PLL Supply

Core PLL Supply

DDR PLL Supply

DSP PLL Supply

V9

V10

H8

—

AVDD_PLAT

AVDD_CORE

AVDD_DDR

AVDD_DSP

—

N18

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

40

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

Signal Description

Number

Supply

AVDD_RF

POVDD1

POVDD2

RF PLL Supply

M17

N8

—

AVDD_RF

POVDD1

—

7

Secure Fuse Programming Overdrive

Central Fuse Programming Overdrive—Power

Architecture

L8

POVDD3

FA_VDD

VDDC

Central Fuse Programming Overdrive—DSP

POSt VDD

AA10

U9

—

7

—

6

Core/Platform Supply

T10

J9

VDDC

—

J11

J13

J15

K10

K12

L9

L11

L13

M10

M12

N9

N11

N13

P10

P12

P14

P16

R9

R11

R13

R15

R17

T12

T14

T16

U11

U13

U15

U17

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

41

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

VDD

MAPLE Supply

J17

K14

K16

L15

L17

M14

M16

N15

N17

H5

—

VDD

—

VDD

MAPLE Supply

VDD

MAPLE Supply

VDD

MAPLE Supply

VDD

MAPLE Supply

VDD

MAPLE Supply

VDD

MAPLE Supply

VDD

MAPLE Supply

VDD

MAPLE Supply

VDD

GVDD

LVDD

BVDD

CVDD

DDR Supply

GVDD

LVDD

BVDD

CVDD

DDR Supply

P8

DDR Supply

R8

DDR Supply

T8

DDR Supply

U8

DDR Supply

V8

DDR Supply

J8

DDR Supply

K8

DDR Supply

L5

DDR Supply

P5

DDR Supply

U5

DDR Supply

Y5

Ethernet Supply

V12

V14

V15

V16

V17

E12

E15

E18

H12

H13

H14

H15

H16

V11

Ethernet Supply

IFC, eSDHC, USIM, TDM Supply

USB, eSPI, DUART, UART, I2C, USIM, PWM

Supply

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

42

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Number

Type

Power

Note

Signal

Signal Description

Supply

CVDD

USB, eSPI, DUART, UART, I2C, USIM, PWM

Supply

V13

—

CVDD

—

USB, eSPI, DUART, UART, I2C, USIM, PWM

Supply

AA7

AA9

USB, eSPI, DUART, UART, I2C, USIM, PWM

Supply

USB, eSPI, DUART, UART, I2C, USIM, PWM

Supply

AB14

AA17

AC7

USB, eSPI, DUART, UART, I2C, USIM, PWM

Supply

USB, eSPI, DUART, UART, I2C, USIM, PWM

Supply

USB, eSPI, DUART, UART, I2C, USIM, PWM

Supply

AC11

OVDD

X1VDD

X2VDD

RVDD

DUART1, System, I2C, PWM, JTAG Supply

eSPI, RF Supply

B4

E6

—

OVDD

X1VDD

X2VDD

RVDD

—

E9

H9

H10

A23

D22

H18

J18

eSPI, RF Supply

eSPI, USB, TDM, RF Supply

RF Supply

P18

R18

T18

U18

V18

V23

AB22

AE21

H23

K18

L18

M18

RVDD

RF Supply

RVDD

RF Supply

RVDD

RF Supply

RVDD

Ground

VSS

Platform and Core Ground

A25

B3

—

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

43

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

VSS

Platform and Core Ground

B8

B11

B14

B17

B19

C21

C24

D2

—

VSS

Platform and Core Ground

D7

D10

D13

D16

E4

F23

G2

H22

J4

J10

J12

J14

J16

K15

K17

K22

K2

K9

K11

K13

L10

L12

L14

L16

M4

M9

M11

M13

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

44

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

Signal Description

Number

Supply

VSS

Platform and Core Ground

M15

M24

N2

—

Platform and Core Ground

Platform and Core ground

Platform and Core Ground

N10

N12

N14

N16

N22

P9

P11

P13

P15

P17

R25

R24

R16

R14

R4

R10

R12

T2

T9

T11

T13

T15

T17

T22

U14

U16

U10

U12

V4

W22

W2

AA24

AA20

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

45

Pin Assignments

Signal

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Supply

Signal Description

Note

Number

VSS

Platform and Core Ground

AA11

AB2

—

VSS

Platform and Core Ground

AB8

AB13

AB16

AB19

AB20

AC4

AC21

AD2

AD10

AD12

AD15

AD18

AD21

AD24

AE25

AE1

AE4

No Connect

NC

No connect

AB11

AE10

AD19

AD20

AC20

AE14

—

12

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

46

Freescale Semiconductor

Pin Assignments

Table 1. BSC9131 Pinout Listing (continued)

Type

Power

Note

Signal

Signal Description

Number

Supply

NC

No connect

AE20

K23

—

12

NC

1

This is a test signal for factory use only and must be pulled up (with 100 Ω –1 kΩ) to OVDD for normal operation.

2

This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the reset

state. This pull-up is designed such that it can be overpowered by an external 4.7 kΩ pull-down resistor. However, if the signal is

intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a

pull-up or active driver is needed.

3

4

5

This pin has a weak (~20 kΩ) internal pull-up P-FET that is always enabled.

This pin must NOT be pulled down during power-on reset.

This pin is an open-drain signal.Recommend that a pull-up resistor (1 kΩ to 4.7 kΩ) be placed on this pin to the respective power

supply.

6

7

This pin should be pulled down to VSS with 10 kΩ.

This pin is used for fuse programming. Should be tied to VSS for normal operation (fuse read). See section Section 2.2, “Power

Sequencing,” for more details.

8

This pin may be connected to a temperature diode monitoring device such as the Analog Devices, ADT7461A™ or similar. If a

temperature diode monitoring device will not be connected, these pins may be connected to test point or left as a no connect.

9

Pin should be pulled high or low depending on the JTAG topology selected. Refer to Section 3.9, “JTAG Configuration Signals.”

¹⁰This pin should be tied to GND/VSS when MAPLE is powered down, otherwise it should be tied to OVDD. Also with MAPLE

module off, AIC (RF interfaces) and SPI2 modules are disabled.

¹¹.It has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such

that it can be overpowered by an external 4.7 kΩ pull-down resistor. However, if thesignal is intended to be high after reset, and

if there is any device on the net which might pull down the value of the net at reset, then a pull-up or active driver is needed.

¹²Do not connect.These pins should be left floating.

¹³These pins are connected to the same global power and ground (VDD, VDDC and GND) nets internally and may be connected

as a differential pair to be used by the voltage regulators with remote sense function.

¹⁴Recommend that a weak pull-up resistor (4.7 kΩ to 20 kΩ) be placed on this pin to the respective power supply.

¹⁵Recommend that a weak pull-down resistor (4.7 kΩ) be placed on this pin.

¹⁶Recommend that a weak pull-up resistor (10 to 100 kΩ) be placed on this pin to the respective power supply.

¹⁷MDIC00 is grounded through an 36.5 Ω precision 1% resistor and MDIC01 is connected to GVDD through an 36.5 Ω precision

1% resistor. These pins are used for automatic calibration of the DDR3/DDR3L IOs.

¹⁸Recommend that a weak pull-up resistor (4.7 kΩ) be placed on this pin.

¹⁹When TEST_SEL_B is low the SPI2 I/F is disable.

²⁰Reset configuration default value is 1due to weak internal pull-up.

²¹Reset configuration value doesn’t have default.

²²Recommend that a weak pull-up resistor (4.7 kΩ to 20 kΩ) be placed on this pin to the respective power supply if it connected

to an external device.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

47

Electrical Characteristics

2

Electrical Characteristics

This section provides the AC and DC electrical specifications. This device is currently targeted to these specifications. Some

of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O

buffer design specifications.

2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1

Absolute Maximum Ratings

This table provides the absolute maximum ratings.

1

Table 2. Absolute Maximum Ratings

Characteristic

Symbol

Max Value

Unit Note

Platform supply voltage

MAPLE-B2F supply voltage

PLL supply voltage

V_DDC

V_DD

–0.3 to 1.05

V

—

2

AV_{DD_CORE}

AV_{DD_DDR}

AV_{DD_PLAT}

AV_{DD_DSP}

AV_{DD_RF}

Fuse programming supply

POV_DD1

POV_DD2

POV_DD3

–0.3 to 1.65

V

—

DDR3/DDR3L DRAM I/O voltage

GV_DD

LV_DD

BV_DD

–0.3 to 1.65

–0.3 to 1.45

V

—

3

Three-speed Ethernet, Ethernet management (eTSEC) and 1588,

USB

–0.3 to 3.63

–0.3 to 2.75

IFC, eSDHC, USIM, TDM

–0.3 to 3.63

–0.3 to 2.75

–0.3 to 1.98

DUART1, SYSCLK, system control and power management, I²C1,

PWM2, clocking, I/O voltage select, and JTAG I/O voltage

OV_DD

CV_DD

X1V_DD

X2V_DD

RV_DD

–0.3 to 3.63

V

—

3, 4

—

USB, eSPI1, DUART2, I²C2, USIM, PWM1

eSPI3, eSPI4, RF parallel interface

eSPI2, USB, TDM, RF parallel interface

RF serial MaxPHY interface

–0.3 to 3.63

–0.3 to 1.98

–0.3 to 3.63

–0.3 to 1.98

–0.3 to 3.63

–0.3 to 1.98

—

–0.3 to 1.65

—

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

48

Freescale Semiconductor

Electrical Characteristics

1

Table 2. Absolute Maximum Ratings (continued)

Characteristic

Symbol

Max Value

Unit Note

Input voltage DDR3/DDR3L DRAM signals

DDR3/DDR3L DRAM reference

MV_IN

–0.3 to (GV_DD+ 0.3)

V

5, 10

10

MV_REF

–0.3 to (GV_DD/2 +

0.3)

Ethernet, USB signals

LV_IN

BV_IN

OV_IN

–0.3 to (LV_DD+ 0.3)

–0.3 to (BV_DD+ 0.3)

–0.3 to (OV_DD+ 0.3)

V

—

V

6, 10

7, 10

8, 10

IFC, eSDHC, USIM, TDM signals

DUART1, SYSCLK, system control and power

management, I²C1, PWM2, clocking, I/O voltage

select, and JTAG I/O voltage

USB, eSPI1, DUART2, I²C2, USIM, PWM1

eSPI3, eSPI4, RF parallel interface

eSPI2, USB, TDM, RF parallel interface

RF serial MaxPHY interface

CV_IN

X1V_IN

X2V_IN

RV_IN

–0.3 to (CV_DD+ 0.3)

–0.3 to (X1V_DD+ 0.3)

–0.3 to (X2V_DD+ 0.3)

–0.3 to (RV_DD+ 0.3)

–55 to 150

V

4, 10

9, 10

10

V

Storage temperature range

T_STG

°C

—

Note:

1

Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional

operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent

damage to the device.

2

3

AV_DDis measured at the input to the filter and not at the pin of the device.

USIM pins are multiplexed with the pins of other interfaces. Check Table 3 for which power supply is used (BV_DDor a CV_DD

for each particular USIM pin.

)

4

5

6

7

8

9

Caution: CV_INmust not exceed CV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on

reset and power-down sequences.

Caution: MV_INmust not exceed GV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on

reset and power-down sequences.

Caution: LV_INmust not exceed LV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on

reset and power-down sequences.

Caution: BV_INmust not exceed BV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on

reset and power-down sequences.

Caution: OV_INmust not exceed OV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on

reset and power-down sequences.

Caution: X[1-2]V_INmust not exceed X[1-2]V_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

¹⁰(C,X,B,G,L,O,R)V_DDand MV_REFmay overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 7.

2.1.2

Recommended Operating Conditions

This table provides the recommended operating conditions for this device. Note that the values in this table are the

recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed.

Table 3. Recommended Operating Conditions

Characteristic

Symbol

Recommended Value Unit Note

Platform supply voltage

V_DDC

V_DD

1 + 50 mV / – 30mV

V

1

MAPLE-B2F supply voltage

—

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

49

Electrical Characteristics

Table 3. Recommended Operating Conditions (continued)

Characteristic

Symbol

Recommended Value Unit Note

PLL supply voltage

Fuse supply voltage

AV_{DD_CORE}

AV_{DD_DDR}

AV_{DD_PLAT}

AV_{DD_DSP}

AV_{DD_RF}

1 + 50 mV / – 30mV

V

1

POV_DD1

1.5 V 75 mV

V

1

DDR3 DRAM I/O voltage

DDR3L DRAM I/O voltage

GV_DD

—

1.35 V +100mV/

–67mV

Three-speed Ethernet, Ethernet management (eTSEC) and 1588,

USB

DUART1, SYSCLK, system control and power management, I²C1,

PWM2, clocking, I/O voltage select, and JTAG I/O voltage

LV_DD

OV_DD

BV_DD

3.3 V 165 mV

2.5 V 125 mV

V

—

2

3.3 V 165 mV

IFC, eSDHC, USIM, TDM

3.3 V 165 mV

2.5 V 125 mV

1.8 V 90 mV

USB, eSPI1, DUART2, I²C2, USIM, PWM1

eSPI3, eSPI4, RF parallel interface

eSPI2, USB, TDM, RF parallel interface

RF serial MaxPHY Interface

CV_DD

X1V_DD

X2V_DD

3.3 V 165 mV

1.8 V 90 mV

V

2

3.3 V 165 mV

1.8 V 90 mV

—

3.3 V 165 mV

1.8 V 90 mV

RV_DD

MV_IN

MV_REF

LV_IN

1.5 V 75 mV

GND to GV_DD

GND to GV_DD/2

GND to LV_DD

GND to BV_DD

GND to OV_DD

V

—

Input voltage

DDR3/DDR3L DRAM

DDR3/DDR3L DRAM reference

Ethernet, USB

IFC, eSDHC, TDM signals

BV_IN

DUART1, SYSCLK, system control and power

management, eSPI, I²C1, USIM, PWM2,

clocking, I/O voltage select, and JTAG I/O

voltage

OV_IN

USB, eSPI, eSDHC, DUART2, I²C2, USIM,

PWM1

CV_IN

GND to CV_DD

V

—

eSPI3, eSPI4, RF parallel interface

eSPI2, USB, TDM, RF parallel interface

RF serial MaxPHY interface

X1V_IN

X2V_IN

RV_IN

GND to X1V_DD

GND to X2V_DD

GND to RV_DD

10

V

—

3

V

Maximum input capacitance

C_INMAX

pF

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

50

Freescale Semiconductor

Electrical Characteristics

Table 3. Recommended Operating Conditions (continued)

Characteristic

Standard

Symbol

Recommended Value Unit Note

Operating

Temperature

range

TA/TJ

TA = 0 (min) to

TJ = 105 (max)

°C

—

1

Extended

TA/TJ

TA = –40 (min) to

TJ = 105 (max)

Secure boot fuse programming

TA = 0 (min) to

TJ = 70 (max)

Note:

1

Caution: POV_DD1must be supplied 1.5 V and the device must operate in the specified fuse programming temperature range

only during secure boot fuse programming. For all other operating conditions, POV_DD1must be tied to GND, subject to the

power sequencing constraints shown in Section 2.2, “Power Sequencing.”

2

3

USIM pins are multiplexed with the pins of other interfaces. Check Table 3 for which power supply is used (BV_DDor a CV_DD

for each particular USIM pin.

)

Unless otherwise stated in an interface’s DC specifications, the maximum allowed input capacitance in this table is a general

recommendation for signals.

This figure shows the undershoot and overshoot voltages at the interfaces.

B/G/L/O/XV/RV_DD+ 20%

B/G/L/O/XV/RV_DD+ 5%

B/G/L/O/XV/RV_DD

V_IH

GND

GND – 0.3 V

V_IL

GND – 0.7 V

Not to Exceed 10%

1

of t_CLOCK

Note:

1. t_CLOCKrefers to the clock period associated with the respective interface:

For I²C and JTAG, t_CLOCKreferences SYSCLK.

For DDR, t_CLOCKreferences MCLK.

For eTSEC, t_CLOCKreferences TSECn_GTX_CLK125.

For IFC, t_CLOCKreferences IFC_CLK.

Figure 7. Overshoot/Undershoot Voltage for BV /GV /LV /OV /X1V /X2V /RV

DD

The core voltage must always be provided at nominal 1 V (see Table 3 for actual recommended core voltage). Voltage to the

processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 3.

The input voltage threshold scales with respect to the associated I/O supply voltage. OV and LV based receivers are simple

DD

CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR3 SDRAM interface uses a differential

receiver referenced the externally supplied MV signal (nominally set to GV /2). The DDR DQS receivers cannot be

REF

DD

operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

51

Electrical Characteristics

2.1.3

Output Driver Characteristics

This table provides information on the characteristics of the output driver strengths. The values are preliminary estimates.

Table 4. Output Drive Capability

Driver Type

IFC, GPIO[0:7], eSDHC, TDM

Output Impedance (Ω)

47

16

Supply Voltage

Note

7

BV_DD= 3.3/2.5/1.8 V

GV_DD= 1.5 V DDR3

—

1

DDR3 (programmable)

32 (half strength mode) GV_DD= 1.35 V DDR3L

eTSEC, USB

47

7

LV_DD= 3.3/2.5 V

OV_DD= 3.3 V

—

2

DUART1, system control, I²C1, USIM, PWM2, JTAG

USB, eSPI1, DUART2, I²C2, USIM, PWM1

eSPI3, eSPI4, RF parallel interface

eSPI2, USB, TDM, RF parallel interface

RF serial MaxPHY interface, DDR3 I/O

CV_DD= 3.3/1.8 V

X1V_DD= 3.3/1.8 V

X2V_DD= 3.3/1.8 V

RV_DD= 1.5 V

2

LVCMOS

—

20 (full strength mode)

40 (half strength mode)

Note:

1

The drive strength of the DDR3 interface in half-strength mode is at T_j= 125°C and at GV_DD(min).

USIM pins are multiplexed with the pins of other interfaces. Check Table 3 for which power supply is used (BV_DDor a CV_DD

for each particular USIM pin.

2

)

2.2

Power Sequencing

The device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These

requirements are as follows for power up:

1. VDD, VDDC, AVDD (all PLL supplies)

2. LVDD, BVDD, CVDD, OVDD, X1VDD, X2VDD, GVDD

3. For secure boot fuse programming: After deassertion of HRESET_B, drive POV

= 1.5 V after a required minimum

DD1

delay per Table 5. After fuse programming is completed, it is required to return POV

= GND before the system is

DD1

power cycled (HRESET_B assertion) or powered down (V

ramp down) per the required timing specified in

DDC

Table 5. See Section 3.11, “Security Fuse Processor,” for additional details.

WARNING

Only 100,000 POR cycles are permitted per lifetime of a device. Only one secure boot fuse

programming event is permitted per lifetime of a device.

No activity other than that required for secure boot fuse programming is permitted while

POV

driven to any voltage above GND, including the reading of the fuse block. The

DD1

reading of the fuse block may only occur while POV

= GND.

DD1

POV

and POV

are always tied to GND.

DD3

DD2

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

52

Freescale Semiconductor

Electrical Characteristics

This figure provides the POV

timing diagram.

DD1

1

Fuse programming

POV_DD1

V_DDC

10% POV

DD1

10% POV

DD1

90% V

t

DD_PL

POVDD_VDD

t

90% OV

DD

90% OV

POVDD_PROG

DD

HRESET_B

t

POVDD_RST

POVDD_DELAY

NOTE: POVDD must be stable at 1.5 V prior to initiating fuse programming.

Figure 8. POV Timing Diagram

DD1

This table provides information on the power-down and power-up sequence parameters for POV

.

DD1

5

Table 5. POV

Min

Timing

DD1

Driver Type

Max

Unit

t_SYSCLK

μs

Note

t_{POVDD_DELAY}

t_{POVDD_PROG}

t_{POVDD_VDD}

t_{POVDD_RST}

Note:

1500

—

1

2

3

4

0

μs

1. Delay required from the deassertion of HRESET_B to driving POV_DD1ramp up. Delay measured from HRESET_B deassertion

at 90% OV_DDto 10% POV_DD1ramp up.

2. Delay required from fuse programming finished to POV_DD1ramp down start. Fuse programming must complete while POV_DD1

is stable at 1.5 V. No activity other than that required for secure boot fuse programming is permitted while POV_DD1driven to

any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while

POV_DD1= GND. After fuse programming is completed, it is required to return POV_DD1= GND.

3. Delay required from POV_DD1ramp down complete to V_DDCramp down start. POV_DD1must be grounded to minimum

10% POV_DD1before V_DDCis at 90% V_DDC

4. Delay required from POV_DD1ramp down complete to HRESET_B assertion. POV_DD1must be grounded to minimum 10%

POV_DD1before HRESET_B assertion reaches 90% OV_DD

.

5. Only one secure boot fuse programming event is permitted per lifetime of a device.

All supplies must be at their stable values within 50 ms.

Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered

sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step

reach 10% of theirs.

In order to guarantee MCKE low during power-up, the above sequencing for GV is required. If there is no concern about any

DD

of the DDR signals being in an indeterminate state during power-up, the sequencing for GV is not required.

DD

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

53

Electrical Characteristics

2.3

Power-Down Requirements

The power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be

started.

2.4

RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements. Table 6 provides the

RESET initialization AC timing specifications.

Table 6. RESET Initialization Timing Specifications

Parameter

Min Max

Unit

Note

Required assertion time of HRESET_B

600

25

3

—

μs

ns

1, 2, 5

Minimum assertion time of TRESET_B simultaneous to HRESET_B assertion

Minimum assertion time for SRESET_B

3

4

t_SYSCLK

μs

PLL input setup time with stable SYSCLK before HRESET_B negation

25

4

—

4

Input setup time for POR configurations (other than PLL configuration) with respect to negation

of HRESET_B

t_SYSCLK

Input hold time for all POR configurations (including PLL configuration) with respect to

negation of HRESET_B

2

—

8

t_SYSCLK

4

Maximum valid-to-high impedance time for actively driven POR configurations with respect to

negation of HRESET_B

—

Note:

1. There may be some extra current leakage when driving signals high during this time.

2. Reset assertion timing requirements for DDR3 DRAMs may differ.

3. TRST is an asynchronous level sensitive signal. For guidance on how this requirement can be met, refer to the JTAG signal

termination guidelines in Section 3.9.1, “Termination of Unused Signals.”

4. SYSCLK is the primary clock input.

5. Reset initialization should start only after all power supplies are stable.

This table provides the PLL lock times.

Table 7. PLL Lock Times

Parameter

Min

Max

Unit

Note

PLL lock times

—

100

μs

—

2.5

Power-on Ramp Rate

This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum

power-on ramp rate is required to avoid falsely triggering the ESD circuitry. Table 8 provides the power supply ramp rate

specifications.

Table 8. Power Supply Ramp Rate

Parameter

Min

Max

Unit

Required ramp rate

Required ramp time

—

36000

50

V/s

ms

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

54

Freescale Semiconductor

Electrical Characteristics

Table 8. Power Supply Ramp Rate (continued)

Parameter

Min

Max

Unit

Note:

1. Ramp rate is specified as a linear ramp from 10 to 90% of the nominal voltage of the specific voltage supply.

2. All MCKE signals must remain low during the power up sequence.

2.6

Power Characteristics

This table shows the power dissipations of the V

and V supplies for various operating DSP and core complex bus clock

DD

DDC

(CCB_clk) frequencies versus the core and DDR clock frequencies.

Table 9. Core Power Dissipation

CCB PA DDR

PA Core

DSP Core

Power

Mode

V_DDCCore V_DDMAPLE Junction V_DDC+V_DD

Frequency Frequency Frequency Frequency

Note

(V)

Temp (°C) Power (W)

(MHz)

Typical

Thermal

Maximum

Typical

1000

500

800

1.0

65

3.4

5.0

5.9

3.0

4.4

5.2

1, 2

105

1, 3, 5

1, 4, 5

1, 2

800

400

800

1.0

65

Thermal

Maximum

Note:

105

1, 3, 5

1, 4, 5

1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and

configurations. The values do not include power dissipation for I/O supplies.

2. Typical power is an average value measured while running a typical use case, using the nominal process and recommended

core and platform (V_DDC) and MAPLE (V_DD) voltages at 65 °C junction temperature (see Table 3).

3. Thermal power is the power measured while running a 70% (cores) and 50% (platform) utilization case, using the worst case

process and recommended core and platform (V_DDC) and MAPLE (V_DD) voltages at maximum operating junction temperature

(see Table 3).

4. Maximum power is the maximum power measured while running a maximum power pattern, using the worst case process

and recommended core and platform (V_DDC) and MAPLE (V_DD) voltages at maximum operating junction temperature (see

Table 3).

5. An estimated I/O power while running a typical use case, using the nominal process and recommended voltages of 1 W (see

Table 3).

Table 10. I/O Power

width

Recommended Current

Typical

current (A)

Max

(A)

PS# Primary pin name

Voltage domain

Note

value

max

OVDD

BVDD

LVDD

37

46

32

19

General I/O supply

3.3V

0.178

0.097

0.051

0.030

0.710

0.098

0.266

0.148

0.076

0.045

—

3

Local Bus and GPIO I/O supply 1.8V/ 2.5V/ 3.3V

TSEC I/O supply

ULPI/SPI/UART/SIM I/O supply

DDR I/O supply

3.3V/ 2.5V

3.3V/ 1.8V

1.5V/ 1.35V

3.3V/ 1.8V

3

I/O

CVDD

GVDD

X1VDD

X2VDD

3

0.950 1, 2, 3

ANT1I/O supply

0.140

3

ANT2, ANT3 I/O supply

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

55

Electrical Characteristics

PS# Primary pin name

Table 10. I/O Power (continued)

width

Recommended Current

Typical

current (A)

Max

(A)

Voltage domain

Note

value

max

AVDD_CORE

AVDD_PLAT

AVDD_DDR

Core PLL supply

Platform PLL supply

DDR PLL supply

—

Analog

1.0 V

0.005

0.015

Note:

1

For DDR typical, it is 40% DIMM utilization.

For DDR max, it is 75% DIMM utilization.

2

3

For I/O with different possible voltages, the currents listed above are for the higher voltage.

2.7

Input Clocks

This section provides information about the system clock specifications, spread spectrum sources, real time clock

specifications, eTSEC gigabit reference clock specifications, TDM clock specifications, and other input sources.

2.7.1

System Clock and DDR Clock Specifications

This table provides the system clock (SYSCLK) and DDR clock (DDRCLK) 3.3 V DC specifications.

Table 11. SYSCLK/DDRCLK DC Electrical Characteristics

At recommended operating conditions with OV_DD= 3.3 V 165 mV

Parameter

Input high voltage

Symbol

Min

Typical

Max

Unit

Note

V_IH

V_IL

C_IN

I_IN

2.0

—

7

—

0.8

15

50

V

1

Input low voltage

Input capacitance

pf

—

2

Input current (V_IN= 0 V or V_IN= V_DDC)

Note:

—

μA

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 3.

This table provides the system clock (SYSCLK) and DDR clock (DDRCLK) AC timing specifications.

Table 12. SYSCLK/DDRCLK AC Timing Specifications

At recommended operating conditions with OV_DD= 3.3 V 165 mV

Parameter/Condition

SYSCLK frequency

Symbol

Min

Typ

Max

Unit

Note

f_SYSCLK

t_SYSCLK

f_DDRCLK

t_DDRCLK

66

7.5

66

—

100

10

MHz

ns

1, 2

1

SYSCLK cycle time

DDRCLK frequency

166

15.15

60

MHz

ns

DDRCLK cycle time

6.0

40

—

2

SYSCLK/DDRCLK duty cycle

t_KHK

/

%

t_{SYSCLK/DDRCLK}

SYSCLK/DDRCLK slew rate

—

1

—

4

V/ns

3

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

56

Freescale Semiconductor

Electrical Characteristics

Table 12. SYSCLK/DDRCLK AC Timing Specifications (continued)

At recommended operating conditions with OV_DD= 3.3 V 165 mV

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Note

SYSCLK/DDRCLK peak period jitter

—

150

500

ps

—

4

SYSCLK/DDRCLK jitter phase noise

at –56 dBc

kHz

AC Input Swing Limits at 3.3 V OV_DD

ΔV_AC

1.9

—

V

—

Note:

1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency do not exceed their

respective maximum or minimum operating frequencies.

2. Measured at the rising edge and/or the falling edge at OV_DD/2.

3. Slew rate as measured from 0.3 ΔV_ACat the center of peak to peak voltage at clock input.

4. Phase noise is calculated as FFT of TIE jitter.

2.7.2

DSP Clock (DSPCLKIN) Specifications

This table provides the DSP clock (DSPCLKIN) 3.3 V DC specifications.

Table 13. DSPCLKIN DC Electrical Characteristics

At recommended operating conditions with OV_DD= 3.3 V 165 mV

Parameter

Input high voltage

Symbol

Min

Typical

Max

Unit

Note

V_IH

V_IL

C_IN

I_IN

2.0

—

7

—

0.8

15

50

V

1

Input low voltage

Input capacitance

pf

—

2

Input current (V_IN= 0 V or V_IN= V_DDC)

Note:

—

μA

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 3.

This table provides the DSP clock (DSPCLKIN) AC timing specifications.

Table 14. DSPCLKIN AC Timing Specifications

At recommended operating conditions with OV_DD= 3.3 V 165 mV

Parameter/Condition

DSPCLKIN frequency

Symbol

Min

Typical

Max

Unit

Note

f_SYSCLK

t_SYSCLK

_KHK/ t_SYSCLK

—

66

7.5

40

1

—

133

10

MHz

ns

1, 2

2

DSPCLKIN cycle time

DSPCLKIN duty cycle

t

60

%

DSPCLKIN slew rate

4

V/ns

ps

3

DSPCLKIN peak period jitter

DSPCLKIN jitter phase noise at –56 dBc

AC Input Swing Limits at 3.3 V OV_DD

—

1.9

150

500

—

4

—

kHz

V

ΔV_AC

—

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

57

Electrical Characteristics

Table 14. DSPCLKIN AC Timing Specifications (continued)

At recommended operating conditions with OV_DD= 3.3 V 165 mV

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Note

Note:

1. Caution: The relevant clock ratio settings must be chosen such that the resulting DSPCLKIN frequency do not exceed their

respective maximum or minimum operating frequencies.

2. Measured at the rising edge and/or the falling edge at OV_DD/2.

3. Slew rate as measured from 0.3 ΔV_ACat the center of peak to peak voltage at clock input.

4. Phase noise is calculated as FFT of TIE jitter.

2.7.3

Spread Spectrum Sources

Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by

spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and

government requirements. These clock sources intentionally add long-term jitter in order to diffuse the EMI spectral content.

The jitter specification given in this table considers short-term (cycle-to-cycle) jitter only and the clock generator’s

cycle-to-cycle output jitter should meet the input cycle-to-cycle jitter requirement. Frequency modulation and spread are

separate concerns, and the device is compatible with spread spectrum sources if the recommendations listed in this table are

observed.

Table 15. Spread Spectrum Clock Source Recommendations

At recommended operating conditions. See Table 3.

Parameter

Min

Max

Unit

Note

Frequency modulation

Frequency spread

Note:

—

60

kHz

%

—

1.0

1, 2

1. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the

minimum and maximum specifications given in Table 95.

2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device

CAUTION

The processor’s minimum and maximum SYSCLK, core, and VCO frequencies must not

be exceeded regardless of the type of clock source. Therefore, systems in which the

processor is operated at its maximum rated e500 core frequency should avoid violating the

stated limits by using down-spreading only.

2.7.4

Real Time Clock Specifications

The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the

counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC

signal should be greater than 2x the period of the CCB clock. That is, minimum clock high time is 2 × t

, and minimum clock

CCB

low time is 2 × t

. There is no minimum RTC frequency; RTC may be grounded if not needed.

CCB

2.7.5

eTSEC Gigabit Reference Clock Specifications

Table 16 lists the eTSEC gigabit reference clock DC electrical characteristics.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

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Freescale Semiconductor

Electrical Characteristics

Table 16. eTSEC Gigabit Reference Clock DC Electrical Characteristics

Parameter

High-level input voltage

Symbol

Min

Max

Unit

Note

V_IH

V_IL

I_IN

1.7

—

0.8

40

V

1

2

Input low voltage

Input current (V_IN= 0 V or V_IN= V_DDC)

—

μA

Note:

1. The max V_IH, and min V_ILvalues can be found in Table 3.

2. The symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 3.

Table 17 provides the eTSEC gigabit reference clocks (TSECn_GTX_CLK125) AC timing specifications.

Table 17. TSECn_GTX_CLK125 AC Timing Specifications

At recommended operating conditions with LV_DD= 2.5 0.125 mV

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Note

TSECn_GTX_CLK125 frequency

TSECn_GTX_CLK125 cycle time

t_G125

—

125

8

—

MHz

ns

—

1

EC_GTX_CLK rise and fall time

LV_DD= 2.5 V

t

_G125R/t_G125F

—

ns

0.75

TSECn_GTX_CLK125 duty cycle

1000Base-T for RGMII

t_{G125H G125}

/t

—

%

2

47

—

53

TSECn_GTX_CLK125 jitter

—

150

ps

Note:

1. Rise and fall times for TSECn_GTX_CLK125 are measured from 0.5 and 2.0 V for LV_DD= 2.5 V and from 0.6 .

2. TSECn_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The

TSECn_GTX_CLK125 duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle

generated by the eTSEC GTX_CLK. See Section 2.11.1.2, “RMII and RGMII AC Timing Specifications,” for the duty cycle for

10Base-T and 100Base-T reference clock.

2.7.6

RF Parallel Interface Clock Specifications

The following table lists the RF parallel interface clock DC electrical characteristics.

Table 18. RF Parallel Reference Clock DC Electrical Characteristics

Parameter

Symbol

Min

Typical

Max

Unit

Note

Input high voltage

Input low voltage

Input capacitance

V_IH

V_IL

C_IN

I_IN

2.0

—

7

—

0.8

15

50

V

1

C

—

2

Input current (V_IN= 0 V or V_IN= V_DDC)

—

μA

Note:

1. The max V_IH, and min V_ILvalues can be found in Table 3.

2. The symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 3.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

59

Electrical Characteristics

The following table lists the RF parallel interface clock AC electrical characteristics.

Table 19. RF Parallel Reference Clock AC Electrical Characteristics

At recommended operating conditions with OV_DD= 3.3 V 165 mV

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Note

ANT_REF_CLK frequency

ANT_REF_CLK cycle time

ANT_REF_CLK duty cycle

ANT_REF_CLK slew rate

ANT_REF_CLK peak period jitter

AC Input Swing Limits at 3.3 V OV_DD

Note:

f_{ANT_REF_CLK}

t_{ANT_REF_CLK}

t_KHK/t_{ANT_REF_CLK}

—

48

1

19.2

52

50

—

52

4

MHz

ns

—

1

%

—

V/ns

ps

—

1.9

—

100

—

ΔV_AC

—

V

1. Slew rate as measured from 0.3 ΔV_ACat the center of peak to peak voltage at clock input.

2.7.7

RF Serial (MaxPHY) Interface Clock Specifications

Table 20 lists the RF serial (MaxPHY) interface clock DC electrical characteristics.

Table 20. RF Serial (MaxPHY) Reference Clock DC Electrical Characteristics

Parameter

Symbol

Min

Typical

Max

Unit

Note

Input high voltage

Input low voltage

Input capacitance

V_IH

V_IL

C_IN

I_IN

2.0

—

7

—

0.8

15

50

V

1

C

—

2

Input current (V_IN= 0 V or V_IN= V_DDC)

—

μA

Note:

1. The max V_IH, and min V_ILvalues can be found in Table 3.

2. The symbol V_IN, in this case, represents the OV_INsymbol referenced in Table 3.

Table 21 lists the RF serial (MaxPHY) interface clock AC electrical characteristics.

Table 21. RF Serial (MaxPHY) Reference Clock AC Electrical Characteristics

At recommended operating conditions with OV_DD= 3.3 V 165 mV

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Note

MAX_REF_CLK frequency

MAX_REF_CLK cycle time

MAX_REF_CLK duty cycle

MAX_REF_CLK slew rate

MAX_REF_CLK peak period jitter

AC Input Swing Limits at 3.3 V OV_DD

Note:

f_{MAX_PHY_REF_CLK}

t_{MAX_PHY_REF_CLK}

t_KHK/t_{MAX_PHY_REF_CLK}

19.2

50.86

48

—

50

—

19.6608

MHz

ns

—

1

52

4

%

—

1

V/ns

ps

—

100

—

ΔV_AC

1.9

V

1. Slew rate as measured from 0.3 ΔV_ACat the center of peak to peak voltage at clock input.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

60

Freescale Semiconductor

Electrical Characteristics

2.7.8

Other Input Clocks

A description of the overall clocking of this device is available in the BSC9131QorIQ Qonverge Multicore Baseband Processor

Reference Manual in the form of a clock subsystem block diagram. For information about the input clock requirements of other

functional blocks such asEthernet Management, eSDHC, and IFC, see the specific interface section.

2.8

DDR3 and DDR3L SDRAM Controller

This section describes the DC and AC electrical specifications for the DDR3 and DDR3L SDRAM controller interface. Note

that the required GV (typ) voltage is 1.5 V and 1.35 V when interfacing to DDR3 or DDR3L SDRAM, respectively.

DD

2.8.1

DDR3 and DDR3L SDRAM Interface DC Electrical Characteristics

This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3

SDRAM.

Table 22. DDR3 SDRAM Interface DC Electrical Characteristics

At recommended operating condition with GV_DD= 1.5 V¹

Parameter

I/O reference voltage

Symbol

Min

Max

Unit

Note

MVREFn

V_IH

0.49 × GV_DD

MVREFn + 0.100

GND

0.51 × GV_DD

GV_DD

V

2, 3, 4

Input high voltage

Input low voltage

I/O leakage current

Note:

5

6

V_IL

MVREFn – 0.100

50

V

I_OZ

–50

μA

1. GV_DDis expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage

supply may or may not be from the same source.

2. MVREFn is expected to be equal to 0.5 × GV_DDand to track GV_DDDC variations as measured at the receiver. Peak-to-peak

noise on MVREFn may not exceed 1% of the DC value.

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be

equal to MVREFn with a min value of MVREFn – 0.04 and a max value of MVREFn + 0.04. V_TTshould track variations in the

DC level of MVREFn.

4. The voltage regulator for MVREFn must be able to supply up to125 μA current.

5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.

6. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV_DD

.

This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3L

SDRAM.

Table 23. DDR3L SDRAM Interface DC Electrical Characteristics

At recommended operating condition with GV_DD= 1.35 V¹

Parameter

I/O reference voltage

Symbol

Min

Max

Unit

Note

MVREFn

V_IH

0.49 × GV_DD

0.51 × GV_DD

V

2, 3, 4

5

Input high voltage

MVREFn + 0.090

GV_DD

Input low voltage

V_IL

GND

—

MVREFn – 0.090

V

5

Output high current (V_OUT= 0.641 V)

Output low current (V_OUT= 0.641 V)

I/O leakage current

I_OH

–23.3

—

mA

μA

6, 7

8

I_OL

23.3

–50

I_OZ

50

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

61

Electrical Characteristics

Table 23. DDR3L SDRAM Interface DC Electrical Characteristics (continued)

At recommended operating condition with GV_DD= 1.35 V¹

Parameter

Symbol

Min

Max

Unit

Note

Note:

1. GV_DDis expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage

supply may or may not be from the same source.

2. MVREFn is expected to be equal to 0.5 × GV_DDand to track GV_DDDC variations as measured at the receiver.Peak-to-peak

noise on MVREFn may not exceed the MVREFn DC level by more than 1% of GV_DD(i.e. 13.5 mV).

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be

equal to MVREFn with a min value of MVREFn – 0.04 and a max value of MVREFn + 0.04. V_TTshould track variations in the

DC level of MVREFn.

4. The voltage regulator for MVREFn must be able to supply up to125 μA current.

5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.

6. IOH and IOL are measured at GV_DD= 1.282 V

7. See the IBIS model for the complete output IV curve characteristics.

8. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV_DD

.

This table provides the DDR controller interface capacitance for DDR3.

Table 24. DDR3 SDRAM Capacitance

At recommended operating conditions with GV_DDof 1.5 V 5% for DDR3 or 1.35 V 5% for DDR3L.

Parameter

Symbol

Min

Max

Unit

Note

Input/output capacitance: DQ, DQS, DQS_B

C_IO

6

8

pF

—

Delta input/output capacitance: DQ, DQS, DQS_B

C_DIO

—

0.5

This table provides the current draw characteristics for MVREFn.

-

Table 25. Current Draw Characteristics for MVREFn

For recommended operating conditions, seeTable 3.

Parameter

Symbol

Min

Max

Unit

Note

Current draw for DDR3 SDRAM for MVREFn

Current draw for DDR3L SDRAM for MVREFn

I_MVREFn

—

700

μA

—

2.8.2

DDR3 and DDR3L SDRAM Interface AC Timing Specifications

This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports

DDR3 and DDR3L memories. Note that the required GV (typ) voltage is 1.5 V when interfacing to DDR3 SDRAM, and the

DD

required GV (typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.

DD

2.8.2.1

DDR3 and DDR3L SDRAM Interface Input AC Timing Specifications

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM.

Table 26. DDR3 SDRAM Interface Input AC Timing Specifications

For recommended operating conditions, see Table 3.

Parameter

AC input low voltage

Symbol

Min

Max

Unit

Note

V_ILAC

—

MVREFn – 0.175

V

—

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

62

Freescale Semiconductor

Electrical Characteristics

Table 26. DDR3 SDRAM Interface Input AC Timing Specifications (continued)

For recommended operating conditions, see Table 3.

Parameter

AC input high voltage

Symbol

Min

Max

Unit

Note

V_IHAC

MVREFn + 0.175

—

V

—

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3L SDRAM.

Table 27. DDR3L SDRAM Interface Input AC Timing Specifications

For recommended operating conditions, see Table 3.

Parameter

AC input low voltage

AC input high voltage

Symbol

Min

Max

Unit

Note

V_ILAC

V_IHAC

—

MVREFn – 0.160

V

—

MVREFn + 0.160

—

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3/3L SDRAM.

Table 28. DDR3 and DDR3L SDRAM Interface Input AC Timing Specifications

At recommended operating conditions with GV_DDof 1.5 V 5% for DDR3 or 1.35 V 5% for DDR3L.

Parameter

Symbol

Min

Max

Unit

Note

Controller Skew for MDQS—MDQ/MECC

800 MHz data rate

t_CISKEW

—

ps

1

–200

–240

—

200

240

—

667 MHz data rate

Tolerated Skew for MDQS—MDQ/MECC

800 MHz data rate

t_DISKEW

ps

2

–425

–510

425

510

667 MHz data rate

Note:

1. t_CISKEWrepresents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

is captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t_DISKEW.This can be

determined by the following equation: t_DISKEW= (T ÷ 4 – abs(t_CISKEW)) where T is the clock period and abs(t_CISKEW) is the

absolute value of t_CISKEW

.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

63

Electrical Characteristics

This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram.

MCK[n]_B

MCK[n]

t_MCK

MDQS[n]

t_DISKEW

MDQ[x]

D0

D1

t_DISKEW

Figure 9. DDR3 and DDR3L SDRAM Interface Input Timing Diagram

2.8.2.2

DDR3 and DDR3L SDRAM Interface Output AC Timing Specifications

This table contains the output AC timing targets for the DDR3 and DDR3L SDRAM interface.

Table 29. DDR3 and DDR3L SDRAM Interface Output AC Timing Specifications

At recommended operating conditions with GV_DDof 1.5 V 5% for DDR3 or 1.35 V 5% for DDR3L.

Parameter

MCK[n] cycle time

Symbol¹

Min

Max

Unit

Note

t_MCK

2.5

3

ns

2

3

ADDR/CMD output setup with respect to MCK

800 MHz data rate

t_DDKHAS

0.917

1.10

—

667 MHz data rate

ADDR/CMD output hold with respect to MCK

800 MHz data rate

t_DDKHAX

t_DDKHCS

t_DDKHCX

t_DDKHMH

ns

3

4

0.917

1.10

—

667 MHz data rate

MCS[n]_B output setup with respect to MCK

800 MHz data rate

0.917

1.10

—

667 MHz data rate

MCS[n]_B output hold with respect to MCK

800 MHz data rate

0.917

1.10

—

667 MHz data rate

MCK to MDQS Skew

800 MHz data rate

–0.375

–0.6

0.375

0.6

667 MHz data rate

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

64

Freescale Semiconductor

Electrical Characteristics

Table 29. DDR3 and DDR3L SDRAM Interface Output AC Timing Specifications (continued)

At recommended operating conditions with GV_DDof 1.5 V 5% for DDR3 or 1.35 V 5% for DDR3L.

Parameter

Symbol¹

Min

Max

Unit

Note

MDQ/MECC/MDM output setup with respect

to MDQS

t_DDKHDS,

t_DDKLDS

ps

5

800 MHz data rate

667 MHz data rate

375

450

—

MDQ/MECC/MDM output hold with respect to

MDQS

t_DDKHDX,

t_DDKLDX

ps

5

800 MHz data rate

667 MHz data rate

MDQS preamble

MDQS postamble

Note:

375

—

450

t_DDKHMP

t_DDKHME

0.9 × t_MCK

0.4 × t_MCK

—

ns

—

0.6 × t_MCK

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

t_DDKHASsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, t_DDKLDXsymbolizes DDR timing (DD) for the time t_MCKmemory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS.

4. Note that t_DDKHMHfollows the symbol conventions described in note 1. For example, t_DDKHMHdescribes the DDR timing (DD)

from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t_DDKHMHcan be modified through control

of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay

as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters

have been set to the same adjustment value. See the BSC9131 QorIQ Qonverge Multicore Baseband Processor Reference

Manual for a description and explanation of the timing modifications enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

NOTE

For the ADDR/CMD setup and hold specifications in Table 29, it is assumed that the clock

control register is set to adjust the memory clocks by ½ applied cycle.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

65

Electrical Characteristics

This figure shows the DDR3 and DDR3L SDRAM interface output timing for the MCK to MDQS skew measurement

(t

).

DDKHMH

MCK_B[n]

MCK[n]

tMCK

t_{DDKHMH(max) = 0.6 ns or 0.375 n}

s

MDQS

t_{DDKHMH(min) = –0.6 ns or –0.375 ns}

Figure 10. t

Timing Diagram

DDKHMH

This figure shows the DDR3 and DDR3L SDRAM output timing diagram.

MCK_B

MCK

t_MCK

t_DDKHAS, t_DDKHCS

t_DDKHAX, t_DDKHCX

ADDR/CMD

Write A0

t_DDKHMP

NOOP

t_DDKHMH

MDQS[n]

MDQ[x]

t_DDKHME

t_DDKHDS

t_DDKLDS

D0

D1

t_DDKLDX

t_DDKHDX

Figure 11. DDR3 and DDR3L Output Timing Diagram

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

66

Freescale Semiconductor

Electrical Characteristics

This figure provides the AC test load for the DDR3 and DDR3Lcontroller bus.

Output

GV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 12. DDR3 and DDR3L Controller Bus AC Test Load

2.8.2.3

DDR3 and DDR3L SDRAM Differential Timing Specifications

This section describes the DC and AC differential timing specifications for the DDR3 SDRAM controller interface. Figure 13

shows the differential timing specification.

GVDD

VTR

GV_DD/2

V_OXor V_IX

VCP

GND

Figure 13. DDR3, and DDR3L SDRAM Differential Timing Specifications

NOTE

VTR specifies the true input signal (such as MCK or MDQS) and VCP is the

complementary input signal (such as MCK_B or MDQS_B).

This table provides the DDR3 differential specifications for the differential signals MDQS/MDQS_B and MCK/MCK_B.

Table 30. DDR3 SDRAM Differential Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

Note

Input AC Differential Cross-Point Voltage

Output AC Differential Cross-Point Voltage

Note:

V_IXAC

0.5 × GV_DD– 0.150 0.5 × GV_DD+ 0.150

0.5 × GV_DD– 0.115 0.5 × GV_DD+ 0.115

V

1

V_OXAC

1. I/O drivers are calibrated before making measurements.

This table provides the DDR3 differential specifications for the differential signals MDQS/MDQS_B and MCK/MCK_B.

Table 31. DDR3L SDRAM Differential Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

Note

Input AC Differential Cross-Point Voltage

Output AC Differential Cross-Point Voltage

Note:

V_IXAC

0.5 × GV_DD– 0.135 0.5 × GV_DD+ 0.135

0.5 × GV_DD– 0.105 0.5 × GV_DD+ 0.105

V

1

V_OXAC

1. I/O drivers are calibrated before making measurements.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

67

Electrical Characteristics

2.9

eSPI

This section describes the DC and AC electrical specifications for the SPI.

2.9.1

eSPI1 DC Electrical Characteristics

This table provides the DC electrical characteristics for the eSPI1 on the device operating on a 3.3 V power supply.

Table 32. eSPI1 DC Electrical Characteristics (CV = 3.3 V)

DD

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

V_IH

V_IL

2.0

—

0.8

10

V

1

Input low voltage

Input current (0 V ≤ V_IN≤ CV_DD

)

I_IN

—

μA

V

2

Output high voltage (I_OH= –6.0 mA)

Output low voltage (I_OL= 6.0 mA)

Output low voltage (IOL = 3.2 mA)

V_OH

V_OL

2.4

—

0.5

0.4

V

—

V

OL

Note:

1

The min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2

The symbol V_IN, in this case, represents the OV_INsymbol referenced in Section 2.1.2, “Recommended Operating Conditions.”

This table provides the DC electrical characteristics for the eSPI1, eSPI2, eSPI3, and eSPI4 on the device operating on a 1.8 V

power supply.

Table 33. eSPI DC Electrical Characteristics (CV , X2V , X1V = 1.8 V)

DD

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

V_IH

V_IL

1.25

—

0.6

40

—

V

1

Input low voltage

Input current (0 V ≤ V_IN≤ CV_DD/X2V_DD/X1V_DD

Output high voltage (I_OH= –6.0 mA)

Output low voltage (I_OL= 6.0 mA)

)

I_IN

—

μA

V

2, 3

—

V_OH

V_OL

1.35

—

0.4

V

Note:

1

The min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2

3

The symbol V_IN, in this case, represents the OV_INsymbol referenced in Section 2.1.2, “Recommended Operating Conditions.”

eSPI1 is powered on CV_DD, SPI2 is on X2V_DD, SPI3 and SPI4 are on X1V_DD(see Table 3).

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

68

Freescale Semiconductor

Electrical Characteristics

2.9.2

eSPI1 AC Timing Specifications

This table provides the eSPI1 input and output AC timing specifications.

Table 34. eSPI1 AC Timing Specifications

For recommended operating conditions, see Table 3.

Characteristic

Symbol¹

Min

Max

Unit Note

eSPI outputs—Master data (internal clock) hold time

t_NIKHOX

0.5 +

—

ns

2

(t_{PLATFORM_CLK}/2)

eSPI outputs—Master data (internal clock) delay

t_NIKHOV

—

6.0 +

ns

2

(t_{PLATFORM_CLK}/2)

SPI_CS outputs—Master data (internal clock) hold time

SPI_CS outputs—Master data (internal clock) delay

eSPI inputs—Master data (internal clock) input setup time

eSPI inputs—Master data (internal clock) input hold time

Note:

t_NIKHOX2

t_NIKHOV2

t_NIIVKH

0

—

5

—

6.0

—

ns

2

—

t_NIIXKH

0

—

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_NIKHOVsymbolizes the NMSI outputs

internal timing (NI) for the time t_SPImemory clock reference (K) goes from the high state (H) until outputs (O) are valid (V).

2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin.

This figure provides the AC test load for eSPI1.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 14. eSPI1 AC Test Load

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

69

Electrical Characteristics

This figure represents the AC timing from Table 34 in master mode (internal clock). Note that although the specifications are

generally refer to the rising edge of the clock, Figure 14 also apply when the falling edge is the active edge. Also, note that the

clock edge is selectable on eSPI1.

SPICLK (output)

t_NIIXKH

t_NIIVKH

Input Signals:

SPIMISO¹

t_NIKHOX

t_NIKHOV

Output Signals:

SPIMOSI¹

t_NIKHOX2

t_NIKHOV2

Output Signals:

SPI_CS[0:3]¹

Figure 15. eSPI1 AC Timing in Master Mode (Internal Clock) Diagram

2.10 DUART

This section describes the DC and AC electrical specifications for the DUART interfaces.

2.10.1 DUART DC Electrical Characteristics

Table 35 and Table 37 provide the DC electrical characteristics for the two DUARTs on the device, which correspond to four

UART interfaces. DUART1 is powered by OV , while DUART2 is powered by the CV

.

DD

This table provides the DC timing parameters for the DUART interface operating from a 3.3 V power supply.

Table 35. DUART DC Electrical Characteristics (OV , CV = 3.3 V)

DD

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

V_IH

V_IL

2

—

0.8

40

—

V

1

Input low voltage

—

2.4

—

Input current (OV_IN/CV_IN= 0 V or OV_IN/CV_IN= OV_DD/CV_DD

Output high voltage (OV_DD/CV_DD= mn, I_OH= –2 mA)

Output low voltage (OV_DD/CV_DD= min, I_OL= 2 mA)

Note:

)

I_IN

μA

V

2

V_OH

V_OL

—

0.4

V

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max OV_IN/CV_INvalues found in Figure 3.

2. Note that the symbol OV_IN/CV_INrepresents the input voltage of the supply. It is referenced in Figure 3.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

70

Freescale Semiconductor

Electrical Characteristics

This table provides the DC timing parameters for the DUART interface operating from a 1.8 V power supply.

Table 36. DUART DC Electrical Characteristics (CV = 1.8 V)

DD

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

V_IH

V_IL

1.25

—

0.6

40

—

V

1

Input current (CV_IN= 0 V or CV_IN= CV_DD

)

I_IN

—

μA

V

2

Output high voltage (CV_DD= mn, I_OH= –2 mA)

Output low voltage (CV_DD= min, I_OL= 2 mA)

Note:

V_OH

V_OL

1.35

—

0.4

V

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max CV_INvalues found in Figure 3.

2. Note that the symbol CV_INrepresents the input voltage of the supply. It is referenced in Figure 3.

2.10.2 DUART AC Electrical Specifications

This table provides the AC timing parameters for the DUART interface.

Table 37. DUART AC Timing Specifications

Parameter

Minimum baud rate

Value

Unit

Note

CCB clock/1,048,576

CCB clock/16

16

baud

—

1

2

3

Maximum baud rate

Oversample rate

Note:

1. CCB clock refers to the platform clock.

2. Actual attainable baud rate is limited by the latency of interrupt processing.

3. The middle of a start bit is detected as the 8^thsampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

sampled each 16^thsample.

2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

This section provides the AC and DC electrical characteristics for enhanced three-speed Ethernet10/100/1000 controller and

MII management.

2.11.1 RMII/RGMII Interface Electrical Specifications

This section provides AC and DC electrical characteristics of RMII/RGMII interface for eTSEC.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

71

Electrical Characteristics

2.11.1.1 RMII and RGMII DC Electrical Characteristics

Table 38 presents the RGMII/RMII DC timing specifications.

Table 38. RGMII/RMII DC Electrical Characteristics (LV = 3.3 V)

DD

At recommended operating conditions with LV_DD= 3.3 V

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

V_IH

V_IL

I_IH

2.0

—

0.8

50

—

V

1

—

2

Input low voltage

Input high current (V_IN= LV_DD

Input low current (V_IN= GND)

)

—

μA

V

I_IL

–50

2.4

—

2

Output high voltage (LV_DD= min, I_OH= –4.0 mA)

Output low voltage (LV_DD= min, I_OL= 4.0 mA)

Note:

V_OH

V_OL

—

0.4

V

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the LV_INsymbols referenced in Table 2 and Table 3.

Table 39 shows the RGMII/RMII DC electrical characteristics when operating from a 2.5 V supply.

Table 39. RGMII/RMII DC Electrical Characteristics (LV = 2.5 V)

DD

At recommended operating conditions with LV_DD= 2.5 V.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

V_IH

V_IL

I_IH

1.70

—

0.70

V

1

Input low voltage

Input high current (V_IN= LV_DD

Input low current (V_IN= GND)

)

—

50

μA

V

2

I_IL

–50

—

2

Output high voltage (LV_DD= min, I_OH= –1.0 mA)

Output low voltage (LV_DD= min, I_OL= 1.0 mA)

Note:

V_OH

V_OL

2.00

LV_DD+ 0.3

0.40

—

GND – 0.3

V

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the LV_INsymbols referenced in Table 3.

2.11.1.2 RMII and RGMII AC Timing Specifications

Table 40 presents the RMII transmit AC timing specifications.

Table 40. RMII Transmit AC Timing Specifications

For recommended operating conditions, see Table 3.

Parameter

TSECn_TX_CLK clock period

Symbol

Min

Typ

Max

Unit

t_RMT

t_RMTH

t_RMTJ

t_RMTR

t_RMTF

—

35

—

20.0

—

65

ns

%

TSECn_TX_CLK duty cycle

TSECn_TX_CLK peak-to-peak jitter

Rise time TSECn_TX_CLK (20%–80%)

Fall time TSECn_TX_CLK (80%–20%)

—

250

5.0

ps

ns

1.0

—

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

72

Freescale Semiconductor

Electrical Characteristics

Table 40. RMII Transmit AC Timing Specifications (continued)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay

t_RMTDX

2.0

—

10.0

ns

Figure 16 shows the RMII transmit AC timing diagram.

t_RMT

t_RMTR

REF_CLK

t_RMTH

t_RMTF

TXD[1:0]

TX_EN

TX_ER

t_RMTDX

Figure 16. RMII Transmit AC Timing Diagram

Table 41 lists the RMII receive AC timing specifications.

Table 41. RMII Receive AC Timing Specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

TSECn_TX_CLK clock period

TSECn_TX_CLK duty cycle

t_RMR

t_RMRH

t_RMRJ

—

35

20.0

—

65

ns

%

TSECn_TX_CLK peak-to-peak jitter

—

250

5.0

—

ps

ns

Rise time TSECn_TX_CLK (20%–80%)

t_RMRR

t_RMRF

t_RMRDV

t_RMRDX

1.0

4.0

2.0

—

Fall time TSECn_TX_CLK (80%–20%)

—

RXD[1:0], CRS_DV, RX_ER setup time to TSECn_TX_CLK rising edge

RXD[1:0], CRS_DV, RX_ER hold time to TSECn_TX_CLK rising edge

—

Figure 17 provides the AC test load for eTSEC.

LV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 17. eTSEC AC Test Load

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

73

Electrical Characteristics

Figure 18 shows the RMII receive AC timing diagram.

t_RMR

t_RMRR

TSECn_TX_CLK

t

t_RMRH

RMRF

RXD[1:0]

CRS_DV

RX_ER

Valid Data

t_RMRDV

t_RMRDX

Figure 18. RMII Receive AC Timing Diagram

Table 42 presents the RGMII AC timing specifications.

Table 42. RGMII AC Timing Specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol¹

Min

Typ

Max

Unit

Note

Data to clock output skew (at transmitter)

Data to clock input skew (at receiver)

Clock period duration

t_{SKRGT_TX}

t_{SKRGT_RX}

t_RGT

–500

1.0

7.2

40

0

500

2.6

ps

ns

%

5

2

—

8.0

50

—

8.8

60

3

Duty cycle for 10BASE-T and 100BASE-TX

Duty cycle for Gigabit

t_{RGTH RGT}

_RGTH/t_RGT

t_RGTR

t_RGTF

/t

3, 4

—

t

45

55

%

Rise time (20%–80%)

—

0.75

ns

Fall time (20%–80%)

—

Note:

1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing.

For example, the subscript of t_RGTrepresents the TBI (T) receive (RX) clock. Note also that the notation for rise (R) and fall

(F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK)

followed by the clock that is being skewed (RGT).

2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is

added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their chip. If so,

additional PCB delay is probably not needed.

3. For 10 and 100 Mbps, t_RGTscales to 400 ns 40 ns and 40 ns 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three t_RGTof the lowest speed transitioned

between.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

74

Freescale Semiconductor

Electrical Characteristics

Figure 19 shows the RGMII AC timing and multiplexing diagrams.

t_RGT

t_RGTH

GTX_CLK

(At TSEC, output)

t_{SKRGT_TX}

TXD[3:0]

TX_CTL

TXEN

TXERR

t_{SKRGT_RX}

GTX_CLK

(At PHY, input)

t

RGT

t_RGTH

RX_CLK

(At PHY, output)

RXD[3:0]

RX_CTL

t_{SKRGT_TX}

RXDV

RXERR

t_{SKRGT_RX}

RX_CLK

(At TSEC, input)

Figure 19. RGMII AC Timing and Multiplexing Diagram

2.11.2 MII Management

2.11.2.1 MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 3.3 V and 2.5 V. The DC electrical characteristics for MDIO

and MDC are provided in Table 43 and Table 44.

Table 43. MII Management DC Electrical Characteristics

At recommended operating conditions with LV_DD= 3.3 V.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

V_IH

V_IL

I_IH

2.0

—

0.90

V

—

1

Input high current (LV_DD= Max, V_IN= 2.1 V)

Input low current (LV_DD= Max, V_IN= 0.5 V)

Output high voltage (LV_DD= Min, I_OH= –1.0 mA)

Output low voltage (LV_DD= Min, I_OL= 1.0 mA)

—

40

μA

V

I_IL

–600

2.4

—

1

V_OH

V_OL

LV_DD+ 0.3

0.4

—

GND

V

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

75

Electrical Characteristics

Table 43. MII Management DC Electrical Characteristics (continued)

At recommended operating conditions with LV_DD= 3.3 V.

Parameter

Note:

Symbol

Min

Max

Unit

Note

1. Note that the symbol V_IN, in this case, represents the LV_INsymbol referenced in Table 2 and Table 3.

Table 44. MII Management DC Electrical Characteristics

At recommended operating conditions with LV_DD= 2.5 V.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

V_IH

V_IL

I_IH

1.70

–0.3

—

LV_DD+ 0.3

0.70

V

—

Input high current (V_IN= LV_DD,)

Input low current (V_IN= GND)

10

μA

V

1, 2

—

I_IL

–15

2.00

—

Output high voltage

V_OH

LV_DD+ 0.3

—

(LV_DD= Min, IOH = –1.0 mA)

Output low voltage

V_OL

GND – 0.3

0.40

V

—

(LV_DD= Min, I_OL= 1.0 mA)

Note:

1. EC1_MDC and EC1_MDIO operate on LV_DD

.

2. Note that the symbol V_IN, in this case, represents the LV_INand TV_INsymbols referenced in Table 3.

2.11.2.2 MII Management AC Electrical Specifications

This table provides the MII management AC timing specifications.

Table 45. MII Management AC Timing Specifications

Parameter

MDC frequency

Symbol¹

Min

Typ

Max

Unit

Note

f_MDC

t_MDC

—

2.5

400

—

MHz

ns

2

—

MDC period

—

MDC clock pulse width high

MDC to MDIO delay

MDIO to MDC setup time

MDIO to MDC hold time

t_MDCH

32

—

ns

—

t_MDKHDX

t_MDDVKH

t_MDDXKH

(16*t_{plb_clk}) – 3

—

(16*t_{plb_clk}) + 3

ns

3, 4

—

5

0

—

ns

—

ns

—

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

76

Freescale Semiconductor

Electrical Characteristics

Table 45. MII Management AC Timing Specifications (continued)

Parameter Min Typ Max

Symbol¹

Unit

Note

Note:

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MDKHDXsymbolizes management

data timing (MD) for the time t_MDCfrom clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.

Also, t_MDDVKHsymbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state

(V) relative to the t_MDCclock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention

is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of

the MgmtClk Clock EC_MDC).

3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods 3 ns. For

example, with a platform clock of 333 MHz, the min/max delay is 48 ns 3 ns. Similarly, if the platform clock is 400 MHz, the

min/max delay is 40 ns 3 ns.

4. t_{plb_clk}is the platform (CCB) clock.

This figure shows the MII management interface timing diagram.

t_MDCR

t_MDC

MDC

t_MDCF

t_MDCH

MDIO

(Input)

t_MDDVKH

t_MDDXKH

MDIO

(Output)

t_MDKHDX

Figure 20. MII Management Interface Timing Diagram

2.11.3 eTSEC IEEE Std 1588 Electrical Specifications

2.11.3.1 eTSEC IEEE Std 1588 DC Specifications

This table shows IEEE Std 1588 DC electrical characteristics when operating at LV = 3.3 V supply.

DD

Table 46. eTSEC IEEE 1588 DC Electrical Characteristics (LV = 3.3 V)

DD

For recommended operating conditions with LV_DD= 3.3 V.

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

V_IH

V_IL

I_IH

2.0

—

0.9

40

V

2

1

Input low voltage

Input high current (LV_DD= Max, V_IN= 2.1 V)

—

μA

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

77

Electrical Characteristics

Table 46. eTSEC IEEE 1588 DC Electrical Characteristics (LV = 3.3 V) (continued)

DD

For recommended operating conditions with LV_DD= 3.3 V.

Parameter

Symbol

Min

Max

Unit

Notes

Input low current (LV_DD= Max, V_IN= 0.5 V)

Output high voltage (LV_DD= Min, I_OH= –1.0 mA)

Output low voltage (LV_DD= Min, I_OL= 1.0 mA)

Note:

I_IL

–600

2.4

—

μA

V

1

V_OH

V_OL

—

0.4

V

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the LV_INsymbols referenced in Table 2 and Table 3.

This table shows the IEEE 1588 DC electrical characteristics when operating at LV = 2.5 V supply.

DD

Table 47. eTSEC IEEE 1588 DC Electrical Characteristics (LV = 2.5 V)

DD

For recommended operating conditions with LV_DD= 2.5 V

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

V_IH

V_IL

1.70

—

0.70

40

V

—

2

Input low voltage

Input current (LV_IN= 0 V or LV_IN= LV_DD

)

I_IH

—

μA

V

Output high voltage (LV_DD= min, I_OH= –1.0 mA)

Output low voltage (LV_DD= min, I_OL= 1.0 mA)

Note:

V_OH

V_OL

2.00

—

0.40

V

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the LV_INsymbols referenced in Table 2 and Table 3.

2.11.3.2 eTSEC IEEE Std 1588 AC Specifications

This table provides the IEEE Std 1588 AC timing specifications.

Table 48. eTSEC IEEE 1588 AC Timing Specifications

For recommended operating conditions, see Table 3

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Note

TSEC_1588_CLK clock period

TSEC_1588_CLK duty cycle

t_T1588CLK

5

—

T_{RX_CLK}*7

60

ns

%

1, 3

—

t_T1588CLKH

/t_T1588CLK

40

50

TSEC_1588_CLK peak-to-peak jitter

Rise time eTSEC_1588_CLK (20%–80%)

Fall time eTSEC_1588_CLK (80%–20%)

TSEC_1588_CLK_OUT clock period

TSEC_1588_CLK_OUT duty cycle

t_T1588CLKINJ

t_T1588CLKINR

t_T1588CLKINF

t_T1588CLKOUT

—

50

250

2.0

—

ps

ns

%

—

1.0

2 x t_T1588CLK

30

t_T1588CLKOTH

/t_T1588CLKOUT

70

TSEC_1588_PULSE_OUT

t_T1588OV

0.5

—

3.0

—

ns

—

2

TSEC_1588_TRIG_IN pulse width

t_T1588TRIGH

2*t_{T1588CLK_MAX}

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

78

Freescale Semiconductor

Electrical Characteristics

Table 48. eTSEC IEEE 1588 AC Timing Specifications (continued)

For recommended operating conditions, see Table 3

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Note

Note:

1.T_{RX_CLK}is the max clock period of eTSEC receiving clock selected by TMR_CTRL[CKSEL]. See the BSC9131 QorIQ

Qonverge Multicore Baseband Processor Reference Manual for a description of TMR_CTRL registers.

2. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the BSC9131 QorIQ

Qonverge Multicore Baseband Processor Reference Manualfor a description of TMR_CTRL registers.

3. The maximum value of t_T1588CLKis not only defined by the value of T_{RX_CLK}, but also defined by the recovered clock. For

example, for 10/100/1000 Mbps modes, the maximum value of t_T1588CLKis 2800, 280, and 56 ns respectively.

Figure 21 shows the data and command output AC timing diagram.

t_T1588CLKOUT

t_T1588CLKOUTH

TSEC_1588_CLK_OUT

t_T1588OV

TSEC_1588_PULSE_OUT

TSEC_1588_TRIG_OUT

1

eTSEC IEEE 1588 Output AC timing: The output delay is counted starting at the rising edge if t_T1588CLKOUTis non-inverting.

Otherwise, it is counted starting at the falling edge.

Figure 21. eTSEC IEEE 1588 Output AC Timing

This figure shows the data and command input AC timing diagram.

t_T1588CLK

t_T1588CLKH

TSEC_1588_CLK

TSEC_1588_TRIG_IN

t_T1588TRIGH

Figure 22. eTSEC IEEE 1588 Input AC Timing

2.12 USB

This section provides the AC and DC electrical specifications for the USB interface.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

79

Electrical Characteristics

2.12.1 USB DC Electrical Characteristics

This table provides the DC electrical characteristics for the ULPI interface when operating at 3.3 V.

Table 49. USB DC Electrical Characteristics (CV /LV /X2V = 3.3 V)

DD

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

2

—

0.8

40

V

1

2

—

Input current

μA

(CV_IN/LV_IN/X2V_IN= 0 V or CV_IN/LV_IN/X2V_IN= CV_DD/LV_DD/X2V_DD

)

Output high voltage

(CV_DD/LV_DD/X2V_DD= min, I_OH= –2 mA)

V_OH

V_OL

2.8

—

V

—

Output low voltage

0.3

(CV_DD/LV_DD/X2V_DD= min, I_OL= 2 mA)

Note:

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max CV_IN/LV_IN/X2V_INvalues found in Table 3.

2. Note that the symbol CV_IN, LV_IN, and X2V_INrepresent the input voltage of the power supplies. See Table 3.

Table 51 provides the DC electrical characteristics for the ULPI interface when operating at 2.5 V.

Table 50. USB DC Electrical Characteristics (LV = 2.5 V)

DD

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

V_IH

V_IL

1.7

—

0.7

40

—

V

1

Input low voltage

Input current (LV_IN= 0 V or LV_IN= LV_DD

)

I_IN

—

μA

V

2

Output high voltage (LV_DD= min, I_OH= –2 mA)

Output low voltage (LV_DD= min, I_OL= 2 mA)

Note:

V_OH

V_OL

2.0

—

0.4

V

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. Note that the symbol LV_INrepresents the input voltage of the supply. It is referenced in Table 3.

This table provides the DC electrical characteristics for the ULPI interface when operating at 1.8 V.

Table 51. USB DC Electrical Characteristics (CV /X2V = 1.8 V)

DD

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

V_IH

V_IL

1.25

—

0.6

40

—

V

1

Input low voltage

Input current (CV_IN/X2V_IN= 0 V or CV_IN/X2V_IN= CV_DD/X2V_DD

Output high voltage (CV_DD/X2V_DD= min, I_OH= –2 mA)

Output low voltage (CV_DD/X2V_DD= min, I_OL= 2 mA)

)

I_IN

—

μA

V

2

V_OH

V_OL

1.35

—

0.4

V

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

80

Freescale Semiconductor

Electrical Characteristics

Table 51. USB DC Electrical Characteristics (CV /X2V = 1.8 V) (continued)

DD

For recommended operating conditions, see Table 3.

Note:

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max CV_IN/X2V_INvalues found in Table 3.

2. Note that the symbol CV_IN/X2V_INrepresents the input voltage of the supply. See Table 3.

2.12.2 USB AC Electrical Specifications

This table describes the general timing parameters of the USB interface of the device.

Table 52. USB General Timing Parameters (ULPI Mode)

For recommended operating conditions, see Table 3.

Parameter

USB clock cycle time

Symbol¹

Min

Max

Unit

Note

t_USCK

t_USIVKH

t_USIXKH

t_USKHOV

t_USKHOX

15

4

—

7

ns

2, 3, 4, 5

Input setup to USB clock—all inputs

input hold to USB clock—all inputs

USB clock to output valid—all outputs

Output hold from USB clock—all outputs

Note:

1

—

2

—

1. The symbols for timing specifications follow the pattern of t_{(First two letters of functional block)(signal)(state) (reference)(state)}for inputs

and t_{(First two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_USIXKHsymbolizes USB timing (US) for

the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, t_USKHOXsymbolizes

USB timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold

time.

2. All timings are in reference to USB clock.

3. All signals are measured from BV_DD/2 of the rising edge of the USB clock to 0.4 × OV_DDof the signal in question for 3.3 V

signaling levels.

4. Input timings are measured at the pin.

5. For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered through

the component pin is less than or equal to that of the leakage current specification.

Figure 23 and Figure 24 provide the USB AC test load and signals, respectively.

OV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 23. USB AC Test Load

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

81

Electrical Characteristics

USB0_CLK/USB1_CLK/DR_CLK

t_USIXKH

t_USIVKH

Input Signals

t_USKHOX

t_USKHOV

Output Signals:

Figure 24. USB Signals

This table provides the USB clock input (USB_CLK_IN) AC timing specifications.

Table 53. USB_CLK_IN AC Timing Specifications

Parameter/Condition

Conditions

Symbol

Min

Typ

Max

Unit

Frequency range

Steady state

—

f_{USB_CLK_IN}

t_{CLK_TOL}

t_{CLK_DUTY}

t_{CLK_PJ}

59.97

–0.05

40

60

0

60.03

0.05

60

MHz

%

Clock frequency tolerance

Reference clock duty cycle Measured at 1.6 V

50

—

%

Total input jitter/time interval Peak-to-peak value measured with a second

—

200

ps

error

order high-pass filter of 500 kHz bandwidth

2.13 Integrated Flash Controller (IFC)

This section describes the DC and AC electrical specifications for the integrated flash controller.

2.13.1 IFC DC Electrical Characteristics

This table provides the DC electrical characteristics for the integrated flash controller when operating at BV = 3.3 V.

DD

Table 54. Integrated Flash Controller DC Electrical Characteristics (3.3 V)

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

Input current

V_IH

V_IL

I_IN

2

—

0.8

40

V

1

2

—

μA

(V_IN= 0 V or V_IN= BV_DD)

Output high voltage

(BV_DD= min, I_OH= –2 mA)

V_OH

V_OL

2.8

—

V

—

Output low voltage

0.4

(BV_DD= min, I_OH= 2 mA)

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

82

Freescale Semiconductor

Electrical Characteristics

Table 54. Integrated Flash Controller DC Electrical Characteristics (3.3 V) (continued)

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Max

Unit

Note

Note:

1. The min V_ILand max V_IHvalues are based on the respective min and max BV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the BV_INsymbol referenced in Section 2.1.2, “Recommended Operating

Conditions.”

This table provides the DC electrical characteristics for the integrated flash controller when operating at BV = 2.5 V.

DD

Table 55. Integrated Flash Controller DC Electrical Characteristics (2.5 V)

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

Input current

V_IH

V_IL

I_IN

1.7

—

0.7

40

V

1

2

—

μA

(V_IN= 0 V or V_IN= BV_DD)

Output high voltage

(BV_DD= min, I_OH= –1 mA)

V_OH

V_OL

2.0

—

V

—

Output low voltage

0.4

(BV_DD= min, I_OL= 1 mA)

Note:

1. The min V_ILand max V_IHvalues are based on the respective min and max BV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the BV_INsymbol referenced in Section 2.1.2, “Recommended Operating Conditions.”

This table provides the DC electrical characteristics for the integrated flash controller when operating at BV = 1.8 V.

DD

Table 56. Integrated Flash Controller DC Electrical Characteristics (1.8 V)

For recommended operating conditions, see Table 3

Parameter

Input high voltage

Symbol

Min

Max

Unit

Note

V_IH

V_IL

I_IN

1.25

—

0.6

40

V

1

2

Input low voltage

Input current

—

μA

(V_IN= 0 V or V_IN= BV_DD

)

Output high voltage

(BV_DD= min, I_OH= –0.5 mA)

V_OH

V_OL

1.35

—

V

—

Output low voltage

0.4

(BV_DD= min, I_OL= 0.5 mA)

Note:

1. The min V_ILand max V_IHvalues are based on the respective min and max BV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the BV_INsymbol referenced in Section 2.1.2, “Recommended Operating Conditions.”

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

83

Electrical Characteristics

2.13.2 IFC AC Timing Specifications

This section describes the AC timing specifications for the integrated flash controller.

2.13.2.1 Test Condition

This figure provides the AC test load for the integrated flash controller.

BV_DD/2

Output

Z₀= 50 Ω

R_L= 50 Ω

Figure 25. Integrated Flash Controller AC Test Load

2.13.2.2 IFC AC Timing Specifications

All output signal timings are relative to the falling edge of any IFC_CLK. The external circuit must use the rising edge of the

IFC_CLKs to latch the data.

All input timings are relative to the rising edge of IFC_CLKs.

This table describes the timing specifications of the integrated flash controller interface.

Table 57. IFC Timing Specifications (BV = 3.3 V, 2.5 V, and 1.8 V)

DD

For recommended operating conditions, see Table 3

Parameter

Symbol¹

Min

Max

Unit

Note

IFC_CLK cycle time

IFC_CLK duty cycle

Input setup

t_IBK

10

45

4

—

55

—

ns

%

—

t

_IBKH/t_IBK

t_IBIVKH

t_IBIXKH

t_IBKLOV

t_IBKLOX

ns

—

Input hold

1

—

Output delay

Output hold

—

–2

1.5

—

5, 6

Note:

1. All signals are measured from BV_DD/2 of rising/falling edge of IFC_CLK to BV_DD/2 of the signal in question.

2. Skew measured between different IFC_CLK signals at BV_DD/2.

3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current

delivered through the component pin is less than or equal to the leakage current specification.

4. t_IBONOTis a measurement of the maximum time between the negation of ALE and any change in AD when

FTIM0_CSn[TEAHC] = 0.

5. Here the negative sign means output transit happens earlier than the falling edge of IFC_CLK.

6. Here a convention has been followed in which the more negative/less-positive the number, the smaller the number would be.

For example –2 is smaller then –1 and –1 is smaller then 0. So if the min value of this parameter is shown as –2 ns than the

for any part parameter’s measure will never go to –3ns though it can go to –1 ns.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

84

Freescale Semiconductor

Electrical Characteristics

This figure shows the AC timing diagram.

IFC_CLK[m]

t_IBIXKH

t_IBIVKH

Input Signals

t_IBKLOV

t_IBKLOX

Output Signals

AD

(address phase)

ALE

t_IBKLOX

AD

(data phase)

Figure 26. Integrated Flash Controller Signals

Figure 26 applies to all the controllers that IFC supports.

For input signals, the AC timing data is used directly for all controllers. For output signals, each type of controller provides its

own unique method to control the signal timing. The final signal delay value for output signals is the programmed delay plus

the AC timing delay.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

85

Electrical Characteristics

This figure shows how the AC timing diagram applies to GPCM. The same principle also applies to other controllers of IFC.

IFC_CLK

address

AD[0:31]

read data

write data

address

t_eahc+ t_IBKLOV

_eadc+ t_IBKLOV

t

ALE

t_acse+ t_IBKLOV

CE_B

t_aco+ t

IBKLOV

t_rad+ t

IBKHOV

OE_B

WE_B

t_ch+ t_IBKLOV

t_cs+ t_IBKLOV

t_wp+ t_IBKLOV

BCTL

read

write

1

2

t_aco, t_rad, t_eahc, t_eadc, t_acse, t_cs, t_ch, t_wpare programmable. See the BSC9131 QorIQ Qonverge Multicore Baseband Processor

Reference Manual.

For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay

value for output signals is the programmed delay plus the AC timing delay.

Figure 27. GPCM Output Timing Diagram

2.14 Enhanced Secure Digital Host Controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC interface.

2.14.1 eSDHC DC Electrical Characteristics

This table provides the DC electrical characteristics for the eSDHC interface.

Table 58. eSDHC Interface DC Electrical Characteristics

At recommended operating conditions with BV_DD= 3.3 V or 1.8 V.

Characteristic

Input high voltage

Symbol

Condition

Min

Max

Unit

Note

V_IH

V_IL

—

0.625 × BV_DD

—

0.25 × BV_DD

—

V

1

Input low voltage

—

Output high voltage

Output low voltage

Output high voltage

V_OH

V_OL

V_OH

I_OH= –100 uA at BV_DDmin

I_OL= 100uA at BV_DDmin

I_OH= –100 uA

0.75 × BV_DD

—

2

0.125 × BV_DD

—

BV_DD- 0.2

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

86

Freescale Semiconductor

Electrical Characteristics

Table 58. eSDHC Interface DC Electrical Characteristics (continued)

At recommended operating conditions with BV_DD= 3.3 V or 1.8 V.

Characteristic

Output low voltage

Symbol

Condition

Min

Max

Unit

Note

V_OL

I_OL= 2 mA

—

0.3

10

V

2

Input/output leakage current

I_IN/I_OZ

–10

uA

—

Note:

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max BV_INvalues found in Figure 3.

2. Open drain mode for MMC cards only.

2.14.2 eSDHC AC Timing Specifications

This table provides the eSDHC AC timing specifications as defined in Figure 29.

Table 59. eSDHC AC Timing Specifications

At recommended operating conditions with BV_DD= 3.3 or 1.8 V

Parameter

Symbol¹

Min

Max

Unit

Note

SD_CLK clock frequency:

f_SFSCK

MHz

2, 4

SD/SDIO Full-speed/High-speed mode

MMC Full-speed/High-speed mode

0

25/50

20/52

SD_CLK clock low time—Full-speed/High-speed mode

SD_CLK clock high time—Full-speed/High-speed mode

SD_CLK clock rise and fall times

t_SFSCKL

t_SFSCKH

t_SFSCKR/

t_SFSCKF

10/7

—

3

ns

4

Input setup times: SD_CMD, SD_DATx

Input hold times: SD_CMD, SD_DATx

Output delay time: SD_CLK to SD_CMD, SD_DATx valid

Output delay time: SD_CLK to SD_CMD, SD_DATx hold time

Note:

t_SFSIVKH

t_SFSIXKH

t_SFSKHOV

t_SFSKHOX

2.5

—

3

ns

3, 4

4

–3

—

4

1. The symbols used for timing specifications herein follow the pattern of t_{(first three letters of functional block)(signal)(state)}

_{(reference)(state)}for inputs and t_{(first three letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_FHSKHOV

symbolizes eSDHC high speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the

output (O) reaching the invalid state (X) or output hold time. Note that, in general, the clock reference symbol representation

is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used

with the appropriate letter: R (rise) or F (fall).

2. In full speed mode, clock frequency value can be 0–25 MHz for a SD/SDIO card and 0–20 MHz for a MMC card. In high

speed mode, clock frequency value can be 0–50 MHz for a SD/SDIO card and 0–52 MHz for a MMC card.

3. To satisfy setup timing, one way board routing delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should

not exceed 1 ns for any high speed MMC card. For any high speed or default speed mode SD card, the one way board routing

delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should not exceed 1.5 ns.

4. CCARD ≤10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

87

Electrical Characteristics

This figure provides the eSDHC clock input timing diagram.

eSDHC

External Clock

VM

operational mode

t_SFSCKL

t_SFSCKH

t_SFSCK

t_SFSCKF

t_SFSCKR

VM = Midpoint Voltage (BV_DD/2)

Figure 28. eSDHC Clock Input Timing Diagram

This figure provides the data and command input/output timing diagram.

VM

SD_CK

External Clock

t_SFSIXKH

t_SFSIVKH

SD_DAT/CMD

Inputs

SD_DAT/CMD

Outputs

t_SFSKHOX

t_SFSKHOV

VM = Midpoint Voltage (BV_DD/2)

Figure 29. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock

2.15 Programmable Interrupt Controller (PIC) Specifications

This section describes the DC and AC electrical specifications for the PIC.

2.15.1 PIC DC Electrical Characteristics

This table provides the DC electrical characteristics for the PIC interface when operating at

CV /OV /BV /X1V /X2V = 3.3 V.

DD

Table 60. PIC DC Electrical Characteristics (3.3 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

2

—

0.8

40

V

1

2

—

Input current (CV_IN/OV_IN/BV_IN/X1V_IN/X2V_IN= 0V or

μA

CV_IN/OV_IN/BV_IN/X1V_IN/X2V_IN= CV_DD/OV_DD/BV_DD/X1V_DD/X2V_DD

)

Output high voltage (CV_DD/OV_DD/BV_DD/X1V_DD/X2V_DD= min,

I_OH= –2 mA)

V_OH

2.4

—

V

—

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

88

Freescale Semiconductor

Electrical Characteristics

Table 60. PIC DC Electrical Characteristics (3.3 V) (continued)

For recommended operating conditions, see Table 3.

Parameter

Output low voltage (CV_DD/OV_DD/BV_DD/X1V_DD/X2V_DD= min,

Symbol

Min

Max

Unit

Note

V_OL

—

0.4

V

—

I

_OL= 2 mA)

Note:

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max CV_IN/OV_IN/BV_IN/X1V_IN/X2V_INvalues

found in Table 3.

2. Note that the symbol CV_IN/OV_IN/BV_IN/X1V_IN/X2V_INrepresents the input voltage of the supply. See Table 3.

This table provides the DC electrical characteristics for the PIC interface when operating at LV /OV /BV /CV = 2.5 V.

DD

Table 61. PIC DC Electrical Characteristics (2.5 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

1.7

—

0.7

40

V

1

2

Input current (CV_IN/OV_IN/BV_IN/X1V_IN/X2V_IN= 0V or

CV_IN/OV_IN/BV_IN/X1V_IN/X2V_IN

CV_DD/OV_DD/BV_DD/X1V_DD/X2V_DD

—

μA

=

)

Output high voltage (CV_DD/OV_DD/BV_DD/X1V_DD/X2V_DD= min,

I_OH= –2 mA)

V_OH

V_OL

2.0

—

V

—

Output low voltage (CV_DD/OV_DD/BV_DD/X1V_DD/X2V_DD= min,

I_OL= 2 mA)

0.4

Note:

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max CV_IN/OV_IN/BV_IN/X1V_IN/X2V_INvalues

found in Table 3.

2. Note that the symbol CV_IN/OV_IN/BV_IN/X1V_IN/X2V_INrepresents the input voltage of the supply. See Table 3.

This table provides the DC electrical characteristics for the PIC interface when operating at LV /OV /BV /CV = 1.8 V.

DD

Table 62. PIC DC Electrical Characteristics (1.8 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

1.25

—

0.6

40

V

1

2

Input current (CV_IN/OV_IN/BV_IN/X1V_IN/X2V_IN= 0V or

CV_IN/OV_IN/BV_IN/X1V_IN/X2V_IN

CV_DD/OV_DD/BV_DD/X1V_DD/X2V_DD

—

μA

=

)

Output high voltage (CV_DD/OV_DD/BV_DD/X1V_DD/X2V_DD= min,

_OH= –2 mA)

V_OH

1.35

—

V

—

I

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

89

Electrical Characteristics

Table 62. PIC DC Electrical Characteristics (1.8 V) (continued)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Output low voltage (CV_DD/OV_DD/BV_DD/X1V_DD/X2V_DD= min,

V_OL

—

0.4

V

—

I_OL= 2 mA)

Note:

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max CV_IN/OV_IN/BV_IN/X1V_IN/X2V_INvalues

found in Table 3.

2. Note that the symbol CV_IN/OV_IN/BV_IN/X1V_IN/X2V_INrepresents the input voltage of the supply. See Table 3.

2.15.2 PIC AC Timing Specifications

This table provides the PIC input and output AC timing specifications.

Table 63. PIC Input AC Timing Specifications

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Max

Unit

Note

PIC inputs—minimum pulse width

t_PIWID

3

—

SYSCLK

1

Note:

1. PIC inputs and outputs are asynchronous to any visible clock. PIC outputs should be synchronized before use by any external

synchronous logic. PIC inputs are required to be valid for at least t_PIWIDns to ensure proper operation when working in

edge-triggered mode.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

90

Freescale Semiconductor

Electrical Characteristics

2.16 JTAG

This section describes the AC electrical specifications for the IEEE Std 1149.1™ (JTAG) interface. This section applies to both

the Power Architecture and DSP JTAG ports. The BSC9131 has multiple JTAG topology; see Section 3.9, “JTAG Configuration

Signals,” for details.

2.16.1 JTAG DC Electrical Characteristics

This table provides the JTAG DC electrical characteristics.

Table 64. JTAG DC Electrical Characteristics

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

V_IH

V_IL

2.1

—

0.8

40

—

V

1

Input current (OV_IN= 0V or OV_IN= OV_DD

)

I_IN

—

μA

V

2

Output high voltage (OV_DD= min, I_OH= –2 mA)

Output low voltage (OV_DD= min, I_OL= 2 mA)

Note:

V_OH

V_OL

2.4

—

0.4

V

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3

2. Note that the symbol OV_INrepresents the input voltage of the supply. It is referenced in Table 3.

2.16.2 JTAG AC Timing Specifications

This table provides the JTAG AC timing specifications as defined in Figure 30 through Figure 33.

Table 65. JTAG AC Timing Specifications

For recommended operating conditions see Table 3.

Parameter

Symbol¹

Min

Max

Unit

Note

JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock pulse width measured at 1.4 V

JTAG external clock rise and fall times

TRST_B assert time

f_JTG

t_JTG

0

30

15

0

33.3

—

2

MHz

ns

—

2

t_JTKHKL

t_JTGRand t_JTGF

t_TRST

ns

25

4

—

10

—

ns

Input setup times

t_JTDVKH

t_JTDXKH

t_JTKLDV

ns

—

3

Input hold times

10

4

ns

Output valid times

ns

Output hold times

t_JTKLDX

30

ns

3

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

91

Electrical Characteristics

Table 65. JTAG AC Timing Specifications (continued)

For recommended operating conditions see Table 3.

Parameter

Symbol¹

Min

Max

Unit

Note

JTAG external clock to output high impedance

t_JTKLDZ

4

10

ns

—

Note:

1. The symbols used for timing specifications follow the pattern t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_JTDVKHsymbolizes JTAG device timing

(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t_JTGclock reference (K) going to

the high (H) state or setup time. Also, t_JTDXKHsymbolizes JTAG timing (JT) with respect to the time data input signals (D)

reaching the invalid state (X) relative to the t_JTGclock reference (K) going to the high (H) state. Note that in general, the clock

reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. All outputs are measured from the midpoint voltage of the falling/rising edge of t_TCLKto the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays

must be added for trace lengths, vias, and connectors in the system.

This figure provides the AC test load for TDO and the boundary-scan outputs.

Z₀= 50 Ω

Output

OV_DD/2

R_L= 50 Ω

Figure 30. AC Test Load for the JTAG Interface

This figure provides the JTAG clock input timing diagram.

JTAG

External Clock

VM

t_JTKHKL

VM

t_JTGR

t_JTG

t_JTGF

VM = Midpoint Voltage (OV /2)

DD

Figure 31. JTAG Clock Input Timing Diagram

This figure provides the TRST_B timing diagram.

TRST_B

VM

t_TRST

VM = Midpoint Voltage (OV /2)

DD

Figure 32. TRST_B Timing Diagram

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

92

Freescale Semiconductor

Electrical Characteristics

This figure provides the boundary-scan timing diagram.

JTAG

VM

External Clock

t_JTDVKH

t_JTDXKH

Boundary

Data Inputs

Input

Data Valid

t_JTKLDV

t_JTKLDX

Boundary

Data Outputs

Output Data Valid

t_JTKLDZ

Boundary

Output Data Valid

Data Outputs

VM = Midpoint Voltage (OV /2)

DD

Figure 33. Boundary-Scan Timing Diagram

2

2.17 I C

2

This section describes the DC and AC electrical characteristics for the two I C interfaces. The input voltage for I C1 is provided

2

by a OV (3.3 V) power supply, while the input voltage for I C2 is provided by a CV (3.3 V/1.8 V) power supply.

DD

2.17.1 I²C DC Electrical Characteristics

2

This table provides the DC electrical characteristics for the I C interfaces operating from a 3.3 power supply.

2

Table 66. I C DC Electrical Characteristics (CV = 3.3 V)

DD

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

Output low voltage

V_IH

V_IL

2

—

0

—

0.8

0.4

50

V

1

2

3

4

V_OL

t_I2KHKL

I_I

V

Pulse width of spikes which must be suppressed by the input filter

0

ns

μA

Input current each I/O pin (input voltage is between 0.1 × OV_DDand

0.9 × OV_DD(max)

–10

10

Capacitance for each I/O pin

C_I

—

10

pF

—

Note:

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max CV_INvalues found in Table 3.

2. Output voltage (open drain or open collector) condition = 3 mA sink current.

3. See the BSC9131 QorIQ Qonverge Multicore Baseband Processor Reference Manual for information on the digital filter used.

4. I/O pins obstruct the SDA and SCL lines if OV_DDis switched off.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

93

Electrical Characteristics

2

This table provides the DC timing parameters for the I C interface operating from a 1.8 V power supply.

2

Table 67. I C DC Electrical Characteristics (CV = 1.8 V)

DD

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

V_IH

V_IL

1.25

—

0.6

40

—

V

1

Input current (CV_IN= 0 V or CV_IN= CV_DD

)

I_IN

—

μA

V

2

Output high voltage (CV_DD= mn, I_OH= –2 mA)

Output low voltage (CV_DD= min, I_OL= 2 mA)

Note:

V_OH

V_OL

1.35

—

0.4

V

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max CV_INvalues found in Figure 3.

2. Note that the symbol CV_INrepresents the input voltage of the supply. It is referenced in Figure 3.

2.17.2 I²C AC Electrical Specifications

2

This table provides the AC timing parameters for the I C interfaces.

2

Table 68. I C AC Electrical Specifications

For recommended operating conditions see Table 3. All values refer to V_IH(min) and V_IL(max) levels (see Table 66)

Parameter

Symbol¹

Min

Max

Unit

Note

SCL clock frequency

f_I2C

t_I2CL

0

400

—

kHz

μs

2

Low period of the SCL clock

1.3

0.6

—

High period of the SCL clock

t_I2CH

—

μs

Setup time for a repeated START condition

t_I2SVKH

t_I2SXKL

—

μs

Hold time (repeated) START condition (after this period, the first

clock pulse is generated)

—

μs

Data setup time

t_I2DVKH

t_I2DXKL

100

—

ns

—

3

Data hold time:

μs

CBUS compatible masters

I²C bus devices

—

0

—

Data output delay time

t_I2OVKL

—

0.6

0.9

—

μs

V

4

Set-up time for STOP condition

t

—

I2PVKH

Bus free time between a STOP and START condition

t_I2KHDX

V_NL

1.3

Noise margin at the LOW level for each connected device

(including hysteresis)

0.1 × OV_DD

Noise margin at the HIGH level for each connected device

(including hysteresis)

V_NH

Cb

0.2 × OV_DD

—

V

—

Capacitive load for each bus line

—

400

pF

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

94

Freescale Semiconductor

Electrical Characteristics

2

Table 68. I C AC Electrical Specifications (continued)

For recommended operating conditions see Table 3. All values refer to V_IH(min) and V_IL(max) levels (see Table 66)

Parameter

Symbol¹

Min

Max

Unit

Note

Note:

1. The symbols used for timing specifications herein follow the pattern t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_I2DVKHsymbolizes I²C timing (I2)

with respect to the time data input signals (D) reaching the valid state (V) relative to the t_I2Cclock reference (K) going to the

high (H) state or setup time. Also, t_I2SXKLsymbolizes I²C timing (I2) for the time that the data with respect to the START

condition (S) went invalid (X) relative to the t_I2Cclock reference (K) going to the low (L) state or hold time. Also, t_I2PVKH

symbolizes I²C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative

to the t_I2Cclock reference (K) going to the high (H) state or setup time.

2. The requirements for I²C frequency calculation must be followed. See Freescale application note AN2919, “Determining the

I2C Frequency Divider Ratio for SCL.”

3. As a transmitter, the device provides a delay time of at least 300 ns for the SDA signal (referred to as the V_IHminof the SCL

signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP

condition. When the device acts as the I²C bus master while transmitting, it drives both SCL and SDA. As long as the load on

SCL and SDA are balanced, the device does not generate an unintended START or STOP condition. Therefore, the 300 ns

SDA output delay time is not a concern. If under some rare condition, the 300 ns SDA output delay time is required for the

device as transmitter, application note AN2919 referred to in note 4 below is recommended.

4. The maximum t_I2OVKLhas only to be met if the device does not stretch the LOW period (t_I2CL) of the SCL signal.

2

This figure provides the AC test load for the I C.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

2

Figure 34. I C AC Test Load

2

This figure shows the AC timing diagram for the I C bus.

SDA

t_I2CF

t_I2CL

t_I2DVKH

t_I2KHKL

t_I2CF

t_I2SXKL

t_I2CR

SCL

t_I2SXKL

t_I2CH

t_{I2DXKL, I2OVKL}

t_I2SVKH

t_I2PVKH

t

S

Sr

P

S

2

Figure 35. I C Bus AC Timing Diagram

2.18 GPIO

This section describes the DC and AC electrical specifications for the GPIO interface.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

95

Electrical Characteristics

2.18.1 GPIO DC Electrical Characteristics

This table provides the DC electrical characteristics for the GPIO interface when operating from 3.3-V supply.

Table 69. GPIO DC Electrical Characteristics (3.3 V)

For recommended operating conditions, see Table 3

Parameter

Input high voltage

Symbol

Min

Max

Unit

Note

V_IH

V_IL

I_IN

2

—

0.8

40

V

1

2

Input low voltage

—

Input current

μA

(BV_IN= 0 V or BV_IN= BV_DD)

Output high voltage

(BV_DD= min, I_OH= –2 mA)

V_OH

V_OL

2.4

—

V

—

Low-level output voltage

(BV_DD= min, I_OL= 2 mA)

0.4

Note:

1. Note that the min V_ILand max V_IHvalues are based on the min and max BV_INrespective values found in Table 3.

2. Note that the symbol BV_INrepresents the input voltage of the supply. It is referenced in Table 3.

This table provides the DC electrical characteristics for the GPIO interface when operating from 2.5-V supply.

Table 70. GPIO DC Electrical Characteristics (2.5 V)

For recommended operating conditions, see Table 3.

Parameter

Input high voltage

Symbol

Min

Max

Unit

Note

V_IH

V_IL

I_IN

1.7

—

0.7

40

V

1

2

Input low voltage

Input current

—

μA

(BV_IN= 0 V or BV_IN= BV_DD)

Output high voltage

(BV_DD= min, I_OH= 2 mA)

V_OH

V_OL

1.7

—

V

—

Low-level output voltage

(BV_DD= min, I_OL= 2 mA)

0.7

Note:

1. Note that the min V_ILand max V_IHvalues are based on the min and max BV_INrespective values found in Table 3.

2. Note that the symbol BV_INrepresents the input voltage of the supply. It is referenced in Table 3.

This table provides the DC electrical characteristics for the GPIO interface when operating from 1.8-V supply.

Table 71. GPIO DC Electrical Characteristics (1.8 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

V_IH

V_IL

1.2

—

0.6

40

—

V

1

Input current (BV_IN= 0 V or BV_IN= BV_DD)

I_IN

—

μA

V

2

Output high voltage (BV_DD= min, I_OH= –0.5 mA)

Low-level output voltage (BV_DD= min, I_OL= 0.5 mA)

V_OH

V_OL

1.35

—

0.4

V

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

96

Freescale Semiconductor

Electrical Characteristics

Table 71. GPIO DC Electrical Characteristics (1.8 V) (continued)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Note:

1. Note that the min V_ILand max V_IHvalues are based on the min and max BV_INrespective values found in Table 3.

2. Note that the symbol BV_INrepresents the input voltage of the supply. It is referenced in Table 3.

2.18.2 GPIO AC Timing Specifications

This table provides the GPIO input and output AC timing specifications.

Table 72. GPIO Input AC Timing Specifications

For recommended operating conditions, see Table 3

Parameter

GPIO inputs—minimum pulse width

Note:

Symbol

Min

Unit

Note

t_PIWID

20

ns

1

1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any

external synchronous logic. GPIO inputs are required to be valid for at least t_PIWIDto ensure proper operation.

This figure provides the AC test load for the GPIO.

OV_DD/2

Output

Z = 50

Ω

0

R = 50

Ω

L

Figure 36. GPIO AC Test Load

2.19 TDM

This section describes the DC and AC electrical specifications for the TDM.

2.19.1 TDM DC Electrical Characteristics

This table provides the DC electrical characteristics for the TDM interface when operating at 3.3 V.

Table 73. TDM DC Electrical Characteristics (BV /X2V = 3.3 V)

DD

For recommended operating conditions, see Table 3.

Characteristic

Symbol

Min

Max

Unit

Note

Input high voltage

V_IH

V_IL

I_IN

2.0

–0.3

—

0.8

40

V

1

2

Input low voltage

Input current (BV_IN/X2V_IN= 0 V or

μA

BV_IN/X2V_IN= BV_DD/X2V_DD

Output high voltage (BV_DD/X2V_DD= min,

_OH= –2 mA)

Output low voltage (BV_DD/X2V_DD= min, I_OL= 2 mA)

)

V_OH

V_OL

2.4

—

V

—

I

0.4

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

97

Electrical Characteristics

Table 73. TDM DC Electrical Characteristics (BV /X2V = 3.3 V) (continued)

DD

For recommended operating conditions, see Table 3.

Characteristic

Note:

Symbol

Min

Max

Unit

Note

1. Note that the min V_ILand max V_IHvalues are based on the min and max BV_IN/X2V_INrespective values found in Table 3

2. Note that the symbol BV_IN/X2V_INrepresents the input voltage of the supply. It is referenced in Table 3

Table 74 provides the DC electrical characteristics for the TDM interface when operating at 2.5 V.

Table 74. TDM DC Electrical Characteristics (BV = 2.5 V)

DD

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

V_IH

V_IL

1.7

—

0.7

40

—

V

1

Input low voltage

Input current (BV_IN= 0 V or BV_IN= BV_DD

)

I_IN

—

μA

V

2

Output high voltage (BV_DD= min, I_OH= –2 mA)

Output low voltage (BV_DD= min, I_OL= 2 mA)

Note:

V_OH

V_OL

2.0

—

0.4

V

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max BV_INvalues found in Table 3.

2. Note that the symbol BV_INrepresents the input voltage of the supply. It is referenced in Table 3.

This table provides the DC electrical characteristics for the TDM interface when operating at 1.8 V.

Table 75. TDM DC Electrical Characteristics (BV /X2V = 1.8 V)

DD

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

V_IH

V_IL

I_IN

1.25

—

0.6

40

V

1

2

Input low voltage

Input current (BV_IN/X2V_IN= 0 V or

—

μA

BV_IN/X2V_IN= BV_DD/X2V_DD

Output high voltage (BV_DD/X2V_DD= min,

_OH= –2 mA)

)

V_OH

V_OL

1.35

—

V

—

I

Output low voltage (BV_DD/X2V_DD= min, I_OL= 2 mA)

0.4

Note:

1. Note that the min V_ILand max V_IHvalues are based on the min and max BV_IN/X2V_INrespective values found in Table 3

2. Note that the symbol BV_IN/X2V_INrepresents the input voltage of the supply. It is referenced in Table 3

2.19.2 TDM AC Electrical Characteristics

This table provides the input and output AC timing specifications for the TDM interface.

1

Table 76. TDM AC Timing Specifications for 62.5 MHz

Parameter

Symbol²

Min

Max

Unit

Note

TDMxRCK/TDMxTCK

t_DM

16.0

—

ns

3

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

98

Freescale Semiconductor

Electrical Characteristics

Table 76. TDM AC Timing Specifications for 62.5 MHz (continued)

1

Parameter

Symbol²

Min

Max

Unit

Note

TDMxRCK/TDMxTCK high pulse width

TDMxRCK/TDMxTCK low pulse width

TDM all input setup time

t_{DM_HIGH}

t_{DM_LOW}

7.0

3.6

1.9

2.5

—

ns

3

t_DMIVKH

—

4, 5

4, 8

5

TDMxRD input hold time

t_DMRDIXKH

t_DMFSIXKH

t_{DM_OUTAC}

t_DMTKHOV

t_DMTKHOX

t_{DM_OUTHI}

t_DMFSKHOV

t_DMFSKHOX

—

TDMxTFS/TDMxRFS input hold time

TDMxTCK high to TDMxTD output active

TDMxTCK high to TDMxTD output valid

TDMxTD hold time

—

7

9.8

—

7, 9

7

2.5

—

TDMxTCK high to TDMxTD output high impedance

TDMxTFS/TDMxRFS output valid

TDMxTFS/TDMxRFS output hold time

Note: Output values are based on 30 pF capacitive load.

9.8

9.25

—

7

—

6

2.0

6

Note: Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming

edge they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. t_DMxTCKand

t_DMxRCKare shown using the rising edge.

1. All values are based on a maximum TDM interface frequency of 62.5 MHz.

2. The symbols used for timing specifications follow the pattern t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_HIKHOXsymbolizes the output internal

timing (HI) for the time t_serialmemory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).

3. Relevant for all pins that function as TDM RX/TX clock—pins may be TDM_RCK and TDM_TCK, pending TDM port

configuration.

4. Relevant for all pins that function as TDM receive data—pins may be TDM_RCK, TDM_RSN, TDM_RDT, TDM_TDT, pending

TDM port configuration.

5. Relevant for all pins that function as TDM input frame sync (TX/RX)—pins may be TDM_TSN, TDM_RSN, pending TDM port

configuration.

6. Relevant for all pins that function as TDM output frame sync (TX/RX)—pins may be TDM_TSN, TDM_RSN, pending TDM port

configuration.

7. Relevant for all pins that function as TDM transmit data—pins may be TDM_RCK, TDM_RSN, TDM_RDT, TDM_TDT, pending

TDM port configuration.

8. Applies to any TDM pin that functions as Rx data (including TDMxTD and others).

9. Represents the time from the positive clock edge to the valid data on the Tx data like; it applies to any TDM pin that functions

as Tx data (including TDMxRD and others).

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

99

Electrical Characteristics

This figure shows the TDM receive signal timing.

t_DM

t_{DM_HIGH}

t_{DM_LOW}

TDMxRCK

t_DMIVKH

t_DMRDIXKH

TDMxRD

t_DMFSIXKH

t_DMIVKH

TDMxRFS

t_DMFSKHOV

t_DMFSKHOX

TDMxRFS (output)

Figure 37. TDM Receive Signals

This figure shows the TDM transmit signal timing.

t_DM

t_{DM_HIGH}

t_{DM_LOW}

t_{DM_OUTHI}

t_DMTKHOX

TDMxTCK

t_DMTKHOV

t_{DM_OUTAC}

TDMxTD

TDMxRCK

t_DMFSKHOV

t_DMFSKHOX

TDMxTFS (output)

t_DMFSIXKH

t_DMIVKH

TDMxTFS (input)

Figure 38. TDM Transmit Signals

This figure provides the AC test load for the TDM.

Output

V_DDIO/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 39. TDM AC Test Load

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

100

Freescale Semiconductor

Electrical Characteristics

2.20 Radio Frequency (RF) Interface

2.20.1 RF Parallel Interface

There are two RF interfaces—parallel and MaxPHY serial interfaces.

2.20.1.1 RF Parallel Interface DC Electrical Characteristics (eSPI2)

2.20.1.1.1 RF Parallel Interface DC Data Path

Table 77 provides the DC electrical characteristics for the RF parallel interface when operating at 3.3 V.

Table 77. RF Parallel Interface DC Electrical Characteristics (X1V , X2V = 3.3 V)

DD

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

2

—

0.8

40

V

1

2

—

Input current

μA

(X1V_IN/X2V_IN= 0 V or X1V_IN/X2V_IN= X1V_DD/X2V_DD

)

Output high voltage

(X1V_DD/X2V_DD= min, I_OH= –2 mA)

V_OH

V_OL

2.8

—

V

—

Output low voltage

0.3

(X1V_DD/X2V_DD= min, I_OL= 2 mA)

Note:

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max X1V_IN/X2V_INvalues found in Table 3.

2. Note that the symbol X1V_IN/X2V_INrepresent the input voltage of the power supplies. It is referenced in Table 3.

Table 78 provides the DC electrical characteristics for the RF interface when operating at 1.8 V.

Table 78. RF Parallel Interface DC Electrical Characteristics (X1V , X2V = 1.8 V)

DD

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Input high voltage

V_IH

V_IL

1.25

—

0.6

40

—

V

1

Input low voltage

Input current (X1V_IN/X2V_IN= 0 V or X1V_IN/X2V_IN= X1V_DD/X2V_DD

Output high voltage (X1V_DD/X2V_DD= min, I_OH= –2 mA)

Output low voltage (X1V_DD/X2V_DD= min, I_OL= 2 mA)

Note:

)

I_IN

—

μA

V

2

V_OH

V_OL

1.35

—

0.4

V

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max X1V_IN/X2V_INvalues found in Table 3.

2. Note that the symbol X1V_IN/X2V_INrepresents the input voltage of the supply. It is referenced in Table 3.

2.20.1.1.2

RF Parallel Interface DC Control Plane

See Table 33 in Section 2.9.1, “eSPI1 DC Electrical Characteristics,” for the DC specs for eSPI2, powered by X2V = 1.8 V.

DD

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

101

Electrical Characteristics

2.20.1.2 RF Parallel Interface AC Electrical Characteristics (eSPI2)

2.20.1.2.1

RF Parallel AC Data Interface

Table 79 provides the timing specifications for the RF parallel interface.

Table 79. RF Parallel Interface Timing Specification (3.3 V, 1.8 V)

1,2

Parameter

Data_clk (MCLK) clock period

Symbol

Min

Max

Unit

Note

t_PDCP

16.276

(61.44)

—

ns

(MHz)

—

t_PDMP

t_PDCD

45% of t_PDCP

—

ns

—

Data_clk (MCLK) and fb_clk (FCLK) pulse width

Delay between MCLK and FCLK at the external RFIC including

trace delay

7.32

MCLK input to FCLK output delay at the BSC9131 BBIC

t_PDMFD

t_PDOV

—

6.32

6.0

ns

—

Control/Data output valid time wrt FCLK during Tx from the

BSC9131 BBIC

Control/Data hold from FCLK during Tx from the BSC9131 BBIC

Control/Data setup wrt MCLK

t_PDOX

t_PDIV

t_PDIX

1.37

2.5

—

ns

3

—

Control/Data hold wrt MCLK

0.4

Note:

1

The max trace delay of MCLK from the external RFIC to the BSC9131 BBIC and FCK/TXNRX/ENABLE from BBIC to RFIC =

1 ns each.

2

3

The max allowable trace skew between MCLK/FCLK and the respective data/control is 70 ps.

1.37 ns includes 70 ps trace skew.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

102

Freescale Semiconductor

Electrical Characteristics

Launch edge at RFIC

during Rx (both pos

and neg edge of clock)

Launch edge at BBIC

during Tx (both pos

and neg edge of clock)

Capture edge wrt

the shown launch

edge (opp. of the

launch edge)

MCLK

(data_clk)

at BBIC

FB_CLK

at BBIC

t_PDCP

BBIC Tx

Data/Control

RX_DATA/

t_PDOX

RX_FRAME

t_PDOV

MCLK input to FCLK out-

put delay at BBIC end

t_PDIV

t_PDIX

Figure 40. RF Parallel Interface AC Timing Diagram

2.20.1.2.2

RF Parallel Interface AC Control Plane

Table 80. RF Parallel Control Plane Interface AC Timing Specification

Parameter

Symbol

Min

Max

Unit

Control plane clock period

Clock min pulse width

t_PCCP

t_PCMP

33.3 (30)

16.6

—

ns (MHz)

ns

PCB trace delay between the BSC9131 BBIC master and the

external RFIC slave

t_PCBD

—

1

ns

Setup time from CPCSB assertion to first rising edge of SPICLK

Hold time from last SPICLK falling edge to CPCSB deassertion

MOSI data output setup time against SPICLK

t_PCSC

t_PCHC

t_PCOV

t_PCOX

t_PCIV

6.1

9.9

—

ns

—

15.4

—

MOSI data ouptut hold time against SPICLK

–16.4

7.9

MISO data input setup time against SPICLK

—

MISO data input hold time against SPICLK

t_PCIX

21.9

—

Note: RF parallel control plane is SPI2; RF serial control plane is SPI3 and SPI4.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

103

Electrical Characteristics

ci=0; cp=1

CPCSB

Launch edge at BBIC

(always rise-edge)

Capture edge at BBIC

(always fall-edge)

SPICLK (BBIC)

MOSI

t_PCOX

t_PCSC

t_PCOV

Capture edge at RFIC

SPICLK (RFIC)

MISO

t_BD+ t_CQ

t_PCIX

t_BD

t_PCIV

t_BD: Board delay from the BSC9131 BBIC to the external RFIC or

back

t_CQ: Delay in RFIC from input of SPICLK to output valid data

Max permissible board skew: 100 ps

Data timing at RF parallel interface:

Input data setup requirement: 1 ns

Input data hold requirement: 0 ns

t_CQ: 4.5 ns–6.5 ns (6.5 ns is critical, which defines

the max frequency)

Proposed frequency of SPICLK: 30 MHz

Figure 41. RF Parallel Control Plane Interface AC Timing Diagram

2.20.2 RF Serial (MaxPHY) Interface

2.20.2.1 RF Serial (MaxPHY) Interface DC Electrical Characteristics (eSPI3,

eSPI4)

2.20.2.1.1

RF Serial (MaxPHY) Interface DC Data Path

Table 81. RF Serial Interface DC Electrical Characteristics

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

Differential input logic high

Differential input logic low

Differential input high AC

Differential input low AC

V_IHdiff

V_ILdiff

0.200

—

V

1, 2

2

–0.200

—

V_IHdiff(AC)

V_ILdiff(AC)

0.350

—

–0.350

2

Note:

1. Used to define a differential signal slew rate.

2. These values are not defined. However, each signal must be within the respective limites for inputs as well as the limitations

for overshoot and undershoot (see Table 82 for specifications).

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

104

Freescale Semiconductor

Electrical Characteristics

Table 82 provides the AC overshoot/undershoot specifications; see Figure 42 for the areas referenced.

Table 82. AC Overshoot/Undershoot Specification for Clock and Data

Parameter

Maxim 153.6 MHz

Maximum peak amplitude allowed for overshoot area

Maximum peak amplitude allowed for undershoot area

Maximum overshoot area above RVDD

0.4

0.25

Maximum overshoot area below GND

Maximum Amplitude

Overshoot Area

VDDQ

VSSQ

Volts

(V)

Undershoot Area

Maximum Amplitude

Time (ns)

Figure 42. RF Serial Interface AC Overshoot/Undershoot Diagram

2.20.2.1.2

RF Serial (MaxPHY) Interface DC Control Plane

See Table 33 in Section 2.9.1, “eSPI1 DC Electrical Characteristics,” for the DC specs for eSPI3 and eSPI4, powered by

X1V = 1.8 V.

DD

2.20.2.2 RF Serial (MaxPHY) Interface AC Electrical Characteristics (eSPI3,

eSPI4)

2.20.2.2.1

RF Serial (MaxPHY) AC Data Interface

Table 83 provides the timing specifications for the RF parallel interface.

Table 83. RF Serial Interface Timing Specification

Parameter

Symbol

Min

Max

Unit

Note

TXCLK max period (frequency)

t_SDCP

t_SDOV

6.51 (153.6)

—

ns (MHz)

ns

1

2

3.08

Setup time to falling edge of TXCLK

Hold time to falling edge of TXCLK

t_SDOX

–3.05

—

ns

2

Note:

1

The maximum trace skew between TXLCK and data is estimated <50 ps.

Assuming 50 ps worst trace skew.

2

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

105

Electrical Characteristics

Launch edge of clock at

BBIC (always at rise edge)

Capture edge of clock at

RFIC (always at fall edge)

TXCLK

Tx data

t_SDOV

t_SDOX

Figure 43. RF Serial Interface AC Timing Diagram

2.20.2.2.2

RF Serial (MaxPHY) Interface AC Control Plane

Table 84. RF Serial Control Plane Interface AC Timing Specification

Parameter

Symbol

Min

Max

Unit

Note

Control plane clock period (frequency)

Clock min pulse width

t_SCCP

t_SCMP

50 (20)

20

—

ns (MHz)

ns

—

PCB trace delay between the BSC9131 BBIC master and the

external RFIC slave

t_SCBP

—

1

ns

—

Setup time from CS assertion to first SPICLK rising edge

Hold time from last SPICLK falling edge to CS deassertion

MOSI data output setup time against SPICLK

MOSI data ouptut hold time against SPICLK

MISO data input setup time against SPICLK

MISO data input hold time against SPICLK

Note:

t_SCSC

t_SCHC

t_SCOV

t_SCOX

t_SCIV

5

—

ns

—

1

—

10.4

—

–10.4

10.4

31

—

2

—

t_SCIX

—

1

Wrt 30 MHz SPICLK

2

Wrt 25 MHz SPICLK

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

106

Freescale Semiconductor

Electrical Characteristics

CI=0; CP=0; CS0AFT=1

MAXIMCNTL[SPI_READ_EN1] and MAXIMCNTL[SPI_READ_EN2]

Launch edge at BBIC

(always fall-edge)

Capture edge at BBIC

(always rise-edge)

SPICLK (BBIC)

MOSI

t_SCOX

t_SCOV

PICLK (RFIC)

MISO

t_BD

t_BD+ t_CQ

t_SCIV

t_SCIX

Data timing at RF serial interface:

Input data setup requirement: 6 ns

Input data hold requirement: 6 ns

t

_BD: Board delay from either side

t_CQ: Data delay wrt to clock at the external RFIC

Proposed max frequency: 25 MHz

t_CQ: 12.5 ns

Max board skey permissible: 100 ps

Figure 44. RF Serial Control Plane Interface AC Timing Diagram

2.20.2.2.3

RF Serial (MaxPHY) Jitter and Skew Specfications

Table 85. RF Serial (MaxPHY) Jitter and Skew Specifications

Parameter

Symbol

Max

Unit

Comments

Rx Path

Jitter introduced in Rx path (peak-to-peak)

Skew introduced between I and Q in Rx path

t_SDIJ

705

118

ps

Where D_J= 345 ps, R_J= 360 ps p-p

—

t_SDIIQS

Skew introduced between differential I & Q pair

in Rx path

t_SDIDS

149

ps

—

Tx Path

Jitter introduced in Tx path (peak-to-peak)

Skew introduced between I and Q in Tx path

t_SDOJ

725

117

ps

—

t_SDOIQS

Skew introduced between differential I & Q pair

in Tx path

t_SDODS

73

ps

—

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

107

Electrical Characteristics

2.20.3 Pulse-Width Modulator (PWM)

There are two pulse-width modulators (PWM). Both PWMs are connected at two different pins. The output of PWM is

pulse-width modulated signal (PWMO) available at external output pin.

2.20.3.1 PWM Timing

Figure 45 shows the timing diagram of PWM.

1

PWM Output

2b

2a

Figure 45. PWM Timing Diagram

Table 86 lists the PWM output timing characteristics.

Table 86. PWM Output Timing Parameter

Ref No.

Parameter

Minimum

Maximum

Unit

1

Output pulse width

Output rise time

Output fall time

(1/f_{platform_clk}

TBD

)

—

ns

2a

2b

TBD

2.21 Universal Subscriber Identity Module (USIM)

The USIM module interface consist of a total of five pins. Only “Internal One Wire” interface mode is supported. In this mode,

the Rx input of the USIM IP is connected to the TX output of the USIM, which is internal to the device. Only one bidirectional

signal (Rx/Tx) is routed to the device pin, which is connected to the external SIM card.

The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides a clock for the SIM

card to use. The frequency of this clock is normally 372 times the data rate on the Rx/Tx pins; however, the SIM module can

work with CLK equal to 16 times the data rate on Rx/Tx pins.

There is no timing relationship between the clock and the data. The clock that the SIM module provides to the SIM card will

be used by the SIM card to recover the clock from the data much like a standard UART. All five pins of SIM module are

asynchronous to each other.

There are no required timing relationships between the pads in normal mode, The SIM card is initiated by the interface device,

whereupon the SIM card will send a response with an Answer to Reset. Although the SIM interface has no specific requirement,

the ISO-7816 specifies reset and power down sequences. For detailed information, see ISO-7816.

The USIM interface pins are available at two locations. At one location, it is multiplexed with eSDHC and TDM functionality

and is powered by the BVDD power supply (3.3V/2.5V/1.8V). At the other location, it is multiplexed with eSPI and UART

functionality and is powered by CVDD power supply (3.3V/1.8V).

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

108

Freescale Semiconductor

Electrical Characteristics

2.21.1 USIM DC Electrical Characteristics

This table provides the DC electrical characteristics for the USIM interface.

Table 87. USIM Interface DC Electrical Characteristics

At recommended operating conditions with BV_DD= 3.3 V/2.5 V/1.8 V.

Characteristic

Input high voltage

Symbol

Condition

Min

Max

Unit

Note

V_IH

V_IL

—

0.625 × BV_DD

—

V

1

Input low voltage

Output high voltage

Output low voltage

Output high voltage

Output low voltage

Input/output leakage current

Note:

—

I_OH= –100 uA at BV_DDmin

I_OL= 100uA at CV_DDmin

I_OH= –100 uA

I_OL= 2 mA

—

0.75 × BV_DD

—

0.25 × BV_DD

V_OH

V_OL

—

V

—

2

0.125 × BV_DD

V

V_OH

V_OL

BV_DD- 0.2

—

0.3

10

V

2

I_IN/I_OZ

—

–10

uA

—

1. Note that the min V_ILand max V_IHvalues are based on the respective min and max BV_INvalues found in Figure 3.

2. Open drain mode for SIM cards only.

2.21.2 USIM General Timing Requirements

The timing requirements for the USIM are found in Table 88.

Table 88. USIM Timing Specification, High Drive Strength

Parameter

Symbol

Min

Max

Unit

Note

USIM clock frequency (SIM_CLK)

USIM clock rise time (SIM_CLK)

USIM clock fall time (SIM_CLK)

USIM input transition time (SIM_TRXD, SIM_PD)

USIM I/O rise time / fall time (SIM_TRXD)

USIM RST rise time / fall time (SIM_RST)

Note:

S_freq

S_rise

S_fall

0.01

—

25

MHz

ns

1

2

0.09 × (1/S_freq

)

—

0.09* × 1/S_freq

)

ns

2

S_trans

Tr/Tf

10

—

25

1

ns

—

3

μs

—

1

μs

4

1

50% duty cycle clock

2

With C = 50 pF

3

With CIN = 30 pF, COUT = 30 pF

4

With C_IN= 30 pF

1/SI1

SIM_CLK

SI3

Figure 46. USIM Clock Timing Diagram

SI2

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

109

Electrical Characteristics

2.21.3 USIM External Pull Up/Pull Down Resistor Requirements

External off-chip pull up resistor of 20 KΩ is required on the SIM_TRXD pin.

External off-chip pull down resistors are required on the SIM_PD, SIM_SVEN, SIM_RST pins.

2.21.4 USIM Reset Sequence

2.21.4.1 SIM Cards With Internal Reset

The sequence of reset for this kind of SIM cards is as follows (see Figure 47):

•

After power up, the clock signal is enabled on SIM_CLK (time T0).

After 200 clock cycles, Rx must be high.

The card must send a response on Rx acknowledging the reset between 400 and 40000 clock cycles after T0.

SIM_SVEN

SIM_CLK

RESPONSE

SIM_TRXD

SI7

SI8

T0

Figure 47. Internal-Reset Card Reset Sequence

Table 89. Parameters of Reset Sequence For Card With Internal Reset

ID

Parameter

Symbol

Min

Max

Unit

SI7

SI8

SIM clock to SIM TX data H

S_clk2dat

S_clk2atr

—

200

SIM_CLK clock cycle

SIM clock to SIM get ATR data

400

40000

2.21.4.2 SIM Cards With Active-Low Reset

The sequence of reset for this kind of card is as follows (see Figure 48):

•

After powering up, the clock signal is enabled on SIM_CLK (time T0).

After 200 clock cycles, SIM_TRXD must be high.

SIM_RST must remain Low for at least 40000 clock cycles after T0 (no response is to be received on Rx during those

40000 clock cycles).

•

SIM_RST is set High (time T1).

SIM_RST must remain High for at least 40000 clock cycles after T1 and a response must be received on SIM_TRXD

between 400 and 40000 clock cycles after T1.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

110

Freescale Semiconductor

Electrical Characteristics

SIM_SVEN

SIM_RST

SIM_CLK

RESPONSE

SIM_TRXD

SI9

SI10

SI11

T0

T1

Figure 48. Active-Low Reset Card Reset Sequence

Table 90. Parameters of Reset Sequence For Active-Low Reset Card

ID

Parameter

SIM clock to SIM TX data H

Symbol

Min

Max

Unit

SI9

S_clk2dat

S_clk2atr

S_clk2rst

—

200

40000

—

SIM_CLK clock cycle

SI10 SIM reset rising to SIM TX data low

SI11 SIM clock to SIM reset signals

400

40000

2.21.4.3 USIM Power Down Sequence

Power down sequence for SIM interface is as follows:

•

SIM_PD port detects the removal of the SIM card

SIM_RST goes low

SIM_CLK goes low

SIM_TRXD goes low

SIM_SVEN goes low

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

111

Electrical Characteristics

Each of these steps is done in one CKIL period (typically 32 KHz). Power down is initiated by detection of a SIM card removal

or is launched by the processor. See Figure 49 and Table 91 for the timing requirements for this sequence, with F

frequency value.

= CKIL

CKIL

SIM_PD

SIM_RST

SI12

SIM_CLK

SI13

SIM_TRXD

SI14

SIM_SVEN

Figure 49. SmartCard Interface Power Down AC Timing

Table 91. Timing Requirements for Power Down Sequence

ID

Parameter

Symbol

Min

Max

Unit

SI12 USIM reset to USIM clock stop

S_rst2clk

S_rst2dat

S_rst2ven

S_pd2rst

0.9 × 1/Fckil

1.8 × 1/Fckil

2.7 × 1/Fckil

0.9 × 1/Fckil

1.1 × 1/F_CKIL

2.2 × 1/F_CKIL

3.3 × 1/F_CKIL

1.1 × 1/F_CKIL

ns

SI13 USIM reset to USIM Tx data low

SI14 USIM reset to USIM voltage enable low

SI15 USIM presence detect to USIM reset low

2.22 Timers and Timers_32b AC Timing Specifications

This table lists the timer input AC timing specifications.

Table 92. Timers Input AC Timing Specifications

For recommended operating conditions, see Table 3.

Parameter

Timers inputs—minimum pulse width

Note:

1. The maximum allowed frequency of timer outputs is 125 MHz. Configure the timer modules appropriately.

Symbol

Minimum

Unit

ns

Note

T_TIWID

8

1, 2

2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any

external synchronous logic. Timer inputs are required to be valid for at least t_TIWIDns to ensure proper operation.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

112

Freescale Semiconductor

Hardware Design Considerations

This figure shows the AC test load for the timers.

Output

V_DDIO/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 50. Timer AC Test Load

3

Hardware Design Considerations

This section discusses the hardware design considerations.

3.1

Power Architecture System Clocking

This section describes the PLL configuration for the Power Architecture side of the device. Note that the platform clock is

identical to the internal core complex bus (CCB) clock.

This device includes 3 PLLs, as follows:

•

The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio

between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in

Section 3.1.2, “Power Architecture Platform to SYSCLK PLL Ratio.”

The e500 core PLL generates the core clock from the platform clock. The frequency ratio between the e500 core clock

and the platform clock is selected using the e500 PLL ratio configuration bits as described in Section 3.1.3, “e500 Core

to Platform Clock PLL Ratio.”

The DDR PLL generates the clocking for the DDR SDRAM controller. The frequency ratio between DDR clock and

platform clock is selected using the DDR PLL ratio configuration bits as described in section Section 3.1.4, “Power

Architecture DDR/DDRCLK PLL Ratio.”

•

The MAPLE eTVPE clock is sourced from the DDR PLL and has a maximum frequency of 800 MHz.

3.1.1

Power Architecture Clock Ranges

Table 93 provides the clocking specifications for the processor core and platform.

Table 93. Power Architecture Processor Clocking Specifications

Maximum Processor Core

Frequency

Characteristic

Unit

Note

Min

Max

e500 core processor frequency

Platform CCB bus clock frequency

400

267

1000

500

MHz

1, 2, 3

1, 4, 5

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

113

Hardware Design Considerations

Table 93. Power Architecture Processor Clocking Specifications (continued)

Maximum Processor Core

Frequency

Characteristic

Unit

Note

Min

Max

Note:

1. Caution: The Power Architecture platform clock to SYSCLK ratio and e500 core to platform clock ratio settings must be

chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and platform clock frequency do not exceed their

respective maximum or minimum operating frequencies. See Section 3.1.2, “Power Architecture Platform to SYSCLK PLL

Ratio,” and Section 3.1.3, “e500 Core to Platform Clock PLL Ratio” and Section 3.1.4, “Power Architecture DDR/DDRCLK PLL

Ratio,” for ratio settings.

2. The minimum e500 core frequency is based on the minimum platform clock frequency of 267 MHz.

3. The reset config signal cfg_core_speed must be pulled low if the core frequency is 500 MHz or below.

4. These values are preliminary and subject to change.

5. The reset config signal cfg_plat_speed must be pulled low if the CCB bus frequency is lower than 320 MHz.

The DDR memory controller can run in asynchronous mode.

Table 94 provides the clocking specifications for the memory bus.

Table 94. Power Architecture Memory Bus Clocking Specifications

Characteristic

Memory bus clock frequency

Note:

Min

Max

Unit

Note

320

400

MHz

1, 2, 3

1. Caution: The platform clock to SYSCLK ratio and e500 core to platform clock ratio settings must be chosen such that the

resulting SYSCLK frequency, e500 (core) frequency, and platform frequency do not exceed their respective maximum or

minimum operating frequencies. See Section 3.1.2, “Power Architecture Platform to SYSCLK PLL Ratio,” and Section 3.1.3,

“e500 Core to Platform Clock PLL Ratio,” and Section 3.1.4, “Power Architecture DDR/DDRCLK PLL Ratio,” for ratio settings.

2. The memory bus clock refers to the memory controllers’ Dn_MCK[0:5] and Dn_MCK[0:5]_B output clocks, running at half of

the DDR data rate.

3. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. See Section 3.1.4, “Power Architecture

DDR/DDRCLK PLL Ratio.” The memory bus clock speed must be less than or equal to the platform clock rate, which in turn

must be less than the DDR data rate.

As a general guideline, the following procedures can be used for selecting the DDR data rate or platform frequency:

1. Start with the processor core frequency selection.

2. Once the processor core frequency is determined, select the platform frequency from the options listed in Table 96 and

Table 100.

3. Check the platform to SYSCLK ratio to verify a valid ratio can be chosen from Table 98.

4. Please note that the DDR data rate must be greater than the platform frequency. In other words, running DDR data rate

lower than the platform frequency is not supported.

5. Verify all clock ratios to ensure that there is no violation to any clock and/or ratio specification.

3.1.2

Power Architecture Platform to SYSCLK PLL Ratio

The clock that drives the internal CCB bus is called the platform clock. The frequency of the platform clock is set using the

following reset signals, as shown in Table 95:

•

SYSCLK input signal

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

114

Freescale Semiconductor

Hardware Design Considerations

•

Binary value on IFC_AD[0:2] at power up

These signals must be pulled to the desired values.

In asynchronous mode, the memory bus clock frequency is decoupled from the platform bus frequency.

Table 95. Power Architecture Platform/SYSCLK Clock Ratios

Binary Value of IFC_AD[0:2] Signals

Platform: SYSCLK Ratio

000

001

4:1

5:1

010

6:1

All Others

Reserved

3.1.3

e500 Core to Platform Clock PLL Ratio

The clock ratio between the e500 core and the platform clock is determined by the binary value of IFC_AD[3:5] signals at power

up. Table 96 describes the supported ratios. There are no default values for these PLL ratios; these signals must be pulled to the

desired values. Note that IFC_AD[6] must be pulled low if the core frequency is 500 MHz or below.

Table 96. e500 Core to Platform Clock Ratios

Binary Value of

IFC_AD[3:5]Signals

e500 Core: Platform

Ratio

010

011

1:1

1.5:1

2:1

100

101

2.5:1

3:1

110

All Others

Reserved

3.1.4

Power Architecture DDR/DDRCLK PLL Ratio

Table 97 describes the clock ratio between the DDR memory controller complex and the DDR PLL reference clock, DDRCLK,

which is not the memory bus clock. The DDR memory controller complex clock frequency is equal to the DDR data rate.

The DDR PLL rate to DDRCLK ratios listed in Table 97 reflects the DDR data rate to DDRCLK ratio, since the DDR PLL rate

in asynchronous mode means the DDR data rate resulting from DDR PLL output. This ratio is determined by the binary value

of the IFC_AD[7].

Table 97. Power Architecture DDR Clock Ratio

Binary Value of {IFC_AD[7],

DDR:DDRCLK Ratio

IFC_ADDR[22]} Signal

00

01

10

11

8:1

10:1

12:1

Reserved

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

115

Hardware Design Considerations

3.1.5

Power Architecture SYSCLK and Platform Frequency Options

Table 98 shows the expected frequency options for SYSCLK and platform frequencies.

Table 98. Power Architecture SYSCLK and Platform Frequency Options

SYSCLK Frequency (MHz)

Platform:SYSCLK

66.66

80

100

Platform Frequency (MHz)¹

4:1

5:1

6:1

267

333

400

320

400

480

400

500

600

1)

Platform frequency values are shown rounded down to the nearest whole number (decimal place accuracy removed).

3.2

DSP System Clocking

This section describes the PLL configuration for the DSP side of the device. Note that the platform clock is identical to the

internal core complex bus (CCB) clock.

This device has the following PLL:

•

One SC3850 core PLL

3.2.1

DSP Clock Ranges

Table 99 provides the clocking specifications for the SC3850 processor core.

Table 99. DSP Processor Clocking Specifications

DSP Core

Minimum Frequency

800

Maximum Frequency

1000

Unit

SC3850 core

MHz

3.2.2

DSPCLKIN and SC3850 Core Frequency Options

Table 100 shows the expected frequency options for DSPCLKIN and SC3850 core frequencies.

Table 100. Options for SC3850 Core Clocking

DSPCLKIN Frequency (MHz)

PLL_T2 MF

66.66

80

100

133

SC3850 Core Frequency (MHz)

1

66.66

533

80

640

800

960

—

100

800

1000

—

133

1066

—

8

10

12

15

667

800

—

1000

—

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

116

Freescale Semiconductor

Hardware Design Considerations

3.3

Supply Power Default Setting

This device is capable of supporting multiple power supply levels on its I/O supply. Table 101 through Table 105 shows the

encoding used to select the voltage level for each I/O supply. When setting the VSEL signals, "1" is selected through a pull-up

resistor to OVDD (as seen in Table 1).

Table 101. Default Voltage Level for BV

DD

BVDD_VSEL[0:1]

I/O Voltage Level

00

01

10

11

3.3 V

2.5 V

1.8 V

Reserved

Table 102. Default Voltage Level for CV

DD

CVDD_VSEL

I/O Voltage Level

0

1

3.3 V

1.8 V

Table 103. Default Voltage Level for X1V

DD

X1VDD_VSEL

I/O Voltage Level

0

1

3.3 V

1.8 V

Table 104. Default Voltage Level for X2V

DD

XVDD2_VSEL

I/O Voltage Level

0

1

3.3 V

1.8 V

Table 105. Default Voltage Level for LV

DD

LVDD_VSEL

I/O Voltage Level

0

1

3.3 V

2.5 V

3.4

PLL Power Supply Design

Each of the PLLs listed above is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CORE,

AVDD_DDR, AVDD_DSP, and AVDD_RF respectively). The AV level should always be equivalent to V , and these

DD

DDC

voltages must be derived directly from V

through a low frequency filter scheme.

DDC

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

117

Hardware Design Considerations

The recommended solution for PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated in

Figure 51, one for each of the AV pins. By providing independent filters to each PLL the opportunity to cause noise injection

DD

from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLL’s resonant frequency range from a 500-kHz to 10-MHz range. It should be built

with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of

Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small

capacitors of equal value are recommended over a single large value capacitor.

Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize noise coupled from

DD

nearby circuits. It should be possible to route directly from the capacitors to the AV pin, which is on the periphery of 624 ball

DD

FCPBGA the footprint, without the inductance of vias.

Figure 51 shows the core PLL (AV

) power supply filter circuit.

DD_CORE

AV_{DD_PLAT}/AV_{DD_CORE}

AV_{DD_DDR}/AV_{DD_DSP}

C2

Low ESL Surface Mount Capacitors

/

V_DDC

R

C1

GND

Notes:

R = 5Ω 5%

C1 = 10µF 10%, 603, X5R with ESL ≤ 0.5 nH

C2 = 1.0µF 10%, 402 X5R with ESL ≤ 0.5 nH

This circuit applies for system PLL, core PLL, DDR PPLL, and DSP PLL.

Figure 51. PLL Power Supply Filter Circuit

The AVDD_RF signal provides power for the RF PLL. This PLL generates clock for communication with the MaxPHY RF

interface controller. This supply should be after low pass filter from board. Filter components, a resistor and three capacitors

are required on this supply. The resistor should be connected between platform 1 V and AVDD_RF. Platform 1 V should be

directly tapped from a 1 V regulator using a star connection. Place capacitors in parallel on AVDD_RF pin, physically close to

chip. See Figure 52.

1.0 Ω

V_DDC

AV_{DD_RF}

2.2 µF ¹

0.003 µF

GND

1. An 0805 sized capacitor is recommended for system initial bring-up

Figure 52. RF PLL Power Supply Filter Circuit

3.5

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high

frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching

other components in the system, and the device itself requires a clean, tightly regulated source of power. Therefore, it is

recommended that the system designer place at least one decoupling capacitor at each VDD, BVDD, CVDD, OVDD, GVDD,

LVDD, RVDD, X1VDD, and X2VDD pin of the device. These decoupling capacitors should receive their power from separate

VDD, BVDD, OVDD, GVDD, LVDD, RVDD, X1VDD, X2VDD, and GND power planes in the PCB, utilizing short traces to

minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround

the part.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

118

Freescale Semiconductor

Hardware Design Considerations

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be

used to minimize lead inductance, preferably 0402 or 0201 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the V , BV

,

DD

OV , GV , and LV planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have

DD

a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to

the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS

tantalum or Sanyo OSCON).

3.6

Pull-Up and Pull-Down Resistor Requirements

2

The device requires weak pull-up resistors on open drain type pins including I C pins (1 kΩ is recommended) and MPIC

interrupt pins (2–10 kΩ is recommended).

Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 54.

Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions,

because most have asynchronous behavior, and spurious assertion gives unpredictable results.

3.7

Output Buffer DC Impedance

The drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver

2

type (open drain for I C).

To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV or GND. Then, the

0

DD

value of each resistor is varied until the pad voltage is OV /2 (see Figure 53). The output impedance is the average of two

DD

components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and

R is trimmed until the voltage at the pad equals OV /2. R then becomes the resistance of the pull-up devices. R and R

P

DD

P

N

are designed to be close to each other in value. Then, Z = (R + R ) ÷ 2.

0

P

N

OV_DD

R_N

SW2

SW1

Pad

Data

R_P

OGND

Figure 53. Driver Impedance Measurement

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

119

Hardware Design Considerations

Table 106 summarizes the signal impedance targets. The driver impedances are targeted at minimum V

, nominal OV

,

DD

DDC

90°C.

Table 106. Impedance Characteristics

IFC, Ethernet, DUART, Control, Configuration, Power

Impedance

DDR DRAM

Symbol

Unit

Management

R

43 Target

20 Target

Z₀

W

N

P

Note: Nominal supply voltages. See Table 2.

3.8

Configuration Pin Muxing

The device provides the user with power-on configuration options which can be set through the use of external pull-up or

pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as

output only pins in normal operation.

While HRESET_B is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET_B

is asserted, is latched when HRESET_B deasserts, at which time the input receiver is disabled and the I/O circuit takes on its

normal function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 kΩ.

This value should permit the 4.7-kΩ resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is

enabled only during HRESET_B (and for platform/system clocks after HRESET_B deassertion to ensure capture of the reset

value). When the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with

minimal signal quality or delay disruption. The default value for all configuration bits treated this way has been encoded such

that a high voltage level puts the device into the default state and external resistors are needed only when non-default settings

are required by the user.

Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down

resistor should minimize the disruption of signal quality or speed for output pins thus configured.

The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices.

3.9

JTAG Configuration Signals

There are two JTAG ports:

•

Power Architecture JTAG (TDI, TDO, TMS, TCK, and TRST_B)

DSP JTAG (DSP_TDI, DSP_ TDO, DSP_TMS, DSP_TCK, and DSP_TRST_B)

Note that the DSP JTAG is available as a muxed option on I/O pins.

The Power Architecture JTAG is the primary JTAG interface of the chip. DSP JTAG is defined as optional debug interface. As

seen in Table 107, the JTAG topology is selectable by static value driven on two pins—CFG_0_JTAG_MODE and

CFG_1_JTAG_MODE.

Table 107. JTAG Topology

Uses Power

Architecture

Debug Header

{CFG_0_JTAG_MODE,

CFG_1_JTAG_MODE}

Uses DSP

Debug Header

JTAG Topology

00

Yes

No

Access Power Architecture domain and DSP domain using

Power Architecture JTAG port

01

10

Yes

No

Access DSP domain using Power Architecture JTAG port

Access Power Architecture domain using Power

Architecture JTAG port

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

120

Freescale Semiconductor

Hardware Design Considerations

JTAG Topology

Table 107. JTAG Topology (continued)

Uses Power

Architecture

{CFG_0_JTAG_MODE,

CFG_1_JTAG_MODE}

Uses DSP

Debug Header

11

Yes

Access Power Architecture domain using Power

Architecture JTAG and DSP domain using DSP JTAG

Note: For boundary SCAN, set {CFG_0_JTAG_MODE, CFG_1_JTAG_MODE} = 10.

The TRST/DSP_TRST signal is optional in the IEEE 1149.1 specification, but is provided on the device. The device requires

TRST/DSP_TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not interfere with normal chip

operation. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, generally

systems assert TRST/DSP_TRST during the power-on reset flow. Simply tying TRST/DSP_TRST to HRESET_B is not

practical because the JTAG interface is also used for accessing the common on-chip processor (COP) function.

The COP function of the processor allow a remote computer system (typically, a PC with dedicated hardware and debugging

software) to access and control the internal operations of the processor. The arrangement shown in Figure 54 and Figure 55

allows the COP/ONCE port to independently assert HRESET_B or TRST, while ensuring that the target can drive HRESET_B

as well.

The COP interface has a standard header for connection to the target system. The 16-pin PA COP connector is shown in

Figure 54.

2

4

1

3

COP_TDO

COP_TDI

NC

COP_TRST_B

COP_VDD_SENSE

COP_CHKSTP_IN_B

NC

5

6

COP_TCK

COP_TMS

COP_SRESET_B

7

8

9

10

12

NC

11

KEY

13

15

COP_HRESET_B

No pin

GND

COP_CHKSTP_OUT_B

16

Figure 54. COP Connector Physical Pinout

The ONCE interface also has a standard header for connection to the target system. The 14-pin DSP ONCE connector is shown

in Figure 55.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

121

Hardware Design Considerations

1

3

2

4

ONCE_TDI

ONCE_TDO

GND

ONCE_TCK

NC

5

7

6

8

ONCE_KEY

ONCE_HRST_B

ONCE_VDD_SNS

9

10

12

ONCE_TMS

NC

11

NC

13

14

ONCE_TRST_B

Figure 55. ONCE Connector Physical Pinout

3.9.1

Termination of Unused Signals

If the Power Architecture JTAG or DSP JTAG interface and COP/ONCE header is not used, Freescale recommends the

following connections:

•

TRST_B should be tied to HRESET_B through a 0 kΩ isolation resistor so that it is asserted when the system reset

signal (HRESET_B) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow.

Freescale recommends that the COP header be designed into the system as shown in Figure 54. If this is not possible,

the isolation resistor allows future access to TRST_B in case a JTAG interface may need to be wired onto the system

in future debug situations.

•

TCK should be pulled down to GND through a 1 kΩ resistor. This prevents TCK from changing state and reading

incorrect data into the device. See AN4405, “BSC9131 QorIQ Qonverge Multicore Baseband Processor Design

Checklist,” for more information.

No connection is required for TDI, TDO, or TMS.

NOTE

In the case where the DSP JTAG is also used (as described in Table 107), DSP_TRST and

DSP_TCK need to be handled in the same way as TRST and TCK are, as mentioned above.

3.10 Thermal

This section describes the thermal specifications.

3.10.1 Thermal Characteristics

Table 108 provides the package thermal characteristics.

Table 108. Package Thermal Resistance Characteristics

Characteristic

JEDEC Board

Symbol

Lid

Unit

Junction-to-Ambient Natural Convection

Junction-to-Ambient (at 200 ft/min)

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

R_θJA

32–33

23–24

24–25

°C/W

R_θJMA

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

122

Freescale Semiconductor

Package Information

Table 108. Package Thermal Resistance Characteristics (continued)

Characteristic

Junction-to-Ambient (at 200 ft/min)

JEDEC Board

Symbol

Lid

Unit

Four layer board (2s2p)

R_θJMA

R_θJB

18–19

12–13

<0.1

°C/W

Junction-to-Board

Junction-to-Case Top

Note:

—

R_θJCtop

1. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets

JEDEC specification for this package.

2. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification

for the specified package.

3. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is

used for the case temperature. Reported value includes the thermal resistance of the interface layer.

3.10.2 Temperature Diode

The chip has a temperature diode on the microprocessor that can be used in conjunction with other system temperature

monitoring devices (such as Analog Devices, ADT7461A™). These devices use the negative temperature coefficient of a diode

operated at a constant current to determine the temperature of the microprocessor and its environment.

The following are the specifications of the chip’s on-board temperature diode:

Operating range: 10 – 230μA

Ideality factor over 13.5 – 220 μA: n = 1.007 ± 0.008

3.11 Security Fuse Processor

This device implements the QorIQ platform’s Trust Architecture, supporting capabilities such as secure boot. Use of the Trust

Architecture features is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the Trust

Architecture and SFP can be found in the BSC9131 QorIQ Qonverge Multicore Baseband Processor Reference Manual.

In order to program SFP fuses, the user is required to supply 1.5 V to the POV

pin per Section 2.2, “Power Sequencing.”

DD1

POV

should only be powered for the duration of the fuse programming cycle, with a per device limit of one fuse

DD1

programming cycle. All other times POV

should be connected to GND. The sequencing requirements for raising and

DD1

lowering POV

are shown in Figure 8. To ensure device reliability, fuse programming must be performed within the

DD1

recommended fuse programming temperature range per Table 3.

Users not implementing the QorIQ platform’s Trust Architecture features are not required to program fuses and should connect

POV

to GND.

DD1

4

Package Information

The following section describes the detailed content and mechanical description of the package.

4.1

Package Parameters

The package parameters are provided in the following list. The package type is plastic ball grid array (FC-PBGA).

Package outline

Interconnects

Die Size

21 mm × 21 mm

520

7.0 mm × 6.9 mm

0.8 mm

Pitch

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

123

Package Information

Module height (typical)

Ball diameter (typical)

1.83 mm

0.4 mm

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

124

Freescale Semiconductor

Package Information

4.2

Mechanical Dimensions of the FC-PBGA

Figure 56 shows the package and bottom surface nomenclature.

Notes:

1. All dimentions are in milimeters.

2. Dimensions and tolerancing per ASME Y14.5-1994.

3. Maximum ball diameter measured parallel to Datum A.

4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

5. Parallelism measurement shall exclude any effect of mark on top surface of package.

Figure 56. BSC9131 Mechanical Dimensions and Package Diagram

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

125

Ordering Information

5

Ordering Information

The table below provides the Freescale part numbering nomenclature for the BSC9131. Note that the individual part numbers

correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. Each

part number also contains a revision code which refers to the die mask revision number.

Table 109. Part numbering nomenclature

n

x

t

e

n

c

d

f

r

Part

Identifier

Qual

Status

Temp

Range

Encryp- Package

tion Type

CPU

Freq

DDR

Speed

DSP

Freq

Die

Revision

Product code

BSC

9131

C =

S, L = Std

E = SEC 1 =

H =

B =

Commercial temp

Present FC-PBGA 800 MHz 800 MHz 800 MHz Rev 1.1

Tier

N =

Industrial

Tier

(0–105°C)

X, J = Ext

temp

(-40–105°C)

Pb-free

K =

1000 MHz

K =

1000 MHz

N = No

SEC

Present

5.1

Part Marking

Parts are marked as the example shown in this figure.

BSC9131C

SE1HHHB

ATWLYYWW

MMMMM

CCCCC

YWWLAZ

FCPBGA

Notes:

ATWLYYWW is the traceability code.

CCCCC is the country code.

MMMMM is the mask number.

YWWLAZ is the assembly traceability code.

BSC9131CSE1HHHB is the orderable part number. See Table 109 for

details.

Figure 57. Part Marking for FCPBGA Device

6

Product Documentation

The following documents are required for a complete description of the device and are needed to design properly with the part.

Some documents may require a non-disclosure agreement. Contact your local FAE for assistance.

•

BSC9131 QorIQ Qonverge Multicore Baseband Processor Reference Manual (BSC9131RM)

e500 PowerPC Core Reference Manual (E500CORERM)

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

126

Freescale Semiconductor

Revision History

7

Revision History

Table 110. Document Revision History

Rev

Date

Substantive Change(s)

0

03/2014

Initial public release.

BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0

Freescale Semiconductor

127

Information in this document is provided solely to enable system and software

implementers to use Freescale products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits based on the

information in this document.

How to Reach Us:

Home Page:

freescale.com

Freescale reserves the right to make changes without further notice to any products

herein. Freescale makes no warranty, representation, or guarantee regarding the

suitability of its products for any particular purpose, nor does Freescale assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. “Typical” parameters that may be provided in Freescale data sheets and/or

specifications can and do vary in different applications, and actual performance may

vary over time. All operating parameters, including “typicals,” must be validated for each

customer application by customer’s technical experts. Freescale does not convey any

license under its patent rights nor the rights of others. Freescale sells products pursuant

to standard terms and conditions of sale, which can be found at the following address:

freescale.com/SalesTermsandConditions.

Web Support:

freescale.com/support

Freescale, the Freescale logo, QorIQ, and StarCore are trademarks of

Freescale Semiconductor, Inc. Reg., U.S. Pat. & Tm. Off. QorIQ Qonverge is

a trademark of Freescale Semiconductor, Inc. All other product or service

names are the property of their respective owners. The Power Architecture

and Power.org word marks and the Power and Power.org logos and related

marks are trademarks and service marks licensed by Power.org.

Document Number: BSC9131

Rev. 0

03/2014


型号：	BSC9131CLN1HHHB
厂家：	NXP
描述：	IC RISC PROCESSOR, Microprocessor
文件：	总128页 (文件大小：1485K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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