BSP304A,126 [NXP]
BSP304A - P-channel vertical D-MOS intermediate level FET TO-92 3-Pin;
| 型号： | BSP304A,126 |
| 厂家： | 
NXP |
| 描述： | BSP304A - P-channel vertical D-MOS intermediate level FET TO-92 3-Pin |
| 文件： | 总9页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
BSP304; BSP304A
P-channel enhancement mode
vertical D-MOS transistors
1995 Apr 07
Product specification
File under Discrete Semiconductors, SC07
Philips Semiconductors
Philips Semiconductors
Productspecification
P-channel enhancement mode
vertical D-MOS transistors
BSP304; BSP304A
FEATURES
DESCRIPTION
• Direct interface to C-MOS, TTL etc.
• High speed switching
P-channel enhancement mode vertical D-MOS transistor
in a TO-92 variant package.
• No secondary breakdown.
APPLICATIONS
d
handbook, halfpage
• Intended for use as a Line current interruptor in
telephone sets and for applications in relay, high speed
and line transformer drivers.
1
2
3
g
PINNING - TO-92 variant
MAM144
s
PIN
SYMBOL
DESCRIPTION
BSP304
1
2
3
g
d
s
gate
Fig.1 Simplified outline and symbol.
drain
source
BSP304A
CAUTION
1
2
3
s
g
d
source
gate
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
drain
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
−300
UNIT
VDS
drain-source voltage (DC)
gate-source voltage (DC)
gate-source threshold voltage
drain current (DC)
−
−
V
V
V
VGSO
VGSth
ID
open drain
±20
ID = −1 mA; VDS = VGS
−1.7
−
−2.55
−170
17
mA
RDSon
drain-source on-state resistance
ID = −170 mA;
VGS = −10 V
−
Ω
Ptot
total power dissipation
up to Tamb = 25 °C
−
1
W
1995 Apr 07
2
Philips Semiconductors
Productspecification
P-channel enhancement mode
vertical D-MOS transistors
BSP304; BSP304A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDS
VGSO
ID
PARAMETER
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
CONDITIONS
MIN.
MAX.
−300
UNIT
−
−
−
−
−
V
V
open drain
±20
−170
−0.75
1
mA
A
IDM
Ptot
Tstg
Tj
peak drain current
total power dissipation
storage temperature
up to Tamb = 25 °C; note 1
W
−65
+150
150
°C
°C
operating junction temperature
−
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
thermal resistance from junction to ambient note 1
CONDITIONS
VALUE
125
UNIT
Rth j-a
K/W
Note to the “Limiting values” and “Thermal characteristics”
1. Device mounted on a printed-circuit board, maximum lead length 4 mm; mounting pad for drain lead minimum 1 cm2.
CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
V(BR)DSS
VGSth
IDSS
PARAMETER
drain-source breakdown voltage
gate-source threshold voltage
drain-source leakage current
gate leakage current
CONDITIONS
VGS = 0; ID = −10 µA
MIN.
−300
−1.7
−
TYP. MAX. UNIT
−
−
V
VDS = VGS; ID = −1 mA
VGS = 0; VDS = −240 V
VGS = ±20 V; VDS = 0
VGS = −10 V; ID = −170 mA
VDS = −25 V; ID = −170 mA
−
−2.55
−100
±100
17
V
−
nA
nA
Ω
IGSS
−
−
RDSon
yfs
drain-source on-state resistance
forward transfer admittance
input capacitance
−
−
100
−
−
mS
pF
pF
pF
Ciss
VGS = 0; VDS = −25 V; f = 1 MHz −
VGS = 0; VDS = −25 V; f = 1 MHz −
VGS = 0; VDS = −20 V; f = 1 MHz −
60
15
5
90
Coss
output capacitance
30
Crss
reverse transfer capacitance
15
Switching times (see Figs 2 and 3)
ton
turn-on time
VGS = 0 to −10 V; VDD = −50 V;
ID = −250 mA
−
−
5
10
30
ns
ns
toff
turn-off time
VGS = −10 to 0 V; VDD = −50 V;
ID = −250 mA
15
1995 Apr 07
3
Philips Semiconductors
Productspecification
P-channel enhancement mode
vertical D-MOS transistors
BSP304; BSP304A
V
= 50 V
handbook, halfpage
INPUT
10 %
handbook, halfpage
DD
90 %
I
D
0
10 %
10 V
OUTPUT
50 Ω
90 %
MBB689
t
t
off
on
MBB690
Fig.2 Switching time test circuit.
Fig.3 Input and output waveforms.
MLC697
MLC699
1
1.2
handbook, halfpage
handbook, halfpage
I
t
=
D
p
(1)
P
tot
(A)
10 µs
(W)
100 µs
1 ms
1
0.8
10
10 ms
100 ms
1 s
t
p
P
2
=
δ
0.4
10
T
DC
t
t
p
T
3
0
0
10
2
3
50
100
150
T
200
( C)
1
10
10
10
o
V
(V)
DS
amb
δ = 0.01.
Tamb = 25 °C.
(1) RDSon limitation.
Fig.4 Power derating curve.
Fig.5 DC SOAR.
1995 Apr 07
4
Philips Semiconductors
Productspecification
P-channel enhancement mode
vertical D-MOS transistors
BSP304; BSP304A
MLC688
MLD139
100
800
handbook, halfpage
handbook, halfpage
C
(pF)
I
D
(mA)
V
=
10 V
GS
80
P = 1 W
600
7 V
6 V
C
60
40
iss
5 V
400
200
4 V
3.5 V
20
0
C
oss
3 V
C
rss
0
0
0
10
20
30
2
4
6
8
10
V
12
(V)
V
(V)
DS
DS
VGS = 0.
Tj = 25 °C.
f = 1 MHz.
Tj = 25 °C.
Fig.6 Capacitance as a function of drain source
voltage; typical values.
Fig.7 Typical output characteristics.
MLC689
MLC691
800
80
handbook, halfpage
handbook, halfpage
R
I
DSon
D
(mA)
(Ω)
600
60
400
200
0
40
20
0
0
0
2
4
6
8
V
10
(V)
2
4
6
8
10
GS
V
(V)
GS
ID = −170 mA.
Tj = 25 °C.
VDS = −25 V.
Tj = 25 °C.
Fig.9 Drain-source on-state resistance as a function
of gate-source voltage; typical values.
Fig.8 Typical transfer characteristics.
1995 Apr 07
5
Philips Semiconductors
Productspecification
P-channel enhancement mode
vertical D-MOS transistors
BSP304; BSP304A
MLC696
MLC692
1.1
60
DSon
handbook, halfpage
handbook, halfpage
R
V
= 3 V
(Ω)
4 V 5 V
GS
50
k
1.0
40
30
20
10
0
6 V
0.9
7 V
10 V
0.8
50
2
3
1
10
10
10
0
50
100
150
I
(mA)
o
D
T
( C)
j
VGSth at Tj
--------------------------------------
VGSth at 25°C
k =
Typical VGSth at ID = −1 mA; VDS =VGS
.
Tj = 25 °C.
Fig.10 Drain-source on-state resistance as a
Fig.11 Temperature coefficient of gate-source
threshold voltage.
function of drain current; typical values.
MLC695
2.5
handbook, halfpage
k
2
1.5
1
0.5
0
50
0
50
100
150
o
T ( C)
j
RDSon at Tj
-----------------------------------------
RDSon at 25 °C
k =
Typical RDSon at ID = −170 mA; VGS = −10 V.
Fig.12 Temperature coefficient of drain-source
on-state resistance.
1995 Apr 07
6
Philips Semiconductors
Productspecification
P-channel enhancement mode
vertical D-MOS transistors
BSP304; BSP304A
MLC698
3
10
R
th j-a
(K/W)
2
10
=
δ
0.75
0.5
0.2
0.1
10
0.05
0.02
0.01
t
p
P
=
δ
T
1
0
t
t
p
T
1
10
5
4
3
2
1
3
2
10
10
10
10
10
1
10
10
10
t
(s)
p
Tamb = 25 °C.
Fig.13 Transient thermal resistance from junction to ambient as a function of pulse time; typical values.
1995 Apr 07
7
Philips Semiconductors
Productspecification
P-channel enhancement mode
vertical D-MOS transistors
BSP304; BSP304A
PACKAGE OUTLINE
0.40
min
4.2 max
1.6
5.2 max
12.7 min
0.48
0.40
1
2
4.8
max
2.54
3
0.66
0.56
(1)
MBC015 - 1
2.5 max
Dimensions in mm.
(1) Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
Fig.14 TO-92 variant.
1995 Apr 07
8
Philips Semiconductors
Productspecification
P-channel enhancement mode
vertical D-MOS transistors
BSP304; BSP304A
DEFINITIONS
Data Sheet Status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1995 Apr 07
9
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