BUK108-50DL,118 [NXP]
BUK108-50DL - PowerMOS transistor Logic level TOPFET D2PAK 3-Pin;型号: | BUK108-50DL,118 |
厂家: | NXP |
描述: | BUK108-50DL - PowerMOS transistor Logic level TOPFET D2PAK 3-Pin 驱动 接口集成电路 |
文件: | 总10页 (文件大小:72K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK108-50DL
DESCRIPTION
QUICK REFERENCE DATA
Monolithic temperature and
overload protected logic level power
MOSFET in a 3 pin plastic surface
mount envelope, intended as a
general purpose switch for
automotive systems and other
applications.
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Continuous drain source voltage
Continuous drain current
50
13.5
40
150
125
V
A
W
˚C
mΩ
PD
Tj
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
RDS(ON)
APPLICATIONS
IISL
Input supply current
VIS = 5 V
650
µA
General controller for driving
lamps
motors
solenoids
heaters
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Vertical power DMOS output
stage
Low on-state resistance
Overload protection against
over temperature
Overload protection against
short circuit load
Latched overload protection
reset by input
DRAIN
O/V
CLAMP
POWER
INPUT
MOSFET
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
RIG
LOGIC AND
derived from input
PROTECTION
Lower operating input current
permits direct drive by
micro-controller
ESD protection on input pin
Overvoltage clamping for turn
off of inductive loads
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
D
S
mb
TOPFET
input
drain
2
I
P
3
source
2
mb drain
1
3
June 1996
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK108-50DL
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VIS
ID
Continuous drain source voltage1
-
-
-
0
-
-
-
-
50
6
13.5
8.5
54
40
150
150
V
V
A
A
A
W
˚C
˚C
Continuous input voltage
Continuous drain current
Continuous drain current
Repetitive peak on-state drain current
Total power dissipation
Tmb ≤25 ˚C; VIS = 5 V
Tmb ≤100 ˚C; VIS = 5 V
Tmb ≤ 25 ˚C; VIS = 5 V
Tmb ≤ 25 ˚C
ID
IDRM
PD
Tstg
Tj
Storage temperature
-
-55
-
Continuous junction temperature2
normal operation
Tsold
Lead temperature
during soldering
-
250
˚C
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload.
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VISP
Protection supply voltage3
for valid protection
4
-
V
Over temperature protection
VDDP(T)
Protected drain source supply voltage VIS = 5 V
-
50
V
Short circuit load protection4
VDDP(P)
PDSM
Protected drain source supply
VIS = 5 V
-
-
24
V
voltage5
Instantaneous overload dissipation
Tmb = 25 ˚C
0.6
kW
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
IDROM
EDSM
Repetitive peak clamping current
Non-repetitive clamping energy
VIS = 0 V
-
-
15
200
A
mJ
T
mb ≤ 25 ˚C; IDM = 15 A;
DD ≤ 20 V; inductive load
mb ≤ 95 ˚C; IDM = 8 A;
DD ≤ 20 V; f = 250 Hz
V
T
V
EDRM
Repetitive clamping energy
-
20
mJ
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VC
Electrostatic discharge capacitor
voltage
Human body model;
C = 250 pF; R = 1.5 kΩ
-
2
kV
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.
3 The input voltage for which the overload protection circuits are functional.
4 For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.
5 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for
PDSM, which is always the case when VDS is less than VDDP(P) maximum.
June 1996
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK108-50DL
THERMAL CHARACTERISTICS
SYMBOL PARAMETER
Thermal resistance
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-mb
Rth j-a
Junction to mounting base
Junction to ambient
-
-
-
2.5
50
3.1
-
K/W
K/W
minimum footprint FR4 PCB
(see fig. 23)
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(CL)DSS
V(CL)DSS
Drain-source clamping voltage VIS = 0 V; ID = 10 mA
50
-
-
-
-
V
V
Drain-source clamping voltage VIS = 0 V; IDM = 1 A; tp ≤ 300 µs;
δ ≤ 0.01
70
IDSS
IDSS
IDSS
RDS(ON)
Zero input voltage drain current VDS = 12 V; VIS = 0 V
Zero input voltage drain current VDS = 50 V; VIS = 0 V
Zero input voltage drain current VDS = 40 V; VIS = 0 V; Tj = 125 ˚C
-
-
-
-
0.5
1
10
85
10
20
100
125
µA
µA
µA
Drain-source on-state
VIS = 5 V; IDM = 7.5 A; tp ≤ 300 µs;
δ ≤ 0.01
mΩ
resistance1
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Short circuit load protection2 Tmb = 25 ˚C; L ≤ 10 µH; RL = 10 mΩ
EDS(TO)
Overload threshold energy
Response time
VDD = 13 V; VIS = 5 V
VDD = 13 V; VIS = 5 V
VDD = 13 V; VIS = 5 V
-
-
-
0.2
0.8
25
-
-
-
J
ms
A
td sc
ID(SC)
Drain current3
IDM(SC)
Peak drain current4
VIS = 5 V; VDD = 13 V
-
60
-
A
Over temperature protection
Tj(TO)
Threshold junction temperature VIS = 5 V; from ID ≥ 0.5 A5
150
-
-
˚C
TRANSFER CHARACTERISTIC
Tmb = 25 ˚C
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
gfs
Forward transconductance
VDS = 10 V; IDM = 7.5 A tp ≤ 300 µs;
δ ≤ 0.01
5
9
-
S
1 Continuous input voltage. The specified pulse width is for the drain current.
2 Refer to OVERLOAD PROTECTION LIMITING VALUES.
3 Continuous drain-source supply voltage. Pulsed input voltage.
4 Continuous input voltage. Momentary short circuit load connection. (The higher peak current is due to the effect of capacitance Cgd).
5 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID
ensures this condition.
June 1996
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK108-50DL
INPUT CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL PARAMETER
VIS(TO) Input threshold voltage
IIS
CONDITIONS
MIN. TYP. MAX. UNIT
VDS = 5 V; ID = 1 mA
normal operation;
1.0
100
-
2.0
1.0
1.5
200
160
2.6
-
2.0
350
270
3.5
-
V
µA
µA
V
Input supply current
VIS = 5 V
VIS = 4 V
Tj = 25 ˚C
Tj = 150 ˚C
VISR
IISL
Protection reset voltage1
Input supply current
protection latched;
II = 10 mA
VIS = 5 V
VIS = 3.5 V
-
-
6
-
330
240
-
33
50
650
430
-
-
-
µA
µA
V
kΩ
kΩ
V(BR)IS
RIG
Input breakdown voltage
Input series resistance
to gate of power MOSFET
Tj = 25 ˚C
Tj = 150 ˚C
-
SWITCHING CHARACTERISTICS
Tmb = 25 ˚C. RI = 50 Ω . Refer to waveform figure and test circuit.
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
td on
tr
td off
tf
Turn-on delay time
Rise time
VDD = 13 V; VIS = 5 V
resistive load RL = 4 Ω
VDD = 13 V; VIS = 0 V
resistive load RL = 4 Ω
-
-
-
-
8
-
-
-
-
µs
µs
µs
µs
40
40
35
Turn-off delay time
Fall time
REVERSE DIODE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
15
UNIT
IS
Continuous forward current
Tmb ≤ 25 ˚C; VIS = 0 V
-
A
REVERSE DIODE CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
VSDO
trr
Forward voltage
IS = 15 A; VIS = 0 V; tp = 300 µs
not applicable2
-
-
1.0
-
1.5
-
V
-
Reverse recovery time
ENVELOPE CHARACTERISTICS
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from upper edge of tab
to centre of die
Measured from source lead
soldering point to source bond pad
-
-
2.5
7.5
-
-
nH
nH
1 The input voltage below which the overload protection circuits will be reset.
2 The reverse diode of this type is not intended for applications requiring fast reverse recovery.
June 1996
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK108-50DL
Normalised Power Derating
Zth / (K/W)
BUK108-50DL
PD%
120
10
1
110
100
90
80
70
60
50
40
30
20
10
0
D =
0.5
0.2
0.1
0.05
0.1
0.02
t
T
p
p
t
P
D =
D
0
t
T
0.01
0
20
40
60
80
Tmb /
100
120
140
1E-07
1E-05
1E-03
t / s
1E-01
1E+01
C
Fig.2. Normalised limiting power dissipation.
PD% = 100 PD/PD(25 ˚C) = f(Tmb)
Fig.5. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
ID / A
BUK108-50DL
120
110
100
90
80
70
60
50
40
30
20
10
0
30
20
10
0
VIS / V =
6
5.5
5
4.5
4
3.5
3
0
20
40
60
80
Tmb /
100
120
140
0
2
4
C
VDS / V
Fig.3. Normalised continuous drain current.
ID% = 100 ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V
Fig.6. Typical on-state characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 2 ms
ID & IDM / A
BUK108-50DL
RDS(ON) / Ohm
VIS / V =
BUK108-50DL
100
10
1
0.20
0.15
0.10
0.05
0
5
5.5
6
4
4.5
3.5
RDS(ON) = VDS/ID
tp =
100 us
1 ms
DC
10 ms
100 ms
Overload protection characteristics not shown
10 100
0.1
1
0
10
20
30
VDS / V
ID / A
Fig.4. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.7. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VIS; tp = 2 ms
June 1996
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK108-50DL
a
BUK108-50DL
Energy & Time
Normalised RDS(ON) = f(Tj)
1
0.5
0
1.5
Time / ms
Energy / J
1.0
0.5
0
Tj(TO)
-60 -40 -20
0
20 40 60 80 100 120 140
Tj /
-60
-20
20
60
100
Tmb / C
140
180
220
C
Fig.8. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 7.5 A; VIS = 5 V
Fig.11. Typical overload protection characteristics.
Conditions: VDD = 13 V; VIS = 5 V; SC load = 30 mΩ
td sc / ms
ID / A
BUK108-50DL
BUK108-50DL
100
10
1
20
15
10
5
typ.
PDSM
0.1
0
0.01
0.1
1
50
60
70
PDS / kW
VDS / V
Fig.9. Typical overload protection characteristics.
Fig.12. Typical clamping characteristics, 25 ˚C.
td sc = f(PDS); conditions: VIS ≥ 4 V; Tj = 25 ˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs
VIS(TO) / V
PDSM%
120
max.
2
100
80
60
40
20
0
typ.
min.
1
0
-60
-40
-20
0
20
40
Tmb / C
60
80
100 120 140
-60 -40 -20
0
20
40
Tj /
60
C
80 100 120 140
Fig.10. Normalised limiting overload dissipation.
PDSM% =100 PDSM/PDSM(25 ˚C) = f(Tmb)
Fig.13. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
June 1996
6
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK108-50DL
VIS / V & VDS / V
VDS
BUK108-50DL
IISL & IIS / uA
600
BUK108-50DL
PROTECTION LATCHED
500
400
300
200
100
0
10
5
IISL
RESET
VIS
IIS
NORMAL
0
0
100
200
time / us
300
400
0
2
4
6
VIS / V
Fig.17. Typical switching waveforms, resistive load.
Fig.14. Typical DC input characteristics, Tj = 25 ˚C.
IISL & IIS = f(VIS); protection latched & normal operation
VDD = 13 V; RL = 4 Ω; RI = 50 Ω, Tj = 25 ˚C.
EDSM%
120
IS / A
BUK108-50DL
60
50
40
30
20
10
0
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80
100
120
140
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Tmb / C
VSD / V
Fig.18. Normalised limiting clamping energy.
EDSM% = f(Tmb); conditions: ID = 15 A; VIS = 5 V
Fig.15. Typical reverse diode current, Tj = 25 ˚C.
IS = f(VSDS); conditions: VIS = 0 V; tp = 250 µs
V(CL)DSS
VDS
VDD
VDD
VDD
+
-
0
L
RL
ID
VDS
0
D
S
D
VIS
TOPFET
TOPFET
-ID/100
D.U.T.
I
0
I
P
P
D.U.T.
R
I
Schottky
R 01
shunt
VIS
RIS
S
ID measure
0V
0R1
Fig.19. Clamping energy test circuit, RIS = 50 Ω.
EDSM = 0.5 LID2 V(CL)DSS/(V(CL)DSS − VDD
Fig.16. Test circuit for resistive load switching times.
)
June 1996
7
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK108-50DL
Idss
Iiso & Iisl normalised to 25 C
1 mA
1.5
100 uA
10 uA
1 uA
typ.
1
100 nA
0.5
0
20
40
60
80
Tj / C
100
120
140
-60
-20
20
60
Tj / C
100
140
180
Fig.20. Typical off-state leakage current.
IDSS = f(Tj); Conditions: VDS = 40 V; IIS = 0 V.
Fig.21. Normalised input currents (normal & latched).
IISO/IISO25˚C & IISL/IISL25˚C = f(Tj); VIS = 5 V
June 1996
8
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK108-50DL
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.4 g
4.5 max
1.4 max
10.3 max
11 max
15.4
2.5
0.85 max
(x2)
0.5
2.54 (x2)
Fig.22. SOT404 : centre pin connected to mounting base.
Notes
1. Epoxy meets UL94 V0 at 1/8".
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.23. SOT404 : minimum pad sizes for surface mounting.
Notes
1. Plastic meets UL94 V0 at 1/8".
June 1996
9
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK108-50DL
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
June 1996
10
Rev 1.000
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