BUK564-200A [NXP]
PowerMOS transistor Logic level FET; 功率MOS晶体管逻辑电平场效应管
| 型号： | BUK564-200A |
| 厂家： | 
NXP |
| 描述： | PowerMOS transistor Logic level FET |
| 文件： | 总7页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK564-200A
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mount applications.
The device is intended for use in
Switched Mode Power Supplies
(SMPS), motor control, welding,
DC/DC and AC/DC converters, and in
automotive and general purpose
switching applications.
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Drain-source voltage
Drain current (DC)
200
9.2
90
175
0.4
V
A
W
˚C
Ω
Ptot
Tj
Total power dissipation
Junction temperature
Drain-source on-state
RDS(ON)
resistance;
VGS = 5 V
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
d
mb
gate
2
drain
g
3
source
2
mb drain
1
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
±VGSM
ID
Drain-source voltage
-
-
200
200
15
V
V
Drain-gate voltage
RGS = 20 kΩ
-
Gate-source voltage
-
-
V
Non-repetitive gate-source voltage tp ≤ 50 µs
-
20
V
Drain current (DC)
Drain current (DC)
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
-
9.2
6.5
36
90
175
175
A
ID
-
A
IDM
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
-
A
Ptot
Tstg
Tj
-
- 55
-
W
˚C
˚C
-
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX.
UNIT
Rth j-mb
Rth j-a
Thermal resistance junction to
-
-
-
1.67
-
K/W
mounting base
Thermal resistance junction to
ambient
minimum footprint,
FR4 board (see Fig. 18).
50
K/W
February 1996
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK564-200A
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
Drain-source breakdown
voltage
VGS = 0 V; ID = 0.25 mA
200
-
-
V
VGS(TO)
Gate threshold voltage
VDS = VGS; ID = 1 mA
1.0
1.5
1
2.0
10
1.0
100
0.4
V
µA
mA
nA
Ω
IDSS
Zero gate voltage drain current VDS = 200 V; VGS = 0 V; Tj = 25 ˚C
Zero gate voltage drain current VDS = 200 V; VGS = 0 V; Tj =125 ˚C
Gate source leakage current
Drain-source on-state
resistance
-
-
-
-
IDSS
0.1
10
IGSS
VGS = ±10 V; VDS = 0 V
VGS = 5 V; ID = 3.5 A
RDS(ON)
0.35
DYNAMIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
gfs
Forward transconductance
VDS = 25 V; ID = 3.5 A
VGS = 0 V; VDS = 25 V; f = 1 MHz
3.5
6.0
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
-
-
-
800
120
65
1000
160
90
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 2.9 A;
VGS = 5 V; RGS = 50 Ω;
Rgen = 50 Ω
-
-
-
-
16
75
120
50
30
110
180
75
ns
ns
ns
ns
Ld
Internal drain inductance
Measured from upper edge of drain
tab to centre of die
Measured from source lead
soldering point to source bond pad
-
2.5
-
nH
Ls
Internal source inductance
-
7.5
-
nH
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IDR
Continuous reverse drain
-
-
-
9.2
A
current
IDRM
VSD
Pulsed reverse drain current
Diode forward voltage
-
-
-
-
36
1.3
A
V
IF = 9.2 A ; VGS = 0 V
1.1
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 9.2 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 100 V
-
-
200
0.6
-
-
ns
µC
AVALANCHE LIMITING VALUE
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 9 A ; VDD ≤ 100 V ;
VGS = 5 V ; RGS = 50 Ω
-
-
50
mJ
February 1996
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK564-200A
Normalised Power Derating
PD%
120
Zth / (K/W)
10
1
110
100
90
80
70
60
50
40
30
20
10
0
D =
0.5
0.2
0.1
0.1
0.05
t
T
p
tp
P
D =
D
0.02
t
0
T
0.01
0
20
40
60
80
Tmb /
100 120 140 160 180
C
1E-07
1E-05
1E-03
t / s
1E-01
1E+01
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
ID / A
120
110
100
90
80
70
60
50
40
30
20
10
0
20
15
10
5
5
10
7
VGS / V =
4
3
0
0
20
40
60
80
100 120 140 160 180
0
2
4
6
8
10 12 14 16 18 20
VDS / V
Tmb /
C
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
ID / A
RDS(ON) / Ohm
4.5
100
10
1
1.0
0.8
0.6
0.4
0.2
0
2.5
3
3.5
4
A
tp = 10 us
RDS(ON) = VDS/ID
VGS / V =
5
100 us
1 ms
DC
10
10 ms
100 ms
0.1
0
2
4
6
8
10 12 14 16 18 20
ID / A
1
10
100
VDS / V
1000
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
February 1996
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK564-200A
VGS(TO) / V
ID / A
20
max.
Tj / C =
25
150
2
1
0
15
10
5
typ.
min.
0
-60
-20
20
60
Tj /
100
140
180
0
2
4
6
8
C
VGS / V
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
SUB-THRESHOLD CONDUCTION
ID / A
gfs / S
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
8
7
6
5
4
3
2
1
0
2 %
98 %
typ
0
0.4
0.8
1.2
VGS / V
1.6
2
2.4
0
2
4
6
8
10 12 14 16 18 20
ID / A
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised RDS(ON) = f(Tj)
a
C / pF
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10000
1000
100
Ciss
Coss
Crss
10
-60
-20
20
60
Tj /
100
140
180
0
20
40
C
VDS / V
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 3.5 A; VGS = 5 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
February 1996
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK564-200A
WDSS%
VGS / V
12
VDS / V =40
120
110
100
90
80
70
60
50
40
30
20
10
0
10
8
160
6
4
2
0
20
40
60
80
100
120
140
160
180
0
10
20
30
40
Tmb /
C
QG / nC
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 9.2 A; parameter VDS
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 9 A
IF / A
20
15
10
5
VDD
+
L
VDS
Tj / C = 150
25
-
VGS
-ID/100
T.U.T.
0
R 01
RGS
shunt
0
0
1
2
VSDS / V
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
)
February 1996
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK564-200A
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.4 g
4.5 max
1.4 max
10.3 max
11 max
15.4
2.5
0.85 max
(x2)
0.5
2.54 (x2)
Fig.17. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.18. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
February 1996
6
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK564-200A
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
February 1996
7
Rev 1.000
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