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BUK7618-30 [NXP]

TrenchMOS transistor Standard level FET; 的TrenchMOS晶体管标准水平FET
BUK7618-30
型号： BUK7618-30
厂家： NXP    NXP
描述：

TrenchMOS transistor Standard level FET
的TrenchMOS晶体管标准水平FET

晶体 晶体管 功率场效应晶体管 开关 脉冲
文件： 总8页 (文件大小：53K)
中文：  中文翻译
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Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Standard level FET  
BUK7618-30  
GENERAL DESCRIPTION  
QUICK REFERENCE DATA  
N-channel enhancement mode  
standard level field-effect power  
transistor in a plastic envelope  
suitable for surface mounting using  
’trench’ technology. The device  
features very low on-state resistance  
and has integral zener diodes giving  
ESD protection up to 2kV. It is  
intended for use in automotive and  
SYMBOL  
PARAMETER  
MAX.  
UNIT  
VDS  
ID  
Ptot  
Tj  
Drain-source voltage  
Drain current (DC)  
Total power dissipation  
Junction temperature  
Drain-source on-state  
30  
55  
103  
175  
18  
V
A
W
˚C  
mΩ  
RDS(ON)  
resistance  
VGS = 10 V  
general  
purpose  
switching  
applications.  
PINNING - SOT404  
PIN CONFIGURATION  
SYMBOL  
PIN  
1
DESCRIPTION  
d
mb  
gate  
2
drain  
source  
g
3
2
mb drain  
s
1
3
LIMITING VALUES  
Limiting values in accordance with the Absolute Maximum System (IEC 134)  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VDS  
VDGR  
±VGS  
ID  
ID  
IDM  
Drain-source voltage  
Drain-gate voltage  
Gate-source voltage  
Drain current (DC)  
-
-
-
-
-
-
-
-
30  
30  
20  
55  
38  
220  
103  
175  
V
V
V
A
A
A
W
˚C  
RGS = 20 kΩ  
-
Tmb = 25 ˚C  
Tmb = 100 ˚C  
Tmb = 25 ˚C  
Tmb = 25 ˚C  
-
Drain current (DC)  
Drain current (pulse peak value)  
Total power dissipation  
Storage & operating temperature  
Ptot  
Tstg, Tj  
- 55  
THERMAL RESISTANCES  
SYMBOL PARAMETER  
CONDITIONS  
TYP.  
MAX.  
UNIT  
Rth j-mb  
Rth j-a  
Thermal resistance junction to  
mounting base  
Thermal resistance junction to  
ambient  
-
-
1.45  
K/W  
minimum footprint, FR4  
board  
50  
-
K/W  
ESD LIMITING VALUE  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VC  
Electrostatic discharge capacitor  
voltage, all pins  
Human body model  
(100 pF, 1.5 kΩ)  
-
2
kV  
December 1997  
1
Rev 1.100  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Standard level FET  
BUK7618-30  
STATIC CHARACTERISTICS  
Tj= 25˚C unless otherwise specified  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
V(BR)DSS  
VGS(TO)  
Drain-source breakdown  
voltage  
Gate threshold voltage  
VGS = 0 V; ID = 0.25 mA;  
30  
27  
2.0  
1.0  
-
-
-
-
-
16  
-
-
-
-
-
-
V
V
V
V
Tj = -55˚C  
VDS = VGS; ID = 1 mA  
3.0  
-
-
0.05  
-
0.02  
-
-
4.0  
-
4.4  
10  
500  
1
20  
-
18  
33.5  
Tj = 175˚C  
Tj = -55˚C  
IDSS  
IGSS  
Zero gate voltage drain current VDS = 30 V; VGS = 0 V;  
Gate source leakage current VGS = ±10 V; VDS = 0 V  
Gate source breakdown voltage IG = ±1 mA;  
Drain-source on-state  
resistance  
µA  
µA  
µA  
µA  
V
mΩ  
mΩ  
Tj = 175˚C  
Tj = 175˚C  
±V(BR)GSS  
RDS(ON)  
VGS = 10 V; ID = 25 A  
15  
-
Tj = 175˚C  
DYNAMIC CHARACTERISTICS  
Tmb = 25˚C unless otherwise specified  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
gfs  
Forward transconductance  
VDS = 25 V; ID = 25 A  
7
15  
-
S
Qg(tot)  
Qgs  
Qgd  
Total gate charge  
Gate-source charge  
Gate-drain (Miller) charge  
ID = 55 A; VDD = 24 V; VGS = 10 V  
-
-
-
29.5  
4.5  
14  
-
-
-
nC  
nC  
nC  
Ciss  
Coss  
Crss  
Input capacitance  
Output capacitance  
Feedback capacitance  
VGS = 0 V; VDS = 25 V; f = 1 MHz  
-
-
-
1000  
390  
180  
-
-
-
pF  
pF  
pF  
td on  
tr  
td off  
tf  
Turn-on delay time  
Turn-on rise time  
Turn-off delay time  
Turn-off fall time  
VDD = 15 V; ID = 25 A;  
VGS = 10 V; RG = 5 Ω  
Resistive load  
-
-
-
-
15  
22  
30  
18  
20  
35  
45  
25  
ns  
ns  
ns  
ns  
Ld  
Ld  
Internal drain inductance  
Internal drain inductance  
Measured from tab to centre of die  
Measured from drain lead solder  
point to centre of die  
-
-
3.5  
4.5  
-
-
nH  
nH  
Ls  
Internal source inductance  
Measured from source lead solder  
point to source bond pad  
-
7.5  
-
nH  
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS  
Tj = 25˚C unless otherwise specified  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
IDR  
Continuous reverse drain  
current  
-
-
55  
A
IDRM  
VSD  
Pulsed reverse drain current  
Diode forward voltage  
-
-
-
-
220  
1.2  
-
A
V
IF = 25 A; VGS = 0 V  
IF = 55 A; VGS = 0 V  
0.95  
1.0  
trr  
Qrr  
Reverse recovery time  
Reverse recovery charge  
IF = 55 A; -dIF/dt = 100 A/µs;  
VGS = -10 V; VR = 25 V  
-
-
70  
0.1  
-
-
ns  
µC  
December 1997  
2
Rev 1.100  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Standard level FET  
BUK7618-30  
AVALANCHE LIMITING VALUE  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
WDSS  
Drain-source non-repetitive  
unclamped inductive turn-off  
energy  
ID = 28 A; VDD ≤ 25 V;  
-
-
80  
mJ  
VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C  
December 1997  
3
Rev 1.100  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Standard level FET  
BUK7618-30  
Normalised Power Derating  
PD%  
Zth / (K/W)  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
1E+01  
1E+00  
1E-01  
1E-02  
1E-03  
0.5  
0.2  
0.1  
0.05  
0.02  
0
p
t
tp  
P
D =  
D
T
t
T
0
20  
40  
60  
80  
Tmb /  
100 120 140 160 180  
C
1E-07  
1E-05  
1E-03  
t / s  
1E-01  
1E+01  
Fig.1. Normalised power dissipation.  
PD% = 100 PD/PD 25 ˚C = f(Tmb)  
Fig.4. Transient thermal impedance.  
Zth j-mb = f(t); parameter D = tp/T  
Normalised Current Derating  
ID%  
ID / A  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
80  
60  
40  
20  
0
12  
10  
8
VGS / V =  
6.5  
6
5.5  
5
4.5  
4
0
20  
40  
60  
80  
100 120 140 160 180  
0
2
4
6
8
10  
Tmb /  
C
VDS / V  
Fig.2. Normalised continuous drain current.  
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V  
Fig.5. Typical output characteristics, Tj = 25 ˚C.  
ID = f(VDS); parameter VGS  
ID / A  
RDS(ON) / mOhm  
1000  
100  
10  
40  
5.5  
6
6.5  
8
30  
20  
10  
0
tp = 10 us  
10  
12  
RDS(ON) = VDS / ID  
100 us  
1 ms  
DC  
VGS / V =  
10 ms  
100 ms  
1
0
20  
40  
60  
80  
100  
1
10  
VDS / V  
100  
ID / A  
Fig.3. Safe operating area. Tmb = 25 ˚C  
ID & IDM = f(VDS); IDM single pulse; parameter tp  
Fig.6. Typical on-state resistance, Tj = 25 ˚C.  
RDS(ON) = f(ID); parameter VGS  
December 1997  
4
Rev 1.100  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Standard level FET  
BUK7618-30  
VGS(TO) / V  
max.  
ID / A  
80  
5
4
3
2
1
0
Tj / C = 25  
175  
60  
40  
20  
0
typ.  
min.  
-100  
-50  
0
50  
Tj / C  
100  
150  
200  
0
2
4
6
8
10  
VGS / V  
Fig.7. Typical transfer characteristics.  
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj  
Fig.10. Gate threshold voltage.  
GS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS  
V
Sub-Threshold Conduction  
gfs / S  
1E-01  
1E-02  
1E-03  
1E-04  
1E-05  
1E-06  
25  
20  
15  
10  
5
Tj / C = 25  
2%  
typ  
98%  
175  
0
0
20  
40  
ID / A  
60  
80  
0
1
2
3
4
5
Fig.8. Typical transconductance, Tj = 25 ˚C.  
gfs = f(ID); conditions: VDS = 25 V  
Fig.11. Sub-threshold drain current.  
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS  
a
C / pF  
10000  
1000  
100  
2
1.5  
1
Ciss  
Coss  
Crss  
0.5  
0
-100  
0
100  
200  
-50  
50  
Tj / C  
150  
0.1  
1
10  
100  
VDS / V  
Fig.9. Normalised drain-source on-state resistance.  
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 10 V  
Fig.12. Typical capacitances, Ciss, Coss, Crss.  
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz  
December 1997  
5
Rev 1.100  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Standard level FET  
BUK7618-30  
WDSS%  
VGS / V  
10  
24  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
8
VDS / V = 6  
6
4
2
0
20  
40  
60  
80  
100  
120  
140  
160  
180  
0
5
10  
15  
QG / nC  
20  
25  
30  
Tmb /  
C
Fig.13. Typical turn-on gate-charge characteristics.  
VGS = f(QG); conditions: ID = 55 A; parameter VDS  
Fig.15. Normalised avalanche energy rating.  
WDSS% = f(Tmb); conditions: ID = 28 A  
IF / A  
80  
60  
40  
20  
0
VDD  
+
L
VDS  
-
Tj / C = 175  
25  
VGS  
-ID/100  
T.U.T.  
0
R 01  
RGS  
shunt  
0
0.5  
1
1.5  
2
VSDS / V  
Fig.16. Avalanche energy test circuit.  
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD  
Fig.14. Typical reverse diode current.  
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj  
)
VDD  
+
-
RD  
VDS  
VGS  
0
RG  
T.U.T.  
Fig.17. Switching test circuit.  
December 1997  
6
Rev 1.100  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Standard level FET  
BUK7618-30  
MECHANICAL DATA  
Dimensions in mm  
Net Mass: 1.4 g  
4.5 max  
1.4 max  
10.3 max  
11 max  
15.4  
2.5  
0.85 max  
(x2)  
0.5  
2.54 (x2)  
Fig.18. SOT404 : centre pin connected to mounting base.  
MOUNTING INSTRUCTIONS  
Dimensions in mm  
11.5  
9.0  
17.5  
2.0  
3.8  
5.08  
Fig.19. SOT404 : soldering pattern for surface mounting.  
Notes  
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent  
damage to MOS gate oxide.  
2. Epoxy meets UL94 V0 at 1/8".  
December 1997  
7
Rev 1.100  
Philips Semiconductors  
Product specification  
TrenchMOS transistor  
Standard level FET  
BUK7618-30  
DEFINITIONS  
Data sheet status  
Objective specification  
This data sheet contains target or goal specifications for product development.  
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.  
Product specification  
This data sheet contains final product specifications.  
Limiting values  
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and  
operation of the device at these or at any other conditions above those given in the Characteristics sections of  
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
Philips Electronics N.V. 1997  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the  
copyright owner.  
The information presented in this document does not form part of any quotation or contract, it is believed to be  
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any  
consequence of its use. Publication thereof does not convey nor imply any license under patent or other  
industrial or intellectual property rights.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices or systems where malfunction of these  
products can be reasonably expected to result in personal injury. Philips customers using or selling these products  
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting  
from such improper use or sale.  
December 1997  
8
Rev 1.100  

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