BUK9614-55 [NXP]
TrenchMOS transistor Logic level FET; 的TrenchMOS晶体管逻辑电平场效应管
| 型号： | BUK9614-55 |
| 厂家： | 
NXP |
| 描述： | TrenchMOS transistor Logic level FET |
| 文件： | 总8页 (文件大小：58K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9614-55
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. Using ’trench’ technology
the device features very low on-state
resistance and has integral zener
diodes giving ESD protection up to
2kV. It is intended for use in
automotive and general purpose
switching applications.
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Ptot
Tj
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
55
68
142
175
14
V
A
W
˚C
mΩ
RDS(ON)
resistance
VGS = 5 V
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
d
mb
gate
2
drain
g
3
source
2
mb drain
s
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
ID
IDM
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
-
-
-
-
-
-
-
-
55
55
10
68
48
240
142
175
V
V
V
A
A
A
W
˚C
RGS = 20 kΩ
-
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
Ptot
Tstg, Tj
- 55
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VC
Electrostatic discharge capacitor
voltage
Human body model
(100 pF, 1.5 kΩ)
-
2
kV
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-mb
Thermal resistance junction to
mounting base
-
-
1.05
K/W
Rth j-a
Thermal resistance junction to
ambient
Minimum footprint, FR4
board
50
-
K/W
April 1998
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9614-55
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA;
55
50
1.0
0.5
-
-
-
-
-
10
-
-
-
-
V
V
V
V
V
µA
uA
µA
µA
V
Tj = -55˚C
VDS = VGS; ID = 1 mA
1.5
-
-
0.05
-
0.02
-
-
2.0
-
2.3
10
500
1
Tj = 175˚C
Tj = -55˚C
IDSS
Zero gate voltage drain current VDS = 55 V; VGS = 0 V;
Tj = 175˚C
Tj = 175˚C
IGSS
Gate source leakage current
VGS = ±5 V; VDS = 0 V
IG = ±1 mA;
10
-
±V(BR)GSS
RDS(ON)
Gate-source breakdown
voltage
Drain-source on-state
resistance
VGS = 5 V; ID = 25 A
-
-
12
-
14
30
mΩ
mΩ
Tj = 175˚C
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
gfs
Forward transconductance
VDS = 25 V; ID = 25 A
30
65
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
2900 3800
pF
pF
pF
500
240
600
330
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 25 A;
VGS = 5 V; RG = 10 Ω
-
-
-
-
35
95
130
60
50
145
180
80
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from upper edge of drain
tab to centre of die
Measured from source lead
soldering point to source bond pad
-
-
2.5
7.5
-
-
nH
nH
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IDR
Continuous reverse drain
current
-
-
68
A
IDRM
VSD
Pulsed reverse drain current
Diode forward voltage
-
-
-
-
240
1.2
-
A
V
V
IF = 25 A; VGS = 0 V
IF = 65 A; VGS = 0 V
0.95
1.0
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 65 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
-
57
0.14
-
-
ns
µC
April 1998
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9614-55
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 65 A; VDD ≤ 25 V;
-
-
200
mJ
VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
Normalised Power Derating
PD%
120
1000
110
100
90
80
70
60
50
40
30
20
10
0
ID / A
tp =
1 us
RDS(ON) = VDS/ID
100
10 us
100 us
1 ms
DC
10
1
10 ms
100 ms
100
1
10
55
0
20
40
60
80
Tmb /
100 120 140 160 180
C
VDS / V
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Current Derating
ID%
Zth / (K/W)
120
110
100
90
80
70
60
50
40
30
20
10
0
1E+01
1E+00
0.5
0.2
0.1
0.05
1E-01
p
t
t
p
P
D
D =
0.02
0
T
1E-02
1E-03
t
T
0
20
40
60
80
100 120 140 160 180
1E-07
1E-05
1E-03
t / s
1E-01
1E+01
Tmb /
C
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
April 1998
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9614-55
100
70
gfs/S
60
10
5
4
VGS/V =
ID/A
3.8
3.6
80
50
40
30
20
10
0
3.4
3.2
60
40
20
0
3.0
2.8
2.6
2.4
2.2
0
2
4
6
8
10
0
20
40
60
80
100
VDS/V
ID/A
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
RDS(ON)/mOhm
Rds(on) normlised to 25degC
20
a
2.5
2
3.6
VGS/V =
4
18
16
14
12
10
4.2
4.4
4.6
1.5
1
5
0.5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
-100
-50
0
50
Tmb / degC
100
150
200
ID/A
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
100
VGS(TO) / V
max.
2.5
2
ID/A
80
60
40
20
0
typ.
1.5
1
min.
0.5
Tj/C = 175
25
0
-100
-50
0
50
Tj / C
100
150
200
0
1
2
3
4
5
VGS/V
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
April 1998
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9614-55
100
IF/A
Sub-Threshold Conduction
1E-01
1E-02
1E-03
1E-04
1E-05
1E-05
80
60
40
20
0
2%
typ
98%
Tj/C = 175
25
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
0.5
1
1.5
2
2.5
3
VSDS/V
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
6
5
4
3
2
1
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
Ciss
ThouandspF
Coss
Crss
20
40
60
80
100
120
140
160
180
0
VDS/V
0.01
0.1
1
10
100
Tmb / C
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 75 A
6
VGS/V
5
VDD
+
L
VDS = 14V
VDS = 44V
4
3
2
1
0
VDS
-
VGS
-ID/100
T.U.T.
0
R 01
RGS
shunt
0
10
20
30
40
50
QG/nC
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 50 A; parameter VDS
)
April 1998
5
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9614-55
VDD
+
-
RD
VDS
VGS
0
RG
T.U.T.
Fig.17. Switching test circuit.
April 1998
6
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9614-55
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.4 g
4.5 max
1.4 max
10.3 max
11 max
15.4
2.5
0.85 max
(x2)
0.5
2.54 (x2)
Fig.18. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.19. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
April 1998
7
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9614-55
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
April 1998
8
Rev 1.000
相关型号：
BUK9614-55-T
TRANSISTOR 68 A, 55 V, 0.014 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power
NXP
BUK9614-55/T3
TRANSISTOR 68 A, 55 V, 0.014 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power
NXP
BUK9616-55A/T3
TRANSISTOR 66 A, 55 V, 0.017 ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, D2PAK-3, FET General Purpose Power
NXP
©2020 ICPDF网 联系我们和版权申明