BUK964R2-80E_技术文档

BUK964R2-80E

AK

D2P

N-channel TrenchMOS logic level FET

Rev. 2 — 16 May 2012

Product data sheet

1. Product profile

1.1 General description

Logic level N-channel MOSFET in a SOT404 package using TrenchMOS technology. This

product has been designed and qualified to AEC Q101 standard for use in high

performance automotive applications.

1.2 Features and benefits

 AEC Q101 compliant

 Suitable for thermally demanding

environments due to 175 °C rating

 Repetitive avalanche rated

 True logic level gate with Vgst(th)

rating of greater than 0.5V at 175 °C

1.3 Applications

 12V, 24V and 48V Automotive

 Transmission control

systems

 Ultra high performance power

 Motors, lamps and solenoid control

 Start-Stop micro-hybrid applications

switching

1.4 Quick reference data

Table 1.

Symbol

V_DS

Quick reference data

Parameter

Conditions

Min

Typ

Max

80

Unit

V

drain-source voltage

drain current

T_j≥ 25 °C; T_j≤ 175 °C

-

[1]

I_D

V_GS= 5 V; T_mb= 25 °C; T_mb= 25 °C;

see Figure 1

120

A

P_tot

total power dissipation T_mb= 25 °C; see Figure 2

-

357

4.2

W

Static characteristics

R_DSondrain-source on-state

resistance

Dynamic characteristics

V_GS= 5 V; I_D= 25 A; T_j= 25 °C;

see Figure 11

3.4

mΩ

Q_GD

gate-drain charge

V_GS= 5 V; I_D= 25 A; V_DS= 64 V;

see Figure 13; see Figure 14

-

37.5

-

nC

[1] Continuous current is limited by package.

BUK964R2-80E

NXP Semiconductors

N-channel TrenchMOS logic level FET

2. Pinning information

Table 2.

Pinning information

Symbol Description

1

Simplified outline

Graphic symbol

G

D

S

D

gate

mb

D

2

drain

source

3

G

mb

mounting base;

connected to drain

mbb076

S

2

1

3

SOT404 (D2PAK)

3. Ordering information

Table 3.

Ordering information

Type number

Package

Name

Description

Version

BUK964R2-80E

D2PAK

plastic single-ended surface-mounted package (D2PAK);

3 leads (one lead cropped)

SOT404

4. Marking

Table 4.

Marking codes

Type number

BUK964R2-80E

Marking code

BUK964R2-80E

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Product data sheet

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NXP Semiconductors

N-channel TrenchMOS logic level FET

5. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DS

Parameter

Conditions

T_j≥ 25 °C; T_j≤ 175 °C

R_GS= 20 kΩ

DC

Min

Max

80

Unit

V

drain-source voltage

drain-gate voltage

gate-source voltage

-

V_DGR

V_GS

-

80

V

-10

-15

-

10

V

Pulsed

15

V

[1]

I_D

drain current

T_mb= 25 °C; T_mb= 25 °C; V_GS= 5 V;

see Figure 1

120

A

T_mb= 100 °C; V_GS= 5 V; see Figure 1

-

120

740

A

I_DM

peak drain current

T_mb= 25 °C; pulsed; t_p≤ 10 µs;

see Figure 4

P_tot

T_stg

T_j

total power dissipation

storage temperature

junction temperature

T_mb= 25 °C; see Figure 2

-

357

175

W

-55

°C

Source-drain diode

[1]

I_S

source current

peak source current

T_mb= 25 °C

-

120

740

A

I_SM

pulsed; t_p≤ 10 µs; T_mb= 25 °C

Avalanche ruggedness

E_DS(AL)Snon-repetitive drain-source

avalanche energy

[2][3]

I_D= 120 A; V_sup≤ 80 V; R_GS= 50 Ω;

V_GS= 5 V; T_j(init)= 25 °C; unclamped;

see Figure 3

-

485

mJ

[1] Continuous current is limited by package.

[2] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.

[3] Refer to application note AN10273 for further information.

BUK964R2-80E

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Product data sheet

Rev. 2 — 16 May 2012

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BUK964R2-80E

NXP Semiconductors

N-channel TrenchMOS logic level FET

003aag356

03aa16

120

240

I_D

P

(%)

(A)

der

180

80

120

(1)

40

60

0

50

100

150

200

0

50

100

150

200

T_mb( C)

°

T

(°C)

mb

Fig 1. Continuous drain current as a function of

mounting base temperature

Fig 2. Normalized total power dissipation as a

function of mounting base temperature

003aag367

10³

I_AL

(A)

10²

10

(1)

(2)

(3)

1

10^-1

10^-3

10^-2

10^-1

1

10

t_AL(ms)

Fig 3. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time

BUK964R2-80E

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Product data sheet

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BUK964R2-80E

NXP Semiconductors

N-channel TrenchMOS logic level FET

003aag357

10³

I_D

(A)

Limit R_DSon= V_DS/ I_D

μ

t_p=10

s

10²

10

1

μ

100

s

DC

1 ms

10 ms

100 ms

10^-1

1

10

10²

10³

V_DS(V)

Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

6. Thermal characteristics

Table 6.

Symbol

R_th(j-mb)

Thermal characteristics

Parameter

Conditions

Min

Typ

Max

Unit

thermal resistance from

junction to mounting base

see Figure 5

-

0.42

K/W

R_th(j-a)

thermal resistance from

junction to ambient

minimum footprint; mounted on

a printed-circuit board

-

50

-

K/W

003aaf570

1

Z_th(j-mb)

(K/W)

= 0.5

0.2

0.1

10^-1

10^-2

10^-3

0.05

0.02

t_p

T

P

t

t_p

single shot

T

10^-6

10^-5

10^-4

10^-3

10^-2

10^-1

1

t_p(s)

Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration.

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Product data sheet

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BUK964R2-80E

NXP Semiconductors

N-channel TrenchMOS logic level FET

7. Characteristics

Table 7.

Symbol

Characteristics

Parameter

Conditions

Min

Typ

Max

Unit

Static characteristics

V_(BR)DSSdrain-source

breakdown voltage

I_D= 250 µA; V_GS= 0 V; T_j= 25 °C

I_D= 250 µA; V_GS= 0 V; T_j= -55 °C

80

72

1.4

-

V

-

V_GS(th)

gate-source threshold I_D= 1 mA; V_DS= V_GS; T_j= 25 °C;

1.7

2.1

voltage

see Figure 9; see Figure 10

I_D= 1 mA; V_DS= V_GS; T_j= -55 °C;

see Figure 9

-

2.45

-

V

I_D= 1 mA; V_DS= V_GS; T_j= 175 °C;

see Figure 9

0.5

I_DSS

drain leakage current

gate leakage current

V_DS= 80 V; V_GS= 0 V; T_j= 25 °C

V_DS= 80 V; V_GS= 0 V; T_j= 175 °C

V_GS= 10 V; V_DS= 0 V; T_j= 25 °C

V_GS= -10 V; V_DS= 0 V; T_j= 25 °C

-

0.08

-

1

µA

nA

mΩ

500

100

4.2

I_GSS

2

R_DSon

drain-source on-state

resistance

V_GS= 5 V; I_D= 25 A; T_j= 25 °C;

see Figure 11

3.4

V_GS= 10 V; I_D= 25 A; T_j= 25 °C;

see Figure 11

-

3.2

-

4

mΩ

V_GS= 5 V; I_D= 25 A; T_j= 175 °C;

10.4

see Figure 12; see Figure 11

Dynamic characteristics

Q_G(tot)

Q_GS

Q_GD

C_iss

total gate charge

I_D= 25 A; V_DS= 64 V; V_GS= 5 V;

see Figure 13; see Figure 14

-

123

-

nC

gate-source charge

gate-drain charge

input capacitance

output capacitance

26.6

37.5

V_GS= 0 V; V_DS= 25 V; f = 1 MHz;

T_j= 25 °C; see Figure 15

12850 17130 pF

C_oss

C_rss

850

420

1020 pF

reverse transfer

capacitance

580

pF

t_d(on)

t_r

t_d(off)

t_f

turn-on delay time

rise time

V_DS= 60 V; R_L= 2.4 Ω; V_GS= 5 V;

R_G(ext)= 5 Ω

-

70

-

ns

nH

109

203

115

2.5

turn-off delay time

fall time

L_D

internal drain

inductance

from upper edge of drain mounting base

to center of die

L_S

internal source

inductance

from source lead to source bonding

pad

-

7.5

-

nH

V

Source-drain diode

V_SD

source-drain voltage

I_S= 25 A; V_GS= 0 V; T_j= 25 °C;

see Figure 16

0.77

1.2

t_rr

reverse recovery time I_S= 20 A; dI_S/dt = -100 A/µs; V_GS= 0 V;

-

61

-

ns

V_DS= 25 V

Q_r

recovered charge

139

nC

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Product data sheet

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NXP Semiconductors

N-channel TrenchMOS logic level FET

003aag358

003aag363

200

10

R_DSon

(mΩ)

V_GS(V) =

10

4.0

3.0

2.9

I_D

(A)

8

6

4

2

0

150

2.8

2.7

2.6

100

50

0

2.5

2.4

0

0.5

1

1.5

2

0

2

4

6

8

10

V_GS(V)

V_DS(V)

T_j= 25 °C; t_p= 300 μs

Fig 6. Output characteristics: drain current as a

function of drain-source voltage; typical values

Fig 7. Drain-source on-state resistance as a function

of gate-source voltage; typical values

003aag359

003aah025

400

3

V_GS(th)

(V)

I_D

(A)

2.5

max

300

200

100

2

typ

1.5

min

1

°

T_j= 175

C

°

T_j= 25

C

0.5

0

-60

0

2

4

6

0

60

120

180

V_GS(V)

T ( C)

°

j

Fig 8. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

Fig 9. Gate-source threshold voltage as a function of

junction temperature

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Product data sheet

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NXP Semiconductors

N-channel TrenchMOS logic level FET

003aah026

003aag364

10^-1

12

R_DSon

(mΩ)

2.6

2.7

2.8

V_GS(V) =

I_D

(A)

10^-2

2.9

9

min

typ

max

10^-3

6

3

0

3.0

4.0

10^-4

10^-5

10^-6

10.0

0

1

2

3

0

50

100

150

200

V_GS(V)

I_D(A)

T_j= 25 °C; t_p= 300 µs

Fig 10. Sub-threshold drain current as a function of

gate-source voltage

Fig 11. Drain-source on-state resistance as a function

of drain current; typical values

003aae090

3

a

V

DS

2.4

I

D

1.8

1.2

0.6

0

V

GS(pl)

V

GS(th)

GS

V

Q

GS1

GS2

Q

GD

GS

Q

G(tot)

-60

0

60

120

180

003aaa508

T ( C)

°

j

Fig 12. Normalized drain-source on-state resistance

factor as a function of junction temperature

Fig 13. Gate charge waveform definitions

BUK964R2-80E

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Product data sheet

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NXP Semiconductors

N-channel TrenchMOS logic level FET

003aag365

003aag361

10

V_GS

10⁵

C

(V)

(pF)

8

C_iss

10⁴

6

14 V

4

2

0

10³

V_DS= 64 V

C_oss

C_rss

10²

10^-1

0

80

160

240

1

10

10²

Q

_G(nC)

V_DS(V)

T_j= 25 °C; I_D= 25 A

V_GS= 0 V; f = 1 MHz

Fig 14. Gate-source voltage as a function of gate

charge; typical values

Fig 15. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

003aag366

200

I_S

(A)

150

100

50

°

T_j= 175

C

°

T_j= 25

0.9

C

0

0.3

0.6

1.2

V_SD(V)

V_GS= 0 V

Fig 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values

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N-channel TrenchMOS logic level FET

8. Package outline

Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)

SOT404

A

E

1

mounting

base

D

1

D

H

D

2

L

p

1

3

c

b

e

Q

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

D

E

A

b

UNIT

c

D

e

L

H

Q

1

p

D

max.

4.50

4.10

1.40

1.27

0.85

0.60

0.64

0.46

1.60

1.20

10.30

9.70

2.90 15.80 2.60

2.10 14.80 2.20

mm

11

2.54

REFERENCES

JEDEC JEITA

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

05-02-11

06-03-16

SOT404

Fig 17. Package outline SOT404 (D2PAK)

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Product data sheet

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N-channel TrenchMOS logic level FET

9. Revision history

Table 8.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

BUK964R2-80E v.2

Modifications:

20120516

Product data sheet

-

BUK964R2-80E v.1

• Status changed from objective to product.

• Various changes to content.

BUK964R2-80E v.1

20120404

Objective data sheet

-

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N-channel TrenchMOS logic level FET

10. Legal information

10.1 Data sheet status

Document status^{[1] [2]}

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term 'short data sheet' is explained in section "Definitions".

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URLhttp://www.nxp.com.

Right to make changes — NXP Semiconductors reserves the right to make

10.2 Definitions

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Preview — The document is a preview version only. The document is still

subject to formal approval, which may result in modifications or additions.

NXP Semiconductors does not give any representations or warranties as to

the accuracy or completeness of information included herein and shall have

no liability for the consequences of use of such information.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

10.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with theTerms and conditions of commercial sale of NXP Semiconductors.

BUK964R2-80E

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Product data sheet

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NXP Semiconductors

N-channel TrenchMOS logic level FET

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published athttp://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

10.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Adelante,Bitport,Bitsound,CoolFlux,CoReUse,DESFire,EZ-HV,FabKey,G

reenChip,HiPerSmart,HITAG,I²C-bus

logo,ICODE,I-CODE,ITEC,Labelution,MIFARE,MIFARE Plus,MIFARE

Ultralight,MoReUse,QLPAK,Silicon

Tuner,SiliconMAX,SmartXA,STARplug,TOPFET,TrenchMOS,TriMedia

andUCODE — are trademarks of NXP B.V.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

HD Radio andHD Radio logo — are trademarks of iBiquity Digital

Corporation.

Export control — This document as well as the item(s) described herein may

be subject to export control regulations. Export might require a prior

authorization from competent authorities.

11. Contact information

For more information, please visit:http://www.nxp.com

For sales office addresses, please send an email to:salesaddresses@nxp.com

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N-channel TrenchMOS logic level FET

12. Contents

1

Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1

1.2

1.3

1.4

General description . . . . . . . . . . . . . . . . . . . . . .1

Features and benefits. . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2

3

4

5

6

7

8

9

Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

Ordering information. . . . . . . . . . . . . . . . . . . . . .2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3

Thermal characteristics . . . . . . . . . . . . . . . . . . .5

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6

Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10

Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11

10

Legal information. . . . . . . . . . . . . . . . . . . . . . . .12

Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13

10.1

10.2

10.3

10.4

11

Contact information. . . . . . . . . . . . . . . . . . . . . .13

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 May 2012

Document identifier: BUK964R2-80E


型号：	BUK964R2-80E
厂家：	NXP
描述：	120A, 80V, 0.0042ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, D2PAK-3/2 局域网开关脉冲晶体管
文件：	总14页 (文件大小：215K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BUK964R2-80E [NXP]

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