C5NPD0-DS/D_技术文档

Data Sheet

C-5 NETWORK PROCESSOR

SILICON REVISION D0

C5NPD0-DS/D

Rev 04

Data Sheet

C-5 Network Processor

Silicon Revision D0

C5NPD0-DS/D

Rev 04

C5NPD0-DS/D

Rev 04

CONTENTS

About This Guide

Data Sheet Description and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Using C-Port Electronic Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Guide Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Related Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CHAPTER 1

Functional Description

Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Channel Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Executive Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Fabric Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table Lookup Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

External Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Queue Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

CHAPTER 2

Signal Descriptions

Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Pin Descriptions Grouped by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

LVTTL and LVPECL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

CP Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

DS1/T1 Framer Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10/100 Ethernet (RMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Gigabit Ethernet (GMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Gigabit Ethernet and Fibre Channel TBI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

SONET OC-3 Transceiver Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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SONET OC-12 Transceiver Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Executive Processor System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

PCI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Serial Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

PROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

General System Interface Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Fabric Processor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

BMU SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

TLU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

QMU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Power Supply Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

No Connection Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Signals Grouped by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

JTAG Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Boundary Scan Cell Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

IDcode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Boundary Scan Description Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

CHAPTER 3

Electrical Specifications

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Power and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Clock Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

CP Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DS1/DS3 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10/100 Ethernet Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications . . . . . . . . . . . . . . . . . . 77

OC-3 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

OC-12 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Executive Processor Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

C5NP

CONTENTS

7

PCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

MDIO Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Low Speed Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

PROM Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Fabric Processor Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

BMU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

TLU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

QMU Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

CHAPTER 4

Mechanical Specifications

Package Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Package Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Marking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Typical Reflow Profile for the C-5 Switch Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

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C5NP

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List of Figures

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C-5 Network Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Pin Locations (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

GMII/TBI Transmit and Receive Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PROM Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

PROM Interface Timing Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power and Ground Connections (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Observe-Only Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Cell Design That Can Be Used for Both Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . 64

Bringup Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Thermal Performance for C-5 Network Processor Heat Sink (see step 2 above). . . . . . . . . . 72

Test Loading Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

System Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

DS1/DS3 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10/100 Ethernet Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Gigabit Ethernet and TBI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

OC-3 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

OC-12 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

PCI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

MDIO Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Low Speed Serial Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

PROM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Fabric Processor Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

BMU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

TLU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

QMU Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

C-5 Network Processor BGA Package Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

C-5 Network Processor BGA Package (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

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List of Tables

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Navigating Within a C-Port Electronic Document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

C-5 Network Processor Data Sheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

C-Port Silicon Documentation Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

TLU SRAM Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Clock and Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

CP Physical Interface Signals and Pins (Grouped by Clusters) . . . . . . . . . . . . . . . . . . . . . . . 31

DS1/T1 Framer Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10/100 Ethernet Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel . . . . . . . . . 33

Gigabit Ethernet (GMII/MII) Signals One Cluster Example. . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Gigabit Ethernet and Fibre Channel TBI Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . 36

OC-3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

OC-12 Signals Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

PCI Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Serial Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

PROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

General System Interface Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Fabric Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Utopia1*, 2, 3 ATM Mode, C-5 Network Processor to Fabric Interface Pin Mapping . . . . . 45

Utopia1*, 2, 3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping . . . . . . 45

PRIZMA Mode, C-5 Network Processor to Fabric Interface Pin Mapping . . . . . . . . . . . . . . . 46

Power X Mode, C-5 Network Processor to Fabric Interface Pin Mapping . . . . . . . . . . . . . . . 47

BMU SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

TLU SRAM Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Memory Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

QMU SRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Power Supply Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines . . . . . . . . . . . . . 53

No Connection Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

Signals Listed by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

JTAG Internal Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

JTAG Identification Code and Its Sub-components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Instruction Register Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

C-5 Network Processor Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

C-5 Network Processor Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . 68

C-5 Network Processor DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

C-5 Network Processor Capacitance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

C-5 Network Processor Power and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 70

System Clock Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

DS1/DS3 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10/100 Ethernet Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Gigabit GMII/MII Ethernet Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Gigabit TBI Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

OC-3 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

OC-12 Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

PCI Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

MDIO Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Low Speed Serial Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

PROM Interface Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Fabric Processor Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

BMU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Signal Groups in BMU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

TLU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Signal Groups in TLU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

QMU Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Signal Groups in QMU Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Package Measurements (Reference Figure 26 and Figure 27 for Symbols) . . . . . . . . . . . . . 95

C-5 Network Processor Marking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

C5NP

C5NPD0-DS/D

Rev 04

ABOUT THIS GUIDE

Data Sheet Description

and Organization

This data sheet describes the C-5 Network processor, Version D0. It provides hardware

layout specifications including pinouts, memory configuration guidelines, timing

diagrams, power and power sequencing guidelines, thermal design guidelines, and

mechanical specifications.

The data sheet is divided into the following topics:

• Functional Description

• Signal Descriptions

• Electrical Specifications

• Mechanical Specifications

Using C-Port Electronic

Documents

C-Port electronic documents are provided as PDF files. Open and view them using the

Adobe® Acrobat® Reader application, verion 3.0 or later. If necessary, download the

Acrobat Reader from the Adobe Systems, Inc. web site:

http://www.adobe.com/prodindex/acrobat/readstep.html

Each provided PDF file offers several ways for moving among the document’s pages,

as follows:

To move quickly from section to section within the document, use the Acrobat bookmarks

that appear on the left side of the Acrobat Reader window. The bookmarks provide an

expandable ‘outline’ view of the document’s contents. To display the document’s Acrobat

bookmarks, press the ‘Display both bookmarks and page’ button on the Acrobat Reader

tool bar.

To move to the referenced page of an entry in the document’s Contents or Index, click on

the entry itself, each of which is “hot linked.”

To follow a cross-reference to a heading, figure, or table, click the blue text.

V 04

14

To move to the beginning or end of the document, to move page by page within the

document, or to navigate among the pages you displayed by clicking on hyperlinks, use

the Acrobat Reader navigation buttons shown in this figure:

Beginning

of document

End of document

Previous or next hyperlink

Table 1 summarizes how to navigate within a C-Port electronic document.

Table 1 Navigating Within a C-Port Electronic Document

TO NAVIGATE THIS WAY

CLICK THIS

Move from section to section within the

document.

A bookmark on the left side of the Acrobat Reader

window

Move to an entry in the document’s Contents The entry itself

or Index.

Follow a cross-reference (highlighted in blue The cross-reference text

text).

Move page by page.

The appropriate Acrobat Reader navigation

buttons

Move to the beginning or end of the

document.

The appropriate Acrobat Reader navigation

buttons

Move backward or forward among a series of The appropriate Acrobat Reader navigation

hyperlinks you have selected. buttons

Guide Conventions

The following visual elements are used throughout this guide, where applicable:

This icon and text designates information of special note.

Warning: This icon and text indicate a potentially dangerous procedure. Instructions

contained in the warnings must be followed.

C5NP

Revision History

15

Warning: This icon and text indicate a procedure where the reader must take

precautions regarding laser light.

This icon and text indicate the possibility of electro-static discharge (ESD) in a procedure

that requires the reader to take the proper ESD precautions.

Revision History

Table 2 shows the revision history for this data sheet, providing a description of the

changes.

Table 2 C-5 Network Processor Data Sheet Revision History

REVISION DATE

March 10, 2000

June 12, 2000

CHANGE

PAGE NO.

First printing for the C-5 NP.

Chapter 2 contains the following revisions:

17

18 - 39

•

LVTTL and LVPECL specifications have been added.

Several of the tables listing pin configurations have had

their descriptions updated. Check each application’s

configuration table as required.

25

31

•

CPn3+1 is RCLKN (5/25/00), not NC (3/10/00)

Mechanism for EPROM signaling has changed.

XPUHOT functionality is clarified

31

36

38

QCPA is a NC (5/25/00), not Address Parity (3/10/00)

The power and ground connections illustration has been

updated.

Chapter 3 contains the following revisions:

•

Many values listed in individual timing diagrams and

specification tables have updated or corrected. Check each

specification table as required.

61 - 78

71

•

Low speed serial interface timing specifications have been

added.

72

PROM I/F timing specifications are changed

June 14, 2000

July 17, 2000

QMU timing specification for Tqdo has been changed from

2.2 to 1.5.

77

12

Updated BMU section to reflect change to external Pipeline

Architecture, Single Data Rate Synchronous DRAM.

V 04

16

Table 2 C-5 Network Processor Data Sheet Revision History

REVISION DATE

CHANGE

PAGE NO.

August 8, 2000

Operating temperatiure range added.

Power sequencing diagram updated.

BMU timing diagram updated.

TLU timing diagram updated.

54

56

75

77

78

QMU timing diagram updated.

March 26, 2001

Chapter 1 contains the following revisions:

Thru-out

• Fabric Processor Interface Frequency changed from 100

MHz to 110 MHz thruoughout.

• TLU interface memory was incorrectly noted at 64 MBytes.

Changed to 32 MBytes.

18

19

The maximum amount of memory supported by the TLU is

32MBytes in four banks.

Chapter 2 contains the following revisions:

• Buffer Management Unit (BMU) has 161 pins

• Added Figure 5. PROM Interface Timing Outline

• Added Figure 7. Observe-Only Cell

21

37

57

• Added Figure 8. Cell Design That Can Be Used for Both

Input and Output Pins

• PROM Interface Timing Outline added.

• Numerous changes in tables 17, 18 and 19

36

39, 40

41

• Data lines incorrectly noted at 128. The useful

configuration is 139 data lines and all 12 address lines.

• The TLU SRAM interface was incorrectly noted at 64

MBytes. Changed to 32 MBytes.

42

Chapter 3 contains the following revisions:

• Table 40, Gigabit Ethernet (TBI) Timing Description, Tcgr

min value of -1.0 removed.

71

73

• Figure 16, OC 12 Clock Duty Cycle was added

• Tc12d added to Table 42

• Figure 17, Executive Processor PCI Timing Diagram PGNTX

74

is only an input. PGNTX Output removed.

• Tpgo, Tpgz, Tpgv removed from Table 43.

Chapter 4 contains the following revisions:

• Mechanical specs changed.

75

C5NP

Related Product

Documentation

The following table lists the C-5 and CST documentation set. Find the latest editions of

these documents for your installed CST version in the Support section of the C-Port

Corporation web site:

V 04

18

Table 3 C-Port Silicon Documentation Set

DOCUMENT

SUBJECT

DOCUMENT NAME

PURPOSE

DOCUMENT ID

Processor

Information

C-5 Network Processor Architecture Guide

Describes the full architecture of the C-5

network processor.

C5NPARCH-RM/D

C5NP

C5NPD0-DS/D

Rev 04

Chapter 1

FUNCTIONAL DESCRIPTION

Feature List

Complete programmability

• Programmability at all levels of the protocol stack: Layers 2-7

• Examples of C-5 enabled systems:

– Multiservice Access Platforms (MSAPs)

– Optical edge switch/routers

– IP Gigabit/Terabit routers

– WAN Customer Premises Equipment (CPE)

– Load balancing web server switches

Simple programming model

• C/C++ programmable

• Standard instruction set

• Standard Applications Programming Interface (C-Ware API^TM)

• Comprehensive C-Ware^TMSoftware Toolset (easy to program, debug, and tune

applications)

Maximum system flexibility

• Software implementation of functions from physical interfaces through switching

fabric support

• Reprogram to support new functionality and ratified standards, improving your

time-in-market^TMmetric

• Deliver new services to market through simple software upgrades — no forklift

Massive processing power

• Operating frequencies: 166MHz, 200MHz, and 233MHz

• 5Gbps of bandwidth (for non-blocking throughput)

V 04

20

CHAPTER 1: FUNCTIONAL DESCRIPTION

• More than 3,000MIPs of computing power (for adding services throughout the

protocol stack)

• Up to 15 million packets per second transmitted at wire speed

• 17 programmable RISC Cores (for cell/packet forwarding)

• 32 programmable Serial Data Processors (for processing bit streams)

• Up to 133 million table lookups per second

• Three internal buses for 60Gb of aggregate bandwidth

High functional integration

• 838 pin Ball Grid Array (BGA) package

• 16 Channel Processors including:

– Embedded OC-3c, OC-12, OC-12c SONET framers

– Programmable MAC interface

– RISC Cores

– Programmable pin PHY interfaces

• Embedded coprocessors for table lookup (classification), buffer memory (payload

control), and queue management (CoS/QoS implementation)

• Dedicated Fabric Processor and port

• Embedded RISC Executive Processor

• Integrated 32bit/66MHz PCI bus

Stable programming interfaces

• Supports generic communications programming interfaces to simplify programming

and allow future reuse of code across generations of the processor

• Network Processing Forum (NPF), (formerly CPIX), Charter member

Third-party support

• Support for virtually any third-party protocol stack, PHY or fabric interface, and

industry standard tools

• Smart Networks Alliance Program ensures a wide range of verified solutions

C5NP

Block Diagram

21

Block Diagram

The C-5^TMnetwork processor, has an architecture specifically designed for networking

applications. Figure 1 shows a block diagram of the C-5 NP, including its potential external

interfaces. The following sections describe each component of the C-5 NP.

For more information about the architecture of the C-5 NP, see the C-5 Network Processor

Architecture Guide.

Figure 1 C-5 Network Processor Block Diagram

External

Host CPU

(optional)

External

PROM

(optional)

SRAM

SDRAM

Fabric

Control

Logic

(optional)

Table

Lookup

Unit

PCI

Serial

PROM

Fabric

Processor

Executive Processor

Queue

Mgmt

Unit

Buffer

Mgmt

Unit

Buses (60Gbps Bandwidth)

Channel

CP-0 CP-1 CP-2 CP-3

PHY PHY PHY PHY

CP-12 CP-13 CP-14 CP-15

Cluster

Processors

C-5

NP

Cluster

Processor Boundary

PHY

PHY Interface Examples:

10/100 Ethernet Gigabit Ethernet

OC-3 OC-12

The main components of the C-5 NP are:

• Channel Processors

• Executive Processor

• Fabric Processor

• Buffer Management Unit

• Table Lookup Unit

• Queue Management Unit

V 04

22

CHAPTER 1: FUNCTIONAL DESCRIPTION

Channel Processors

The C-5 NP contains sixteen programmable Channel Processors (CPs) that receive,

process, and transmit network data. The number of CPs per port is configurable,

depending on the line interface. Typically one CP is assigned to each port for medium

bandwidth applications (Fast Ethernet to OC-3). Multiple CPs can be assigned to a port in

a configuration called channel aggregation in high bandwidth applications (greater than

OC-3). Multiple logical ports can be assigned to a single CP, with the addition of an

external multiplexor, for low bandwidth applications, such as DS1 to DS3.

The C-5 NP’s architecture supports a variety of industry-standard serial and parallel

protocols and individual port data rates including:

• 10Mb Ethernet (RMII)

• 100Mb Ethernet (RMII)

• 1Gb Ethernet (GMII and TBI)

• OC-3

• OC-12

• DS1/DS3, supported through the use of external framers/multiplexors

The C-5 NP’s programmability can also support a variety of special interfaces, such as

various xDSL encapsulations and proprietary protocols.

Key components of each CP are a RISC Core (CPRC) that orchestrates cell/packet

processing and a set of microprogrammable, special-purpose processors, called Serial

Data Processors (SDPs), that provide features such as Ethernet MAC and SONET framing,

multichannel HDLC, and ATM cell delineation. This means you usually only need to

include PHYs to complete the system.

Executive Processor

The Executive Processor (XP) serves as a centralized computing resource for the C-5 NP

and manages the system interfaces.

The XP performs conventional supervisory tasks in the C-5 NP, including:

• Reset and initialization of the C-5 NP

• Program loading and control of CPs

• Centralized exception handling

C5NP

Fabric Processor

23

• Management of a host interface through the PCI

• Management of system interfaces (PCI, Serial Bus, PROM)

System Interfaces The system interfaces to the XP are:

• PCI — Provides an industry standard 32bit 33/66MHz PCI channel used for chip-level

shared resources. The PCI has both initiator and target capabilities. The PCI interface is

typically connected to a host processor.

• Serial Bus Interface — Provides a general purpose bi-directional, two-wire serial bus

and I/O port that allows the C-5 NP to control external logic with either of two

standard protocols:

– The MDIO (high-speed) protocol: uses a 16bit data format with 10bits of

addressing and supports transfers up to 25MHz.

– The low-speed protocol: uses an 8bit data format followed by an acknowledge bit

and supports transfers up to 400kbps.

Software is used to select which protocol to use, by setting the appropriate bits in the

Serial Bus Configuration Register. When a serial bus transfer is active, an external pin is

driven by the C-5 NP to indicate which protocol is being used (SPLD=0 indicates MDIO

protocol; SPLD=1 indicates low-speed protocol).

Both SIDA and SICL are bi-directional lines that are connected, via an external pull-up

resistor, to a positive supply voltage. When the bus is free, both lines are HIGH because

of the pull-up resistor. The output stages of the devices connected to the bus must

have either an open-drain or open-collector in order to perform the wired-AND

function required for its arbitration mechanism.

• PROM Interface — Allows the XP to boot from nonvolatile, flash memory. The PROM

interface is a low-speed, serial I/O port that runs at ¹/₂to ¹/₁₆the core clock rate. The

maximum PROM size is 8MBytes, and a 16bit wide configuration is required. External

board logic is required to perform serial-to-parallel conversion for PROM address

outputs and parallel-to-serial conversion for PROM data inputs.

Fabric Processor

The Fabric Processor (FP) acts as a high-speed network interface port with advanced

functionality. It allows the C-5 NP to interface to an application-specific switching solution

internal to your design. The FP port supports the bidirectional transfer of packets, frames,

V 04

24

CHAPTER 1: FUNCTIONAL DESCRIPTION

or cells from the C-5 NP to a hardware interface that provides connectivity to other

network processors or other similar line processing hardware. There are numerous

parameters that can be configured within the FP to allow the interface to be adapted to

different fabric protocols. The FP is Utopia-1, 2 and Utopia-3, IBM PRIZMA, and PowerX

(Csix-L0) compatible.

The FP can be configured to run at any frequency up to 110MHz, and the receive and

transmit data buses are 16 or 32 bits wide. This allows a wide range of supported

bandwidths to and from the switching fabric, all the way up to 3200Mbps full duplex

bandwidth.

Buffer Management Unit

The Buffer Management Unit (BMU) interfaces the C-5 NP to external pipeline

architecture, Single Data Rate Synchronous DRAM. The external memory is partitioned

and used as buffers for receiving and transmitting data between CPs, the FP, and the XP. It

is also used as second level storage in the XP memory hierarchy.

The interface to an array of SDRAM chips is 139bits wide, composed of 128 data bits, two

internal control bits, and nine SECDED (single error correction-double error detection) ECC

(error correction code) bits. The interface is compliant with the PC100 standard and

operates at up to 125MHz with 3.3V LVTTL-compatible inputs and outputs. The refresh

period, Trcd, Tcas, Trp, Tmrd, and Trc are configurable via boot time configuration (see the

C-5 Network Processor Architecture Guide for more details).

The C-5 NP uses auto-refresh mode and the interface, (which is not configurable),

transfers four bits of data for each read and write using a sequential burst type.

Some of these parameters are programmed into the SDRAMs’ mode register and can be

applied only once per power cycle. The ECC functionality can be enabled or disabled via

configuration register writes.

If needed, the interface can narrowed to 128bits by disabling ECC and providing board

pull-ups for the two control bits and nine ECC bits. This is useful if DIMMs are used in the

board design. If individual SDRAM parts are used, x16 and x32 are supported. The BMU

supports SDRAM devices that use 12 address lines. Internal address calculation paths limit

the maximum memory size to 128MBytes. Only one physical bank of SDRAM is supported.

Table Lookup Unit

The Table Lookup Unit (TLU) performs table lookups in external SRAM. It can also be used

for statistics accumulation and retrieval and as general data storage. The TLU

C5NP

External Mode

25

simultaneously supports multiple application-defined tables and multiple search

strategies, such as those needed for routing, circuit switching, and QoS lookup tasks.

The C-5 NP uses external 64bit wide ZBT Pipelined Bursting Static RAM (SRAM) modules

(at frequencies to 133MHz) for storage of its tables. These modules allow implementation

of tables with 2²⁰x 64bit entries at a cycle time of up to 7.5 nanoseconds using 4Mbit

SRAM technology. The maximum amount of memory supported by the TLU is 32MBytes

in four banks.

Table 4 TLU SRAM Configurations

MIN TABLE SIZE

(ONE BANK)

NO. OF

PARTS

MAXIMUM TABLE SIZE

(FOUR BANKS)

NO. OF

PARTS

SRAM TECHNOLOGY*

1Mbit (32k x 32)

2Mbit (64k x 32)

4Mbit (256k x 18)

8Mbit (512k x 18

16Mbit (1M x 18)

256kBytes

512kBytes

2MBytes

4MBytes

8MBytes

2

4

1MBytes

2MBytes

8MBytes

16MBytes

32MBytes

8

16

*

For (n x 32) parts, divide total memory and number of parts by two.

External Mode

There is support for external devices. Refer to the C-5 Archictecture Guide.

Queue Management Unit

The Queue Management Unit (QMU) autonomously manages a number of

application-defined descriptor queues. It handles inter-CP and inter-C-5 NP descriptor

flows by providing switching and buffering. It also performs descriptor replication for

multicast applications. A number of queues can be assigned to each CPRC for QoS-based

services.

The QMU provides a queuing engine internal to the chip and uses external SRAM to store

the descriptors. Scheduling is done by the CPs. The QMU supports up to 512 queues and

16, 384 descriptor buffers. A descriptor buffer holds an application-defined “descriptor”,

which is a structure that defines the payload buffer handle and other attributes of the

forwarded cell or packet.

The QMU’s external SRAM interface uses ZBT synchronous SRAMs organized in a single

bank of up to 128k, 32bit words. This interface runs at half (¹/₂) the core clock frequency.

V 04

26

CHAPTER 1: FUNCTIONAL DESCRIPTION

C5NP

C5NPD0-DS/D

Rev 04

Chapter 2

SIGNAL DESCRIPTIONS

Signal Summary

There are ten functional groupings of signals in the C-5 network processor:

• Clock — 11 pins

• Channel Processors (CP0 - CP15) — 16x7 = 112 pins

• Executive Processor (XP) — 57 pins

– PCI Interface — 50 pins

– PROM Interface — 4 pins

– Serial Bus Interface — 2 pins

– General System Interface — 1 pin

• Fabric Processor (FP) — 80 pins

• Buffer Management Unit (BMU) — 161 pins

• Table Lookup Unit (TLU) — 100 pins

• Queue Management Unit (QMU) — 55 pins

• Power — 233 pins

• Test — 18 pins

• No connection (NC) — 11 pins

Two of the sections (CPs and FP) are configurable, depending on the type of device being

implemented.

Pinout Diagram

The C-5 NP contains 838 pins as shown in Figure 2. These pin numbers are referenced

throughout the remaining chapter.

V 04

28

CHAPTER 2: SIGNAL DESCRIPTIONS

Figure 2 Pin Locations (Bottom View)

C-5 Network Processor

838 Total Pins

AC

AB

AA

Z

Y

X

W

V

U

T

S

R

Q

P

O

N

M

L

K

J

I

H

G

F

E

D

C

B

A

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Pin Descriptions Grouped

by Function

The C-5 NP pins are categorized in groups, reflecting interfaces to the chip:

• Clock Signals

• CP Interface Signals

• Executive Processor System Interface Signals

C5NP

Pin Descriptions Grouped by Function

29

• Fabric Processor Interface Signals

• BMU SDRAM Interface Signals

• TLU SRAM Interface Signals

• QMU SRAM Interface Signals

• Power Supply Signals

• Test Signals

• No Connection Pins

LVTTL and LVPECL C-5 NP pins are the following types:

Specifications

• Low Voltage TTL-Compatible (LVTTL). The C-5 NP’s LVTTL pins conform to the JEDEC

JESD8-B specification.

• Low Voltage Positive Emitter Coupled Logic (LVPECL). The C-5 NP’s LVPECL pins

conform to the JEDEC JESD8-2 specification.

Clock Signals Table 5 describes the C-5 NP clock signals.

Table 5 Clock and Reference Signals

SIGNAL NAME

PIN #

TOTAL

TYPE

I/O

SIGNAL DESCRIPTION

SCLK*

SCLKX*

H15

G15

1

LVPECL

I

Core Clock Rate (Differential)

CCLK0

CCLK1

CCLK2

CCLK3

CCLK4

CCLK5

CCLK6

CCLK7

K12

J13

J15

I12

1

LVTTL

I

1_544MHZ_CLK (T1)†

2_048MHZ_CLK (E1)†

34_368MHZ_CLK (E3)†

44_736MHZ_CLK (T3)†

50MHZ_CLK (100Mbit Ethernet)†

I14

H13

K14

K16

106_25MHZ_CLK (Fibre Channel)†

125MHZ_CLK (Gigabit Ethernet)†

155_52MHZ_CLK (OC-3)†

V 04

30

CHAPTER 2: SIGNAL DESCRIPTIONS

Table 5 Clock and Reference Signals (continued)

SIGNAL NAME

PIN #

TOTAL

TYPE

I/O

SIGNAL DESCRIPTION

CPREF‡

L13

1

LVPECL

I

Reference

TOTAL

11

*

SCLK and SCLKX must not be AC-coupled.

†

The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5 NP. Clock inputs associated with a

specific protocol should be wired to ground when that protocol is not used by the C-5 NP. It is also possible

to use one or more CCLKn inputs for other frequencies. Contact your C-Port representative for more

information.

If any of the CPs are configured for LVPECL operation (OC3) using the pin mode registers, then CPREF must

be wired to an external reference, as specified in Table 36 on page 68. If none of the CPs are configured for

LVPECL operation, then the CPREF pin can be left unconnected. It is acceptable to tie the CPREF pin high or

low through a resistor, or into the specified reference, but this is not required.

‡

CP Interface Signals The C-5 NP’s 16 CPs support various network physical interfaces, providing a serial

interface to the PHY layer. Interfaces are configured via bits in the C-5 NP register set.

Many interfaces are possible by programming the configuration registers. CPs can be

used individually or in a cluster (four CPs) to implement the various interfaces.

Table 6 provides a quick reference of all the CP pins organized by clusters. There are seven

physical I/O pins associated with each CP. All pins are capable of receiving data, with some

configurable to be input clocks, output clocks, or data drivers. In addition, pairs of pins can

be configured as differential pairs for LVPECL compatibility.

In the case of RMII, OC-3, DS1, and DS3, the drivers and receivers at the pin are locally

configured to match the relevant PHY or Framer chip. OC-12 uses the aggregation of four

CPs (one cluster), while GMII and Ten Bit Interface (TBI) can use either eight CPs (four for

receive and four for transmit) or four CPs that share the transmit and receive functions for

non-wire speed applications.

During CP aggregation, all 28 pins associated with a cluster are routed to all of the Serial

Data Processors (SDPs) in that cluster. This allows round-robin usage of portions of the

SDPs, with each getting access to the necessary I/O pins.

The signals for the following CP physical interfaces are included in this section:

• DS1/T1 Framer Interface Configuration

• 10/100 Ethernet (RMII) Configuration

• Gigabit Ethernet (GMII) Configuration

C5NP

Pin Descriptions Grouped by Function

31

• Gigabit Ethernet and Fibre Channel TBI Configuration

• SONET OC-3 Transceiver Interface Configuration

• SONET OC-12 Transceiver Interface Configuration

Table 6 CP Physical Interface Signals and Pins (Grouped by Clusters)

CP CLUSTER 1

SIGNAL

CP CLUSTER 2

SIGNAL

CP CLUSTER 3

SIGNAL

CP CLUSTER 4

SIGNAL

PIN #

AC28

AC26

AC24

AC22

AC20

AC18

AC16

AC02

AC04

AC06

AC08

AC10

AC12

AC14

AB29

AB28

AB27

AB26

AB25

AB24

AB23

AB01

AB02

PIN #

AB22

AB21

AB20

AB19

AB18

AB17

AB16

AB08

AB09

AB10

AB11

AB12

AB13

AB14

AA28

AA26

AA24

AA22

AA20

AA18

AA16

AA02

AA04

PIN #

Z29

Z28

Z27

Z26

Z25

Z24

Z23

Z01

Z02

Z03

Z04

Z05

Z06

Z07

Z22

Z21

Z20

Z19

Z18

Z17

Z16

Z08

Z09

PIN #

Y28

Y26

Y24

Y22

Y20

Y18

Y16

Y02

Y04

Y06

Y08

Y10

Y12

Y14

X29

X28

X27

X26

X25

X24

X23

X01

X02

CP0_0

CP0_1

CP0_2

CP0_3

CP0_4

CP0_5

CP0_6

CP1_0

CP1_1

CP1_2

CP1_3

CP1_4

CP1_5

CP1_6

CP2_0

CP2_1

CP2_2

CP2_3

CP2_4

CP2_5

CP2_6

CP3_0

CP3_1

CP4_0

CP4_1

CP4_2

CP4_3

CP4_4

CP4_5

CP4_6

CP5_0

CP5_1

CP5_2

CP5_3

CP5_4

CP5_5

CP5_6

CP6_0

CP6_1

CP6_2

CP6_3

CP6_4

CP6_5

CP6_6

CP7_0

CP7_1

CP8_0

CP8_1

CP8_2

CP8_3

CP8_4

CP8_5

CP8_6

CP9_0

CP9_1

CP9_2

CP9_3

CP9_4

CP9_5

CP9_6

CP10_0

CP10_1

CP10_2

CP10_3

CP10_4

CP10_5

CP10_6

CP11_0

CP11_1

CP12_0

CP12_1

CP12_2

CP12_3

CP12_4

CP12_5

CP12_6

CP13_0

CP13_1

CP13_2

CP13_3

CP13_4

CP13_5

CP13_6

CP14_0

CP14_1

CP14_2

CP14_3

CP14_4

CP14_5

CP14_6

CP15_0

CP15_1

V 04

32

CHAPTER 2: SIGNAL DESCRIPTIONS

Table 6 CP Physical Interface Signals and Pins (Grouped by Clusters) (continued)

CP CLUSTER 1 CP CLUSTER 2 CP CLUSTER 3 CP CLUSTER 4

SIGNAL

PIN #

AB03

AB04

AB05

AB06

AB07

SIGNAL

PIN #

AA06

AA08

AA10

AA12

AA14

SIGNAL

PIN #

Z10

Z11

Z12

Z13

Z14

SIGNAL

PIN #

X03

X04

X05

X06

X07

CP3_2

CP3_3

CP3_4

CP3_5

CP3_6

CP7_2

CP7_3

CP7_4

CP7_5

CP7_6

CP11_2

CP11_3

CP11_4

CP11_5

CP11_6

CP15_2

CP15_3

CP15_4

CP15_5

CP15_6

DS1/T1 Framer Interface Configuration

Table 7 describes the serial framer interface signals. For each CP (0-15), you can

implement one serial Framer interface.

Table 7 DS1/T1 Framer Interface Signals

SIGNAL NAME*

CPn_0

PIN #†

TOTAL TYPE

I/O

O

I

LABEL

TCLK

SIGNAL DESCRIPTION

Transmit Clock (1.544MHz)

Receive Clock (1.544MHz)

Transmit Data

Table 6

1

7

LVTTL

nc

CPn_1

RCLK

CPn_2

O

I

TData

TFrame

RData

RFrame

nc

CPn_3

Transmit Frame Synchronization

Receive Data

CPn_4

CPn_5

I

Receive Frame Synchronization

nc

CPn_6

nc

TOTAL PINS

*

n can be from 0 to 15. See Table 6.

Reference Table 6 for pin numbers for the actual cluster(s) you are configuring.

†

10/100 Ethernet (RMII) Configuration

Table 8 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface

(RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface.

C5NP

Pin Descriptions Grouped by Function

33

Table 8 10/100 Ethernet Signals

SIGNAL NAME*

CPn_0

PIN #

TOTAL TYPE

I/O

O

I

LABEL

SIGNAL DESCRIPTION

Transmit and Receive Clock (50MHz)

Table 6

1

LVTTL

REF_CLK

CRS_DV

CPn_1

Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that

traffic is on the link, and is asserted if the signal is a 1 or an

alternating 1010... RX_DV indicates that a receive frame is in

progress and the data present on the RXD pins is valid. It is

asserted if this signal is a 1 for more than one cycle.

CPn_2

CPn_3

CPn_4

CPn_5

CPn_6

Table 6

1

LVTTL

O

I

TXD(0)

TXD(1)

RXD(0)

RXD(1)

TX_EN

Transmit Data 0 (first on wire)

Transmit Data 1 (second on wire)

Receive Data 0 (first on wire)

Receive Data 1 (second on wire)

I

O

Transmit Enable. When asserted, the data on TXD is encoded and

transmitted on the twisted pair cable.

7

TOTAL PINS

*

n can be from 0 to 15. See Table 6.

Gigabit Ethernet (GMII) Configuration

Gigabit Ethernet Media Independent Interface (GMII) is configured in one of two ways:

1 Use one CP cluster when density is more important than wire-speed performance

because you can then implement up to four Gigabit Ethernet ports per C-5 NP.

2 Use two CP clusters for wire-speed performance and additional processing power. You

can implement up to two Gigabit Ethernet ports per C-5 NP.

Table 9 lists the possible CP cluster combinations you can use and Figure 3 shows receive

and transmit pin configurations by cluster. Table 10 lists the signals and pinouts for

Gigabit Ethernet (GMII).

Table 9 Transmit and Receive Pin Combinations for Gigabit Ethernet and Fibre Channel

CLUSTER

SINGLE CLUSTER MODE (TBI OR GMII)

Port 1 Tx and Rx

TWO CLUSTER MODE (GMII)*

Port 1 Tx

0

1

2

3

Port 2 Tx and Rx

Port 1 Rx

Port 3 Tx and Rx

Port 2 Tx

Port 4 Tx and Rx

Port 2 Rx

*

The Two Cluster Mode column lists typical configurations. Any cluster can be set up to either receive

or transmit. So you could configure a dual cluster mode where cluster 0 receives and cluster 3

transmits.

V 04

34

CHAPTER 2: SIGNAL DESCRIPTIONS

Figure 3 GMII/TBI Transmit and Receive Pin Configurations

Single Cluster Mode

Pin Configuration

Two Cluster Mode

Pin Configuration

Tx

Rx

Cluster

0

Cluster

0

}

Port 1

Port 2

Port 3

Port 4

Rx

nc

Port 1

Port 2

Tx

nc

Tx

Rx

}

Cluster

1

Cluster

1

Rx

Tx

Rx

Cluster

2

Cluster

2

Rx

nc

Tx

nc

Tx

Rx

Cluster

3

Cluster

3

Rx

nc = not connected

The unused CP pins in the two cluster configurations should be wired to ground using a

resistor.

Table 10 Gigabit Ethernet (GMII/MII) Signals One Cluster Example

SIGNAL NAME*

PIN #† TOTAL TYPE

I/O

LABEL

SIGNAL DESCRIPTION

CPn_0

Table 6 1

LVTTL

O

T_CLK

GMII Transmit Clock (125MHz). This clock is used to synchronize the

transmit data.

CPn_1

Table 6 1

LVTTL

I

TCLKI

MII transmit clock. Transmit data aligned to this clock input from

phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT

CPn_2

CPn_3

CPn_4

CPn_5

CPn_6

Table 6 1

LVTTL

O

TXD(0)

TXD(1)

TXD(2)

TXD(3)

TX_EN

Transmit Data (byte-wide data, least significant bit)

Transmit Data

Transmit Enable. When asserted, the data on TXD is encoded and

transmitted on the twisted pair cable.

CPn+1_0

CPn+1_1

Table 6 1

nc

I

nc

LVTTL

COL

Collision. Asserted when both RX_DV and TX_EN are valid during

half duplex operation.

CPn+1_2

CPn+1_3

Table 6 1

LVTTL

O

TXD(4)

TXD(5)

Transmit Data

C5NP

Pin Descriptions Grouped by Function

35

Table 10 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued)

SIGNAL NAME*

CPn+1_4

PIN #† TOTAL TYPE

I/O

O

LABEL

TXD(6)

TXD(7)

TX_ER

SIGNAL DESCRIPTION

Table 6 1

LVTTL

Transmit Data

CPn+1_5

O

Transmit Data (byte-wide receive data, most significant bit)

CPn+1_6

O

Transmit Error. Asserting TX_ER when TX_EN is a 1 causes

transmission of the designated “bad code” in lieu of the normal

encoded data on the twisted pair data.

CPn+2_0

CPn+2_1

CPn+2_2

CPn+2_3

CPn+2_4

CPn+2_5

CPn+2_6

Table 6 1

nc

LVTTL

I

RCLK

Receive Clock (125MHz)

RXD(0)

RXD(1)

RXD(2)

RXD(3)

RX_DV

Receive Data (byte-wide receive data, least significant bit)

Receive Data

Receive Data Valid. Indicates that there is a receive frame in progress

and that the data present on the RXD signals is valid.

CPn+3_0

CPn+3_1

Table 6 1

nc

I

nc

LVTTL

CRS

Carrier Sense. Indicates traffic is on the link. CRS is asserted when a

non-idle condition is detected on the receive data stream. CRS is

deasserted when an end of frame or idle condition is detected.

CPn+3_2

CPn+3_3

CPn+3_4

CPn+3_5

CPn+3_6

Table 6 1

LVTTL

I

RXD(4)

RXD(5)

RXD(6)

RXD(7)

RX_ER

Receive Data

Receive Data (most significant bit)

Receive Error Detected. Indicates that there has been an error

received in the receive frame.

28

TOTAL PINS

*

n can be 0, 4, 8, or 12.

Reference Table 6 for pin numbers for the actual cluster(s) you are configuring.

†

Gigabit Ethernet and Fibre Channel TBI Configuration

1000BASE-T Gigabit Ethernet and Fibre Channel TBI is implemented in much the same

way as Gigabit Ethernet (GMII). Table 9 shows the possible CP pin combinations you can

V 04

36

CHAPTER 2: SIGNAL DESCRIPTIONS

use and Figure 3 shows receive and transmit pin configurations by cluster. Table 11 shows

the signals and pinouts for a single cluster for Gigabit Ethernet and Fibre Channel TBI.

The unused pins for the two cluster configurations should be wired down using a resistor.

Table 11 Gigabit Ethernet and Fibre Channel TBI Signals Example

SIGNAL NAME*

PIN #† TOTAL TYPE

I/O

LABEL

SIGNAL DESCRIPTION

CPn_0

Table 6 1

LVTTL

O

TCLK

Transmit Clock (125MHz). This clock is used to synchronize the

transmit data.

CPn_1

Table 6 1

nc

O

nc

O

nc

I

nc

CPn_2

LVTTL

nc

TXD(9)

TXD(8)

TXD(7)

TXD(6)

TXD(1)

nc

Transmit Data (ten bits wide, last on wire)

CPn_3

Transmit Data

CPn_4

Transmit Data

CPn_5

Transmit Data

CPn_6

Transmit Data

CPn+1_0

CPn+1_1

CPn+1_2

CPn+1_3

CPn+1_4

CPn+1_5

CPn+1_6

CPn+2_0

CPn+2_1

CPn+2_2

CPn+2_3

CPn+2_4

CPn+2_5

CPn+2_6

CPn+3_0

CPn+3_1

nc

LVTTL

nc

TXD(5)

TXD(4)

TXD(3)

TXD(2)

TXD(0)

nc

Transmit Data

Transmit Data (ten bits wide, first on wire)

nc

LVTTL

nc

RCLK

Receive Clock (62.5 MHz)

Receive Data (ten bits wide, last on wire)

Receive Data

I

RXD(9)

RXD(8)

RXD(7)

RXD(6)

RXD(1)

nc

I

Receive Data

I

Receive Data

I

Receive Data

nc

I

nc

LVTTL

RCLKN

Receive Clock Inverted

C5NP

Pin Descriptions Grouped by Function

37

Table 11 Gigabit Ethernet and Fibre Channel TBI Signals Example (continued)

SIGNAL NAME*

CPn+3_2

PIN #† TOTAL TYPE

I/O

LABEL

SIGNAL DESCRIPTION

Table 6 1

LVTTL

I

RXD(5)

RXD(4)

RXD(3)

RXD(2)

RXD(0)

Receive Data

CPn+3_3

Receive Data

CPn+3_4

Receive Data

CPn+3_5

Receive Data

CPn+3_6

Receive Data (ten bits wide, first on wire)

28

TOTAL PINS

*

n can be 0, 4, 8, or 12

Reference Table 6 for pin numbers for the actual cluster(s) you are configuring.

†

SONET OC-3 Transceiver Interface Configuration

Table 12 describes the SONET Optical Carrier (OC) 3 transceiver interface signals. For each

CP (0-15), you can implement a single OC-3 interface.

Table 12 OC-3 Signals

SIGNAL NAME*

CPn_0

PIN #†

TOTAL TYPE

I/O

LABEL

SIGNAL DESCRIPTION

Table 6

1

LVPECL

I

RCLK_H

RCLK_L

TXD_H

TXD_L

RXD_H

RXD_L

Receive Clock noninverted side of pair (155.52MHz)

Receive Clock inverted side of pair (155.52MHz)

Transmit Data noninverted side of pair

Transmit Data inverted side of pair

Receive Data noninverted side of pair

Receive Data inverted side of pair

CPn_1

LVPECL

I

CPn_2

O

I

CPn_3

CPn_4

CPn_5

I

CPn_6

I

SIGNAL_DET A light level above a certain threshold is present at the optical

receiver - single ended LVPECL.

7

TOTAL PINS

*

n can be from 0 to 15.

Reference Table 6 for pin numbers for the actual cluster(s) you are configuring.

†

SONET OC-12 Transceiver Interface Configuration

SONET Optical Carrier (OC) 12 is implemented by using one cluster of CPs. At any time, a

CP within a cluster spends half its time performing receive functions, and the other half

performing transmit functions. Table 13 shows a CP Cluster configured for one OC-12

interface.

V 04

38

CHAPTER 2: SIGNAL DESCRIPTIONS

Table 13 OC-12 Signals Example

SIGNAL NAME*

PIN #†

TOTAL TYPE

I/O

LABEL

SIGNAL DESCRIPTION

CPn_0

Table 6

1

LVTTL

O

TCLK

Deskewed Transmit Clock (77.76MHz). This clock is used to

synchronize the transmit data.

CPn_1

Table 6

1

LVTTL

I

TCLK1

Transceiver Transmit Clock. This clock sets the frequency of the

transmit data and is typically sourced by the PHY chip.

CPn_2

Table 6

1

LVTTL

nc

O

0

TXD(0)

TXD(1)

TXD(2)

TXD(3)

00F

Transmit Data (byte-wide data, least significant bit)

CPn_3

Transmit Data

CPn_4

Transmit Data

CPn_5

Transmit Data

CPn_6

Out of Frame

CPn+1_0

CPn+1_1

CPn+1_2

CPn+1_3

CPn+1_4

CPn+1_5

CPn+1_6

CPn+2_0

CPn+2_1

CPn+2_2

CPn+2_3

CPn+2_4

CPn+2_5

CPn+2_6

nc

O

nc

I

nc

LVTTL

nc

TXD(4)

TXD(5)

TXD(6)

TXD(7)

nc

Transmit Data

Transmit Data (byte-wide data, most significant bit)

nc

LVTTL

RCLK

RXD(0)

RXD(1)

RXD(2)

RXD(3)

FP

Receive Clock (77.76MHz)

I

Receive Data (byte-wide receive data, least significant bit)

I

Receive Data

I

Frame Synchronization Pulse. This is valid during the third A2 of

the receive SONET frame.

CPn+3_0

CPn+3_1

CPn+3_2

CPn+3_3

CPn+3_4

Table 6

1

nc

LVTTL

I

RXD(4)

RXD(5)

RXD(6)

Receive Data

C5NP

Pin Descriptions Grouped by Function

39

Table 13 OC-12 Signals Example (continued)

SIGNAL NAME*

CPn+3_5

PIN #†

TOTAL TYPE

I/O

I

LABEL

RXD(7)

nc

SIGNAL DESCRIPTION

Table 6

1

LVTTL

nc

Receive Data (most significant bit)

nc

CPn+3_6

1

nc

28

TOTAL PINS

*

n can be 0, 4, 8, or 12

Reference Table 6 for pin numbers for a different cluster.

†

Executive Processor The XP’s system interface manages the supervisory controls for the network interfaces, as

System Interface Signals

well as the set of pins that provide interfaces to other components in the system that are

not memories or network interfaces. It is also the primary interface used for initializing the

C-5 NP after reset. The XP signals include PCI signals, Serial interface signals, and PROM

interface signals.

PCI Signals

The PCI can be configured to support a 32bit PCI capable of operating at either 33MHz or

66MHz. The PCI is fully compliant with PCVI Specification revision 2.1. Table 14 describes

the PCI signals.

Table 14 PCI Signals

SIGNAL NAME

PIN #

TOTAL TYPE

I/O

SIGNAL DESCRIPTION

PAD0 - PAD31

T22, R21, P21, T21, R20, P20, T20, 32

R19, Q20, S20, R18, P19, T19,

R17, P18, T18, R16, Q18, S18, S16,

P17, T17, R15, P16, T16, S14, Q16,

T15, R14, P15, T14, Q14

PCI

I/O Multiplexed Address/Data Bus. These signals are

multiplexed address and data bits. The C-5 NP

receives addresses as target and drives addresses as

master. It drives the data and receives read data as

master.

PCBEX0 - PCBEX3 N21, N20, M20, O20

4

PCI

I/O Command byte enables. These signals are

multiplexed command and byte enabled signals.

The C-5 NP receives byte enables as target and drives

byte enables as master.

PPAR

P14

1

I/O Parity. This signal carries even parity for AD and CBE#

pins. It has the same receive and drive characteristics

as the address and data bus, except that it is one PCI

cycle later.

PFRAMEX

PTRDYX

PIRDYX

K20

L20

L19

1

PCI

I/O Cycle frame

I/O Target ready for data transfer

I/O Initiator ready for data transfer

V 04

40

CHAPTER 2: SIGNAL DESCRIPTIONS

Table 14 PCI Signals (continued)

SIGNAL NAME

PSTOPX

PDEVSELX

PPERRX

PSERRX

PCLK

PIN #

K18

N18

M18

L18

TOTAL TYPE

I/O

SIGNAL DESCRIPTION

1

PCI

I/O Target transaction stop request

I/O Target device selected

I/O Bus parity error

1

I/O System error

L15

1

I

Bus clock

PRSTX

N17

L17

1

I

Bus reset

PREQX

1

O

I

Initiator bus request (arbitration)

Initiator bus grant (arbitration)

Initialization device select

Interrupt

PGNTX

N19

O18

O16

1

PIDSEL

1

I

PINTA

1

O

50

TOTAL PINS

Serial Interface Signals

The Serial interface is a bidirectional two-wire serial bus. It can use one of the following

formats:

1 An 8bit data format followed by an acknowledge bit, which supports transfers at up to

400kbps (low speed).

2 a 16bit IEEE 802.3 MDIO data format with 10bits of addressing, which supports

transfers up to 25MHz (high speed).

The signals and pins are identical for both the high and low speed protocols.

Which of the two data rates used is selected by the state of the PROM interface’s SPLD

signal that is asserted while the PROM interface is idle. When SPLD is asserted HI the low

speed serial bus protocol is selected and when SPLD is asserted LOW the MDIO protocol is

selected.

The bus only supports a single master hierarchy that can operate as either a receiver or a

transmitter. The bus also supports collision detection and arbitration, and an integrated

addressing and data-transfer protocol.

Both SIDA and SICL are bidirectional lines that are connected, through a pull-up resistor,

to a positive supply voltage. When the bus is free, both lines are HIGH. The output stages

C5NP

Pin Descriptions Grouped by Function

41

of the devices connected to the bus must have either an open-drain or open-collector in

order to perform the wired-AND function required for its arbitration mechanism.

Table 15 Serial Port Signals

SIGNAL NAME

SICL

PIN #

O14

N14

TOTAL TYPE

I/O

SIGNAL DESCRIPTION

Serial Clock line

1

2

LVTTL I/O

SIDA

Serial Data line

TOTAL PINS

PROM Interface Signals

The PROM interface is a low speed I/O port that allows the C-5 NP to communicate

through external logic to PROM. The PROM clock is ¹/₂to ¹/₁₆the core clock rate. The

maximum PROM size is 4MBytes x 16, and configuration is required. The PROM signals are

listed in Table 16.

Table 16 PROM Interface Signals

SIGNAL

NAME

SPDO

SPDI

PIN #

N15

N16

M16

TOTAL TYPE

I/O

O

I

SIGNAL DESCRIPTION

Serial Data Out

Serial Data In

1

LVTTL

SPLD

O

When load is asserted on a positive clock

edge, the external logic performs a parallel

load. On each positive clock edge when

load is de-asserted, the shift registers shift.

When the PROM interface is idle:

• if SPLD is asserted HI it indicates low

speed serial protocol,

• if asserted LOW it indicates MDIO serial

protocol.

SPCK

M14

1

LVTTL

O

Clock

4

TOTAL PINS

Figure 4 shows the connections between the PROM Interface and external board logic.

The application is required to provide an external shift register with parallel-in and

parallel-out capabilities, and a parallel load register. Both devices should be

V 04

42

CHAPTER 2: SIGNAL DESCRIPTIONS

positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When

SPLD is deasserted the shift register shifts.

Figure 4 PROM Interface Diagram

C-5 Network Processor External Logic

21

0

CE

PROM_ADDR<21:1>

SPDO

21

1

6 0

21

6

0

SPDI

Internal Shift

Register

External Shift Register

15

21

0

CE

PROM_ADDR<21:1>

31

16 15

0

PROM _H_Word

PROM _LO_Word

1

21

16

PROM _Return_Data

PROM Clock Gen.

PROM Sequencer

PROM

SPCLK

SPLD

PROM_Data

The PROM interface operates in the following manner:

Two accesses are piplined together to execute one 32-bit fetch. The steps are shown in

Figure 5.

1 The PROM_ADDR is loaded into the network processor internal shift register.

2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles.

3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external

presentation register.

4 SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit

PROM_DATA. At the same time, the next PROM_ADDR is shifted into the external shift

register.

5 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external

presentation register and the first PROM_DATA into the external shift register.

6 SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network

processor internal shift register.

C5NP

Pin Descriptions Grouped by Function

43

7 SPLD is asserted for one SPCLK cycle, loading the first PROM_DATA into the network

processor PROM_RETURN_DATA register and the second PROM_DATA into the

external shift register.

8 SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the

network processor internal shift register.

9 SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the

network processor PROM_RETURN_DATA register.

Figure 5 PROM Interface Timing Outline

XP PROM Interface outline

‘

SPLD

‘

A1

A2

A3

A4

A5

SPDTO

SPDTI

D1

D2

D3

XP PROM Interface detail

23

14 15 16 17 18 19 20 21 22 23

1

2

3

4

5

6

7

1

2

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

1

2

3

4

5

6

7

8

9

10 11 12 13

SPCLK

SPLD

SPDTO

1

A1

A

A2

A3

A4

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

CE

x

20 19 18 17 16 15 14 13 12 11 10

0

The PROM_ADDR is loaded into the

C-5’s internal shift register.

3

5

The PROM_ADDR is shifted into

the external shift register.

The PROM_ADDR is loaded into the

external presentation register.

(SPCLK Rising Edge used for shifting)

2

4

The PROM_DATA is

presenting.

The PROM_DATA is loaded into the

external shift register.

D1

D2

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

x

SPDTI

15 14 13 12 11 10

The PROM_DATA is shifted into the C-5’s

Internal shift register.

6

8

The PROM_DATA is loaded into the C-5’s

internal PROM_RETURN_DATA register.

7

9

General System Interface Signal

Table 17 provides the signal for the Executive Processor reset power status and I/O clock.

The C-5 NP can be powered up with the XP either running or with the XP in reset mode

similar to the CPs. When the XP remains in reset mode, an external host can be used to

control the initialization of the C-5 NP.

V 04

44

CHAPTER 2: SIGNAL DESCRIPTIONS

Table 17 General System Interface Signal

SIGNAL NAME

PIN #

TOTAL TYPE

I/O

SIGNAL DESCRIPTION

XPUHOT

J19

1

LVTTL

I

Sample at Power On Reset determines if the XP RISC Core is held in reset. Low

equals reset and High equals active. During normal operation, this is an

external interrupt.

1

TOTAL PINS

Fabric Processor Interface The FP consists of two logical signal interfaces: a receive data interface and a transmit

Signals

data interface, each with its own control and clocking signals. The interface has the

following characteristics:

• The interface clocks FRXCLK and FTXCLK can have a different frequency from the core

C-5 NP clock frequency. The Fabric Data Processor (FDP) has synchronizing FIFOs at its

interface boundary to allow for a fabric interface frequency from 10MHz to 110MHz.

• The receive clock FRXCLK and the transmit clock FTXCLK must share the same

frequency. The synchronization logic internal to the FP requires related clock domains

on the transmit and receive interfaces. Each of the two clocks can have different phase

alignment, however, because they are generated externally.

Each data bus can be run at widths of 16 or 32 bits of data (FIN0 - FIN31 and FOUT0 -

FOUT31) per clock. The extra data pins in each configuration remain unused. The output

pins are driven to a known state, and the input pins should also be pulled to a known

state.

Table 18 Fabric Interface Signals

SIGNAL NAME

PIN #

TOTAL TYPE

I/O

SIGNAL DESCRIPTION

FIN0 - FIN31

W2, V1, T1, V2, U2, V3, T3, T2, W4, V4, V5, U4, T4, 32

W6, V6, U6, T5, T6, V7, T7, X8, W8, V8, V9, U8, X9,

V10, U10, X10, W10, X11, V11

LVTTL

I

Fabric Data Bus In

FOUT0 - FOUT31

W28, V29, T29, V28, U28, V27, T27, T28, W26,

V26, V25, U26, T26, W24, V24, U24, T25, T24,

V23, T23, X22, W22, V22, V21, U22, X21, V20,

U20, X20, W20, X19, V19

32

LVTTL

O

Fabric Data Bus Out

FRXCLK

W14

1

7

LVTTL

I

Receive Clock

Transmit Clock

FTXCLK

W16

FRXCTL0 - FRXCTL6

U12, W12, V12, X12, X13, V13, X14

I, O Receive Control Signals

C5NP

Pin Descriptions Grouped by Function

45

Table 18 Fabric Interface Signals (continued)

SIGNAL NAME

PIN #

TOTAL TYPE

I/O

SIGNAL DESCRIPTION

FTXCTL0 - FTXCTL6

U18, W18, V18, X18, X17, V17, X16

7

LVTTL

I, O Transmit Control Signals

80

TOTAL PINS

The following tables list the Fabric Interface pin mappings:

• Utopia1, Utopia2, Utopia3 ATM Mode mappings are listed in Table 19

• Utopia1, Utopia2, Utopia3 PHY Mode mappings are listed in Table 20

• PRIZMA Mode mappings are listed in Table 21 (PRIZMA mode is an example of Utopia3

PHY mode)

• Power X Mode mappings are listed in Table 22

Table 19 Utopia1*, 2*, 3 ATM Mode, C-5 Network Processor to Fabric Interface Pin Mapping

RECEIVE SIGNALS

TRANSMIT SIGNALS

C-5 NETWORK

PROCESSOR

C-5 NETWORK

PROCESSOR

I/O

UTOPIA

RxEnb*

RxClav

RxSOC

n/a

NOTE

I/O

UTOPIA

TxEnb*

TxClav

TxSOC

nc

NOTE

FRXCTL0

FRXCTL1

FRXCTL2

FRXCTL3

Output

Input

Pullup or nc

Pulldown

FTXCTL0

FTXCTL1

FTXCTL2

FTXCTL3

Output

Input

Output

nc

Pullup or nc

Pulldown

Pullup or

Pulldown

FRXCTL4

FRXCTL5

FRXCTL6

Input

n/a

FTXCTL4

FTXCTL5

FTXCTL6

nc

n/a

nc

RxPrty

Output

TxPrty

*

cell size must be 4Byte aligned.

Table 20 Utopia1*, 2*, 3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping

RECEIVE SIGNALS

TRANSMIT SIGNALS

C-5 NETWORK

PROCESSOR

C-5 NETWORK

PROCESSOR

I/O

UTOPIA

NOTE

I/O

UTOPIA

NOTE

FRXCTL0

Input

TxEnb*

Pullup

FTXCTL0

Input

RxEnb*

Pullup

V 04

46

CHAPTER 2: SIGNAL DESCRIPTIONS

Table 20 Utopia1*, 2*, 3 PHY Mode, C-5 Network Processor to Fabric Interface Pin Mapping

RECEIVE SIGNALS

TRANSMIT SIGNALS

C-5 NETWORK

PROCESSOR

C-5 NETWORK

PROCESSOR

I/O

UTOPIA

TxClav

TxSOC

n/a

NOTE

I/O

UTOPIA

RxClav

RxSOC

nc

NOTE

FRXCTL1

FRXCTL2

FRXCTL3

Output

Input

Pulldown or nc FTXCTL1

Output

nc

Pulldown or nc

Pulldown

FTXCTL2

FTXCTL3

Pullup or

Pulldown

FRXCTL4

FRXCTL5

FRXCTL6

Input

n/a

Pullup or

Pulldown

FTXCTL4

FTXCTL5

FTXCTL6

nc

n/a

Pullup or

Pulldown

nc

TxPrty

Output

RxPrty

*

cell size must be 4Byte aligned.

When configuring two C-5 network processors back-to-back using the Fabric Port, set up

the transmit side of each C-5 network processor in Utopia ATM mode and the receive side

of each C-5 network processor in Utopia PHY mode.

Table 21 PRIZMA Mode, C-5 Network Processor to Fabric Interface Pin Mapping

RECEIVE SIGNALS

TRANSMIT SIGNALS

C-5 NETWORK

PROCESSOR

C-5 NETWORK

PROCESSOR

I/O

UTOPIA

NOTE

I/O

UTOPIA

NOTE

FRXCTL0

Input

TxEnb*

pulldown

(not connected to

fabric)

FTXCTL0

Input

RxEnb*

pulldown

(not connected to

fabric)

FRXCTL1

FRXCTL2

FRXCTL3

Output

Input

TxClav

TxSOP

n/a

nc

FTXCTL1

FTXCTL2

FTXCTL3

Output

nc

RxClav

RxSOP

nc

Pulldown

Input

Pullup or

Pulldown

FRXCTL4

FRXCTL5

FRXCTL6

Input

n/a

Pullup or

Pulldown

FTXCTL4

FTXCTL5

FTXCTL6

nc

n/a

Pullup or

Pulldown

nc

TxPrty or nc

Output

RxPrty or nc

C5NP

Pin Descriptions Grouped by Function

47

Table 22 Power X Mode, C-5 Network Processor to Fabric Interface Pin Mapping

RECEIVE SIGNALS

TRANSMIT SIGNALS

C-5 NETWORK

PROCESSOR

C-5 NETWORK

PROCESSOR

I/O

POWER X

RxCtrl[0]

RxCtrl[1]

RxCtrl[2]

RxPrty[3]

RxPrty[2]

RxPrty[1]

RxPrty[0]

NOTE

I/O

POWER X

TxCtrl[0]

TxCtrl[1]

TxCtrl[2]

TxPrty[3]

TxPrty[2]

TxPrty[1]

TxPrty[0]

NOTE

FRXCTL0

FRXCTL1

FRXCTL2

FRXCTL3

FRXCTL4

FRXCTL5

FRXCTL6

Input

Pulldown FTXCTL0

Pulldown FTXCTL1

Pulldown FTXCTL2

FTXCTL3

Output

Pulldown or nc

FTXCTL4

FTXCTL5

FTXCTL6

BMU SDRAM Interface The BMU and SDRAM interface signals are described in Table 23.

Signals

The BMU is designed to support SDRAM devices with 12 address lines. All 139 data lines

and all 12 address lines must be connected to the SDRAM in order for the BMU to be able

to read and write external SDRAM properly.

Table 23 BMU SDRAM Interface Signals

SIGNAL NAME

PIN #

TOTAL TYPE

130 LVTTL

I/O

SIGNAL DESCRIPTION

MD0 - MD129

R29, Q28, P28, S28, R28, P29, R27,

Q26, P26, S26, R26, P27, R25, Q24,

P24, S24, R24, P25, S22, R23, R22,

N29, M28, L28, J29, O28, N28, L29,

K28, N27, M26, L26, J28, O26, N26,

L27, K26, N25, M24, L24, J27, O24,

N24, L25, K24, P22, M22, K22, J23,

Q22, N23, L22, J25, O22, L23, J26,

J22, P23, N22, L21, J24, B29, D29,

F29, A28, C28, E28, G28, B28, D28,

F28, B27, D27, F27, A26, C26, E26,

B26, D26, F26, G26, B25, D25, F25,

A24, C24, E24, B24, D24, F24, B23,

D23, F23, G24, A22, C22, E22, B22,

D22, F22, B21, D21, F21, A20, C20,

E20, G22, B20, D20, F20, B19, D19,

F19, A18, C18, E18, B18, D18, F18,

G20, B17, D17, F17, A16, C16, E16,

B16, D16, F16, B15

I/O Data Lines In

MDECC0 - MDECC8 G16, F15, F14, E14, D15, D14, C14,

B14, A14

9

LVTTL

I/O Stored as data, ECC bits

V 04

48

CHAPTER 2: SIGNAL DESCRIPTIONS

Table 23 BMU SDRAM Interface Signals (continued)

SIGNAL NAME

PIN #

TOTAL TYPE

I/O

SIGNAL DESCRIPTION

MA0 - MA11

H22, I22, H23, H24, I24, H25, H26,

I26, H27, H28, I28, H29

12

LVTTL

O

Address Outputs: A0-A11 are sampled during the

ACTIVE command and READ/WRITE to select one

location out of the memory array in the respective

bank. The address inputs also provide the

op-code during a LOAD MODE REGISTER

command

MBA0 - MBA1

G18, H19

2

LVTTL

O

Bank Address Outputs: BA0 and BA1 define which

bank the ACTIVE, READ, WRITE or PRECHARGE

command is being applied

MCLK

I16

1

nc

O

Reserved

MCASX

J21

LVTTL

Command Outputs: MRASX, MCASX, MWEX and

MCSX define the command being entered.

NOTE: MCSX is considered part of the command

code.

MRASX

MWEX

MCSX

I20

1

LVTTL

O

Command Outputs: MRASX, MCASX, MWEX and

MCSX define the command being entered. MCSX

is considered part of the command code.

J20

H20

Command Outputs: MRASX, MCASX, MWEX and

MCSX define the command being entered. MCSX

is considered part of the command code.

Chip Select: MCSX enables (registered LOW) and

disables (registered HIGH) the command decoder.

All commands are masked when MCSX is

registered HIGH. MCSX provides the external bank

selection on systems with multiple banks. MCSX is

considered part of the command code.

MDQM

MDQML

H21

G14

1

LVTTL

O

Input/Output Mask: MDQM is an input mask

signal for write accesses and an output enable

signal for read accesses. Input data is masked

when MDQM is sampled HIGH during a WRITE

cycle. The output buffers are placed in a high Z

state (two-clock latency) when MDQM is sampled

HIGH during the READ cycle.

NOTE: MDQML is an identical copy of MDQM

used to drive the loading on SDRAM

configurations with 2 DQM pins.

C5NP

Pin Descriptions Grouped by Function

49

Table 23 BMU SDRAM Interface Signals (continued)

SIGNAL NAME

PIN #

TOTAL TYPE

I/O

SIGNAL DESCRIPTION

Clock: MDCLK is driven by the system clock. All

MDCLK

J17

1

LVTTL

I

SDRAM input signals are sampled on the positive

edge of the MDCLK. MDCLK also increments the

internal burst counter and controls the output

registers.

161

TOTAL PINS

TLU SRAM Interface The TLU SRAM interface supports up to 32MBytes of SRAM at frequencies to 133MHz

Signals

using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to

64Mbits. The TLU SRAM interface signals are described in Table 24.

Table 24 TLU SRAM Interface Signals

SIGNAL NAME

PIN #

TOTAL TYPE

I/O

SIGNAL DESCRIPTION

TD0 - TD63

N1, L1, J1, H1, M2, K2, I2, G2, N2, L2, J2, H2, L3, J3, 64

H3, G4, 04, M4, K4, I4, L4, J4, H4, G6, N5, L5, J5, H5,

N6, L6, I6, H6, K6, J6, M6, H7, L7, J7, H8, N8, M8, K8,

I8, G8, N7, L8, J8, H9, L9, J9, J10, G10, P9, O8, L10,

H10, O10, N9, L11, I10, M10, K10, J11, H11

LVTTL I/O TLU Memory Data

TA0 - TA21

R1, P1, S2, Q2, O2, R2, P2, R3, P3, N3, S4, Q4, R4, P4, 22

N4, R5, P5, S6, R6, Q6, P6, O6

LVTTL

O

TLU Memory Address

TA18x - TA21x

TCE0X - TCE3X

TWE0X - TWE3X

TCLKI

T8, Q8, R7, P7

P8, R8, S8, T9

Q10, R9, S10, T10

M12

4

LVTTL

O

I

Data Parity

4

TLU Memory Chip Enable

TLU Memory Write Enable

TLU Clock Input

4

1

99

TOTAL PINS

Table 25 Memory Bank Selection

CHIP SELECT (SIGNALS TA18X THROUGH TA21X)

BANK 1

BANK 2

BANK 3

BANK 4

SIZE

CE2

CE2X

TA19

TA20

TA21

CE2

CE2X

TA19

TA20

TA21

CE2

CE2X

CE2

CE2X

4Mbit

8Mbit

TA18x

TA19x

TA18

TA19

TA20

TA18x

TA19x

TA20x

TA19x

TA20x

TA21x

TA18

TA19

TA20

TA19x

TA20x

TA21x

16Mbit TA20x

V 04

50

CHAPTER 2: SIGNAL DESCRIPTIONS

QMU SRAM Interface The QMU signals are described in Table 26. The QMU’s clock frequency is ¹/₂the internal

Signals

core clock frequency.

Table 26 QMU SRAM Interface Signals

SIGNAL NAME

QCPAR

PIN #

A10

TOTAL TYPE

I/O* SIGNAL DESCRIPTION

1

nc

O

Not used

QCLK

G12

1

LVTTL

Clock Signal to the memory ICs

QCMD0 - QCMD15

B10, C10, D10, E10, F10, B11, D11, F11,

A12, B12, C12, D12, E12, B13, D13, F13

16

O

Memory Address [15: 0] to the memory

ICs

QDPAR

A8

1

LVTTL I/O

Data parity

QDATA0 - QDATA31

D1, F1, F2, B2, C2, D2, E2, B3, D3, F3, A4,

B4, C4, D4, E4, F4, B5, D5, F5, A6, B6, C6,

D6, E6, F6, B7, D7, F7, C8, D8, E8, F8

32

Memory Data

QSFLOW

QXCTRL0

QXCTRL1

QXRQST

B9

D9

F9

B8

1

LVTTL

nc

O

Not Used

O

Rd/Wr (Read is true high, write is true low)

Memory Address [16] to the memory ICs

O

nc

Reserved

Note: Requires Pullup or Pulldown.

55

TOTAL PINS

*

During normal (non-scan) operation.

Power Supply Signals Power supply and ground signals are described in Table 27 and their pinouts are shown in

Figure 6.

Table 27 Power Supply Signals

SIGNAL NAME

PIN #

TOTAL

TYPE

SIGNAL DESCRIPTION

VDD

A3, A11, A15, A23, A27, C1, C5, C13, C17, C25, C29,

E3, E7, E15, E19, E27, G5, G9, G17, G21, G29, I7, I11,

I19, I23, J12, K1, K9, K13, K21, K25, L14, M3, M11,

M15, M23, M27, O1, O5, O13, O17, O25, O29, Q3, Q7,

Q15, Q19, Q27, S5, S9, S17, S21, S29, U7, U11, U19,

U23, W1, W9, W13, W21, W25, Y3, Y11, Y15, Y23, Y27,

AA1, AA5, AA13, AA17, AA25, AA29, AC3, AC7, AC15,

AC19, AC27

78

P

Core Supply Voltage (1.8V Input)

C5NP

Pin Descriptions Grouped by Function

51

Table 27 Power Supply Signals (continued)

SIGNAL NAME

PIN #

TOTAL

TYPE

SIGNAL DESCRIPTION

VDD33

A7, A19, C9, C21, E11, E23, F12, G1, G13, G25, H14, I3, 39

I15, I27, J16, K5, K17, K29, M7, M19, O9, O21, Q11,

Q23, S1, S13, S25, U3, U15, U27, W5, W17, W29, Y7,

Y19, AA9, AA21, AC11, AC23

P

I/O Supply Voltage (3.3V Input)

VSS

A5, A9, A13, A17, A21, A25, A29, C3, C7, C11, C15,

C19, C23, C27, E1, E5, E9, E13, E17, E21, E25, E29, G3,

G7, G11, G19, G23, G27, H12, H16, I1, I5, I9, I13, I17,

I21, I25, I29, J14, J18, K3, K7, K11, K15, K19, K23, K27,

L16, M1, M5, M9, M13, M17, M21, M25, M29, O3, O7,

O11, O15, O19, O23, O27, Q1, Q5, Q9, Q13, Q17, Q21,

Q25, Q29, S3, S7, S11, S15, S19, S23, S27, U1, U5, U9,

U13, U17, U21, U25, U29, W3, W7, W11, W15, W19,

W23, W27, Y1, Y5, Y9, Y13, Y17, Y21, Y25, Y29, AA3,

AA7, AA11, AA15, AA19, AA23, AA27, AC1, AC5, AC9,

AC13, AC17, AC21, AC25, AC29

116

P

Ground

234

TOTAL PINS

V 04

52

CHAPTER 2: SIGNAL DESCRIPTIONS

Figure 6 Power and Ground Connections (Bottom View)

AC

AB

AA

Z

Y

X

W

V

U

T

S

R

Q

P

O

N

M

L

K

J

I

H

G

F

E

D

C

B

A

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

VSS (Ground) - 0.0V

VDD (Core Supply) - 2.5V

VDD33 (I/O Supply) - 3.3V

Other

Test Signals Test signals are described in Table 28 and their pinouts are shown in Figure 6.

C5NP

Signals Grouped by Pin Number

53

Table 28 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines

SIGNAL NAME

JTCK

PIN #

T11

TOTAL

TYPE

SIGNAL DESCRIPTION

1

LVTTL

Test Clock

JTMS*

Z15

Test Mode Select. High selects modes

as defined in the IEEE 1149.1 JTAG

specification.

JTRSTX†

JTDI†

X15

AB15

V15

T12

1

LVTTL

Test Reset (low active)

Test Data In

JTDO

Test Data Out

JHIGHZ

JCLKBYP

Turns off all output drivers when High

T13

1X or 2X Clock Mode Select. Low

selects 1X, High selects 2X.

JSE

S12

1

LVTTL

Scan Enable. High enables scan test.

Scan Out Pins

JS00-JS09

L12, N13, N12, P13, P12, Q12, R13, R12, 10

R11, R10

18

TOTAL PINS

*

According to the IEEE 1149.1 specification, the JTMS, JTRST, and JTDI pins must have internal pullups. While the C-5 NP does not currently have pads

with pullups, customers can pull up these three pins on the board.

During JTAG, SCLK and SCLKX must remain as differential inputs.

No Connection Pins No connection pins are listed in Table 29.

Table 29 No Connection Pins

SIGNAL NAME

PIN #

TOTAL

TYPE

SIGNAL DESCRIPTION

NC1 - NC11

I18, H17, H18, N10, P10, N11, P11, U14, 11

V14, U16, V16

nc

Reserved for future functionality

11

TOTAL PINS

Signals Grouped by Pin

Number

The C-5 NP signals are listed by pin number in Table 30.

V 04

54

CHAPTER 2: SIGNAL DESCRIPTIONS

Table 30 Signals Listed by Pin Number

FUNCTION

A 1-29

FUNCTION

A1

A2

A3

A4

A5

A6

A7

A8

Not present A9

Not present A10

VSS

A17

A18

A19

A20

A21

A22

A23

A24

VSS

A25

A26

A27

A28

A29

VSS

QCPAR

VDD

MD113

VDD33

MD103

VSS

MD74

VDD

MD64

VSS

VDD

A11

A12

A13

A14

A15

A16

QDATA10

VSS

QCMD8

VSS

QDATA19

VDD33

QDPAR

MECC8

VDD

MD94

VDD

MD123

MD84

B 1-29

B1

B2

B3

B4

B5

B6

B7

B8

Not present B9

QSFLOW

QCMD0

QCMD5

QCMD9

QCMD13

MECC7

B17

B18

B19

B20

B21

B22

B23

B24

MD120

MD116

MD110

MD107

MD100

MD97

B25

B26

B27

B28

B29

MD81

MD77

MD71

MD68

MD61

QDATA3

QDATA7

QDATA11

QDATA16

QDATA20

QDATA25

QXRQST

B10

B11

B12

B13

B14

B15

B16

MD129

MD126

MD90

MD87

C 1-29

C1

C2

C3

C4

C5

C6

C7

C8

VDD

C9

VDD33

QCMD1

VSS

C17

C18

C19

C20

C21

C22

C23

C24

VDD

C25

CB26

C27

C28

C29

VDD

MD75

VSS

QDATA4

VSS

C10

C11

C12

C13

C14

C15

C16

MD114

VSS

QDATA12

VDD

QCMD10

VDD

MD104

VDD33

MD95

VSS

MD65

VDD

QDATA21

VSS

MECC6

VSS

QDATA28

MD124

MD85

C5NP

Signals Grouped by Pin Number

55

Table 30 Signals Listed by Pin Number (continued)

FUNCTION

D 1-29

FUNCTION

D1

D2

D3

D4

D5

D6

D7

D8

QDATA0

QDATA5

QDATA8

QDATA13

QDATA17

QDATA22

QDATA26

QDATA29

D9

QXCTRL0

QCMD2

QCMD6

QCMD11

QCMD14

MECC5

D17

D18

D19

D20

D21

D22

D23

D24

MD121

MD117

MD111

MD108

MD101

MD98

D25

D26

D27

D28

D29

MD82

MD78

MD72

MD69

MD62

D10

D11

D12

D13

D14

D15

D16

MECC4

MD91

MD127

MD88

E 1-29

E1

E2

E3

E4

E5

E6

E7

E8

VSS

E9

VSS

E17

E18

E19

E20

E21

E22

E23

E24

VSS

E25

E26

E27

E28

E29

VSS

QDATA6

VDD

E10

E11

E12

E13

E14

E15

E16

QCMD3

VDD33

QCMD12

VSS

MD115

VDD

MD76

VDD

MD66

VSS

QDATA14

VSS

MD105

VSS

QDATA23

VDD

MECC3

VDD

MD96

VDD33

MD86

QDATA30

MD125

F 1-29

F1

F2

F3

F4

F5

F6

F7

F8

QDATA1

QDATA2

QDATA9

QDATA15

QDATA18

QDATA24

QDATA27

QDATA31

F9

QXCTRL1

QCMD4

QCMD7

VDD33

F17

F18

F19

F20

F21

F22

F23

F24

MD122

MD118

MD112

MD109

MD102

MD99

F25

F26

F27

F28

F29

MD83

MD79

MD73

MD70

MD63

F10

F11

F12

F13

F14

F15

F16

QCMD15

MECC2

MECC1

MD128

MD92

MD89

V 04

56

CHAPTER 2: SIGNAL DESCRIPTIONS

Table 30 Signals Listed by Pin Number (continued)

FUNCTION

G 1-29

FUNCTION

G1

G2

G3

G4

G5

G6

G7

G8

VDD33

TD7

G9

VDD

G17

G18

G19

G20

G21

G22

G23

G24

VDD

G25

G26

G27

G28

G29

VDD33

MD80

VSS

G10

G11

G12

G13

G14

G15

G16

TD51

MBA0

VSS

TD15

VDD

TD23

VSS

QCLK

VDD33

MDQML

SCLKX

MECC0

MD119

VDD

MD67

VDD

MD106

VSS

TD43

MD93

H 1-29

H1

H2

H3

H4

H5

H6

H7

H8

TD3

H9

TD47

TD55

TD63

VSS

H17

H18

H19

H20

H21

H22

H23

H24

NC2

H25

H26

H27

H28

H29

MA5

MA6

MA8

MA9

MA11

TD11

TD14

TD22

TD27

TD31

TD35

TD38

H10

H11

H12

H13

H14

H15

H16

NC3

MBA1

MCSX

MDQM

MA0

CCLK5

VDD33

SCLK

VSS

MA2

MA3

I 1-29

I1

I2

I3

I4

I5

I6

I7

I8

VSS

I9

VSS

I17

I18

I19

I20

I21

I22

I23

I24

VSS

I25

I26

I27

I28

I29

VSS

TD6

I10

I11

I12

I13

I14

I15

I16

TD59

VDD

NC1

MA7

VDD33

MA10

VSS

VDD33

TD19

VSS

VDD

MRASX

VSS

CCLK3

VSS

TD30

VDD

TD42

CCLK4

VDD33

MCLK

MA1

VDD

MA4

C5NP

Signals Grouped by Pin Number

57

Table 30 Signals Listed by Pin Number (continued)

FUNCTION

J 1-29

FUNCTION

J1

J2

J3

J4

J5

J6

J7

J8

TD2

J9

TD49

TD50

TD62

VDD

J17

J18

J19

J20

J21

J22

J23

J24

MDCLK

VSS

J25

J26

J27

J28

J29

MD52

MD55

MD40

MD32

MD24

TD10

TD13

TD21

TD26

TD33

TD37

TD46

J10

J11

J12

J13

J14

J15

J16

XPUHOT

MWEX

MCASX

MD56

MD48

MD60

CCLK1

VSS

CCLK2

VDD33

K 1-29

K1

K2

K3

K4

K5

K6

K7

K8

VDD

TD5

K9

VDD

K17

K18

K19

K20

K21

K22

K23

K24

VDD33

PSTOPX

VSS

K25

K26

K27

K28

K29

VDD

K10

K11

K12

K13

K14

K15

K16

TD61

VSS

MD36

VSS

TD18

VDD33

TD32

VSS

CCLK0

VDD

PFRAMEX

VDD

MD28

VDD33

CCLK6

VSS

MD47

VSS

TD41

CCLK7

MD44

L 1-29

L1

L2

L3

L4

L5

L6

L7

L8

TD1

L9

TD48

TD54

TD58

JSO0

CPREF

VDD

L17

L18

L19

L20

L21

L22

L23

L24

PREQX

PSERRX

PIRDYX

PTRDYX

MD59

L25

L26

L27

L28

L29

MD43

MD31

MD35

MD23

MD27

TD9

L10

L11

L12

L13

L14

L15

L16

TD12

TD20

TD25

TD29

TD36

TD45

MD51

PCLK

VSS

MD54

MD39

V 04

58

CHAPTER 2: SIGNAL DESCRIPTIONS

Table 30 Signals Listed by Pin Number (continued)

FUNCTION

M 1-29

FUNCTION

M1

M2

M3

M4

M5

M6

M7

M8

VSS

M9

VSS

M17

M18

M19

M20

M21

M22

M23

M24

VSS

M25

M26

M27

M28

M29

VSS

TD4

M10

M11

M12

M13

M14

M15

M16

TD60

VDD

TCLKI

VSS

PPERRX

VDD33

PCBEX2

VSS

MD30

VDD

MD22

VSS

VDD

TD17

VSS

TD34

VDD33

TD40

SPCK

VDD

SPLD

MD46

VDD

MD38

N 1-29

N1

N2

N3

N4

N5

N6

N7

N8

TD0

N9

TD57

NC4

N17

N18

N19

N20

N21

N22

N23

N24

PRSTX

N25

N26

N27

N28

N29

MD37

MD34

MD29

MD26

MD21

TD8

N10

N11

N12

N13

N14

N15

N16

PDEVSELX

PGNTX

PCBEX1

PCBEX0

MD58

TA9

NC6

TA14

TD24

TD28

TD44

TD39

JSO2

JSO1

SIDA

SPDO

SPDI

MD50

MD42

O 1-29

O1

O2

O3

O4

O5

O6

O7

O8

VDD

TA4

O9

VDD33

TD56

VSS

O17

O18

O19

O20

O21

O22

O23

O24

VDD

O25

O26

O27

O28

O29

VDD

MD33

VSS

O10

O11

O12

O13

O14

O15

O16

PIDSEL

VSS

TD16

VDD

TA21

VSS

TCLKO

VDD

PCBEX3

VDD33

MD53

VSS

MD25

VDD

SICL

VSS

TD53

PINTA

MD41

C5NP

Signals Grouped by Pin Number

59

Table 30 Signals Listed by Pin Number (continued)

FUNCTION

P 1-29

FUNCTION

P1

P2

P3

P4

P5

P6

P7

P8

TA1

P9

TD52

NC5

P17

P18

P19

P20

P21

P22

P23

P24

PAD20

PAD14

PAD11

PAD5

P25

P26

P27

P28

P29

MD17

MD8

TA6

P10

P11

P12

P13

P14

P15

P16

TA8

NC7

MD11

MD2

TA13

TA16

TA20

TA21X

TCE0X

JSO4

JSO3

PPAR

PAD29

PAD23

PAD2

MD5

MD45

MD57

MD14

Q 1-29

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

VSS

Q9

VSS

Q17

Q18

Q19

Q20

Q21

Q22

Q23

Q24

VSS

Q25

Q26

Q27

Q28

Q29

VSS

TA3

Q10

Q11

Q12

Q13

Q14

Q15

Q16

TWE0X

VDD33

JSO5

PAD17

VDD

MD7

VDD

MD1

VSS

VDD

TA11

VSS

PAD8

VSS

TA19

VDD

TA19X

PAD31

VDD

MD49

VDD33

MD13

PAD26

R 1-29

R1

R2

R3

R4

R5

R6

R7

R8

TA0

R9

TWE1X

JSO9

R17

R18

R19

R20

R21

R22

R23

R24

PAD13

PAD10

PAD7

R25

R26

R27

R28

R29

MD12

MD10

MD6

TA5

R10

R11

R12

R13

R14

R15

R16

TA7

JSO8

TA12

TA15

TA18

TA20X

TCE1X

JSO7

PAD4

MD4

JSO6

PAD1

MD0

PAD28

PAD22

PAD16

MD20

MD19

MD16

V 04

60

CHAPTER 2: SIGNAL DESCRIPTIONS

Table 30 Signals Listed by Pin Number (continued)

FUNCTION

S 1-29

FUNCTION

S1

S2

S3

S4

S5

S6

S7

S8

VDD33

TA2

S9

VDD

S17

S18

S19

S20

S21

S22

S23

S24

VDD

S25

S26

S27

S28

S29

VDD33

MD9

VSS

S10

S11

S12

S13

S14

S15

S16

TWE2X

VSS

PAD18

VSS

TA10

VDD

TA17

VSS

JSE

PAD9

VDD

MD3

VDD

VDD33

PAD25

VSS

MD18

VSS

TCE2X

PAD19

MD15

T 1-29

T1

T2

T3

T4

T5

T6

T7

T8

FIN2

T9

TCE3X

TWE3X

JTCK

T17

T18

T19

T20

T21

T22

T23

T24

PAD21

PAD15

PAD12

PAD6

T25

T26

TT27

T28

T29

FOUT16

FOUT12

FOUT6

FOUT7

FOUT2

FIN7

T10

T11

T12

T13

T14

T15

T16

FIN6

FIN12

FIN16

FIN17

FIN19

TA18X

JHIGHZ

JCLKBYP

PAD30

PAD27

PAD24

PAD3

PAD0

FOUT19

FOUT17

U 1-29

U1

U2

U3

U4

U5

U6

U7

U8

VSS

U9

VSS

U17

U18

U19

U20

U21

U22

U23

U24

VSS

U25

U26

U27

U28

U29

VSS

FIN4

U10

U11

U12

U13

U14

U15

U16

FIN27

VDD

FTXCTL0

VDD

FOUT11

VDD33

FOUT4

VSS

VDD33

FIN11

VSS

FRXCTL0

VSS

FOUT27

VSS

FIN15

VDD

NC8

FOUT24

VDD

VDD33

NC10

FIN24

FOUT15

C5NP

Signals Grouped by Pin Number

61

Table 30 Signals Listed by Pin Number (continued)

FUNCTION

V 1-29

FUNCTION

V1

V2

V3

V4

V5

V6

V7

V8

FIN1

V9

FIN23

FIN26

FIN31

FRXCTL2

FRXCTL5

NC9

V17

V18

V19

V20

V21

V22

V23

V24

FTXCTL5

FTXCTL2

FOUT31

FOUT26

FOUT23

FOUT22

FOUT18

FOUT14

V25

V26

V27

V28

V29

FOUT10

FOUT9

FOUT5

FOUT3

FOUT1

FIN3

V10

V11

V12

V13

V14

V15

V16

FIN5

FIN9

FIN10

FIN14

FIN18

FIN22

JTDO

NC11

W 1-29

W1

W2

W3

W4

W5

W6

W7

W8

VDD

W9

VDD

W17

W18

W19

W20

W21

W22

W23

W24

VDD33

FTXCTL1

VSS

W25

W26

W27

W28

W29

VDD

FIN0

VSS

W10

W11

W12

W13

W14

W15

W16

FIN29

VSS

FOUT8

VSS

FIN8

VDD33

FIN13

VSS

FRXCTL1

VDD

FOUT29

VDD

FOUT0

VDD33

FRXCLK

VSS

FOUT21

VSS

FIN21

FTXCLK

FOUT13

X 1-29

X1

X2

X3

X4

X5

X6

X7

X8

CP15_0

CP15_1

CP15_2

CP15_3

CP15_4

CP15_5

CP15_6

FIN20

X9

FIN25

X17

X18

X19

X20

X21

X22

X23

X24

FTXCTL4

FTXCTL3

FOUT30

FOUT28

FOUT25

FOUT20

CP14_6

CP14_5

X25

X26

X27

X28

X29

CP14_4

CP14_3

CP14_2

CP14_1

CP14_0

X10

X11

X12

X13

X14

X15

X16

FIN28

FIN30

FRXCTL3

FRXCTL4

FRXCTL6

JTRSTX

FTXCTL6

V 04

62

CHAPTER 2: SIGNAL DESCRIPTIONS

Table 30 Signals Listed by Pin Number (continued)

FUNCTION

Y 1-29

FUNCTION

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

VSS

Y9

VSS

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

VSS

Y25

Y26

Y27

Y28

Y29

VSS

CP13_0

VDD

Y10

Y11

Y12

Y13

Y14

Y15

Y16

CP13_4

VDD

CP12_5

VDD33

CP12_4

VSS

CP12_1

VDD

CP13_1

VSS

CP13_5

VSS

CP12_0

VSS

CP13_2

VDD33

CP13_3

CP13_6

VDD

CP12_3

VDD

CP12_6

CP12_2

Z 1-29

Z1

Z2

Z3

Z4

Z5

Z6

Z7

Z8

CP9_0

CP9_1

CP9_2

CP9_3

CP9_4

CP9_5

CP9_6

CP11_0

Z9

CP11_1

CP11_2

CP11_3

CP11_4

CP11_5

CP11_6

JTMS

Z17

Z18

CP10_5

CP10_4

CP10_3

CP10_2

CP10_1

CP10_0

CP8_6

Z25

Z26

Z27

Z28

Z29

CP8_4

CP8_3

CP8_2

CP8_1

CP8_0

Z10

Z11

Z12

Z13

Z14

Z15

Z16

Z19

Z20

Z21

Z22

Z23

CP10_6

Z24

CP8_5

AA 1-29

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

VDD

AA9

VDD33

CP7_4

VSS

AA17

VDD

AA25

AA26

AA27

AA28

AA29

VDD

CP7_0

VSS

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA18

AA19

AA20

AA21

AA22

AA23

AA24

CP6_5

VSS

CP6_1

VSS

CP7_1

VDD

CP7_5

VDD

CP6_4

VDD33

CP6_3

VSS

CP6_0

VDD

CP7_2

VSS

CP7_6

VSS

CP7_3

CP6_6

CP6_2

C5NP

JTAG Support

63

Table 30 Signals Listed by Pin Number (continued)

FUNCTION

AB 1-29

AB1

AB2

AB3

AB4

AB5

AB6

AB7

AB8

CP3_0

CP3_1

CP3_2

CP3_3

CP3_4

CP3_5

CP3_6

CP5_0

AB9

CP5_1

CP5_2

CP5_3

CP5_4

CP5_5

CP5_6

JTDI

AB17

CP4_5

CP4_4

CP4_3

CP4_2

CP4_1

CP4_0

CP2_6

CP2_5

AB25

AB26

AB27

AB28

AB29

CP2_4

CP2_3

CP2_2

CP2_1

CP2_0

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB18

AB19

AB20

AB21

AB22

AB23

AB24

CP4_6

AC 1-29

AC1

AC2

AC3

AC4

AC5

AC6

AC7

AC8

VSS

AC9

VSS

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

VSS

AC25

AC26

AC27

AC28

AC29

VSS

CP1_0

VDD

AC10

AC11

AC12

AC13

AC14

AC15

AC16

CP1_4

VDD33

CP1_5

VSS

CP0_5

VDD

CP0_1

VDD

CP0_0

VSS

CP1_1

VSS

CP0_4

VSS

CP1_2

VDD

CP1_6

VDD

CP0_3

VDD33

CP0_2

CP1_3

CP0_6

JTAG Support

The C-5 NP contains JTAG test logic compliant with the IEEE 1149.1 specification. All

required public instructions are implemented, as well as some optional instructions. This

section contains information regarding the pinout, instructions, identification codes, and

boundary scan cell types.

Pinout The C-5 NP uses the standard JTAG pins including the optional test reset pin. Table 28

describes the pins and their functions. Note that pins for JTRSTX, JTDI, and JTMS require

external pullups on the board. These ports do not have internal pullups as required by the

1149.1 specification.

V 04

64

CHAPTER 2: SIGNAL DESCRIPTIONS

JTAG Data Registers The C-5 NP contains the standard internal registers as specified in IEEE 1149.1. These

registers are described in Table 31.

Table 31 JTAG Internal Register Descriptions

REGISTER NAME

Bypass

REGISTER LENGTH

DESCRIPTION

1

Standard JTAG bypass register

Boundary Scan Register

Standard JTAG IDCODE Register

Boundary

1807

32

Device Identification

Boundary Scan Cell Types The C-5 NP boundary scan register contains only two cell types. All input cells are observe

only cells of type BC_4. All enable and output cells are standard cells of type BC_1. In IEEE

1149.1-1990 specification, the BC_4 cell is shown in Figure 7 and the BC_1 cell is shown in

Figure 8.

Figure 7 Observe-Only Cell

To next cell

To System

Logic

From System Pin

G1

0

1D

C1

1

C5NP

JTAG Support

65

Figure 8 Cell Design That Can Be Used for Both Input and Output Pins

Node

To next cell

Shift DR

G1

From

System

0

1

To

System

Logic

G1

0

1D

C1

1D

C1

1

From last cell

Update DR

Clock

DR

IDcode Register The C-5 NP implements a standard 32bit JTAG identification register. Table 32 lists the

value of the code for full identification and its sub-components.

Table 32 JTAG Identification Code and Its Sub-components

FIELD NAME

Version

WIDTH

BIT POSITIONS

BINARY VALUE

4

31-28

27-12

11-1

0

0000

Part Number

Manufacturer Identity

LSB

16

11

1

0000_0000_0000_0010

001_1001_0110

1

The concatenated 32bit value is hexidecimal 0000232d.

JTAG Instruction Register The C-5 NP contains a 4bit instruction register. Table 33 lists the instructions that are

supported.

Table 33 Instruction Register Instructions

INSTRUCTION MNEMONIC

SELECTED REGISTER

Boundary Scan

INSTRUCTION OPCODE

Extest

0000

0001

Idcode

Identification Register

V 04

66

CHAPTER 2: SIGNAL DESCRIPTIONS

Table 33 Instruction Register Instructions (continued) (continued)

INSTRUCTION MNEMONIC

SELECTED REGISTER

Boundary Scan

Bypass Register

INSTRUCTION OPCODE

Sample/Preload

Highz

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Clamp

Bypass

Reserved*

Bypass

*

There are two reserved instructions intended for C-Port Corporation’s internal use. These should not be

programmed by users.

Boundary Scan In order to simplify board test, C-Port Corporation has provided a boundary scan

Description Language

description language (BSDL) file in the C-Port web site support area that describes the

complete set of instructions, boundary scan order, and identification code value in an

industry standard format. This information can be found at:

http://e-www.motorola.com/webapp/sps/site/homepage.jsp?nodeId=03M0ylgx1Ks.

C5NP

C5NPD0-DS/D

Rev 04

Chapter 3

ELECTRICAL SPECIFICATIONS

Absolute Maximum

Ratings

Table 34 lists the absolute maximum ratings for the C-5 network processor. Stresses

beyond those listed may cause permanent damage to the device. These are stress ratings

only and do not imply that operation under any conditions other than those listed under

“Recommended Operating Conditions” (Table 35) is possible.

Exposure to conditions beyond Table 34 can:

• Reduce device reliability

• Result in premature device failure, even with no immediate sign of failure

Prolonged exposure to conditions at or near the absolute maximum ratings could also

result in reduced useful life and reliability of the C-5 NP.

Table 34 C-5 Network Processor Absolute Maximum Ratings

PARAMETER

MIN

-0.5

MAX

UNIT

V

V_DD33Supply Voltage (3.3V input)*†

V_DDSupply Voltage (1.8V input)*

Voltage on any pin

+5

-0.5

+2.8

V

-0.5

V_DD33+ 0.5

V

Static Discharge Voltage

Storage Temperature

2000/500

-40

V

+125

°C

Absolute Maximum Junction Temperature

-40

*

Voltages are relative to Ground

Not to exceed V_DD+ 2.5V

†

V 04

68

CHAPTER 3: ELECTRICAL SPECIFICATIONS

Recommended Operating

Conditions

The recommended operating conditions describe an environment the C-5 NP network

processor is expected to encounter during normal operation. Table 35 delineates the

recommended operating parameters for the C-5 NP.

Table 35 C-5 Network Processor Recommended Operating Conditions

PARAMETER

MIN

3.135

1.7

MAX

3.465

1.9

UNIT

V

V_DD33Supply Voltage

V_DDSupply Voltage

V

I_DD33- V_DD33Supply Current

I_DD- V_DDSupply Current

T_jJunction Temperature

1.5*

14*

A

-40

100

°C

*

Peak values to be used by power supply designer.

DC Characteristics

The DC electrical characteristics define the input operating conditions for proper

operation and the output responses to applied DC signals and switch characteristics over

specified voltage and temperature ranges. The DC electrical characteristics are specified

within the recommended operating conditions including operating temperature and

power supply range as stated in this data sheet. Table 36 outlines the C-5 NP DC

characteristics.

Table 36 C-5 Network Processor DC Characteristics

PARAMETER*

MIN

2.0

MAX

UNIT

V

NOTES

LVTTL Input High Voltage

LVTTL Input Low Voltage

LVTTL Output High Voltage

LVTTL Output Low Voltage

LVTTL Input Current

V_DD33+.3

0.8

-0.3

2.4

V

@I_OH= -2mA

0.4

+5

V

@I_OL= +2mA

V_IN= 0V or V_DD33

-5

µA

V

LVPECL Input High Voltage

LVPECL Input Low Voltage

LVPECL Output High Voltage

V_DD33-1.165 V_DD33+.3V

-0.3 V_DD33-1.475

V_DD33-1.025 V_DD33-0.880

V

Load = 50ohm to

V_DD33- 2V

C5NP

Power Sequencing

69

Table 36 C-5 Network Processor DC Characteristics (continued) (continued)

PARAMETER*

MIN

MAX

UNIT

NOTES

LVPECL Output Low Voltage

V_DD33-1.810 V_DD33-1.620

V

Load = 50ohm to

V_DD33- 2V

LVPECL Input Current

CPREF

-5

+5

µA

V_DD33-1.38

V_DD33-1.26

V

Single-ended LVPECL

reference

*

All voltages are relative to Ground unless otherwise indicated.

Each control input pin has a capacitance associated with it. The capacitance at the control

input is due to the package and the input circuitry connected to the pin. Capacitance is

based on these conditions: T_A= 25°C; V_DD33= 3.3V; f = 1MHz. Table 37 provides

capacitance data.

Table 37 C-5 Network Processor Capacitance Data

PARAMETER

Input/Output Pins

Input Pins

TYPICAL

MAX

UNIT

pF

7

6

8

7

pF

Clock Pins

pF

Power Sequencing

The VDD rail must be kept within 2.5V of the VDD33 rail. However, this rule can be violated

for periods up to one second, as is typical during power sequencing, as long as:

• The VDD is not clamped to ground or some other low voltage.

• The number of power cycling events averages to less than once per day over the

lifetime of the product.

It is intended that the VDD and VDD33 rail be sequenced to their final value together for

most applications.

It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running

or begin running during power sequencing to propagate reset inside the C-5 NP. Figure 9

indicates the relationship between the clocks and PRSTX. There is no requirement that the

asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be

asserted within 100µs of power initiation. Typically, reset is held low during power

initiation.

V 04

70

CHAPTER 3: ELECTRICAL SPECIFICATIONS

Figure 9 Bringup Clock Timing Diagram

VDD, VDD33

PRSTX

£100ms

)

(

‡1ms

‡100ms

TCLKI, PCLK,

SCLK, SCLKX,

DCLK, FTXCLK,

FRXCLK

)

(

Power and Thermal

Characteristics

Table 38 provides the derived power and thermal characteristics for the production

version (Revision D0) of the C-5 NP.

Table 38 C-5 Network Processor Power and Thermal Characteristics

PARAMETER

MIN

TYP

MAX

UNITS TEST CONDITIONS

Power Dissipation, P_D

10.5

11.5

12.5

14.5

15.0

16.0

17.5

20.0

18.0

19.0

20.5

23.0

W

166MHz core clock (See Note 1)

180MHz core clock (See Note 1)

200MHz core clock (See Note 1)

233MHz core clock (See Note 1)

Maximum Junction

Temperature, T_J

100

^oC

Thermal Resistance, junction

0.24

1.87

4.8

^oC/W

See Note 2

to case, φ_JC

Thermal Resistance, junction

to ambient, φ_JA

Thermal Resistance, junction

to printed circuit board, φ_JB

C5NP

Power and Thermal Characteristics

71

Table 38 C-5 Network Processor Power and Thermal Characteristics (continued)

PARAMETER

MIN

TYP

MAX

UNITS TEST CONDITIONS

Thermal Resistance, Junction

through Board to Ambient,

φ_JBA

6.0

See Note 2

Effective Thermal Resistance,

φ_effective

1.43

^oC/W

See Note 3

Notes for Table 38:

1 Estimated power dissipation (+/-10%) is derived from measurements on the C-5 NP

Revision D00 under following conditions:

• BMU memory operating at 125MHz.

• TLU memory operating at 133MHz.

• V_DD= 1.8V, V_DD33= 3.3V, T_Jat approximately 50^oC.

• “Minimum” P_Dbased on idle condition (clocks running and no programs

executing).

• “Typical” P_Dbased on test application that implements Fast Ethernet forwarding

actively running on all CPs.

• “Maximum” P_Dbased on projected maximum consumption for any

high-bandwidth communications application executing on all CPs, FP, and XP.

2 Thermal performance specifications based on following conditions:

• Printed circuit board is based on the C-Ware Development System’s C-5 NP Switch

Module reference design, with specifications of:

– 14 total layers (5 planes). Planes at least 100mm x 100mm below the C-5 NP

before any interruptions.

– FR4 board material, Cu signal and plane material.

– 0.5mils signal layer thickness, 1.4mils plane layer thickness.

– Thermal resistance, board to ambient (φ_BA) of 1.2 ^oC/W.

• Custom heat sink design has the following characteristics:

V 04

72

CHAPTER 3: ELECTRICAL SPECIFICATIONS

– Dimensions: 100mm x 80mm x 10mm (height)

– Thermal resistance heat sink to ambient (φ_SA) of 1.6 ^oC/W @200 LFM. Figure 10

provides the characteristic thermal resistance curve for this heat sink for various

airflow rates.

– Thermal resistance case to heat sink (φ_CS) of 0.03 ^oC/W (Chromerics T705

thermal material).

– Note that target heat sink design is for low profile (10mm height) applications.

Significantly better thermal performance is possible with taller and/or wider

designs. Contact your C-Port representative for heat sink options.

3 Effective Thermal Resistance (φ_effective= φ_JAφ_JBA/ (φ_JA+ φ_JBA)) reflects the total thermal

performance of the heat sink and board, as outlined in Note 2 above.

Figure 10 Thermal Performance for C-5 Network Processor Heat Sink (see step 2 above)

3

2

1

0

200

400

600

800

1000

Velocity (ft/min)

Theoretical calculation of thermal resistance as a function of airflow velocity across heat sink

AC Timing Specifications

AC timing specifications consist of input requirements and output responses. The input

requirements include setup and hold times, pulse widths, and high and low times. The

output responses include delays from clock to signal. The AC timing specifications are

defined separately for each interface to the C-5 NP

Unless otherwise noted, all AC specifications were tested within the functional operating

range.

C5NP

AC Timing Specifications

73

See Figure 11. Output timing specifications for LVTTL pins are given with a 10pF load on

the output. Other loads can be simulated with the IBIS model available from C-Port. The

LVPECL driver is specified into a 50Ω load terminated to a (VDD33 - 2V) reference.

Figure 11 Test Loading Conditions

LVTTL

DUT

10pF

VDD33

+2V

LVPECL

DUT

50Ω

Clock Timing The system clock timing is shown in Figure 12 and described in Table 39.

Specifications

Figure 12 System Clock Timing Diagram

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 1

SCLK

SCLKX

T

sc

T

sl

sh

CCLKn

T

ccN

T

ccl

cch

V 04

74

CHAPTER 3: ELECTRICAL SPECIFICATIONS

Table 39 System Clock Timing Description

MIN

MAX

SYMBOL PARAMETER

1X CLK MODE

2X CLK MODE TYP

1X CLK MODE 2X CLK MODE UNIT COMMENT

Tsc

System Cycle Time 6.0

3.0

ns

166MHz core clock

5.0

4.3

2.5

2.14

200MHz core clock

233MHz core clock

Tsh

Sys Clk High Pulse 45

30

55

70

Duty cycle*

Tsl

Sys Clk Low Pulse

CCLK0 Cycle Time

CCLK1 Cycle Time

CCLK2 Cycle Time

CCLK3 Cycle Time

CCLK4 Cycle Time

CCLK5 Cycle Time

CCLK6 Cycle Time

CCLK7 Cycle Time

45

Duty cycle†

Tcc0

Tcc1

Tcc2

Tcc3

Tcc4

Tcc5

Tcc6

Tcc7

Tcch

Tccl

647.67

ns

T1†

488.28

29.097

22.353

20.00

9.412

8.00

E1†

E3†

T3†

RMII†

Fibre Channel†

GMII†

6.43

OC-3†

CCLKm High Time 40%

CCLKm Low Time 40%

40%

60%

% cycle pulse is high

% cycle pulse is low

*

Pulse duty cycle measured at crossing voltage of SCLK/SCLKX

†

The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5 NP . Clock inputs associated with a specific protocol should be tied to ground

when that protocol is not used by the C-5 NP . It is also possible to use one or more CCLKn inputs for other frequencies; contact your C-Port

representative for more information.

Unused clocks should be pulled to a known state (ground) through a resistor. If you are

using a clock generator, disabling the output should not cause a tristate. If it does, then

the line should be pulled down.

CP Timing Specifications This section describes the timing for the following CP interfaces:

• DS1/DS3 Ethernet Timing Description

• 10/100 Ethernet Timing Description

• Gigabit GMII/MII Ethernet Interface Timing Description

• OC-3 Timing Description

C5NP

AC Timing Specifications

75

• Gigabit TBI Interface Timing Description

• OC-12 Timing Description

DS1/DS3 Timing Specifications

The DS1/DS3 interface timing is shown in Figure 13 and described in Table 40.

Figure 13 DS1/DS3 Ethernet Timing Diagram

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 1

CPn_0 (TCLK)

CPn_2/3 (Tx)

T

cdt

T

cdo

Cycle 5

Cycle 2

Cycle 3

Cycle 4

CPn_1 (RCLK)

CPn_4/5 (Rx)

T

cdr

T

cds

cdh

Table 40 DS1/DS3 Ethernet Timing Description

SYMBOL PARAMETER MIN

TYP

MAX

UNIT

Tcdt

Tcdo

Tcdr

Tcds

Tcdh

DS1/DS3 Transmit Cycle Time

647/22.4

ns

DS1/DS3 Output Time

DS1/DS3 Receive Cycle Time

DS1/DS3 Setup Time

DS1/DS3 Hold Time

3.0/3.0

400/15.0 ns

647/22.4

ns

2.0

2.5

10/100 Ethernet Timing Specifications

The 10/100 Ethernet interface timing is shown in Figure 14 and described in Table 41.

V 04

76

CHAPTER 3: ELECTRICAL SPECIFICATIONS

Figure 14 10/100 Ethernet Timing Diagram

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 1

CPn_0 (TCLK)

T

cet

CPn_2/3/6 (Tx)

CPn_1/4/5 (Rx)

T

ceo

T

ceh

ces

Table 41 10/100 Ethernet Timing Description

SYMBOL PARAMETER

MIN

TYP

MAX

UNIT

ns

Tcet

Tceo

Tces

Tceh

Transmit Cycle Time*

20

Output Time

Setup Time

Hold Time

3.0

2.0

2.5

15.0

ns

*

STD/Fast Ethernet

Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications

The Gigabit GMII Ethernet interface timing is shown in Figure 15 and described in

Table 42. The TBI interface timing is shown in Figure 15 and described in Table 43.

C5NP

AC Timing Specifications

77

Figure 15 Gigabit Ethernet and TBI Interface Timing Diagram

Cycle 2

Cycle 3

Cycle 4

Cycle 5

GMII / TBI Tx

Cycle 1

CPn_0 (TCLK)

T

cgt

CPn_2-6 (Tx)

CPn+1_2-6 (Tx)

T

cgo

Cycle 1

Cycle 2

Cycle 3

MII Tx

MII CPn_1 (TCLK)

T

cmt

MII CPn_2-6 (Tx)

T

cmo

TBI Rx

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

CPn+2_1 (RCLKN)

CPn+3_1 (RCLK)

T

ctr

T

ctd

CPn_2-6 (Rx)

CPn+1_2-6 (Rx)

T

cth

cts

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

GMII Rx

CPn+2_1 (RCLK)

CPn+2_2-6 (Rx)

CPn+3_2-6 (Rx)

T

cgr

T

cgh

cgs

V 04

78

CHAPTER 3: ELECTRICAL SPECIFICATIONS

Table 42 Gigabit GMII/MII Ethernet Interface Timing Description

SYMBOL

GIGABIT PARAMETER

MIN

TYP

MAX

UNIT

ns

COMMENT

Tcgt

Transmit Cycle Time, GMII

8.0

Tcgo

Tcgr

Output Time, GMII

Receive Cycle Time

Setup Time

3.0

6.0

ns

8.0

ns

Tcgs

Tcgh

Tcmt

Tcmo

1.5

0.5

ns

Hold Time

ns

Transmit Cycle Time, MII

Output Time, MII

40/400

ns

100BaseT/10BaseT

2

12

ms

Table 43 Gigabit TBI Interface Timing Description

SYMBOL

TBI

PARAMETER

MIN

TYP

MAX

UNIT

ns

Tctt

Tcto

Tctr

Tctd

Tcts

Tcth

Transmit Cycle Time

Output Time

8.0

3.0

6.0*

1.0

ns

Receive Cycle Time

Rclk/Rclkn Deviation

Setup Time

16.0

ns

1.5

0.5

ns

Hold Time

ns

*

For Fibre Channel applications this value is 7.0ns for a transmit cycle time of 9.4ns.

OC-3 Timing Specifications

The OC-3 interface timing is shown in Figure 16 and described in Table 44.

C5NP

AC Timing Specifications

79

Figure 16 OC-3 Timing Diagram

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 1

CPn_2

CPn_3

T

c3t

T

c3i

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

CPn_0

CPn_1

T

c3r

T

c3d

CPn_4

CPn_5

T

c3h

c3s

T

c3h

c3s

Table 44 OC-3 Timing Description

SYMBOL PARAMETER

MIN

TYP

MAX

UNIT

ns

Tc3t

OC-3 Transmit Cycle Time

OC-3 Pulse Width

6.43

Tc3i

2.0

ns

Tc3r

OC-3 Receive Cycle Time* 6.0

ns

Tc3d

Tc3s

OC-3 Clock Duty Cycle

OC-3 Setup Time

OC-3 Hold Time

40

60

%

2.0

2.5

ns

Tc3h

155.52MHz

ns

*

V 04

80

CHAPTER 3: ELECTRICAL SPECIFICATIONS

OC-12 Timing Specifications

The OC-12 interface timing is shown in Figure 17 and described in Table 45.

Figure 17 OC-12 Timing Diagram

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 1

CPn_1 (TCLKI)

T

c12i

T

c12d

CPn_0 (TCLK)

CPn_2-6 (Tx)

T

c12t

T

c12o

Cycle 1

Cycle 2

Cycle 3

CPn_1 (RCLK)

CPn_2-6 (Rx)

T

c12r

T

c12h

c12s

Table 45 OC-12 Timing Description

SYMBOL PARAMETER

MIN

TYP

MAX

60

UNIT

Tc12i

Tc12d

Tc12t

Tc12o

Tc12r

Tc12s

Tc12h

OC-12 Transmit Cycle Time*

OC-3 Clock Duty Cycle

OC-12 Transmit Cycle Time†

OC-12 Output Time‡

OC-12 Receive Cycle Time

OC-12 Setup Time

12.86

ns

%

40

ns

3.0

10.0

12.0

2.0

OC-12 Hold Time

2.5

*

Input from PHY

Output from C-5 NP

Aligned to TCLK

†

‡

C5NP

AC Timing Specifications

81

Executive Processor The XP timing specifications include:

Timing Specifications

• PCI Timing Specifications

• MDIO Serial Interface Timing Specifications

• Low Speed Serial Interface Timing Specifications

• PROM Interface Timing Specifications

PCI Timing Specifications

The PCI timing is shown in Figure 18 and described in Table 46.

Figure 18 PCI Timing Diagram

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 1

PCLK

T

pc

PAD/P_ctl

(output)

T

pav

pao

paz

PAD/P_ctl

(input)

T

pas

pah

PGNTX

(input)

T

pgs

pgh

PIDSEL

(input)

T

pis

pih

Table 46 PCI Timing Description

SYMBOL PARAMETER

MIN

TYP

MAX

UNIT

ns

Tpc

PCI Cycle Time*

15.0

3.0

Tpas

PAD/P_ctl† Setup

ns

V 04

82

CHAPTER 3: ELECTRICAL SPECIFICATIONS

Table 46 PCI Timing Description (continued) (continued)

SYMBOL PARAMETER

MIN

0.0

2.0

1.8

1.3

5.1

0.0

5.0

0.0

TYP

MAX

UNIT

ns

Tpah

Tpao

Tpaz

Tpav

Tpgs

Tpgh

Tpis

PAD/P_ctl Hold

PAD/P_ctl Output

PAD/P_ctl Clk to Tri‡

PAD/P_ctl Clk to Driven‡

PGNTX Setup

PGNTX Hold

6.0

5.5

PIDSEL Setup

PIDSEL Hold

Tpih

PRSTX**

PINTA**

*

66MHz PCI

†

P_ctl includes all PCI control parameters including: PPAR, PFRAMEX, PTRDYX, PIRDYX,

PSTOPX, PDEVSELX, PPERRX, PSERRX

Not fully tested, values based on design/characterization.

^**Asynchronous

‡

MDIO Serial Interface Timing Specifications

The MDIO serial interface timing is shown in Figure 19 and described in Table 47.

Figure 19 MDIO Serial Interface Timing Diagram

Cycle 2

Cycle 3

Cycle 4

SICL

SIDA

T

sic

(output)

T

sods

sodh

SIDA

(input)

T

sids

C5NP

AC Timing Specifications

83

Table 47 MDIO Serial Interface Timing Description

SYMBOL PARAMETER

MIN

40

TYP

MAX

UNIT

ns

Tsic

SICL Cycle Time

SIDA Input Setup

SIDA Input Hold

Tsids

Tsidh

Tsods

Tsodh

10

ns

0.0

ns

SIDA Output Setup 10

SIDA Output Hold 10

ns

Low Speed Serial Interface Timing Specifications

The low speed serial interface timing is shown in Figure 20 and described in Table 48.

Figure 20 Low Speed Serial Interface Timing Diagram

Cycle 2

Cycle 3

SICL

SIDA

T

cyc

T

buf

su:s

hd:s

hd:d

su:d

T

su:stop

Table 48 Low Speed Serial Interface Timing Description

SYMBOL PARAMETER

MIN

2500

600

250

0.0

MAX

UNIT

ns

Tcycle

Tsu:s

SICL Cycle Time

Set-up Time for Repeated START Condition

Hold Time START Condition

Data Set-up Time

ns

Thd:s

Tsu:d

Thd:d

ns

Data Hold Time

ns

Tsu:stop Set-up Time for STOP Condition

600

ns

V 04

84

CHAPTER 3: ELECTRICAL SPECIFICATIONS

Table 48 Low Speed Serial Interface Timing Description (continued) (continued)

SYMBOL PARAMETER

MIN

MAX

UNIT

ns

Tbuf

Bus Free Time Between a STOP and START Condition

Capacitive load for each line of the bus

1250

Cmax

400

pF

PROM Interface Timing Specifications

The PROM interface timing is shown in Figure 21 and described in Table 49.

Figure 21 PROM Interface Timing Diagram

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 1

SPCK

T

spc

SPDI

SPLD

SPDO

T

spih

spis

T

splo

T

spdo

Table 49 PROM Interface Timing Description

SYMBOL PARAMETER

CLOCK MODE

MIN

TYP

MAX

UNIT

Tspc

SPCK Cycle Time

40.0

ns

Tspis

Tspih

Tsplo

SPDI Setup

SPDI Hold

10.0

0.0

SPLD Output

1X

2X

1X

2X

Tsc*

Tsc + 3.0

2 x Tsc*

Tsc*

2 x Tsc + 3.0 ns

Tsc + 3.0 ns

2 x Tsc + 3.0 ns

Tspdo

SPDO Output

2 x Tsc*

*

Tsc is the System Cycle Time. See Table 39 on page 74

C5NP

AC Timing Specifications

85

Fabric Processor Timing The FP timing specifications are shown in Figure 22 and described in Table 50.

Specifications

Figure 22 Fabric Processor Timing Diagram

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 1

FRXCLK

T

frc

FRXCTL

(output)

T

frco

T

frcv

frcz

FRXCTL

(input)

T

frcs

frds

frch

FINn

frdh

FTXCLK

T

ftc

FTXCTL

(output)

T

ftco

T

ftcv

ftcz

FTXCTL

(input)

T

ftch

ftcs

FOUTn

T

ftdo

Table 50 Fabric Processor Timing Description

SYMBOL PARAMETER

MIN

TYP

MAX

UNIT

ns

COMMENT

Tfrc

FRX Cycle Time

FRXCTL Setup

9.0

Tfrcs

4.0

1.5

ns

Utopia2 Mode

All other modes

Tfrch

FRXCTL Hold

0.5

ns

V 04

86

CHAPTER 3: ELECTRICAL SPECIFICATIONS

Table 50 Fabric Processor Timing Description (continued)

SYMBOL PARAMETER

MIN

1.0

1.8

1.3

TYP

MAX

3.4

UNIT

ns

COMMENT

Tfrco

Tfrcz

Tfrcv

Tfrds

FRXCTL Output

FRXCTL Clk to Tri*

FRXCTL Clk to Driven*

FIN Setup

5.5

ns

5.5

ns

4.0

1.5

ns

Utopia2 Mode

All other modes

Tfrdh

Tftc

FIN Hold

0.5

9.0

ns

FTX Cycle Time

FTXCTL Setup

Tftcs

4.0

1.5

Utopia2 Mode

All other modes

Tftch

Tftco

Tftcz

Tftcv

Tftdo

FTXCTL Hold

0.5

1.0

1.7

1.3

1.0

ns

FTXCTL Output

FTXCTL Clk to Tri*

FTXCTL Tri to Driven*

FOUT Output

3.6

5.5

3.6

*

Not fully tested, values based on design/characterization.

BMU Timing The BMU timing specifications are shown in Figure 23 and described in Table 51.

Specifications

The BMU synchronous DRAM interface is PC100-compliant and designed to work with

industry standard SDRAM components with 12 or fewer address lines. The information

below is intended to provide the output, setup, and hold data required to design this

interface without duplicating the transaction waveform diagrams in SDRAM data sheets.

C5NP

AC Timing Specifications

87

Figure 23 BMU Timing Diagram

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 1

MDCLK

M_ctl

T

mc

T

mco

mao

MAn

T

MDn

(output)

T

mdo

T

mdv

mdz

MDn

(input)

T

mdh

mds

Table 51 BMU Timing Description

SYMBOL PARAMETER

MIN

TYP

MAX

UNIT

ns

Tmc

BMU Cycle Time

8.0

1.2

0.5

1.0

1.2

1.8

1.4

Tmco

Tmao

Tmds

Tmdh

Tmdo

Tmdz

Tmdv

BMU Ctrl Output

BMU Addr Output

BMU Data Setup

3.7

3.8

ns

BMU Data Hold

ns

BMU Data Output

BMU Data Clk to Tri*

BMU Data Clk to Driven*

4.0

ns

*

Not fully tested, values based on design/characterization.

Table 52 Signal Groups in BMU Timing Diagrams

SIGNAL GROUP

Control (M_ctl)

Address (MAn)

Data (MDn)

INCLUDED SIGNALS

MBA0, MBA1, MCASX, MRASX, MWEX, MCSX, MDQM

MA0 - MA11

MD0 - MD129, MDECC0 - MDECC8

V 04

88

CHAPTER 3: ELECTRICAL SPECIFICATIONS

TLU Timing Specifications The TLU timing specifications are shown in Figure 24 and described in Table 53.

Figure 24 TLU Timing Diagram

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 1

TCLKI

T_ctl

T

tc

T

tco

TAn

T

tao

TDn

(output)

T

tdo

tdv

T

tdz

TDn

(input)

T

tdh

tds

Table 53 TLU Timing Description

SYMBOL PARAMETER

MIN

7.5

1.2

0.5

1.0

1.2

2.0

1.5

TYP

MAX

UNIT

Ttc

TLU Cycle Time

ns

Ttco

Ttao

Ttds

Ttdh

Ttdo

Ttdz

Ttdv

TLU Ctrl Output

TLU Addr Output

TLU Data Setup

3.4

TLU Data Hold

TLU Data Output

TLU Data Clk to Tri*

TLU Data Clk to Driven*

3.5

*

Not fully tested, values based on design/characterization.

Table 54 Signal Groups in TLU Timing Diagrams

SIGNAL GROUP

Control (T_ctl)

Address (TAn)

INCLUDED SIGNALS

TA18X - TA21X, TCE0X - TCE3X, TWE0X - TWE3X

TA0 - TA21

C5NP

AC Timing Specifications

89

Table 54 Signal Groups in TLU Timing Diagrams

SIGNAL GROUP

INCLUDED SIGNALS

TD0 - TD63

Data (TDn)

QMU Timing The QMU timing specifications are shown in Figure 25 and described in Table 55.

Specifications

Figure 25 QMU Timing Diagram

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 1

QCLK

T

qc

QCMDn

(output)

T

qco

QDATAn

(output)

T

qdv

qdo

T

qdz

QDATAn

(input)

T

qdh

qds

Table 55 QMU Timing Description

SYMBOL PARAMETER

MIN

TYP

MAX

UNIT

COMMENT

Tqc

QMU Cycle Time

2 x Tsc

4 x Tsc

ns

1X Clock Mode

2X Clock Mode

Tqco

QMU Ctrl Output

1.5

1/2 Tsc + 1.0 ns

Tsc + 1.0

1X Clock Mode

2X Clock Mode

Tqds

Tqdh

Tqdo

QMU Data Setup

QMU Data Hold

QMU Data Output

3.1

1.3

1.5

ns

3.5

ns

1/2 Tsc + 1.0 ns

Tsc + 1.0

1X Clock Mode

2X Clock Mode

Tqdz

QMU Data Clk to Tri*

1.1

5.5

ns

V 04

90

CHAPTER 3: ELECTRICAL SPECIFICATIONS

Table 55 QMU Timing Description (continued) (continued)

SYMBOL PARAMETER

Tqdv QMU Data Clk to Driven* 0.6

Not fully tested, values based on design/characterization.

MIN

TYP

MAX

UNIT

COMMENT

5.5

ns

*

Table 56 Signal Groups in QMU Timing Diagrams

SIGNAL GROUP

QCMDn

INCLUDED SIGNALS

QCMD0 - QCMD15, QSFLOW, QXCTRL0, QXCTRL1, QXRQST

QDATA0 - QDATA31, QDPAR

QDATAn

C5NP

C5NPD0-DS/D

Rev 04

Chapter 4

MECHANICAL SPECIFICATIONS

Package Views

The C-5 network processor is an 838 pin (29 pins x 29 pins) Ball Grid Array (BGA) package

as shown in the following illustrations. Table 57 defines the package measurements.

Figure 26 C-5 Network Processor BGA Package Side View

A₄

A₂

A₃

A

A₁

Seating Plane

HiTCE: Green ceramic is thermally matched to FR4 circuit board.

The aluminum lid is electrically connected to the grounded substrate of the C-5 NP.

Neither the lid nor any heat sink connected to the lid should be part of a current-carrying

path. It is acceptable, however, to connect the lid or heatsink to ground if necessary

(through the standoff screws for the heat sink).

V 04

94

CHAPTER 4: MECHANICAL SPECIFICATIONS

Figure 27 C-5 Network Processor BGA Package (Bottom View)

D

D₁

e

AC

AB

AA

Z

e

Y

X

W

V

U

T

S

R

Q

P

E₁

E

O

N

M

L

K

J

I

H

G

F

b

E

D

C

B

A

1

2 3 4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Package Measurements

Table 57 defines the C-5 NP package measurements, providing nominal, minimum, and

maximum sizes where appropriate.

C5NP

Marking Codes

95

Table 57 Package Measurements (Reference Figure 26 and Figure 27 for Symbols)

SYMBOL

DEFINITION

Overall

NOM. (MM)

5.63

MIN. (MM)

MAX. (MM)

A

5.31

5.95

A₁

A₂

A₃

A₄

D

Ball height

0.89

C4 and Die

Body thickness

Lid thickness

Body size

0.88

2.26

2.07

2.53

1.6

37.50

35.56

37.50

35.56

1.27

D₁

E

Ball footprint (X)

Body size

E₁

e

Ball footprint (Y)

Ball pitch

b

Ball diameter

0.89

Marking Codes

Table 58 explains the marking on the C-5 NP.

Table 58 C-5 Network Processor Marking Codes

MARKING (EXPLANATION OF CODES)

Top

Logo/Part#/Country of Origin/Date Code

Bottom

N/A

Pin 1 Marking

Chamfered Corner

Reflow

Typical Reflow Profile for the C-5 Switch Module

1 Follow the guidelines recommended by your solder paste supplier.

Flux requrements must be met for best solderability.

2 The temperature profile should be carefully characterized to ensure uniform

temperature across the board and package.

Solder ball voiding may be affected by ramp rates and dwell times below and above

liquidus.

V 04

96

CHAPTER 4: MECHANICAL SPECIFICATIONS

3 A nitrogen atmosphere is not required, but will make the process more robust. It can

make a difference for marginally solderable PC board pads.

4 Full convection forced air furnaces work best, but IR, Convection/IR, or vapor phase can

be used.

C5NP

C5NPD0-DS/D

Rev 04

INDEX

Channel Processor Interface Signals 30

Channel Processors 22

Channel Processors Physical Interface Signals and Pins

Grouped by Clusters 31

Symbols

10/100 Ethernet (RMII) Configuration 32

10/100 Ethernet Signals 32

Clock and Reference Signals 29

Clock Signals 29

Clock Timing Specifications 73

Configuration

10/100 Ethernet Timing Description 77

10/100 Ethernet Timing Diagram 77

10/100 Ethernet Timing Specifications 76

10/100 Ethernet (RMII) 32

DS1/T1 Framer Interface 32

FibreChannel TBI 35

A

About This Guide 13

Absolute Maximum Ratings 67

AC Timing Specifications 72

Gigabit Ethernet 35

Gigabit Ethernet (GMII) 33

SONET OC-12 Transceiver Interface 37

SONET OC-3 Transceiver Interface 37

Configurations

GMII/TBI Transmit and Receive Pin 34

Connections

B

Block Diagram, C-5 Network Processor 21

BMU SDRAM Interface Signals 47

BMU Signal Groups 89

Power and Ground (Bottom View) 52

CP Timing Specifications 75

BMU Timing Description 89

BMU Timing Diagram 89

BMU Timing Specifications 88

Boundary Scan Cell Types 63

Boundary Scan Description Language 66

Bringup Clock Timing Diagram 70

Buffer Management Unit 24

D

Data Registers

JTAG 63

Data Sheet Description and Organization 13

DC Characteristics 68

Description

Functional 19

C

Description Language

Boundary Scan 66

Descriptions

Signal 27

Diagram

C-5 Network Processor Absolute Maximum Ratings 67

C-5 Network Processor BGA Package, Bottom View 94

C-5 Network Processor BGA Package, Side View 93

C-5 Network Processor Capacitance Data 69

C-5 Network Processor DC Characteristics 68

C-5 Network Processor Power and Thermal Characteristics 70

C-5 NP Channel Processors 22

10/100 Ethernet Timing 77

BMU Timing 89

V 04

98

INDEX

Bringup Clock Timing 70

DS1/DS3 Ethernet Timing 76

Fabric Processor Timing 87

Gigabit Ethernet (TBI) Timing 78

Low Speed Serial Interface Timing 85

MDIO Serial Interface Timing 84

OC-3 Timing 80

Fabric Processor 24

Fabric Processor Interface Signals 44

Fabric Processor Timing Description 87

Fabric Processor Timing Diagram 87

Fabric Processor Timing Specifications 86

Functional Description 19

PCI Timing 82

Pinout 27

PROM Interface 42

G

General System Interface Signal 43

Gigabit Ethernet (GMII) Configuration 33

Gigabit Ethernet (GMII) Signals

PROM Interface Timing 86

QMU Timing 91

Signal Groups in BMU Timing 89

Signal Groups in QMU Timing 92

Signal Groups in TLU Timing 90

System Clock Timing 74

TLU Timing 90

One Cluster Example 34

Gigabit Ethernet (TBI) Timing Description 79, 79

Gigabit Ethernet (TBI) Timing Diagram 78

Gigabit Ethernet and FibreChannel TBI Configuration 35

Gigabit Ethernet and FibreChannel TBI Signals

Example 36

Gigabit GMII Ethernet, TBI and MII Interface Timing Specification 77

GMII/TBI Transmit and Receive Pin Configurations 34

Guide Conventions 14

Diagram, Block

C-5 Network Processor 21

DS1/DS3 Ethernet Timing Description 76

DS1/DS3 Ethernet Timing Diagram 76

DS1/DS3 Timing Specifications 75

DS1/T1 Framer Interface Configuration 32

DS1/T1 Framer Interface Signals 32

I

IDcode Register 64

Instruction Register Instructions 65

E

Electrical Specifications 67

Absolute Maximum Ratings 67

Executive Processor 22

PCI 23

J

JTAG Data Registers 63

JTAG Identification Code and Its Sub-components 65

JTAG Instruction Register 65

JTAG Internal Register Descriptions 63

JTAG Support

PROM Interface 23

Serial Bus Interface 23

System Interface Signals 39

System Interfaces 23

Executive Processor Timing Specifications 82

Pinouts 63

L

F

Low Speed Serial Interface Timing Description 85

Low Speed Serial Interface Timing Diagram 85

Low Speed Serial Interface Timing Specifications 84

LVPECL Specifications 29

Fabric Interface Pin Mapping

Power X Mode 47

PRIZMA Mode 46

Utopia2/Utopia3 ATM Mode 45

Utopia2/Utopia3 PHY Mode 45

LVTTL Specifications 29

C5NP

INDEX

99

Processor, Fabric 24

PROM Interface Diagram 42

PROM Interface Signals 41

PROM Interface Timing Description 86

PROM Interface Timing Diagram 86

PROM Interface Timing Outline 43

PROM Interface Timing Specifications 85

M

MDIO Serial Interface Timing Description 84

MDIO Serial Interface Timing Diagram 84

MDIO Serial Interface Timing Specifications 83

Measurements

C-5 Network Processor 94

Mechanical Specifications 93

Miscellaneous Test Signals for JTAG, Scan, and Internal Test

Routines 53

Q

QMU Signal Groups 92

QMU SRAM Interface Signals 50

QMU Timing Description 91

QMU Timing Diagram 91

QMU Timing Specifications 91

Queue Management Unit 25

N

No Connection Pins 53

O

OC-12 Signals 38

R

OC-12 Timing Description 81

OC-12 Timing Specifications 81

OC-3 Signals 37

Recommended Operating Conditions 67

Register

IDcode 64

JTAG Instruction 65


型号：	C5NPD0-DS/D
厂家：	NXP
描述：	RISC PROCESSOR 时钟外围集成电路
文件：	总100页 (文件大小：2345K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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