CBTL06DP212 [NXP]
CBTL06DP212 provides an additional level of multiplexing of AUX and DDC signals delivering true flexibility and choice.; CBTL06DP212提供了AUX和DDC信号提供真正的灵活性和选择复用的级别。
| 型号： | CBTL06DP212 |
| 厂家： | 
NXP |
| 描述： | CBTL06DP212 provides an additional level of multiplexing of AUX and DDC signals delivering true flexibility and choice. |
| 文件： | 总19页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CBTL06DP212
High-performance DisplayPort Gen2 2 : 1 multiplexer
Rev. 2 — 3 November 2011
Product data sheet
1. General description
CBTL06DP212 is a high performance multi-channel Generation 2 multiplexer meant for
DisplayPort (DP) v1.2, v1.1a or Embedded DisplayPort applications operating at data rate
of 1.62 Gbit/s, 2.7 Gbit/s or 5.4 Gbit/s. It is designed using NXP proprietary
high-bandwidth pass-gate technology and it can be used for 1 : 2 switching or 2 : 1
multiplexing of four high-speed differential AC-coupled DP channels. Further, it is capable
of switching/multiplexing of Hot Plug Detect (HPD) signal as well as Auxiliary (AUX) and
Display Data Channel (DDC) signals. In order to support GPUs/CPUs that have dedicated
AUX and DDC I/Os, CBTL06DP212 provides an additional level of multiplexing of AUX
and DDC signals delivering true flexibility and choice.
A typical application of CBTL06DP212 is on motherboards where one of two GPU
DisplayPort sources needs to be selected to connect to a DisplayPort sink device or
connector. A controller chip selects which path to use by setting a select signal HIGH or
LOW. Due to the bidirectional nature of the signal paths, CBTL06DP212 can also be used
in the reverse topology, e.g., to connect one display source device to one of two display
sink devices or connectors.
2. Features and benefits
1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.2 - 5.4 Gbit/s) signals
4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort
main link signals
1 channel with 4 : 1 multiplexing/switching for AUX or DDC signals
1 channel with 2 : 1 multiplexing/switching for HPD signal
High-bandwidth: 5 GHz at 3 dB
Low insertion loss:
0.5 dB at 100 MHz
3 dB at 5 GHz
Low crosstalk: 35 dB at 3 GHz
Low off-state isolation: 30 dB at 3 GHz
Low return loss: 8 dB at 3 GHz
Very low intra-pair skew (5 ps typical)
Very low inter-pair skew (< 80 ps)
Switch/multiplexer position select CMOS input
DDC and AUX ports tolerant to being pulled to +5 V via 2.2 k resistor
Supports HDMI/DVI incorrect dongle connection
Single 3.3 V power supply
Operation current of 2 mA typical
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
ESD 8 kV HBM, 1 kV CDM
ESD 2 kV HBM, 500 V CDM for control pins
Available in 5 mm 5 mm, 0.5 mm ball pitch TFBGA48 package
3. Applications
Motherboard applications requiring DisplayPort and PCI Express
switching/multiplexing
Docking stations
Notebook computers
Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board
connectors
4. Ordering information
Table 1.
Ordering information
Type number
Solder process
Package
Name
Description
Version
CBTL06DP212EE
Pb-free (SnAgCu
solder compound)
TFBGA48
plastic thin fine-pitch ball grid array package;
48 balls; body 5 5 0.8 mm[1]
SOT918-1
[1] Total height including solder balls after printed circuit board mounting = 1.15 mm maximum.
5. Marking
Table 2.
Package marking
Marking
6D212[1]
Line
A
Description
basic type number
diffusion lot number
manufacturing code:
Z = diffusion site
P = assembly site
G = lead-free
B
xxxxxxx
C
ZPGyyww
yy = year code
ww = week code
[1] Industrial temperature range.
CBTL06DP212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
2 of 18
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
6. Functional diagram
VDD
CBTL06DP212
4
IN1_n+
0
1
IN1_n−
4
OUT_n+
OUT_n−
4
IN2_n+
IN2_n−
AUX1+
00
10
01
11
AUX1−
AUX2+
AUX2−
AUX+ or SCL
AUX+
AUX−
AUX− or SDA
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
0
1
HPD_1
HPD_2
HPDIN
GPU_SEL
DDC_AUX_SEL
TST0
GND
002aaf878
Fig 1. Functional diagram
CBTL06DP212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
3 of 18
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
7. Pinning information
7.1 Pinning
ball A1
index area
CBTL06DP212EE
1
2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
002aaf879
Transparent top view
Fig 2. Pin configuration for TFBGA48
1
2
3
4
5
6
7
8
9
GPU_SEL
A
B
C
D
E
F
VDD
IN1_0−
IN1_1−
IN1_2−
IN1_3+
IN1_3−
OUT_0−
OUT_0+
GND
IN1_0+
IN1_1+
IN1_2+
TST0
IN2_0+
GND
IN2_0−
DDC_AUX
_SEL
OUT_1−
OUT_2−
OUT_3−
OUT_1+
OUT_2+
OUT_3+
GND
IN2_1+
IN2_1−
IN2_2−
IN2_3−
IN2_2+
IN2_3+
G
H
J
GND
AUX−
AUX+
HPD_2
GND
VDD
DDC_CLK2
DDC_DAT2
AUX2+
GND
DDC_CLK1
DDC_DAT1
AUX1+
HPDIN
HPD_1
AUX2−
AUX1−
002aaf943
Transparent top view
Fig 3. Ball mapping
CBTL06DP212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
4 of 18
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
7.2 Pin description
Table 3.
Symbol
GPU_SEL
Pin description
Ball
A1
Type
Description
3.3 V CMOS
single-ended input
Selects between two multiplexer/switch paths. When HIGH, path 2
left-side is connected to its corresponding right-side I/O. When
LOW, path 1 left-side is connected to its corresponding right-side
I/O.
DDC_AUX_SEL C2
3.3 V CMOS
single-ended input
Selects between DDC and AUX paths. When HIGH, the CLK and
DAT I/Os are connected to their respective DDCOUT terminals.
When LOW, the AUX+ and AUX I/Os are connected to their
respective DDCOUT terminals.
TST0
B7
3.3 V CMOS
single-ended input
Test pin for NXP use only. Should be tied to VDD in normal
operation.
IN1_0+
IN1_0
IN1_1+
IN1_1
IN1_2+
IN1_2
IN1_3+
IN1_3
IN2_0+
IN2_0
IN2_1+
IN2_1
IN2_2+
IN2_2
IN2_3+
IN2_3
OUT_0+
OUT_0
OUT_1+
OUT_1
OUT_2+
OUT_2
OUT_3+
OUT_3
AUX1+
AUX1
B4
A4
B5
A5
B6
A6
A8
A9
B8
B9
D8
D9
E8
E9
F8
F9
B2
B1
D2
D1
E2
E1
F2
F1
H9
J9
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 1, left-side.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 2, left-side.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, right-side.
High-speed differential pair for AUX signals, path 1, left-side.
High-speed differential pair for AUX signals, path 2, left-side.
AUX2+
AUX2
H6
J6
DDC_CLK1
DDC_DAT1
H8
J8
Pair of single-ended terminals for DDC clock and data signals,
path 1, left-side.
CBTL06DP212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
5 of 18
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
Table 3.
Symbol
DDC_CLK2
DDC_DAT2
AUX+
Pin description …continued
Ball
H5
Type
Description
differential I/O
differential I/O
differential I/O
differential I/O
single-ended I/O
single-ended I/O
single-ended I/O
power supply
Pair of single-ended terminals for DDC clock and data signals,
path 2, left-side.
J5
H2
High-speed differential pair for AUX or single-ended DDC signals,
right-side.
AUX
H1
HPD_1
HPD_2
HPDIN
VDD
J2
Single ended channel for the HPD signal, path 1, left-side.
Single ended channel for the HPD signal, path 2, left-side.
Single ended channel for the HPD signal, right-side.
3.3 V power supply.
H3
J1
A2, J4
GND
B3, C8, ground
G2, G8,
Ground.
H4, H7
8. Functional description
Refer to Figure 1 “Functional diagram”.
The CBTL06DP212 uses a 3.3 V power supply. All main signal paths are implemented
using high-bandwidth pass-gate technology and are bidirectional. No clock or reset signal
is needed for the multiplexer to function.
The switch position for the main channels is selected using the select signal GPU_SEL.
Additionally, the signal DDC_AUX_SEL selects between AUX and DDC positions for the
DDC / AUX channel. The detailed operation is described in Section 8.1.
8.1 Multiplexer/switch select functions
The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and
DDC_AUX_SEL as described below.
Table 4.
Multiplexer/switch select control for INn and OUTn channels
GPU_SEL
IN1_n
IN2_n
0
1
active; connected to OUT_n
high-impedance
high-impedance
active; connected to OUT_n
Table 5.
Multiplexer/switch select control for HPD channel
GPU_SEL
HPD_1
HPD_2
0
1
active; connected to HPDIN
high-impedance
high-impedance
active; connected to HPDIN
CBTL06DP212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
6 of 18
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
Table 6.
Multiplexer/switch select control for DDC and AUX channels
DDC_AUX_SEL GPU_SEL
AUX1
AUX2
DDC_CLK1,
DDC_DAT1
DDC_CLK2,
DDC_DAT2
0
0
1
1
0
1
0
1
active;
connected to AUX
high-impedance
high-impedance
high-impedance
high-impedance
high-impedance
high-impedance
high-impedance
high-impedance
active;
connected to AUX
high-impedance
high-impedance
active;
connected to AUX
high-impedance
high-impedance
active;
connected to AUX
9. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions
Min
Max
+5
Unit
VDD
supply voltage
0.3
V
Tcase
VESD
case temperature
40
+85
C
V
[1]
[1]
[2]
[2]
electrostatic discharge HBM
voltage
-
-
-
8000
2000
1000
500
HBM; CMOS inputs
V
CDM
V
CDM; CMOS inputs
V
[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -
Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device
Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
10. Recommended operating conditions
Table 8.
Recommended operating conditions
Symbol Parameter
Conditions
Min
3.0
Typ
Max
Unit
V
VDD
VI
supply voltage
input voltage
3.3
3.6
CMOS inputs
HPD inputs
0.3
0.3
0.3
0.3
40
-
-
-
-
-
VDD + 0.3
VDD + 0.3
VDD + 0.3
+2.6
V
[1]
[2]
V
DDC/AUX inputs
other inputs
V
V
Tamb
ambient temperature operating in free air
+85
C
[1] HPD input is tolerant to 5 V input, provided a 1 k series resistor between the voltage source and the pin is
placed in series. See Section 12.1 “Special considerations”.
[2] DDC/AUX inputs are tolerant to 5 V input, provided a 2.2 k series resistor between the voltage source and
the pin is placed in series. See Section 12.1 “Special considerations”.
CBTL06DP212
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
7 of 18
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
11. Characteristics
11.1 General characteristics
Table 9.
General characteristics
Symbol Parameter
Conditions
VDD = 3.3 V
VDD = 3.3 V
Min
Typ
Max
3
Unit
mA
mW
s
IDD
supply current
power consumption
start-up time
-
-
-
2
-
Pcons
tstartup
10
10
supply voltage valid to channel specified
operating characteristics
-
trcfg
reconfiguration time
GPU_SEL or DDC_AUX_SEL state change
to channel specified operating characteristics
-
-
1
s
11.2 DisplayPort channel characteristics
Table 10. DisplayPort channel characteristics
Symbol Parameter Conditions
Min
Typ
Max
Unit
V
VI
input voltage
0.3
-
+2.6
VIC
VID
Ron
DDIL
common-mode input voltage
differential input voltage
ON-state resistance
differential insertion loss
0
-
-
-
-
-
-
-
-
2.0
V
peak-to-peak
-
+1.2
V
VDD = 3.3 V; VI = 2 V; II = 20 mA
channel is ON; f 100 MHz
channel is ON; f = 3.0 GHz
channel is OFF; f 3.0 GHz
f = 100 MHz
6.5
0.5
2.5
30
25
8
-
-
-
-
-
-
dB
dB
dB
dB
dB
DDRL
differential return loss
f = 3.0 GHz
DDNEXT differential near-end crosstalk adjacent channels are ON
f = 100 MHz
f = 3.0 GHz
-
-
-
-
65
35
5
-
-
-
-
dB
dB
B
bandwidth
3.0 dB intercept
GHz
ps
tPD
propagation delay
from left-side port to right-side port
or vice versa
80
tsk(dif)
tsk
differential skew time
skew time
intra-pair
inter-pair
-
-
5
-
-
ps
ps
80
CBTL06DP212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
8 of 18
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
11.3 AUX and DDC ports
Table 11. AUX and DDC port characteristics
Symbol Parameter Conditions
Min
Typ
Max
VDD + 0.3
VDD
Unit
V
VI
input voltage
0.3
-
VO
VIC
VID
tPD
output voltage
no load
AUX
-
-
V
common-mode input voltage
differential input voltage
propagation delay
0
-
-
2.0
V
AUX
-
+1.4
-
V
[1]
from left-side port to right-side
port or vice versa
-
80
ps
[1] Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time.
11.4 HPDIN input, HPD_x outputs
Table 12. HPD input and output characteristics
Symbol
VI
Parameter
Conditions
Min
Typ
Max
Unit
V
input voltage
output voltage
propagation delay
0.3
-
VDD + 0.3
VO
no load
-
-
-
VDD
-
V
[1]
tPD
from HPDIN to HPD_x or vice versa
80
ps
[1] Time from HPDIN changing state to HPD_x changing state. Includes HPD rise/fall time.
11.5 GPU_SEL and DDC_AUX_SEL inputs
Table 13. GPU_SEL and DDC_AUX_SEL input characteristics
Symbol
VIH
Parameter
Conditions
Min
Typ
Max
-
Unit
V
HIGH-level input voltage
LOW-level input voltage
input leakage current
2.0
-
-
-
VIL
-
-
0.8
10
V
ILI
VDD = 3.6 V; 0.3 V VI 3.9 V
A
CBTL06DP212
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
9 of 18
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
12. Application information
CBTL06DP212
IN1_n+
IN1_n−
OUT_n+
2 : 1
MUX
OUT_n−
IN2_n+
IN2_n−
GND
100 kΩ
AUX1+
AUX1−
GND
100 kΩ
100 kΩ
V
DD
AUX2+
AUX+
AUX−
AUX2−
4 : 1
MUX
+3.3 V
100 kΩ
2 kΩ
V
DD
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
HPD_1
HPD_2
HPDIN
2 : 1
MUX
GPU2_DP++ SOURCE
DDC_AUX_SEL
GPU_SEL
002aaf944
Fig 4. Application diagram
12.1 Special considerations
Certain cable or dongle misplug scenarios make it possible for a 5 V input condition to
occur on pins AUX+ and AUX, as well as HPDIN. When AUX+ and AUX are connected
through a minimum of 2.2 k each, the CBTL06DP212 will sink current but will not be
damaged. Similarly, HPDIN may be connected to 5 V via at least a 1 k resistor. (Correct
functional operation to specification is not expected in these scenarios.) The latter also
prevents the HPDIN input from loading down the system HPD signal when power to the
CBTL06DP212 is off.
CBTL06DP212
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
10 of 18
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
13. Package outline
TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 5 x 5 x 0.8 mm
SOT918-1
B
A
D
ball A1
index area
A
2
E
A
A
1
detail X
e
1
C
M
M
∅ v
∅ w
C
C
A
B
e
b
y
y
C
1
J
H
G
F
e
2
E
D
C
B
A
e
ball A1
index area
1
2
3
4
5
6
7
8
9
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
A
2
b
D
E
e
e
1
e
2
v
w
y
y
1
max
0.25 0.90 0.35
0.15 0.75 0.25
5.1
4.9
5.1
4.9
mm
1.15
0.5
4
4
0.15 0.05 0.08
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
05-09-21
05-10-13
SOT918-1
- - -
MO-195
- - -
Fig 5. Package outline TFBGA48 (SOT918-1)
CBTL06DP212
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
11 of 18
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
CBTL06DP212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
12 of 18
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 6) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 14 and 15
Table 14. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 15. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 6.
CBTL06DP212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
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CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 6. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 16. Abbreviations
Acronym
AUX
CDM
CMOS
CPU
DP
Description
Auxiliary channel (in DisplayPort definition)
Charged-Device Model
Complementary Metal-Oxide Semiconductor
Central Processing Unit
DisplayPort
DVI
Digital Video Interface
ESD
GPU
HBM
HDMI
I/O
ElectroStatic Discharge
Graphics Processor Unit
Human Body Model
High-Definition Multimedia Interface
Input/Output
PCI
Peripheral Component Interconnect
CBTL06DP212
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Product data sheet
Rev. 2 — 3 November 2011
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CBTL06DP212
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High-performance DisplayPort Gen2 2 : 1 multiplexer
16. Revision history
Table 17. Revision history
Document ID
Release date
20111103
Data sheet status
Change notice
Supersedes
CBTL06DP212 v.2
Modifications:
Product data sheet
-
CBTL06DP212 v.1
• Table 2 “Package marking”: Line A marking corrected from “6DP212” to “6D212”
20110221 Product data sheet
CBTL06DP212 v.1
-
-
CBTL06DP212
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Product data sheet
Rev. 2 — 3 November 2011
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CBTL06DP212
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High-performance DisplayPort Gen2 2 : 1 multiplexer
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
17.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
CBTL06DP212
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
16 of 18
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
17.4 Licenses
Purchase of NXP ICs with HDMI technology
Use of an NXP IC with HDMI technology in equipment that complies with
the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.
Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:
admin@hdmi.org.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
17.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
CBTL06DP212
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 November 2011
17 of 18
CBTL06DP212
NXP Semiconductors
High-performance DisplayPort Gen2 2 : 1 multiplexer
19. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
8
8.1
9
Functional description . . . . . . . . . . . . . . . . . . . 6
Multiplexer/switch select functions . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
10
11
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 8
General characteristics. . . . . . . . . . . . . . . . . . . 8
DisplayPort channel characteristics . . . . . . . . . 8
AUX and DDC ports . . . . . . . . . . . . . . . . . . . . . 9
HPDIN input, HPD_x outputs . . . . . . . . . . . . . . 9
GPU_SEL and DDC_AUX_SEL inputs. . . . . . . 9
11.1
11.2
11.3
11.4
11.5
12
12.1
13
Application information. . . . . . . . . . . . . . . . . . 10
Special considerations . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
14
Soldering of SMD packages . . . . . . . . . . . . . . 12
Introduction to soldering . . . . . . . . . . . . . . . . . 12
Wave and reflow soldering . . . . . . . . . . . . . . . 12
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 12
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 13
14.1
14.2
14.3
14.4
15
16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
17.1
17.2
17.3
17.4
17.5
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 November 2011
Document identifier: CBTL06DP212
Mouser Electronics
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