CD3207BB [NXP]
7-bit Futurebus transceiver; 7位FUTUREBUS收发
| 型号： | CD3207BB |
| 厂家： | 
NXP |
| 描述： | 7-bit Futurebus transceiver |
| 文件： | 总14页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
FB2041
7-bit Futurebus+ transceiver
Product specification
IC19 Data Handbook
1995 May 25
Philips
Semiconductors
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
DESCRIPTION
• Allows incident wave switching in heavily loaded backplane buses
The FB2041 is a 7-bit bidirectional BTL transceiver and is intended
to provide the electrical interface to a high performance wired-OR
bus. The FB2041 is an inverting transceiver.
• Reduced BTL voltage swing produces less noise and reduces
power consumption
• Built-in precision band-gap reference provides accurate receiver
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
thresholds and improved noise immunity
• Compatible with IEEE Futurebus+ or proprietary BTL backplanes
• Controlled output ramp and multiple GND pins minimize ground
bounce
FEATURES
• Each BTL driver has a dedicated Bus GND for a signal return
• Glitch-free power up/power down operation
• 7-bit BTL transceiver
• Separate I/O on TTL A-port
• Inverting
• Low I current
CC
• Tight output skew
• Three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
• Supports live insertion
arrangement
• Pins for the optional JTAG boundary scan function are provided
• High density packaging in plastic Quad Flatpack
• Drives heavily loaded backplanes with equivalent load
impedances down to 10Ω.
• High drive 100mA BTL open collector drivers on B-port
QUICK REFERENCE DATA
SYMBOL
PARAMETER
TYPICAL
3.7
2.7
3.4
3.2
6
UNIT
t
t
t
t
Propagation delay
AIn to Bn
PLH
PHL
PLH
PHL
ns
Propagation delay
Bn to AOn
ns
C
Output capacitance (B0 - B6 only)
Output current (B0 - B6 only)
pF
OB
I
OL
100
19
mA
Standby
AIn to Bn (outputs Low or High)
Bn to AOn (outputs Low)
Bn to AOn (outputs High)
40
I
Supply Current
mA
CC
22
19
ORDERING INFORMATION
PACKAGE
COMMERCIAL RANGE
= 5V±10%; T = 0 to +70°C
INDUSTRIAL RANGE
DWG
No.
V
CC
V
CC
= 5V±10%; T = -40 to +85°C
amb
amb
52-pin Plastic Quad Flatpack
FB2041BB
CD3207BB
SOT379-1
2
1995 May 25
853-1561 15279
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
LOGIC GND
AI1
BUS GND
1
2
3
4
5
6
7
39
38 B1
AI2
37 BUS GND
36 B2
AO2
7-Bit Transceiver
FB2041
35
34
33
LOGIC GND
BUS GND
AO3
B3
LOGIC GND
BUS GND
AI3
AI4
B4
8
32
31
30
29
28
52-lead PQFP
9
BUS GND
B5
10
11
12
AO4
LOGIC GND
AO5
BUS GND
B6
LOGIC GND 13
27 BUS GND
14 15 16 17 18 19 20 21 22 23 24 25 26
The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced
capacitive loading by placing an internal series diode on the drivers.
BTL also provides incident wave switching, a necessity for high
performance backplanes.
To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
5V level while V is Low. If live insertion is not a requirement, the
CC
BIAS V pin should be tied to a V pin.
CC
The LOGIC GND and BUS GND pins are isolated in the package to
minimize noise coupling between the BTL and TTL sides. These
pins should be tied to a common ground external to the package.
There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement. The TTL/BTL output drivers for bit 0 are enabled with
OEA1/OEB1, output drivers for bits 1–2–3 are enabled with
OEA2/OEB2 and output drivers for bits 4–5–6 are enabled with
OEA3/OEB3.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble-shoot.
The A-port operates at TTL levels with separate I/O. The 3-state
A-port drivers are enabled when OEAn goes High after an extra 6ns
delay which is built in to provide a break-before-make function.
When OEAn goes Low, A-port drivers become High impedance
without any extra delay. During power on/off cycles, the A-port
The LOGIC V and BUS V pins are also isolated internally to
CC
CC
minimize noise and may be externally decoupled separately or
simply tied together.
drivers are held in a High impedance state when V is below 2.5V.
CC
JTAG boundary scan functionality is provided as an option with
signals TMS, TCK, TDI and TDO. When this option is not present,
TMS and TCK are no-connects (no bond wires) and TDI and TDO
are shorted together internally.
The B-port has an output enable, OEB0, which affects all seven
drivers. When OEB0 is High and OEBn is Low the output driver will
be enabled. When OEB0 is Low or if OEBn is High, the B-port
drivers will be inactive and at the level of the backplane signal.
3
1995 May 25
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
PIN DESCRIPTION
SYMBOL
AI0 – AI6
AO0 – AO6
B0 – B6
OEB0
PIN NUMBER
TYPE
Input
Output
I/O
NAME AND FUNCTION
51, 2, 3, 8, 9, 14, 18
Data inputs (TTL)
50, 52, 4, 6, 10, 12, 16
3-state outputs (TTL)
40, 38, 36, 34, 32, 30, 28
Data inputs/Open Collector outputs, High current drive (BTL)
Enables the Bn outputs when High
Enables the B0 output when Low
Enables the B1 – B3 outputs when Low
Enables the B4 – B6 outputs when Low
Enables the A0 outputs when High
Enables the A1 – A3 outputs when High
Enables the A4 – A6 outputs when High
Bus ground (0V)
46
Input
Input
Input
Input
Input
Input
Input
GND
GND
Power
Power
Power
Input
Input
Input
Output
OEB1
45
OEB2
25
OEB3
26
OEA1
47
OEA2
20
OEA3
24
BUS GND
LOGIC GND
41, 39, 37, 35, 33, 31, 29, 27
1, 5, 7, 11, 13, 15, 19
Logic ground (0V)
BUS V
23, 43
17, 49
48
Positive supply voltage
CC
LOGIC V
Positive supply voltage
CC
BIAS V
TMS
TCK
Positive supply voltage
42
Test Mode Select (no-connect)
Test Clock (no-connect)
44
TDI
22
Test Data In (shorted to TDO)
Test Data Out (TDI)
TDO
21
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.
SYMBOL
PARAMETER
RATING
UNIT
V
Supply voltage
Input voltage
-0.5 to +7.0
-1.2 to +7.0
-1.2 to +5.5
-18 to +5.0
V
V
CC
AI0 – AI6, OEB0, OEBn, OEAn
V
IN
B0 – B6
I
IN
Input current
mA
V
V
OUT
Voltage applied to output in High output state
Current applied to output in
Low output state
-0.5 to +V
48
CC
AO0 – AO6
B0 – B6
mA
I
OUT
200
T
STG
Storage temperature
-65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
COMMERCIAL LIMITS
INDUSTRIAL LIMITS
V
CC
= 5V±10%;
V
CC
= 5V±10%;
PARAMETER
SYMBOL
UNIT
T
amb
= 0 to +70°C
T
amb
= -40 to +85°C
MIN
4.5
TYP
MAX
MIN
4.5
TYP
MAX
V
Supply voltage
5.0
5.5
5.0
5.5
V
V
CC
Except B0–B6
B0 – B6
2.0
2.0
V
High-level input voltage
IH
1.62
1.55
1.62
1.55
Except B0–B6
B0 – B6
0.8
1.47
-18
-3
0.8
1.47
-18
-3
V
V
Low-level input voltage
IL
I
IK
Input clamp current
mA
mA
mA
I
High-level output current
AO0 – AO6
AO0 – AO6
B0 – B6
OH
24
24
I
OL
Low-level output current
100
7
100
7
C
Output capacitance on B port
6
6
pF
OB
T
amb
Operating free-air temperature range
0
+70
-40
+85
°C
4
1995 May 25
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
FUNCTION TABLE
MODE
AIn
L
INPUTS
OUTPUTS
Bn*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
OEB0 OEB1 OEB2 OEB3 OEA1 OEA2 OEA3
AOn
Z
Z
L
Bn*
H**
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
AIn to Bn
H
L
L
L
L
H
H
L
H
H
L
H
H
L
H**
L
H
L
L
L
L
H
Z
Z
L
L
X
X
X
X
L
X
X
X
X
X
X
X
X
L
H**
L
AI0 to B0
H
L
L
L
L
L
L
H
H
L
H
H
L
H
H
L
H**
L
H
L
L
H
Z
Z
L
X
X
X
X
X
X
X
X
X
H
H
X
X
X
X
H
H
X
X
H
H
X
X
H
H
X
X
H
H
X
X
X
X
H**
L
AI1 – AI3 to B1 – B3
H
L
L
L
L
L
L
H
H
L
H
H
L
H
H
L
H**
L
H
L
L
H
Z
Z
L
X
X
X
X
X
H
X
H
X
X
X
H
H
X
X
H
H
X
X
H
H
X
X
H
H
X
X
X
X
H**
L
AI4 – AI6 to B4 – B6
Disable Bn outputs
H
L
L
L
L
L
L
H
H
X
X
X
X
X
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
H
H
X
X
X
X
X
H
H
H
H
X
X
X
X
H
H
H
H
X
X
X
X
L
H
H
X
X
X
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
H
H
H
L
H**
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
H
L
X
H
X
X
H
X
X
H
H
X
X
H
H
X
X
H
H
X
X
H
H
X
X
X
X
H**
H**
H**
H**
H**
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
X
X
X
H
H
H
L
Disable B0 outputs
X
Disable B1 – B3 outputs
Disable B4 – B6 outputs
X
X
L
Bn to AOn
H
L
L
X
X
L
H
L
H
L
H
L
B0 to AO0
H
L
L
X
X
L
H
L
H
L
H
L
B1 – B3 to AO1 – AO3
B4 – B6 to AO4 – AO6
H
L
L
X
X
L
H
L
H
L
H
L
H
L
L
X
X
X
X
X
X
H
L
H
Disable AOn outputs
X
Z
Z
Z
Z
Disable AO0 outputs
X
L
X
L
X
X
L
X
Disable AO1 – AO3 outputs
Disable AO4 – AO6 outputs
X
X
X
X
X
X
X
NOTES:
H
L
X
Z
—
=
=
=
=
=
High voltage level
Low voltage level
Don’t care
High-impedance (OFF) state
Input not externally driven
Z
—
=
=
High-impedance (OFF) state
Input not externally driven
H** = Goes to level of pull-up voltage
B*
=
Precaution should be taken to ensure B inputs do not float.
If they do, they are equal to Low state.
H** = Goes to level of pull-up voltage
B*
=
Precaution should be taken to ensure B inputs do not float.
If they do, they are equal to Low state.
5
1995 May 25
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
LOGIC DIAGRAM
46
OEB0
45
OEB1
47
OEA1
40
B0
51
AI0
50
AO0
25
OEB2
20
OEA2
38
B1
2
AI1
52
AO1
36
34
B2
B3
3
AI2
4
AO2
TTL
Levels
BTL
Levels
8
AI3
6
AO3
26
OEB3
24
OEA3
32
B4
9
AI4
10
AO4
30
28
B5
B6
14
AI5
12
AO5
18
AI6
16
AO6
42
TMS
44
TCK
TDI
TDO
(Future JTAG Boundary Scan option)
22
21
LOGIC V
=
=
=
=
=
17, 49
1, 5, 7, 11, 13, 15, 19
23, 43
27, 29, 31, 33, 35, 37, 39, 41
48
CC
LOGIC GND
BUS V
CC
BUS GND
BIAS V
SG00071
6
1995 May 25
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
LIVE INSERTION SPECIFICATIONS
LIMITS
TYP
SYMBOL
PARAMETER
UNIT
MAX
MIN
V
Bias pin voltage
V
V
= 0 to 5.25V, Bn = 0 to 2.0V
= 0 to 4.75V, Bn = 0 to 2.0V,
4.5
5.5
V
BIASV
CC
CC
1
mA
Bias V = 4.5 to 5.5V
I
Bias pin DC current
BIASV
V
CC
= 4.5 to 5.5V, Bn = 0 to 2.0V,
10
µA
Bias V = 4.5 to 5.5V
V
Bus voltage during prebias
Fall current during prebias
Rise current during prebias
B0 – B8 = 0V, Bias V = 5.0V
B0 – B8 = 2V, Bias V = 4.5 to 5.5V
B0 – B8 = 1V, Bias V = 4.5 to 5.5V
1.62
1
2.1
V
Bn
I
µA
µA
LM
I
-1
HM
Peak bus current during
insertion
V
= 0 to 5.25V, B0 – B8 = 0 to 2.0V,
CC
I
Bn
PEAK
10
mA
Bias V = 4.5 to 5.5V, OEB0 = 0.8V, t = 2ns
r
V
CC
V
CC
V
CC
= 0 to 5.25V, OEB0 = 0.8V
= 0 to 2.2V, OEB0 = 0 to 5V
= 5.0V
100
100
I
OFF
Power up current
µA
OL
t
Input glitch rejection
1.0
1.35
ns
GR
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
TYP
MAX
100
I
High level output current B0 – B6
Power-off output current B0 – B6
High-level output
V
V
= MAX, V = MAX, V = MIN, V = 2.1V
µA
µA
OH
CC
IL
IH
OH
I
= 0.0V, V = MAX, V = MIN, V = 2.1V
100
OFF
CC
IL
IH
OH
3
3
V
OH
AO0 – AO6
V
CC
= MIN, V = MAX, V = MIN, I = -3mA
2.5
.75
2.85
V
IL
IH
OH
voltage
AO0 – AO6
V
CC
V
CC
V
CC
V
CC
= MIN, V = MAX, V = MIN, I = 24mA
0.33
1.0
0.5
1.10
1.15
-1.2
IL
IH
OL
V
OL
Low-level output voltage B0 – B6
= MIN, V = MAX, V = MIN, I = 80mA
IL IH OL
V
= MIN, V = MAX, V = MIN, I = 100mA
IL
IH
OL
V
IK
Input clamp voltage
= MIN, I = I
IK
V
I
Input current at
maximum input voltage
OEB0, OEBn,
OEAn, AI0 – AI6
I
I
V
CC
= MAX, V = GND or 5.5V
±50
µA
I
OEB0, OEBn,
OEAn, AI0 – AI6
V
V
= MAX, V = 2.7V
20
I
High-level input current
Low-level input current
CC
I
µA
µA
IH
B0 – B6
= MAX, V = 2.1V
100
CC
I
OEB0, OEBn,
OEAn, AI0 – AI6
-20
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX, V = 0.5V
I
I
IL
B0 – B6
= MAX, V = 0.75V
-100
50
I
I
Off-state output current
Off-state output current
Output current
AO0 – AO6
AO0 – AO6
AO0 – AO6 only
= MAX, V = 2.7V
µA
µA
OZH
O
I
= MAX, V = 0.5V
-50
-150
30
OZL
O
I
= MAX
-30
-55
19
40
22
19
mA
O
I
I
I
I
(standby)
AIn to Bn
Bn to AOn
Bn to AOn
= MAX
CCZ
= MAX, outputs Low or High
= MAX, outputs Low
= MAX, outputs High
60
CCB,
CCA,
CCA,
I
Supply current (total)
mA
CC
35
35
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
A
3. Due to test equipment limitations, actual test conditions are V = 1.8V and V = 1.3V for the B side.
IH
IL
7
1995 May 25
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
AC ELECTRICAL CHARACTERISTICS (Commercial)
TEST
A PORT LIMITS
T
V
= 0 to 70°C,
= 5V±10%,
amb
CC
T
= +25°C, V = 5V,
SYMBOL
PARAMETER
UNIT
amb
L
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L
L L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay,
Bn to AOn
1.8
1.6
3.4
3.2
5.0
4.9
1.6
1.6
5.5
5.0
PLH
PHL
Waveform 1, 2
Waveform 4, 5
Waveform 4, 5
ns
ns
ns
ns
ns
t
Output enable time,
OEA to AOn
2.2
2.0
5.0
4.0
6.5
6.5
2.0
1.8
10.0
8.0
PZH
t
PZL
t
Output disable time,
OEA to AOn
1.5
1.8
3.3
3.0
4.8
5.0
1.2
1.5
5.0
5.5
PHZ
t
PLZ
t
t
Transition time, AOn Port
(10% to 90% or 90% to 10%)
Test Circuit and
Waveforms
1.5
1.5
2.2
2.4
3.0
3.0
1.5
1.5
3.5
3.5
TLH
THL
Output skew between receivers
t
(o)
Waveform 3
0.4
1.0
1.0
SK
1
in same package
B PORT LIMITS
T
= 0 to 70°C,
= 5V±10%,
amb
CC
SYMBOL
T
= +25°C, V = 5V,
CC
amb
V
PARAMETER
TEST CONDITION
UNIT
C
= 30pF, R = 9Ω
D
U
C
= 30pF, R = 9Ω
D
U
t
t
Propagation delay,
AIn to Bn
2.4
1.5
3.7
2.7
4.9
4.4
1.9
1.5
5.7
5.0
PLH
PHL
Waveform 1, 2
Waveform 2
Waveform 1
ns
ns
ns
ns
t
t
Enable/disable time,
OEB0 to Bn
2.4
1.9
3.7
3.5
4.9
4.9
1.9
1.8
6.4
5.4
PLH
PHL
t
t
Enable/disable time,
OEB1 to Bn
2.4
1.9
4.0
3.6
5.5
5.5
1.9
2.5
5.9
5.9
PLH
PHL
t
t
Transition time, Bn Port
(1.3V to 1.8V)
Test Circuit and
Waveforms
1.0
0.5
1.4
1.1
3.0
3.0
1.0
0.5
3.0
3.0
TLH
THL
Output skew between drivers in
same package
t
(o)
Waveform 3
TEST CONDITION
Waveform 1, 2
0.3
1.0
1.0
ns
UNIT
ns
SK
1
SYMBOL
PARAMETER
R
= 16.5Ω
R = 16.5Ω
U
U
t
t
Propagation delay,
AIn to Bn
2.5
1.6
3.8
2.8
5.0
4.5
2.0
1.6
5.8
5.1
PLH
PHL
t
t
Enable/disable time,
OEB0 to Bn
2.5
2.0
3.8
3.6
5.0
5.0
2.0
1.9
6.5
5.5
PLH
PHL
Waveform 2
Waveform 1
ns
ns
ns
ns
t
t
Enable/disable time,
OEB1 to Bn
2.5
2.0
4.1
3.7
5.6
5.6
2.0
2.6
6.0
6.0
PLH
PHL
t
t
Transition time, Bn Port
(1.3V to 1.8V)
Test Circuit and
Waveforms
1.0
0.5
1.5
1.1
3.0
3.0
1.0
0.5
3.0
3.0
TLH
THL
Output skew between drivers in
t
(o)
Waveform 3
0.3
1.0
1.0
SK
1
same package
NOTES:
1.
t
actual – t actual for any data input to output path compared to any other data input to output path where N and M are either LH or
PN PM
HL. Skew times are valid only under same test conditions (temperature, V , loading, etc.).
CC
8
1995 May 25
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
AC ELECTRICAL CHARACTERISTICS (Industrial)
TEST
A PORT LIMITS
T
amb
= -40 to +85°C,
T
= +25°C, V = 5V,
CC
amb
L L
V
= 5V±10%,
SYMBOL
PARAMETER
UNIT
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay,
Bn to AOn
1.8
1.6
3.4
3.2
5.0
4.9
1.6
1.6
5.5
5.5
PLH
PHL
Waveform 1, 2
Waveform 4, 5
Waveform 4, 5
ns
ns
ns
ns
ns
t
Output enable time,
OEA to AOn
2.2
2.0
5.0
4.0
6.5
6.5
1.5
1.5
8.0
8.0
PZH
t
PZL
t
Output disable time,
OEA to AOn
1.5
1.5
3.3
3.0
4.8
5.0
0.8
1.2
6.0
6.0
PHZ
t
PLZ
t
t
Transition time, AOn Port
(10% to 90% or 90% to 10%)
Test Circuit and
Waveforms
1.5
1.5
2.2
2.4
3.0
3.0
1.5
1.5
3.5
3.5
TLH
THL
Output skew between receivers
t
(o)
Waveform 3
0.4
1.0
1.0
SK
1
in same package
B PORT LIMITS
T
= -40 to +85°C,
amb
V
D
SYMBOL
PARAMETER
TEST CONDITION
UNIT
T
= +25°C, V = 5V,
CC
amb
= 5V±10%,
CC
C
= 30pF, R = 9Ω
D
U
C
= 30pF, R = 9Ω
U
t
t
Propagation delay,
AIn to Bn
2.4
1.5
3.7
2.7
4.9
4.4
1.9
1.5
5.9
5.0
PLH
PHL
Waveform 1, 2
Waveform 2
Waveform 1
ns
ns
ns
ns
t
t
Enable/disable time,
OEB0 to Bn
2.4
1.9
3.7
3.5
4.9
4.9
1.9
1.8
6.4
5.9
PLH
PHL
t
t
Enable/disable time,
OEB1 to Bn
2.4
1.9
4.0
3.6
5.5
5.5
1.9
1.5
6.8
6.8
PLH
PHL
t
t
Transition time, Bn Port
(1.3V to 1.8V)
Test Circuit and
Waveforms
1.0
0.5
1.4
1.1
3.0
3.0
1.0
0.5
3.0
3.0
TLH
THL
Output skew between drivers in
same package
t
(o)
Waveform 3
TEST CONDITION
Waveform 1, 2
0.3
1.0
1.0
ns
UNIT
ns
SK
1
SYMBOL
PARAMETER
R
= 16.5Ω
R = 16.5Ω
U
U
t
t
Propagation delay,
AIn to Bn
2.5
1.6
3.8
2.8
5.0
4.5
2.0
1.6
6.0
5.1
PLH
PHL
t
t
Enable/disable time,
OEB0 to Bn
2.5
2.0
3.8
3.6
5.0
5.0
2.0
1.9
6.5
6.0
PLH
PHL
Waveform 2
Waveform 1
ns
ns
ns
ns
t
t
Enable/disable time,
OEB1 to Bn
2.5
2.0
4.1
3.7
5.5
5.5
2.0
1.6
6.9
6.9
PLH
PHL
t
t
Transition time, Bn Port
(1.3V to 1.8V)
Test Circuit and
Waveforms
1.0
0.5
1.5
1.1
3.0
3.0
1.0
0.5
3.0
3.0
TLH
THL
Output skew between drivers in
t
(o)
Waveform 3
0.3
1.0
1.0
SK
1
same package
NOTES:
1.
t
actual – t actual for any data input to output path compared to any other data input to output path where N and M are either LH or
PN PM
HL. Skew times are valid only under same test conditions (temperature, V , loading, etc.).
CC
9
1995 May 25
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
AC WAVEFORMS
AIn, Bn
OEB0
V
t
V
V
V
M
AIn, Bn or Bn
OEBn
M
M
M
t
t
PHL
PLH
PHL
t
PLH
V
V
M
AOn, Bn
V
V
M
M
M
AOn or Bn
Waveform 1. Propagation Delay for Data
or Output Enable to Output
Waveform 2. Propagation Delay for Data
or Output Enable to Output
V
t
AIn, Bn
M
(o)
SK
AOn, Bn
V
M
V
t
V
M
Waveform 3. Output Skews
M
OEAn
AOn
V
V
OEA
AOn
M
M
PZL
t
t
t
PLZ
PZH
PHZ
V
-0.3V
OV
OH
V
M
V
V
+0.3V
M
OL
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
NOTE: V = 1.55V for Bn, V = 1.5V for all others.
SG00079
M
M
10
1995 May 25
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
TEST CIRCUIT AND WAVEFORMS
V
CC
t
W
V
IN
BIAS
V
90%
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
R
L
10%
10%
V
V
OUT
IN
LOW V
PULSE
GENERATOR
D.U.T.
t
t
(t )
r
t
(t )
f
TLH
THL
TLH
R
C
R
L
T
L
(t )
t
(t )
r
THL
f
V
IN
90%
90%
POSITIVE
PULSE
V
V
M
M
10%
10%
LOW V
t
W
Test Circuit for 3-State Outputs on A Port
SWITCH POSITION
V
= 1.55V for Bn, V = 1.5V for all others.
M
M
Input Pulse Definitions
TEST
SWITCH
t
t
closed
open
PLZ, PZL
All other
INPUT PULSE REQUIREMENTS
Family
FB+
Amplitude Low V
Rep. Rate
t
t
t
THL
W
TLH
2.0V (for R = 9 Ω)
V
U
CC
500ns 2.5ns 2.5ns
500ns 2.5ns 2.5ns
A Port
B Port
3.0V
2.0V
0.0V
1.0V
1MHz
1MHz
2.1V (for R = 16.5 Ω)
BIAS
V
U
R
U
V
V
IN
OUT
PULSE
GENERATOR
D.U.T.
R
T
C
D
DEFINITIONS:
R
C
=
=
Load Resistor; see AC CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
L
L
Test Circuit for Outputs on B Port
R
C
=
=
Termination resistance should be equal to Z
Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
of pulse generators.
T
D
OUT
R
=
Pull up resistor; see AC CHARACTERISTICS for value.
U
SG00059
11
1995 May 25
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
SOT379-1
12
1995 May 25
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
NOTES
13
1995 May 25
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 08-98
Document order number:
Philips
Semiconductors
相关型号：
CD32C1-3.579545MHZ
Parallel - Fundamental Quartz Crystal, 3.579545MHz Nom, HC49/US, SMD, 2 PIN
CALIBER
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