CLRC66103HN_技术文档

CLRC661

High performance NFC frontend CLRC661 plus

Rev. 3.7 — 23 June 2021

Product data sheet

456937

COMPANY PUBLIC

1 General description

CLRC661, the high performance multiprotocol NFC frontend.

The CLRC661 multiprotocol NFC frontend IC supports the following operating modes

• Read/write mode supporting ISO/IEC 14443 type A and MIFARE Classic

communication mode

• Read/write mode supporting ISO/IEC 15693

• Read/write mode supporting ICODE EPC UID/ EPC OTP

• Read/write mode supporting ISO/IEC 18000-3 mode 3/ EPC Class-1 HF

The CLRC661’s internal transmitter is able to drive a reader/writer antenna designed

to communicate with ISO/IEC 14443A and MIFARE Classic IC-based cards and

transponders without additional active circuitry. The digital module manages the complete

ISO/IEC 14443A framing and error detection functionality (parity and CRC).

The CLRC661 supports the communication of MIFARE Classic with 1K memory, MIFARE

Classic with 4K memory, MIFARE Ultralight, MIFARE Ultralight C, MIFARE Plus, and

MIFARE DESFire products. The CLRC661 supports higher transfer speeds of the

MIFARE family up to 848 kbit/s in both directions.

The CLRC661 supports the vicinity protocol according to ISO/IEC15693, EPC UID and

ISO/IEC 18000-3 mode 3/ EPC Class-1 HF.

The following host interfaces are supported:

• Serial Peripheral Interface (SPI)

• Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply)

• I²C-bus interface (two versions are implemented: I2C and I2CL)

The CLRC661 supports the connection of a secure access module (SAM). A dedicated

separate I2C interface is implemented for a connection of the SAM. The SAM can be

used for high secure key storage and acts as a very performant cryptocoprocessor. A

dedicated SAM is available for connection to the CLRC661.

In this document, the term „MIFARE Classic card“ refers to a MIFARE Classic IC-based

contactless card.

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CLRC661

High performance NFC frontend CLRC661 plus

2 Features and benefits

• Includes NXP ISO/IEC14443-A intellectual property licensing rights

• High performance multiprotocol NFC frontend for transfer speed up to 848 kbit/s

• Supports ISO/IEC 14443 A

• MIFARE Classic encryption supported by hardware

• Allows reading cards based on MIFARE Ultralight, MIFARE Classic with 1K memory,

MIFARE Classic with 4K memory, MIFARE DESFire EV1, MIFARE DESFire EV2 and

MIFARE Plus ICs

• Supports ISO/IEC15693, ICODE EPC UID, and ISO/IEC 18000-3 mode 3/ EPC

Class-1 HF

• Low-Power Card Detection

• Supported host interfaces:

– SPI up to 10 Mbit/s

– I²C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mode plus

– RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin voltage

supply

• Separate I²C-bus interface for connection of a secure access module (SAM)

• FIFO buffer with size of 512 bytes for highest transaction performance

• Flexible and efficient power-saving modes including hard power down, standby, and

low-power card detection

• Cost saving by integrated PLL to derive system clock from 27.12 MHz RF quartz crystal

• 2.5 V to 5.5 V power supply

• Up to 8 free programmable input/output pins

• Typical operating distance in read/write mode for communication to a ISO/IEC 14443

type A and MIFARE Classic card up to 12 cm, depending on the antenna size and

tuning

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3 Applications

• ISO/IEC 14443 reader

• ISO/IEC 15693 reader

• Reader for MIFARE product-based cards

• Reader for NTAG and NTAG 5 based products

• Gaming

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4 Quick reference data

Table 1.ꢀQuick reference data CLRC66103HN

Symbol

V_DD

Parameter

Conditions

Min

2.5

-

Typ

5.0

8

Max

5.5

V_DD

5.5

40

Unit

V

supply voltage

[1]

[2]

V_DD(PVDD)

V_DD(TVDD)

I_pd

PVDD supply voltage

TVDD supply voltage

power-down current

supply current

V

PDOWN pin pulled HIGH

nA

mA

I_DD

-

17

20

I_DD(TVDD)

TVDD supply current

recommended operation

absolute limiting value

-

180

-

350

500

-

T_amb

operating ambient temperature device mounted on PCB which

allows sufficient heat dissipation for

the actual power dissipation of the

device

-40

+25

+105 °C

T_stg

storage temperature

no supply voltage applied

-55

+25

+125 °C

[1] VDD(PVDD) must always be the same or lower voltage than VDD.

[2] I_pdis the sum of all supply currents

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5 Ordering information

Table 2.ꢀOrdering information

Type number

Package

Name

Description

Version

CLRC66103HN/TRAYB^[1]

CLRC66103HN/T/R^[2]

HVQFN32

plastic thermal enhanced very thin quad flat package; no

leads; MSL2, 32 terminals + 1 central ground; body 5 x 5 x

0.85 mm, wettable flanks

SOT617-1

[1] Delivered in one tray, MOQ (Minimum order quantity): 490 pcs

[2] Delivered on reel with 6000 pieces; MOQ: 6000 pcs

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6 Block diagram

The analog interface handles the modulation and demodulation of the antenna signals for

the contactless interface.

The contactless UART manages the protocol dependency of the contactless interface

settings managed by the host.

The FIFO buffer ensures fast and convenient data transfer between host and the

contactless UART.

The register bank contains the settings for the analog and digital functionality.

REGISTER BANK

ANALOG

INTERFACE

CONTACTLESS

UART

ANTENNA

FIFO

BUFFER

SERIAL UART

SPI

I C-BUS

HOST

2

001aaj627

Figure 1.ꢀSimplified block diagram of the CLRC661

CLRC661

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7 Pinning information

terminal 1

index area

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

TDO/OUT0

TDI/OUT1

TMS/OUT2

TCK/OUT3

SIGIN/OUT7

SIGOUT

SDA

(1)

SCL

CLKOUT/OUT6

PDOWN

XTAL2

XTAL1

TVDD

heatsink

DVDD

VDD

TX1

001aam004

Transparent top view

1. VSS - heat sink connection

Figure 2.ꢀPinning configuration HVQFN32 (SOT617-1)

7.1 Pin description

Table 3.ꢀPin description

1

Symbol

TDO / OUT0

TDI / OUT1

TMS / OUT2

TCK / OUT3

SIGIN /OUT7

SIGOUT

DVDD

Type

Description

O

test data output for boundary scan interface / general purpose output 0

test data input boundary scan interface / general purpose output 1

test mode select boundary scan interface / general purpose output 2

test clock boundary scan interface / general purpose output 3

Contactless communication interface output. / general purpose output 7

Contactless communication interface input.

2

I

3

I

4

I

5

I/O

O

6

7

PWR

O

digital power supply buffer ^[1]

8

VDD

power supply

analog power supply buffer ^[1]

9

AVDD

10

11

12

13

14

15

16

17

AUX1

auxiliary outputs: Pin is used for analog test signal

receiver input pin for the received RF signal.

AUX2

O

RXP

I

RXN

I

receiver input pin for the received RF signal.

internal receiver reference voltage ^[1]

VMID

PWR

O

TX2

transmitter 2: delivers the modulated 13.56 MHz carrier

transmitter ground, supplies the output stage of TX1, TX2

transmitter 1: delivers the modulated 13.56 MHz carrier

TVSS

PWR

O

TX1

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Table 3.ꢀPin description...continued

18

Symbol

TVDD

Type

PWR

I

Description

transmitter voltage supply

19

XTAL1

crystal oscillator input: Input to the inverting amplifier of the oscillator. This pin is

also the input for an externally generated clock (fosc = 27.12 MHz)

20

21

22

23

24

25

26

27

28

XTAL2

O

crystal oscillator output: output of the inverting amplifier of the oscillator

Power Down (RESET)

PDOWN

CLKOUT / OUT6

SCL

I

O

clock output / general purpose output 6

Serial Clock line

O

SDA

I/O

Serial Data Line

PVDD

PWR

pad power supply

IFSEL0 / OUT4

IFSEL1 / OUT5

IF0

I

host interface selection 0 / general purpose output 4

host interface selection 1 / general purpose output 5

I

I/O

interface pin, multifunction pin: Can be assigned to host interface RS232, SPI,

I²C, I²C-L

29

30

IF1

IF2

I/O

interface pin, multifunction pin: Can be assigned to host interface SPI, I²C, I²C-L

interface pin, multifunction pin: Can be assigned to host interface RS232, SPI,

I²C, I²C-L

31

IF3

I/O

interface pin, multifunction pin: Can be assigned to host interface RS232, SPI,

I²C, I²C-L

32

33

IRQ

O

interrupt request: output to signal an interrupt event

ground and heat sink connection

VSS

PWR

[1] This pin is used for connection of a buffer capacitor. Connection of a supply voltage might damage the device.

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8 Functional description

SAM interface

2

SDA

SCL

I C,

FIFO

512 Bytes

EEPROM

8 kByte

LOGICAL

SPI

host interfaces

RESET

LOGIC

IFSEL1

IFSEL0

PDOWN

2

I C

IF0

IF1

IF2

IF3

REGISTERS

UART

SPI

STATEMACHINES

ANALOGUE FRONT-END

VDD

VSS

VOLTAGE

REGULATOR

3/5 V =>

1.8 V

VOLTAGE

REGULATOR

3/5 V =>

1.8 V

PVDD

TVDD

TVSS

AVDD

DVDD

TCK

TDI

TMS

TDO

BOUNDARY

SCAN

DVDD

AVDD

POR

ADC

RNG

PLL

TIMER4

(WAKE-UP

TIMER)

TX

CODEC

RX

DECOD

TIMER0..3

LFO

TX

CLKOUT

CL-

COPRO

AUX1

AUX2

SIGIN/

SIGOUT

CONTROL

INTERRUPT

CONTROLLER

CRC

SIGPRO

RX

OSC

RXP

VMID RXN

TX2

TX1

XTAL2

XTAL1

IRQ

SIGIN SIGOUT

001aam005

Figure 3.ꢀDetailed block diagram of the CLRC661

8.1 Interrupt controller

The interrupt controller handles the enabling/disabling of interrupt requests. All of the

interrupts can be configured by firmware. Additionally, the firmware has possibilities to

trigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0

and IRQ1 are implemented, accompanied by two 8-bit interrupt enable registers IRQ0En

and IRQ1En. A dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt

controller register is implemented.

The CLRC661 indicates certain events by setting bit IRQ in the register Status1Reg and

additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the

host using its interrupt handling capabilities. This allows the implementation of efficient

host software.

Table 4. shows the available interrupt bits, the corresponding source and the condition

for its activation. The interrupt bits Timer0IRQ, Timer1IRQ, Timer2IRQ, Timer3OIRQ, in

register IRQ1 indicate an interrupt set by the timer unit. The setting is done if the timer

underflows.

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The TxIRQ bit in register IRQ0 indicates that the transmission is finished. If the state

changes from sending data to transmitting the end of the frame pattern, the transmitter

unit sets the interrupt bit automatically.

The bit RxIRQ in register IRQ0 indicates an interrupt when the end of the received data is

detected.

The bit IdleIRQ in register IRQ0 is set if a command finishes and the content of the

command register changes to idle.

The register WaterLevel defines both - minimum and maximum warning levels - counting

from top and from bottom of the FIFO by a single value.

The bit HiAlertIRQ in register IRQ0 is set to logic 1 if the HiAlert bit is set to logic 1, that

means the FIFO data number has reached the top level as configured by the register

WaterLevel and bit WaterLevelExtBit.

The bit LoAlertIRQ in register IRQ0 is set to logic 1 if the LoAlert bit is set to logic 1, that

means the FIFO data number has reached the bottom level as configured by the register

WaterLevel.

The bit ErrIRQ in register IRQ0 indicates an error detected by the contactless UART

during receive. This is indicated by any bit set to logic 1 in register Error.

The bit LPCDIRQ in register IRQ0 indicates a card detected.

The bit RxSOFIRQ in register IRQ0 indicates a detection of a SOF or a subcarrier by the

contactless UART during receiving.

The bit GlobalIRQ in register IRQ1 indicates an interrupt occurring at any other interrupt

source when enabled.

Table 4.ꢀInterrupt sources

Interrupt bit

Timer0IRQ

Timer1IRQ

Timer2IRQ

Timer3IRQ

TxIRQ

Interrupt source

Timer Unit

Is set automatically, when

the timer register T0 CounterVal underflows

the timer register T1 CounterVal underflows

the timer register T2 CounterVal underflows

the timer register T3 CounterVal underflows

a transmitted data stream ends

Timer Unit

Transmitter

RxIRQ

Receiver

a received data stream ends

IdleIRQ

Command Register

FIFO-buffer pointer

a command execution finishes

HiAlertIRQ

the FIFO data number has reached the top level as

configured by the register WaterLevel

LoAlertIRQ

FIFO-buffer pointer

the FIFO data number has reached the bottom level as

configured by the register WaterLevel

ErrIRQ

contactless UART

LPCD

a communication error had been detected

LPCDIRQ

a card was detected when in low-power card detection

mode

RxSOFIRQ

GlobalIRQ

Receiver

detection of a SOF or a subcarrier

all interrupt sources

will be set if another interrupt request source is set

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8.2 Timer module

Timer module overview

The CLRC661 implements five timers. Four timers -Timer0 to Timer3 - have an input

clock that can be configured by register T(x)Control to be 13.56 MHz, 212 kHz, (derived

from the 27.12 MHz quartz) or to be the underflow event of the fifth Timer (Timer4). Each

timer implements a counter register which is 16 bit wide. A reload value for the counter

is defined in a range of 0000h to FFFFh in the registers TxReloadHi and TxReloadLo.

The fifth timer Timer4 is intended to be used as a wake-up timer and is connected to the

internal LFO (Low Frequency Oscillator) as input clock source.

The TControl register allows the global start and stop of each of the four timers Timer0

to Timer3. Additionally, this register indicates if one of the timers is running or stopped.

Each of the five timers implements an individual configuration register set defining timer

reload value (e.g. T0ReloadHi,T0ReloadLo), the timer value (e.g. T0CounterValHi,

T0CounterValLo) and the conditions which define start, stop and clockfrequency (e.g.

T0Control).

The external host may use these timers to manage timing relevant tasks. The timer unit

may be used in one of the following configurations:

• Time-out counter

• Watch-dog counter

• Stop watch

• Programmable one-shot timer

• Periodical trigger

The timer unit can be used to measure the time interval between two events or to

indicate that a specific event has occurred after an elapsed time. The timer register

content is modified by the timer unit, which can be used to generate an interrupt to allow

a host to react on this event.

The counter value of the timer is available in the registers T(x)CounterValHi,

T(x)CounterValLo. The content of these registers is decremented at each timer clock.

If the counter value has reached a value of 0000h and the interrupts are enabled for this

specific timer, an interrupt will be generated as soon as the next clock is received.

If enabled, the timer event can be indicated on the pin IRQ (interrupt request). The bit

Timer(x)IRQ can be set and reset by the host controller. Depending on the configuration,

the timer will stop counting at 0000h or restart with the value loaded from registers

T(x)ReloadHi, T(x)ReloadLo.

The counting of the timer is indicated by bit TControl.T(x)Running.

The timer can be started by setting bits TControl.T(x)Running and

TControl.T(x)StartStopNow or stopped by setting the bits TControl.T(x)StartStopNow and

clearing TControl.T(x)Running.

Another possibility to start the timer is to set the bit T(x)Mode.T(x)Start. This can be

useful if dedicated protocol requirements need to be fulfilled.

8.2.1 Timer modes

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8.2.1.1 Time-Out- and Watch-Dog-Counter

Having configured the timer by setting register T(x)ReloadValue and starting the counting

of Timer(x) by setting bit TControl.T(x)StartStop and TControl.T(x)Running, the timer unit

decrements the T(x)CounterValue Register beginning with the configured start event. If

the configured stop event occurs before the Timer(x) underflows (e.g. a bit is received

from the card), the timer unit stops (no interrupt is generated).

If no stop event occurs, the timer unit continues to decrement the counter registers until

the content is zero and generates a timer interrupt request at the next clock cycle. This

allows indicating to a host that the event did not occur during the configured time interval.

8.2.1.2 Wake-up timer

The wake-up Timer4 allows to wake-up the system from standby after a predefined time.

The system can be configured in such a way that it is entering the standby mode again in

case no card had been detected.

This functionality can be used to implement a low-power card detection (LPCD). For

the low-power card detection, it is recommended to set T4Control.T4AutoWakeUp

and T4Control.T4AutoRestart, to activate the Timer4 and automatically set the system

in standby. The internal low frequency oscillator (LFO) is then used as input clock

for this Timer4. If a card is detected, the host-communication can be started. If bit

T4Control.T4AutoWakeUp is not set, the CLRC661 will not enter the standby mode again

in case no card is detected but stays fully powered.

8.2.1.3 Stop watch

The elapsed time between a configured start- and stop event may be measured by the

CLRC661 timer unit. By setting the registers T(x)ReloadValueHi, T(x)reloadValueLo the

timer starts to decrement as soon as activated. If the configured stop event occurs, the

timer stops decrementing. The elapsed time between start and stop event can then be

calculated by the host dependent on the timer interval TTimer:

(1)

If an underflow occurred which can be identified by evaluating the corresponding IRQ bit,

the performed time measurement according to the formula above is not correct.

8.2.1.4 Programmable one-shot timer

The host configures the interrupt and the timer, starts the timer and waits for the interrupt

event on pin IRQ. After the configured time, the interrupt request will be raised.

8.2.1.5 Periodical trigger

If the bit T(x)Control.T(x)AutoRestart is set and the interrupt is activated, an interrupt

request will be indicated periodically after every elapsed timer period_.

8.3 Contactless interface unit

The contactless interface unit of the CLRC661 supports the following read/write operating

modes:

• ISO/IEC14443A / MIFARE Classic communication mode

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• ISO/IEC15693/ICODE

• ICODE EPC UID

• ISO/IEC 18000-3 mode 3/ EPC Class-1 HF

BATTERY/POWER SUPPLY

READER IC

ISO/IEC 14443 A CARD

MICROCONTROLLER

reader/writer

001aal996

Figure 4.ꢀRead/write mode

A typical system using the CLRC661 is using a microcontroller to implement the higher

levels of the contactless communication protocol and a power supply (battery or external

supply).

8.3.1 Communication mode for ISO/IEC 14443 type A and for MIFARE Classic

The physical level of the communication is shown in the following figure:

(1)

ISO/IEC 14443 A

ISO/IEC 14443 A CARD

READER

(2)

001aam268

1. Reader to Card 100 % ASK, Miller Coded, Transfer speed 106 kbit/s to 848 kbit/s

2. Card to Reader, Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed 106

kbit/s to 848 kbit/s

Figure 5.ꢀRead/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE

Classic

The physical parameters are described in the following table:

Table 5.ꢀCommunication overview for ISO/IEC 14443 type A and read/write mode for MIFARE Classic

Communication

direction

Signal type

Transfer speed

106 kbit/s

212 kbit/s

424 kbit/s

848 kbit/s

Reader to card (send

reader side

100 % ASK

100% ASK

data from the CLRC661 modulation

to a card)

bit encoding

fc = 13.56 MHz

modified Miller

encoding

modified Miller

encoding

modified Miller

encoding

modified Miller

encoding

bit rate [kbit/s]

fc / 128

fc / 64

fc / 32

fc / 16

Card to reader

(CLRC661 receives

data from a card)

card side

modulation

subcarrier load

modulation

subcarrier load

modulation

subcarrier load

modulation

subcarrier load

modulation

subcarrier

frequency

fc / 16

bit encoding

Manchester

encoding

BPSK

The CLRC661 connection to a host is required to manage the complete ISO/IEC 14443

type A and MIFARE Classic communication protocol. The following figure shows the data

coding and framing according to ISO/IEC 14443A and MIFARE Classic communication.

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ISO/IEC 14443 A framing at 106 kBd

start

8-bit data

odd

parity

start bit is 1

ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd

start

even

parity

8-bit data

odd

parity

start bit is 0

burst of 32

subcarrier clocks

even parity at the

end of the frame

001aak585

Figure 6.ꢀData coding and framing according to ISO/IEC 14443 A

The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A part

3 and handles parity generation internally according to the transfer speed.

8.3.2 ISO/IEC15693

The physical parameters are described in the following table:

Table 6.ꢀCommunication overview for ISO/IEC 15693 reader/writer reader to label

Communication

direction

Signal type

Transfer speed

fc / 8192 kbit/s

fc / 512 kbit/s

Reader to label

(send data from the

CLRC661 to a card)

reader side

modulation

10 % to 30 % ASK or

100 % ASK

10 % to 30 % ASK 90 %

to 100 % ASK

bit encoding

data rate

1/256

1/4

1.66 kbit/s

26.48 kbit/s

Table 7.ꢀCommunication overview for ISO/IEC 15693 reader/writer label to reader

Communication Signal type Transfer speed

direction

6.62 (6.67) kbit/s 13.24 kbit/s^[1]26.48

52.96 kbit/s

(26.69) kbit/s

Label to reader

(CLRC661

receives data

from a card)

card side

modulation

not supported

not supported single (dual) single

subcarrier

load

subcarrier

load

modulation

ASK

modulation

ASK

fc = 13.56 MHz

bit length

(μs)

-

37.76 (37.46) 18.88

bit encoding -

Manchester

coding

Manchester

coding

subcarrier

frequency

[MHz]

-

fc / 32 (fc /

28)

fc / 32

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[1] Fast inventory (page) read command only (ICODE proprietary command).

pulse

modulated

carrier

~9.44 µs

~18.88 µs

0 1 2 3 4

.

2

5

.

2 2 2 2

5 5 5 5

2 3 4 5

~4,833 ms

001aam272

Figure 7.ꢀData coding according to ISO/IEC 15693. standard mode reader to label

8.3.3 EPC-UID/UID-OTP

The physical parameters are described in the following table:

Table 8.ꢀCommunication overview for EPC/UID

Communication

direction

Signal type

Transfer speed

26.48 kbit/s

52.96 kbit/s

Reader to card

reader side modulation 10 % to 30 % ASK

(send data from the

CLRC661 to a card)

bit encoding

RTZ

bit length

37.76 μs

Card to reader

(CLRC661 receives

data from a card)

card side modulation

single subcarrier load

modulation

bit length

18.88 μs

bit encoding

Manchester coding

Data coding and framing according to EPC global 13.56 MHz ISM (industrial, scientific

and medical) Band Class 1 Radio Frequency Identification Tag Interface Specification

(Candidate Recommendation, Version 1.0.0).

8.3.4 ISO/IEC 18000-3 mode 3/ EPC Class-1 HF

The ISO/IEC 18000-3 mode 3/ EPC Class-1 HF is not described in this document. For a

detailed explanation of the protocol, refer to the ISO/IEC 18000-3 mode 3/ EPC Class-1

HF standard.

8.3.4.1 Data encoding ICODE

The ICODE protocols have mainly three different methods of data encoding:

• "1" out of "4" coding scheme

• "1" out of "256" coding scheme

• "Return to Zero" (RZ) coding scheme

Data encoding for all three coding schemes is done by the ICODE generator.

The supported EPC Class-1 HF modes are:

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• 2 pulse for 424 kbit subcarrier

• 4 pulse for 424 kbit subcarrier

• 2 pulse for 848 kbit subcarrier

• 4 pulse for 848 kbit subcarrier

8.4 Host interfaces

8.4.1 Host interface configuration

The CLRC661 supports direct interfacing of various hosts as the SPI, I²C, I²CL and serial

UART interface type. The CLRC661 resets its interface and checks the current host

interface type automatically having performed a power-up or resuming from power down.

The CLRC661 identifies the host interface by the means of the logic levels on the control

pins after the Cold Reset Phase. This is done by a combination of fixed pin connections.

The following table shows the possible configurations defined by IFSEL1, IFSEL0:

Table 9.ꢀConnection scheme for detecting the different interface types

28

29

30

31

26

27

Pin Symbol

IF0

UART

RX

SPI

I²C

I²C-L

MOSI

SCK

ADR1

SCL

ADR1

IF1

n.c.

SCL

IF2

TX

MISO

NSS

ADR2

SDA

IF3

PAD_VDD

VSS

ADR2

IFSEL0

IFSEL1

VSS

PAD_VDD

VSS

PAD_VDD

VSS

PAD_VDD

8.4.2 SPI interface

8.4.2.1 General

READER IC

SCK

IF1

IF0

IF2

IF3

MOSI

MISO

NSS

001aal998

Figure 8.ꢀConnection to host with SPI

The CLRC661 acts as a slave during the SPI communication. The SPI clock SCK has to

be generated by the master. Data communication from the master to the slave uses the

Line MOSI. Line MISO is used to send data back from the CLRC661 to the master.

A serial peripheral interface (SPI compatible) is supported to enable high-speed

communication to a host. The implemented SPI compatible interface is according to a

standard SPI interface. The SPI compatible interface can handle data speed of up to

10 Mbit/s. In the communication with a host, CLRC661 acts as a slave receiving data

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from the external host for register settings and to send and receive data relevant for the

communication on the RF interface.

NSS (Not Slave Select) enables or disables the SPI interface. When NSS is logical high,

the interface is disabled and reset. Between every SPI command, the NSS must go to

logical high to be able to start the next command read or write.

On both data lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI

line shall be stable on rising edge of the clock line (SCK) and is allowed to change on

falling edge. The same is valid for the MISO line. Data is provided by the CLRC661 on

the falling edge and is stable on the rising edge. The polarity of the clock is low at SPI

idle.

8.4.2.2 Read data

To read out data from the CLRC661 by using the SPI compatible interface, the following

byte order has to be used.

The first byte that is sent defines the mode (LSB bit) and the address.

Table 10.ꢀByte Order for MOSI and MISO

byte 0

byte 1

byte 2

byte 3 to n-1 byte n

byte n+1

00h

MOSI address 0

address 1

data 0

address 2

data 1

……..

address n

data n - 1

MISO

X

data n

Remark: The Most Significant Bit (MSB) has to be sent first.

8.4.2.3 Write data

To write data to the CLRC661 using the SPI interface, the following byte order has to

be used. It is possible to write more than one byte by sending a single address byte

(see.8.5.2.4).

The first send byte defines both, the mode itself and the address byte.

Table 11.ꢀByte Order for MOSI and MISO

byte 0

address 0

X

byte 1

data 0

X

byte 2

data 1

X

3 to n-1

……..

byte n

data n - 1

X

byte n + 1

data n

X

MOSI

MISO

……..

Remark: The Most Significant Bit (MSB) has to be sent first.

8.4.2.4 Address byte

The address byte has to fulfill the following format:

The LSB bit of the first byte defines the used mode. To read data from the CLRC661, the

LSB bit is set to logic 1. To write data to the CLRC661, the LSB bit has to be cleared. The

bits 6 to 0 define the address byte.

NOTE: When writing the sequence [address byte][data0][data1][data2]..., [data0] is

written to address [address byte], [data1] is written to address [address byte + 1] and

[data2] is written to [address byte + 2].

Exception: This auto increment of the address byte is not performed if data is written to

the FIFO address.

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Table 12.ꢀAddress byte 0 register; address MOSI

7

6

5

4

3

2

1

0

address 6 address 5 address 4 address 3 address 2 address 1 address 0 1 (read)

0 (write)

MSB

LSB

8.4.2.5 Timing Specification SPI

The timing condition for SPI interface is as follows:

Table 13.ꢀTiming conditions SPI

Symbol

t_SCKL

Parameter

Min

50

25

-

Typ

Max

Unit

SCK LOW time

-

ns

t_SCKH

SCK HIGH time

-

t_h(SCKH-D)

t_su(D-SCKH)

t_h(SCKL-Q)

t_(SCKL-NSSH)

t_NSSH

SCK HIGH to data input hold time

data input to SCK HIGH set-up time

SCK LOW to data output hold time

SCK LOW to NSS HIGH time

NSS HIGH time

-

25

-

0

50

-

t

SCKL

NSSH

SCKL

SCKH

SCK

t

h(SCKL-Q)

t

su(D-SCKH)

t

h(SCKH-D)

MOSI

MISO

MSB

LSB

t

(SCKL-NSSH)

NSS

aaa-016093

Figure 9.ꢀConnection to host with SPI

Remark: To send more bytes in one data stream, the NSS signal must be LOW during

the send process. To send more than one data stream, the NSS signal must be HIGH

between each data stream.

8.4.3 RS232 interface

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8.4.3.1 Selection of the transfer speeds

The internal UART interface is compatible to an RS232 serial interface. The levels

supplied to the pins are between VSS and PVDD. To achieve full compatibility of the

voltage levels to the RS232 specification, an RS232 level shifter is required.

Table 15 describes examples for different transfer speeds and relevant register settings.

The resulting transfer speed error is less than 1.5 % for all described transfer speeds.

The default transfer speed is 115.2 kbit/s.

To change the transfer speed, the host controller has to write a value for the new transfer

speed to the register SerialSpeedReg. The bits BR_T0 and BR_T1 define factors to set

the transfer speed in the SerialSpeedReg.

Table 14 describes the settings of BR_T0 and BR_T1.

Table 14.ꢀSettings of BR_T0 and BR_T1

BR_T0

0

1

2

3

4

5

6

7

factor BR_T0

range BR_T1

1

2

4

8

16

32

64

1 to 32

33 to 64

Table 15.ꢀSelectable transfer speeds

Transfer speed (kbit/s)

Serial SpeedReg

Transfer speed accuracy (%)

(Hex.)

FA

7.2

-0.25

0.32

-0.25

0.32

-0.25

-0.06

-0.25

1.45

0.32

9.6

EB

DA

CB

AB

9A

14.4

19.2

38.4

57.6

115.2

128

7A

74

230.4

460.8

921.6

1228.8

5A

3A

1C

15

The selectable transfer speeds as shown are calculated according to the following

formulas:

if BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)

if BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33)/2^{(BR_T0 - 1)}

Remark: Transfer speeds above 1228.8 kBits/s are not supported.

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8.4.3.2 Framing

Table 16.ꢀUART framing

Bit

Length

1 bit

Value

0

Start bit (Sa)

Data bits

Stop bit (So)

8 bit

Data

1

1 bit

Remark: For data and address bytes, the LSB bit has to be sent first. No parity bit is

used during transmission.

Read data: To read out data using the UART interface, the flow described below has to

be used. The first send byte defines both the mode itself and the address. The Trigger on

pin IF3 has to be set, otherwise no read of data is possible.

Table 17.ꢀByte Order to Read Data

Mode

RX

byte 0

address

-

byte 1

-

TX

data 0

ADDRESS

RX

Sa

A0

A1

A2

A3

A4

A5

A6 RD/ So

NWR

DATA

TX

Sa

D0

D1

D2

D3

D4

D5

D6

D7

So

001aam298

Figure 10.ꢀExample for UART Read

Write data:

To write data to the CLRC661 using the UART interface, the following sequence has to

be used.

The first send byte defines both, the mode itself and the address.

Table 18.ꢀByte Order to Write Data

Mode

RX

byte 0

byte 1

address 0

data 0

TX

address 0

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ADDRESS

DATA

RX

Sa

A0

A1

A2

A3

A4

A5

A6 RD/ So

NWR

Sa

D0

D1

D2

D3

D4

D5

D6

D7

So

ADDRESS

TX

Sa

A0

A1

A2

A3

A4

A5

A6 RD/ So

NWR

001aam299

Figure 11.ꢀExample diagram for a UART write

Remark: Data can be sent before address is received.

8.4.4 I²C-bus interface

8.4.4.1 General

An Inter IC (I²C) bus interface is supported to enable a low cost, low pin count serial bus

interface to the host. The implemented I²C interface is mainly implemented according to

the NXP Semiconductors I²C interface specification, rev. 3.0, June 2007. The CLRC661

can act as a slave receiver or slave transmitter in standard mode, fast mode and fast

mode plus.

The following features defined by the NXP Semiconductors I²C interface specification,

rev. 3.0, June 2007 are not supported:

• The CLRC661 I2C interface does not stretch the clock

• The CLRC661 I2C interface does not support the general call. This means that the

CLRC661 does not support a software reset

• The CLRC661 does not support the I2C device ID

• The implemented interface can only act in slave mode. Therefore no clock generation

and access arbitration is implemented in the CLRC661.

• High-speed mode is not supported by the CLRC661

PULL-UP

NETWORK

PULL-UP

NETWORK

READER IC

MICROCONTROLLER

SDA

SCL

001aam000

Figure 12.ꢀI²C-bus interface

The voltage level on the I2C pins is not allowed to be higher than PVDD.

SDA is a bidirectional line, connected to a positive supply voltage via a pull-up resistor.

Both lines SDA and SCL are set to HIGH level if no data is transmitted. Data on the I²C-

bus can be transferred at data rates of up to 400 kbit/s in fast mode, up to 1 Mbit/s in the

fast mode+.

If the I²C interface is selected, a spike suppression according to the I²C interface

specification on SCL and SDA is automatically activated.

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For timing requirements, refer to Table 201.

8.4.4.2 I²C Data validity

Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH state

or LOW state of the data line shall only change when the clock signal on SCL is LOW.

SDA

SCL

change

data line stable;

data valid

of data

allowed

001aam300

Figure 13.ꢀBit transfer on the I²C-bus

8.4.4.3 I²C START and STOP conditions

To handle the data transfer on the I²C-bus, unique START (S) and STOP (P) conditions

are defined.

A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL

is HIGH.

A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is

HIGH.

The master always generates the START and STOP conditions. The bus is considered to

be busy after the START condition. The bus is considered to be free again a certain time

after the STOP condition.

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition.

In this respect, the START (S) and repeated START (Sr) conditions are functionally

identical. Therefore, the S symbol will be used as a generic term to represent both the

START and repeated START (Sr) conditions.

SDA

SCL

SDA

SCL

S

P

START condition

STOP condition

001aam301

Figure 14.ꢀSTART and STOP conditions

8.4.4.4 I²C byte format

Each byte has to be followed by an acknowledge bit. Data is transferred with the

MSB first, see Figure 14. The number of transmitted bytes during one data transfer is

unrestricted but shall fulfill the read/write cycle format.

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8.4.4.5 I²C Acknowledge

An acknowledge at the end of one data byte is mandatory. The acknowledge-related

clock pulse is generated by the master. The transmitter of data, either master or slave,

releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull

down the SDA line during the acknowledge clock pulse so that it remains stable LOW

during the HIGH period of this clock pulse.

The master can then generate either a STOP (P) condition to stop the transfer, or a

repeated START (Sr) condition to start a new transfer.

A master-receiver shall indicate the end of data to the slave- transmitter by not

generating an acknowledge on the last byte that was clocked out by the slave. The slave-

transmitter shall release the data line to allow the master to generate a STOP (P) or

repeated START (Sr) condition.

DATA OUTPUT

BY TRANSMITTER

not acknowledge

DATA OUTPUT

BY RECEIVERER

acknowledge

SCL FROM

MASTER

1

2

8

9

S

clock pulse for

acknowledgement

START

condition

001aam302

Figure 15.ꢀAcknowledge on the I²C- bus

P

MSB

acknowledgement

signal from slave

acknowledgement

signal from receiver

Sr

byte complete,

interrupt within slave

clock line held low while

interrupts are serviced

S

or

Sr

or

P

1

2

7

8

9

1

2

3 - 8

9

ACK

001aam303

Figure 16.ꢀData transfer on the I²C- bus

8.4.4.6 I²C 7-bit addressing

During the I²C-bus addressing procedure, the first byte after the START condition is used

to determine which slave will be selected by the master.

Alternatively the I²C address can be configured in the EEPROM. Several address

numbers are reserved for this purpose. During device configuration, the designer has to

ensure, that no collision with these reserved addresses in the system is possible. Check

the corresponding I²C specification for a complete list of reserved addresses.

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For all CLRC661 devices, the upper 5 bits of the device bus address are reserved by

NXP and set to 01010(bin). The remaining 2 bits (ADR_2, ADR_1) of the slave address

can be freely configured by the customer in order to prevent collisions with other I²C

devices by using the interface pins (refer to Table 9) or the value of the I²C address

EEPROM register (refer to Table 31).

MSB

LSB

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W

slave address

001aam304

Figure 17.ꢀFirst byte following the START procedure

8.4.4.7 I²C-register write access

To write data from the host controller via I²C to a specific register of the CLRC661, the

following frame format shall be used.

The read/write bit shall be set to logic 0.

The first byte of a frame indicates the device address according to the I²C rules. The

second byte indicates the register address followed by up to n-data bytes. In case the

address indicates the FIFO, in one frame all n-data bytes are written to the FIFO register

address. This enables for example a fast FIFO access.

8.4.4.8 I²C-register read access

To read out data from a specific register address of the CLRC661, the host controller

shall use the procedure:

First a write access to the specific register address has to be performed as indicated in

the following frame:

The first byte of a frame indicates the device address according to the I²C rules. The

second byte indicates the register address. No data bytes are added.

The read/write bit shall be logic 0.

Having performed this write access, the read access starts. The host sends the device

address of the CLRC661. As an answer to this device address, the CLRC661 responds

with the content of the addressed register. In one frame n-data bytes could be read

using the same register address. The address pointing to the register is incremented

automatically (exception: FIFO register address is not incremented automatically).

This enables a fast transfer of register content. The address pointer is incremented

automatically and data is read from the locations [address], [address+1], [address+2]...

[address+(n-1)]

In order to support a fast FIFO data transfer, the address pointer is not incremented

automatically in case the address is pointing to the FIFO.

The read/write bit shall be set to logic 1.

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Write Cycle

0

(W)

I2C slave address

A7-A0

Frontend IC register

address A6-A0

DATA

[7..0]

SA

Ack

[0..n]

Ack

SO

Read Cycle

0

(W)

I2C slave address

A7-A0

Frontend IC register

address A6-A0

SA

Ack

0

Ack

Optional, if the previous access was on the same register address

0..n

1

(R)

I2C slave address

A7-A0

DATA

[7..0]

SA

Ack

[0..n]

Ack

sent by master

sent by slave

DATA

[7..0]

Nack

SO

001aam305

Figure 18.ꢀRegister read and write access

8.4.4.9 I²CL-bus interface

The CLRC661 provides an additional interface option for connection of a SAM. This

logical interface fulfills the I²C specification, but the rise/fall timings will not be compliant

to the I²C standard. The I²CL interface uses standard I/O pads, and the communication

speed is limited to 5 MBaud. The protocol itself is equivalent to the fast mode protocol of

I²C. The SCL levels are generated by the host in push/pull mode. The RC661 does not

stretch the clock. During the high period of SCL, the status of the line is maintained by a

bus keeper.

The address is 01010xxb, where the last two bits of the address can be defined by the

application. The definition of these bits can be done by two options. With a pin, where

the higher bit is fixed to 0 or the configuration can be defined via EEPROM. Refer to the

EEPROM configuration in Section 8.7.

Table 19.ꢀTiming parameter I²CL

Parameter

f_SCL

Min

0

Max

Unit

MHz

ns

5

-

t_HD;STA

t_LOW

80

100

80

0

-

ns

t_HIGH

-

ns

t_SU;SDA

t_HD;DAT

t_SU;DAT

t_SU;STO

t_BUF

-

ns

50

20

-

ns

0

ns

80

200

ns

-

ns

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The pull-up resistor is not required for the I²CL interface. Instead, a on chip buskeeper

is implemented in the CLRC661 for SDA of the I²CL interface. This protocol is intended

to be used for a point-to-point connection of devices over a short distance and does

not support a bus capability.The driver of the pin must force the line to the desired

logic voltage. To avoid that two drivers are pushing, the line at the same time following

regulations must be fulfilled:

SCL: As there is no clock stretching, the SCL is always under control of the Master.

SDA: The SDA line is shared between master and slave. Therefore the master and the

slave must have the control over the own driver enable line of the SDA pin. The following

rules must be followed:

• In the idle phase, the SDA line is driven high by the master

• In the time between start and stop condition, the SDA line is driven by master or slave

when SCL is low. If SCL is high, the SDA line is not driven by any device

• To keep the value on the SDA line a on chip, buskeeper structure is implemented for

the line

8.4.5 SAM interface

8.4.5.1 SAM functionality

The CLRC661 implements a dedicated I2C or SPI interface to integrate a MIFARE SAM

(Secure Access Module) in a very convenient way into applications (e.g. a proximity

reader).

The SAM can be connected to the microcontroller to operate like a cryptographic

coprocessor. For any cryptographic task, the microcontroller requests an operation from

the SAM, receives the answer and sends it over a host interface (e.g. I2C, SPI) interface

to the connected reader IC.

The MIFARE SAM supports an optimized method to integrate the SAM in a very

efficient way to reduce the protocol overhead. In this system configuration, the SAM is

integrated between the microprocessor and the reader IC, connected by one interface

to the reader IC and by another interface to the microcontroller. In this application, the

microcontroller accesses the SAM using the T=1 protocol and the SAM accesses the

reader IC using an I2C interface. The I2C SAM address is always defined by EEPROM

register. Default value is 0101100. As the SAM is directly communicating with reader IC,

the communication overhead is reduced. In this configuration, a performance boost of up

to 40 % can be achieved for a transaction time.

The MIFARE SAM supports applications using MIFARE product-based cards. For multi-

application purposes, an architecture connecting the microcontroller additionally directly

to the reader IC is recommended. This is possible by connecting the CLRC661 on

one interface (SAM Interface SDA, SCL) with the MIFARE SAM AV2.6 (P5DF081XX/

T1AR1070) and by connecting the microcontroller to the S2C or SPI interface.

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T=1

I2C

SAM

AV2.6

READER

IC

µC

I2C

Reader

aaa-002963

Figure 19.ꢀI2C interface enables convenient MIFARE SAM integration

8.4.5.2 SAM connection

The CLRC661 provides an interface to connect a SAM dedicated to the CLRC661. Both

interface options of the CLRC661, I²C, I²CL or SPI can be used for this purpose. The

interface option of the SAM itself is configured by a host command sent from the host to

the SAM.

The I²CL interface is intended to be used as connection between two ICs over a short

distance. The protocol fulfills the I²C specification, but does support a single device

connected to the bus only.

The SPI block for SAM connection is identical with the SPI host interface block.

The pins used for the SAM SPI are described in the following table:

Table 20.ꢀSPI SAM connection

SPI functionality

MISO

SCL

SDA2

SCL2

IFSEL1

IFSEL0

MOSI

NSS

8.4.6 Boundary scan interface

The CLRC661 provides a boundary scan interface according to the IEEE 1149.1. This

interface allows testing interconnections without using physical test probes. This is done

by test cells, assigned to each pin, which override the functionality of this pin.

To be able to program the test cells, the following commands are supported:

Table 21.ꢀBoundary scan command

Value

Command

Parameter in

Parameter out

(decimal)

0

1

2

3

4

5

bypass

-

preload

data (24)

-

sample

-

data (24)

ID code (default)

USER code

Clamp

data (32)

-

HIGH Z

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Table 21.ꢀBoundary scan command...continued

Value

Command

Parameter in

Parameter out

(decimal)

7

extest

data (24)

8

interface on/off

register access read

register access write

interface (1)

-

9

address (7)

data (8)

-

10

address (7) - data (8)

The Standard IEEE 1149.1 describes the four basic blocks necessary to use this

interface: Test Access Port (TAP), TAP controller, TAP instruction register, TAP data

register;

8.4.6.1 Interface signals

The boundary scan interface implements a four line interface between the chip and the

environment. There are three Inputs: Test Clock (TCK); Test Mode Select (TMS); Test

Data Input (TDI) and one output Test Data Output (TDO). TCK and TMS are broadcast

signals, TDI to TDO generate a serial line called Scan path.

Advantage of this technique is that independent of the numbers of boundary scan

devices the complete path can be handled with four signal lines.

The signals TCK, TMS are directly connected with the boundary scan controller. Because

these signals are responsible for the mode of the chip, all boundary scan devices in one

scan path will be in the same boundary scan mode.

8.4.6.2 Test Clock (TCK)

The TCK pin is the input clock for the module. If this clock is provided, the test logic

is able to operate independent of any other system clocks. In addition, it ensures that

multiple boundary scan controllers that are daisy-chained together can synchronously

communicate serial test data between components. During normal operation, TCK

is driven by a free-running clock. When necessary, TCK can be stopped at 0 or 1 for

extended periods of time. While TCK is stopped at 0 or 1, the state of the boundary scan

controller does not change and data in the Instruction and Data Registers is not lost.

The internal pull-up resistor on the TCK pin is enabled. This assures that no clocking

occurs if the pin is not driven from an external source.

8.4.6.3 Test Mode Select (TMS)

The TMS pin selects the next state of the boundary scan controller. TMS is sampled on

the rising edge of TCK. Depending on the current boundary scan state and the sampled

value of TMS, the next state is entered. Because the TMS pin is sampled on the rising

edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the

falling edge of TCK.

Holding TMS high for five consecutive TCK cycles drives the boundary scan controller

state machine to the Test-Logic-Reset state. When the boundary scan controller enters

the Test-Logic-Reset state, the Instruction Register (IR) resets to the default instruction,

IDCODE. Therefore, this sequence can be used as a reset mechanism.

The internal pull-up resistor on the TMS pin is enabled.

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8.4.6.4 Test Data Input (TDI)

The TDI pin provides a stream of serial information to the IR chain and the DR chains.

TDI is sampled on the rising edge of TCK and, depending on the current TAP state and

the current instruction, presents this data to the proper shift register chain. Because the

TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the

value on TDI to change on the falling edge of TCK.

The internal pull-up resistor on the TDI pin is enabled.

8.4.6.5 Test Data Output (TDO)

The TDO pin provides an output stream of serial information from the IR chain or the

DR chains. The value of TDO depends on the current TAP state, the current instruction,

and the data in the chain being accessed. In order to save power when the port is not

being used, the TDO pin is placed in an inactive drive state when not actively shifting out

data. Because TDO can be connected to the TDI of another controller in a daisy-chain

configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the

falling edge of TCK.

8.4.6.6 Data register

According to the IEEE1149.1 standard, there are two types of data register defined:

bypass and boundary scan

The bypass register enable the possibility to bypass a device when part of the scan path.

Serial data is allowed to be transferred through a device from the TDI pin to the TDO pin

without affecting the operation of the device.

The boundary scan register is the scan-chain of the boundary cells. The size of this

register is dependent on the command.

8.4.6.7 Boundary scan cell

The boundary scan cell opens the possibility to control a hardware pin independent of its

normal use case. Basically the cell can only do one of the following: control, output and

input.

IC1

IC2

Boundary scan cell

TDI

TDO

TDI

TDO

TAP

TCK

TMS

TCK

TMS

001aam306

Figure 20.ꢀBoundary scan cell path structure

8.4.6.8 Boundary scan path

This chapter shows the boundary scan path of the CLRC661.

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Table 22.ꢀBoundary scan path of the CLRC661

Number (decimal)

Cell

Port

Function

Control

Bidir

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

BC_1

BC_8

BC_1

BC_8

BC_1

BC_8

BC_1

BC_8

BC_1

BC_8

BC_1

BC_8

BC_1

BC_8

BC_1

BC_8

BC_1

BC_4

BC_1

BC_8

BC_1

BC_8

BC_1

BC_8

-

CLKOUT

-

Control

Bidir

SCL2

-

Control

Bidir

SDA2

-

Control

Bidir

IFSEL0

-

Control

Bidir

IFSEL1

-

Control

Bidir

IF0

-

Control

Bidir

IF1

-

Control

Bidir

8

IF2

7

IF2

Output2

Input

6

IF3

5

-

Control

Bidir

4

IRQ

3

-

Control

Bidir

2

SIGIN

-

1

Control

Bidir

0

SIGOUT

Refer to the CLRC663 BSDL file.

8.4.6.9 Boundary Scan Description Language (BSDL)

All of the boundary scan devices have a unique boundary structure which is necessary to

know for operating the device. Important components of this language are:

• available test bus signal

• compliance pins

• command register

• data register

• boundary scan structure (number and types of the cells, their function and the

connection to the pins.)

The CLRC661 is using the cell BC_8 for the IO-Lines. The I²C Pin is using a BC_4 cell.

For all pad enable lines, the cell BC1 is used.

The manufacturer's identification is 02Bh.

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• attribute IDCODEISTER of CLRC661: entity is "0001" and -- version

• "0011110010000010b" and -- part number (3C82h)

• "00000010101b" and -- manufacturer (02Bh)

• "1b"; -- mandatory

The user code data is coded as followed:

• product ID (3 bytes)

• version

These four bytes are stored as the first four bytes in the EEPROM.

8.4.6.10 Non-IEEE1149.1 commands

Interface on/off

With this command, the host/SAM interface can be deactivated and the Read and Write

command of the boundary scan interface is activated. (Data = 1). With Update-DR, the

value is taken over.

Register Access Read

At Capture-DR, the actual address is read and stored in the DR. Shifting the DR is

shifting in a new address. With Update-DR, this address is taken over into the actual

address.

Register Access Write

At the Capture-DR, the address and the data are taken over from the DR. The data is

copied into the internal register at the given address.

8.5 Buffer

8.5.1 Overview

A 512 × 8-bit FIFO buffer is implemented in the CLRC661. It buffers the input and output

data stream between the host and the internal state machine of the CLRC661. Thus, it

is possible to handle data streams with lengths of up to 512 bytes without taking timing

constraints into account. The FIFO can also be limited to a size of 255 bytes. In this case

all the parameters (FIFO length, Watermark...) require a single byte only for definition. In

case of a 512 byte FIFO length, the definition of this value requires 2 bytes.

8.5.2 Accessing the FIFO buffer

When the μ-Controller starts a command, the CLRC661 may, while the command is in

progress, access the FIFO-buffer according to that command. Physically only one FIFO-

buffer is implemented, which can be used in input and output direction. Therefore the μ-

Controller has to take care, not to access the FIFO buffer in a way that corrupts the FIFO

data.

8.5.3 Controlling the FIFO buffer

Besides writing to and reading from the FIFO buffer, the FIFO-buffer pointers might be

reset by setting the bit FIFOFlush in FIFOControl to 1. Consequently, the FIFOLevel bits

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are set to logic 0, the actually stored bytes are not accessible any more and the FIFO

buffer can be filled with another 512 bytes (or 255 bytes if the bit FIFOSize is set to 1)

again.

8.5.4 Status Information about the FIFO buffer

The host may obtain the following data about the FIFO-buffers status:

• Number of bytes already stored in the FIFO-buffer. Writing increments, reading

decrements the FIFO level: FIFOLength in register FIFOLength (and FIFOControl

Register in 512 byte mode)

• Warning, that the FIFO-buffer is almost full: HiAlert in register FIFOControl according

to the value of the water level in register WaterLevel (Register 02h bit [2], Register 03h

bit[7:0])

• Warning, that the FIFO-buffer is almost empty: LoAlert in register FIFOControl

according to the value of the water level in register WaterLevel (Register 02h bit [2],

Register 03h bit[7:0])

• FIFOOvl bit indicates, that bytes were written to the FIFO buffer although it was already

full: ErrIRQ in register IRQ0.

WaterLevel is one single value defining both HiAlert (counting from the FIFO top) and

LoAlert (counting from the FIFO bottom). The CLRC661 can generate an interrupt signal

if:

• LoAlertIRQEn in register IRQ0En is set to logic 1 it will activate pin IRQ when LoAlert in

the register FIFOControl changes to 1.

• HiAlertIRQEN in register IRQ0En is set to logic 1 it will activate pin IRQ when HiAlert in

the register FIFOControl changes to 1.

The bit HiAlert is set to logic 1 if maximum water level bytes (as set in register

WaterLevel) or less can be stored in the FIFO-buffer. It is generated according to the

following equation:

(2)

The bit LoAlert is set to logic 1 if water level bytes (as set in register WaterLevel) or less

are actually stored in the FIFO-buffer. It is generated according to the following equation:

(3)

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8.6 Analog interface and contactless UART

8.6.1 General

The integrated contactless UART supports the external host online with framing and

error checking of the protocol requirements up to 848 kbit/s. An external circuit can be

connected to the communication interface pins SIGIN and SIGOUT to modulate and

demodulate the data.

The contactless UART handles the protocol requirements for the communication

schemes in co-operation with the host. The protocol handling itself generates bit- and

byte-oriented framing and handles error detection like Parity and CRC according to the

different contactless communication schemes.

The size, the tuning of the antenna, and the supply voltage of the output drivers have an

impact on the achievable field strength. The operating distance between reader and card

depends additionally on the type of card used.

8.6.2 TX transmitter

The signal delivered on pin TX1 and pin TX2 is the 13.56 MHz carrier modulated by an

envelope signal for energy and data transmission. It can be used to drive an antenna

directly, using a few passive components for matching and filtering, see Section 14. The

signal on TX1 and TX2 can be configured by the register DrvMode, see Section 9.8.1.

The modulation index can be set by the TxAmp.

Following figure shows the general relations during modulation

influenced by set_clk_mode

envelope

TX ASK100

(1)

TX ASK10

(2)

time

001aan355

1: Defined by set_cw_amplitude.

2: Defined by set_residual_carrier.

Figure 21.ꢀGeneral dependences of modulation

Note: When changing the continuous carrier amplitude, the residual carrier amplitude

also changes, while the modulation index remains the same.

The registers Section 9.8and Section 9.9 control the data rate, the framing during

transmission and the setting of the antenna driver to support the requirements at the

different specified modes and transfer speeds.

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Table 23.ꢀSettings for TX1 and TX2

TxClkMode

Tx1 and TX2 output

Remarks

(binary)

000

High impedance

-

001

0

output pulled to 0 in any case

output pulled to 1 in any case

010

1

110

RF high side push

open-drain, only high side (push) MOS supplied

with clock, clock parity defined by invtx; low

side MOS is off

101

111

RF low side pull

open-drain, only low side (pull) MOS supplied

with clock, clock parity defined by invtx; high

side MOS is off

13.56 MHz clock derived

from 27.12 MHz quartz

divided by 2

push/pull Operation, clock polarity defined by

invtx; setting for 10 % modulation

Register TXamp and the bits for set_residual_carrier define the modulation index:

Table 24.ꢀSetting residual carrier and modulation index by

TXamp.set_residual_carrier

set_residual_carrier (decimal) residual carrier [%]

modulation index [%]

0

99

98

96

94

91

89

87

86

85

84

83

82

81

80

79

78

77

76

75

74

72

0.5

1

1.0

2

2.0

3

3.1

4

4.7

5

5.8

6

7.0

7

7.5

8

8.1

9

8.7

10

11

12

13

14

15

16

17

18

19

20

9.3

9.9

10.5

11.1

11.7

12.4

13.0

13.6

14.3

14.9

16.3

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Table 24.ꢀSetting residual carrier and modulation index by

TXamp.set_residual_carrier...continued

set_residual_carrier (decimal) residual carrier [%]

modulation index [%]

21

22

23

24

25

26

27

28

29

30

31

70

68

65

60

55

50

45

40

35

30

25

17.6

19.0

21.2

25.0

29.0

33.3

37.9

42.9

48.1

53.8

60.0

Note: At VDD(TVDD) <5 V and residual carrier settings <50 %, the accuracy of the

modulation index may be low in dependency of the antenna tuning impedance

8.6.2.1 Overshoot protection

The CLRC661 provides an overshoot protection for 100 % ASK to avoid overshoots

during a PCD communication. Therefore two timers overshoot_t1 and overshoot_t2 can

be used.

During the timer overshoot_t1 runs an amplitude defined by set_cw_amplitude bits is

provided to the output driver. Followed by an amplitude denoted by set_residual_carrier

bits with the duration of overshoot_t2.

7.0

(V)

5.0

3.0

1.0

-1.0

2.50

3.03

3.56

4.10

time ( s)

001aan356

Figure 22.ꢀExample 1: overshoot_t1 = 2d; overhoot_t2 = 5d.

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7.0

5.0

3.0

1.0

(V)

-1.0

0

1

2

3

4

5

time ( s)

001aan357

Figure 23.ꢀExample 2: overshoot_t1 = 0d; overhoot_t2 = 5d

8.6.2.2 Bit generator

The default coding of a data stream is done by using the Bit-Generator. It is activated

when the value of TxFrameCon.DCodeType is set to 0000 (bin). The Bit-Generator

encodes the data stream byte-wise and can apply the following encoding steps to each

data byte.

1. Add a start-bit of specified type at beginning of every byte

2. Add a stop-bit and EGT bits of a specified type. The maximum number of EGT bit is 6,

only full bits are supported

3. Add a parity-bit of a specified type

4. TxLastBits (skips a given number of bits at the end of the last byte in a frame)

5. Encrypt data-bit (MIFARE Classic encryption)

It is not possible to skip more than 8 bit of a single byte!

By default, data bytes are always treated LSB first.

8.6.3 Receiver circuitry

8.6.3.1 General

The CLRC661 features a versatile quadrature receiver architecture with fully differential

signal input at RXP and RXN. It can be configured to achieve optimum performance for

reception of various 13.56 MHz based protocols.

For all processing units various adjustments can be made to obtain optimum

performance.

8.6.3.2 Block diagram

The following figure shows the block diagram of the receiver circuitry. The receiving

process includes several steps. First the quadrature demodulation of the carrier signal of

13.56 MHz is done. Several tuning steps in this circuit are possible.

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fully/quasi-differential

rcv_hpcf<1:0>

rcv_gain<1:0>

rx_p

rx_n

mix_out_i_p

out_i_p

out_i_n

mixer

DATA

mix_out_i_n

2-stage BBA

clk_27 MHz

2-stage BBA

I-clks

rx_p

rx_n

13.56 MHz

I/O CLOCK

GENERATION

TIMING

GENERATION

ADC

clk_27 MHz

Adc_data_ready

DATA

Q-clks

rx_p

rx_n

mix_out_q_p

mix_out_q_n

out_q_p

out_q_n

mixer

rcv_gain<1:0>

rcv_hpcf<1:0>

fully/quasi-differential

001aan358

Figure 24.ꢀBlock diagram of receiver circuitry

The receiver can also be operated in a single ended mode. In this case, the

Rcv_RX_single bit has to be set. In the single ended mode, the two receiver pins RXP

and RXN need to be connected together and will provide a single ended signal to the

receiver circuitry.

When using the receiver in a single ended mode, the receiver sensitivity is decreased

and the achievable reading distance might be reduced, compared to the fully differential

mode.

Table 25.ꢀConfiguration for single or differential receiver

Mode

rcv_rx_single pins RXP and RXN

Fully differential

0

provide differential signal from differential antenna by

separate rx-coupling branches

Quasi differential

1

connect RXP and RXN together and provide single

ended signal from antenna by a single rx-coupling

branch

The quadrature-demodulator uses two different clocks, Q-clock and I-clock, with a

phase shift of 90° between them. Both resulting baseband signals are amplified, filtered,

digitized and forwarded to a correlation circuitry.

The typical application is intended to implement the Fully differential mode and

will deliver maximum reader/writer distance. The Quasi differential mode can be

used together with dedicated antenna topologies that allow a reduction of matching

components at the cost of overall reading performance.

During low-power card detection the DC levels at the I- and Q-channel mixer outputs

are evaluated. This requires that mixers are directly connected to the ADC. This can be

configured by setting the bit Rx_ADCmode in register Rcv (38h).

8.6.4 Active antenna concept

Two main blocks are implemented in the CLRC661. A digital circuitry, comprising state

machines, coder and decoder logic and an analog circuitry with the modulator and

antenna drivers, receiver and amplification circuitry. For example, the interface between

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these two blocks can be configured in the way, that the interfacing signals may be routed

to the pins SIGIN and SIGOUT. The most important use of this topology is the active

antenna concept where the digital and the analog blocks are separated. This opens the

possibility to connect e.g. an additional digital block of another CLRC661 device with a

single analog antenna frontend.

SIGIN

SIGOUT

SIGIN

READER IC

(DIGITAL)

READER IC

(ANTENNA)

SIGOUT

001aam307

Figure 25.ꢀBlock diagram of the active Antenna concept

The Table 26and Table 27 describe the necessary register configuration for the use case

active antenna concept.

Table 26.ꢀRegister configuration of CLRC661 active antenna concept (DIGITAL)

Register

Value (binary)

Description

SigOut.SigOutSel

Rcv.SigInSel

0100

TxEnvelope

10

11

Receive over SigIn (ISO/IEC14443A)

Receive over SigIn (Generic Code)

DrvCon.TxSel

00

Low (idle)

Table 27.ꢀRegister configuration of CLRC661 active antenna concept (Antenna)

Register

Value (binary)

Description

SigOut.SigOutSel

0110

0111

Generic Code (Manchester)

Manchester with Subcarrier (ISO/IEC14443A)

Rcv.SigInSel

01

10

1

Internal

DrvCon.TxSel

RxCtrl.RxMultiple

External (SigIn)

RxMultiple on

The interface between these two blocks can be configured in the way, that the interfacing

signals may be routed to the pins SIGIN and SIGOUT (see Figure 26).

This topology supports, that some parts of the analog part of the CLRC661 may be

connected to the digital part of another device.

The switch SigOutSel in registerSigOut can be used to measure signals. This is

especially important during the design-in phase or for test purposes to check the

transmitted and received data.

However, the most important use of SIGIN/SIGOUT pins is the active antenna concept.

An external active antenna circuit can be connected to the digital circuit of the CLRC661.

SigOutSel has to be configured in that way that the signal of the internal Miller Coder

is sent to SIGOUT pin (SigOutSel = 4). SigInSel has to be configured to receive

Manchester signal with subcarrier from SIGIN pin (SigInSel = 1).

It is possible, to connect a passive antenna to pins TX1, TX2 and RX (via the appropriate

filter and matching circuit) and at the same time an active antenna to the pins SIGOUT

and SIGIN. In this configuration, two RF-parts may be driven (one after another) by a

single host processor.

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8.6.5 Symbol generator

The symbol generator is used to create various protocol symbols. These can be e.g.

SOF or EOF symbols as they are used by the ISO14443 protocols or proprietary protocol

symbols like the CS symbol as used by the ICODE EPC protocol.

Symbols are defined by means of the symbol definition registers and the mode registers.

Four different symbols can be used. Two of them, Symbol0 and Symbol1 have a

maximum pattern length of 16 bit and feature a burst length of up to 256 bits of either

logic "0" or logic "1". The Symbol2 and Symbol3 are limited to 8-bit pattern length and do

not support a burst.

The definition of symbol patterns is done by writing the bit sequence of the pattern to

the appropriate register. The last bit of the pattern to be sent is located at the LSB of

the register. By setting the symbol length in the symbol-length register (TxSym10Len

and TxSym32Len), the definition of the symbol pattern is completed. All other bits at bit-

position higher than the symbol length in the definition register are ignored. (Example:

length of Symbol2 = 5, bit7 and bit6 are ignored, bit5 to bit0 define the symbol pattern,

bit5 is sent first)

Which symbol-pattern is sent can be configured in the TxFrameCon register. Symbol0,

Symbol1 and Symbol2 can be sent before data packets, Symbol1, Symbol2 and Symbol3

can be sent after data packets. Each symbol is defined by a set of registers. Symbols are

configured by a pair of registers. Symbol0 and Symbol1 share the same configuration

and Symbol2 and Symbol3 share the same configuration. The configuration includes

setting of bit-clock- and subcarrier-frequency, as well as selection of the pulse type/length

and the envelope type.

8.7 Memory

8.7.1 Memory overview

The CLRC661 implements three different memories: EEPROM, FIFO and Registers.

At startup, the initialization of the registers which define the behavior of the IC is

performed by an automatic copy of an EEPROM area (read/write EEPROM section1

and section2, register reset) into the registers. The behavior of the CLRC661 can be

changed by executing the command LoadProtocol, which copies a selected default

protocol from the EEPROM (read-only EEPROM section4, register Set Protocol area)

into the registers.

The read/write EEPROM section2 can be used to store any user data or predefined

register settings. These predefined settings can be copied with the command

"LoadRegister" into the internal registers.

The FIFO is used as Input/Out buffer and is able to improve the performance of a system

with limited interface speed.

8.7.2 EEPROM memory organization

The CLRC661 has implemented a EEPROM non-volatile memory with a size of 8

kB. The EEPROM is organized in pages of 64 bytes. One page of 64 bytes can be

programmed at a time. Defined purposes had been assigned to specific memory areas

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of the EEPROM, which are called Sections. Five sections 0..4 with different purpose do

exist.

Table 28.ꢀEEPROM memory organization

Section

Page

Byte

addresses

Access Memory content

rights

0

00 to 31

r

product information and configuration

32 to 63

r/w

w

product configuration

register reset

1

2

3

4

1 to 2

64 to 191

3 to 95

192 to 6143

6144 to 7167

7168 to 8191

free

96 to 111

112 to 127

MIFARE Classic key

Register Set Protocol (RSP)

r

The following figure shows the structure of the EEPROM:

Section 0:

Section 1:

Production and config

Register reset

Section 2:

Free

MIFARE Classic

key area (MKA)

Section 3:

Section 4_TX:

Section 4_RX:

RSP-Area for TX

RSP-Area for RX

001aan359

Figure 27.ꢀSector arrangement of the EEPROM

8.7.2.1 Product information and configuration - Page 0

The first EEPROM page includes production data as well as configuration information.

Table 29.ꢀProduction area (Page 0)

Address

(Hex.)

0

1

2

3

4

5

6

7

00

08

ProductID

Version

Unique IDentifier

Manufacturer

Data

10

18

ManufacturerData

ProductID: Identifier for a CLRC663 product or derivative, only address 01h shall be

evaluated for identifying the Product, address 00h and 02h shall be ignored by software.

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Please note, that the silicon version CLRC66103 and derivatives can be identified on

register address 7Fh, it is not coded in the EEPROM production area.

Table 30.ꢀProduct ID overview of CLRC663 family

Address 01h

CLRC663

MFRC631

MFRC630

SLRC610

CLRC661

Product ID

01h

C0h

80h

20h

E0h

Version: This register indicates the version of the EEPROM initialization data during

production.

Unique IDentifier: Unique serial number code for this device

Manufacturer Data: This data is programmed during production. The content is not

intended to be used by any application and might not be constant for different devices.

Therefore the content needs to be considered to be undefined.

Table 31.ꢀConfiguration area (Page 0)

Address

(Hex.)

0

1

2

3

4

5

6

7

20

28

30

38

I²C_Address

Interface I²C SAM_Address DefaultProtRx DefaultProtTx

-

TxCRCPreset

RxCRCPreset

-

I²C-Address

Two possibilities exist to define the address of the I²C interface. This can be done either

by configuring the pins IF0, IF2 (address is then 10101xx, xx is defined by the interface

pins IF0, IF2) or by writing value into the I²C address area. The selection, which of this

2-information pin configuration or EEPROM content - is used as I²C-address is done at

EEPROM address 21h (Interface, bit4)

Interface

This section describes the interface byte configuration.

Table 32.ꢀInterface byte

Bit

7

6

5

4

3

2

1

0

I²C_HSP

-

I2C_Address

r/w

Boundary Scan

r/w

Host

-

access rights

r/w

RFU

-

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Table 33.ꢀInterface bits

Bit

Symbol

Description

7

I²C_HSP

when cleared, the high-speed mode is used

when set, the high speed+ mode is used (default)

6, 5

4

RFU

I²C_Address

-

when cleared, the pins are used (default)

when set, the EEPROM is used

3

Boundary

Scan

when set, the boundary scan interface is ON (default)

when cleared, the boundary scan is OFF

2 to 0

Host

000b - RS232

001b - I²C

010b - SPI

011b - I²CL

1xxb - pin selection

I²C_SAM_Address

The I²C SAM Address is always defined by the EEPROM content.

The Register Set Protocol (RSP) Area contains settings for the TX registers (16 bytes)

and for the RX registers (8 bytes).

Table 34.ꢀTx and Rx arrangements in the register set protocol area

Section

Section 4 TX

Section 4 Rx

Tx0

Tx4

RX0

RX8

Tx1

TX2

Tx3

Tx5

TX6

TX7

RX6

RX14

RX1

RX9

RX2

RX10

RX3

RX4

RX12

RX5

RX7

RX11

RX13

RX15

TxCrcPreset

The data bits are sent by the analog module and are automatically extended by a CRC.

8.7.3 EEPROM initialization content LoadProtocol

The CLRC661 EEPROM is initialized at production with values which are used to reset

certain registers of the CLRC661 to default settings by copying the EEPROM content

to the registers. Only registers or bits with "read/write" or "dynamic" access rights are

initialized with this default values copied from the EEPROM.

Note that the addresses used for copying reset values from EEPROM to registers are

dependent on the configured protocol and can be changed by the user.

Table 35.ꢀRegister reset values (Hex.) (Page0)

Address 0 (8)

1 (9)

2 (A)

3 (B)

Version

XX

4 (C)

Unique IDentifier

XX XX

5 (D)

6 (E)

7 (F)

Function Product ID

00

XX

see table 30 XX

XX

Function Unique IDentifier

Factory trim

value

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Table 35.ꢀRegister reset values (Hex.) (Page0)...continued

Address 0 (8)

08 XX

1 (9)

2 (A)

3 (B)

4 (C)

5 (D)

6 (E)

7 (F)

XX

Function TrimLFO

10 XX

Factory trim values

XX

Function Factory trim values

18....

XX

Factory trim values

XX XX

....38

The register reset values are configuration parameters used after startup of the IC. They

can be changed to modify the default behavior of the device. In addition to these register

reset values, is the possibility to load settings for various users implemented protocols.

The load protocol command is used for this purpose.

Table 36.ꢀRegister reset values (Hex.)(Page1 and page 2)

Address 0 (8)

Command

40

1 (9)

HostCtrl

00

2 (A)

3 (B)

4 (C)

5 (D)

6 (E)

IRQ0

00

7 (F)

IRQ1

00

FiFoControl WaterLevel FiFoLength FiFoData

40

80

05

00

IRQ0En

10

IRQ1En

00

Error

00

Status

00

RxBitCtrl

00

RxColl

00

TControl

00

T0Control

00

48

T0ReloadHi T0ReloadLo T0Counter

ValHi

T0Counter

ValLo

T1Control

T1ReloadHi T1ReloadLo T1Counter

ValHi

50

58

60

68

00

80

00

80

00

T1Counter

ValLo

T2Control

T2ReloadHi T2ReloadLo T2Counter

ValHi

T2Counter

ValLo

T3Control

T3ReloadHi

00

80

00

T3ReloadLo T3Counter

ValHi

T3Counter

ValHi

T4Control

T4ReloadHi T4ReloadLo T4Counter

ValHi

T4Counter

ValLo

80

00

80

00

DrvMode

TxAmp

DrvCon

Txl

TxCRC

Preset

RxCRC

Preset

TxDataNum TxModWith

86

15

11

06

18

08

27

TxSym10

BurstLen

TxWaitCtrl

TxWaitLo

FrameCon

RxSofD

RxCtrl

RxWait

RxThres

hold

70

78

00

C0

12

CF

00

04

90

3F

Rcv

12

RxAna

0A

RFU

00

SerialSpeed LFO_trimm PLL_Ctrl

PLL_Div

20

LPCD_QMin

48

7A

80

04

LPCD_

QMax

LPCD_IMin LPCD _

result_I

LPCD _

result_Q

PadEn

PadOut

PadIn

SigOut

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Table 36.ꢀRegister reset values (Hex.)(Page1 and page 2)...continued

Address 0 (8)

1 (9)

2 (A)

3 (B)

4 (C)

5 (D)

6 (E)

7 (F)

80

88

12

88

00

TxBitMod

20

RFU

xx

TxDataCon TxDataMod TxSymFreq TxSym0H

TySym0L

00

TxSym1H

00

04

50

40

00

TxSym1L

0x00

TxSym2

0x00

TxSym3

TxSym10Le TxSym32Le TxSym32Bu TxSym10M TxSym32M

ngth

rstCtrl

od

90

98

0x00

0x50

RxBitMod

0x02

RxEOFSym RxSyncValH RxSyncValL RxSyncMod RxMod

0x00 0x00 0x01 0x00 0x08

RXCorr

0x08

FabCal

0xB2

8.8 Clock generation

8.8.1 Crystal oscillator

The clock applied to the CLRC661 acts as time basis for generation of the carrier sent

out at TX and for the quadrature mixer I and Q clock generation as well as for the coder

and decoder of the synchronous system. Therefore stability of the clock frequency is an

important factor for proper performance. To obtain highest performance, clock jitter has to

be as small as possible. This is best achieved by using the internal oscillator buffer with

the recommended circuitry.

READER IC

XTAL1 XTAL2

27.12 MHz

001aam308

Figure 28.ꢀCrystal connection

Table 37.ꢀCrystal requirements recommendations

Symbol

f_xtal

Parameter

Conditions

Min

-

Typ

27.12

-

max

-

Unit

MHz

ppm

crystal frequency

Δf_xtal/f_xtal

relative crystal

-250

+250

frequency variation

ESR

equivalent series

resistance

-

50

100

Ω

C_L

load capacitance

-

10

50

-

pF

P_xtal

crystal power

dissipation

100

μW

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8.8.2 IntegerN PLL clock line

The CLRC661 is able to provide a clock with configurable frequency at CLKOUT from

1 MHz to 24 MHz (PLL_Ctrl and PLL_DIV). There it can serve as a clock source to a

microcontroller which avoids the need of a second crystal oscillator in the reader system.

Clock source for the IntegerN-PLL is the 27.12 MHz crystal oscillator.

Two dividers are determining the output frequency. First a feedback integer-N divider

configures the VCO frequency to be N × fin/2 (control signal pll_set_divfb). As supported

Feedback Divider Ratios are 23, 27 and 28, VCO frequencies can be 23 × fin / 2 (312

MHz), 27 × fin / 2 (366 MHz) and 28 × fin / 2 (380 MHz).

The VCO frequency is divided by a factor which is defined by the output divider

(pll_set_divout). The following table shows the accuracy achieved for various frequencies

(integer multiples of 1 MHz and some typical RS232 frequencies) and the divider ratios to

be used. The register bit ClkOutEn enables the clock at CLKOUT pin.

The following formula can be used to calculate the output frequency:

f_out= 13.56 MHz × PLLDiv_FB /PLLDiv_Out

Table 38.ꢀDivider values for selected frequencies using the integerN PLL

Frequency [MHz]

PLLDiv_FB

4

6

8

10

28

38

12

23

26

20

28

19

24

23

16

1.8432 3.6864

23

78

27

61

23

39

28

PLLDiv_Out

206

103

0.01

accuracy [%]

0.04 0.03 0.04 0.08 0.04 0.08 0.04 0.01

8.8.3 Low Frequency Oscillator (LFO)

The CLRC661 implements a Low-Frequency Oscillator (LFO). Timer T4 can be

configured to use a clock generated by this LFO as input clock, and can be configured

as wake-up counter. As wake-up counter, the timer T4 allows waking up the system in

regular time intervals which allows to design a reader that is regularly polling for card

presence or implements a low-power card detection (LPCD).

The LFO is trimmed during chip production to run at 16 kHz. Unless a high accuracy

of the LFO is required by the application, and the device is operated in an environment

with changing ambient temperatures, trimming of the LFO is not required. For a typical

application making use of the LFO for wake-up from power-saving mode, the trim value

set during production can be used.

Optional trimming to achieve a higher accuracy of the 16 kHz LFO clock is supported by

a digital state machine which compares LFO-clock to a reference clock generated by the

connected 27.12 MHz crystal. As reference clock frequency for trimming of the LFO, a

13.56 MHz clock (27.12 MHz divided by 2) input clock to one of the timers T0, T1, T2 or

T3 is used.

One of the timers T0, T1, T2, T3 with an input clock of 13.56 MHz crystal clock is used

to count one clock period of the LFO. For an LFO Clock running at 16 KHz this would

result in 848 wake-up timer clocks of timer Tx (T0, T1, T2, T3). Therefore, the timer count

value Tx at the end of a trimming cycle is expected to be 176 (wake-up timer is counting

down: 1023-848=175, +/- 1 tolerance is accepted). The trim cycle is executed once in the

T4 timer cycle. Therefore the T4 autoload value shall be bigger than 0x05 to ensure that

one trimming cycle takes place before T4 expires. The Tx timer value is reloaded to 1023

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during the start of an Auto trim cycle. This happens every time, once after the T4 timer

underflows.

At the end of each trim cycle, the timer value is checked:

• Timer Tx value < 174: LFO Frequency is too low and the trim value is incremented by 1

on T4 Timer event

• Timer Tx value > 176: LFO Frequency is too high and the trim value is decremented by

1 on T4 Timer event

• Timer Tx value is within 174 and 176: LFO Frequency = 16 kHz and trimming

procedure is stopped

The cycle proceeds until the autotrimm function is stopped (Timer Tx value is within 174

and 176).

In addition, the trimming cycle can be aborted by sending an IDLE Command from the

host to cancel the current command execution. T3 is not allowed to be used in case

T4AutoLPCD is set in parallel. It is not required to configure a TXStart condition with

underflow. The T0/1/2/3 timer will typically not underflow. It may happen if the LPO clock

is very slow, but it is not required to take an action to generate this event.

8.9 Power management

8.9.1 Supply concept

The CLRC661 is supplied by V_DD(Supply Voltage), PVDD (Pad Supply) and TVDD

(Transmitter Power Supply). These three voltages are independent from each other.

To connect the CLRC661 to a Microcontroller supplied by 3.3 V, PVDD and V_DDshall be

at a level of 3.3 V, TVDD can be in a range from 3.3 V to 5.0 V. A higher supply voltage at

TVDD results in a higher field strength.

Independent of the voltage it is recommended to buffer these supplies with blocking

capacitances close to the terminals of the package. V_DDand PVDD are recommended to

be blocked with a capacitor of 100 nF min, TVDD is recommended to be blocked with 2

capacitors, 100 nF parallel to 1.0 μF

AVDD and DVDD are not supplied input pins. They are output pins and shall be

connected to blocking capacitors 470 nF each.

8.9.2 Power reduction mode

8.9.2.1 Power-down

A hard power-down is enabled with HIGH level on pin PDOWN. This turns off the internal

1.8 V voltage regulators for the analog and digital core supply as well as the oscillator.

All digital input buffers are separated from the input pads and clamped internally (except

pin PDOWN itself). The output pins are switched to high impedance. HardPowerDown is

performing a reset of the IC. All registers will be reset, the FIFO will be cleared.

To leave the power-down mode the level at the pin PDOWN as to be set to LOW. This

starts the internal start-up sequence.

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8.9.2.2 Standby mode

The standby mode is entered immediately after setting the bit PowerDown in the register

Command. All internal current sinks are switched off. Voltage references and voltage

regulators are set into standby mode.

In opposition to the power-down mode, the digital input buffers are not separated by the

input pads and keep their functionality. The digital output pins do not change their state.

During standby mode, all registers values, the FIFO’s content and the configuration itself

keeps its current content.

To leave the standby mode, the bit PowerDown in the register Command is cleared. This

triggers the internal start-up sequence. The reader IC is in full operation mode again

when the internal start-up sequence is finalized.

A value of 55h must be sent to the CLRC661 using the RS232 interface to leave the

standby mode. This is must at RS232, but cannot be used for the I²C/SPI interface. Then

read accesses shall be performed at address 00h until the device returns the content of

this address. The return of the content of address 00h indicates that the device is ready

to receive further commands and the internal start-up sequence is finalized.

8.9.2.3 Modem off mode

When the ModemOff bit in the register Control is set the antenna transmitter and the

receiver are switched off.

To leave the modem off mode, clear the ModemOff bit in the register Control.

8.9.3 Low-Power Card Detection (LPCD)

The low-power card detection is an energy-saving mode in which the CLRC661 is not

fully powered permanently.

The LPCD works in two phases. First the standby phase is controlled by the wake-up

counter (WUC), which defines the duration of the standby of the CLRC661. Second

phase is the detection-phase. In this phase, the values of the I and Q channel are

detected and stored in the register map. (LPCD_I_Result, LPCD_Q_Result).This time

period can be handled with Timer3. The value is compared with the min/max values in

the registers (LPCD_IMin, LPCD_IMax; LPCD_QMin, LPCD_QMax). If it exceeds the

limits, an LPCDIRQ is raised.

After the command LPCD the standby of the CLRC661 is activated, if selected.

The wake-up Timer4 can activate the system after a given time. For the LPCD, it is

recommended to set T4AutoWakeUp and T4AutoRestart, to start the timer and then go to

standby. If a card is detected, the communication can be started. If T4AutoWakeUp is not

set, the IC will not enter Standby mode in case no card is detected.

8.9.4 Reset and start-up time

A 10 μs constant high level at the PDOWN pin starts the internal reset procedure.

The following figure shows the internal voltage regulator:

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V

DD

PVDD

AVDD

DVDD

1.8 V

GLITCH

FILTER

INTERNAL VOLTAGE

REGULATOR

PDown

1.8 V

V

SS

V

SS

001aan360

Figure 29.ꢀInternal PDown to voltage regulator logic

When the CLRC661 has finished, the reset phase and the oscillator have entered a

stable working condition the IC is ready to be used.

8.10 Command set

8.10.1 General

The behavior is determined by a state machine capable to perform a certain set of

commands. By writing a command-code to the command register, the command is

executed.

Arguments and/or data necessary to process a command, are exchanged via the FIFO

buffer.

• Each command that needs a certain number of arguments will start processing only

when it has received the correct number of arguments via the FIFO buffer.

• The FIFO buffer is not cleared automatically at command start. It is recommended to

write the command arguments and/or the data bytes into the FIFO buffer and start the

command afterwards.

• Each command may be stopped by the host by writing a new command code into the

command register e.g.: the Idle-Command.

8.10.2 Command set overview

Table 39.ꢀCommand set

Command

Idle

No.

00h

01h

02h

Parameter (bytes)

Short description

-

no action, cancels current command execution

low-power card detection

LPCD

LoadKey

(keybyte1),(keybyte2), (keybyte3),

(keybyte4), (keybyte5),(keybyte6);

reads a MIFARE Classic key (size of 6 bytes) from

FIFO buffer ant puts it into Key buffer

MFAuthent

03h

60h or 61h, (block address), (card

serial number byte0),(card serial

number byte1), (card serial number

byte2),(card serial number byte3);

performs the MIFARE Classic authentication

AckReq

04h

-

performs a query, an Ack and a Req-Rn for ISO/IEC

18000-3 mode 3/ EPC Class-1 HF

Receive

Transmit

05h

06h

-

activates the receive circuit

bytes to send: byte1, byte2,....

transmits data from the FIFO buffer

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Table 39.ꢀCommand set...continued

Command

No.

Parameter (bytes)

Short description

Transceive

07h

bytes to send: byte1, byte2,....

transmits data from the FIFO buffer and automatically

activates the receiver after transmission finished

WriteE2

08h

09h

0Ah

0Ch

addressH, addressL, data;

gets one byte from FIFO buffer and writes it to the

internal EEPROM

WriteE2Page

ReadE2

(page Address), data0,

[data1 ..data63];

gets up to 64 bytes (one EEPROM page) from the FIFO

buffer and writes it to the EEPROM

addressH, address L, length;

reads data from the EEPROM and copies it into the

FIFO buffer

LoadReg

(EEPROM addressH), (EEPROM

addressL), RegAdr, (number of

Register to be copied);

reads data from the internal EEPROM and initializes

the CLRC661 registers. EEPROM address needs to be

within EEPROM sector 2

LoadProtocol

0Dh

(Protocol number RX), (Protocol

number TX);

reads data from the internal EEPROM and initializes the

CLRC661 registers needed for a Protocol change

LoadKeyE2

StoreKeyE2

0Eh

0Fh

KeyNr;

copies a key from the EEPROM into the key buffer

KeyNr, byte1, byte2, byte3, byte4,

byte5, byte6;

stores a MIFARE Classic key (size of 6 bytes) into the

EEPROM

ReadRNR

Soft Reset

1Ch

1Fh

-

Copies bytes from the Random Number generator into

the FIFO until the FIFO is full

-

resets the CLRC661

8.10.3 Command functionality

8.10.3.1 Idle command

Command (00h);

This command indicates that the CLRC661 is in idle mode. This command is also used to

terminate the actual command.

8.10.3.2 LPCD command

Command (01h);

This command performs a low-power card detection and/or an automatic trimming of

the LFO. After wake-up from standby, the values of the sampled I and Q channels are

compared with the min/max threshold values in the registers. If it exceeds the limits, an

LPCD_IRQ will be raised. After the LPCD command the standby is activated, if selected.

8.10.3.3 Load key command

Command (02h), Parameter1 (key byte1),..., Parameter6 (key byte6);

Loads a MIFARE Classic key (6 bytes) for Authentication from the FIFO into the crypto-

unit.

Abort condition: Less than 6 bytes written to the FIFO.

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8.10.3.4 MFAuthent command

Command (03h), Parameter1 (Authentication command code 60h or 61h), Parameter2

(block address), Parameter3 (card serial number byte0), Parameter4 (card serial number

byte1), Parameter5 (card serial number byte2), Parameter6 (card serial number byte3);

This command handles the MIFARE Classic authentication in Reader/Writer mode to

ensure a secure communication to any MIFARE Classic card.

When the MFAuthent command is active, any FIFO access is blocked. Anyhow if there is

access to the FIFO, the bit WrErr in the Error register is set.

This command terminates automatically when the MIFARE Classic card is authenticated

and the bit MFCrypto1On is set to logic 1.

This command does not terminate automatically, when the card does not answer,

therefore the timer should be initialized to automatic mode. In this case, beside the bit

IdleIRQ the bit TimerIRQ can be used as termination criteria. During authentication

processing the bits RxIRQ and TxIRQ are blocked. The Crypto1On shows if the

authentication was successful. The Crypto1On is always valid.

In case, there is an error during authentication, the bit ProtocolErr in the Error register is

set to logic 1 and the bit Crypto1On in register Status2Reg is set to logic 0.

8.10.3.5 AckReq command

Command (04h);

Performs a Query (Full command must be written into the FIFO); an Ack and a ReqRn

command. All answers to the command will be written into the FIFO. The error flag is

copied after the answer into the FIFO.

This command terminates automatically and the then active state is idle.

8.10.3.6 Receive command

Command (05h);

The CLRC661 activates the receiver path and waits for any data stream to be received,

according to its register settings. The registers must be set before starting this command

according to the used protocol and antenna configuration. The correct settings have to be

chosen before starting the command.

This command terminates automatically when the received data stream ends. This

is indicated either by the end of frame pattern or by the length byte depending on the

selected framing and speed.

Remark: If the bit RxMultiple in the RxModeReg register is set to logic 1, the Receive

command does not terminate automatically. It has to be terminated by activating any

other command in the CommandReg register (see Section 9.8.1).

8.10.3.7 Transmit command

Command (06h); data to transmit

The content of the FIFO is transmitted immediately after starting the command. Before

transmitting the FIFO, all relevant registers have to be set to transmit data.

This command terminates automatically when the FIFO gets empty. It can be terminated

by any other command written to the command register.

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8.10.3.8 Transceive command

Command (07h); data to transmit

This command transmits data from FIFO buffer and automatically activates the receiver

after a transmission is finished.

Each transmission process starts by writing the command into CommandReg.

Remark: If the bit RxMultiple in register RxModeReg is set to logic 1, this command will

never leave the receiving state, because the receiving will not be cancelled automatically.

8.10.3.9 WriteE2 command

Command (08h), Parameter1 (addressH), Parameter2 (addressL), Parameter3 (data);

This command writes one byte into the EEPROM. If the FIFO contains no data, the

command will wait until the data is available.

Abort condition: Address-parameter outside of allowed range 0x00 – 0x7F.

8.10.3.10 WriteE2PAGE command

Command (09h), Parameter1 (page address), Parameter2..65 (data0, data1...data63);

This command writes up to 64 bytes into the EEPROM. The addresses are not allowed

to wrap over a page border. If this is the case, this additional data be ignored and stays

in the FIFO. The programming starts after 64 bytes are read from the FIFO or the FIFO is

empty.

Abort condition: Insufficient parameters in FIFO; Page address parameter outside of

range 0x00 – 0x7F.

8.10.3.11 ReadE2 command

Command (0Ah), Parameter1 (addressH), Parameter2 (addressL), Parameter3 (length);

Reads up to 256 bytes from the EEPROM to the FIFO. If a read operation exceeds the

address 1FFFh, the read operation continues from address 0000h.

Abort condition: Insufficient parameter in FIFO; Address parameter outside of range.

8.10.3.12 LoadReg command

Command (0Ch), Parameter1 (EEPROM addressH),Parameter2 (EEPROM addressL),

Parameter3 (RegAdr), Parameter4 (number);

Read a defined number of bytes from the EEPROM and copies the value into the

Register set, beginning at the given address RegAdr.

Abort condition: Insufficient parameter in FIFO; Address parameter outside of range.

8.10.3.13 LoadProtocol command

Command (0Dh), Parameter1 (Protocol number RX), Parameter2 (Protocol number TX);

Reads out the EEPROM Register Set Protocol Area and overwrites the content of the

Rx- and Tx- related registers. These registers are important for a Protocol selection.

Abort condition: Insufficient parameter in FIFO

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Table 40.ꢀPredefined protocol overview RX^[1]

Protocol

Number

Protocol

Receiver speed

[kbits/s]

Receiver Coding

(decimal)

00

01

02

03

04

05

06

07

08

ISO/IEC14443 A

ISO/IEC15693

EPC/UID

106

212

424

848

26

Manchester SubC

BPSK

SSC

52

SSC

26

DSC

26

SSC

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

212

2/424

09

10

11

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

106

424

212

4/424

2/848

4/848

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

[1] For more protocol details, please refer to Section 8.

Table 41.ꢀPredefined protocol overview TX^[1]

Protocol

Number

(decimal)

Protocol

Transmitter speed Transmitter Coding

[kbits/s]

00

01

02

03

04

05

06

07

08

ISO/IEC14443 A

ISO/IEC15693

EPC/UID

106

212

424

848

26

Miller

1/4

26

1/4

1,66

53

1/256

Unitray

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

-

based on Tari value,

ASK, PIE

09

10

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

-

based on Tari value,

ASK, PIE

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

based on Tari value,

ASK, PIE

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Table 41.ꢀPredefined protocol overview TX^[1]...continued

Protocol

Number

Protocol

Transmitter speed Transmitter Coding

[kbits/s]

(decimal)

11

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

-

based on Tari value,

ASK, PIE

[1] For more protocol details, please refer to Section 8.

8.10.3.14 LoadKeyE2 command

Command (0Eh), Parameter1 (key number);

Loads a MIFARE Classic key for authentication from the EEPROM into the crypto 1 unit.

Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MIFARE Classic key

area.

8.10.3.15 StoreKeyE2 command

Command (0Fh), Parameter1 (KeyNr), Parameter2(keybyte1), Parameter3(keybyte2),

Parameter4(keybyte3), Parameter5(keybyte4), Parameter6(keybyte5), Parameter7

(keybyte6);

Stores MIFARE Classic keys into the EEPROM. The key number parameter indicates

the first key (n) in the MKA that will be written. If more than one MIFARE Classic key is

available in the FIFO then the next key (n+1) will be written until the FIFO is empty. If an

incomplete key (less than 6 bytes) is written into the FIFO, this key will be ignored and

will remain in the FIFO.

Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MKA;

8.10.3.16 GetRNR command

Command (1Ch);

This command is reading Random Numbers from the random number generator of the

CLRC661. The Random Numbers are copied to the FIFO until the FIFO is full.

8.10.3.17 SoftReset command

Command (1Fh);

This command is performing a soft reset. Triggered by this command all the default

values for the register setting will be read from the EEPROM and copied into the register

set.

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9 CLRC661 registers

9.1 Register bit behavior

Depending on the functionality of a register, the access conditions to the register can

vary. In principle, bits with same behavior are grouped in common registers. The access

conditions are described in the following table: 5 m

Table 42.ꢀBehavior of register bits and their designation

Abbreviation Behavior

Description

r/w

dy

r

read and write These bits can be written and read via the host interface. Since

they are used only for control purposes, the content is not

influenced by the state machines but can be read by internal

state machines.

dynamic

These bits can be written and read via the host interface. They

can also be written automatically by internal state machines, for

example Command register changes its value automatically after

the execution of the command.

read only

These register bits indicate hold values which are determined by

internal states only.

w

write only

-

Reading these register bits always returns zero.

RFU

These bits are reserved for future use and must not be changed.

In case of a required write access, it is recommended to read out

this bits, modify other bits of the register and write back only the

modified bits (read-modify-write).

Table 43.ꢀRegister overview

Address

00h

Register name

Command

HostCtrl

FIFOControl

WaterLevel

FIFOLength

FIFOData

IRQ0

Function

Starts and stops command execution

Host control register

01h

02h

Control register of the FIFO

03h

Level of the FIFO underflow and overflow warning

Length of the FIFO

04h

05h

Data In/Out exchange register of FIFO buffer

Interrupt register 0

06h

07h

IRQ1

Interrupt register 1

08h

IRQ0En

Interrupt enable register 0

09h

IRQ1En

Interrupt enable register 1

0Ah

0Bh

0Ch

0Dh

0Eh

Error

Error bits showing the error status of the last command execution

Contains status of the communication

Control register for anticollision adjustments for bit oriented protocols

Collision position register

Status

RxBitCtrl

RxColl

TControl

Control of Timer 0..3

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Table 43.ꢀRegister overview...continued

Address

0Fh

10h

11h

Register name

T0Control

Function

Control of Timer0

T0ReloadHi

T0ReloadLo

T0CounterValHi

T0CounterValLo

T1Control

High register of the reload value of Timer0

Low register of the reload value of Timer0

Counter value high register of Timer0

Counter value low register of Timer0

Control of Timer1

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

T1ReloadHi

T1ReloadLo

T1CounterValHi

T1CounterValLo

T2Control

High register of the reload value of Timer1

Low register of the reload value of Timer1

Counter value high register of Timer1

Counter value low register of Timer1

Control of Timer2

T2ReloadHi

T2ReloadLo

T2CounterValHi

T2CounterValLo

T3Control

High byte of the reload value of Timer2

Low byte of the reload value of Timer2

Counter value high byte of Timer2

Counter value low byte of Timer2

Control of Timer3

T3ReloadHi

T3ReloadLo

T3CounterValHi

T3CounterValLo

T4Control

High byte of the reload value of Timer3

Low byte of the reload value of Timer3

Counter value high byte of Timer3

Counter value low byte of Timer3

Control of Timer4

T4ReloadHi

T4ReloadLo

T4CounterValHi

T4CounterValLo

DrvMode

High byte of the reload value of Timer4

Low byte of the reload value of Timer4

Counter value high byte of Timer4

Counter value low byte of Timer4

Driver mode register

TxAmp

Transmitter amplifier register

DrvCon

Driver configuration register

Txl

Transmitter register

TxCrcPreset

RxCrcPreset

TxDataNum

TxModWidth

TxSym10BurstLen

TXWaitCtrl

Transmitter CRC control register, preset value

Receiver CRC control register, preset value

Transmitter data number register

Transmitter modulation width register

Transmitter symbol 1 + symbol 0 burst length register

Transmitter wait control

TxWaitLo

Transmitter wait low

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Table 43.ꢀRegister overview...continued

Address

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

54h

55h

56h

Register name

FrameCon

RxSofD

Function

Transmitter frame control

Receiver start of frame detection

RxCtrl

Receiver control register

RxWait

Receiver wait register

RxThreshold

Rcv

Receiver threshold register

Receiver register

RxAna

Receiver analog register

LPCD_Options

SerialSpeed

LFO_Trimm

PLL_Ctrl

Options for LPCD configuration

Serial speed register

Low-power oscillator trimming register

IntegerN PLL control register, for microcontroller clock output adjustment

Low-power card detection Q channel minimum threshold

Low-power card detection Q channel maximum threshold

Low-power card detection I channel minimum threshold

Low-power card detection I channel result register

Low-power card detection Q channel result register

PIN enable register

PLL_DivOut

LPCD_QMin

LPCD_QMax

LPCD_IMin

LPCD_I_Result

LPCD_Q_Result

PadEn

PadOut

PIN out register

PadIn

PIN in register

SigOut

Enables and controls the SIGOUT Pin

Transmitter bit mode register

TxBitMod

RFU

-

TxDataCon

TxDataMod

TxSymFreq

TxSym0H

TxSym0L

Transmitter data configuration register

Transmitter data modulation register

Transmitter symbol frequency

Transmitter symbol 0 high register

Transmitter symbol 0 low register

Transmitter symbol 1 high register

Transmitter symbol 1 low register

Transmitter symbol 2 register

TxSym1H

TxSym1L

TxSym2

TxSym3

Transmitter symbol 3 register

TxSym10Len

TxSym32Len

TxSym10BurstCtrl

TxSym10Mod

Transmitter symbol 1 + symbol 0 length register

Transmitter symbol 3 + symbol 2 length register

Transmitter symbol 1 + symbol 0 burst control register

Transmitter symbol 1 + symbol 0 modulation register

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Table 43.ꢀRegister overview...continued

Address

57h

Register name

TxSym32Mod

RxBitMod

RxEofSym

RxSyncValH

RxSyncValL

RxSyncMod

RxMod

Function

Transmitter symbol 3 + symbol 2 modulation register

Receiver bit modulation register

58h

59h

Receiver end of frame symbol register

Receiver synchronisation value high register

Receiver synchronisation value low register

Receiver synchronisation mode register

Receiver modulation register

5Ah

5Bh

5Ch

5Dh

5Eh

RxCorr

Receiver correlation register

5Fh

FabCal

Calibration register of the receiver, calibration performed at production

-

48h-5Fh

7Fh

RFU

Version

Version and subversion register

9.2 Command configuration

9.2.1 Command

Starts and stops command execution.

Table 44.ꢀCommand register (address 00h)

Bit

7

6

5

4

3

2

1

0

Symbol Standby

Modem

Off

RFU

Command

Access

rights

dy

r/w

-

dy

Table 45.ꢀCommand bits

Bit

7

Symbol

Description

Standby

ModemOff

Set to 1, the IC is entering power-down mode.

6

Set to logic 1, the receiver and the transmitter circuit are powering

down.

5

RFU

-

4 to 0

Command

Defines the actual command for the CLRC661.

9.3 SAM configuration register

9.3.1 HostCtrl

Via the HostCtrl Register the interface access right can be controlled

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Table 46.ꢀHostCtrl register (address 01h);

Bit

7

RegEn

dy

6

5

4

RFU

-

3

SAMInterface

r/w

2

SAMInterface

r/w

1

RFU

-

0

RFU

-

Symbol

BusHost

r/w

BusSAM

r/w

Access

rights

Table 47.ꢀHostCtrl bits

Bit

Symbol

Description

7

RegEn

If this bit is set to logic 1, the register HostCtrl_reg can be changed

at the next register access. The next write access clears this bit

automatically.

6

5

BusHost

BusSAM

RFU

Set to logic 1, the bus is controlled by the host. This bit cannot be set

together with the bit BusSAM. This bit can only be set if the bit RegEn

is previously set.

Set to logic 1, the bus is controlled by the SAM. This bit cannot be

set together with BusHost. This bit can only be set if the bit RegEn is

previously set.

4

-

3 to 2

SAMInterface 0h:SAM Interface switched off

1h:SAM Interface SPI active

2h:SAM Interface I²CL active

3h:SAM Interface I²C active

1 to 0

RFU

-

9.4 FIFO configuration register

9.4.1 FIFOControl

FIFOControl defines the characteristics of the FIFO.

Table 48.ꢀFIFOControl register (address 02h);

Bit

7

6

5

4

3

2

1

0

Symbol

FIFOSize

HiAlert

LoAlert

FIFOFlush

RFU

WaterLe

velExtBit

FIFOLengthExtBits

Access

rights

r/w

r

w

-

r/w

r

Table 49.ꢀFIFOControl bits

Bit

Symbol

Description

7

FIFOSize

Set to logic 1, FIFO size is 255 bytes;

Set to logic 0, FIFO size is 512 bytes.

It is recommended to change the FIFO size only, when the FIFO

content had been cleared.

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Table 49.ꢀFIFOControl bits...continued

Bit

Symbol

Description

6

HiAlert

Set to logic 1, when the number of bytes stored in the FIFO buffer

fulfills the following equation:

HiAlert = (FIFOSize - FIFOLength) <= WaterLevel

5

4

LoAlert

Set to logic 1, when the number of bytes stored in the FIFO buffer

fulfills the following conditions:

LoAlert =1 if FIFOLength <= WaterLevel

FIFOFlush

Set to logic 1 clears the FIFO buffer. Reading this bit will always

return 0

3

2

RFU

-

WaterLevelExtBit

Defines the bit 8 (MSB) for the water level (extension of register

WaterLevel). This bit is only evaluated in the 512-byte FIFO mode.

Bits 7..0 are defined in register WaterLevel.

1 to 0 FIFOLengthExtBits Defines the bit9 (MSB) and bit8 for the FIFO length (extension of

FIFOLength). These two bits are only evaluated in the 512-byte

FIFO mode. The bits 7..0 are defined in register FIFOLength.

9.4.2 WaterLevel

Defines the level for FIFO under- and overflow warning levels. This register is extended

by 1 bit in FIFOControl in case the 512-byte FIFO mode is activated by setting bit

FIFOControl.FIFOSize.

Table 50.ꢀWaterLevel register (address 03h);

Bit

7

6

5

4

3

2

1

0

Symbol

WaterLevelBits

r/w r/w

Access

rights

r/w

Table 51.ꢀWaterLevel bits

Bit

Symbol

Description

Sets a level to indicate a FIFO-buffer state which can be read

7 to 0

WaterLevelBits

from bits HighAlert and LowAlert in the FifoControl. In 512-byte

FIFO mode, the register is extended by bit WaterLevelExtBit in the

FIFOControl. This functionality can be used to avoid a FIFO buffer

overflow or underflow:

The bit HiAlert bit in FIFO Control is read logic 1, if the number of

bytes in the FIFO-buffer is equal or less than the number defined by

the water level configuration.

The bit LoAlert bit in FIFO control is read logic 1, if the number of

bytes in the FIFO buffer is equal or less than the number defined by

the water level configuration.

Note: For the calculation of HiAlert and LoAlert, see register

description of these bits (see section Section 9.4.1).

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9.4.3 FIFOLength

Number of bytes in the FIFO buffer. In 512-byte mode, this register is extended by

FIFOControl.FifoLength.

Table 52.ꢀFIFOLength register (address 04h); reset value: 00h

Bit

7

6

5

4

3

2

1

0

Symbol

FIFOLength

dy

Access

rights

Table 53.ꢀFIFOLength bits

Bit

Symbol

Description

7 to 0

FIFOLength

Indicates the number of bytes in the FIFO buffer. In 512-byte mode

this register is extended by the bits FIFOLength in the FIFOControl

register. Writing to the FIFOData register increments, reading

decrements the number of available bytes in the FIFO.

9.4.4 FIFOData

In- and output of FIFO buffer. Contrary to any read/write access to other addresses,

reading or writing to the FIFO address does not increment the address pointer. Writing

to the FIFOData register increments, reading decrements the number of bytes present in

the FIFO.

Table 54.ꢀFIFOData register (address 05h);

Bit

7

6

5

4

3

2

1

0

Symbol

FIFOData

Access

rights

dy

Table 55.ꢀFIFOData bits

Bit

Symbol

Description

7 to 0

FIFOData

Data input and output port for the internal FIFO buffer. Refer to

Section 8.5

9.5 Interrupt configuration registers

The Registers IRQ0 register and IRQ1 register implement a special functionality to avoid

the unintended modification of bits.

The mechanism of changing register contents requires the following consideration:

IRQ(x).Set indicates, if a set bit on position 0 to 6 shall be cleared or set. Depending

on the content of IRQ(x).Set, a write of a 1 to positions 0 to 6 either clears or sets the

corresponding bit. With this register, the application can modify the interrupt status which

is maintained by the CLRC661.

Bit 7 indicates, if the intended modification is a setting or clearance of a bit. Any 1 written

to a bit position 6...0 will trigger the setting or clearance of this bit as defined by bit 7.

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Example: writing FFh sets all bits 6..0, writing 7Fh clears all bits 6..0 of the interrupt

request register

9.5.1 IRQ0 register

Interrupt request register 0.

Table 56.ꢀIRQ0 register (address 06h); reset value: 00h

Bit

7

6

5

4

3

2

1

0

Symbol

Set

Hi AlertIRQ

Lo

AlertIRQ

IdleIRQ

TxIRQ

RxIRQ

ErrIRQ

RxSOF

IRQ

Access

rights

w

dy

Table 57.ꢀIRQ0 bits

Bit

Symbol

Description

7

Set

1: writing a 1 to a bit position 6..0 sets the interrupt request

0: Writing a 1 to a bit position 6..0 clears the interrupt request

6

5

4

HiAlerIRQ Set, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert,

HiAlertIRQ stores this event.

LoAlertIRQ Set, when bit LoAlert in register Status1 is set. In opposition to LoAlert,

LoAlertIRQ stores this event.

IdleIRQ

Set, when a command terminates by itself e.g. when the Command

changes its value from any command to the Idle command. If an unknown

command is started, the Command changes its content to the idle state and

the bit IdleIRQ is set. Starting the Idle command by the Controller does not

set bit IdleIRQ.

3

2

TxIRQ

RxIRQ

Set, when data transmission is completed, which is immediately after the

last bit is sent.

Set, when the receiver detects the end of a data stream.

Note: This flag is no indication that the received data stream is correct. The

error flags have to be evaluated to get the status of the reception.

1

0

ErrIRQ

Set, when the one of the following errors is set:

FifoWrErr, FiFoOvl, ProtErr, NoDataErr, IntegErr.

RxSOFlrq Set, when a SOF or a subcarrier is detected.

9.5.2 IRQ1 register

Interrupt request register 1.

Table 58.ꢀIRQ1 register (address 07h)

Bit

7

Set

w

6

5

4

3

2

Timer2IRQ

dy

1

0

Symbol

GlobalIRQ LPCD_IRQ Timer4IRQ Timer3IRQ

dy dy dy dy

Timer1IRQ Timer0IRQ

dy dy

Access

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Table 59.ꢀIRQ1 bits

Bit

Symbol

Description

7

Set

1: writing a 1 to a bit position 5..0 sets the interrupt request

0: Writing a 1 to a bit position 5..0 clears the interrupt request

6

5

4

3

2

1

0

GlobalIRQ Set, if an enabled IRQ occurs.

LPCD_IRQ Set if a card is detected in Low-power card detection sequence.

Timer4IRQ Set to logic 1 when Timer4 has an underflow.

Timer3IRQ Set to logic 1 when Timer3 has an underflow.

Timer2IRQ Set to logic 1 when Timer2 has an underflow.

Timer1IRQ Set to logic 1 when Timer1 has an underflow.

Timer0IRQ Set to logic 1 when Timer0 has an underflow.

9.5.3 IRQ0En register

Interrupt request enable register for IRQ0. This register allows defining if an interrupt

request is processed by the CLRC661.

Table 60.ꢀIRQ0En register (address 08h)

Bit

7

6

5

4

3

2

1

0

Symbol

IRQ_Inv Hi AlertIRQEn LoAlertIRQEn IdleIRQEn

TxIRQEn

RxIRQEn ErrIRQEn

RxSOF

IRQEn

Access

rights

r/w

r/w r/w

r/w

Table 61.ꢀIRQ0En bits

Bit

7

Symbol

Description

IRQ_Inv

Set to one the signal of the IRQ pin is inverted

6

Hi AlerIRQEn Set to logic 1, it allows the High Alert interrupt Request (indicated by the

bit HiAlertIRQ) to be propagated to the GlobalIRQ

5

4

3

2

1

0

Lo AlertIRQEn Set to logic 1, it allows the Low Alert Interrupt Request (indicated by the

bit LoAlertIRQ) to be propagated to the GlobalIRQ

IdleIRQEn

TxIRQEn

RxIRQEn

ErrIRQEn

Set to logic 1, it allows the Idle interrupt request (indicated by the bit

IdleIRQ) to be propagated to the GlobalIRQ

Set to logic 1, it allows the transmitter interrupt request (indicated by the

bit TxtIRQ) to be propagated to the GlobalIRQ

Set to logic 1, it allows the receiver interrupt request (indicated by the bit

RxIRQ) to be propagated to the GlobalIRQ

Set to logic 1, it allows the Error interrupt request (indicated by the bit

ErrorIRQ) to be propagated to the GlobalIRQ

RxSOFIRQEn Set to logic 1, it allows the RxSOF interrupt request (indicated by the bit

RxSOFIRQ) to be propagated to the GlobalIRQ

9.5.4 IRQ1En

Interrupt request enable register for IRQ1.

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Table 62.ꢀIRQ1EN register (address 09h);

Bit

7

6

5

4

3

2

1

0

Symbol IRQPushPull IRQPinEn LPCD_IRQEn

Timer4

IRQEn

Timer3

IRQEn

Timer2

IRQEn

Timer1

IRQEn

Timer0

IRQEn

Access

rights

r/w

Table 63.ꢀIRQ1EN bits

Bit

Symbol

Description

7

IRQPushPull

Set to 1 the IRQ-pin acts as PushPull pin, otherwise it acts as

OpenDrain pin

6

5

4

3

2

1

0

IRQPinEN

Set to logic 1, it allows the global interrupt request (indicated by the bit

GlobalIRQ) to be propagated to the interrupt pin

LPCD_IRQEN

Timer4IRQEn

Timer3IRQEn

Timer2IRQEn

Timer1IRQEn

Timer0IRQEn

Set to logic 1, it allows the LPCDinterrupt request (indicated by the bit

LPCDIRQ) to be propagated to the GlobalIRQ

Set to logic 1, it allows the Timer4 interrupt request (indicated by the bit

Timer4IRQ) to be propagated to the GlobalIRQ

Set to logic 1, it allows the Timer3 interrupt request (indicated by the bit

Timer3IRQ) to be propagated to the GlobalIRQ

Set to logic 1, it allows the Timer2 interrupt request (indicated by the bit

Timer2IRQ) to be propagated to the GlobalIRQ

Set to logic 1, it allows the Timer1 interrupt request (indicated by the bit

Timer1IRQ) to be propagated to the GlobalIRQ

Set to logic 1, it allows the Timer0 interrupt request (indicated by the bit

Timer0IRQ) to be propagated to the GlobalIRQ

9.6 Contactless interface configuration registers

9.6.1 Error

Error register.

Table 64.ꢀError register (address 0Ah)

Bit

7

EE_Err

dy

6

FiFoWrErr

dy

5

FIFOOvl

dy

4

MinFrameErr

dy

3

NoDataErr

dy

2

CollDet

dy

1

ProtErr

dy

0

IntegErr

dy

Symbol

Access

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Table 65.ꢀError bits

Bit

Symbol

Description

7

EE_Err

An error appeared during the last EEPROM command. For

details see the descriptions of the EEPROM commands

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Table 65.ꢀError bits...continued

Bit

Symbol

Description

6

FIFOWrErr Data was written into the FIFO, during a transmission of a possible

CRC, during "RxWait", "Wait for data" or "Receiving" state, or during an

authentication command. The Flag is cleared when a new CL command is

started. If RxMultiple is active, the flag is cleared after the error flags have

been written to the FIFO.

5

4

FIFOOvl

Data is written into the FIFO when it is already full. The data that is already

in the FIFO remains untouched. All data that is written to the FIFO after this

Flag is set to 1 will be ignored.

Min

A valid SOF was received, but afterwards less than 4 bits of data were

received.

FrameErr

Note: Frames with less than 4 bits of data are automatically discarded and

the RxDecoder stays enabled. Furthermore no RxIRQ is set. The same is

valid for less than 3 bytes, if the EMD suppression is activated

Note: MinFrameErr is automatically cleared at the start of a receive or

transceive command. In case of a transceive command, it is cleared at the

start of the receiving phase ("Wait for data" state)

3

2

NoDataErr Data should be sent, but no data is in FIFO

CollDet

A collision has occurred. The position of the first collision is shown in the

register RxColl.

Note: CollDet is automatically cleared at the start of a receive or transceive

command. In case of a transceive command, it is cleared at the start of the

receiving phase ("Wait for data" state).

Note: If a collision is part of the defined EOF symbol, CollDet is not set to 1.

1

ProtErr

A protocol error has occurred. A protocol error can be a wrong stop bit,

a missing or wrong ISO/IEC14443B EOF or SOF or a wrong number of

received data bytes. When a protocol error is detected, data reception is

stopped.

Note: ProtErr is automatically cleared at start of a receive or transceive

command. In case of a transceive command, it is cleared at the start of the

receiving phase ("Wait for data" state).

Note: When a protocol error occurs the last received data byte is not written

into the FIFO.

0

IntegErr

A data integrity error has been detected. Possible cause can be a wrong

parity or a wrong CRC. In case of a data integrity error the reception is

continued.

Note: IntegErr is automatically cleared at start of a Receive or Transceive

command. In case of a Transceive command, it is cleared at the start of the

receiving phase ("Wait for data" state).

Note: If the NoColl bit is set, also a collision is setting the IntegErr.

9.6.2 Status

Status register.

Table 66.ꢀStatus register (address 0Bh)

Bit

7

-

6

-

5

Crypto1On

dy

4

-

3

-

2

1

0

Symbol

ComState

r

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Table 67.ꢀStatus bits

Bit

7 to 6

5

Symbol

Description

-

RFU

Crypto1On Indicates if the MIFARE Classic Crypto is on. Clearing this bit is switching

the MIFARE Classic Crypto off. The bit can only be set by the MFAuthent

command.

4 to 3

-

RFU

2 to 0 ComState ComState shows the status of the transmitter and receiver state machine:

000b ... Idle

001b ... TxWait

011b ... Transmitting

101b ... RxWait

110b ... Wait for data

111b ... Receiving

100b ... not used

9.6.3 RxBitCtrl

Receiver control register.

Table 68.ꢀRxBitCtrl register (address 0Ch);

Bit

7

ValuesAfterColl

r/w

6

5

4

3

2

1

RxLastBits

w

0

Symbol

RxAlign

r/w

NoColl

r/w

Access

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r/w

w

Table 69.ꢀRxBitCtrl bits

Bit

Symbol

Description

7

ValuesAfter If cleared, every received bit after a collision is replaced by a zero. This

Coll

function is needed for ISO/IEC14443 anticollision

6 to 4

RxAlign

Used for reception of bit oriented frames: RxAlign defines the bit position

length for the first bit received to be stored. Further received bits are

stored at the following bit positions.

Example:

RxAlign = 0h - the LSB of the received bit is stored at bit 0, the second

received bit is stored at bit position 1.

RxAlign = 1h - the LSB of the received bit is stored at bit 1, the second

received bit is stored at bit position 2.

RxAlign = 7h - the LSB of the received bit is stored at bit 7, the second

received bit is stored in the following byte at position 0.

Note: If RxAlign = 0, data is received byte-oriented, otherwise bit-

oriented.

3

NoColl

If this bit is set, a collision will result in an IntegErr

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Table 69.ꢀRxBitCtrl bits...continued

Bit

Symbol

Description

2 to 0

RxLastBits

Defines the number of valid bits of the last data byte received in bit-

oriented communications. If zero the whole byte is valid.

Note: These bits are set by the RxDecoder in a bit-oriented

communication at the end of the communication. They are reset at start

of reception.

9.6.4 RxColl

Receiver collision register.

Table 70.ꢀRxColl register (address 0Dh);

Bit

7

6

5

4

3

2

1

0

Symbol

CollPosValid

r

CollPos

r

Access

rights

Table 71.ꢀRxColl bits

Bit

Symbol

Description

7

CollPos

Valid

If set to 1, the value of CollPos is valid. Otherwise no collision is detected or

the position of the collision is out of the range of bits CollPos.

6 to 0 CollPos

These bits show the bit position of the first detected collision in a received

frame (only data bits are interpreted). CollPos can only be displayed for the

first 8 bytes of a data stream.

Example:

00h indicates a bit collision in the 1st bit

01h indicates a bit collision in the 2nd bit

08h indicates a bit collision in the 9th bit (1st bit of 2nd byte)

3Fh indicates a bit collision in the 64th bit (8th bit of the 8th byte)

These bits shall only be interpreted in Passive communication mode at 106

kbit/s or ISO/IEC 14443 type A and read /write mode for MIFARE Classic or

ISO/IEC 15693/ICODE SLI read/write mode if bit CollPosValid is set.

Note: If RxBitCtrl.RxAlign is set to a value different to 0, this value is

included in the CollPos.

Example: RxAlign = 4h, a collision occurs in the 4th received bit (which is

the last bit of that UID byte). The CollPos = 7h in this case.

9.7 Timer configuration registers

9.7.1 TControl

Control register of the timer section.

The TControl implements a special functionality to avoid the not intended modification of

bits.

Bit 3..0 indicates, which bits in the positions 7..4 are intended to be modified.

Example: writing FFh sets all bits 7..4, writing F0h does not change any of the bits 7..4

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Table 72.ꢀTControl register (address 0Eh)

Bit

7

6

5

4

3

2

1

0

Symbol

T3Running T2Running T1Running T0Running

T3Start

T2Start

T1Start

T0Start

StopNow

Access

rights

dy

w

Table 73.ꢀTControl bits

Bit

Symbol

Description

7

T3Running

Indicates Timer3 is running. If the bit T3startStopNow is set/reset, this

bit and the timer can be started/stopped

6

5

4

3

T2Running

T1Running

T0Running

Indicates Timer2 is running. If the bit T2startStopNow is set/reset, this

bit and the timer can be started/stopped

Indicates tTmer1 is running. If the bit T1startStopNow is set/reset, this

bit and the timer can be started/stopped

Indicates Timer0 is running. If the bit T0startStopNow is set/reset, this

bit and the timer can be started/stopped

T3StartStop

Now

The bit 7 of TControl T3Running can be modified if set

The bit 6of TControl T2Running can be modified if set

The bit 5of TControl T1Running can be modified if set

The bit 4 of TControl T0Running can be modified if set

2

1

0

T2StartStop

Now

T1StartStop

Now

T0StartStop

Now

9.7.2 T0Control

Control register of the Timer0.

Table 74.ꢀT0Control register (address 0Fh);

Bit

7

6

-

5

4

3

T0AutoRestart

r/w

2

-

1

0

Symbol

T0StopRx

r/w

T0Start

r/w

T0Clk

r/w

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Table 75.ꢀT0Control bits

Bit

Symbol

Description

7

T0StopRx

If set, the timer stops immediately after receiving the first 4 bits. If

cleared, the timer does not stop automatically.

Note: If LFO Trimming is selected by T0Start, this bit has no effect.

6

-

RFU

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Table 75.ꢀT0Control bits...continued

Bit

Symbol

Description

5 to 4

T0Start

00b: The timer is not started automatically

01 b: The timer starts automatically at the end of the transmission

10 b: Timer is used for LFO trimming without underflow (Start/Stop on

PosEdge)

11 b: Timer is used for LFO trimming with underflow (Start/Stop on

PosEdge)

3

T0AutoRestart 1: the timer automatically restarts its count-down from

T0ReloadValue, after the counter value has reached the value zero.

0: the timer decrements to zero and stops.

The bit Timer1IRQ is set to logic 1 when the timer underflows.

2

-

RFU

1 to 0

T0Clk

00 b: The timer input clock is 13.56 MHz.

01 b: The timer input clock is 211,875 kHz.

10 b: The timer input clock is an underflow of Timer2.

11 b: The timer input clock is an underflow of Timer1.

9.7.2.1 T0ReloadHi

High byte reload value of the Timer0.

Table 76.ꢀT0ReloadHi register (address 10h);

Bit

7

6

5

4

3

2

1

0

Symbol

T0Reload Hi

r/w

Access

rights

Table 77.ꢀT0ReloadHi bits

Bit

Symbol

Description

7 to 0

T0ReloadHi

Defines the high byte of the reload value of the timer. With the start

event, the timer loads the value of the registers T0ReloadValHi,

T0ReloadValLo. Changing this register affects the timer only at the

next start event.

9.7.2.2 T0ReloadLo

Low byte reload value of the Timer0.

Table 78.ꢀT0ReloadLo register (address 11h);

Bit

7

6

5

4

3

2

1

0

Symbol

T0ReloadLo

r/w

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Table 79.ꢀT0ReloadLo bits

Bit

Symbol

Description

7 to0

T0ReloadLo

Defines the low byte of the reload value of the timer. With the

start event, the timer loads the value of the T0ReloadValHi,

T0ReloadValLo. Changing this register affects the timer only at the

next start event.

9.7.2.3 T0CounterValHi

High byte of the counter value of Timer0.

Table 80.ꢀT0CounterValHi register (address 12h)

Bit

7

6

5

4

3

2

1

0

Symbol

T0CounterValHi

dy

Access

rights

Table 81.ꢀT0CounterValHi bits

Bit

Symbol

Description

High byte value of the Timer0.

This value shall not be read out during reception.

7to0

T0Counter

ValHi

9.7.2.4 T0CounterValLo

Low byte of the counter value of Timer0.

Table 82.ꢀT0CounterValLo register (address 13h)

Bit

7

6

5

4

3

2

1

Symbol

T0CounterValLo

dy

Access

rights

Table 83.ꢀT0CounterValLo bits

Bit

Symbol

Description

7 to 0

T0CounterValLo

Low byte value of the Timer0.

This value shall not be read out during reception.

9.7.2.5 T1Control

Control register of the Timer1.

Table 84.ꢀT1Control register (address 14h);

Bit

7

6

-

5

4

3

T1AutoRestart

r/w

2

-

1

Symbol

T1StopRx

r/w

T1Start

r/w

T1Clk

r/w

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Table 85.ꢀT1Control bits

Bit

Symbol

Description

7

T1StopRx

If set, the timer stops after receiving the first 4 bits. If cleared, the

timer is not stopped automatically.

Note: If LFO trimming is selected by T1start, this bit has no effect.

6

-

RFU

5 to 4

T1Start

00b: The timer is not started automatically

01 b: The timer starts automatically at the end of the transmission

10 b: Timer is used for LFO trimming without underflow (Start/Stop on

PosEdge)

11 b: Timer is used for LFO trimming with underflow (Start/Stop on

PosEdge)

3

T1AutoRestart Set to logic 1, the timer automatically restarts its countdown from

T1ReloadValue, after the counter value has reached the value zero.

Set to logic 0 the timer decrements to zero and stops.

The bit Timer1IRQ is set to logic 1 when the timer underflows.

2

-

RFU

1 to 0

T1Clk

00 b: The timer input clock is 13.56 MHz

01 b: The timer input clock is 211,875 kHz.

10 b: The timer input clock is an underflow of Timer0

11 b: The timer input clock is an underflow of Timer2

9.7.2.6 T1ReloadHi

High byte (MSB) reload value of the Timer1.

Table 86.ꢀT0ReloadHi register (address 15h)

Bit

7

6

5

4

3

2

1

0

Symbol

T1ReloadHi

r/w

Access

rights

Table 87.ꢀT1ReloadHi bits

Bit

Symbol

Description

7 to 0

T1ReloadHi

Defines the high byte reload value of the Timer 1. With the start event,

the timer loads the value of the T1ReloadValHi and T1ReloadValLo.

Changing this register affects the Timer only at the next start event.

9.7.2.7 T1ReloadLo

Low byte (LSB) reload value of the Timer1.

Table 88.ꢀT1ReloadLo register (address 16h)

Bit

7

6

5

4

3

2

1

0

Symbol

T1ReloadLo

r/w

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Table 89.ꢀT1ReloadValLo bits

Bit

Symbol

Description

7 to 0

T1ReloadLo

Defines the low byte of the reload value of the Timer1. Changing this

register affects the timer only at the next start event.

9.7.2.8 T1CounterValHi

High byte (MSB) of the counter value of byte Timer1.

Table 90.ꢀT1CounterValHi register (address 17h)

Bit

7

6

5

4

3

2

1

0

Symbol

T1CounterValHi

dy

Access

rights

Table 91.ꢀT1CounterValHi bits

Bit

Symbol

Description

7 to 0

T1Counter

ValHi

High byte of the current value of the Timer1.

This value shall not be read out during reception.

9.7.2.9 T1CounterValLo

Low byte (LSB) of the counter value of byte Timer1.

Table 92.ꢀT1CounterValLo register (address 18h)

Bit

7

6

5

4

3

2

1

Symbol

T1CounterValLo

dy

Access

rights

Table 93.ꢀT1CounterValLo bits

Bit

Symbol

Description

7 to 0

T1Counter

ValLo

Low byte of the current value of the counter 1.

This value shall not be read out during reception.

9.7.2.10 T2Control

Control register of the Timer2.

Table 94.ꢀT2Control register (address 19h)

Bit

7

6

-

5

4

3

T2AutoRestart

r/w

2

-

1

Symbol

T2StopRx

r/w

T2Start

r/w

T2Clk

r/w

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Table 95.ꢀT2Control bits

Bit

Symbol

Description

7

T2StopRx

If set the timer stops immediately after receiving the first 4 bits. If

cleared indicates, that the timer is not stopped automatically.

Note: If LFO Trimming is selected by T2Start, this bit has no effect.

6

-

RFU

5 to 4

T2Start

00 b: The timer is not started automatically.

01 b: The timer starts automatically at the end of the transmission.

10 b: Timer is used for LFO trimming without underflow (Start/Stop on

PosEdge).

11 b: Timer is used for LFO trimming with underflow (Start/Stop on

PosEdge).

3

T2AutoRestart Set to logic 1, the timer automatically restarts its countdown from

T2ReloadValue, after the counter value has reached the value

zero. Set to logic 0 the timer decrements to zero and stops. The bit

Timer2IRQ is set to logic 1 when the timer underflows

2

-

RFU

1 to 0

T2Clk

00 b: The timer input clock is 13.56 MHz.

01 b: The timer input clock is 212 kHz.

10 b: The timer input clock is an underflow of Timer0

11b: The timer input clock is an underflow of Timer1

9.7.2.11 T2ReloadHi

High byte of the reload value of Timer2.

Table 96.ꢀT2ReloadHi register (address 1Ah)

Bit

7

6

5

4

3

2

1

0

Symbol

T2ReloadHi

r/w

Access

rights

Table 97.ꢀT2Reload bits

Bit

Symbol

Description

7 to 0

T2ReloadHi

Defines the high byte of the reload value of the Timer2. With the

start event, the timer load the value of the T2ReloadValHi and

T2ReloadValLo. Changing this register affects the timer only at the

next start event.

9.7.2.12 T2ReloadLo

Low byte of the reload value of Timer2.

Table 98.ꢀT2ReloadLo register (address 1Bh)

Bit

7

6

5

4

3

2

1

0

Symbol

T2ReloadLo

r/w

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Table 99.ꢀT2ReloadLo bits

Bit

Symbol

Description

7 to 0

T2ReloadLo

Defines the low byte of the reload value of the Timer2. With the

start event, the timer load the value of the T2ReloadValHi and

T2RelaodVaLo. Changing this register affects the timer only at the

next start event.

9.7.2.13 T2CounterValHi

High byte of the counter register of Timer2.

Table 100.ꢀT2CounterValHi register (address 1Ch)

Bit

7

6

5

4

3

2

1

0

Symbol

T2CounterValHi

dy

Access

rights

Table 101.ꢀT2CounterValHi bits

Bit

Symbol

Description

7 to 0

T2Counter

ValHi

High byte current counter value of Timer2.

This value shall not be read out during reception.

9.7.2.14 T2CounterValLoReg

Low byte of the current value of Timer 2.

Table 102.ꢀT2CounterValLo register (address 1Dh)

Bit

7

6

5

4

3

2

1

Symbol

T2CounterValLo

dy

Access

rights

Table 103.ꢀT2CounterValLo bits

Bit

Symbol

Description

7 to 0

T2Counter

ValLo

Low byte of the current counter value of Timer1Timer2.

This value shall not be read out during reception.

9.7.2.15 T3Control

Control register of the Timer 3.

Table 104.ꢀT3Control register (address 1Eh)

Bit

7

6

-

5

4

3

T3AutoRestart

r/w

2

-

1

Symbol

T3StopRx

r/w

T3Start

r/w

T3Clk

r/w

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Table 105.ꢀT3Control bits

Bit

Symbol

Description

7

T3StopRx

If set, the timer stops immediately after receiving the first 4 bits. If

cleared, indicates that the timer is not stopped automatically.

Note: If LFO Trimming is selected by T3Start, this bit has no effect.

6

-

RFU

5 to 4

T3Start

00b - timer is not started automatically

01 b - timer starts automatically at the end of the transmission

10 b - timer is used for LFO trimming without underflow (Start/Stop on

PosEdge)

11 b - timer is used for LFO trimming with underflow (Start/Stop on

PosEdge).

3

T3AutoRestart Set to logic 1, the timer automatically restarts its countdown from

T3ReloadValue, after the counter value has reached the value zero.

Set to logic 0 the timer decrements to zero and stops.

The bit Timer1IRQ is set to logic 1 when the timer underflows.

2

-

RFU

1 to 0

T3Clk

00 b - the timer input clock is 13.56 MHz.

01 b - the timer input clock is 211,875 kHz.

10 b - the timer input clock is an underflow of Timer0

11 b - the timer input clock is an underflow of Timer1

9.7.2.16 T3ReloadHi

High byte of the reload value of Timer3.

Table 106.ꢀT3ReloadHi register (address 1Fh);

Bit

7

6

5

4

3

2

1

0

Symbol

T3ReloadHi

r/w

Access

rights

Table 107.ꢀT3ReloadHi bits

Bit

Symbol

Description

7 to 0

T3ReloadHi

Defines the high byte of the reload value of the Timer3. With the

start event, the timer load the value of the T3ReloadValHi and

T3ReloadValLo. Changing this register affects the timer only at the

next start event.

9.7.2.17 T3ReloadLo

Low byte of the reload value of Timer3.

Table 108.ꢀT3ReloadLo register (address 20h)

Bit

7

6

5

4

3

2

1

0

Symbol

T3ReloadLo

r/w

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Table 109.ꢀT3ReloadLo bits

Bit

Symbol

Description

7 to 0

T3ReloadLo

Defines the low byte of the reload value of Timer3. With the

start event, the timer load the value of the T3ReloadValHi and

T3RelaodValLo. Changing this register affects the timer only at the

next start event.

9.7.2.18 T3CounterValHi

High byte of the current counter value the 16-bit Timer3.

Table 110.ꢀT3CounterValHi register (address 21h)

Bit

7

6

5

4

3

2

1

0

Symbol

T3CounterValHi

dy

Access

rights

Table 111.ꢀT3CounterValHi bits

Bit

Symbol

Description

7 to 0

T3Counter

ValHi

High byte of the current counter value of Timer3.

This value shall not be read out during reception.

9.7.2.19 T3CounterValLo

Low byte of the current counter value the 16-bit Timer3.

Table 112.ꢀT3CounterValLo register (address 22h)

Bit

7

6

5

4

3

2

1

0

Symbol

T3CounterValLo

dy

Access

rights

Table 113.ꢀT3CounterValLo bits

Bit

Symbol

Description

7 to 0

T3Counter

ValLo

Low byte current counter value of Timer3.

This value shall not be read out during reception.

9.7.2.20 T4Control

The wake-up timer T4 activates the system after a given time. If enabled, it can start the

low-power card detection function.

Table 114.ꢀT4Control register (address 23h)

Bit

7

6

5

4

3

2

1

0

Symbol

T4Running

T4Start

T4Auto

Trimm

T4Auto

LPCD

T4Auto

Restart

T4AutoWakeUp

T4Clk

StopNow

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Table 114.ꢀT4Control register (address 23h)...continued

Bit

7

6

5

4

3

2

1

0

Access

rights

dy

w

r/w

Table 115.ꢀT4Control bits

Bit

Symbol

Description

7

T4Running

Shows if the timer T4 is running. If the bit T4StartStopNow is set,

this bit and the timer T4 can be started/stopped.

6

5

T4Start

if set, the bit T4Running can be changed.

StopNow

T4AutoTrimm

If set to one, the timer activates an LFO trimming procedure when it

underflows. For the T4AutoTrimm function, at least one timer (T0 to

T3) has to be configured properly for trimming (T3 is not allowed if

T4AutoLPCD is set in parallel).

4

T4AutoLPCD

If set to one, the timer activates a low-power card detection

sequence. If a card is detected an interrupt request is raised and

the system remains active if enabled. If no card is detected the

CLRC661 enters the Power down mode if enabled. The timer is

automatically restarted (no gap). Timer 3 is used to specify the time

where the RF field is enabled to check if a card is present. Therefore

you may not use Timer 3 for T4AutoTrimm in parallel.

3

2

T4AutoRestart

Set to logic 1, the timer automatically restarts its countdown from

T4ReloadValue, after the counter value has reached the value

zero. Set to logic 0 the timer decrements to zero and stops. The bit

Timer4IRQ is set to logic 1 at timer underflow.

T4AutoWakeUp If set, the CLRC661 wakes up automatically, when the timer T4 has

an underflow. This bit has to be set if the IC should enter the Power

down mode after T4AutoTrimm and/or T4AutoLPCD is finished and

no card has been detected. If the IC should stay active after one of

these procedures, this bit has to be set to 0.

1 to 0

T4Clk

00b - the timer input clock is the LFO clock

01b - the timer input clock is the LFO clock/8

10b - the timer input clock is the LFO clock/16

11b - the timer input clock is the LFO clock/32

9.7.2.21 T4ReloadHi

High byte of the reload value of the 16-bit timer 4.

Table 116.ꢀT4ReloadHi register (address 24h)

Bit

7

6

5

4

3

2

1

0

Symbol

T4ReloadHi

r/w

Access

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Table 117.ꢀT4ReloadHi bits

Bit

Symbol

Description

7 to 0

T4ReloadHi

Defines high byte for the reload value of timer 4. With the start event,

the timer 4 loads the T4ReloadVal. Changing this register affects the

timer only at the next start event.

9.7.2.22 T4ReloadLo

Low byte of the reload value of the 16-bit timer 4.

Table 118.ꢀT4ReloadLo register (address 25h)

Bit

7

6

5

4

3

2

1

0

Symbol

T4ReloadLo

r/w

Access

rights

Table 119.ꢀT4ReloadLo bits

Bit

Symbol

Description

7 to 0

T4ReloadLo

Defines the low byte of the reload value of the timer 4. With the start

event, the timer loads the value of the T4ReloadVal. Changing this

register affects the timer only at the next start event.

9.7.2.23 T4CounterValHi

High byte of the counter value of the 16-bit timer 4.

Table 120.ꢀT4CounterValHi register (address 26h)

Bit

7

6

5

4

3

2

1

0

Symbol

T4CounterValHi

dy

Access

rights

Table 121.ꢀT4CounterValHi bits

Bit

Symbol

Description

High byte of the current counter value of timer 4.

7 to 0

T4CounterValHi

9.7.2.24 T4CounterValLo

Low byte of the counter value of the 16-bit timer 4.

Table 122.ꢀT4CounterValLo register (address 27h)

Bit

7

6

5

4

3

2

1

0

Symbol

T4CounterValLo

dy

Access

rights

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Table 123.ꢀT4CounterValLo bits

Bit

Symbol

Description

Low byte of the current counter value of the timer 4.

7 to 0

T4CounterValLo

9.8 Transmitter driver configuration registers

9.8.1 DrvMode

Table 124.ꢀDrvMode register (address 28h)

Bit

7

6

5

-

4

-

3

2

1

TxClk Mode

r/w

0

Symbol

Tx2Inv

r/w

Tx1Inv

r/w

TxEn

r/w

Access

rights

RFU

Table 125.ꢀDrvMode bits

Bit

Symbol

Tx2Inv

Tx1Inv

Description

7

Inverts transmitter 2 at TX2 pin

6

Inverts transmitter 1 at TX1 pin

5

RFU

4

-

3

TxEn

If set to 1 both transmitter pins are enabled

2 to 0

TxClkMode

Transmitter clock settings (see 8.6.2. Table 27). Codes 011b and

0b110 are not supported. This register defines, if the output is

operated in open-drain, push-pull, at high impedance or pulled to a fix

high or low level.

9.8.2 TxAmp

With the set_cw_amplitude register, output power can be traded off against power supply

rejection. Spending more headroom leads to better power supply rejection ration and

better accuracy of the modulation degree.

With CwMax set, the voltage of TX1 will be pulled to the maximum possible. This register

overrides the settings made by set_cw_amplitude.

Table 126.ꢀTxAmp register (address 29h)

Bit

7

6

5

-

4

3

2

set_residual_carrier

r/w

1

0

Symbol

set_cw_amplitude

r/w

Access

rights

RFU

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Table 127.ꢀTxAmp bits

Bit

Symbol

Description

7 to 6

set_cw_amplitude

Allows reducing the output amplitude of the transmitter by a fix

value.

Four different preset values that are subtracted from TVDD

can be selected:

0: TVDD -100 mV

1: TVDD -250 mV

2: TVDD -500 mV

3: T_VDD-1000 mV

5

RFU

-

4 to 0

set_residual_ carrier Set the residual carrier percentage. refer to section

Section 8.6.2.

9.8.3 TxCon

Table 128.ꢀTxCon register (address 2Ah)

Bit

7

6

5

OvershootT2

r/w

4

3

2

1

0

Symbol

CwMax

r/w

TxInv

r/w

TxSel

r/w

Access

rights

Table 129.ꢀTxCon bits

Bit

Symbol

Description

7 to 4

OvershootT2 Specifies the length (number of carrier clocks) of the additional

modulation for overshoot prevention. Refer to section Section 8.6.2.1.

3

Cwmax

Set amplitude of continuous wave carrier to the maximum.

If set, set_cw_amplitude in Register TxAmp has no influence on the

continuous amplitude.

2

TxInv

TxSel

If set, the resulting modulation signal defined by TxSel is inverted

1 to 0

Defines which signal is used as source for modulation

00b ... no modulation

01b ... TxEnvelope

10b ... SigIn

11b ... RFU

9.8.4 Txl

Table 130.ꢀTxl register (address 2Bh)

Bit

7

6

5

OvershootT1

r/w

4

3

2

1

0

Symbol

tx_set_iLoad

r/w

Access

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Table 131.ꢀTxl bits

Bit

Symbol

Description

7 to 4

3 to 0

OvershootT1 Overshoot value for Timer1. Refer to Section Section 8.6.2.1.

tx_set_iLoad

Factory trim value, sets the expected Tx load current. This value is

used to control the modulation index in an optimized way dependent

on the expected TX load current.

9.9 Transmitter CRC configuration registers

9.9.1 TxCrcPreset

Table 132.ꢀTXCrcPreset register (address 2Ch)

Bit

7

RFU

-

6

5

4

3

2

1

TxCRCInvert

r/w

0

Symbol

TXPresetVal

r/w

TxCRCtype

r/w

TxCRCEn

r/w

Access

rights

Table 133.ꢀTxCrcPreset bits

Bit

Symbol

Description

7

RFU

-

6 to 4

3 to 2

TXPresetVal

TxCRCtype

Specifies the CRC preset value for transmission (see following table).

Defines which type of CRC (CRC8/CRC16/CRC5) is calculated:

• 00h -- CRC5

• 01h -- CRC8

• 02h -- CRC16

• 03h -- RFU

1

0

TxCRCInvert if set, the resulting CRC is inverted and attached to the data frame

(ISO/IEC 3309)

TxCRCEn

if set, a CRC is appended to the data stream

Table 134.ꢀTransmitter CRC preset value configuration

TXPresetVal[6...4]

CRC16

0000h

6363h

A671h

FFFEh

-

CRC8

CRC5

0h

1h

2h

3h

4h

5h

6h

7h

00h

12h

BFh

-

FDh

-

User defined

FFFFh

User defined

FFh

User defined

1Fh

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Remark: User-defined CRC preset values can be configured by EEPROM (see section

Section 8.7.2.1, Table 31.

9.9.2 RxCrcCon

Table 135.ꢀRxCrcCon register (address 2Dh)

Bit

7

RxForceCRCWrite

r/w

6

5

4

3

2

1

RxCRCInvert

r/w

0

Symbol

RXPresetVal

r/w

RXCRCtype

r/w

RxCRCEn

r/w

Access

rights

Table 136.ꢀRxCrcCon bits

Bit

Symbol

Description

7

RxForceCrc

Write

If set, the received CRC byte(s) are copied to the FIFO.

If cleared CRC Bytes are only checked, but not copied to the FIFO.

This bit has to be always set in case of a not byte aligned CRC (e.g.

ISO/IEC 18000-3 mode 3/ EPC Class-1HF)

6 to 4

3 to 2

RXPresetVal

RxCRCtype

Defines the CRC preset value (Hex.) for transmission. (see following

table).

Defines which type of CRC (CRC8/CRC16/CRC5) is calculated:

• 00h -- CRC5

• 01h -- CRC8

• 02h -- CRC16

• 03h -- RFU

1

0

RxCrcInvert

RxCrcEn

If set, the CRC check is done for the inverted CRC.

If set, the CRC is checked and in case of a wrong CRC an error flag is

set. Otherwise the CRC is calculated but the error flag is not modified.

Table 137.ꢀReceiver CRC preset value configuration

RXPresetVal[6...4]

CRC16

0000h

6363h

A671h

FFFEh

-

CRC8

CRC5

0h

1h

2h

3h

4h

5h

6h

7h

00h

12h

BFh

-

FDh

-

User defined

FFFFh

User defined

FFh

User defined

1Fh

9.10 Transmitter data configuration registers

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9.10.1 TxDataNum

Table 138.ꢀTxDataNum register (address 2Eh)

Bit

7

6

5

4

KeepBitGrid

r/w

3

2

1

TxLastBits

r/w

0

Symbol

RFU

RFU-

DataEn

r/w

Access

rights

Table 139.ꢀTxDataNum bits

Bit

7 to 5

4

Symbol

RFU

Description

-

KeepBitGrid

If set, the time between consecutive transmissions starts is a multiple

of one ETU. If cleared, consecutive transmissions can even start

within one ETU

3

DataEn

If cleared - it is possible to send a single symbol pattern.

If set - data is sent.

2 to 0

TxLastBits

Defines how many bits of the last data byte to be sent. If set to 000b,

all bits of the last data byte are sent.

Note - bits are skipped at the end of the byte.

Example - Data byte B2h (sent LSB first).

TxLastBits = 011b (3h) => 010b (LSB first) is sent

TxLastBits = 110b (6h) => 010011b (LSB first) is sent

9.10.2 TxDATAModWidth

Transmitter data modulation width register

Table 140.ꢀTxDataModWidth register (address 2Fh)

Bit

7

6

5

4

3

2

1

0

Symbol

DModWidth

r/w

Access

rights

Table 141.ꢀTxDataModWidth bits

Bit

Symbol

Description

7 to 0

DModWidth

Specifies the length of a pulse for sending data with enabled pulse

modulation. The length is given by the number of carrier clocks + 1.

A pulse can never be longer than from the start of the pulse to the

end of the bit. The starting position of a pulse is given by the setting

of TxDataMod.DPulseType. Note: This register is only used if Miller

modulation (ISO/IEC 14443A PCD) is used. The settings are also

used for the modulation width of start and/or stop symbols.

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9.10.3 TxSym10BurstLen

If a protocol requires a burst (an unmodulated subcarrier) the length can be defined with

this TxSymBurstLen, the value high or low can be defined by TxSym10BurstCtrl.

Table 142.ꢀTxSym10BurstLen register (address 30h)

Bit

7

RFU

-

6

5

4

3

RFU

-

2

1

Sym0Burst Len

r/w

0

Symbol

Sym1Burst Len

r/w

Access

rights

Table 143.ꢀTxSym10BurstLen bits

Bit

7

Symbol

Description

RFU

-

6 to 4

Sym1BurstLen Specifies the number of bits issued for symbol 1 burst. The 3 bits

encodes a range from 8 to 256 bit:

00h - 8bit

01h - 16bit

02h - 32bit

03h - 48bit

04h - 64bit

05h - 96bit

06h - 128bit

07h - 256bit

3

RFU

-

2 to 0

Sym0BurstLen Specifies the number of bits issued for symbol 0 burst. The 3 bits

encodes a range from 8 to 256 bit:

00h - 8bit

01h - 16bit

02h - 32bit

03h - 48bit

04h - 64bit

05h - 96bit

06h - 128bit

07h - 256bit

9.10.4 TxWaitCtrl

Table 144.ꢀTxWaitCtrl register (address 31h); reset value: C0h

Bit

7

TxWaitStart

r/w

6

5

4

TxWait High

r/w

3

2

1

TxStopBitLength

r/w

0

Symbol

TxWaitEtu

r/w

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Table 145.ꢀTXWaitCtrl bits

Bit

Symbol

Description

7

TxWaitStart

If cleared, the TxWait time is starting at the End of the send data

(TX).

If set, the TxWait time is starting at the End of the received data

(RX).

6

TxWaitEtu

If cleared, the TxWait time is TxWait × 16/13.56 MHz.

If set, the TxWait time is TxWait × 0.5 / DBFreq (DBFreq is the

frequency of the bit stream as defined by TxDataCon).

5 to 3

2 to 0

TxWait High

Bit extension of TxWaitLo. TxWaitCtrl bit 5 is MSB.

TxStopBitLength

Defines stop-bits and EGT (= stop-bit + extra guard time EGT) to

be sent:

0h: no stop-bit, no EGT

1h: 1 stop-bit, no EGT

2h: 1 stop-bit + 1 EGT

3h: 1 stop-bit + 2 EGT

4h: 1 stop-bit + 3 EGT

5h: 1 stop-bit + 4 EGT

6h: 1 stop-bit + 5 EGT

7h: 1 stop-bit + 6 EGT

Note: This is only valid for ISO/IEC14443 Type B

9.10.5 TxWaitLo

Table 146.ꢀTxWaitLo register (address 32h)

Bit

7

6

5

4

3

2

1

0

Symbol

TxWaitLo

r/w

Access

rights

Table 147.ꢀTxWaitLo bits

Bit

Symbol

Description

7 to 0

TxWaitLo

Defines the minimum time between receive and send or between two

send data streams

Note: TxWait is a 11bit register (additional 3 bits are in the TxWaitCtrl

register)!


型号：	CLRC66103HN
厂家：	NXP
描述：	High performance NFC frontend CLRC661 plus
文件：	总152页 (文件大小：1576K)
中文：	中文翻译
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