DAC1005D650HW/C1_技术文档

DAC1005D650

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

Rev. 01 — 28 July 2009

Product data sheet

1. General description

The DAC1005D650 is a high-speed 10-bit dual-channel Digital-to-Analog Converter

(DAC) with selectable 2×, 4× or 8× interpolating ﬁlters optimized for multi-carrier wireless

transmitters.

Thanks to its digital on-chip modulation, the DAC1005D650 allows the complex I and Q

inputs to be converted up from BaseBand (BB) to IF. The mixing frequency is adjusted

using a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator

(NCO). The phase is controlled by a 16-bit register.

Two modes of operation are available: separate data ports or a single interleaved

high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into

its original I and Q data and then latched.

The DAC1005D650 also includes a 2×, 4× and 8× clock multiplier which provides the

appropriate internal clocks and an internal regulator to adjust the output full-scale current.

2. Features

I Dual 10-bit resolution

I IMD3: 79 dBc; f_s= 640 Msps; f_o= 96 MHz

I SFDR: 75 dBc; f_data= 80 MHz;

f_s= 640 Msps; f_o= 19 MHz; PLL on

I Typical 0.95 W power dissipation at 4×

interpolation

I 650 Msps maximum update rate

I Selectable 2×, 4× or 8× interpolation

ﬁlters

I Input data rate up to 160 Msps

I Power-down and Sleep modes

I Very low noise cap-free integrated PLL I Differential scalable output current from

1.6 mA to 20 mA

I 32-bit programmable NCO frequency I On-chip 1.25 V reference

I Dual-port or Interleaved data modes I External analog offset control

(10-bit auxiliary DACs)

I 1.8 V and 3.3 V power supplies

I LVDS compatible clock

I Two’s complement or binary offset

data format

I Internal digital offset control

I Inverse (sin x) / x function

I Fully compatible SPI port

I 3.3 V CMOS input buffers

I Industrial temperature range from

−40 °C to +85 °C

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

3. Applications

I Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA

I Communication: LMDS/MMDS, point-to-point

I Direct Digital Synthesis (DDS)

I Broadband wireless systems

I Digital radio links

I Instrumentation

I Automated Test Equipment (ATE)

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

DAC1005D650HW/C1 HTQFP100

plastic thermal enhanced thin quad ﬂat package; 100 leads;

SOT638-1

body 14 × 14 × 1 mm; exposed die pad

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

2 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

6. Pinning information

6.1 Pinning

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V

DDA(3V3)

AUXAP

2

AUXBP

AUXBN

AGND

3

AUXAN

AGND

4

5

V

DDA(1V8)

6

DDA(1V8)

AGND

7

GAPOUT

VIRES

d.n.c.

8

CLKP

CLKN

AGND

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

RESET_N

SCS_N

SCLK

V

DDA(1V8)

d.n.c.

TM1

TM0

DAC1005D650HW

SDIO

SDO

TM3

V

DD(IO)(3V3)

GNDIO

n.c.

Q0

I9

I8

I7

I6

I5

I4

I3

I2

AGND

Q1

Q2

Q3

001aak159

Fig 2. Pin conﬁguration

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

4 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

6.2 Pin description

Table 2.

Symbol

V_DDA(3V3)

AUXAP

AUXAN

AGND

V_DDA(1V8)

AGND

CLKP

CLKN

AGND

V_DDA(1V8)

d.n.c.

TM1

Pin description

1

Type^[1]Description

P

O

G

P

G

I

analog supply voltage 3.3 V

2

auxiliary DAC B output current

complementary auxiliary DAC B output current

analog ground

3

4

5

analog supply voltage 1.8 V

analog ground

6

7

8

clock input

9

I

complementary clock input

analog ground

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

G

P

-

analog supply voltage 1.8 V

do not connect

-

do not connect

I/O

P

G

I

test mode 1 (to connect to DGND)

test mode 0 (to connect to DGND)

input/output buffers supply voltage 3.3 V

input/output buffers ground

I data input bit 9 (MSB)

I data input bit 8

TM0

V_DD(IO)(3V3)

GNDIO

I9

I8

I

I7

I

I data input bit 7

I6

I

I data input bit 6

I5

I

I data input bit 5

I4

I

I data input bit 4

I3

I

I data input bit 3

I2

I

I data input bit 2

V_DDD(1V8)

DGND

I1

P

G

I

digital supply voltage 1.8 V

digital ground

I data input bit 1

I0

I

I data input bit 0 (LSB)

not connected

n.c.

I

n.c.

I

not connected

V_DDD(1V8)

DGND

n.c.

P

G

I

digital supply voltage 1.8 V

digital ground

not connected

n.c.

I

not connected

V_DDD(1V8)

DGND

TM2

P

G

-

digital supply voltage 1.8 V

digital ground

test mode 2 (to connect to DGND)

digital ground

DGND

G

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

5 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

Table 2.

Pin description …continued

Symbol

40

Type^[1]Description

V_DDD(1V8)

Q9/SELIQ

P

I

digital supply voltage 1.8 V

41

Q data input bit 9 (MSB)

select IQ

Q8

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

I

Q data input bit 8

DGND

V_DDD(1V8)

Q7

G

P

I

digital ground

digital supply voltage 1.8 V

Q data input bit 7

Q6

I

Q data input bit 6

Q5

I

Q data input bit 5

Q4

I

Q data input bit 4

DGND

V_DDD(1V8)

Q3

G

P

I

digital ground

digital supply voltage 1.8 V

Q data input bit 3

Q2

I

Q data input bit 2

Q1

I

Q data input bit 1

Q0

I

Q data input bit 0 (LSB)

not connected

n.c.

I

n.c.

I

not connected

n.c.

I

not connected

n.c.

I

not connected

GNDIO

V_DD(IO)(3V3)

TM3

G

P

I/O

O

I/O

I

input/output buffers ground

input/output buffers supply voltage 3.3 V

test mode 3 (to connect to DGND)

SPI data output

SDO

SDIO

SPI data input/output

SPI clock

SCLK

SCS_N

RESET_N

d.n.c.

I

SPI chip select (active LOW)

general reset (active LOW)

do not connect

I

-

VIRES

GAPOUT

V_DDA(1V8)

AGND

AUXBN

AUXBP

V_DDA(3V3)

AGND

V_DDA(1V8)

AGND

V_DDA(1V8)

I/O

P

G

O

P

G

P

G

P

DAC biasing resistor

bandgap input/output voltage

analog supply voltage 1.8 V

analog ground

complementary auxiliary DAC B output current

auxiliary DAC B output current

analog supply voltage 3.3 V

analog ground

analog supply voltage 1.8 V

analog ground

analog supply voltage 1.8 V

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

6 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

Table 2.

Pin description …continued

Type^[1]Description

Symbol

AGND

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

H^[2]

G

P

G

P

G

O

G

-

analog ground

V_DDA(1V8)

AGND

analog supply voltage 1.8 V

analog ground

V_DDA(1V8)

AGND

analog supply voltage 1.8 V

analog ground

IOUTBN

IOUTBP

AGND

complementary DAC B output current

DAC B output current

analog ground

n.c.

not connected

AGND

G

O

G

P

G

P

G

P

G

P

G

analog ground

IOUTAP

IOUTAN

AGND

DAC A output current

complementary DAC A output current

analog ground

V_DDA(1V8)

AGND

analog supply voltage 1.8 V

analog ground

V_DDA(1V8)

AGND

analog supply voltage 1.8 V

analog ground

V_DDA(1V8)

AGND

analog supply voltage 1.8 V

analog ground

V_DDA(1V8)

AGND

analog supply voltage 1.8 V

analog ground

AGND

analog ground

[1] P = power supply

G = ground

I = input

O = output.

[2] H = heatsink (exposed die pad to be soldered).

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

7 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

7. Limiting values

Table 3.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

+4.6

+3.0

Unit

V

V_DD(IO)(3V3)input/output supply voltage (3.3 V)

−0.5

V_DDA(3V3)

V_DDA(1V8)

analog supply voltage (3.3 V)

analog supply voltage (1.8 V)

V

V_DDD(1V8)digital supply voltage (1.8 V)

V

V_I

input voltage

pins CLKP, CLKN, VIRES and GAPOUT

referenced to AGND

V

pins I9 to I0, Q9 to Q0, SDO, SDIO, SCLK,

SCS_N and RESET_N referenced to GNDIO

−0.5

+4.6

V

V_O

output voltage

pins IOUTAP, IOUTAN, IOUTBP, IOUTBN,

AUXAP, AUXAN, AUXBP and AUXBN

referenced to AGND

T_stg

T_amb

T_j

storage temperature

ambient temperature

junction temperature

−55

−45

-

+150

+85

°C

125

8. Thermal characteristics

Table 4.

Symbol

R_th(j-a)

Thermal characteristics

Parameter

Conditions

Typ

Unit

[1]

thermal resistance from junction to ambient

thermal resistance from junction to case

19.8

7.7

K/W

R_th(j-c)

[1] In compliance with JEDEC test board, in free air.

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

8 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

9. Characteristics

Table 5.

V_DDA(1V8)= V_DDD(1V8)= 1.8 V; V_DDA(3V3)= V_DD(IO)(3V3)= 3.3 V; AGND, DGND and GNDIO shorted together;

_amb= −40 °C to +85 °C; typical values measured at T_amb= 25 °C; R_L= 50 Ω; I_O(fs)= 20 mA; maximum sample rate; PLL on;

unless otherwise speciﬁed.

Characteristics

T

Symbol

Parameter

Conditions

Test^[1]

Min

Typ

Max

Unit

V_DD(IO)(3V3)

input/output supply

voltage (3.3 V)

I

3.0

3.3

3.6

V

V_DDA(3V3)

V_DDA(1V8)

V_DDD(1V8)

I_DD(IO)(3V3)

I_DDA(3V3)

I_DDD(1V8)

I_DDA(1V8)

analog supply voltage

(3.3 V)

I

3.0

3.3

1.8

5

3.6

1.9

13

V

analog supply voltage

(1.8 V)

1.7

V

digital supply voltage

(1.8 V)

1.7

V

input/output supply

current (3.3 V)

f_o= 19 MHz; f_s= 640 Msps;

8× interpolation; NCO on

-

mA

analog supply current f_o= 19 MHz; f_s= 640 Msps;

(3.3 V)

48

26

8× interpolation; NCO on

digital supply current

(1.8 V)

f_o= 19 MHz; f_s= 640 Msps;

8× interpolation; NCO on

270

330

309

358

analog supply current f_o= 19 MHz; f_s= 640 Msps;

(1.8 V)

8× interpolation; NCO on

I_DDD

P_tot

digital supply current

for x / (sin x) function only

I

-

67

-

mA

W

total power dissipation f_o= 19 MHz; f_s= 320 Msps;

4× interpolation; NCO off;

C

0.53

DAC B off

f_o= 19 MHz; f_s= 320 Msps;

4× interpolation; NCO off

C

I

-

0.82

0.94

0.95

-

W

f_o= 19 MHz; f_s= 320 Msps;

4× interpolation; NCO on

f_o= 19 MHz; f_s= 640 Msps;

8× interpolation; NCO off

f_o= 19 MHz; f_s= 640 Msps;

8× interpolation; NCO on;

all V_DD

1.18 1.4

f_o= 19 MHz; f_s= 640 Msps;

8× interpolation;

C

-

1.07

-

W

NCO low power on

Power-down mode

full power-down; all V_DD

I

-

0.08 0.13

0.88

W

DAC A and DAC B Sleep

mode; 8× interpolation;

NCO on

-

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

9 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

Table 5.

V_DDA(1V8)= V_DDD(1V8)= 1.8 V; V_DDA(3V3)= V_DD(IO)(3V3)= 3.3 V; AGND, DGND and GNDIO shorted together;

_amb= −40 °C to +85 °C; typical values measured at T_amb= 25 °C; R_L= 50 Ω; I_O(fs)= 20 mA; maximum sample rate; PLL on;

unless otherwise speciﬁed.

Characteristics …continued

T

Symbol Parameter

Clock inputs (CLKP and CLKN)^[2]

Conditions

Test^[1]

Min

Typ

Max

Unit

[3]

V_i

input voltage

CLKP; or CLKN |V_gpd| < 50 mV

|V_gpd| < 50 mV

C

825

-

1575

+100

mV

V_idth

input differential

threshold voltage

−100

R_i

C_i

input resistance

D

-

10

-

MΩ

input capacitance

0.5

pF

Digital inputs (I0 to I13, Q0 to Q13)

V_IL

V_IH

I_IL

LOW-level input

voltage

C

I

GNDIO -

1.0

V

HIGH-level input

voltage

2.3

-

V_DD(IO)(3V3)

V

LOW-level input

current

V_IL= 1.0 V

V_IH= 2.3 V

-

40

80

-

µA

I_IH

HIGH-level input

current

I

Digital inputs (SDO, SDIO, SCLK, SCS_N and RESET_N)

V_IL

V_IH

I_IL

LOW-level input

voltage

C

I

GNDIO -

1.0

V

HIGH-level input

voltage

2.3

-

V_DD(IO)(3V3)

V

LOW-level input

current

V_IL= 1.0 V

V_IH= 2.3 V

-

20

-

nA

I_IH

HIGH-level input

current

I

Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN)

I_O(fs)

full-scale output

current

register value = 00h

default register

C

D

C

-

1.6

20

-

mA

-

mA

V_O

output voltage

compliance range

1.8

V_DDA(3V3)

V

R_o

output resistance

output capacitance

DAC monotonicity

offset error variation

gain error variation

-

250

3

-

kΩ

C_o

pF

N_DAC(mono)

∆E_O

∆E_G

guaranteed

8

bit

6

ppm/°C

18

Reference voltage output (GAPOUT)

V_O(ref)

∆V_O(ref)

I_O(ref)

reference output

voltage

T_amb= 25 °C

I

1.2

1.25 1.29

V

reference output

voltage variation

C

D

-

117

40

-

ppm/°C

µA

reference output

current

external voltage 1.25 V

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

10 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

Table 5.

V_DDA(1V8)= V_DDD(1V8)= 1.8 V; V_DDA(3V3)= V_DD(IO)(3V3)= 3.3 V; AGND, DGND and GNDIO shorted together;

_amb= −40 °C to +85 °C; typical values measured at T_amb= 25 °C; R_L= 50 Ω; I_O(fs)= 20 mA; maximum sample rate; PLL on;

unless otherwise speciﬁed.

Characteristics …continued

T

Symbol Parameter

Conditions

Test^[1]

Min

Typ

Max

Unit

Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)

I_O(aux)

auxiliary output current differential outputs

auxiliary output voltage compliance range

I

-

2.2

-

mA

V

V_O(aux)

C

D

0

-

2

-

N_DAC(aux)monoauxiliary DAC

monotonicity

guaranteed

10

bit

Input timing (see Figure 10)

f_data

data rate

Dual-port mode input

C

-

160

MHz

t_w(CLK)

CLK pulse width

input hold time

input set-up time

1.5

1.1

T

-

_data− 1.5 ns

t_h(i)

ns

t_su(i)

-

Output timing

f_s

t_s

sampling frequency

settling time

C

D

-

650

-

Msps

ns

to ±0.5 LSB

20

NCO frequency range; f_s= 640 Msps

f_NCO

NCO frequency

register value = 00000000h

register value = FFFFFFFFh

D

-

0

-

MHz

Hz

640

f_step

step frequency

0.149 -

Low-power NCO frequency range; f_DAC= 640 MHz

f_NCO

NCO frequency

register value = 00000000h

register value = F8000000h

D

-

0

-

MHz

620

20

f_step

step frequency

Dynamic performance; PLL on

SFDR

spurious-free dynamic f_data= 80 MHz; f_s= 320 Msps;

range

B = f_data/ 2

f_o= 35 MHz at 0 dBFS

C

-

82

-

dBc

f_data= 80 MHz; f_s= 640 Msps;

B = f_data/ 2

f_o= 4 MHz at 0 dBFS

f_o= 19 MHz at 0 dBFS

I

-

76

75

-

dBc

f_data= 160 MHz; f_s= 640 Msps;

B = f_data/ 2

f_o= 70 MHz at 0 dBFS

C

-

82

-

dBc

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

11 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

Table 5.

V_DDA(1V8)= V_DDD(1V8)= 1.8 V; V_DDA(3V3)= V_DD(IO)(3V3)= 3.3 V; AGND, DGND and GNDIO shorted together;

_amb= −40 °C to +85 °C; typical values measured at T_amb= 25 °C; R_L= 50 Ω; I_O(fs)= 20 mA; maximum sample rate; PLL on;

unless otherwise speciﬁed.

Characteristics …continued

T

Symbol

Parameter

Conditions

Test^[1]

Min

Typ

Max

Unit

SFDR_RBW

restricted bandwidth

f_s= 640 Msps; f_o= 96 MHz at

spurious-free dynamic 0 dBFS

range

2.51 MHz ≤ f_offset≤ 2.71 MHz;

I

-

−89

−88

−89

−83

-

dBc

B = 30 kHz

2.71 MHz ≤ f_offset≤ 3.51 MHz;

B = 30 kHz

3.51 MHz ≤ f_offset≤ 4 MHz;

B = 30 kHz

−81

−67

4 MHz ≤ f_offset≤ 40 MHz;

B = 1 MHz

IMD3

third-order

intermodulation

distortion

f_s= 320 Msps; 4× interpolation

f_o1= 49 MHz; f_o2= 51 MHz

f_o1= 95 MHz; f_o2= 97 MHz

f_s= 640 Msps; 8× interpolation

f_o1= 95 MHz; f_o2= 97 MHz

[4]

C

-

81

80

-

dBc

[4]

I

67

-

79

77

-

dBc

f_o1= 152 MHz; f_o2= 154 MHz C

ACPR

adjacent channel

power ratio

f_data= 76.8 MHz; f_s= 614.4

Msps; f_o= 96 MHz

1 carrier; B = 5 MHz

2 carriers; B = 10 MHz

4 carriers; B = 20 MHz

I

-

64

61

60

-

dB

C

f_data= 153.6 MHz; f_s= 614.4

Msps; f_o= 115.2 MHz

1 carrier; B = 5 MHz

2 carriers; B = 10 MHz

4 carriers; B = 20 MHz

C

-

67

63

60

-

dB

f_data= 153.6 MHz; f_s= 614.4

Msps; f_o= 153.6 MHz

1 carrier; B = 5 MHz

2 carriers; B = 10 MHz

4 carriers; B = 20 MHz

C

-

65

63

60

-

dB

NSD

noise spectral density f_s= 640 Msps; 8× interpolation;

f_o= 19 MHz at 0 dBFS

noise shaper disabled

noise shaper enabled

C

-

−138

−139

-

dBm/Hz

[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.

[2] CLKP and CLKN inputs are at differential LVDS levels. An external differential resistor with a value of between 80 Ω and 120 Ω should

be connected across the pins (see Figure 8).

[3] |V_gpd| represents the ground potential difference voltage. This is the voltage that results from current ﬂowing through the ﬁnite resistance

and the inductance between the receiver and the driver circuit ground.

[4] IMD3 rejection with −6 dBFS/tone.

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

12 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

10. Application information

10.1 General description

The DAC1005D650 is a dual 10-bit DAC operating at up to 650 Msps. Each DAC consists

of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 4-bit binary

weighted sub-DAC.

With an input data rate of up to 160 MHz, and a maximum output sampling rate of

650 Msps, the DAC1005D650 allows more ﬂexibility for wide bandwidth and multi-carrier

systems. Combined with its quadrature modulator and its 32-bit NCO, the DAC1005D650

simpliﬁes the frequency selection of the system. This is also possible because of the 2×,

4× and 8× interpolation ﬁlters that remove undesired images.

Two modes are available for the digital input. In the Dual-port mode, each DAC uses its

own data input line. In Interleaved mode, both DACs use the same data input line.

Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and

IOUTBP/IOUTBN. This provides a full-scale output current (I_O(fs)) up to 20 mA. An internal

reference is available for the reference current which is externally adjustable using pin

VIRES.

There are embedded features which provide analog offset correction (internal auxiliary

DACs), digital offset control and gain adjustment. All the functions can be set using a SPI.

The DAC1005D650 operates at both 3.3 V and 1.8 V using separate digital and analog

power supplies. The digital input is 3.3 V compliant and the clock input is LVDS compliant.

10.2 Serial interface (SPI)

10.2.1 Protocol description

The DAC1005D650 serial interface is a synchronous serial communication port allowing

easy interfacing with many industry microprocessors. It provides access to the registers

that deﬁne the operating modes of the chip in both write and read modes.

This interface can be conﬁgured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire

type (SDIO and SDO as unidirectional pin, input and output port respectively). In both

conﬁgurations, SCLK acts as the serial clock, and SCS_N acts as the serial chip select

bar.

Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW

assertion to drive the chip with between 2 to 5 bytes, depending on the content of the

instruction byte (see Table 7).

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DAC1005D650

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Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

RESET_N

(optional)

SCS_N

SCLK

SDIO

R/W

N1

N0

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SDO

(optional)

001aaj812

R/W indicates the mode access (see Table 6).

Fig 3. SPI protocol

Table 6.

Read or Write mode access description

Description

R/W

0

Write mode operation

1

Read mode operation

In Table 7 N1 and N0 indicate the number of bytes transferred after the instruction byte.

Table 7.

Number of bytes to be transferred

N1

0

N0

0

Number of bytes

1 byte transferred

2 bytes transferred

3 bytes transferred

4 bytes transferred

0

1

0

1

A0 to A4 indicates which register is being addressed. In the case of a multiple transfer,

this address concerns the ﬁrst register after which the next registers follow directly in

decreasing order according to Table 9 “Register allocation map”.

10.2.2 SPI timing description

SPI can operate at a frequency of up to 15 MHz. The SPI timing is shown in Figure 4.

t

w(RESET_N)

RESET_N

(optional)

50 %

t

h(SCS_N)

su(SCS_N)

SCS_N

50 %

t

w(SCLK)

SCLK

SDIO

50 %

t

h(SDIO)

su(SDIO)

t

001aaj813

Fig 4. SPI timing diagram

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The SPI timing characteristics are given in Table 8.

Table 8.

SPI timing characteristics

Symbol

f_SCLK

Parameter

Min

-

Typ

Max

Unit

MHz

ns

SCLK frequency

SCLK pulse width

SCS_N set-up time

SCS_N hold time

SDIO set-up time

SDIO hold time

-

15

-

t_w(SCLK)

t_{su(SCS_N)}

t_{h(SCS_N)}

t_su(SDIO)

t_h(SDIO)

30

20

10

5

-

ns

-

ns

-

ns

-

ns

t_{w(RESET_N)}

RESET_N pulse width

30

-

ns

10.2.3 Detailed descriptions of registers

An overview of the details for all registers is provided in Table 9.

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Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

10.2.4 Registers detailed description

Please refer to Table 9 for a register overview and their default values. In the following

tables, all default results are shown highlighted.

Table 10. COMMon register (address 00h) bit description

Default settings are shown highlighted.

Bit

Symbol

Access Value Description

serial interface bus type

7

3W_SPI

R/W

0

4 wire SPI

1

3 wire SPI

6

5

3

2

1

SPI_RST

CLK_SEL

MODE_SEL

CODING

IC_PD

serial interface reset

no reset

0

1

performs a reset on all registers except 00h

data input latch

at CLK rising edge

at CLK falling edge

input data mode

dual-port

0

1

0

1

interleaved

coding

0

binary

1

two’s compliment

power-down

0

disabled

1

all circuits (digital and analog, except SPI)

are switched off

0

GAP_PD

R/W

internal bandgap power-down

power-down disabled

0

1

internal bandgap references are switched off

Table 11. TXCFG register (address 01h) bit description

Default settings are shown highlighted.

Bit

Symbol

Access Value Description

7

NCO_ON

R/W

NCO

disabled (the NCO phase is reset to 0°)

0

1

enabled

6

NCO_LP_SEL

low-power NCO

disabled

0

1

NCO frequency and phase given by the ﬁve

MSBs of the registers 06h and 08h

respectively

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Table 11. TXCFG register (address 01h) bit description …continued

Default settings are shown highlighted.

Bit Symbol Access Value Description

4 to 2 MODULATION[2:0]

R/W

modulation

000

dual DAC: no modulation

001

positive upper single sideband

up-conversion

010

011

100

positive lower single sideband up-conversion

negative upper single sideband up-conversion

negative lower single sideband up-conversion

1 to 0 INTERPOLATION[1:0] R/W

interpolation

f_s= 2f_clk

01

10

11

f_s= 4f_clk

f_s= 8f_clk

Table 12. PLLCFG register (address 02h) bit description

Default settings are shown highlighted.

Bit

Symbol

Access Value Description

7

PLL_PD

R/W

PLL

switched on

0

1

switched off

PLL divider

switched on

switched off

PLL divider factor

f_s= 2 × f_clk

f_s= 4 × f_clk

f_s= 8 × f_clk

PLL phase shift of f_s

0°

5

PLL_DIV_PD

0

1

4 to 3 PLL_DIV[1:0]

00

01

10

2 to 1 PLL_PHASE[1:0]

R/W

00

01

10

120°

240°

0

PLL_POL

DAC clock edge

normal

0

1

inverted

Table 13. FREQNCO_LSB register (address 03h) bit description

Bit Symbol Access Value Description

7 to 0 FREQ_NCO[7:0] R/W lower 8 bits for the NCO frequency setting

-

Table 14. FREQNCO_LISB register (address 04h) bit description

Bit Symbol Access Value Description

7 to 0 FREQ_NCO[15:8]

R/W

-

lower intermediate 8 bits for the NCO

frequency setting

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Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

Table 15. FREQNCO_UISB register (address 05h) bit description

Bit

Symbol

Access Value Description

7 to 0 FREQ_NCO[23:16]

R/W

-

upper intermediate 8 bits for the NCO

frequency setting

Table 16. FREQNCO_MSB register (address 06h) bit description

Bit Symbol Access Value Description

7 to 0 FREQ_NCO[31:24]

R/W

-

most signiﬁcant 8 bits for the NCO frequency

setting

Table 17. PHINCO_LSB register (address 07h) bit description

Bit Symbol Access Value Description

7 to 0 PH_NCO[7:0] R/W lower 8 bits for the NCO phase setting

-

Table 18. PHINCO_MSB register (address 08h) bit description

Bit Symbol Access Value Description

7 to 0 PH_NCO[15:8] R/W most signiﬁcant 8 bits for the NCO phase setting

-

Table 19. DAC_A_Cfg_1 register (address 09h) bit description

Default settings are shown highlighted.

Bit

Symbol

Access Value Description

7

DAC_A_PD

R/W

DAC A power

0

on

1

off

6

DAC_A_SLEEP

DAC A Sleep mode

disabled

0

1

-

enabled

5 to 3 DAC_A_OFFSET[2:0] R/W

lower 3 bits for the DAC A offset

Table 20. DAC_A_Cfg_2 register (address 0Ah) bit description

Bit Symbol Access Value Description

7 to 6 DAC_A_GAIN_COARSE[1:0] R/W

-

least signiﬁcant 2 bits for the DAC A gain

setting for coarse adjustment

5 to 0 DAC_A_GAIN_FINE[5:0]

R/W

the 6 bits for the DAC A ﬁne adjustment

gain setting

Table 21. DAC_A_Cfg_3 register (address 0Bh) bit description

Bit Symbol Access Value Description

7 to 6 DAC_A_GAIN_COARSE[3:2] R/W

-

most signiﬁcant 2 bits for the DAC A gain

setting for coarse adjustment

5 to 0 DAC_A_OFFSET[8:3]

R/W

most signiﬁcant 6 bits for the DAC A

offset

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Table 22. DAC_B_Cfg_1 register (address 0Ch) bit description

Default settings are shown highlighted.

Bit

Symbol

Access Value Description

7

DAC_B_PD

R/W

DAC B power

0

on

1

off

6

DAC_B_SLEEP

DAC B Sleep mode

disabled

0

1

enabled

5 to 3 DAC_B_OFFSET[2:0]

lower 3 bits for the DAC B offset

Table 23. DAC_B_Cfg_2 register (address 0Dh) bit description

Bit Symbol Access Value Description

7 to 6 DAC_B_GAIN_COARSE[1:0] R/W

-

less signiﬁcant 2 bits for the DAC B gain

setting for coarse adjustment

5 to 0 DAC_B_GAIN_FINE[5:0]

R/W

the 6 bits for the DAC B gain setting for

ﬁne adjustment

Table 24. DAC_B_Cfg_3 register (address 0Eh) bit description

Bit Symbol Access Value Description

7 to 6 DAC_B_GAIN_COARSE[3:2] R/W

-

most signiﬁcant 2 bits for the DAC B gain

setting for coarse adjustment

5 to 0 DAC_B_OFFSET[8:3]

R/W

most signiﬁcant 6 bits for the DAC B

offset

Table 25. DAC_Cfg register (address 0Fh) bit description

Default settings are shown highlighted.

Bit

Symbol

Access Value Description

1

MINUS_3DB

R/W

NCO gain

unity

0

1

−3 dB

0

NOISE_SHPER

noise shaper

disabled

enabled

0

1

Table 26. DAC_A_Aux_MSB register (address 1Ah) bit description

Bit Symbol Access Value Description

7 to 0 AUX_A[9:2] R/W most signiﬁcant 8 bits for the auxiliary DAC A

-

Table 27. DAC_A_Aux_LSB register (address 1Bh) bit description

Default settings are shown highlighted.

Bit

Symbol

Access Value Description

7

AUX_A_PD

R/W

auxiliary DAC A power

0

on

1

off

1 to 0

AUX_A[1:0]

lower 2 bits for the auxiliary DAC A

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Table 28. DAC_B_Aux_MSB register (address 1Ch) bit description

Bit

Symbol

Access Value Description

R/W most signiﬁcant 8 bits for the auxiliary DAC B

7 to 0 AUX_B[9:2]

-

Table 29. DAC_B_Aux_LSB register (address 1Dh) bit description

Default settings are shown highlighted.

Bit

Symbol

Access Value Description

7

AUX_B_PD

R/W

auxiliary DAC B power

0

on

1

off

1 to 0

AUX_B[1:0]

lower 2 bits for the auxiliary DAC B

10.3 Input data

The setting applied to MODE_SEL (register 00h[3]; see Table 10 on page 17) deﬁnes

whether the DAC1005D650 operates in the Dual-port mode or in the Interleaved mode

(see Table 30).

Table 30. Mode selection

Bit 3 setting

Function

I9 to I0

Q9 to Q0

active

off

0

1

Dual-port mode (pin Q9)

active

Interleaved mode (pin SELIQ) active

10.3.1 Dual-port mode

The data input for Dual-port mode operation is shown in Figure 5 “Dual-port mode”. Each

DAC has its own independent data input. The data enters the input latch on the rising

edge of the internal clock signal and is transferred to the DAC latch.

FIR 1

FIR 2

FIR 3

LATCH

I

In

2 ×

FIR 1

FIR 2

FIR 3

LATCH

Q

Qn

2 ×

001aaj585

n in Qn = 0 to 9 and for In is 0 to 9.

Fig 5. Dual-port mode

10.3.2 Interleaved mode

The data input for Interleaved mode operation is shown in Figure 6 “Interleaved mode

operation”.

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Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

FIR 1

FIR 2

FIR 3

LATCH

I

2 ×

In

FIR 1

FIR 2

FIR 3

LATCH

Q

Qn/SELIQ

2 ×

001aaj586

n in Qn = 9 and for In is 0 to 9.

Fig 6. Interleaved mode operation

In the Interleaved mode, both DACs use the same data input at twice the Dual-port mode

frequency. Data enters the latch on the rising edge of the internal clock signal. The data is

sent to either latch I or latch Q, see Figure 6 “Interleaved mode operation” and Figure 7

“Interleaved mode timing (8x interpolation, latch on rising edge)”.

The SELIQ input (pin 41) allows the synchronization of the internally de-multiplexed I and

Q channels.

In

N

N + 1

N + 2

N + 3

N + 4

N + 5

SELIQ

(synchronous alternative)

SELIQ

(asynchronous alternative 1)

SELIQ

(asynchronous alternative 2)

CLK

dig

Latch I output

Latch Q output

XX

N

N + 2

N + 3

N + 1

001aaj814

Fig 7. Interleaved mode timing (8x interpolation, latch on rising edge)

SELIQ can be either a synchronous or asynchronous (single rising edge, single pulse)

signal. The ﬁrst data bits following the SELIQ rising edge are sent in channel I and the

following data bits are sent in channel Q. After this, the data is distributed alternately

between both channels.

10.4 Input clock

The DAC1005D650 can operate with a clock frequency of 160 MHz in the Dual-port mode

and up to 320 MHz in the Interleaved mode. The input clock is LVDS (see Figure 8) but it

can also be interfaced with CML (see Figure 9).

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Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

Z = 50 Ω

CLKP

LVDS

Zdiff =

100 Ω

Z = 50 Ω

CLKN

001aah021

Fig 8. LVDS clock conﬁguration

V

DDA(1V8)

1.1 kΩ

Z = 50 Ω

100 nF

CLKP

55 Ω

LVDS

CML

Zdiff =

100 Ω

55 Ω

Z = 50 Ω

100 nF

CLKN

100 nF

2.2 kΩ

AGND

001aah020

Fig 9. Interfacing CML to LVDS

10.5 Timing

The DAC1005D650 can operate at an update rate (f_s) of up to 650 Msps and with an input

data rate (f_data) of up to 160 MHz. The input timing is shown in Figure 10 “Input timing

diagram”.

t

h(i)

su(i)

90 %

In/Qn

N

N + 1

N + 2

CLK

(CLKP-CLKN)

50 %

t

w(CLK)

001aaj815

n in Qn = 0 to 9 and for In is 0 to 9.

Fig 10. Input timing diagram

The typical performances are measured at 50 % duty cycle but any timing within the limits

of the characteristics will not alter the performance.

In Table 31 “Frequencies”, the links between internal and external clocking are deﬁned.

The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see Table 12 “PLLCFG register

(address 02h) bit description”) allows the frequency between the digital part and the DAC

core to be adjusted.

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DAC1005D650

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Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

Table 31. Frequencies

Mode

CLK input Input data rate Interpolation Update rate PLL_DIV[1:0]

(MHz)

160

80

(MHz)

160

80

(Msps)

Dual-port

2×

4×

8×

2×

4×

8×

320

01 (/4)

10 (/8)

00 (/2)

01 (/4)

Dual-port

640

Dual-port

640

Interleaved

320

160

320

160

320

640

The settings applied to PLL_PHASE[1:0] (register 02h[2:1]) and PLL_POL

(register 02h[0]), allows adjustment of the phase and polarity of the sampling clock. This

occurs at the input of the DAC core and depends mainly on the sampling frequency. Some

examples are given in Table 32 “Sample clock phase and polarity examples”.

Table 32. Sample clock phase and polarity examples

Mode

Input data rate Interpolation Update rate PLL_PHASE PLL_POL

(MHz)

(Msps)

[1:0]

Dual-port

Interleaved

80

2×

4×

8×

2×

4×

8×

160

01

1

0

1

0

1

80

320

01

80

640

01

160

01

320

01

640

01

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DAC1005D650

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Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

10.6 FIR ﬁlters

The DAC1005D650 integrates three selectable Finite Impulse Response (FIR) ﬁlters

which enable the device to use interpolation rates of 2×, 4× or 8×.

All three interpolation ﬁlters have a stop-band attenuation of at least 80 dBc and a

pass-band ripple of less than 0.0005 dB.

The coefﬁcients of the interpolation ﬁlters are given in Table 33 “Interpolation ﬁlter

coefﬁcients”.

Table 33. Interpolation ﬁlter coefﬁcients

First interpolation ﬁlter^[1]

Second interpolation ﬁlter^[1]Third interpolation ﬁlter^[1]

Lower

H(1)

Upper

H(55)

H(54)

H(53)

H(52)

H(51)

H(50)

H(49)

H(48)

H(47)

H(46)

H(45)

H(44)

H(43)

H(42)

H(41)

H(40)

H(39)

H(38)

H(37)

H(36)

H(35)

H(34)

H(33)

H(32)

H(31)

H(30)

H(29)

Value

−4

Lower

Upper

Value

Lower

Upper

Value

H(1)

H(23)

−2

H(1)

H(15)

−39

H(2)

0

H(2)

H(22)

0

H(2)

H(14)

0

H(3)

13

H(3)

H(21)

17

H(3)

H(13)

273

H(4)

0

H(4)

H(20)

0

H(4)

H(12)

0

H(5)

−34

0

H(5)

H(19)

−75

H(5)

H(11)

−1102

H(6)

H(18)

0

H(6)

H(10)

0

H(7)

72

H(7)

H(17)

238

H(7)

H(9)

4964

H(8)

0

H(8)

H(16)

0

H(8)

-

8192

H(9)

−138

0

H(9)

H(15)

−660

-

H(10)

H(11)

H(12)

H(13)

H(14)

H(15)

H(16)

H(17)

H(18)

H(19)

H(20)

H(21)

H(22)

H(23)

H(24)

H(25)

H(26)

H(27)

H(28)

H(10)

H(14)

0

245

0

H(11)

H(13)

2530

H(12)

-

4096

−408

0

-

650

0

−1003

0

1521

0

−2315

0

3671

0

−6642

0

20756

32768

[1] H(n) is the digital ﬁlter coefﬁcient.

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Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

10.7 Quadrature modulator and NCO

The quadrature modulator allows the 10-bit I and Q data to be mixed with the carrier

signal generated by the Numerically Controlled Oscillator (NCO).

The frequency of the NCO is programmed over 32-bit and allows the sign of the sine

component to be inverted in order to operate positive or negative, lower or upper single

sideband up-conversion.

10.7.1 NCO in 32-bit

When using the NCO, the frequency can be set by the four registers FREQNCO_LSB,

FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits.

The frequency for the NCO in 32-bit is calculated as follows:

M × f _s

2³²

f _NCO

=

(1)

----------------

where M is the decimal representation of FREQ_NCO[31:0].

The phase of the NCO can be set from 0° to 360° by both registers PHINCO_LSB and

PHINCO_MSB over 16 bits.

The default setting is f_NCO= 96 MHz when f_s= 640 Msps and the default phase is 0°.

10.7.2 Low-power NCO

When using the low-power NCO, the frequency can be set by the 5 MSB of register

FREQNCO_MSB.

The frequency for the low-power NCO is calculated as follows:

M × f _s

2⁵

f _NCO

=

(2)

----------------

where M is the decimal representation of FREQ_NCO[31:27].

The phase of the low-power NCO can be set by the 5 MSB of the register PHINCO_MSB.

10.7.3 Minus 3 dB

During normal use, a full-scale pattern will also be full scale at the output of the DAC.

Nevertheless, when the I and Q data are simultaneously close to full scale, some clipping

can occur and the Minus_3dB function can be used to reduce gain by 3 dB in the

modulator. This is to keep a full-scale range at the output of the DAC without added

interferers.

10.8 x / (sin x)

Due to the roll-off effect of the DAC, a selectable FIR ﬁlter is inserted to compensate for

the (sin x) / x effect. This ﬁlter introduces a DC loss of 3.4 dB. The coefﬁcients are

represented in Table 34 “Inversion ﬁlter coefﬁcients”.

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Table 34. Inversion ﬁlter coefﬁcients

First interpolation ﬁlter^[1]

Lower

H(1)

H(2)

H(3)

H(4)

H(5)

Upper

H(9)

H(8)

H(7)

H(6)

-

Value

2

−4

10

−35

401

[1] H(n) is the digital ﬁlter coefﬁcient.

10.9 DAC transfer function

The full-scale output current for each DAC is the sum of the two complementary current

outputs:

I_{O( fs)}= I_IOUTP+ I_IOUTN

(3)

The output current depends on the digital input data:

DATA

1023

I_IOUTP= I_{O( fs)}

×

(4)

(5)

---------------

1023 – DATA

---------------------------------

1023

I_IOUTN= I_{O( fs)}

The setting applied to CODING (register 00h[2]; see Table 9 “Register allocation map”)

deﬁnes whether the DAC1005D650 operates with a binary input or a two’s complement

input.

Table 35 “DAC transfer function” shows the output current as a function of the input data,

when I_O(fs)= 20 mA.

Table 35. DAC transfer function

Data

(Decimal)

I9/Q9 to I0/Q0

Binary

IOUTP

IOUTN

Two’s complement

10 0000 0000

...

0

00 0000 0000

...

0 mA

...

20 mA

...

512

...

10 0000 0000

...

00 0000 0000

...

10 mA

...

10 mA

...

1023

11 1111 1111

01 1111 1111

20 mA

0 mA

10.10 Full-scale current

10.10.1 Regulation

The DAC1005D650 reference circuitry integrates an internal bandgap reference voltage

which delivers a 1.25 V reference to the GAPOUT pin. It is recommended to decouple pin

GAPOUT using a 100 nF capacitor.

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

27 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

The reference current is generated using an external resistor of 910 Ω (1 %) connected to

pin VIRES. A control ampliﬁer sets the appropriate full-scale current (I_O(fs)) for both DACs

(see Figure 11 “Internal reference conﬁguration”).

REF.

BANDGAP

100 nF

GAPOUT

AGND

910 Ω

(1 %)

DAC

VIRES

CURRENT

SOURCES

ARRAY

AGND

001aaj816

Fig 11. Internal reference conﬁguration

This conﬁguration is optimum for temperature drift compensation because the bandgap

reference voltage can be matched to the voltage across the feedback resistor.

The DAC current can also be set by applying an external reference voltage to the

non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage

with GAP_PD (register 00h[0]; see Table 10 “COMMon register (address 00h) bit

description”).

10.10.2 Full-scale current adjustment

The default full-scale current (I_O(fs)) is 20 mA. It can be further adjusted for each DAC

using SPI. The adjustment range is between 1.6 mA to 22 mA ± 10 %.

The settings applied to DAC_A_GAIN_COARSE[3:0] (register 0Ah; see Table 20

“DAC_A_Cfg_2 register (address 0Ah) bit description” and register 0Bh; see Table 21

“DAC_A_Cfg_3 register (address 0Bh) bit description”) and to DAC_B_GAIN

COARSE[3:0] (register 0Dh; see Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit

description” and register 0Eh; see Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit

description”) deﬁne the coarse variation of the full-scale current (see Table 36 “I_O(fs)

coarse adjustment”).

Table 36. I_O(fs)coarse adjustment

Default settings are shown highlighted.

DAC_GAIN_COARSE[3:0]

I_O(fs)(mA)

Decimal

Binary

0000

0001

0010

0011

0100

0101

0110

0111

0

1

2

3

4

5

6

7

1.6

3.0

4.4

5.8

7.2

8.6

10.0

11.4

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

28 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

Table 36. I_O(fs)coarse adjustment …continued

Default settings are shown highlighted.

DAC_GAIN_COARSE[3:0]

I_O(fs)(mA)

Decimal

Binary

8

1000

1001

1010

1011

1100

1101

1110

1111

12.8

14.2

15.6

17.0

18.5

20.0

21.0

22.0

9

10

11

12

13

14

15

The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see Table 20

“DAC_A_Cfg_2 register (address 0Ah) bit description”) and to DAC_B_GAIN_FINE[5:0]

(register 0Dh; see Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit description”) deﬁne

the ﬁne variation of the full-scale current (see Table 37 “I_O(fs)ﬁne adjustment”).

Table 37. I_O(fs)ﬁne adjustment

Default settings are shown highlighted.

DAC_GAIN_FINE[5:0]

Delta I_O(fs)

Decimal

Two’s complement

−32

...

10 0000

...

−10 %

...

0

00 0000

...

0

...

+31

01 1111

+10 %

The coding of the ﬁne gain adjustment is two’s complement.

10.11 Digital offset adjustment

When the DAC1005D650 analog output is DC connected to the next stage, the digital

offset correction can be used to adjust the common mode level at the output of the DAC. It

adds an offset at the end of the digital part, just before the DAC.

The settings applied to DAC_A_OFFSET[8:0] (register 09h; see Table 19 “DAC_A_Cfg_1

register (address 09h) bit description” and register 0Bh; see Table 21 “DAC_A_Cfg_3

register (address 0Bh) bit description”) and to “DAC_B_OFFSET[8:0]” (register 0Ch; see

Table 22 “DAC_B_Cfg_1 register (address 0Ch) bit description” and register 0Eh; see

Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit description”) deﬁne the range of

variation of the digital offset (see Table 38 “Digital offset adjustment”).

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

29 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

Table 38. Digital offset adjustment

Default settings are shown highlighted.

DAC_OFFSET[8:0]

Offset applied

Decimal

−256

−255

...

Two’s complement

1 0000 0000

1 0000 0001

...

−256

−255

...

−1

1 1111 1111

0 0000 0000

0 0000 0001

...

−1

0

+1

...

+254

+255

0 1111 1110

0 1111 1111

+254

+255

10.12 Analog output

The DAC1005D650 has two output channels each of which produces two complementary

current outputs. These allow the even-order harmonics and noise to be reduced. The pins

are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected using

a load resistor R_Lto the 3.3 V analog power supply (V_DDA(3V3)).

Refer to Figure 12 for the equivalent analog output circuit of one DAC. This circuit consists

of a parallel combination of NMOS current sources, and their associated switches, for

each segment.

V

DDA(3V3)

R

L

R

L

IOUTAP/IOUTBP

IOUTAN/IOUTBN

001aah019

AGND

Fig 12. Equivalent analog output circuit (one DAC)

The cascode source conﬁguration increases the output impedance of the source, thus

improving the dynamic performance of the DAC by introducing less distortion.

The device can provide an output level of up to 2 V_o(p-p)depending on the application, the

following stages and the targeted performances.

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

30 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

10.13 Auxiliary DACs

The DAC1005D650 integrates two auxiliary DACs that can be used to compensate for any

offset between the DAC and the next stage in the transmission path.

Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to

ground). The settings applied to AUX_A[9:0] and AUX_B[9:0] deﬁne the offset data.

I_O(AUX)= I_AUXP+ I_AUXN

(6)

The output current depends on the auxiliary DAC data:

AUX[9:0]

AUXP = I_O(AUX)

AUXN = I_O(AUX)

×

(7)

(8)

-------------------------

1023

(1023–AUX[9:0])

---------------------------------------------

1023

Table 39 “Auxiliary DAC transfer function” shows the output current as a function of the

auxiliary DAC data.

Table 39. Auxiliary DAC transfer function

Default settings are shown highlighted.

Data

0

AUX_A[9:0] and AUX_B[9:0] (binary) I_AUXP

I_AUXN

2.2 mA

...

00 0000 0000

...

0 mA

...

512

...

10 0000 0000

...

1.1 mA

...

1.1 mA

...

1023

11 1111 1111

2.2 mA

0 mA

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

31 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

10.14 Output conﬁguration

10.14.1 Basic output conﬁguration

The use of a differentially-coupled transformer output provides optimum distortion

performance (see Figure 13 “Differential output with transformer; V_o(dif)(p-p)= 1 V”). In

addition, it helps to match the impedance and provides electrical isolation.

3.3 V

50 Ω

0 mA to 20 mA

2:1

IOUTnP

IOUTnN

50 Ω

0 mA to 20 mA

50 Ω

3.3 V

= 2.8 V; V

IOUTnP/IOUTnN; V

= 1 V

o(dif)(p-p)

o(cm)

001aaj817

Fig 13. Differential output with transformer; V_o(dif)(p-p)= 1 V

The DAC1005D650 can operate up to 2 V_o(p-p)differential outputs. In this conﬁguration, it

is recommended to connect the center tap of the transformer to a 62 Ω resistor connected

to the 3.3 V analog power supply, in order to adjust the DC common mode to

approximately 2.7 V (see Figure 14 “Differential output with transformer; V_o(dif)(p-p)= 2 V”).

3.3 V

100 Ω

62 Ω

0 mA to 20 mA

4:1

IOUTnP

IOUTnN

50 Ω

0 mA to 20 mA

100 Ω

3.3 V

= 2.7 V; V

IOUTnP/IOUTnN; V

= 2 V

o(cm)

o(dif)(p-p)

001aaj818

Fig 14. Differential output with transformer; V_o(dif)(p-p)= 2 V

10.14.2 DC interface to an AQM

When the system operation requires to keep the DC component of the spectrum, the

DAC1005D650 can use a DC interface to connect to an Analog Quadrature Modulator

(AQM). In this case, the offset compensation for LO cancellation can be made with the

use of the digital offset control in the DAC.

Figure 15 provides an example of a connection to an AQM with a 1.7 V common mode

input level.

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

32 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

AQM (V

(2)

= 1.7 V)

i(cm)

3.3 V

(1)

51.1 Ω

442 Ω

IOUTnP

IOUTnN

BBP

BBN

0 mA to 20 mA

768 Ω

(1)

IOUTnP/IOUTnN; V

= 2.67 V; V

= 1.98 V

o(dif)(p-p)

o(cm)

(2)

BBP/BBN; V

= 1.7 V; V

= 1.26 V

i(dif)(p-p)

i(cm)

001aaj541

Fig 15. An example of a DC interface to a 1.7 V AQM

Figure 16 provides an example of a connection to an AQM with a 3.3 V_i(cm)common mode

input level.

AQM (V

(2)

= 3.3 V)

i(cm)

3.3 V

5 V

(1)

54.9 Ω

750 Ω

237 Ω

IOUTnP

IOUTnN

BBP

BBN

1.27 kΩ

(1)

(2)

IOUTnP/IOUTnN; V

= 2.75 V; V

= 1.97 V

o(dif)(p-p)

o(cm)

BBP/BBN; V

= 3.3 V; V

= 1.5 V

i(dif)(p-p)

001aaj542

i(cm)

Fig 16. An example of a DC interface to a 3.3 V AQM

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

33 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

The auxiliary DACs can be used to control the offset in a precise range or with precise

steps.

Figure 17 provides an example of a DC interface with the auxiliary DACs to an AQM with a

1.7 V common mode input level.

AQM (V

= 1.7 V)

i(cm)

3.3 V

(1)

(2)

51.1 Ω

442 Ω

IOUTnP

IOUTnN

BBP

BBN

0 mA to 20 mA

1.1 mA (typ.)

698 Ω

AUXnP

AUXnN

51.1 Ω

(1)

IOUTnP/IOUTnN; V

= 2.67 V; V

= 1.94 V

o(dif)(p-p)

o(cm)

(2)

BBP/BBN; V

= 1.7 V; V

= 1.23 V; offset correction up to 36 mV

001aaj543

i(cm)

i(dif)(p-p)

Fig 17. An example of a DC interface to a 1.7 V_i(cm)AQM using auxiliary DACs

Figure 18 provides an example of a DC interface with the auxiliary DACs to an AQM with a

3.3 V common mode input level.

AQM (V

= 3.3 V)

i(cm)

3.3 V

5 V

54.9 Ω

634 kΩ

750 Ω

(1)

(2)

237 Ω

IOUTnP

BBP

BBN

IOUTnN

634 kΩ

442 kΩ

AUXnP

AUXnN

442 kΩ

(1)

IOUTnP/IOUTnN; V

= 2.75 V; V

= 1.96 V

o(dif)(p-p)

o(cm)

(2)

BBP/BBN; V

= 3.3 V; V

= 1.5 V; offset correction up to 36 mV

i(dif)(p-p)

i(cm)

001aaj544

Fig 18. An example of a DC interface to a 3.3 V_i(cm)AQM using auxiliary DACs

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

34 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

The constraints to adjust the interface are the output compliance range of the DAC and

the auxiliary DACs, the input common mode level of the AQM, and the range of offset

correction required.

10.14.3 AC interface to an AQM

When the Analog Quadrature Modulator (AQM) common mode voltage is close to ground,

the DAC1005D650 must be AC-coupled and the auxiliary DACs are needed for offset

correction.

Figure 18 provides an example of a connection to an AQM with a 0.5 V common mode

input level when using auxiliary DACs.

AQM (V

= 0.5 V)

i(cm)

3.3 V

5 V

(1)

(2)

66.5 Ω

2 kΩ

10 nF

IOUTnP

IOUTnN

BBP

BBN

0 mA to 20 mA

1.1 mA (typ.)

174 Ω

AUXnP

AUXnN

34 Ω

(1)

IOUTnP/IOUTnN; V

= 2.65 V; V

= 1.96 V

o(dif)(p-p)

o(cm)

(2)

BBP/BBN; V

= 0.5 V; V

= 1.96 V; offset correction up to 70 mV

001aaj589

i(cm)

i(dif)(p-p)

Fig 19. An example of an AC interface to a 0.5 V_i(cm)AQM using auxiliary DACs

10.15 Power and grounding

In order to obtain optimum performance, it is recommended that the 1.8 V analog power

supplies on pins 5, 11, 71, 77 and 99 should not be connected with those on pins 70, 79,

81, 83, 93, 95 and 97 on the top layer.

To optimize the decoupling, the power supplies should be decoupled with the following

pins:

• V_DDD(1V8): pin 26 with 27; pin 32 with 33; pin 36 with 37; pin 40 with 39; pin 44 with 43

and pin 50 with 49.

• V_DD(IO)(3V3): pin 16 with 17 and pin 60 with 59.

• V_DDA(1V8): pin 5 with 4; pin 6 with 7; pin 11 with 10; pin 71 with 72; pin 77 with 78; pins

79, 81, 83 with 80, 82, 84; pins 93, 95, 97 with 92, 94, 96 and pin 99 with 98.

• V_DDA(3V3): pin 1 with 100 and pin 75 with 76.

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

35 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

10.16 Alternative parts

The following alternative parts are available.

Table 40. Alternative parts

Type number

Description

Sampling frequency

up to 650 Msps

DAC1205D650

dual 12-bit DAC

dual 14-bit DAC

DAC1405D650

up to 650 Msps

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

36 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

11. Package outline

HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads;

body 14 x 14 x 1 mm; exposed die pad

SOT638-1

c

y

exposed die pad side

X

D

h

A

75

51

50

76

Z

E

e

H

E

(A )

3

A

h

2

A

1

w M

p

θ

b

L

p

pin 1 index

L

detail X

26

100

1

25

w M

Z

v

M

A

B

D

b

p

e

D

B

H

D

0

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

θ

UNIT

A

b

c

D

E

e

H

L

p

v

w

y

Z

1

2

3

p

h

D

E

D

E

max.

0.15 1.05

0.05 0.95

0.27 0.20 14.1 7.1 14.1 7.1

0.17 0.09 13.9 6.1 13.9 6.1

16.15 16.15

15.85 15.85

0.75

0.45

1.15 1.15

0.85 0.85

7°

0°

mm

1.2

0.25

0.5

1

0.2 0.08 0.08

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

03-04-07

05-02-02

SOT638-1

MS-026

Fig 20. Package outline SOT638-1 (HTQFP100)

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

37 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

12. Abbreviations

Table 41. Abbreviations

Acronym

BB

Description

BaseBand

CDMA

CML

Code Division Multiple Access

Current Mode Logic

CMOS

DAC

Complementary Metal-Oxide Semiconductor

Digital-to-Analog Converter

FIR

Finite Impulse Response

GSM

Global System for Mobile communications

Intermediate Frequency

IF

IMD3

LISB

Third-order Inter Modulation Distortion

Lower Intermediate Signiﬁcant Byte

Local Multipoint Distribution Service

Least Signiﬁcant Bit

LMDS

LSB

LTE

Long Term Evolution

LVDS

MMDS

MSB

Low-Voltage Differential Signaling

Multichannel Multipoint Distribution Service

Most Signiﬁcant Bit

NCO

Numerically Controlled Oscillator

Negative Metal-Oxide Semiconductor

Phase-Locked Loop

NMOS

PLL

SFDR

SPI

Spurious-Free Dynamic Range

Serial Peripheral Interface

TD-SCDMA

UISB

WCDMA

WiMAX

Time Division-Synchronous Code Division Multiple Access

Upper Intermediate Signiﬁcant Byte

Wideband Code Division Multiple Access

Worldwide Interoperability for Microwave Access

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

38 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

13. Glossary

Spurious-Free Dynamic Range (SFDR): — The ratio between the RMS value of the

reconstructed output sine wave and the RMS value of the largest spurious observed

(harmonic and non-harmonic, excluding DC component) in the frequency domain.

Intermodulation Distortion (IMD): — From a dual-tone digital input sine wave (these two

frequencies being close together), the intermodulation distortion products IMD2 and IMD3

(respectively, 2^ndand 3^rdorder components) are deﬁned below.

IMD2 — The ratio of the RMS value of either tone to the RMS value of the worst 2^ndorder

intermodulation product.

IMD3 — The ratio of the RMS value of either tone to the RMS value of the worst 3^rdorder

intermodulation product.

Restricted Bandwidth Spurious-Free Dynamic Range — The ratio of the RMS value of

the reconstructed output sine wave to the RMS value of the noise, including the

harmonics, in a given bandwidth centered around f_offset

.

14. Revision history

Table 42. Revision history

Document ID

Release date

20090728

Data sheet status

Change notice

Supersedes

DAC1005D650_1

Product data sheet

-

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

39 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

DAC1005D650_1

Product data sheet

Rev. 01 — 28 July 2009

40 of 41

DAC1005D650

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating

17. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

14

Revision history . . . . . . . . . . . . . . . . . . . . . . . 39

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 40

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 40

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40

15.1

15.2

15.3

15.4

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

16

17

Contact information . . . . . . . . . . . . . . . . . . . . 40

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7

8

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal characteristics. . . . . . . . . . . . . . . . . . . 8

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 9

10

10.1

10.2

Application information. . . . . . . . . . . . . . . . . . 13

General description. . . . . . . . . . . . . . . . . . . . . 13

Serial interface (SPI). . . . . . . . . . . . . . . . . . . . 13

Protocol description . . . . . . . . . . . . . . . . . . . . 13

SPI timing description. . . . . . . . . . . . . . . . . . . 14

Detailed descriptions of registers . . . . . . . . . . 15

Registers detailed description . . . . . . . . . . . . 17

Input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Dual-port mode. . . . . . . . . . . . . . . . . . . . . . . . 21

Interleaved mode . . . . . . . . . . . . . . . . . . . . . . 21

Input clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

FIR ﬁlters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Quadrature modulator and NCO. . . . . . . . . . . 26

NCO in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 26

Low-power NCO . . . . . . . . . . . . . . . . . . . . . . . 26

Minus 3 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

x / (sin x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DAC transfer function . . . . . . . . . . . . . . . . . . . 27

Full-scale current . . . . . . . . . . . . . . . . . . . . . . 27

10.2.1

10.2.2

10.2.3

10.2.4

10.3

10.3.1

10.3.2

10.4

10.5

10.6

10.7

10.7.1

10.7.2

10.7.3

10.8

10.9

10.10

10.10.1 Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.10.2 Full-scale current adjustment . . . . . . . . . . . . . 28

10.11

10.12

10.13

10.14

Digital offset adjustment . . . . . . . . . . . . . . . . . 29

Analog output . . . . . . . . . . . . . . . . . . . . . . . . . 30

Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 31

Output conﬁguration . . . . . . . . . . . . . . . . . . . . 32

10.14.1 Basic output conﬁguration . . . . . . . . . . . . . . . 32

10.14.2 DC interface to an AQM . . . . . . . . . . . . . . . . . 32

10.14.3 AC interface to an AQM . . . . . . . . . . . . . . . . . 35

10.15

10.16

Power and grounding . . . . . . . . . . . . . . . . . . . 35

Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 36

11

12

13

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 37

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 38

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 28 July 2009

Document identifier: DAC1005D650_1


型号：	DAC1005D650HW/C1
厂家：	NXP
描述：	Dual 10-bit DAC, up to 650 Msps; 2´ 4´ and 8´ interpolating 双10位DAC ，高达650 Msps的; 2 ×4×和8 ×插值转换器数模转换器
文件：	总41页 (文件大小：193K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC1005D650HW/C1 [NXP]

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