DAC1405D750 [NXP]
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating; 双14位DAC ,高达750 Msps的; 4 ×和8 ×插值型号: | DAC1405D750 |
厂家: | NXP |
描述: | Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating |
文件: | 总43页 (文件大小:313K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Rev. 01 — 10 March 2010
Preliminary data sheet
1. General description
The DAC1405D750 is a high-speed 14-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 4× or 8× interpolating filters optimized for multi-carrier wireless
transmitters.
Thanks to its digital on-chip modulation, the DAC1405D750 allows the complex I and Q
inputs to be converted from BaseBand (BB) to IF. The mixing frequency is adjusted via a
Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and
the phase is controlled by a 16-bit register.
Two modes of operation are available: separate data ports or a single interleaved
high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into
its original I and Q data and then latched.
A 4× and 8× clock multiplier enables the DAC1405D750 to provide the appropriate
internal clocks from the internal PLL. The internal PLL can be bypassed enabling the use
of an external high frequency clock. The voltage regulator enables adjustment of the
output full-scale current.
2. Features and benefits
Dual 14-bit resolution
750 Msps maximum update rate
IMD3: 76 dBc; fs = 737.28 Msps;
fo = 140 MHz
ACPR: 71 dBc; 2-carrier WCDMA;
fs = 737.28 Msps; fo = 153.6 MHz
Selectable 4× or 8× interpolation filters Typical 1.2 W power dissipation at 4×
interpolation, PLL off and 740 Msps
Input data rate up to 185 Msps
Power-down and Sleep modes
Very low noise cap-free integrated PLL Differential scalable output current from
1.6 mA to 22 mA
32-bit programmable NCO frequency On-chip 1.25 V reference
Dual port or Interleaved data modes
External analog offset control
(10-bit auxiliary DACs)
1.8 V and 3.3 V power supplies
LVDS compatible clock
Internal digital offset control
Inverse x / (sin x) function
Fully compatible SPI port
Two’s complement or binary offset
data format
1.8 V/3.3 V CMOS input buffers
Industrial temperature range from
−40 °C to +85 °C
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
3. Applications
Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA
Communication: LMDS/MMDS, point-to-point
Direct Digital Synthesis (DDS)
Broadband wireless systems
Digital radio links
Instrumentation
Automated Test Equipment (ATE)
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
DAC1405D750HW
HTQFP100
plastic thermal enhanced thin quad flat package; 100 leads;
SOT638-1
body 14 × 14 × 1 mm; exposed die pad
DAC1405D750_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 March 2010
2 of 43
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SDO
SCS_N
SDIO
62 63
SPI
SCLK
64
65
2
3
NCO
sin
10-BIT
OFFSET
CONTROL
AUXAP
AUXAN
AUXILIARY
DAC
cos
mixer
10-BIT
GAIN
DAC1405D750
CONTROL
+
90
91
IOUTAP
IOUTAN
18 to 25,
FIR1
FIR2
FIR3
A
x
DAC A
28 to 31, 34, 35
sin x
LATCH
I0 to I14
−
+
I
14
2 ×
2 ×
2 ×
mixer
68
69
VIRES
REFERENCE
BANDGAP
OFFSET
CONTROL
dual port/
interleaved
data modes
GAPOUT
mixer
FIR1
FIR2
FIR3
41, 42,
45 to 48,
51 to 58
LATCH
Q
2 ×
2 ×
2 ×
+
+
+
86
85
IOUTBP
IOUTBN
B
x
Q0 to Q14
DAC B
14
sin x
8
9
10-BIT
GAIN
CONTROL
CLKP
CLKN
CLOCK GENERATOR/PLL
mixer
74
73
COMPLEX MODULATOR
10-BIT
OFFSET
CONTROL
AUXBP
AUXBN
AUXILIARY
DAC
12
13
66
001aal377
SYNCP
SYNCN
RESET_N
Fig 1. Block diagram
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
6. Pinning information
6.1 Pinning
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
V
DDA(3V3)
DDA(3V3)
2
AUXAP
AUXBP
AUXBN
AGND
3
AUXAN
AGND
4
5
V
V
V
V
DDA(1V8)
DDA(1V8)
DDA(1V8)
6
DDA(1V8)
AGND
7
GAPOUT
VIRES
d.n.c.
8
CLKP
CLKN
AGND
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
RESET_N
SCS_N
SCLK
V
DDA(1V8)
SYNCP
SYNCN
TM1
DAC1405D750HW
SDIO
SDO
TM0
TM3
V
V
DD(IO)(3V3)
DD(IO)(3V3)
GNDIO
GNDIO
Q0
I13
I12
I11
I10
I9
AGND
Q1
Q2
Q3
Q4
I8
Q5
I7
Q6
I6
Q7
001aal378
Fig 2. Pin configuration
DAC1405D750_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 March 2010
4 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
6.2 Pin description
Table 2.
Symbol
VDDA(3V3)
AUXAP
AUXAN
AGND
VDDA(1V8)
VDDA(1V8)
AGND
CLKP
CLKN
AGND
VDDA(1V8)
SYNCP
SYNCN
TM1
Pin description
Pin
1
Type[1] Description
P
O
O
G
P
P
G
I
analog supply voltage 3.3 V
2
auxiliary DAC B output current
complementary auxiliary DAC B output current
analog ground
3
4
5
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
6
7
8
clock input
9
I
complementary clock input
analog ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
G
P
O
O
I/O
I/O
P
G
I
analog supply voltage 1.8 V
synchronous clock output
complementary synchronous clock output
test mode 1 (connected to DGND)
test mode 0 (connected to DGND)
input/output buffers supply voltage 3.3 V
input/output buffers ground
I data input bit 13 (MSB)
I data input bit 12
TM0
VDD(IO)(3V3)
GNDIO
I13
I12
I
I11
I
I data input bit 11
I10
I
I data input bit 10
I9
I
I data input bit 9
I8
I
I data input bit 8
I7
I
I data input bit 7
I6
I
I data input bit 6
VDDD(1V8)
DGND
I5
P
G
I
digital supply voltage 1.8 V
digital ground
I data input bit 5
I4
I
I data input bit 4
I3
I
I data input bit 3
I2
I
I data input bit 2
VDDD(1V8)
DGND
I1
P
G
I
digital supply voltage 1.8 V
digital ground
I data input bit 1
I0
I
I data input bit 0 (LSB)
digital supply voltage 1.8 V
digital ground
VDDD(1V8)
DGND
TM2
P
G
-
test mode 2 (to connect to DGND)
digital ground
DGND
G
DAC1405D750_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 March 2010
5 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 2.
Pin description …continued
Type[1] Description
Symbol
VDDD(1V8)
Q13/SELIQ
Q12
Pin
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P
I
digital supply voltage 1.8 V
Q data input bit 13 (MSB)/select IQ in Interleaved mode
Q data input bit 12
I
DGND
VDDD(1V8)
Q11
G
P
I
digital ground
digital supply voltage 1.8 V
Q data input bit 11
Q10
I
Q data input bit 10
Q9
I
Q data input bit 9
Q8
I
Q data input bit 8
DGND
VDDD(1V8)
Q7
G
P
I
digital ground
digital supply voltage 1.8 V
Q data input bit 7
Q6
I
Q data input bit 6
Q5
I
Q data input bit 5
Q4
I
Q data input bit 4
Q3
I
Q data input bit 3
Q2
I
Q data input bit 2
Q1
I
Q data input bit 1
Q0
I
Q data input bit 0 (LSB)
input/output buffers ground
input/output buffers supply voltage 3.3 V
test mode 3 (to connect to DGND)
SPI data output
GNDIO
VDD(IO)(3V3)
TM3
G
P
I/O
O
I/O
I
SDO
SDIO
SPI data input/output
SPI clock input
SCLK
SCS_N
RESET_N
d.n.c.
I
SPI chip select (active LOW)
general reset (active LOW)
do not connect
I
-
VIRES
GAPOUT
VDDA(1V8)
VDDA(1V8)
AGND
AUXBN
AUXBP
VDDA(3V3)
AGND
VDDA(1V8)
AGND
VDDA(1V8)
AGND
I/O
I/O
P
P
G
O
O
P
G
P
G
P
G
DAC biasing resistor
bandgap input/output voltage
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
auxiliary DAC B output current
complementary auxiliary DAC B output current
analog supply voltage 3.3 V
analog ground
analog supply voltage 1.8 V
analog ground
analog supply voltage 1.8 V
analog ground
DAC1405D750_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 March 2010
6 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 2.
Pin description …continued
Type[1] Description
Symbol
VDDA(1V8)
AGND
Pin
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
H[2]
P
G
P
G
O
O
G
-
analog supply voltage 1.8 V
analog ground
VDDA(1V8)
AGND
analog supply voltage 1.8 V
analog ground
IOUTBN
IOUTBP
AGND
complementary DAC B output current
DAC B output current
analog ground
n.c.
not connected
AGND
G
O
O
G
P
G
P
G
P
G
P
G
G
analog ground
IOUTAP
IOUTAN
AGND
DAC A output current
complementary DAC A output current
analog ground
VDDA(1V8)
AGND
analog supply voltage 1.8 V
analog ground
VDDA(1V8)
AGND
analog supply voltage 1.8 V
analog ground
VDDA(1V8)
AGND
analog supply voltage 1.8 V
analog ground
VDDA(1V8)
AGND
analog supply voltage 1.8 V
analog ground
AGND
analog ground
[1] P = power supply
G = ground
I = input
O = output.
[2] H = heatsink (exposed die pad to be soldered)
DAC1405D750_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 March 2010
7 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
+4.6
+4.6
+3.0
+3.0
+3.0
Unit
V
VDD(IO)(3V3) input/output supply voltage (3.3 V)
VDDA(3V3) analog supply voltage (3.3 V)
VDDA(1V8) analog supply voltage (1.8 V)
VDDD(1V8) digital supply voltage (1.8 V)
−0.5
−0.5
−0.5
−0.5
−0.5
V
V
V
VI
input voltage
pins CLKP, CLKN, VIRES and GAPOUT
referenced to pin AGND
V
pins I13 to I0, Q13 to Q0, SDO, SDIO, SCLK,
SCS_N and RESET_N referenced to GNDIO
−0.5
−0.5
+4.6
+4.6
V
V
VO
output voltage
pins IOUTAP, IOUTAN, IOUTBP, IOUTBN,
AUXAP, AUXAN, AUXBP and AUXBN
referenced to pin AGND
pins SYNCP and SYNCN referenced to
pin AGND
−0.5
+3.0
V
Tstg
Tamb
Tj
storage temperature
ambient temperature
junction temperature
−55
−40
-
+150
+85
°C
°C
°C
125
8. Thermal characteristics
Table 4.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ
Unit
[1]
[1]
thermal resistance from junction to ambient
thermal resistance from junction to case
19.8
7.7
K/W
K/W
Rth(j-c)
[1] In compliance with JEDEC test board, in free air.
DAC1405D750_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 March 2010
8 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
9. Characteristics
Table 5.
Characteristics
VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together;
Tamb = −40 °C to +85 °C; typical values measured at Tamb = 25 °C; RL = 50 Ω differential; IO(fs) = 20 mA; PLL off unless
otherwise specified.
Symbol
Parameter
Conditions
Test[1]
Min
Typ
Max
Unit
VDD(IO)(3V3)
input/output supply voltage
(3.3 V)
I
3.0
3.3
3.6
V
VDDA(3V3)
VDDA(1V8)
analog supply voltage
(3.3 V)
I
I
3.0
1.7
3.3
1.8
3.6
1.9
V
V
analog supply voltage
(1.8 V)
VDDD(1V8)
IDD(IO)(3V3)
digital supply voltage (1.8 V)
I
I
1.7
-
1.8
0.3
1.9
V
input/output supply current fo = 19 MHz;
<tbd>
mA
(3.3 V)
fs = 740 Msps;
4× interpolation;
NCO on
IDDA(3V3)
IDDD(1V8)
IDDA(1V8)
analog supply current
(3.3 V)
fo = 19 MHz;
fs = 740 Msps;
4× interpolation;
NCO on
I
I
I
I
-
-
-
-
44
<tbd>
<tbd>
<tbd>
-
mA
mA
mA
mA
digital supply current (1.8 V) fo = 19 MHz;
fs = 740 Msps;
177
350
68
4× interpolation;
NCO on
analog supply current
(1.8 V)
fo = 19 MHz;
fs = 740 Msps;
4× interpolation;
NCO on
IDDD
Ptot
digital supply current
total power dissipation
for x / (sin x) function
only
fo = 19 MHz; fs = 740 Msps
4× interpolation
NCO off; DAC B off
NCO off
C
C
C
-
-
-
0.75
0.87
1.11
-
W
W
W
-
NCO on; all VDD
8× interpolation
NCO on
<tbd>
I
I
-
-
1.09
0.03
-
W
W
Power-down mode:
full power-down;
all VDD
<tbd>
8× interpolation
DAC A and DAC B
Sleep mode:
NCO on
I
-
0.63
-
W
DAC1405D750_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 March 2010
9 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 5.
Characteristics …continued
VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together;
Tamb = −40 °C to +85 °C; typical values measured at Tamb = 25 °C; RL = 50 Ω differential; IO(fs) = 20 mA; PLL off unless
otherwise specified.
Symbol
Parameter
Conditions
Test[1]
Min
Typ
Max
Unit
Clock inputs (CLKP and CLKN)[2]
[3]
[3]
Vi
input voltage
CLKN |Vgpd| < 50 mV or C
CLKP
825
-
-
1575
+100
mV
mV
Vidth
input differential threshold |Vgpd| < 50 mV
C
−100
voltage
Ri
Ci
input resistance
D
D
-
-
10
-
-
MΩ
input capacitance
0.5
pF
Clock outputs (SYNCP and SYNCN)
Vo(cm)
common mode output
voltage
C
-
VDDA(1V8) − -
0.3
V
VO(dif)
Ro
differential output voltage
output resistance
C
D
<tbd>
-
1.2
80
-
-
V
Ω
Digital inputs (I0 to I13, Q0 to Q13)
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
C
C
I
GNDIO
-
1.0
V
2.3
-
VDD(IO)(3V3)
V
VIL = 1.0 V
VIH = 2.3 V
-
-
60
80
-
-
μA
μA
IIH
I
Digital inputs (SDO, SDIO, SCLK, SCS_N and RESET_N)
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
C
C
I
GNDIO
-
1.0
V
2.3
-
VDD(IO)(3V3)
V
VIL = 1.0 V
VIH = 2.3 V
-
-
20
20
-
-
nA
nA
IIH
I
Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN)
IO(fs)
full-scale output current
register value = 00h
default register
C
C
C
D
D
C
C
-
1.6
20
-
-
mA
-
-
mA
VO
output voltage
compliance range
1.8
VDDA(3V3)
V
Ro
output resistance
output capacitance
offset error variation
gain error variation
-
-
-
-
250
3
-
-
-
-
kΩ
Co
pF
ΔEO
ΔEG
6
ppm/°C
ppm/°C
18
Reference voltage output (GAPOUT)
VO(ref)
reference output voltage
Tamb = 25 °C
I
1.2
-
1.25
117
1.29
-
V
ΔVO(ref)
reference output voltage
variation
C
ppm/°C
IO(ref)
reference output current
external voltage 1.25 V
D
-
40
-
μA
Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)
IO(aux)
auxiliary output current
auxiliary output voltage
differential outputs
compliance range
I
-
2.2
-
-
mA
V
VO(aux)
C
D
0
-
2
-
NDAC(aux)mono auxiliary DAC monotonicity guaranteed
10
bit
DAC1405D750_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 March 2010
10 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 5.
Characteristics …continued
VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together;
Tamb = −40 °C to +85 °C; typical values measured at Tamb = 25 °C; RL = 50 Ω differential; IO(fs) = 20 mA; PLL off unless
otherwise specified.
Symbol
Parameter
Conditions
Test[1]
Min
Typ
Max
Unit
Input timing (see Figure 10)
fdata
data rate
Dual-port mode input
C
C
C
C
-
-
-
-
-
185
MHz
%
tw(CLK)
CLK pulse width
input hold time
input set-up time
40
60
-
th(i)
<tbd>
<tbd>
ns
tsu(i)
-
ns
SYNC signal
td
delay time
fSYNC = fs / 4
fSYNC = fs / 8
variation
C
C
C
-
-
-
0.21
0.3
-
-
-
ns
ns
0.27
ps/°C
Output timing
fs
ts
sampling frequency
settling time
C
D
-
-
-
750
-
Msps
ns
to ± 0.5 LSB
20
NCO frequency range
fNCO NCO frequency
register values
00000000h
D
D
D
-
-
-
0
-
-
-
MHz
MHz
Hz
FFFFFFFFh
740
0.172
fstep
step frequency
Low-power NCO frequency range
fNCO
NCO frequency
step frequency
register values
00000000h
F8000000h
D
D
D
-
-
-
0
-
-
-
MHz
MHz
MHz
716.875
23.125
fstep
Dynamic performance
SFDR
spurious-free dynamic
fs = 737.28 Msps
range
fdata = 91.6 MHz; B = fdata / 2
fo = 4 MHz; 0 dBFS
fdata = 184.32 MHz; B = fdata / 2
C
-
76
-
dBc
fo = 19 MHz; 0 dBFS
fo = 70 MHz; 0 dBFS
I
-
-
74
86
-
-
dBc
dBc
C
SFDRRBW
restricted bandwidth
spurious-free dynamic
range
fo = 153.6 MHz; 0 dBFS; fdata = 184.32 MHz; fs = 737.28 Msps
B = 20 MHz
C
C
C
-
-
-
85
83
75
-
-
-
dBc
dBc
dBc
B = 100 MHz
B = 20 MHz; 8-tone;
500 kHz spacing
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 5.
Characteristics …continued
VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together;
Tamb = −40 °C to +85 °C; typical values measured at Tamb = 25 °C; RL = 50 Ω differential; IO(fs) = 20 mA; PLL off unless
otherwise specified.
Symbol
Parameter
Conditions
Test[1]
Min
Typ
Max
Unit
IMD3
third-order intermodulation
distortion
fdata = 184.32 MHz; fs = 737.28 Msps
[4]
fo1 = 95 MHz;
fo2 = 97 MHz
C
-
-
-
77
76
76
-
-
-
dBc
dBc
dBc
[4]
[4]
fo1 = 152.5 MHz;
I
fo2 = 153.5 MHz
fo1 = 137 MHz;
C
fo2 = 143 MHz
ACPR
adjacent channel power
ratio
fdata = 184.32 MHz; fs = 737.28 Msps; fo = 96 MHz
1-carrier; B = 5 MHz
2-carrier; B = 10 MHz
4-carrier; B = 20 MHz
I
-
-
-
75
72
70
-
-
-
dBc
dBc
dBc
C
C
fdata = 184.32 MHz; fs = 737.28 Msps; fo = 153.6 MHz
1-carrier; B = 5 MHz
2-carrier; B = 10 MHz
4-carrier; B = 20 MHz
C
C
C
-
-
-
73
71
68
-
-
-
dBc
dBc
dBc
NSD
noise spectral density
fdata = 184.32 MHz; fs = 737.28 Msps
fo = 19 MHz; 0 dBFS
C
C
-
-
−161
−156
-
-
dBc/Hz
dBc/Hz
fo = 153.6 MHz;
0 dBFS;
fo = 153.6 MHz;
C
-
−158
-
dBc/Hz
−10 dBFS
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2] CLKP and CLKN inputs are at differential LVDS levels. An external differential resistor with a value of between 80 Ω and 120 Ω should
be connected across the pins (see Figure 8).
[3] |Vgpd| represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance
and the inductance between the receiver and the driver circuit ground voltages.
[4] IMD3 rejection with −6 dBFS/tone.
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DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
10. Application information
10.1 General description
The DAC1405D750 is a dual 14-bit DAC which operates at up to 750 Msps. Each DAC
consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an
8-bit binary weighted sub-DAC.
The input data rate of up to 185 MHz combined with the maximum output sampling rate of
750 Msps make the DAC1405D750 extremely flexible in wide bandwidth and multi-carrier
systems. The device’s quadrature modulator and 32-bit NCO simplifies system frequency
selection. This is also possible because the 4× and 8× interpolation filters remove
undesired images.
A SYNC signal is provided to synchronize data when the PLL is in the off state.
Two modes are available for the digital input. In Dual-port mode, each DAC uses its own
data input line. In Interleaved mode, both DACs use the same data input line.
The on-chip PLL enables generation of the internal clock signals for the digital circuitry
and the DAC from a low speed clock. The PLL can be bypassed enabling the use of an
external, high-speed clock.
Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and
IOUTBP/IOUTBN. This provides a full-scale output current (IO(fs)) up to 22 mA. An internal
reference is available for the reference current which is externally adjustable using pin
VIRES.
There are also some embedded features to provide an analog offset correction (auxiliary
DACs) and digital offset control as well as for gain adjustment. All the functions can be set
using the SPI.
The DAC1405D750 operates at both 3.3 V and 1.8 V each of which has separate digital
and analog power supplies. The digital input is 1.8 V and 3.3 V compliant and the clock
input is LVDS compliant.
10.2 Serial peripheral interface
10.2.1 Protocol description
The DAC1405D750 Serial Peripheral Interface (SPI) is a synchronous serial
communication port allowing easy interfacing with many industry microprocessors. It
provides access to the registers that define the operating modes of the chip in both write
and read modes.
This interface can be configured as a 3-wire type (SDIO as a bidirectional pin) or a 4-wire
type (SDIO and SDO as unidirectional pins, input and output port respectively). In both
configurations, SCLK acts as the serial clock and SCS_N acts as the serial chip select
bar.
Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW
assertion to drive the chip with 1 to 4 bytes, depending on the content of the instruction
byte (see Table 7).
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DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
RESET_N
(optional)
SCS_N
SCLK
SDIO
R/W
N1
N0
A4
A3
A2
A1
A0
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
SDO
(optional)
001aaj812
R/W indicates the mode access, (see Table 6)
Fig 3. SPI protocol
Table 6.
Read or Write mode access description
Description
R/W
0
Write mode operation
1
Read mode operation
In Table 7 N1 and N0 indicate the number of bytes transferred after the instruction byte.
Table 7.
Number of bytes transferred
N1
0
N0
0
Number of bytes
1 byte transferred
2 bytes transferred
3 bytes transferred
4 bytes transferred
0
1
1
0
1
1
A0 to A4: indicate which register is being addressed. In the case of a multiple transfer, this
address concerns the first register after which the next registers follow directly in a
decreasing order according to Table 9 “Register allocation map”.
10.2.2 SPI timing description
The interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in
Figure 4.
t
w(RESET_N)
RESET_N
(optional)
50 %
t
t
h(SCS_N)
su(SCS_N)
SCS_N
50 %
t
w(SCLK)
SCLK
SDIO
50 %
50 %
t
h(SDIO)
su(SDIO)
t
001aaj813
Fig 4. SPI timing diagram
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DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
The SPI timing characteristics are given in Table 8.
Table 8. SPI timing characteristics
Symbol
fSCLK
Parameter
Min
-
Typ
Max
Unit
MHz
ns
SCLK frequency
SCLK pulse width
SCS_N set-up time
SCS_N hold time
SDIO set-up time
SDIO hold time
-
-
-
-
-
-
-
15
-
tw(SCLK)
tsu(SCS_N)
th(SCS_N)
tsu(SDIO)
th(SDIO)
30
20
20
10
5
-
ns
-
ns
-
ns
-
ns
tw(RESET_N)
RESET_N pulse width
30
-
ns
10.2.3 Detailed descriptions of registers
An overview of the details for all registers is provided in Table 9.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 9.
Register allocation map
Address
Dec Hex
Register name
R/W Bit definition
Bit 7
Default
Bin
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Dec Hex
0
1
2
00h COMMon
R/W
3W_SPI
SPI_RST
CLK_SEL
-
MODE_
SEL
CODING
IC_PD
GAP_PD 10000000 128 80
01h TXCFG
R/W NCO_ON
NCO_LP_ INV_SIN_
MODULATION[2:0]
INTERPOLATION[1:0] 10000111 135 87
SEL
SEL
02h PLLCFG
R/W
R/W
PLL_PD
-
PLL_DIV_
PD
PLL_DIV[1:0]
DAC_CLK_DELAY[1:0] DAC_CLK 00010000 16 10
_POL
3
4
5
6
7
8
9
03h FREQNCO_LSB
FREQ_NCO[7:0]
FREQ_NCO[15:8]
FREQ_NCO[23:16]
FREQ_NCO[31:24]
PH_NCO[7:0]
01100110 102 66
01100110 102 66
01100110 102 66
00100110 38 26
04h FREQNCO_LISB R/W
05h FREQNCO_UISB R/W
06h FREQNCO_MSB R/W
07h PHINCO_LSB
08h PHINCO_MSB
09h DAC_A_Cfg_1
R/W
R/W
00000000
00000000
00000000
0
0
0
00
00
00
PH_NCO[15:8]
R/W DAC_A_PD
DAC_A_
SLEEP
DAC_A_OFFSET[5:0]
10
11
12
13
14
15
0Ah DAC_A_Cfg_2
0Bh DAC_A_Cfg_3
0Ch DAC_B_Cfg_1
0Dh DAC_B_Cfg_2
0Eh DAC_B_Cfg_3
0Fh DAC_Cfg
R/W
R/W
DAC_A_GAIN_
COARSE[1:0]
DAC_A_GAIN_FINE[5:0]
DAC_A_OFFSET[11:6]
DAC_B_OFFSET[5:0]
DAC_B_GAIN_FINE[5:0]
DAC_B_OFFSET[11:6]
01000000 64 40
11000000 192 C0
DAC_A_GAIN_
COARSE[3:2]
R/W DAC_B_PD
DAC_B_
SLEEP
00000000
0
00
R/W
R/W
R/W
DAC_B_GAIN_
COARSE[1:0]
01000000 64 40
11000000 192 C0
DAC_B_GAIN_
COARSE[3:2]
-
MINUS_
3DB
NOISE_ 00000000
SHPER
0
00
16
26
27
28
29
10h SYNC_Cfg
R/W SYNC_DIV SYNC_SEL
-
00000000
0
00
1Ah DAC_A_Aux_MSB R/W
AUX_A[9:2]
10000000 128 80
00000000 00
10000000 128 80
00000000 00
1Bh DAC_A_Aux_LSB R/W AUX_A_PD
1Ch DAC_B_Aux_MSB R/W
-
AUX_A[1:0]
0
AUX_B[9:2]
1Dh DAC_B_Aux_LSB R/W AUX_B_PD
-
AUX_B[1:0]
0
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
10.2.4 Detailed register descriptions
Please refer to Table 9 for the register overview and relevant default values. In the
following tables, all the values shown in bold are the default values.
Table 10. COMMon register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7
3W_SPI
R/W
R/W
R/W
serial interface bus type
0
4 wire SPI
1
3 wire SPI
6
5
SPI_RST
CLK_SEL
serial interface reset
no reset
0
1
performs a reset on all registers except 00h
data input latch
at CLK rising edge
at CLK falling edge
reserved
0
1
-
4
3
-
-
MODE_SEL
R/W
input data mode
dual port
0
1
interleaved
2
1
CODING
IC_PD
R/W
R/W
coding
0
binary
1
two’s compliment
power-down
0
disabled
1
all circuits (digital and analog, except SPI)
are switched off
0
GAP_PD
R/W
internal bandgap power-down
power-down disabled
0
1
internal bandgap references are switched off
Table 11. TXCFG register (address 01h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7
NCO_ON
R/W
R/W
NCO
disabled (the NCO phase is reset to 0)
0
1
enabled
6
5
NCO_LP_SEL
INV_SIN_SEL
low-power NCO
disabled
0
1
NCO frequency and phase given by the five
MSBs of the registers 06h and 08h
respectively
R/W
x / (sin x) function
disabled
0
1
enabled
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 11. TXCFG register (address 01h) bit description …continued
Default settings are shown highlighted.
Bit Symbol Access Value Description
4 to 2 MODULATION[2:0]
R/W
modulation
000
dual DAC: no modulation
001
positive upper single sideband
up-conversion
010
011
positive lower single sideband up-conversion
negative upper single sideband
up-conversion
100
negative lower single sideband
up-conversion
1 to 0 INTERPOLATION[1:0] R/W
interpolation
reserved
4×
01
10
11
8×
Table 12. PLLCFG register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
PLL ON
PLL OFF
7
PLL_PD
R/W
PLL
switched on
switched off
0
1
6
5
-
-
reserved
PLL_DIV_PD
R/W
PLL divider
undefined
0
switched on
X
1
switched off
X
4 to 3 PLL_DIV[1:0]
R/W
PLL divider factor
Digital clock delay
00
01
10
11
2
130 ps
280 ps
430 ps
580 ps
undefined
X
4
8
X
2 to 1 DAC_CLK_DELAY[1:0] R/W
phase shift (fs)
00
01
10
0°
120°
240°
X
X
0
DAC_CLK_POL
R/W
clock edge of DAC (fs) undefined
0
normal
X
1
inverted
X
Table 13. FREQNCO_LSB register (address 03h) bit description
Bit Symbol Access Value Description
7 to 0 FREQ_NCO[7:0] R/W lower 8 bits for the NCO frequency setting
-
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 14. FREQNCO_LISB register (address 04h) bit description
Bit
Symbol
Access Value Description
7 to 0 FREQ_NCO[15:8]
R/W
-
lower intermediate 8 bits for the NCO
frequency setting
Table 15. FREQNCO_UISB register (address 05h) bit description
Bit Symbol Access Value Description
7 to 0 FREQ_NCO[23:16]
R/W
-
upper intermediate 8 bits for the NCO
frequency setting
Table 16. FREQNCO_MSB register (address 06h) bit description
Bit Symbol Access Value Description
7 to 0 FREQ_NCO[31:24]
R/W
-
most significant 8 bits for the NCO frequency
setting
Table 17. PHINCO_LSB register (address 07h) bit description
Bit Symbol Access Value Description
7 to 0 PH_NCO[7:0] R/W lower 8 bits for the NCO phase setting
-
Table 18. PHINCO_MSB register (address 08h) bit description
Bit Symbol Access Value Description
7 to 0 PH_NCO[15:8]
R/W
-
most significant 8 bits for the NCO phase
setting
Table 19. DAC_A_Cfg_1 register (address 09h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7
DAC_A_PD
R/W
R/W
DAC A power
0
on
1
off
6
DAC_A_SLEEP
DAC A Sleep mode
disabled
0
1
-
enabled
5 to 0 DAC_A_OFFSET[5:0] R/W
lower 6 bits for the DAC A offset
Table 20. DAC_A_Cfg_2 register (address 0Ah) bit description
Bit Symbol Access Value Description
7 to 6 DAC_A_GAIN_
COARSE[1:0]
R/W
-
lower 2 bits for the DAC A gain setting for
coarse adjustment
5 to 0 DAC_A_GAIN_
FINE[5:0]
R/W
-
lower 6 bits for the DAC A gain setting for fine
adjustment
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 21. DAC_A_Cfg_3 register (address 0Bh) bit description
Bit
Symbol
Access Value Description
7 to 6 DAC_A_GAIN_
COARSE[3:2]
R/W
-
most significant 2 bits for the DAC A gain
setting for coarse adjustment
5 to 0 DAC_A_
OFFSET[11:6]
R/W
-
most significant 6 bits for the DAC A offset
Table 22. DAC_B_Cfg_1 register (address 0Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7
DAC_B_PD
R/W
R/W
DAC B power
0
on
1
off
6
DAC_B_SLEEP
DAC B Sleep mode
disabled
0
1
-
enabled
5 to 0 DAC_B_OFFSET[5:0] R/W
lower 6 bits for the DAC B offset
Table 23. DAC_B_Cfg_2 register (address 0Dh) bit description
Bit Symbol Access Value Description
7 to 6 DAC_B_GAIN_
COARSE[1:0]
R/W
-
less significant 2 bits for the DAC B gain setting
for coarse adjustment
5 to 0 DAC_B_GAIN_
FINE[5:0]
R/W
-
the 6 bits for the DAC B gain setting for fine
adjustment
Table 24. DAC_B_Cfg_3 register (address 0Eh) bit description
Bit Symbol Access Value Description
7 to 6 DAC_B_GAIN_
COARSE[3:2]
R/W
-
most significant 2 bits for the DAC B gain
setting for coarse adjustment
5 to 0 DAC_B_
OFFSET[11:6]
R/W
-
most significant 6 bits for the DAC B offset
Table 25. DAC_Cfg register (address 0Fh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7 to 2 -
-
-
reserved
NCO gain
unity
1
0
MINUS_3DB
R/W
0
1
−3 dB
NOISE_SHPER
R/W
noise shaper
disabled
enabled
0
1
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 26. SYNC_Cfg register (address 10h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7
SYNC_DIV
R/W
R/W
-
fs divided by
4
0
1
8
6
SYNC_SEL
SYNC selection
disabled
enabled
reserved
0
1
-
5 to 0 -
Table 27. DAC_A_Aux_MSB register (address 1Ah) bit description
Bit Symbol Access Value Description
7 to 0 AUX_A[9:2] R/W most significant 8 bits for the auxiliary DAC A
-
Table 28. DAC_A_Aux_LSB register (address 1Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7
AUX_A_PD
R/W
auxiliary DAC A power
0
on
1
off
6 to 1 -
-
reserved
1 to 0 AUX_A[1:0]
R/W
lower 2 bits for the auxiliary DAC A
Table 29. DAC_B_Aux_MSB register (address 1Ch) bit description
Bit Symbol Access Value Description
7 to 0 AUX_B[9:2] R/W most significant 8 bits for the auxiliary DAC B
-
Table 30. DAC_B_Aux_LSB register (address 1Dh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7
AUX_B_PD
R/W
auxiliary DAC B power
0
on
1
off
6 to 1
1 to 0
-
-
reserved
AUX_B[1:0]
R/W
lower 2-bits for the auxiliary DAC B
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
10.2.5 Recommended configuration
It is recommended that the following additional settings are used to obtain optimum
performance at up to 750 Msps
Table 31. Recommended configuration
Address
Dec
17
Value
Hex
11h
13h
14h
Bin
Dec
10
Hex
0Ah
6Ch
6Ch
00001010
01101100
01101100
19
108
108
20
10.3 Input data
The setting applied to MODE_SEL (register 00h[3]; see Table 10 on page 17) defines
whether the DAC1405D750 operates in the Dual-port mode or in Interleaved mode (see
Table 32).
Table 32. Mode selection
Bit 3 setting
Function
I13 to I0
active
Q13 to Q0
active
off
Pin 41
Q13
0
1
Dual port mode
Interleaved mode
active
SELIQ
10.3.1 Dual-port mode
The data input for Dual-port mode operation is shown in Figure 5 “Dual-port mode”. Each
DAC has its own independent data input. The data enters the input latch on the rising
edge of the internal clock signal and is transferred to the DAC latch.
FIR 1
FIR 2
FIR 3
LATCH
I
I13 to I0
2 ×
2 ×
2 ×
FIR 1
FIR 2
FIR 3
LATCH
Q
Q13 to Q0
2 ×
2 ×
2 ×
001aal653
Fig 5. Dual-port mode
10.3.2 Interleaved mode
The data input for the Interleaved mode operation is illustrated in Figure 6 “Interleaved
mode operation”.
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DAC1405D750
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
FIR 1
FIR 2
FIR 3
LATCH
I
2 ×
2 ×
2 ×
I13 to I0
FIR 1
FIR 2
FIR 3
LATCH
Q
Q13/SELIQ
2 ×
2 ×
2 ×
001aal654
Fig 6. Interleaved mode operation
In Interleaved mode, both DACs use the same data input at twice the Dual-port mode
frequency. Data enters the latch on the rising edge of the internal clock signal. The data is
sent to either latch I or latch Q, depending on the SELIQ signal.
The SELIQ input (pin 41) allows the synchronization of the internally demultiplexed I and
Q channels; see Figure 7 “Interleaved mode timing (8x interpolation, latch on rising
edge)”.
In
N
N + 1
N + 2
N + 3
N + 4
N + 5
SELIQ
(synchronous alternative)
SELIQ
(asynchronous alternative 1)
SELIQ
(asynchronous alternative 2)
CLK
dig
Latch I output
Latch Q output
XX
XX
N
N + 2
N + 3
N + 1
001aaj814
CLKdig = internal digital clock
Fig 7. Interleaved mode timing (8x interpolation, latch on rising edge)
The SELIQ signal can be either synchronous or asynchronous (single rising edge, single
pulse). The first data following the SELIQ rising edge is sent in channel I and following
data is sent in channel Q. After this, data is distributed alternately between these
channels.
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DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
10.4 Input clock
The DAC1405D750 can operate at the following clock frequencies:
PLL on: up to 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode
PLL off: up to 750 MHz
The input clock is LVDS compliant (see Figure 8) but it can also be interfaced with CML
differential sine wave signal (see Figure 9).
Z = 50 Ω
CLKP
LVDS
LVDS
Zdiff =
100 Ω
Z = 50 Ω
CLKN
001aah021
Fig 8. LVDS clock configuration
V
DDA(1V8)
1.1 kΩ
Z = 50 Ω
100 nF
CLKP
55 Ω
LVDS
CML
Zdiff =
100 Ω
55 Ω
Z = 50 Ω
100 nF
CLKN
100 nF
2.2 kΩ
AGND
001aah020
Fig 9. Interfacing CML to LVDS
10.5 Timing
The DAC1405D750 can operate at a sampling frequency (fs) up to 750 Msps with an input
data rate (fdata) up to 185 MHz. When using the internal PLL, the input data is referenced
to the CLK signal. When the internal PLL is bypassed, the SYNC signal is used as a
reference. The input timing in the second case is shown in Figure 10 “Input timing diagram
when internal PLL bypassed (off)”.
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
t
t
h(i)
su(i)
I13 to I0/
Q13 to Q0
90 %
90 %
N
N + 1
N + 2
SYNC
(SYNCP − SYNCN)
50 %
001aal384
Fig 10. Input timing diagram when internal PLL bypassed (off)
10.5.1 Timing when using the internal PLL (PLL on)
In Table 33 “Frequencies”, the links between internal and external clocking are defined.
The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see Table 9 “Register allocation
map”) allows the frequency between the digital part and the DAC core to be adjusted.
Table 33. Frequencies
Mode
CLK input Input data rate Interpolation Update rate PLL_DIV[1:0]
(MHz)
(MHz)
(Msps)
Dual Port
Dual Port
Interleaved
Interleaved
185
185
4×
8×
4×
8×
740
01 (/ 4)
10 (/ 8)
00 (/ 2)
01 (/ 4)
92.5
370
92.5
370
740
740
185
185
740
The settings applied to DAC_CLK_DELAY[1:0] (register 02h[2:1]) and DAC_CLK_POL
(register 02h[0]), allow adjustment of the phase and polarity of the sampling clock. This
occurs at the input of the DAC core and depends mainly on the sampling frequency. Some
examples are given in Table 34 “Sample clock phase and polarity examples”.
Table 34. Sample clock phase and polarity examples
Mode
Input data rate Interpolation Update rate DAC_CLK_
DAC_CLK_
(MHz)
(Msps)
DELAY [1:0] POL
Dual Port
Dual Port
92.5
4×
8×
370
01
01
0
0
92.5
740
10.5.2 Timing when using an external PLL (PLL off)
It is recommended that a delay of 280 ps is used on the internal digital clock (CLKdig) to
obtain optimum device performance up to750 Msps.
Table 35. Optimum external PLL timing settings
Address
Register name
Value
Dec
Hex
Digital clock delay Bin
Dec
Hex
2
02h
PLLCFG
280 ps
10001000 136
88h
10.6 FIR filters
The DAC1405D750 integrates three selectable Finite Impulse Response (FIR) filters
which enables the device to use 4× or 8× interpolation rates. All three interpolation filters
have a stop-band attenuation of at least 80 dBc and a pass-band ripple of less than
0.0005 dB. The coefficients of the interpolation filters are given in Table 36 “Interpolation
filter coefficients”.
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 36. Interpolation filter coefficients
First interpolation filter Second interpolation filter
Third interpolation filter
Lower
H(1)
Upper
H(55)
H(54)
H(53)
H(52)
H(51)
H(50)
H(49)
H(48)
H(47)
H(46)
H(45)
H(44)
H(43)
H(42)
H(41)
H(40)
H(39)
H(38)
H(37)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(30)
H(29)
Value
−4
Lower
Upper
Value
Lower
Upper
Value
H(1)
H(23)
−2
H(1)
H(15)
−39
H(2)
0
H(2)
H(22)
0
H(2)
H(14)
0
H(3)
13
H(3)
H(21)
17
H(3)
H(13)
273
H(4)
0
H(4)
H(20)
0
H(4)
H(12)
0
H(5)
−34
0
H(5)
H(19)
−75
H(5)
H(11)
−1102
H(6)
H(6)
H(18)
0
H(6)
H(10)
0
H(7)
72
H(7)
H(17)
238
H(7)
H(9)
4964
H(8)
0
H(8)
H(16)
0
H(8)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
8192
H(9)
−138
0
H(9)
H(15)
−660
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
H(22)
H(23)
H(24)
H(25)
H(26)
H(27)
H(28)
H(10)
H(14)
0
245
0
H(11)
H(13)
2530
H(12)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4096
−408
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
650
0
−1003
0
1521
0
−2315
0
3671
0
−6642
0
20756
32768
10.7 Quadrature modulator and Numerically Controlled Oscillator
The quadrature modulator allows the 14-bit I and Q-data to be mixed with the carrier
signal generated by the NCO.
The frequency of the Numerically Controlled Oscillator (NCO) is programmed over 32-bit
and allows the sign of the sine component to be inverted in order to operate positive or
negative, lower or upper single sideband up-conversion.
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
10.7.1 NCO in 32-bit
When using the NCO, the frequency can be set by the four registers FREQNCO_LSB,
FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits.
The frequency for the NCO in 32-bit is calculated as follows:
M × fs
232
fNCO
=
(1)
--------------
where M is the decimal representation of FREQ_NCO[31:0].
The phase of the NCO can be set from 0° to 360° by both registers PHINCO_LSB and
PHINCO_MSB over 16 bits.
10.7.2 Low-power NCO
When using the low-power NCO, the frequency can be set by the 5 MSB of register
FREQNCO_MSB.
The frequency for the low-power NCO is calculated as follows:
M × fs
25
fNCO
=
(2)
--------------
where M is the decimal representation of FREQ_NCO[31:27].
The phase of the low-power NCO can be set by the 5 MSB of the register PHINCO_MSB.
10.7.3 Minus_3dB function
During normal use, a full-scale pattern will also be full scale at the output of the DAC.
Nevertheless, when the I and Q data are simultaneously close to full scale, some clipping
can occur and the Minus_3dB function can be used to reduce the gain by 3 dB in the
modulator. This is to keep a full-scale range at the output of the DAC without added
interferers.
10.8 x / (sin x)
Due to the roll-off effect of the DAC, a selectable FIR filter is inserted to compensate for
the x / (sin x) effect. This filter introduces a DC loss of 3.4 dB. The coefficients are
represented in Table 37 “Inversion filter coefficients”.
Table 37. Inversion filter coefficients
First interpolation filter
Lower
H(1)
H(2)
H(3)
H(4)
H(5)
Upper
H(9)
H(8)
H(7)
H(6)
-
Value
2
−4
10
−35
401
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
10.9 DAC transfer function
The full-scale output current for each DAC is the sum of the two complementary current
outputs:
IO(fs) = IIOUTP + IIOUTN
(3)
The output current depends on the digital input data:
DATA
16383
⎛
⎝
⎞
⎠
---------------
IIOUTP = IO(fs)
×
×
(4)
(5)
16383 – DATA
⎛
⎝
⎞
⎠
------------------------------------
IIOUTN = IO(fs)
16383
The setting applied to CODING (register 00h[2]; see Table 9 “Register allocation map”)
defines whether the DAC1405D750 operates with a binary input or a two’s complement
input.
Table 38 “DAC transfer function” shows the output current as a function of the input data,
when IO(fs) = 20 mA.
Table 38. DAC transfer function
Data
I13 to I0 and Q13 to Q0
IOUTP (mA) IOUTN (mA)
Binary
Two’s complement
00 0000 0000 0000
...
0
00 0000 0000 0000
0
20
...
10
...
0
...
...
...
10
...
20
8192
...
10 0000 0000 0000
...
00 0000 0000 0000
...
16383
11 1111 1111 1111
01 1111 1111 1111
10.10 Full-scale current
10.10.1 Regulation
The DAC1405D750 reference circuitry integrates an internal bandgap reference voltage
which delivers a 1.25 V reference to the GAPOUT pin. It is recommended to decouple pin
GAPOUT using a 100 nF capacitor.
The reference current is generated via an external resistor of 910 Ω (1 %) connected to
pin VIRES. A control amplifier sets the appropriate full-scale output current (IO(fs)) for both
DACs (see Figure 11 “Internal reference configuration”).
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DAC1405D750
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
REF.
BANDGAP
100 nF
GAPOUT
AGND
AGND
910 Ω
(1 %)
DAC
VIRES
CURRENT
SOURCES
ARRAY
001aaj816
Fig 11. Internal reference configuration
This configuration is optimum for temperature drift compensation because the bandgap
reference voltage can be matched to the voltage across the feedback resistor.
The DAC current can also be set by applying an external reference voltage to the
non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage
with GAP_PD (register 00h[0]; see Table 10 “COMMon register (address 00h) bit
description”).
10.10.2 Full-scale current adjustment
The default full-scale current (IO(fs)) is 20 mA but further adjustments can be made by the
user to both DACs independently via the serial interface from 1.6 mA to 22 mA, ±10 %.
The settings applied to DAC_A_GAIN_COARSE[3:0] (see Table 20 “DAC_A_Cfg_2
register (address 0Ah) bit description” and Table 21 “DAC_A_Cfg_3 register (address
0Bh) bit description”) and to DAC_B_GAIN COARSE[3:0] (see Table 23 “DAC_B_Cfg_2
register (address 0Dh) bit description” and Table 24 “DAC_B_Cfg_3 register (address
0Eh) bit description”) define the coarse variation of the full-scale current (see Table 39
“IO(fs) coarse adjustment”).
Table 39. IO(fs) coarse adjustment
Default settings are shown highlighted.
DAC_GAIN_COARSE[3:0]
IO(fs) (mA)
Decimal
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
0
1.6
1
3.0
2
4.4
3
5.8
4
7.2
5
8.6
6
10.0
11.4
12.8
14.2
15.6
17.0
7
8
9
10
11
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 39. IO(fs) coarse adjustment …continued
Default settings are shown highlighted.
DAC_GAIN_COARSE[3:0]
IO(fs) (mA)
Decimal
Binary
12
13
14
15
1100
1101
1110
1111
18.5
20.0
21.0
22.0
The settings applied to DAC_A_GAIN_FINE[5:0] (see Table 20 “DAC_A_Cfg_2 register
(address 0Ah) bit description”) and to DAC_B_GAIN_FINE[5:0] (see Table 23
“DAC_B_Cfg_2 register (address 0Dh) bit description”) define the fine variation of the
full-scale current (see Table 40 “IO(fs) fine adjustment”).
Table 40. IO(fs) fine adjustment
Default settings are shown highlighted.
DAC_GAIN_FINE[5:0]
Delta IO(fs)
Decimal
Two’s complement
−32
...
10 0000
...
−10.3 %
...
0
00 0000
...
0
...
...
31
01 1111
+10 %
The coding of the fine gain adjustment is two’s complement.
10.11 Digital offset adjustment
When the DAC1405D750 analog output is DC connected to the next stage, the digital
offset correction can be used to adjust the common mode level at the output of the DAC. It
adds an offset at the end of the digital part, just before the DAC.
The settings applied to DAC_A_OFFSET[11:0] (see Table 19 “DAC_A_Cfg_1 register
(address 09h) bit description” and Table 21 “DAC_A_Cfg_3 register (address 0Bh) bit
description”) and to “DAC_B_OFFSET[11:0]” (see Table 22 “DAC_B_Cfg_1 register
(address 0Ch) bit description” and Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit
description”) define the range of variation of the digital offset (see Table 41 “Digital offset
adjustment”).
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DAC1405D750
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 41. Digital offset adjustment
Default settings are shown highlighted.
DAC_OFFSET[11:0]
Offset applied
Decimal
−2048
−2047
...
Two’s complement
1000 0000 0000
1000 0000 0001
...
−4096
−4094
...
−1
1111 1111 1111
0000 0000 0000
0000 0000 0001
...
−2
0
0
+1
+2
...
...
+2046
+2047
0111 1111 1110
0111 1111 1111
+4092
+4094
10.12 Analog output
The DAC1405D750 has two output channels each of which produces two complementary
current outputs. These allow the even-order harmonics and noise to be reduced. The pins
are IOUTAP/IOUTAN and IOUTBP/IOUTBN, respectively and need to be connected via a
load resistor RL to the 3.3 V analog power supply (VDDA(3V3)).
Refer to Figure 12 for the equivalent analog output circuit of one DAC. This circuit consists
of a parallel combination of NMOS current sources, and their associated switches, for
each segment.
V
DDA(3V3)
R
R
L
L
IOUTAP/IOUTBP
IOUTAN/IOUTBN
001aah019
AGND
AGND
Fig 12. Equivalent analog output circuit (one DAC)
The cascode source configuration increases the output impedance of the source, thus
improving the dynamic performance of the DAC by introducing less distortion.
The device can provide an output level of up to 2 Vo(p-p) depending on the application, the
following stages and the targeted performances.
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DAC1405D750
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
10.13 Auxiliary DACs
The DAC1405D750 integrates 2 auxiliary DACs that can be used to compensate for any
offset between the DAC and the next stage in the transmission path.
Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to
ground).
IO(AUX) = IAUXP + IAUXN
(6)
The output current depends on the auxiliary DAC data:
AUX[9:0]
⎛
⎝
⎞
⎠
------------------------
AUXP = IO(AUX)
AUXN = IO(AUX)
×
×
(7)
(8)
1023
(1023–AUX[9:0])
⎛
⎝
⎞
⎠
---------------------------------------------
1023
Table 42 “Auxiliary DAC transfer function” shows the output current as a function of the
auxiliary DAC data.
Table 42. Auxiliary DAC transfer function
Default settings are shown highlighted.
Data
0
AUX[9:0] (binary)
00 0000 0000
...
IAUXP (mA)
IAUXN (mA)
0
2.2
...
...
...
512
...
10 0000 0000
...
1.1
...
1.1
...
1023
11 1111 1111
2.2
0
10.14 Output configuration
10.14.1 Basic output configuration
The use of a differentially-coupled transformer output provides optimum distortion
performance (see Figure 13 “1 Vo(p-p) differential output with transformer”). In addition, it
helps to match the impedance and provides electrical isolation.
V
DDA(3V3)
50 Ω
0 mA to 20 mA
0 mA to 20 mA
2:1
IOUTnP
IOUTnN
50 Ω
50 Ω
V
DDA(3V3)
IOUTnP/IOUTnN; V
= 2.8 V; V
= 1 V
o(cm)
o(dif)(p-p)
001aaj817
Fig 13. 1 Vo(p-p) differential output with transformer
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DAC1405D750
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
The DAC1405D750 differential outputs can operate up to 2 Vo(p-p). In this configuration, it
is recommended to connect the center tap of the transformer to a 62 Ω resistor connected
to the 3.3 V analog power supply, in order to adjust the DC common mode to
approximately 2.7 V (see Figure 14).
V
V
DDA(3V3)
DDA(3V3)
100 Ω
62 Ω
0 mA to 20 mA
0 mA to 20 mA
4:1
IOUTnP
IOUTnN
50 Ω
100 Ω
V
DDA(3V3)
IOUTnP/IOUTnN; V
= 2.7 V; V
= 2 V
o(cm)
o(dif)(p-p)
001aaj818
Fig 14. 2 Vo(p-p) differential output with transformer
10.14.2 DC interface to an Analog Quadrature Modulator (AQM)
When the system operation requires to keep the DC component of the spectrum, the
DAC1405D750 can use a DC interface to connect to an AQM. In this case, the offset
compensation for LO cancellation can be made with the use of the digital offset control in
the DAC.
Figure 15 provides an example of a connection to an AQM with a 1.7 VI(cm) common
mode input level.
V
AQM (V = 1.7 V)
i(cm)
DDA(3V3)
(1)
(2)
51.1 Ω
51.1 Ω
442 Ω
442 Ω
IOUTnP
IOUTnN
BBP
BBN
0 mA to 20 mA
768 Ω
768 Ω
(1)
IOUTnP/IOUTnN; V
= 2.67 V; V
= 1.98 V
o(cm)
o(dif)(p-p)
(2)
BBP/BBN; V
= 1.7 V; V
= 1.26 V
i(cm)
i(dif)(p-p)
001aaj541
Fig 15. An example of a DC interface to a 1.7 VI(cm) AQM
Figure 16 provides an example of a connection to an AQM with a 3.3 VI(cm) common
mode input level.
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DAC1405D750
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Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
V
5 V
AQM (V = 3.3 V)
i(cm)
DDA(3V3)
(1)
(2)
54.9 Ω
54.9 Ω
750 Ω
750 Ω
237 Ω
237 Ω
IOUTnP
IOUTnN
BBP
BBN
1.27 kΩ
1.27 kΩ
(1)
(2)
IOUTnP/IOUTnN; V
= 2.75 V; V
= 1.97 V
o(cm)
o(dif)(p-p)
BBP/BBN; V
= 3.3 V; V
= 1.5 V
001aaj542
i(cm)
i(dif)(p-p)
Fig 16. An example of a DC interface to a 3.3 VI(cm) AQM
The auxiliary DACs can be used to control the offset in a precise range or with precise
steps.
Figure 17 provides an example of a DC interface with the auxiliary DACs to an AQM with
a 1.7 VI(cm) common mode input level.
V
AQM (V = 1.7 V)
i(cm)
DDA(3V3)
(1)
(2)
51.1 Ω
51.1 Ω
442 Ω
442 Ω
IOUTnP
IOUTnN
BBP
BBN
0 mA to 20 mA
698 Ω
698 Ω
AUXnP
AUXnN
1.1 mA (typ.)
51.1 Ω
51.1 Ω
(1)
IOUTnP/IOUTnN; V
= 2.67 V; V
= 1.94 V
o(cm)
o(dif)(p-p)
(2)
BBP/BBN; V
= 1.7 V; V
= 1.23 V; offset correction up to 50 mV
i(cm)
i(dif)(p-p)
001aal655
Fig 17. An example of a DC interface to a 1.7 VI(cm) AQM using auxiliary DACs
Figure 18 provides an example of a DC interface with the auxiliary DACs to an AQM with
a 3.3 VI(cm) common mode input level.
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DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
AQM (V
(2)
= 3.3 V)
V
5 V
i(cm)
DDA(3V3)
54.9 Ω
634 kΩ
54.9 Ω
634 kΩ
750 Ω
750 Ω
(1)
237 Ω
237 Ω
IOUTnP
BBP
BBN
IOUTnN
AUXnP
AUXnN
442 kΩ
442 kΩ
(1)
IOUTnP/IOUTnN; V
= 2.75 V; V
= 1.96 V
o(cm)
o(dif)(p-p)
(2)
BBP/BBN; V
= 3.3 V; V
= 1.5 V; offset correction up to 36 mV
i(cm)
i(dif)(p-p)
001aaj544
Fig 18. An example of a DC interface to a 3.3 VI(cm) AQM using auxiliary DACs
The constraints to adjust the interface are the output compliance range of the DAC and
the auxiliary DACs, the input common mode level of the AQM, and the range of offset
correction.
10.14.3 AC interface to an Analog Quadrature Modulator (AQM)
When the AQM common mode voltage is close to ground, the DAC1405D750 must be
AC-coupled and the auxiliary DACs are needed for offset correction.
Figure 18 provides an example of a connection to an AQM with a 0.5 VI(cm) common
mode input level using auxiliary DACs.
DAC1405D750_1
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Preliminary data sheet
Rev. 01 — 10 March 2010
35 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
V
5 V
AQM (V = 0.5 V)
i(cm)
DDA(3V3)
(1)
(2)
66.5 Ω
66.5 Ω
2 kΩ
2 kΩ
10 nF
10 nF
IOUTnP
IOUTnN
BBP
BBN
0 mA to 20 mA
174 Ω
34 Ω
174 Ω
34 Ω
AUXnP
AUXnN
1.1 mA (typ.)
(1)
IOUTnP/IOUTnN; V
= 2.65 V; V
= 1.96 V
o(cm)
o(dif)(p-p)
(2)
BBP/BBN; V
= 0.5 V; V
= 1.96 V; offset correction up to 70 mV
i(cm)
i(dif)(p-p)
001aaj589
Fig 19. An example of an AC interface to a 0.5 VI(cm) AQM using auxiliary DACs
10.15 Power and grounding
In order to obtain optimum performance, it is recommended that the 1.8 V analog power
supplies on pins 5, 11, 71, 77 and 99 should not be connected with the ones on pins 6, 70,
79, 81, 83, 93, 95 and 97 on the top layer.
To optimize the decoupling, the power supplies should be decoupled with the following
ground pins:
• VDDD(1V8): pin 26 with 27; pin 32 with 33; pin 36 with 37; pin 40 with 39; pin 44 with 43
and pin 50 with 49.
• VDD(IO)(3V3): pin 16 with 17 and pin 60 with 59.
• VDDA(1V8): pin 5 with 4; pin 6 with 7; pin 11 with 10; pin 71 with 72; pin 77 with 78; pins
79, 81, 83 with 80, 82, 84; pins 93, 95, 97 with 92, 94, 96 and pin 99 with 98.
• VDDA(3V3): pin 1 with 100 and pin 75 with 76.
DAC1405D750_1
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 March 2010
36 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
11. Package outline
HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads;
body 14 x 14 x 1 mm; exposed die pad
SOT638-1
c
y
exposed die pad side
X
D
h
A
75
51
50
76
Z
E
e
H
E
E
E
(A )
3
A
h
2
A
A
1
w M
p
θ
b
L
p
pin 1 index
L
detail X
26
100
1
25
w M
Z
v
v
M
M
A
B
D
b
p
e
D
B
H
D
0
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
θ
UNIT
A
A
A
b
c
D
D
E
E
e
H
H
L
L
p
v
w
y
Z
Z
1
2
3
p
h
h
D
E
D
E
max.
0.15 1.05
0.05 0.95
0.27 0.20 14.1 7.1 14.1 7.1
0.17 0.09 13.9 6.1 13.9 6.1
16.15 16.15
15.85 15.85
0.75
0.45
1.15 1.15
0.85 0.85
7°
0°
mm
1.2
0.25
0.5
1
0.2 0.08 0.08
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-04-07
05-02-02
SOT638-1
MS-026
Fig 20. Package outline SOT638-1 (HTQFP100)
DAC1405D750_1
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Preliminary data sheet
Rev. 01 — 10 March 2010
37 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
12. Abbreviations
Table 43. Abbreviations
Acronym
B
Description
Bandwidth
CDMA
CML
Code Division Multiple Access
Current Mode Logic
CMOS
DAC
Complementary Metal-Oxide Semiconductor
Digital-to-Analog Converter
FIR
Finite Impulse Response
GSM
IF
Global System for Mobile communications
Intermediate Frequency
IMD3
LISB
Third-order InterModulation Distortion
Lower Intermediate Significant Byte
Local Multipoint Distribution Service
Least Significant Bit
LMDS
LSB
LTE
Long Term Evolution
LVDS
MMDS
MSB
Low-Voltage Differential Signaling
Multichannel Multipoint Distribution Service
Most Significant Bit
NCO
Numerically Controlled Oscillator
Negative Metal-Oxide Semiconductor
Phase-Locked Loop
NMOS
PLL
SFDR
SPI
Spurious-Free Dynamic Range
Serial Peripheral Interface
TD-SCDMA
UISB
WCDMA
WiMAX
Time Division-Synchronous Code Division Multiple Access
Upper Intermediate Significant Byte
Wideband Code Division Multiple Access
Worldwide Interoperability for Microwave Access
DAC1405D750_1
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Preliminary data sheet
Rev. 01 — 10 March 2010
38 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
13. Glossary
Spurious-Free Dynamic Range (SFDR): — The ratio between the RMS value of the
reconstructed output sine wave and the RMS value of the largest spurious observed
(harmonic and non-harmonic, excluding DC component) in the frequency domain.
Intermodulation Distortion (IMD): — From a dual-tone digital input sine wave (these
two frequencies being close together), the intermodulation distortion products IMD2 and
IMD3 (respectively, second and third-order components) are defined below.
IMD2 — The ratio of the RMS value of either tone to the RMS value of the worst second
order intermodulation product.
IMD3 — The ratio of the RMS value of either tone to the RMS value of the worst third
order intermodulation product.
Restricted Bandwidth Spurious Free Dynamic Range — The ratio of the RMS value of
the reconstructed output sine wave to the RMS value of the noise, including the
harmonics, in a given bandwidth centered around foffset
.
14. Revision history
Table 44. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
DAC1405D750_1
20100310
Preliminary data sheet
-
-
DAC1405D750_1
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Preliminary data sheet
Rev. 01 — 10 March 2010
39 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
15.3 Disclaimers
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
non-automotive qualified products in automotive equipment or applications.
DAC1405D750_1
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 March 2010
40 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
15.4 Patents
Notice is herewith given that the subject device uses one or more of the
following patents and that each of these patents may have corresponding
patents in other jurisdictions.
15.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
DAC1405D750_1
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Preliminary data sheet
Rev. 01 — 10 March 2010
41 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
17. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 3. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 4. Thermal characteristics . . . . . . . . . . . . . . . . . . .8
Table 5. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 6. Read or Write mode access description . . . . .14
Table 7. Number of bytes transferred . . . . . . . . . . . . . .14
Table 8. SPI timing characteristics . . . . . . . . . . . . . . . .15
Table 9. Register allocation map . . . . . . . . . . . . . . . . . .16
Table 10. COMMon register (address 00h)
Table 22. DAC_B_Cfg_1 register (address 0Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 23. DAC_B_Cfg_2 register (address 0Dh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 24. DAC_B_Cfg_3 register (address 0Eh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 25. DAC_Cfg register (address 0Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 26. SYNC_Cfg register (address 10h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 27. DAC_A_Aux_MSB register (address 1Ah)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 28. DAC_A_Aux_LSB register (address 1Bh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 29. DAC_B_Aux_MSB register (address 1Ch)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 30. DAC_B_Aux_LSB register (address 1Dh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 31. Recommended configuration. . . . . . . . . . . . . . 22
Table 32. Mode selection . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 33. Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 34. Sample clock phase and polarity examples . . 25
Table 35. Optimum external PLL timing settings . . . . . . 25
Table 36. Interpolation filter coefficients . . . . . . . . . . . . . 26
Table 37. Inversion filter coefficients . . . . . . . . . . . . . . . . 27
Table 38. DAC transfer function . . . . . . . . . . . . . . . . . . . 28
Table 39. IO(fs) coarse adjustment . . . . . . . . . . . . . . . . . . 29
Table 40. IO(fs) fine adjustment . . . . . . . . . . . . . . . . . . . . 30
Table 41. Digital offset adjustment . . . . . . . . . . . . . . . . . 31
Table 42. Auxiliary DAC transfer function . . . . . . . . . . . . 32
Table 43. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 44. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 39
bit description . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 11. TXCFG register (address 01h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 12. PLLCFG register (address 02h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 13. FREQNCO_LSB register (address 03h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 14. FREQNCO_LISB register (address 04h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 15. FREQNCO_UISB register (address 05h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 16. FREQNCO_MSB register (address 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 17. PHINCO_LSB register (address 07h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 18. PHINCO_MSB register (address 08h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 19. DAC_A_Cfg_1 register (address 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 20. DAC_A_Cfg_2 register (address 0Ah) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 21. DAC_A_Cfg_3 register (address 0Bh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
18. Figures
Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Fig 2. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4
Fig 3. SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Fig 4. SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . .14
Fig 5. Dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . . .22
Fig 6. Interleaved mode operation. . . . . . . . . . . . . . . . .23
Fig 7. Interleaved mode timing (8x interpolation,
AQM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Fig 17. An example of a DC interface to a 1.7 VI(cm)
AQM using auxiliary DACs . . . . . . . . . . . . . . . . . 34
Fig 18. An example of a DC interface to a 3.3 VI(cm)
AQM using auxiliary DACs . . . . . . . . . . . . . . . . . 35
Fig 19. An example of an AC interface to a 0.5 VI(cm)
AQM using auxiliary DACs . . . . . . . . . . . . . . . . . 36
Fig 20. Package outline SOT638-1 (HTQFP100) . . . . . . 37
latch on rising edge) . . . . . . . . . . . . . . . . . . . . . .23
Fig 8. LVDS clock configuration. . . . . . . . . . . . . . . . . . .24
Fig 9. Interfacing CML to LVDS . . . . . . . . . . . . . . . . . . .24
Fig 10. Input timing diagram when internal PLL
bypassed (off) . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Fig 11. Internal reference configuration. . . . . . . . . . . . . .29
Fig 12. Equivalent analog output circuit (one DAC). . . . .31
Fig 13. 1 Vo(p-p) differential output with transformer . . . . .32
Fig 14. 2 Vo(p-p) differential output with transformer . . . . .33
Fig 15. An example of a DC interface to a 1.7 VI(cm)
AQM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Fig 16. An example of a DC interface to a 3.3 VI(cm)
DAC1405D750_1
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 — 10 March 2010
42 of 43
DAC1405D750
NXP Semiconductors
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
19. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
10.14.3 AC interface to an Analog Quadrature
Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 35
2
3
4
5
10.15
Power and grounding. . . . . . . . . . . . . . . . . . . 36
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 37
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision history . . . . . . . . . . . . . . . . . . . . . . . 39
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
11
12
13
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
14
15
Legal information . . . . . . . . . . . . . . . . . . . . . . 40
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 40
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Patents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 41
15.1
15.2
15.3
15.4
15.5
7
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal characteristics . . . . . . . . . . . . . . . . . . 8
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 9
10
10.1
10.2
Application information. . . . . . . . . . . . . . . . . . 13
General description . . . . . . . . . . . . . . . . . . . . 13
Serial peripheral interface. . . . . . . . . . . . . . . . 13
Protocol description . . . . . . . . . . . . . . . . . . . . 13
SPI timing description. . . . . . . . . . . . . . . . . . . 14
Detailed descriptions of registers . . . . . . . . . . 15
Detailed register descriptions . . . . . . . . . . . . . 17
Recommended configuration . . . . . . . . . . . . . 22
Input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Dual-port mode. . . . . . . . . . . . . . . . . . . . . . . . 22
Interleaved mode . . . . . . . . . . . . . . . . . . . . . . 22
Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Timing when using the internal PLL
16
17
18
19
Contact information . . . . . . . . . . . . . . . . . . . . 41
Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.3
10.3.1
10.3.2
10.4
10.5
10.5.1
(PLL on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Timing when using an external PLL
10.5.2
(PLL off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Quadrature modulator and Numerically
10.6
10.7
Controlled Oscillator . . . . . . . . . . . . . . . . . . . . 26
NCO in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 27
Low-power NCO. . . . . . . . . . . . . . . . . . . . . . . 27
Minus_3dB function . . . . . . . . . . . . . . . . . . . . 27
x / (sin x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DAC transfer function . . . . . . . . . . . . . . . . . . . 28
Full-scale current . . . . . . . . . . . . . . . . . . . . . . 28
10.7.1
10.7.2
10.7.3
10.8
10.9
10.10
10.10.1 Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.10.2 Full-scale current adjustment . . . . . . . . . . . . . 29
10.11
10.12
10.13
10.14
Digital offset adjustment . . . . . . . . . . . . . . . . . 30
Analog output . . . . . . . . . . . . . . . . . . . . . . . . . 31
Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 32
Output configuration . . . . . . . . . . . . . . . . . . . . 32
10.14.1 Basic output configuration . . . . . . . . . . . . . . . 32
10.14.2 DC interface to an Analog Quadrature
Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 33
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 March 2010
Document identifier: DAC1405D750_1
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