DAC1627D1G25 [NXP]

Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating; 双16位DAC ， LVDS接口，高达1.25 GSPS ， X2，X4和X8插值


型号：	DAC1627D1G25
厂家：	NXP
描述：	Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating 双16位DAC ， LVDS接口，高达1.25 GSPS ， X2，X4和X8插值转换器数模转换器
文件：	总69页 (文件大小：1677K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DAC1627D1G25

Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and

x8 interpolating

Rev. 1 — 29 April 2011

Objective data sheet

1. General description

The DAC1627D1G25 is a high-speed 16-bit dual channel Digital-to-Analog Converter

(DAC) with selectable ×2, ×4 and ×8 interpolating filters optimized for multi-carrier and

broadband wireless transmitters at sample rates of up to 1.25 Gsps. Supplied from a

3.3 V and a 1.8 V source, the DAC1627D1G25 integrates a differential scalable output

current up to 31.8 mA.

The DAC1627D1G25 is capable of meeting multi-carrier GSM specifications. For

example, with an output frequency of 150 MHz and a DAC clock frequency of 1.22 Gsps

the full-scale dynamic range is:

• SFDR_RBW= 85 dBc (bandwidth = 250 MHz)

• IMD3 = 85 dBc

The Serial Peripheral Interface (SPI) provides full control of the DAC1627D1G25.

The DAC1627D1G25 integrates a Low Voltage Differential Signaling (LVDS) Double Data

Rate (DDR) receiver interface, with an on-chip 100 Ω termination. The LVDS DDR

interface accepts a multiplex input data stream such as interleaved or folded. An internal

LVDS input auto-calibration ensures the robustness and stability of the interface.

Digital on-chip modulation converts the complex I and Q inputs from baseband to IF. The

mixer frequency is set by a 40-bit Numerically Controlled Oscillator (NCO). High resolution

internal gain, phase and offset control provide outstanding image and Local Oscillator

(LO) signal rejection at the system analog modulator output.

An inverse (sin x) / x function ensures a controlled flatness 0.5 dB for high bandwidths at

the DAC output.

Multiple device synchronization allows synchronization of the outputs of multiple DAC

devices. MDS guarantees a maximum skew of one output clock period between several

devices.

The DAC1627D1G25 includes a very low noise capacitor-free integrated Phase-Locked

Loop (PLL) multiplier which generates a DAC clock rate from the LVDS clock rate.

The DAC1627D1G25 is available in a HVQFN72 package (10 mm × 10 mm).

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

2. Features and benefits

Dual 16-bit resolution

Synchronization of multiple DAC

devices

1.25 Gsps maximum update rate

Selectable ×2, ×4 and ×8 interpolation

filters

3 or 4 wires mode SPI interface

Differential scalable output current from

6.95 mA to 31.8 mA

Very low noise capacitor-free integrated External analog offset control

Phase-Locked Loop (PLL)

(10-bit auxiliary DACs)

Embedded Numerically Controlled

Oscillator (NCO) with 40-bit

programmable frequency

High resolution internal digital gain and

offset control to support high

performance IQ-modulator image

rejection

Embedded complex modulator

1.8 V and 3.3 V power supplies

Internal phase correction

Inverse (sin x) / x function

LVDS DDR compatible input interface

with on-chip 100 Ω terminations

Power-down mode and Sleep mode;

5-bit NCO low power mode

LVDS DDR input clock up to 312.5 MHz On-chip 1.25 V reference

LVDS or LVPECL compatible DAC clock Industrial temperature range −40 °C to

+85 °C

Interleaved or folded I and Q data input 72 pins small form factor HVQFN

mode

package

3. Applications

Wireless infrastructure: MG_GSM, LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA

Communication: LMDS/MMDS, point-to-point

Direct Digital Synthesis (DDS)

Broadband wireless systems

Digital radio links

Instrumentation

Automated Test Equipment (ATE)

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

DAC1627D1G25

HVQFN72

plastic thermal enhanced very thin quad flat package; no leads;

SOT813-3

72 terminals; body 10 × 10 × 0.85 mm

DAC1627D1G25

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 29 April 2011

2 of 69

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5. Block diagram

SDO

SDIO

SCS_N

SCLK

DAC1627D

NCO

10-BIT

OFFSET

CONTROL

SPI

AUXAP

AUXAN

40-bit frequency setting

16-bit phase adjustment

AUX.

DAC

cos

sin

DCMSU

10-BIT

ANALOG GAIN

CONTROL

FIR 1

FIR 2

FIR 3

IOUTAP

IOUTAN

DAC A

sin X

PHASE

COMP

ALIGNP

ALIGNN

REF.

BANDGAP

AND

LD(15)P to

LVDS

GAPOUT

VIRES

MDS

COARSE

OFFSET

CONTROL

LD(0)P

DDR/

CDI

DIF

LD(15)N to

LD(0)N

BIASING

LDCLKP

LDCLKN

FIR 1

FIR 2

FIR 3

sin X

PHASE

COMP

IOUTBP

IOUTBN

DAC B

10-BIT

ANALOG GAIN

CONTROL

CLKP

CLKN

CLOCK GENERATOR/PLL

COMPLEX MODULATOR

10-BIT

OFFSET

CONTROL

AUXBP

AUXBN

MDSP

MDSN

AUX.

DAC

MULTI-DAC

SYNCHRONIZATION

RESET_N

001aan827

Fig 1. Block diagram

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

6. Pinning information

6.1 Pinning

terminal 1

index area

CLKP

CLKN

RESET_N

SCS_N

SCLK

SDIO

MDSP

MDSN

SDO

ALIGNP

ALIGNN

LD[15]P

LD[15]N

LD[14]P

LD[14]N

IO0

IO1

LD[0]N

LD[0]P

LD[1]N

LD[1]P

DAC1627D1G25

DDD(1V8)

LD[13]P

LD[2]N

LD[2]P

LD[3]N

LD[3]P

LD[4]N

LD[4]P

LD[13]N

LD[12]P

LD[12]N

LD[11]P

LD[11]N

001aan828

Transparent top view

Fig 2. Pin configuration

6.2 Pin description

Table 2.

Symbol

CLKP

Pin description

Type^[1]Description

DAC clock positive input

DAC clock negative input

CLKN

MDSP

MDSN

multi-device synchronization positive signal

multi-device synchronization negative signal

Test mode selection (connect to GND)

positive input for data alignment

ALIGNP

ALIGNN

LD[15]P

LD[15]N

negative input for data tanglement

LVDS positive input bit 15^[2]

LVDS negative input bit 15^[2]

DAC1627D1G25

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Objective data sheet

Rev. 1 — 29 April 2011

4 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 2.

Pin description …continued

Type^[1]Description

Symbol

LD[14]P

LD[14]N

V_DDD(1V8)

LD[13]P

LD[13]N

LD[12]P

LD[12]N

LD[11]P

LD[11]N

V_DDD(1V8)

LD[10]P

LD[10]N

LD[9]P

LD[9]N

LD[8]P

LD[8]N

V_DDD(1V8)

LCKP

LVDS positive input bit 14^[2]

LVDS negative input bit 14^[2]

1.8 V digital power supply

LVDS positive input bit 13^[2]

LVDS negative input bit 13^[2]

LVDS positive input bit 12^[2]

LVDS negative input bit 12^[2]

LVDS positive input bit 11^[2]

LVDS negative input bit 11^[2]

1.8 V digital power supply

LVDS positive input bit 10^[2]

LVDS negative input bit 10^[2]

LVDS positive input bit 9^[2]

LVDS negative input bit 9^[2]

LVDS positive input bit 8^[2]

LVDS negative input bit 8^[2]

1.8 V digital power supply

LVDS positive data clock input

LVDS negative data clock input

connect to ground

LVDS positive input bit 7^[2]

LVDS negative input bit 7^[2]

LVDS positive input bit 6^[2]

LVDS negative input bit 6^[2]

LVDS positive input bit 5^[2]

LVDS negative input bit 5^[2]

1.8 V digital power supply

LVDS positive input bit 4^[2]

LVDS negative input bit 4^[2]

LVDS positive input bit 3^[2]

LVDS negative input bit 3^[2]

LVDS positive input bit 2^[2]

LVDS negative input bit 2^[2]

1.8 V digital power supply

LVDS positive input bit 1^[2]

LVDS negative input bit 1^[2]

LVDS positive input bit 0^[2]

LVDS negative input bit 0^[2]

IO port bit 1

LCKN

GND_DP

LD[7]P

LD[7]N

LD[6]P

LD[6]N

LD[5]P

LD[5]N

V_DDD(1V8)

LD[4]P

LD[4]N

LD[3]P

LD[3]N

LD[2]P

LD[2]N

V_DDD(1V8)

LD[1]P

LD[1]N

LD[0]P

LD[0]N

IO1

IO0

IO port bit 0

SDO

SPI data output

DAC1627D1G25

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Objective data sheet

Rev. 1 — 29 April 2011

5 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 2.

Pin description …continued

Type^[1]Description

Symbol

SDIO

SPI data input/output

SCLK

SPI clock

SCS_N

SPI chip select (active LOW)

general reset (active LOW)

RESET_N

V_{DDA(1V8)_D}

IOUTBN

IOUTBP

V_{DDA(1V8)_D}

V_DDA(3V3)

AUXBP

1.8 V analog power supply (DAC core)

complementary DAC B output current

DAC B output current

1.8 V analog power supply (DAC core)

3.3 V analog power supply

auxiliary DAC B output current

complementary auxiliary DAC B output current

1.8 V analog power supply (PLL)

DAC biasing resistor

AUXBN

V_{DDA(1V8)_P1}

VIRES

GAPOUT

V_{DDA(1V8)_P2}

AUXAN

band gap input/output voltage

1.8 V analog power supply (PLL)

complementary auxiliary DAC A output current

auxiliary DAC A output current

3.3 V analog power supply

AUXAP

V_DDA(3V3)

V_{DDA1V8_D}

IOUTAP

IOUTAN

V_{DDA(1V8)_D}

GND

1.8 V analog power supply (DAC core)

DAC A output current

complementary DAC A output current

1.8 V analog power supply (DAC core)

ground (exposed die pad)

[1] P: power supply; G: ground; I: input; O: output.

[2] The LVDS input data bus order can be reversed and each element can be swapped between P and N using

dedicated registers (see Table 86, Table 87 and Table 88).

7. Limiting values

Table 3.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

Unit

V_DDA(3V3)analog supply voltage

(3.3 V)

−0.5

+4.6

V_DDD(1V8)digital supply voltage

(1.8 V)

−0.5

+2.5

[1]

V_DDA(1V8)analog supply voltage

(1.8 V)

V_I

input voltage

input pins referenced to GND

−0.5

<tbd>

+4.6

V_O

output voltage

pins IOUTAP, IOUTAN,

IOUTBP, IOUTBN, AUXAP,

AUXAN, AUXBP and AUXBN

referenced to GND

DAC1627D1G25

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 29 April 2011

6 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 3.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions

Min

−55

−40

Max

+150

+85

Unit

°C

T_stg

T_amb

T_j

storage temperature

ambient temperature

junction temperature

°C

+125

°C

[1] The analog 1.8 V power supply must be connected to pins VDDA1V8_D, VDDA1V8_P1, and

VDDA1V8_P2.

8. Thermal characteristics

Table 4.

Thermal characteristics

Symbol

Parameter

Conditions

Typ

Unit

[1]

R_th(j-a)

thermal resistance from junction

to ambient

16.2

K/W

R_th(j-c)

thermal resistance from junction

to case

6.7

K/W

[1] Value for six layers board in still air with a minimum of 49 thermal vias.

DAC1627D1G25

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 29 April 2011

7 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

9. Characteristics

Table 5.

Characteristics

V_DDA(1V8)= 1.8 V; V_DDD(1V8)= 1.8 V; V_DDA(3V3)= 3.3 V; Typical values measured at T_amb= +25 °C; R_L= 50 Ω; I_O(fs)= 20 mA;

maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition

defined in Figure 22; output level = 1 V (p-p).

Symbol

V_DDA(3V3)

V_DDD(1V8)

V_DDA(1V8)

I_DDA(3V3)

I_DDD(1V8)

Parameter

Conditions

Test

Min

Typ

3.3

1.8

Max

3.45

1.9

Unit

[1]

analog supply

voltage (3.3 V)

3.15

1.7

digital supply

voltage (1.8 V)

[2]

analog supply

voltage (1.8 V)

1.7

1.9

analog supply

current (3.3 V)

Aux DAC on

<tbd>

digital supply

current (1.8 V)

f_s= 983.04 67;

×4 interpolation; no NCO;

MDS on

520

f_s= 620 Msps;

<tbd>

440

<tbd>

×2 interpolation; NCO on;

no MDS

[2]

I_DDA(1V8)

analog supply

current (1.8 V)

f_s= 983.04 Msps; 1 V (p-p)

f_s= 620 Msps; 1 V (p-p)

<tbd>

210

<tbd>

210

P_tot

total power

dissipation

f_s= 1228.8 Msps;

×4 interpolation; NCO on;

MDS off

1770

f_s= 983.04 Msps;

×4 interpolation; 5-bit NCO;

MDS off

1530

<tbd>

1540

1400

f_s= 983.04 Msps;

×4 interpolation; NCO off;

MDS off

f_s= 737.28 Msps;

×4 interpolation; 5-bit NCO;

MDS off

f_s= 620 Msps;

×2 interpolation; 40-bit NCO;

MDS off

full power-down

1.2

Clock inputs (pins CLKP, CLKN)

V_i(clk)dif

differential clock peak-to-peak

200

2000

input voltage

R_i

C_i

input resistance

input capacitance

<tbd>

MΩ

Digital inputs (pins LD[15]P to LD[0]P, LD[15]N to LD[0]N, LCKP and LCKN)

V_i

input voltage

input differential |V_gpd| < 50 mV^[3]

|V_gpd| < 50 mV^[3]

825

1575

+100

V_idth

−100

threshold voltage

DAC1627D1G25

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 29 April 2011

8 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 5.

Characteristics …continued

V_DDA(1V8)= 1.8 V; V_DDD(1V8)= 1.8 V; V_DDA(3V3)= 3.3 V; Typical values measured at T_amb= +25 °C; R_L= 50 Ω; I_O(fs)= 20 mA;

maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition

defined in Figure 22; output level = 1 V (p-p).

Symbol

Parameter

Conditions

Test

[1]

Min

Typ

Max

Unit

R_i

C_i

input resistance

100

input capacitance

<tbd>

Digital inputs/outputs (pins MDSN, MDSP)

V_o(dif)(p-p)

peak-to-peak

differential output

voltage

600

C_o(L)

C_i

output load

capacitance

between GND and pin

MDSN or MDSP

<tbd>

input capacitance between GND and pin

MDSN or MDSP

<tbd>

R_i

input resistance

100

V_i

input voltage

input differential |V_gpd| < 50 mV^[3]

|V_gpd| < 50 mV^[3]

825

−100

1575

+100

V_idth

threshold voltage

Digital inputs/outputs (pins SDO, SDIO, SCLK, SCS_N, RESET_N)

V_IL

V_IH

V_OL

V_OH

I_IL

LOW-level input

voltage

GND

0.3V_DD(1V8)

HIGH-level input

voltage

0.7V_DD(1V8)

V_DD(1V8)

LOW-level output pins SDO and SDIO

voltage

<tbd>

HIGH-level

output voltage

pins SDO and SDIO

<tbd>

V_DD(1V8)

LOW-level input V_IL= <tbd> V

current

<tbd>

μA

I_IH

HIGH-level input V_IH= <tbd> V

current

C_i

input capacitance

Analog outputs (pins IOUTAP, IOUTAN, IOUTBP, IOUTBN)

I_O(fs)

full-scale output controlled by the analog

6.19

31.8

current

GAIN registers (see Table 46

to Table 49)

default value

V_O

output voltage

compliance range

<tbd>

V_DDA(3V3)

V_O(cm)

common-mode

output voltage

2.8

R_o

C_o

output resistance

250

kΩ

output

capacitance

N_DAC(mono)

DAC

guaranteed

<tbd>

bits

monotonicity

DAC1627D1G25

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 29 April 2011

9 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 5.

Characteristics …continued

V_DDA(1V8)= 1.8 V; V_DDD(1V8)= 1.8 V; V_DDA(3V3)= 3.3 V; Typical values measured at T_amb= +25 °C; R_L= 50 Ω; I_O(fs)= 20 mA;

maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition

defined in Figure 22; output level = 1 V (p-p).

Symbol

Parameter

Conditions

Test

[1]

Min

Typ

Max

Unit

ΔE_O

offset error

variation

<tbd>

ppm/°C

ΔE_G

gain error

variation

Reference voltage output (pin GAPOUT)

V_O(ref)

reference output T_amb= +25 °C

voltage

<tbd>

1.25

<tbd>

I_O(ref)

reference output 1.25 V external voltage

current

μA

ΔV_O(ref)

reference output

voltage variation

<tbd>

ppm/°C

Analog auxiliary outputs (pins AUXAP, AUXAN, AUXBP and AUXBN)

I_O(fs)

full-scale output auxiliary DAC A;

2.2

current

differential outputs

auxiliary DAC B;

differential outputs

V_O(aux)

auxiliary output

voltage

compliance range

guaranteed

N_DAC(aux)monoauxiliary DAC

monotonicity

Bits

LVDS input timing

f_data

data rate

input; ×2 interpolation

input; ×4 interpolation

input; ×8 interpolation

<tbd>

−<tbd>

312.5

MHz

312.5

156.25

+<tbd>

t_sk(clk-D)

skew time from

clock to data

input

DAC output timing

f_s

t_s

sampling rate

settling time

1250

Msps

to ± 0.5 LSB

Internal PLL timing

f_ssampling rate

40-bit NCO frequency range; f_s= 1000 Msps

1000

Msps

f_NCO

NCO frequency

two’s complement coding

reg value = 8000000000h

−500

MHz

mHz

reg value = FFFFFFFFFFh D

−0.9095

reg value = 0000000000h

reg value = 0000000001h

+0.9095

mHz

MHz

mHz

reg value = 7FFFFFFFFFh D

+499.99909 -

0.9095

f_step

step frequency

DAC1627D1G25

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 29 April 2011

10 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 5.

Characteristics …continued

V_DDA(1V8)= 1.8 V; V_DDD(1V8)= 1.8 V; V_DDA(3V3)= 3.3 V; Typical values measured at T_amb= +25 °C; R_L= 50 Ω; I_O(fs)= 20 mA;

maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition

defined in Figure 22; output level = 1 V (p-p).

Symbol

Parameter

Conditions

Test

[1]

Min

Typ

Max

Unit

Low power NCO frequency range; f_s= 1000 MHz

f_NCO

NCO frequency

two’s complement coding

reg value = F8000000000h

reg value = 00000000000h

reg value = 08000000000h

reg value = 7FFFFFFFFFh

−500

MHz

−31.25

+31.25

+468.75

31.25

MHz

f_step

step frequency

Dynamic performance

SFDR

spurious-free

f_data= 307.2 MHz;

dynamic range

f_s= 1228.8 Msps; BW = f_s/ 2

f_o= 20 MHz at −1 dBFS;

dBc

f_data= 245.76 MHz;

f_s= 983.04 Msps; BW = f_s/ 2

f_o= 20 MHz at −1 dBFS

SFDR_RBW

restricted

bandwidth

spurious-free

dynamic range

f_data= 245.76 MHz;

f_s= 983.04 Msps;

f_o= 150 MHz

BW = 100 MHz

BW = 180 MHz

dBc

<tbd>

f_data= 307.2 MHz;

f_s= 1228.8 Msps;

f_o= 210 MHz

BW = 100 MHz

BW = 180 MHz

<tbd>

dBc

IMD3

third-order

f_data= 245.76 MHz;

f_s= 983.04 Msps;

intermodulation

distortion

f_o1= 20 MHz; f_o2= 21 MHz;

×4 interpolation;

output level = −1 dBFS

f_data= 245.76 MHz;

dBc

f_s= 983.04 Msps;

f_o1= 152 MHz;

f_o2= 155.1 MHz;

f_s= 1228.8 MHz;

×4 interpolation;

output level = −1 dBFS

DAC1627D1G25

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 29 April 2011

11 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 5.

Characteristics …continued

V_DDA(1V8)= 1.8 V; V_DDD(1V8)= 1.8 V; V_DDA(3V3)= 3.3 V; Typical values measured at T_amb= +25 °C; R_L= 50 Ω; I_O(fs)= 20 mA;

maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition

defined in Figure 22; output level = 1 V (p-p).

Symbol

Parameter

Conditions

Test

[1]

Min

Typ

Max

Unit

ACPR

adjacent channel f_s= 1228.8 Msps;

power ratio

×4 interpolation;

f_o= 210 MHz

1 carrier; BW = 5 MHz

2 carriers; BW = 10 MHz

4 carriers; BW = 20 MHz

dBc

NSD

noise spectral

density

f_s= 983.04 Msps;

×4 interpolation;

-164

dBm/Hz

f_o= 20 MHz at −1 dBFS

f_s= 983.04 Msps;

-161

dBm/Hz

×4 interpolation;

f_o= 153.6 MHz at −1 dBFS

[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.

[2] V_{DDA(1V8)_D}, V_{DDA(1V8)_P1}and V_{DDA(1V8)_P2}must be connected to the same 1.8 V analog power supply. it is recommended to use

dedicated filters for the three power pins.

[3] |V_gpd| represents the ground potential difference voltage. This voltage is the result of current flowing through the finite resistance and the

inductance between the receiver and the driver circuit ground voltages.

10. Application information

10.1 General description

The DAC1627D1G25 is a dual 16-bit DAC operating up to 1250 Msps. Each DAC consists

of a segmented architecture, comprising a 6-bit thermometer sub-DAC and a 10-bit binary

weighted sub-DAC.

A maximum input LVDS DDR data rate of up to 312.5 MHz and a maximum output

sampling rate of 1250 Msps ensure more flexibility for wide bandwidth and multi-carrier

systems. The internal 40-bit NCO of the DAC1627D1G25 simplifies the frequency

selection of the system. The DAC1627D1G25 provides ×2, ×4 or ×8 interpolation filters

that are very useful for removing the undesired images.

Each DAC generates two complementary current outputs on pins IOUTAP and IOUTAN

and pins IOUTBP and IOUTBN. These outputs provide a full-scale output current (I_O(fs)) of

up to 31.8 mA. An internal reference is available for the reference current which is

externally adjustable using pin VIRES.

High resolution internal gain, phase and offset control provide outstanding image and

Local Oscillator (LO) signal rejection at the system analog modulator output.

Multiple device synchronization enables synchronization of the outputs of multiple DAC

devices. MDS guarantees a maximum skew of one output clock period between several

devices.

All functions can be set using an SPI interface.

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10.2 Serial Peripheral Interface (SPI)

10.2.1 Protocol description

The DAC1627D1G25 serial interface is a synchronous serial communication port ensures

easy interface with many industry microprocessors. It provides access to the registers that

define the operating modes of the chip in both write and read mode.

This interface can be configured as a 3-wire type (pin SDIO as bidirectional pin) or 4-wire

type (pins SDIO and SDO as unidirectional pins, input and output port respectively). In

both configurations, SCLK acts as the serial clock and SCS_N as the serial chip select.

Figure 3 shows the SPI protocol. Each read/write operation is followed by an SCS_N

signal and enabled by a LOW assertion to drive the chip with two to five bytes, depending

on the content of the instruction byte (see Table 7).

RESET_N

(optional)

SCS_N

SCLK

SDIO

R/W

SDO

(optional)

001aan829

Fig 3. SPI protocol

R/W indicates the mode access (see Table 6)

Table 6.

Read or Write mode access description

Description

R/W

Write mode operation

Read mode operation

Table 7 shows the number of bytes to be transferred. N1 and N0 indicate the number of

bytes transferred after the instruction byte.

Table 7.

Number of bytes to be transferred

Number of bytes transferred

1 byte

2 bytes

3 bytes

4 bytes

A[4:0] indicates which register is being addressed. If a multiple transfer occurs, this

address concerns the first register. Next are those which follow directly in a decreasing

order (see Table 23, Table 55 and Table 79).

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The DAC1627D1G25 incorporates more than the 32 SPI registers allowed by the address

value A[4:0]. It uses three SPI register pages (page_00, page_01, and page_0A), each

containing 32 registers. The 32^ndregister of each page indicates which page is currently

addressed (00h, 01h or 0Ah).

10.2.2 SPI timing description

The SPI interface can operate at a frequency up to 15 MHz. The SPI timings are shown in

Figure 4.

w(RESET_N)

RESET_N

(optional)

50 %

h(SCS_N)

su(SCS_N)

SCS_N

50 %

w(SCLK)

SCLK

SDIO

50 %

h(SDIO)

001aan830

su(SDIO)

Fig 4. SPI timing diagram

The SPI timing characteristics are given in Table 8.

Table 8.

Symbol

f_SCLK

SPI timing characteristics

Parameter

Min

Typ

Max

Unit

MHz

SCLK frequency

t_w(SCLK)

SCLK pulse

width

t_{su(SCS_N)}

t_{h(SCS_N)}

t_su(SDIO)

SCS_N set-up

time

SCS_N hold

time

SDIO set-up

time

t_h(SDIO)

SDIO hold time

t_{w(RESET_N)}

RESET_N pulse

width

10.3 Power-on sequence

There are three steps for the power-on sequence (see Figure 5):

1. The board is power-on. At the turn-on time, all DAC1627D1G25 supplies have

reached their specification ranges.

2. At least 1 μs after the turn-on time pin RESET_N must be released.

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3. When the DAC clock and LVDS clock are stable, the SPI configuration is sent to the

DAC1627D1G25. Writing 0 in bits RST_DCLK and RST_LCLK of the register

MAIN_CNTRL (see Table 80) starts the automatic calibration. 30 μs after this

calibration, the DAC1627D1G25 is operational.

WRITE DAC CONFIGURATION

START CLOCK CALIBRATION

SPI bus

RESET_N

power supplies

time

rst

spi_start

power in

specification

range

001aan810

Fig 5. Power-on sequence

10.4 LVDS Data Input Format (DIF) block

The Data Input Formatting (DIF) block captures and resynchronizes data on the LVDS bus

with its own LCLKP/LCLKN clock. Each LVDS input buffer has an internal resistance of

100 Ω, so an external resistor is not required. The DIF block includes two sub-blocks:

• LDVS receiver:

Provides high flexibility for the LVDS interface, especially for the PCB layout and the

control of the input port polarity and the input port mapping.

• Data format block:

Enables the adaptation, which ensures the support of several data encoding modes.

16 PA[15..0]

16 PB[15..0]

16 I[15..0]

16 Q[15..0]

LD[15]P

LD[15]N

to DAC A

to DAC B

LD[0]P

LD[0]N

LVDS

RECEIVER

DATA

FORMAT

LCLKP

LCLKN

LCLK

001aan392

Fig 6. LVDS Data Input Format (DIF) block diagram

10.4.1 Input port polarity

The polarity of each individual LVDS input (LD[15]P to LD[0]P and LD[15]N to LD[0]N) can

be changed, ensuring a much easier PCB layout design. The input polarity is controlled

with bits LD_POL[7:0] in register LD_POL_LSB (see Table 86) and bits LD_POL[15:8] in

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10.4.2 Input port mapping

Inverting the order of the LSB and the MSB of the LVDS bus using bit WORD_SWAP in

Table 9.

Input LVDS bus swapping

Internal LVDS bus

External LVDS bus

(WORD_SWAP = 0)

External LVDS bus

(WORD_SWAP = 1)

LDI[15]P,N

LDI[14]P,N

LDI[13]P,N

LDI[12]P,N

LDI[11]P,N

LDI[10]P,N

LDI[9]P,N

LDI[8]P,N

LDI[7]P,N

LDI[6]P,N

LDI[5]P,N

LDI[4]P,N

LDI[3]P,N

LDI[2]P,N

LDI[1]P,N

LDI[0]P,N

LD[15]P,N

LD[14]P,N

LD[13]P,N

LD[12]P,N

LD[11]P,N

LD[10]P,N

LD[9]P,N

LD[8]P,N

LD[7]P,N

LD[6]P,N

LD[5]P,N

LD[4]P,N

LD[3]P,N

LD[2]P,N

LD[1]P,N

LD[0]P,N

LD[1]P,N

LD[2]P,N

LD[3]P,N

LD[4]P,N

LD[5]P,N

LD[6]P,N

LD[7]P,N

LD[8]P,N

LD[9]P,N

LD[10]P,N

LD[11]P,N

LD[12]P,N

LD[13]P,N

LD[14]P,N

LD[15]P,N

10.4.3 Input port swapping

The LVDS DDR receiver block internally maps the incoming LVDS data bus into two

buses with a single data rate (Figure 7).

PA[15..0]

LD[15..0]P/N

to DAC A

A0 B0 A1 B1 A2 B2 A3 B3

LVDS

RECEIVER

PB[15..0]

LCLK

to DAC B

LCLKP/N

001aan393

Fig 7. LVDS DDR receiver mapping LDAB SWAP = 0

These two buses can be swapped internally using bit LDAB_SWAP of register

LD_CNTRL (see Table 88 and Figure 8).

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PA[15..0]

LD[15..0]P/N

to DAC A

A0 B0 A1 B1 A2 B2 A3 B3

LVDS

RECEIVER

PB[15..0]

LCLK

to DAC B

LCLKP/N

001aan394

Fig 8. LVDS DDR receiver mapping LDAB SWAP = 1

10.4.4 Input port formatting

The LVDS DDR input bus multiplexes two 16-bit streams. The LVDS receiver block

demultiplexes these two streams.

The two streams can carry two data formats:

• Folded

• Interleaved

The data format block is in charge of the data format adaptation (see Figure 9).

PA[15..0]

LD[15..0]P/N

to DAC A

A0 B0 A1 B1 A2 B2 A3 B3

LVDS

RECEIVER

DATA

FORMAT

PB[15..0]

LCLK

to DAC B

LCLKP/N

001aan395

Fig 9. LVDS DDR data formats

The DAC1627D1G25 can correctly decode the input stream using bit IQ_FORMAT of

LVDS DDR bus.

Table 10 shows the format mapping between the LVDS input data and the data sent to the

two DAC channels depending on the data format selected.

Table 10. Folded and interleaved format mapping

Data format

Data bit mapping

interleaved format (IQ_FORMAT = 1)

folded format (IQ_FORMAT = 0)

In[15..0] = An[15..0]; Qn[15..0] = Bn[15..0]

In[15..8] = An[15..8]; In[7..0] = Bn[15..8]

Qn[15..8] = An[7..0]; Qn[7..0] = Bn[7..0]

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10.5 Input clock

The DAC1627D1G25 operates with two clocks, one for the LVDS DDR interface and one

for the DAC core.

10.5.1 LVDS DDR clock

The LVDS DDR clock can be interfaced as shown in Figure 10 because the clock buffer

contains a 100 Ω internal resistor.

DAC1627D

LCLKP

Z = 100 Ω

LVDS

100 Ω LVDS

LCLKN

001aan811

Fig 10. LVDS DDR clock configuration

10.5.2 DAC core clock

The DAC core clock can achieve a frequency of up to 1.25 Gsps. It includes internal

biasing to support both AC-coupling and DC-coupling. The clock can be easily connected

to any LVDS, CML or PECL clock sources.

Depending on the interface selected, the hardware configuration varies

(see Figure 11 to Figure 13).

CLKP

Z = 100 Ω

100 Ω

LVDS

DAC1627D

CLKN

001aan813

a. DC-coupling

100 nF

CLKP

CLKN

Z = 100 Ω

100 Ω

100 nF

LVDS

DAC1627D

001aan812

b. AC-coupling

Fig 11. DAC core clock: LVDS configuration

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50 Ω

3.3 V

100 nF

CLKP

Z = 50 Ω

CML

DAC1627D

100 nF

CLKN

Z = 50 Ω

50 Ω

3.3 V

001aan831

Fig 12. DAC core clock: CML configuration with AC-coupling

200 Ω

100 nF

CLKP

Z = 50 Ω

PECL

100 Ω

CLKN

DAC1627D

100 nF

Z = 50 Ω

200 Ω

001aan832

Fig 13. DAC core clock: PECL configuration with AC-coupling

10.6 Timing

The DAC1627D1G25 can operate at an update rate (f_s) of up to 1.25 Gsps and with an

input data rate (f_data) of up to 312.5 MHz.

The sampling position of the LVDS data can be tuned using a 16-step compensation delay

clock. The delay clock (see Figure 14, signals LDCLKPcp and LDCLKNcp) is used

internally to obtain a control signal, which enables calibrating the compensation delay at

start-up and monitoring if the sampling position is properly aligned.

Figure 14 shows how the compensation delay helps to recover the LVDS DDR data on

both the A and B paths.

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LDCLKN

LDCLKP

LD[i]N

D [i]

n + 1

[i]

n + 2

[i]

LD[i]P

cmp

LDCLKNcp

LDCLKPcp

[i]

D [i]

[i]

LDA[i]

LDB[i]

n − 1

n + 2

[i]

n − 1

n + 1

n + 3

001aan400

Fig 14. LVDS DDR demux timing (LVDS A and B paths not swapped; LDAB_SWAP = 0)

The compensation delay time, referred to as t_cmpin Figure 14, can be tuned automatically

or manually.

Automatic tuning is recommended for a high-speed LVDS data rate (> 300 MHz). The

external LVDS data and clock signals aligns the rising and falling edges. The timing

requirement is defined in Figure 15 and in Table 5.

LVDS data

sk(min)

sk(max)

LVDS clock

001aan833

t_sk(min)= minimum skew time

t_sk(max)= maximum skew time

Fig 15. Timing requirement automatic tuning

When tuning manually, the compensation delay time (t_cmpin Figure 14), can be tuned as

shown in Table 11 using bits LDCLK_DEL[3:0] of register MAN_LDCLKDEL

(see Table 81) and bit CAL_CNTRL of register MAIN_CNTRL (see Table 80).

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Table 11. Compensation delay values for manual tuning

LDCLK_DEL[3:0]

CAL_CNTRL

Typical compensation delay

time

xxx

t_cmpcontrolled by DCSMU

block (automatic control)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

360 ps to 405 ps

435 ps to 540 ps

525 ps to 645 ps

600 ps to 720 ps

690 ps to 825 ps

780 ps to 900 ps

885 ps to 1035 ps

960 ps to 1200 ps

1260 ps to 1980 ps

1350 ps to 2160 ps

1440 ps to 2340 ps

1512 ps to 2556 ps

1566 ps to 2754 ps

1620 ps to 2952 ps

1674 ps to 3060 ps

1710 ps to 3186 ps

10.7 Operating modes

The DAC1627D1G25 requires two differential clocks:

• The LVDS clock (LDCLKP, LDCLKN) for the LVDS DDR interface

• The data clock (CLKP, CLKN) for the internal PLL and the dual DAC core

The Clock Domain Interface (CDI) and the PLL have to be set correctly to configure the

DAC1627D1G25 for an application mode. The default application is a ×2 upsampling

mode (see Section 10.7.1). The CDI can also support ×4 and ×8 upsampling modes

(see Section 10.7.2 and Section 10.7.3).

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10.7.1 CDI mode 0 (x2 interpolation)

CDI mode 0 (×2 interpolation) is required when the value of the LVDS DDR clock is twice

the internal maximum CDI frequency. Table 12 shows examples of applications using an

internal PLL or an external clock for the DAC core.

Table 12. CDI mode 0: operating modes examples

LVDS DDR

rate (MHz)

I rate;

Q rate

(Msps)

CDI

mode^[1]

FIR mode^[2]

SSBM

rate^[3]

(Msps)

DAC rate

(Msps)

PLL configuration

DAC input

PLL

status^[5]

PLL

clock^[4]

(MHz)

divider^[6]

320

×2

640

320

640

enabled

disabled

n.a.

[1] Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 89).

[2] Bits INTERPOLATION[1:0] of register TXCFG (see Table 25).

[3] If a Single Sideband Modulator (SSBM) is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 25).

[4] Pins CLKP and CLKN (see Figure 2).

[5] Bit PLL_PD of register PLLCFG (see Table 26).

[6] Bits PLL_DIV[1:0] of register PLLCFG (see Table 26).

10.7.2 CDI mode 1 (x4 interpolation)

CDI mode 1 (×4 interpolation) is required when the values of the LVDS DDR clock and the

internal CDI frequency are equal. Table 13 shows examples of applications using an

internal PLL or an external clock for the DAC core.

Table 13. CDI mode 1: operating modes examples

LVDS DDR

rate (MHz)

I rate;

Q rate

(Msps)

CDI

mode^[1]

FIR mode^[2]

SSBM

rate^[3]

(Msps)

DAC rate

(Msps)

PLL configuration

DAC input

PLL

status^[5]

PLL

clock^[4]

(MHz)

divider^[6]

250

×4

1000

250

enabled

disabled

1000

n.a.

[1] Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 89).

[2] Bits INTERPOLATION[1:0] of register TXCFG (see Table 25).

[3] If SSBM is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 25).

[4] Pins CLKP and CLKN (see Figure 2).

[5] Bit PLL_PD of register PLLCFG (see Table 26).

[6] Bits PLL_DIV[1:0] of register PLLCFG (see Table 26).

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10.7.3 CDI mode 2 (x8 interpolation)

CDI mode 2 (×8 interpolation) is required when the LVDS DDR clock is half the maximum

CDI frequency or less. Table 14 shows examples of applications using an internal PLL or

an external clock for the DAC core.

Table 14. CDI mode 2: operating modes examples

LVDS DDR

rate (MHz)

I rate;

Q rate

(Msps)

CDI

mode^[1]

FIR mode^[2]

SSBM

rate^[3]

(Msps)

DAC rate

(Msps)

PLL configuration

DAC input

PLL

status^[5]

PLL

clock^[4]

(MHz)

divider^[6]

125

×8

1000

125

enabled

disabled

1000

n.a.

[1] Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 89).

[2] Bits INTERPOLATION[1:0] of register TXCFG (see Table 25).

[3] If SSBM is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 25).

[4] Pins CLKP and CLKN (see Figure 2).

[5] Bit PLL_PD of register PLLCFG (see Table 26).

[6] Bits PLL_DIV[1:0] of register PLLCFG (see Table 26).

10.8 FIR filters

The DAC1627D1G25 integrates three selectable Finite Impulse Response (FIR) filters

which enable the use of the device with ×2, ×4 or ×8 interpolation rates. All three

interpolation FIR filters have a stop-band attenuation of at least 80 dBc and a pass-band

ripple of less than 0.0005 dB. Table 15 shows the coefficients of the interpolation filters.

001aao039

magnitude

(dB)

-20

-40

-60

-80

-100

0.1

0.2

0.3

0.4

0.5

NF (fs)

Fig 16. First stage half-band filter response

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001aao040

magnitude

(dB)

-20

-40

-60

-80

-100

0.1

0.2

0.3

0.4

0.5

NF (fs)

Fig 17. Second stage half-band filter response

001aao041

magnitude

(dB)

-20

-40

-60

-80

-100

0.1

0.2

0.3

0.4

0.5

NF (fs)

Fig 18. Third stage half-band filter response

Table 15: Interpolation filter coefficients

First interpolation filter

Second interpolation filter

Third interpolation filter

Lower

H(14)

H(13)

H(12)

H(11)

H(10)

H(9)

Upper

Value

65536

41501

−13258

7302

Lower

H(6)

H(5)

H(4)

H(3)

H(2)

H(1)

H(0)

Upper

Value

32768

20272

−5358

1986

−654

159

Lower

H(4)

H(3)

H(2)

H(1)

H(0)

Upper

Value

1024

615

−127

H(15)

H(16)

H(17)

H(18)

H(19)

H(20)

H(21)

H(7)

H(8)

H(9)

H(10)

H(11)

H(12)

H(5)

H(6)

H(7)

H(8)

−4580

2987

−3

H(8)

−1951

1250

−21

H(7)

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Table 15: Interpolation filter coefficients …continued

First interpolation filter Second interpolation filter

Third interpolation filter

Lower

H(6)

H(5)

H(4)

H(3)

H(2)

H(1)

H(0)

Upper

H(22)

H(23)

H(24)

H(25)

H(26)

H(27)

H(28)

Value

−773

456

−252

128

−58

Lower

Upper

Value

Lower

Upper

Value

−6

10.9 Single SideBand Modulator (SSBM)

The SSBM is a quadrature modulator that enables mixing the I data and Q data with the

sine and cosine signals generated by the NCO to generate path A and path B

(see Figure 19).

cos

sin

+/−

sin

+/−

cos

+/−

001aan575

Fig 19. SSBM principle

The frequency of the NCO is programmed over 40 bits. NCO enables inverting the sine

component to operate a positive or negative, lower or upper SSB upconversion

(see register TXCFG in Table 25).

10.9.1 NCO in 40 bits

When using NCO, the frequency can be set over 40 bits by five registers, FREQNCO_B0

to FREQNCO_B4 (see Table 27 to Table 31).

The frequency is calculated with Equation 1.

M × f_s

2⁴⁰

f_NCO

(1)

--------------

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Where:

• M is the two’s complement coding representation of FREQ_NCO[40:0]

• f_sis the DAC clock sampling frequency

The default settings are:

• f_NCO= 96 MHz

• f_s= 640 Msps

The phase of the NCO can be set by registers PHINCO_LSB and PHINCO_MSB over

16 bits from 0 to 360° (see Table 44 and Table 45).

10.9.2 NCO low power

When using NCO low power (bit NCO_LP_SEL; see Table 25), the frequency can be set

by the five MSB-bits of register FREQNCO_B4 (bits FREQ_NCO[39:35]; see Table 31).

The frequency is calculated with Equation 2.

M × f_s

2⁵

f_NCO

(2)

--------------

Where:

• M is the two’s complement coding representation of FREQ_NCO[39:35]

• f_sis the DAC clock sampling frequency

The phase of the NCO low power can be set by the five MSB-bits of register

PHINCO_MSB (see Table 45).

10.9.3 Complex modulator

The complex modulator upconverts the single side band by mixing NCO signals and I and

Q input signals. Table 16 shows the various possibilities set by bits MODULATION[2:0] of

Table 16. Complex modulator operation mode

MODULATION[2:0] Mode Path A

Path B

000

001

bypass

I(t)

Q(t)

positive

upper ssb

I(t) × cos(ω_NCO× t) – Q(t) × sin(ω_NCO× t) I(t) × sin(ω_NCO× t) + Q(t) × cos(ω_NCO× t)

I(t) × cos(ω_NCO× t) + Q(t) × sin(ω_NCO× t) I(t) × sin(ω_NCO× t) – Q(t) × cos(ω_NCO× t)

I(t) × cos(ω_NCO× t) – Q(t) × sin(ω_NCO× t) –I(t) × sin(ω_NCO× t) – Q(t) × cos(ω_NCO× t)

I(t) × cos(ω_NCO× t) + Q(t) × sin(ω_NCO× t) –I(t) × sin(ω_NCO× t) + Q(t) × cos(ω_NCO× t)

010

positive

lower ssb

011

negative

upper ssb

100

negative

lower ssb

others

not defined

DAC1627D1G25

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DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

10.9.4 Minus 3dB

In normal use, a full-scale pattern is also full-scale at the DAC output. Nevertheless, when

the I data and Q data come close to full-scale simultaneously, some clipping can occur.

The Minus 3dB function (bit MINUS_3DB of register DAC_OUT_CTRL; see Table 38) can

be used to reduce the 3 dB gain in the modulator. It retains a full-scale range at the DAC

output without added interferers.

10.10 Inverse sinx / x

A selectable FIR filter is incorporated to compensate the sinx / x effect caused by the

roll-off effect of the DAC. This filter introduces a loss of 3.4 dB at DC. The coefficients are

represented in Table 17.

Table 17. Inversion filter coefficients

First interpolation filter

Lower

H(1)

H(2)

H(3)

H(4)

H(5)

Upper

H(9)

H(8)

H(7)

H(6)

Value

−4

+13

−51

+610

10.11 DAC transfer function

The full-scale output current for each DAC is the sum of the two complementary current

outputs:

• I_OA(fs)= I_IOUTAP+ I_IOUTAN

• I_OB(fs))= I_IOUTBP+ I_IOUTBN

The output current of DAC A depends on the digital input data and the gain factor defined

by bits DAC_A_DGAIN[7:0] of register DAC_A_DGAIN_LSB (see Table 34) and bits

DAC_A_DGAIN[11:8] of register DAC_A_DGAIN_MSB (see Table 35).

(DACADGAIN)

DATA

((65535))

⎛

⎝

⎞

⎠

-----------------------------------------

------------------------

I_IOUTAP= I_OA(fs)

(3)

(4)

1024

(DACADGAIN)

DATA

((65535))

⎛

⎝

⎞⎞

⎠⎠

-----------------------------------------

------------------------

I_IOUTAN= I_OA(fs)× 1 –

⎝

1024

The output current of DAC B depends on the digital input data and the gain factor defined

by bits DAC_B_DGAIN[7:0] of register DAC_B_DGAIN_LSB (see Table 36) and bits

DAC_B_DGAIN[11:8] of register DAC_B_DGAIN_MSB (see Table 37).

(DACBDGAIN)

DATA

((65535))

⎛

⎝

⎞

⎠

-----------------------------------------

------------------------

I_IOUTBP= I_OB(fs)

(5)

(6)

1024

(DACBDGAIN)

DATA

((65535))

⎛

⎝

⎞⎞

⎠⎠

-----------------------------------------

------------------------

I_IOUTBN= I_OB(fs)× 1 –

⎝

1024

DAC1627D1G25

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DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

It is possible to define if the DAC1627D1G25 operates with a binary input or a

two's complement input (bit CODING; see Table 24).

Table 18 shows the output current as a function of the input data, when

I_OA(fs)= I_OB(fs)= 20 mA.

Table 18. DAC transfer function

Data

I15 to I0/Q15 to Q0

(binary coding)

I15 to I0/Q15 to Q0

(two’s complement

coding

IOUTAP/IOUTBP IOUTAN/IOUTBN

0000 0000 0000 0000 1000 0000 0000 0000 0 mA

... ... ...

1000 0000 0000 0000 0000 0000 0000 0000 10 mA

20 mA

....

...

32768

...

10 mA

...

65535

1111 1111 1111 1111

0111 1111 1111 1111

20 mA

0 mA

10.12 Full-scale current

10.12.1 Regulation

The DAC1627D1G25 reference circuitry integrates an internal band gap reference voltage

which delivers a 1.25 V reference on the GAPOUT pin. It is recommended to decouple pin

GAPOUT using a 100 nF capacitor.

The reference current is generated via an external resistor of 910 Ω (1 %) connected to

VIRES and a control amplifier sets the appropriate full-scale current (I_OA(fs)and I_OB(fs)) for

both DACs (see Figure 20)).

DAC1627D

BAND GAP

REFERENCE

100 nF

GAPOUT

AGND

DAC

910 Ω (1 %)

VIRES

CURRENT

SOURCES

ARRAY

AGND

001aan834

Fig 20. Internal reference configuration

Figure 20 shows the optimal configuration for temperature drift compensation because the

band gap reference voltage can be matched to the voltage across the feedback resistor.

The DAC current can also be adjusted by applying an external reference voltage to the

non-inverting input pin GAPOUT and by disabling the internal band gap reference voltage

(bit GAP_PON of the COMMON register; see Table 24).

10.12.2 Full-scale current adjustment

The default full-scale current (I_O(fs)) is 20 mA but further adjustments can be made by the

user to both DACs independently via the serial interface from 6.95 mA to 28.7 mA, ±11 %.

DAC1627D1G25

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DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

The settings applied to DAC_A_GAIN_COARSE[3:0] (register 17h; see Table 46 and

(register 19h; see Table 48 and register 1Ah see Table 49;) define the coarse variation of

the full-scale current (see Table 19).

Table 19. I_O(fs)coarse adjustment

Default settings are shown highlighted.

DAC_GAIN_COARSE[3:0]

I_O(fs)(mA)

Decimal

Binary

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

6.95

8.4

9.85

11.3

12.75

14.2

15.65

17.1

18.55

21.45

22.9

24.35

25.8

27.25

28.7

The settings applied to DAC_A_GAIN_FINE[5:0] (see register 17h in Table 46) and to

DAC_B_GAIN_FINE[5:0] (see register 19h in Table 48) define the fine variation of the

full-scale current (see Table 20).

Table 20. I_O(fs)fine adjustment

Default settings are shown highlighted.

DAC_GAIN_FINE[5:0]

ΔI_O(fs)(%)

Decimal

Two’s complement

−32

...

10 0000

...

−11

...

00 0000

...

+31

01 1111

+11

10.13 Digital offset adjustment

The DAC1627D1G25 provides digital offset correction (bits DAC_A_OFFSET[7:0] in

Table 40 and bits DAC_A_OFFSET[15:8] in Table 41 and register DAC_B_OFFSET[7:0]

in Table 42 and bits DAC_B_OFFSET[15:8] in Table 43) which can be used to adjust the

common-mode level at the output of each DAC. It adds an offset at the end of the digital

part, just before the DACs. Table 21 shows the range of variation of the digital offset.

DAC1627D1G25

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DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 21. Digital offset adjustment

DAC_A_OFFSET[15:0]

Offset applied

DAC_B_OFFSET[15:0]

(two’s complement)

1000 0000 0000 0000

1000 0000 0000 0001

...

−32768

−32767

...

1111 1111 1111 1111

0000 0000 0000 0000

0000 0000 0000 0001

...

−1

...

0111 1111 1111 1110

0111 1111 1111 1111

+32766

+32767

10.14 Analog output

The device has two output channels, producing two complementary current outputs,

which enable the reduction of even-order harmonics and noise. The pins are

IOUTAP/IOUTAN and IOUTBP/IOUTBN. They have to be connected via a load resistor R_L

to the 3.3 V analog power supply (V_DDA(3V3)).

Figure 21 shows the equivalent analog output circuit of one DAC. This circuit includes a

parallel combination of NMOS current sources and associated switches for each

segment.

3.3 V 3.3 V

IOUTAP/IOUTBP

IOUTAN/IOUTBN

GND

001aan835

Fig 21. Equivalent analog output circuit

The cascode source configuration increases the output impedance of the source, which

improves the dynamic performance of the DAC because there is less distortion.

Depending on the application, the various stages and the targeted performances, the

device can be used for an output level of up to 2 V (p-p).

DAC1627D1G25

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DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

10.15 Auxiliary DACs

The DAC1627D1G25 integrates two auxiliary DACs, which are used to compensate any

offset between the DACs and the next stage in the transmission path. Both auxiliary DACs

have a 10-bit resolution and are current sources (referenced to ground).

The full-scale output current for each DAC is the sum of the two complementary current

outputs:

• I_OAUXA(fs)= I_AUXAP+ I_AUXAN

• I_OAUXB(fs)= I_AUXBP+ I_AUXBN

The output current depends on the digital input data set by SPI registers

DAC_A_Aux_MSB (bits AUX_A[9:2]; see Table 50), DAC_A_Aux_LSB (bits AUX_A[1:0];

see Table 51), DAC_B_Aux_MSB (bits AUX_B[9:2]; see Table 52) and DAC_B_Aux_LSB

(bits AUX_B[1:0]; see Table 53).

DATAA

1023

⎛

⎝

⎞

⎠

-------------------

I_AUXAP= I_OAUXA(fs)

I_AUXAN= I_OAUXA(fs)

I_AUXBP= I_OAUXB(fs)

I_AUXBN= I_OAUXB(fs)

(7)

(8)

1023 – DATAA

⎛

⎝

⎞

⎠

-------------------------------------

1023

DATAB

1023

⎛

⎝

⎞

⎠

-------------------

(9)

1023 – DATAB

⎛

⎝

⎞

⎠

-------------------------------------

(10)

1023

Table 22 shows the output current as a function of the auxiliary DACs data DATAA and

DATAB above.

Table 22. Auxiliary DAC transfer function

DATAA; DATAB

AUX_A[9:2]/AUX_A[1:0]; I_AUXAP; I_AUXBP(mA)

AUX_B[9:0]/AUX_B[1:0]

I_AUXAN; I_AUXBN(mA)

(binary coding

00 0000 0000

...

2.2

...

512

...

10 0000 0000

...

1.1

...

1.1

...

1023

11 1111 1111

2.2

DAC1627D1G25

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DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

10.16 Output configuration

10.16.1 Basic output configuration

The use of a differentially coupled transformer output (see Figure 22) provides optimum

distortion performance. In addition, it helps to match the impedance and provides

electrical isolation.

3.3 V

DAC1627D

50 Ω

0 mA to 20 mA

IOUTAP/IOUTBP

2:1

50 Ω

0 mA to 20 mA

IOUTAN/IOUTBN

50 Ω

3.3 V

IOUTAP/IOUTAN

IOUTBP/IOUTBN

O(cm)

O(dif)

= 2.8 V

= 1 V

001aan836

Fig 22. 1 V (p-p) differential output with transformer

The DAC1627D1G25 can operate a differential output of up to 2 V (p-p). In this

configuration, it is recommended to connect the center tap of the transformer to a 62 Ω

resistor, which is connected to the 3.3 V analog power supply. This adjusts the DC

common-mode to around 2.7 V (see Figure 23).

3.3 V

DAC1627D

100 Ω

62 Ω

4:1

0 mA to 20 mA

IOUTAP/IOUTBP

50 Ω

IOUTAN/IOUTBN

100 Ω

3.3 V

IOUTAP/IOUTAN

IOUTBP/IOUTBN

O(cm)

O(dif)

= 2.7 V

= 2 V

001aan837

Fig 23. 2 V (p-p) differential output with transformer

DAC1627D1G25

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DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

10.16.2 IQ-modulator - BGX7100 interface

The DAC1627D1G25 can be easily connected to the BGX7100 NXP IQ-modulator. The

offset compensation for local oscillator can be cancelled using the digital offset control in

the device.

Figure 24 shows an example of a connection between the DAC1627D1G25 and the

BGX7100 interface.

3.3 V

DAC1627D

BGX7100

IQ-modulator

51.1 Ω

IOUTAP/IOUTBP

IOUTAN/IOUTBN

BBAP/BBBP

BBAN/BBBN

0 mA to 20 mA

AUXAP/AUXBP

AUXAN/AUXBN

001aan814

Fig 24. DAC1627D1G25 with BGX7100 IQ-modulator interface

10.16.3 IQ-modulator - DC interface

When the system operation requires to keep the DC component of the spectrum, the

DAC1627D1G25 can use a DC interface to connect an IQ-modulator. In this case, the

offset compensation for local oscillator can be cancelled using the digital offset control in

the device.

Figure 25 shows an example of a connection to an IQ modulator with a 1.7 V common

input level.

3.3 V

IQ-modulator (V

= 1.7 V)

I(cm)

DAC1627D

51.1 Ω

442 Ω

IOUTAP/IOUTBP

IOUTAN/IOUTBN

BBAP/BBBP

BBAN/BBBN

442 Ω

0 mA to 20 mA

768 Ω

IOUTAP/IOUTAN

BBAP/BBAN

BBBP/BBBN

IOUTBP/IOUTBN

O(cm)

O(dif)

= 2.67 V

= 1.98 V

= 1.7 V

I(cm)

I(dif)

= 1.26 V

001aan838

Fig 25. IQ-modulator: DC interface with a 1.7 V common input level

DAC1627D1G25

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DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Figure 26 shows an example of a connection to an IQ-modulator with a 3.3 V common

input level.

3.3 V

54.9 Ω

5 V

DAC1627D

IQ-modulator (V

= 3.3 V)

I(cm)

54.9 Ω

750 Ω

237 Ω

IOUTAP/IOUTBP

IOUTAN/IOUTBN

BBAP/BBBP

BBAN/BBBN

1.27 kΩ

IOUTAP/IOUTAN

IOUTBP/IOUTBN

O(cm)

O(dif)

BBAP/BBAN

BBBP/BBBN

= 2.75 V

= 1.97 V

= 3.3 V

I(cm)

I(dif)

= 1.5 V

001aan839

Fig 26. IQ-modulator: DC interface with a 3.3 V common input level

The auxiliary DACs can be used to control the offset within an accurate range or with

accurate steps.

Figure 27 shows an example of a connection to an IQ-modulator with a 1.7 V common

input level and auxiliary DACs.

3.3 V

DAC1627D

51.1 Ω

442 Ω

IOUTAP/IOUTBP

IOUTAN/IOUTBN

BBAP/BBBP

BBAN/BBBN

442 Ω

0 mA to 20 mA

698 Ω

AUXAP/AUXBP

AUXAN/AUXBN

1.1 mA (typical)

51.1 Ω

IOUTAP/IOUTAN

BBAP/BBAN

BBBP/BBBN

IOUTBP/IOUTBN

O(cm)

O(dif)

= 2.67 V

= 1.94 V

= 1.7 V

I(cm)

I(dif)

= 1.23 V

offset correction = up to 50 mV

001aan840

Fig 27. IQ-modulator: DC interface with a 1.7 V common input level and auxiliary DACs

DAC1627D1G25

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Objective data sheet

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34 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Figure 28 shows an example of a connection to an IQ-modulator with a 3.3 V common

input level and auxiliary DACs.

3.3 V

54.9 Ω

5 V

DAC1627D

54.9 Ω

237 Ω

750 Ω

IOUTAP/IOUTBP

IOUTAN/IOUTBN

BBAP/BBBP

BBAN/BBBN

237 Ω

634 Ω

442 Ω

634 Ω

AUXAP/AUXBP

AUXAN/AUXBN

442 Ω

IOUTAP/IOUTAN

IOUTBP/IOUTBN

O(cm)

O(dif)

BBAP/BBAN

BBBP/BBBN

= 2.75 V

= 1.96 V

= 3.3 V

I(cm)

I(dif)

= 1.5 V

offset correction = up to 36 mV

001aan841

Fig 28. IQ-modulator: DC interface with a 3.3 V common input level and auxiliary DACs

The constraints to adjust the interface are:

• The output compliance range of the DAC

• The output compliance range of the auxiliary DACs

• The input common-mode level of the IQ-modulator

• The range of offset correction

DAC1627D1G25

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Objective data sheet

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35 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

10.16.4 IQ-modulator - AC interface

When the IQ-modulator common-mode voltage is close to ground, the DAC1627D1G25

must be used AC-coupled and the auxiliary DACs are required for local oscillator

cancellation.

Figure 29 shows an example of a connection to an IQ-modulator with a 0.5 V common

input level and auxiliary DACs.

3.3 V

65.5 Ω

5 V

DAC1627D

IQ-modulator (V

= 0.5 V)

I(cm)

65.5 Ω

2 kΩ

10 nF

IOUTAP/IOUTBP

IOUTAN/IOUTBN

BBAP/BBBP

BBAN/BBBN

10 nF

0 mA to 20 mA

1.1 mA (typical)

174 Ω

34 Ω

174 Ω

34 Ω

AUXAP/AUXBP

AUXAN/AUXBN

IOUTAP/IOUTAN

BBAP/BBAN

BBBP/BBBN

IOUTBP/IOUTBN

= 2.65 V

= 1.96 V

= 0.5 V

O(cm)

O(dif)

I(cm)

I(dif)

= 1.96 V

offset correction = up to 70 mV

001aan842

Fig 29. IQ-modulator: AC interface with a 0.5 V common input level and auxiliary DACs

10.17 Design recommendations

10.17.1 Power and grounding

Use a separate power supply regulator for the generation of the 1.8 V analog power

(pins 65, 62, 55, 69, 72 and 58) and the 1.8 V digital power (pins 12, 19, 36, 26 and 43) to

ensure optimal performance.

Also, include individual LC decoupling for the following six sets of power pins:

• V_{DDA(1V8)_P1}(pin 62)

• V_{DDA(1V8)_P2}(pin 65)

• V_DDA(1V8)(pins 55, 69, 72 and 58)

• V_DDD(1V8)(core: pins 12, 26 and 43)

• V_DDD(1V8)(LVDS: pins 19 and 36)

• V_DDA(3V3)(pins 59 and 68)

At least two capacitors must be used for each power pin decoupling. These capacitors

must be located as close as possible to the DAC1627D1G25 power pins.

DAC1627D1G25

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Objective data sheet

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36 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

The die pad is used for both the power dissipation and electrical grounding. Insert several

vias (typically 7 × 7) to connect the internal ground plane to the top layer die area.

10.18 Configuration interface

10.18.1 Register description

The DAC1627D1G25 incorporates more than the 32 SPI registers allowed by the address

value A[4:0]. It uses three SPI register pages (page_00, page_01, and page_0A), each

containing 32 registers. The 32nd register of each page indicates which page is currently

addressed (00h, 01h or 0Ah).

Page 00h (see Table 23) is dedicated to the main control of the DAC1627D1G25:

• Mode selection

• NCO control

• Auxiliary DAC control

• Gain/phase/offset control

• Power-down control

Page 01h (see Table 55) is dedicated to:

• Multi-Device Synchronization (MDS)

• DAC analog core control (biasing current, Sleep mode)

Page 0Ah (seeTable 79) is dedicated to the LVDS input interface configuration.

DAC1627D1G25

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37 of 69

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

10.18.2 Page 0 register allocation map

Table 23 shows an overview of all registers on page 0 (00h in hexadecimal). See Section 10.18.3 for detailed descriptions of

the registers.

Table 23. Page_00 register allocation map

Address Register name

R/W

Bit definition

Default

Bin Hex Dec

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00h COMMON

R/W

3W_SPI SPI_RST

CODING

IC_PON GAP_PON 1000 87h 135

0111

01h TXCFG

NCO_ON NCO_LP INV_SIN

_SEL _SEL

MODULATION[2:0]

PLL_DIV[1:0]

INTERPOLATION[1:0] 0000 01h

0001

02h PLLCFG

PLL_BP PLL_BUF PLL_PLL

PLL_PHASE[1:0]

PLL_

1010 A1h 161

_PD

OSC_PD 0001

04h FREQNCO_B0

05h FREQNCO_B1

06h FREQNCO_B2

07h FREQNCO_B3

08h FREQNCO_B4

09h PH_CORR_CTL0

FREQ_NCO[7:0]

FREQ_NCO[15:8]

FREQ_NCO[23:16]

FREQ_NCO[31:24]

FREQ_NCO[39:32]

PHASE_COR[7:0]

0110 66h 102

0110

0110 66h 102

0110

0110 66h 102

0110

0010 66h 102

0110

0010 26h 38

0110

0000 00h

0000

10 0Ah PH_CORR_CTL1

11 0Bh DAC_A_DGAIN_LSB

12 0Ch DAC_A_DGAIN_MSB

13 0Dh DAC_B_DGAIN_LSB

14 0Eh DAC_B_DGAIN_MSB

15 0Fh DAC_OUT_CTRL

PH_COR

_ENA

PHASE_COR[12:8]

DAC_A_DGAIN[7:0]

0000 00h

0000

1101 50h 80

0100

DAC_A_DGAIN[11:8]

0000 0Bh 11

1011

DAC_B_DGAIN[7:0]

1101 50h 80

0100

DAC_B_DGAIN[11:8]

0000 0Bh 11

0010

A_DGAIN_E B_DGAIN_E MINUS CLIPPING 0000 00h

_3DB _ENA 0000

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 23. Page_00 register allocation map …continued

Address Register name

R/W

Bit definition

Bit 3

Default

Bin Hex Dec

Bit 7

Bit 6

Bit 5

Bit 4

Bit 2

Bit 1

Bit 0

16 10h DAC_CLIPPING

R/W

CLIPPING_LEVEL[7:0]

DAC_A_OFFSET[7:0]

DAC_A_OFFSET[15:8]

DAC_B_OFFSET[7:0]

DAC_B_OFFSET[15:8]

PH_NCO[7:0]

1111 FFh 255

1111

17 11h

DAC_A_OFFSET_LSB R/W

0000 00h

0000

18 12h DAC_A_OFFSET_MSB R/W

19 13h DAC_B_OFFSET_LSB R/W

20 14h DAC_B_OFFSET_MSB R/W

0000 00h

0000

0000 00h

0000

0000 00h

0000

21 15h PHINCO_LSB

R/W

0000 00h

0000

22 16h PHINCO_MSB

23 17h DAC_A_GAIN1

24 18h DAC_A_GAIN2

25 19h DAC_B_GAIN1

26 1Ah DAC_B_GAIN2

27 1Bh DAC_A_AUX_MSB

28 1Ch DAC_A_AUX_LSB

29 1Dh DAC_B_AUX_MSB

30 1Eh DAC_B_AUX_LSB

31 1Fh PAGE_ADDRESS

PH_NCO[15:8]

0000 00h

0000

DAC_A_GAIN_

COARSE[1:0]

DAC_A_GAIN_FINE[5:0]

0100 40h 64

0000

DAC_A_GAIN_

COARSE[3:2]

1000 80h 128

0000

DAC_B_GAIN_

COARSE[1:0]

DAC_B_GAIN_FINE[5:0]

0100 40h 192

0000

DAC_B_GAIN_

COARSE[3:2]

1000 80h 128

0000

AUX_A[9:2]

1000 80h 128

0000

AUX_A

AUX_A[1:0]

0000 00h

0000

_PD

AUX_B[9:2]

1000 80h 128

0000

AUX_B

_PD

AUX_B[1:0]

PAGE_ADD[2:0]

0000 00h

0000

0000 00h

0000

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

10.18.3 Page 0 bit definition detailed description

Table 24. Register COMMON (address 00h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

3W_SPI

R/W

serial interface bus type

4-wire SPI

3-wire SPI

SPI_RST

CODING

IC_PON

R/W

serial interface reset

no reset

performs a reset on all registers except address 00h

coding of input word

two complement’s coding

unsigned format

IC power control

all circuits (digital and analog, except SPI) are in

power-down

all circuits (digital and analog, except SPI) are

switched on

GAP_PON

R/W

internal band gap power control

band gap is power-down

internal band gap references are switched on

Table 25. Register TXCFG (address 01h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

NCO_ON

R/W

NCO

NCO disabled, the NCO phase is reset to 0

NCO enabled

NCO_LP_SEL

INV_SIN_SEL

R/W

NCO low power selection

low power NCO disabled

low power NCO enabled (frequency and phase

given by the five MSB of the registers 06h and 08h,

respectively)

R/W

inverse (sin x) / x function selection

disable

enable

4 to 2 MODULATION[2:0]

modulation

000

dual DAC: no modulation

positive upper single sideband upconversion

positive lower single sideband upconversion

negative upper single sideband upconversion

negative lower single sideband upconversion

not defined

001

010

011

100

others

DAC1627D1G25

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Objective data sheet

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40 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 25. Register TXCFG (address 01h) bit description …continued

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

1 to 0 INTERPOLATION[1:0]

R/W

interpolation

no interpolation

×2 interpolation

×4 interpolation

×8 interpolation

Table 26. Register PLLCFG (address 02h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

PLL_BP

R/W

PLL bypass

DAC clock generated by PLL

DAC clock provided via external pins CLKN and

CLKP (PLL bypass mode)

PLL_BUF_PD

PLL_PLL_PD

R/W

PLL test buffer control

Power-down mode

enabled

PLL and CKGEN control

Power-down mode

enable

4 to 3 PLL_DIV[1:0]

PLL divider factor

f_s= 2 × f_data

f_s= 4 × f_data

f_s= 8 × f

undefined

2 to 1 PLL_PHASE[1:0]

R/W

PLL phase shift

0 degrees phase shift of f_s

120 degrees phase shift of f_s

240 degrees phase shift of f_s

PLL oscillator output power-down

Power-down mode

enabled

PLL_OSC_PD

Table 27. Register FREQNCO_B0 (address 04h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 FREQ_NCO[7:0]

R/W

NCO frequency (two complement’s coding)

least significant 8 bits for the NCO frequency setting

DAC1627D1G25

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Objective data sheet

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DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 28. Register FREQNCO_B1 (address 05h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 FREQ_NCO[15:8]

R/W

NCO frequency

intermediate 8 bits for the NCO frequency setting

Table 29. Register FREQNCO_B2 (address 06h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 FREQ_NCO[23:16]

R/W

NCO frequency

intermediate 8 bits for the NCO frequency setting

Table 30. Register FREQNCO_B3 (address 07h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 FREQ_NCO[31:24]

R/W

NCO frequency

intermediate 8 bits for the NCO frequency setting

Table 31. Register FREQNCO_B4 (address 08h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 FREQ_NCO[39:32]

R/W

NCO frequency (MSB)

most significant 8 bits for the NCO frequency setting

Table 32. Register PH_CORR_CTL0 (address 09h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 PHASE_COR[7:0]]

R/W

DAC output phase correction factor (LSB)

least significant 8 bits for the DAC output phase

correction factor

Table 33. Register PH_CORR_CTL1 (address 0Ah)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

PH_COR_ENA

R/W

DAC output phase correction control

DAC output phase correction disabled

DAC output phase correction enabled

DAC output phase correction factor MSB

4 to 0 PHASE_COR[12:8]

R/W

00000

most significant 5 bits for the DAC output phase

correction factor

Table 34. Register DAC_A_DGAIN_LSB (address 0Bh)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 DAC_A_DGAIN[7:0]

R/W

DAC A digital gain control

least significant 8 bits for the DAC A digital gain

DAC1627D1G25

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Objective data sheet

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42 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 35. Register DAC_A_DGAIN_MSB (address 0Ch)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

3 to 0 DAC_A_DGAIN[11:8]

R/W

DAC A digital gain control

most significant 4 bits for the DAC A digital gain

Table 36. Register DAC_B_DGAIN_LSB (address 0Dh)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 DAC_B_DGAIN[7:0]

R/W

DAC B digital gain control

least significant 8 bits for the DAC B digital gain

Table 37. Register DAC_B_DGAIN_MSB (address 0Eh)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

3 to 0 DAC_B_DGAIN[11:8]

R/W

DAC B digital gain control

most significant 4 bits for the DAC B digital gain

Table 38. Register DAC_OUT_CTRL (address 0Fh)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

A_DGAIN_E

R/W

DAC A digital gain control

disable

enable

B_DGAIN_E

R/W

DAC B digital gain control

disable

enable

MINUS_3DB

CLIPPING_ENA

DAC attenuation control

unity gain

−3 dB gain

Digital DAC output clipping control

disable

enable

Table 39. Register DAC_CLIPPING (address 10h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 CLIPPING_LEVEL[7:0]

R/W

Digital DAC output clipping level value

Table 40. Register DAC_A_OFFSET_LSB (address 11h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 DAC_A_OFFSET[7:0]

R/W

DAC A digital offset value

least significant 8 bits for the DAC A digital offset

DAC1627D1G25

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Objective data sheet

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43 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 41. Register DAC_A_OFFSET_MSB (address 12h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 DAC_A_OFFSET[15:8]

R/W

DAC A digital offset value

most significant 8 bits for the DAC A digital offset

Table 42. Register DAC_B_OFFSET_LSB (address 13h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 DAC_B_OFFSET[7:0]

R/W

DAC B digital offset value

least significant 8 bits for the DAC B digital offset

Table 43. Register DAC_B_OFFSET_MSB (address 14h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 DAC_B_OFFSET[15:8]

R/W

DAC B digital offset value

most significant 8 bits for the DAC B digital offset

Table 44. Register PHINCO_LSB (address 15h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 PH_NCO[7:0]

R/W

NCO phase offset LSB

least significant 8 bits for the NCO phase setting

Table 45. Register PHINCO_MSB (address 16h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 PH_NCO[15:8]

R/W

NCO phase offset MSB

most significant 8 bits for the NCO phase setting

Table 46. Register DAC_A_GAIN1 (address 17h)

Default values are shown highlighted.

Bit

7 to 6 DAC_A_GAIN_COARSE[1:0] R/W

5 to 0 DAC_A_GAIN_FINE[5:0] R/W

Symbol

Access

Value

Description

DAC A analog coarse gain control (LSB)

DAC A analog fine gain control

Table 47. Register DAC_A_GAIN2 (address 18h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 6 DAC_A_GAIN_COARSE[3:2] R/W

DAC A analog gain coarse control (MSB)

Table 48. Register DAC_B_GAIN1 (address 19h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 6 DAC_B_GAIN_COARSE[1:0] R/W

DAC B analog coarse gain control (LSB)

DAC B analog fine gain control

5 to 0 DAC_B_GAIN_FINE[5:0]

R/W

DAC1627D1G25

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Objective data sheet

Rev. 1 — 29 April 2011

44 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 49. Register DAC_B_GAIN2 (address 1Ah)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 6 DAC_B_GAIN_COARSE[3:2] R/W

DAC B analog coarse gain control (MSB)

Table 50. DAC_A_Aux_MSB register (address 1Bh) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 AUX_A[9:2]

R/W

most significant 8 bits for auxiliary DAC A

Table 51. DAC_A_Aux_LSB register (address 1Ch) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

AUX_A_PD

R/W

auxiliary DAC A power

off

1 to 0 AUX_A[1:0]

R/W

least significant 2 bits for auxiliary DAC A

Table 52. DAC_B_Aux_MSB register (address 1Dh) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 AUX_B[9:2]

R/W

most significant 8 bits for auxiliary DAC B

Table 53. DAC_B_Aux_LSB register (address 1Eh) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

AUX_B_PD

R/W

auxiliary DAC B power

off

1 to 0 AUX_B[1:0]

R/W

least significant 2 bits for auxiliary DAC B

Table 54. SPI_PAGE register (address 1Fh) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

2 to 0 PAGE[2:0]

R/W

SPI page address

DAC1627D1G25

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Objective data sheet

Rev. 1 — 29 April 2011

45 of 69

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

10.18.4 Page 1 allocation map

Table 55 shows an overview of all registers on page 1 (01h in hexadecimal). See Section 10.18.5 for detailed descriptions of

the registers.

Table 55. Page 1 register allocation map

Address Register name

R/W

Bit definition

Default^[1]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bin

Hex

00h MDS_MAIN

R/W

MDS_EQCHECK[1:0]

MDS_

RUN

MDS_

NCO

MDS_

NCO_

PULSE

MDS_

SREF_

DIS

MDS_

MASTER

MDS_

ENA

0000 04h

0100

01h MDS_WIN_PERIOD_A

02h MDS_WIN_PERIOD_B

03h MDS_MISCCNTRL0

R/W

MDS_WIN_PERIOD_A[7:0]

MDS_WIN_PERIOD_B[7:0]

1000 80h

0000

0100 40h

0000

MDS_

EVAL_

ENA

MDS_

PRERUN_E

MDS_PULSEWIDTH[2:0]

0001 10h

0000

04h MDS_MAN_ADJUSTDLY R/W

MDS_

MAN

MDS_MAN_ADJUSTDLY[6:0]

0100 40h

0000

05h MDS_AUTO_CYCLES

06h MDS_MISCCNTRL1

07h MDS_OFFSET_DLY

08h MDS_ADJDELAY

09h MDS_STATUS0

R/W

MDS_AUTO_CYCLES[7:0]

1000 80h

0000

MDS_SR_ MDS_SR_

CKEN

MDS_

MDS_LOCK_DELAY[3:0]

MDS_OFFSET_DLY[4:0]

MDS_ADJDELAY[6:0]

0000 0Fh

1111

LOCKOUT SR_LOCK RELOCK

0000 00h

0000

0000 00h

0000

EARLY

LATE

EQUAL

MDS_EQ

EARLY_

ERROR

LATE_

ERROR

EQUAL_

FOUND

MDS_

uuuu uuh

ACTIVE uuuu

10 0Ah MDS_STATUS1

ADD_ERR MDS_EN_PHASE[1:0]

MDS_

PRERUN LOCKOUT

MDS_

LOCK

uuuu uuh

uuuu

14 0Eh DAC_CURRENT_AUX

15 0Fh DAC_CURRENT_0

16 10h DAC_CURRENT_1

R/W

DAC_AUX_BIAS[3:0]

0000 03h

0011

DAC_DIG_BIAS[3:0]

DAC_MST_BIAS[3:0]

0000 03h

0011

0000 03h

0011

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 55. Page 1 register allocation map …continued

Address Register name

R/W

Bit definition

Default^[1]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bin

Hex

17 11h DAC_CURRENT_2

18 12h DAC_CURRENT_3

19 13h DAC_CURRENT_4

20 14h DAC_CURRENT_5

21 15h DAC_CURRENT_6

22 16h DAC_PON_SLEEP

R/W

DAC_DRV_BIAS[3:0]

DAC_SLV_BIAS[3:0]

DAC_CK_BIAS[3:0]

DAC_CAS_BIAS[3:0]

DAC_BLD_BIAS[3:0]

0000 03h

0011

0000 03h

0011

0000 03h

0011

0000 03h

0011

0000 03h

0011

DAC_B_

PON

DAC_B_

SLEEP

DAC_B_

COM_PD

DAC_B_

BLEED_

DAC_A_

SLEEP

DAC_A_

COM_PD

DAC_A_ 1011 BBh

BLEED_ 1011

23 17h DAC_CLKDIG_DELAY

31 1Fh PAGE_ADDRESS

R/W

PLL_DIG_DELAY[2:0]

PAGE[2:0]

0000 02h

0010

0000 00h

0000

[1] u = undefined at power-up or after reset.

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

10.18.5 Page 1 bit definition detailed description

Table 56. MDS_MAIN register (address 00h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 6 MDS_EQCHECK[1:0]

R/W

lock mode

lock when (early = 1 and late = 1)

lock when (early = 1, late = 1 and equal = 1)

lock when equal = 1

force lock (equal-check = 1)

evaluation process restart control

no action

MDS_RUN

R/W

(0 ≥ 1) transition restarts evaluation_counter

NCO synchronization

no action

MDS_NCO

enable

MDS_NCO_PULSE

MDS_SREF_DIS

MDS_MASTER

MDS_ENA

NCO pulse

no action

manual control NCO tuning

internal pulse generation

normal mode

disable

MDS mode selection

slave mode

master mode

MDS function control

disable

enable

Table 57. MDS_WIN_PERIOD_A register (address 01h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 MDS_WIN_PERIOD_A[7:0]

R/W

determines MDS window LOW time

Table 58. MDS_WIN_PERIOD_B register (address 02h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 MDS_WIN_PERIOD_B[7:0]

R/W

determines MDS window HIGH time

Table 59. MDS_MISCCNTRL0 register (address 03h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

MDS evaluation

disable

MDS_EVAL_ENA

R/W

enable

DAC1627D1G25

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Objective data sheet

Rev. 1 — 29 April 2011

48 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 59. MDS_MISCCNTRL0 register (address 03h) bit description …continued

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

MDS_PRERUN_ENA

R/W

automatic MDS start-up

no mds_win/mds_ref generation in advance

mds_win/mds_ref run-in before mds_evaluation

width of MDS (in output clk-periods)

1 DAC clk-period

2 to 0 MDS_PULSEWIDTH[2:0]

R/W

000

001

2 DAC clk-periods

010 to 111

(mds_pulsewidth − 1) × 4 DAC clk-periods

Table 60. MDS_MAN_ADJUSTDLY register (address 04h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

MDS_MAN

R/W

adjustment delays mode

auto-control adjustment delays

manual control adjustment delays

adjustment delay value

6 to 0 MDS_MAN_ADJUSTDLY[6:0] R/W

if MDS_MAN = 0 then initial value adjustment delay

if MDS_MAN = 1 then controls adjustment delay

Table 61. MDS_AUTO_CYCLES register (address 05h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 MDS_AUTO_CYCLES[7:0]

R/W

number of evaluation cycles applied for MDS. If set to

255 then IC continuously generates/monitors the MDS

pulse

Table 62. MDS_MISCCNTRL1 register (address 06h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

MDS_SR_CKEN

R/W

lock mode

free-running MDS_SR_CKEN

MDS_SR_CKEN forced low

lockout detector soft reset

MDS_SR_LOCKOUT in use

MDS_SR_LOCKOUT forced low

lock detector soft reset

MDS_SR_LOCK in use

MDS_SR_LOCK forced low

relock mode

MDS_SR_LOCKOUT

MDS_SR_LOCK

MDS_RELOCK

R/W

no action

relock when lockout occurs

number of succeeding 'equal'-detections until lock

3 to 0 MDS_LOCK_DELAY[3:0]

DAC1627D1G25

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Objective data sheet

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DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 63. MDS_OFFSET_DLY register (address 07h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

4 to 0 MDS_OFFSET_DLY[6:0]

R/W

delay offset for dataflow (two’s complement [−16 to 15]

Table 64. MDS_ADJDELAY register (address 08h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

6 to 0 MDS_ADJDELAY[6:0]

actual value adjustment delay

Table 65. MDS_STATUS0 register (address 09h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

EARLY

early signal (sampled) from early-to-late detector

false

true

LATE

late signal (sampled) from early-to-late detector

false

true

EQUAL

equal signal (sampled) from early-to-late detector

false

true

MDS_LOCK

EARLY_ERROR

LATE_ERROR

EQUAL_FOUND

MDS_ACTIVE

result equal-check

false

true

adjustment delay maximum value stops the search

false

true

adjustment delay minimum value stops the search

false

true

evaluation logic has detected equal condition

false

true

evaluation logic active

false

true

Table 66. MDS_STATUS1 register (address 0Ah) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

ADD_ERR

adjustment delay error detection

delay offset cannot be applied in available range

DAC1627D1G25

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Objective data sheet

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DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 66. MDS_STATUS1 register (address 0Ah) bit description …continued

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

4 to 3 MDS_EN_PHASE[1:0]

MDS enable phase

enable phase = 0

enable phase = 1 (only for ×2)

enable phase = 2 (only for ×2 and ×4)

enable phase = 3 (only for ×2)

MDS_PRERUN

MDS_LOCKOUT

MDS_LOCK

MDS-PRERUN phase active flag

false

true

MDS_LOCKOUT detected flag

false

true

MDS_LOCK flag

false

true

Table 67. DAC_CURRENT_AUX register (address 0Eh) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

3 to 0 DAC_AUX_BIAS[3:0]

R/W

bias current control (see Table 75)

Table 68. DAC_CURRENT_0 register (address 0Fh) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

3 to 0 DAC_DIG_BIAS[3:0]

R/W

bias current control (see Table 75)

Table 69. DAC_CURRENT_1 register (address 10h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

3 to 0 DAC_MST_BIAS[3:0]

R/W

bias current control (see Table 75)

Table 70. DAC_CURRENT_2 register (address 11h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

3 to 0 DAC_DRV_BIAS[3:0]

R/W

bias current control (see Table 75)

Table 71. DAC_CURRENT_3 register (address 12h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

3 to 0 DAC_SLV_BIAS[3:0]

R/W

bias current control (see Table 75)

DAC1627D1G25

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Objective data sheet

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51 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 72. DAC_CURRENT_4 register (address 13h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

3 to 0 DAC_CK_BIAS[3:0]

R/W

bias current control (see Table 75)

Table 73. DAC_CURRENT_5 register (address 14h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

3 to 0 DAC_CAS_BIAS[3:0]

R/W

bias current control (see Table 75)

Table 74. DAC_CURRENT_6 register (address 15h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

3 to 0 DAC_BLD_BIAS[3:0]

R/W

bias current control (see Table 75)

Table 75. Bias current control table

BIAS[3:0]

0 0 0

Deviation from nominal current

−30 %

−20 %

−10 %

0 %

0 0 1

0 1 0

0 1 1

1 0 0

+10 %

+20 %

+30 %

+40 %

1 0 1

1 1 0

1 1 1

Table 76. DAC_PON_SLEEP register (address 16h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

DAC_B_PON

R/W

DAC B power control

power-down

power on

DAC_B_SLEEP

DAC_B_COM_PD

DAC_B_BLEED_PD

DAC_A_PON

DAC B mode selection

normal operation

Sleep mode

commutator B control

disable (power-down)

enable

DAC B bleed current control

disable (power-down)

enable

DAC A power control

power-down

power on

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Table 76. DAC_PON_SLEEP register (address 16h) bit description …continued

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

DAC_A_SLEEP

DAC B mode selection

normal operation

Sleep mode

DAC_A_COM_PD

commutator A control

disable (power-down)

enable

DAC_A_BLEED_PD

DAC A bleed current control

disable (power-down)

enable

Table 77. DAC_TEST_8 register (address 17h) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

2 to 0 PLL_DIG_DELAY[2:0]

R/W

digital clock delay offset of PLL/CKGEN_DIV8

Table 78. SPI_PAGE register (address 1Fh) bit description

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

2 to 0 PAGE[2:0]

R/W

SPI page address

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

10.18.6 Page A register allocation map

Table 79 shows an overview of all registers on page A (0Ah in hexadecimal). See Section 10.18.7 for detailed descriptions of

the registers.

Table 79. Page_0A register allocation map

Address Register name

R/W

Bit definition

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bin Hex Dec

00h MAIN_CNTRL

R/W

LD_PD

PD_CNTRL

CAL_

CNTRL

RST_

DCKL

RST_

LCKL

0000 03h

0011

01h MAN_LDCLKDEL R/W

02h DBG_LVDS R/W

04h RST_EXT_LDCLK R/W

05h RST_EXT_DCLK R/W

06h DCMSU_PREDIV R/W

LDCLK_DEL[3:0]

RESERVED

0000 00h

0000

SBER

0000 00h

0000

RST_EXT_LCLK_TIME[7:0]

RST_EXT_DCLK_TIME[7:0]

DCMSU_PREDIVIDER[7:0]

LD_POL[7:0]

0011 3Fh 63

1111

0010 20h 32

0000

0001 1Eh 30

1110

08h LD_POL_LSB

09h LD_POL_MSB

R/W

0000 00h

0000

LD_POL[15:8]

0000 00h

0000

10 0Ah LD_CNTRL

PARITYC DESCRAMBLE

SEL_EN[1:0]

WORD_SWAP

LDAB_

SWAP

IQ_

EDGE_ 0000 03h

FORMAT LDCLK 0011

11 0Bh MISC_CNTRL

12 0Ch I_DC_LVL_LSB

13 0Dh I_DC_LVL_MSB

14 0Eh Q_DC_LVL_LSB

15 0Fh Q_DC_LVL_MSB

27 1Bh TYPE_ID

SR_CDI

RESERVED

I_LEV_

Q_LEV_CNTRL[1:0]

CDI_MODE[1:0] 0000 00h

CNTRL[1:0]

0000

I_DC_LEVEL[7:0]

0000 00h

0000

I_DC_LEVEL[15:8]

Q_DC_LEVEL[7:0]

Q_DC_LEVEL[15:8]

0100 20h 32

0000

0000 00h

0000

0100 20h 32

0000

DAC

FRONTEND[1:0]

DUAL

DSP[1:0]

BIT_RES[1:0]

0011 3Ch 60

1010

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Table 79. Page_0A register allocation map …continued

Address Register name

R/W

Bit definition

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bin Hex Dec

28 1Ch DAC_VERSION

29 1Dh DIG_VERSION

30 1Eh LD_VERSION

DAC_VERSION_ID[7:0]

0000 01h

0001

DIG_VERSION_ID[7:0]

LVDS_VERSION_ID[7:0]

0000 01h

0001

0000 01h

0001

31 1Fh PAGE_ADDRESS R/W

PAGE_ADD[2:0]

0000 00h

0000

DAC1627D1G25

NXP Semiconductors

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10.18.7 Page A bit definition detailed description

Table 80. Register MAIN_CNTRL (address 00h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

LD_PD

R/W

LVDS interface power-down (control possible only

when PD_CNTRL = 1)

switched on

switched off

PD_CNTRL

CAL_CNTRL

RST_DCLK

RST_LCLK

R/W

power-down modes controlled by

DCMSU block

SPI registers

compensation delay controlled by

DCMSU block (automatic calibration)

SPI registers (manual control)

reset DCLK

disable

enable

reset LVDS clock

disable

enable

Table 81. Register MAN_LDCLKDEL (address 01h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

3 to 0 LDCLK_DEL[3:0]

R/W

LVDS clock compensation delay (control only if

CAL_CNTRL = 1)

4-bit compensation delay for LVDS clock

Table 82. Register DBG_LVDS (address 02h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

SBER

R/W

simple BER control

no action

simple BER active

reserved

2 to 0 RESERVED

R/W

000

Table 83. Register RST_EXT_LCLK (address 04h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 RST_EXT_LCLK_TIME[7:0] R/W

specify extension time reset, expressed in LVDS clock

period

8 bits for the extension time reset

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Table 84. Register RST_EXT_DCLK (address 05h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 RST_EXT_DCLK_TIME[7:0] R/W

specify extension time reset, expressed in

DCLK period

8 bits for the extension time reset

Table 85. Register DCSMU_PREDIV (address 06h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 DCMSU_PREDIVIDER[7:0]

R/W

predivider value for the DCMSU, expressed in LVDS

clock period

8 bits for the predivider value

Table 86. Register LD_POL_LSB (address 08h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 LD_POL[7:0]

R/W

toggles polarity of corresponding bit pair within LD[7:0]

most significant 6 bits for the polarity toggle

Table 87. Register LD_POL_MSB (address 09h)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 LD_POL[15:8]

R/W

toggles polarity of corresponding bit pair within LD[7:0]

most significant 6 bits for the polarity toggle

Table 88. Register LD_CNTRL (address 0Ah)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

PARITYC

R/W

parity check

disable

enable

DESCRAMBLE

R/W

Descramble control

disable descrambling

enable descrambling

LDVS data enable

5 to 4 SEL_EN[1:0]

LDVS data enable = align signal from channel A

LDVS data enable = align signal from channel B

LDVS data enable = 0

LDVS data enable = 1

reverse order for LVDS path

normal operation

WORD_SWAP

R/W

MSB to LSB order reversed

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Table 88. Register LD_CNTRL (address 0Ah) …continued

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

LDAB_SWAP

R/W

swaps LVDS A and LVDS B paths

normal operation

LVDS A and LVDS B paths are swapped

specify IQ supplied format

folded

IQ_FORMAT

R/W

interleaved

EDGE_LDCLK

specify sampling edge for LVDS data path

falling edge of LDCLK

rising edge of LDCLK

Table 89. Register MISC_CNTRL (address 0Bh)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

SR_CDI

R/W

CDI block software reset control

no action

perform a software reset on CDI

reserved

RESERVED

R/W

5 to 4 I_LEV_CNTRL[1:0]

3 to 2 Q_LEV_CNTRL[1:0]

1 to 0 CDI_MODE[1:0]

specifies output from CDI for I path

normal operation (CDI data output sent to digital

signal processing input)

if LDVS data enable = 1, then normal operation; if

LDVS data enable = 0, then digital signal processing

input = I_DC_LEVEL register value

digital signal processing input = I_DC_LEVEL

specifies output from CDI for Q path

R/W

normal operation (CDI data output sent to digital

signal processing input)

if LDVS data enable = 1, then normal operation; if

LDVS data enable = 0, then digital signal processing

input = Q_DC_LEVEL register value

digital signal processing input = Q_DC_LEVEL

specifies CDI mode

R/W

cdi_mode 0 (×2 mode)

cdi_mode 1 (×4 mode)

cdi_mode 2 (×8 mode)

not used

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Table 90. Register I_DC_LVL_LSB(address 0Ch)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 I_DC_LEVEL[7:0]

R/W

I_DC_LEVEL

least significant 8 bits for I_DC_LEVEL

Table 91. Register I_DC_LVL_MSB(address 0Dh)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 I_DC_LEVEL[15:8]

R/W

I_DC_LEVEL

most significant 8 bits for I_DC_LEVEL

Table 92. Register Q_DC_LVL_LSB(address 0Eh)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 Q_DC_LEVEL[7:0]

R/W

Q_DC_LEVEL

least significant 8 bits for Q_DC_LEVEL

Table 93. Register Q_DC_LVL_MSB(address 0Fh)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 Q_DC_LEVEL[15:8]

R/W

Q_DC_LEVEL

most significant 8 bits for Q_DC_LEVEL

Table 94. Register TYPE_ID (address 1Bh)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

DAC

calibration

uncalibrated device

calibrated device

LVDS input interface

dual DAC

6 to 5 FRONTEND

DUAL

3 to 2 DSP

internal digital signal processing

interpolation filter + SSBM

SSBM

interpolation filter

none

1 to 0 BIT_RES

DAC bit resolution

16 bits

14 bits

12 bits

10 bits

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Table 95. Register DAC_VERSION (address 1Ch)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 DAC_VERSION_ID[7:0]

R/W

DAC version number

8 bits for the DAC version number

Table 96. Register DIG_VERSION (address 1Dh)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 DIG_VERSION_ID[7:0]

R/W

digital version number

8 bits for the digital version number

Table 97. Register DIG_VERSION (address 1Eh)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0 LVDS_VERSION_ID[7:0]

R/W

LVDS receiver version number

8 bits for the LVDS receiver version number

Table 98. Register PAGE_ADD (address 1Fh)

Default values are shown highlighted.

Bit

Symbol

Access

Value

Description

2 to 0 PAGE_ADD[2:0]

R/W

Page address

current page address

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11. Package outline

HVQFN72: plastic thermal enhanced very thin quad flat package; no leads;

72 terminals; body 10 x 10 x 0.85 mm

SOT813-3

terminal 1

index area

detail X

1/2 e

terminal 1

index area

10 mm

scale

Dimensions

Unit

max 1.00 0.05 0.30

(1)

10.1 7.2 10.1 7.2

0.5

mm nom 0.85 0.02 0.21 0.2 10.0 7.1 10.0 7.1 0.5 8.5 8.5 0.4 0.1 0.05 0.05 0.1

min 0.80 0.00 0.18 9.9 7.0 9.9 7.0 0.3

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

sot813-3_po

References

Outline

version

European

projection

Issue date

IEC

- - -

JEDEC

- - -

JEITA

- - -

10-03-23

10-04-02

SOT813-3

Fig 30. Package outline SOT813-3 (HVQFN72)

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12. Abbreviations

Table 99. Abbreviations

Acronym

Description

BandWidth

BWA

CDI

Broadband Wireless Access

Clock Domain Interface

CDMA

CML

Code Division Multiple Access

Current Mode Logic

CMOS

DAC

Complementary Metal Oxide Semiconductor

Digital-to-Analog Converter

Enhanced Data rates for GSM Evolution

Finite Impulse Response

EDGE

FIR

GSM

Global System for Mobile communications

Intermediate Frequency

IMD3

LMDS

Third Order InterModulation

Local Multipoint Distribution Service

Local Oscillator

LVDS

NCO

NMOS

PLL

Low-Voltage Differential Signaling

Numerically Controlled Oscillator

Negative Metal-Oxide Semiconductor

Phase-Locked Loop

SFDR

SPI

Spurious-Free Dynamic Range

Serial Peripheral Interface

WCDMA

WLL

Wide band Code Division Multiple Access

Wireless Local Loop

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13. Glossary

13.1 Static parameters

INL — IThe deviation of the transfer function from a best fit straight line (linear regression

computation).

DNL — The difference between the ideal and the measured output value between

successive DAC codes.

13.2 Dynamic parameters

Spurious-Free Dynamic Range (SFDR) — The ratio between the RMS value of the

reconstructed output sine wave and the RMS value of the largest spurious observed

(harmonic and non-harmonic, excluding DC component) in the frequency domain.

Decibels relative to full scale (dBFS) — Unit used in a digital system in order to

measure the amplitude level in decibel relative to the maximum peak value.

InterModulation Distortion (IMD) — From a dual-tone digital input sine wave (these two

frequencies being close together), the intermodulation distortion products IMD2 and IMD3

(second order and third order components) are defined below.

IMD2 — The ratio between the RMS value of either tone and the RMS value of the worst

second order inter modulation product.

IMD3 — The ratio between the RMS value of either tone and the RMS value of the worst

third order inter modulation product.

Total Harmonic Distortion (THD) — The ratio between the RMS value of the harmonics

of the output frequency and the RMS value of the output sine wave. Usually, the

calculation of THD is done on the first 5 harmonics.

Signal-to-Noise Ratio (SNR) — The ratio between the RMS value of the reconstructed

output sine wave and the RMS value of the noise excluding the harmonics and the DC

component.

Restricted BandWidth Spurious-Free Dynamic Range (SFDR_RBW) — the ratio

between the RMS value of the reconstructed output sine wave and the RMS value of the

noise, including the harmonics, in a given bandwidth centered around f_offset

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14. Revision history

Table 100. Revision history

Document ID

Release date

20110429

Data sheet status

Change notice

Supersedes

DAC1627D1G25 v.1

Objective data sheet

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15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

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Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

DAC1627D1G25

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 29 April 2011

66 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

17. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4

Table 3. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 4. Thermal characteristics . . . . . . . . . . . . . . . . . . .7

Table 5. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 6. Read or Write mode access description . . . . .13

Table 7. Number of bytes to be transferred . . . . . . . . . .13

Table 8. SPI timing characteristics . . . . . . . . . . . . . . . .14

Table 9. Input LVDS bus swapping . . . . . . . . . . . . . . . .16

Table 10. Folded and interleaved format mapping. . . . . .17

Table 11. Compensation delay values for manual

(address 13h) . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 43. Register DAC_B_OFFSET_MSB

(address 14h) . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 44. Register PHINCO_LSB (address 15h) . . . . . . 44

Table 45. Register PHINCO_MSB (address 16h) . . . . . . 44

Table 46. Register DAC_A_GAIN1 (address 17h) . . . . . 44

Table 47. Register DAC_A_GAIN2 (address 18h) . . . . . 44

Table 48. Register DAC_B_GAIN1 (address 19h) . . . . . 44

Table 49. Register DAC_B_GAIN2 (address 1Ah) . . . . . 45

Table 50. DAC_A_Aux_MSB register (address 1Bh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 51. DAC_A_Aux_LSB register (address 1Ch)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 52. DAC_B_Aux_MSB register (address 1Dh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 53. DAC_B_Aux_LSB register (address 1Eh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 54. SPI_PAGE register (address 1Fh)

tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 12. CDI mode 0: operating modes examples . . . .22

Table 13. CDI mode 1: operating modes examples . . . .22

Table 14. CDI mode 2: operating modes examples . . . .23

Table 15: Interpolation filter coefficients . . . . . . . . . . . . .24

Table 16. Complex modulator operation mode . . . . . . . .26

Table 17. Inversion filter coefficients . . . . . . . . . . . . . . . .27

Table 18. DAC transfer function . . . . . . . . . . . . . . . . . . .28

Table 19. I_O(fs)coarse adjustment . . . . . . . . . . . . . . . . . .29

Table 20. I_O(fs)fine adjustment . . . . . . . . . . . . . . . . . . . .29

Table 21. Digital offset adjustment . . . . . . . . . . . . . . . . .30

Table 22. Auxiliary DAC transfer function . . . . . . . . . . . .31

Table 23. Page_00 register allocation map . . . . . . . . . . .38

Table 24. Register COMMON (address 00h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 55. Page 1 register allocation map . . . . . . . . . . . . 46

Table 56. MDS_MAIN register (address 00h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 57. MDS_WIN_PERIOD_A register (address 01h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 58. MDS_WIN_PERIOD_B register (address 02h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 59. MDS_MISCCNTRL0 register (address 03h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 60. MDS_MAN_ADJUSTDLY register (address 04h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 61. MDS_AUTO_CYCLES register (address 05h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 62. MDS_MISCCNTRL1 register (address 06h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 63. MDS_OFFSET_DLY register (address 07h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 64. MDS_ADJDELAY register (address 08h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 65. MDS_STATUS0 register (address 09h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 66. MDS_STATUS1 register (address 0Ah)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 67. DAC_CURRENT_AUX register (address 0Eh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 68. DAC_CURRENT_0 register (address 0Fh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 69. DAC_CURRENT_1 register (address 10h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 51

bit description . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 25. Register TXCFG (address 01h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 26. Register PLLCFG (address 02h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 27. Register FREQNCO_B0 (address 04h) . . . . . .41

Table 28. Register FREQNCO_B1 (address 05h) . . . . . .42

Table 29. Register FREQNCO_B2 (address 06h) . . . . . .42

Table 30. Register FREQNCO_B3 (address 07h) . . . . . .42

Table 31. Register FREQNCO_B4 (address 08h) . . . . . .42

Table 32. Register PH_CORR_CTL0 (address 09h) . . . .42

Table 33. Register PH_CORR_CTL1 (address 0Ah) . . .42

Table 34. Register DAC_A_DGAIN_LSB (address 0Bh) .42

Table 35. Register DAC_A_DGAIN_MSB (address 0Ch) 43

Table 36. Register DAC_B_DGAIN_LSB (address 0Dh) 43

Table 37. Register DAC_B_DGAIN_MSB (address 0Eh) 43

Table 38. Register DAC_OUT_CTRL (address 0Fh) . . .43

Table 39. Register DAC_CLIPPING (address 10h) . . . . .43

Table 40. Register DAC_A_OFFSET_LSB

(address 11h) . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 41. Register DAC_A_OFFSET_MSB

(address 12h) . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 42. Register DAC_B_OFFSET_LSB

continued >>

DAC1627D1G25

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 29 April 2011

67 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 70. DAC_CURRENT_2 register (address 11h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 71. DAC_CURRENT_3 register (address 12h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 72. DAC_CURRENT_4 register (address 13h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 73. DAC_CURRENT_5 register (address 14h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 74. DAC_CURRENT_6 register (address 15h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 75. Bias current control table . . . . . . . . . . . . . . . . .52

Table 76. DAC_PON_SLEEP register (address 16h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 77. DAC_TEST_8 register (address 17h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 78. SPI_PAGE register (address 1Fh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 79. Page_0A register allocation map . . . . . . . . . . .54

Table 80. Register MAIN_CNTRL (address 00h) . . . . . .56

Table 81. Register MAN_LDCLKDEL (address 01h) . . . .56

Table 82. Register DBG_LVDS (address 02h) . . . . . . . .56

Table 83. Register RST_EXT_LCLK (address 04h) . . . .56

Table 84. Register RST_EXT_DCLK (address 05h) . . . .57

Table 85. Register DCSMU_PREDIV (address 06h) . . . .57

Table 86. Register LD_POL_LSB (address 08h) . . . . . . .57

Table 87. Register LD_POL_MSB (address 09h) . . . . . .57

Table 88. Register LD_CNTRL (address 0Ah) . . . . . . . .57

Table 89. Register MISC_CNTRL (address 0Bh) . . . . . .58

Table 90. Register I_DC_LVL_LSB(address 0Ch) . . . . .59

Table 91. Register I_DC_LVL_MSB(address 0Dh) . . . . .59

Table 92. Register Q_DC_LVL_LSB(address 0Eh) . . . . .59

Table 93. Register Q_DC_LVL_MSB(address 0Fh) . . . .59

Table 94. Register TYPE_ID (address 1Bh) . . . . . . . . . .59

Table 95. Register DAC_VERSION (address 1Ch) . . . . .60

Table 96. Register DIG_VERSION (address 1Dh) . . . . .60

Table 97. Register DIG_VERSION (address 1Eh) . . . . .60

Table 98. Register PAGE_ADD (address 1Fh) . . . . . . . .60

Table 99. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 100. Revision history . . . . . . . . . . . . . . . . . . . . . . . .64

DAC1627D1G25

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 29 April 2011

68 of 69

DAC1627D1G25

NXP Semiconductors

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

18. Contents

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

10.16.2 IQ-modulator - BGX7100 interface . . . . . . . . 33

10.16.3 IQ-modulator - DC interface. . . . . . . . . . . . . . 33

10.16.4 IQ-modulator - AC interface. . . . . . . . . . . . . . 36

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

10.17

10.17.1 Power and grounding. . . . . . . . . . . . . . . . . . . 36

10.18 Configuration interface. . . . . . . . . . . . . . . . . . 37

Design recommendations . . . . . . . . . . . . . . . 36

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

10.18.1 Register description . . . . . . . . . . . . . . . . . . . . 37

10.18.2 Page 0 register allocation map . . . . . . . . . . . 38

10.18.3 Page 0 bit definition detailed description . . . . 40

10.18.4 Page 1 allocation map . . . . . . . . . . . . . . . . . . 46

10.18.5 Page 1 bit definition detailed description . . . . 48

10.18.6 Page A register allocation map . . . . . . . . . . . 54

10.18.7 Page A bit definition detailed description. . . . 56

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Thermal characteristics . . . . . . . . . . . . . . . . . . 7

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 8

10.1

10.2

10.2.1

10.2.2

10.3

Application information. . . . . . . . . . . . . . . . . . 12

General description . . . . . . . . . . . . . . . . . . . . 12

Serial Peripheral Interface (SPI). . . . . . . . . . . 13

Protocol description . . . . . . . . . . . . . . . . . . . . 13

SPI timing description. . . . . . . . . . . . . . . . . . . 14

Power-on sequence . . . . . . . . . . . . . . . . . . . . 14

LVDS Data Input Format (DIF) block . . . . . . . 15

Input port polarity . . . . . . . . . . . . . . . . . . . . . . 15

Input port mapping . . . . . . . . . . . . . . . . . . . . . 16

Input port swapping . . . . . . . . . . . . . . . . . . . . 16

Input port formatting . . . . . . . . . . . . . . . . . . . . 17

Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

LVDS DDR clock. . . . . . . . . . . . . . . . . . . . . . . 18

DAC core clock. . . . . . . . . . . . . . . . . . . . . . . . 18

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Operating modes . . . . . . . . . . . . . . . . . . . . . . 21

CDI mode 0 (x2 interpolation). . . . . . . . . . . . . 22

CDI mode 1 (x4 interpolation). . . . . . . . . . . . . 22

CDI mode 2 (x8 interpolation). . . . . . . . . . . . . 23

FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Single SideBand Modulator (SSBM). . . . . . . . 25

NCO in 40 bits . . . . . . . . . . . . . . . . . . . . . . . . 25

NCO low power . . . . . . . . . . . . . . . . . . . . . . . 26

Complex modulator . . . . . . . . . . . . . . . . . . . . 26

Minus 3dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Inverse sinx / x . . . . . . . . . . . . . . . . . . . . . . . . 27

DAC transfer function . . . . . . . . . . . . . . . . . . . 27

Full-scale current . . . . . . . . . . . . . . . . . . . . . . 28

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 61

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 62

13.1

13.2

Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Static parameters. . . . . . . . . . . . . . . . . . . . . . 63

Dynamic parameters . . . . . . . . . . . . . . . . . . . 63

10.4

Revision history . . . . . . . . . . . . . . . . . . . . . . . 64

10.4.1

10.4.2

10.4.3

10.4.4

10.5

10.5.1

10.5.2

10.6

Legal information . . . . . . . . . . . . . . . . . . . . . . 65

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 65

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 66

15.1

15.2

15.3

15.4

Contact information . . . . . . . . . . . . . . . . . . . . 66

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.7

10.7.1

10.7.2

10.7.3

10.8

10.9

10.9.1

10.9.2

10.9.3

10.9.4

10.10

10.11

10.12

10.12.1 Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10.12.2 Full-scale current adjustment . . . . . . . . . . . . . 28

10.13

10.14

10.15

10.16

Digital offset adjustment . . . . . . . . . . . . . . . . . 29

Analog output . . . . . . . . . . . . . . . . . . . . . . . . . 30

Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 31

Output configuration . . . . . . . . . . . . . . . . . . . . 32

10.16.1 Basic output configuration . . . . . . . . . . . . . . . 32

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 April 2011

Document identifier: DAC1627D1G25

DAC1627D1G25 [NXP]

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