DSP56321TFC240 [NXP]
IC,DSP,24-BIT,CMOS,BGA,196PIN,PLASTIC;型号: | DSP56321TFC240 |
厂家: | NXP |
描述: | IC,DSP,24-BIT,CMOS,BGA,196PIN,PLASTIC 时钟 外围集成电路 |
文件: | 总88页 (文件大小:1899K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Technical Data
Advance Information
DSP56321T/D
Rev. 2, 10/2002
24-Bit Digital Signal
Processor
3
16
6
6
Memory Expansion Area
Program
RAM
Triple
Timer
32 K × 24 bits
SCI
HI08
ESSI
EFCOP
or
X Data
RAM
Y Data
RAM
31 K × 24 bits
and
Instruction
80 K × 24 bits 80 K × 24 bits
Cache
1024 × 24 bits
Peripheral
The DSP56321T is a
member of the
Expansion Area
YAB
Address
DSP56300 Digital
Signal Processor (DSP)
family intended for
applications requiring a
large amount of
on-device memory. The
on-board EFCOP can
accelerate general
filtering applications,
such as
External
Address
Bus
XAB
PAB
DAB
18
Generation
Unit
Address
Switch
Six Channel
DMA Unit
External
Bus
24-Bit
DSP56300
Core
13
Interface
and
Bootstrap
ROM
Control
I - Cache
Control
DDB
YDB
XDB
PDB
GDB
External
Data
Internal
Data
24
Bus
Bus
Switch
Data
Switch
Power
echo-cancellation,
correlation, and
general-purpose
Management
Data ALU
5
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Clock
Generator
+
→
24 × 24 56 56-bit MAC
JTAG
PLL
Two 56-bit Accumulators
56-bit Barrel Shifter
OnCE™
convolution-based
algorithms. By operating
in parallel with the core,
the EFCOP provides
overall enhanced
DE
EXTAL
XTAL
RESET
PINIT/NMI
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
PCAP
Figure 1. DSP56321T Block Diagram
performance and signal
quality with no impact
on channel throughput
or total channel support.
The Motorola DSP56321T supports networking,
security encryption, and home entertainment
applications using a high- performance,
single-clock-cycle-per- instruction engine
(DSP56000 code-compatible), a barrel shifter,
24-bit addressing, an instruction cache, and a
six-channel direct memory access (DMA)
controller (see Figure 1).
The DSP5321T offers 220/240 MMACS
performance, attaining 440/480 MMACS when the
EFCOP is in use, It operates with an internal
220/240 MHz clock, using a 1.6 volt core and
independent 3.3 volt input/output (I/O) power.
This device is pin- compatible with the Motorola
DSP56303, DSP56L307, DSP56309, and
DSP56311.
Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.
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Table of Contents
DSP56321T Features.......................................................................................................................................... iii
Target Applications ..............................................................................................................................................v
Product Documentation........................................................................................................................................v
Chapter 1
Signal/ Connection Descriptions
1.1 Signal Groupings.............................................................................................................................................. 1-1
1.2 Power................................................................................................................................................................ 1-3
1.3 Ground.............................................................................................................................................................. 1-3
1.4 Clock ................................................................................................................................................................ 1-3
1.5 External Memory Expansion Port (Port A)...................................................................................................... 1-4
1.6 Interrupt and Mode Control ............................................................................................................................. 1-7
1.7 Host Interface (HI08)....................................................................................................................................... 1-8
1.8 Enhanced Synchronous Serial Interface 0 (ESSI0)........................................................................................ 1-12
1.9 Enhanced Synchronous Serial Interface 1 (ESSI1)........................................................................................ 1-13
1.10 Serial Communication Interface (SCI)........................................................................................................... 1-15
1.11 Timers............................................................................................................................................................. 1-16
1.12 JTAG and OnCE Interface ............................................................................................................................. 1-17
Chapter 2
Specifications
2.1 Introduction...................................................................................................................................................... 2-1
2.2 Maximum Ratings............................................................................................................................................ 2-1
2.3 Thermal Characteristics ................................................................................................................................... 2-2
2.4 DC Electrical Characteristics........................................................................................................................... 2-3
2.5 AC Electrical Characteristics........................................................................................................................... 2-4
Chapter 3
Chapter 4
Packaging
3.1 Pin-Out and Package Information.................................................................................................................... 3-1
3.2 FC-PBGA Package Description....................................................................................................................... 3-2
3.3 FC-PBGA Package Mechanical Drawing...................................................................................................... 3-10
Design Considerations
4.1 Thermal Design Considerations....................................................................................................................... 4-1
4.2 Electrical Design Considerations..................................................................................................................... 4-2
4.3 Power Consumption Considerations................................................................................................................ 4-3
4.4 Input (EXTAL) Jitter Requirements................................................................................................................. 4-4
Appendix A
Index
Power Consumption Benchmark
Data Sheet Conventions
OVERBAR
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when
low.)
“asserted”
“deasserted”
Examples:
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Signal/Symbol
Logic State
True
Signal State
Asserted
Voltage
V /V
PIN
PIN
PIN
PIN
IL OL
False
Deasserted
Asserted
V
V
/V
IH OH
True
/V
IH OH
False
Deasserted
V /V
IL OL
Note: Values for V , V , V , and V are defined by individual product specifications.
IL
OL
IH
OH
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DSP56321T Features
High-Performance DSP56300 Core
• 220/240 million multiply-accumulates per second (MMACS) (440/480 MMACS using the EFCOP in
filtering applications) with a 220/240 MHz clock at 1.6 V core and 3.3 V I/O and a junction
temperature range of 0–85°C
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel
Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream
generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under
software control
• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes
optimized for DSP applications (including immediate offsets), on-chip instruction cache controller,
on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses;
one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer
interrupts; and triggering from interrupt lines and all peripherals
• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and
output clock with skew elimination
• Hardware debugging support including On-Chip Emulation (OnCE ) module, Joint Test Action
Group (JTAG) Test Access Port (TAP)
Enhanced Filtering Coprocessor (EFCOP)
• On-chip 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
• Operation at the same frequency as the core (up to 220/240 MHz)
• Support for a variety of filter modes, some of which are optimized for cellular base station applications:
— Real Finite Impulse Response (FIR) with real taps
— Complex FIR with complex taps
— Complex FIR generating pure real or pure imaginary outputs alternately
— A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
— Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
— Direct form 2 (DFII) IIR filter
— Four scaling factors (1, 4, 8, 16) for IIR output
— Adaptive FIR filter with true least mean square (LMS) coefficient updates
— Adaptive FIR filter with delayed LMS coefficient updates
On-Chip Peripherals
• Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses (for example,
ISA) and provides glueless connection to a number of industry-standard microcomputers,
microprocessors, and DSPs
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters
(allows six-channel home theater)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
enabled
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On-Chip Memories
• 192 × 24-bit bootstrap ROM
• 192 K RAM total
• Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:
Program RAM Instruction X Data RAM Y Data RAM Instruction
MSW2 MSW1 MSW0
Size
Cache Size
Size*
Size*
Cache
32 K × 24-bit
31 K × 24-bit
40 K × 24-bit
39 K × 24-bit
48 K × 24-bit
47 K × 24-bit
64 K × 24-bit
63 K × 24-bit
72 K × 24-bit
71 K × 24-bit
80 K × 24-bit
79 K × 24-bit
96 K × 24-bit
95 K × 24-bit
112 K × 24-bit
111 K × 24-bit
0
80 K × 24-bit
80 K × 24-bit
76 K × 24-bit
76 K × 24-bit
72 K × 24-bit
72 K × 24-bit
64 K × 24-bit
64 K × 24-bit
60 K × 24-bit
60 K × 24-bit
56 K × 24-bit
56 K × 24-bit
48 K × 24-bit
48 K × 24-bit
40 K × 24-bit
40 K × 24-bit
80 K × 24-bit
80 K × 24-bit
76 K × 24-bit
76 K × 24-bit
72 K × 24-bit
72 K × 24-bit
64 K × 24-bit
64 K × 24-bit
60 K × 24-bit
60 K × 24-bit
56 K × 24-bit
56 K × 24-bit
48 K × 24-bit
48 K × 24-bit
40 K × 24-bit
40 K × 24-bit
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1024 × 24-bit
0
1024 × 24-bit
0
1024 × 24-bit
0
1024 × 24-bit
0
1024 × 24-bit
0
1024 × 24-bit
0
1024 × 24-bit
0
1024 × 24-bit
*Includes 12 K × 24-bit shared memory (that is, 24 K total memory shared by the core and the EFCOP)
Off-Chip Memory Expansion
• Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external
address lines
• Program memory expansion to one 256 K × 24-bit words memory space using the standard external
address lines
• External memory expansion port
• Chip Select Logic for glueless interface to static random access memory (SRAMs)
Reduced Power Dissipation
• Very low-power CMOS design
• Wait and Stop low-power standby modes
• Fully static design specified to operate down to 0 Hz (dc)
• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and
mode-dependent)
Packaging
The DSP56321T is available in a 196-pin flip-chip plastic ball grid array (FC-PBGA) package.
iv
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Target Applications
DSP56321/DSP56321T applications require high performance, low power, small packaging, and a large
amount of on-chip memory. The EFCOP can accelerate general filtering applications. Examples include:
• Wireless and wireline infrastructure applications
• Multi-channel wireless local loop systems
• Security encryption systems
• Home entertainment systems
• DSP resource boards
• High-speed modem banks
• IP telephony
Product Documentation
The three documents listed in the following table are required for a complete description of the
DSP56321T and are necessary to design properly with the part. Documentation is available from the
following sources. (See the back cover for details.)
• A local Motorola distributor
• A Motorola semiconductor sales office
• A Motorola Literature Distribution Center
• The World Wide Web (WWW)
Table 1. DSP56321T Documentation
Name
Description
Order Number
DSP56300 Family
Manual
Detailed description of the DSP56300 family processor core and
instruction set
DSP56300FM/AD
DSP56321
Reference Manual
Detailed functional description of the DSP56321 memory
configuration, operation, and register programming
DSP56321RM/D
Note:
The DSP56321T is functionally identical to the
DSP56321 with the exception of operating temperature
range.
DSP56321T
Technical Data
DSP56321T features list and physical, electrical, timing, and
package specifications
DSP56321T/D
Note: To ensure that you have the latest documentation for designing your application, click on the
Subscribe for Updates option under Page Contents on the DSP56321 Product Page. Once
registered, you will receive periodic notification via email when the product documentation is
updated.
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Chapter 1
Signal/
Connection
Descriptions
1.1 Signal Groupings
The DSP56321T input and output signals are organized into functional groups as shown in Table 1-1.
Figure 1-1 diagrams the DSP56321T signals by functional group. The remainder of this chapter
describes the signal pins in each functional group.
Table 1-1. DSP56321T Functional Signal Groupings
Number
Functional Group
of
Signals
Power (V
)
20
66
2
CC
Ground (GND)
Clock
PLL
1
Address bus
Data bus
18
24
10
5
1
2
Port A
Port B
Bus control
Interrupt and mode control
Host interface (HI08)
16
12
3
3
Enhanced synchronous serial interface (ESSI)
Serial communication interface (SCI)
Timer
Ports C and D
4
Port E
3
OnCE/JTAG Port
6
Notes: 1. Port A signals define the external memory interface port, including the external address bus, data
bus, and control signals.
2. Port B signals are the HI08 port signals multiplexed with the GPIO signals.
3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.
4. Port E signals are the SCI port signals multiplexed with the GPIO signals.
5. There are 8 signal lines that are not connected internally. These are designated no connect (NC) in
the package description (see Chapter 3). There are also two lines that are reserved.
Note: This chapter refers to a number of configuration registers used to select individual multiplexed
signal functionality. Refer to the DSP56321 Reference Manual (DSP56321RM/D) for details on
these configuration registers.
1-1
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Signal Groupings
After Reset
During Reset
DSP56321T
MODA
MODB
MODC
MODD
RESET
PINIT
IRQA
IRQB
IRQC
IRQD
RESET
NMI
Interrupt/
Power Inputs:
5
3
3
4
2
Mode Control
V
V
V
V
V
Core Logic
I/O
CCQL
CCQH
Address Bus
Data Bus
Bus Control
HI08
CCA
CCD
CCC
V
V
CCH
Non-Multiplexed Multiplexed
Port B
GPIO
PB[0–7]
PB8
PB9
PB10
PB13
2
ESSI/SCI/Timer
CCS
Bus
H[0–7]
HA0
HA1
Bus
8
HAD[0–7]
HAS/HAS
HA8
HA9
HA10
Double DS
HRD/HRD
HWR/HWR
Double HR
HTRQ/HTRQ PB14
HRRQ/HRRQ PB15
Grounds:
Host
66
GND
Ground plane
Interface
HA2
1
(HI08) Port
HCS/HCS
Single DS
HRW
HDS/HDS
Single HR
HREQ/HREQ
HACK/HACK
PB11
PB12
EXTAL
XTAL
Port C GPIO
PC[0–2]
PC3
PC4
PC5
Clock
3
Enhanced
Synchronous Serial
Interface Port 0
SC0[0–2]
SCK0
SRD0
2
(ESSI0)
STD0
Port D GPIO
PD[0–2]
PD3
PD4
PD5
3
Enhanced
Synchronous Serial
Interface Port 1
SC1[0–2]
SCK1
SRD1
Port A
2
(ESSI1)
18
STD1
External
A[0–17]
D[0–23]
Address Bus
24
4
External
Data Bus
Port E GPIO
PE0
PE1
Serial
RXD
TXD
SCLK
Communications
2
Interface (SCI) Port
PE2
AA[0–3]
RD
External
Bus
WR
TA
BR
Timer GPIO
TIO0
TIO1
Control
TIO0
TIO1
TIO2
3
Timers
BG
TIO2
BB
TCK
TDI
OnCE/
TDO
TMS
TRST
DE
JTAG Port
Notes: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or
double Host Request (HR) configurations. Since each of these modes is configured independently, any combination
of these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]).
Signals with dual designations (for example, HAS/HAS) have configurable polarity.
2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals
(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.
3. TIO[0–2] can be configured as GPIO signals.
Figure 1-1. Signals Identified by Functional Group
1-2
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Power
1.2 Power
Table 1-2. Power Inputs
Power Name
Description
V
V
V
V
V
V
V
Quiet Core (Low) Power—An isolated power for the core processing and clock logic. This
input must be isolated externally from all other chip power inputs.
CCQL
CCQH
CCA
Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied
externally to all other chip power inputs, except V
.
CCQL
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This
input must be tied externally to all other chip power inputs, except V
.
CCQL
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must
be tied externally to all other chip power inputs, except V
CCD
CCC
CCH
CCS
.
CCQL
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be
tied externally to all other chip power inputs, except V
.
CCQL
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to
all other chip power inputs, except V
.
CCQL
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers.
This input must be tied externally to all other chip power inputs, except V
.
CCQL
Note: The user must provide adequate external decoupling capacitors for all power connections.
1.3 Ground
Table 1-3. Grounds
Ground
Description
Name
GND
Ground—Connected to an internal device ground plane.
Note: The user must provide adequate external decoupling capacitors for all GND connections.
1.4 Clock
Table 1-4. Clock Signals
State
During
Reset
Signal
Name
Type
Signal Description
EXTAL
Input
Input
External Clock/Crystal Input—Interfaces the internal crystal oscillator
input to an external crystal or an external clock.
XTAL
Output
Chip-driven
Crystal Output—Connects the internal crystal oscillator output to an
external crystal. If an external clock is used, leave XTAL unconnected.
1-3
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External Memory Expansion Port (Port A)
1.5 External Memory Expansion Port (Port A)
Note: When the DSP56321T enters a low-power standby mode (stop or wait), it releases bus
mastership and tri-states the relevant Port A signals: A[0–17], D[0–23], AA0/RAS0–AA3/RAS3,
RD, WR, BB, CAS.
1.5.1 External Address Bus
Table 1-5. External Address Bus Signals
State During
Signal
Name
Type
Reset, Stop, or
Wait
Signal Description
A[0–17]
Output
Tri-stated
Address Bus—When the DSP is the bus master, A[0–17] are
active-high outputs that specify the address for external
program and data memory accesses. Otherwise, the signals
are tri-stated. To minimize power dissipation, A[0–17] do not
change state when external memory spaces are not being
accessed.
1.5.2 External Data Bus
Table 1-6. External Data Bus Signals
State
State
During
Reset
Signal
Type
During
Stop or
Wait
Signal Description
Name
D[0–23] Input/ Output
Ignored
Input
Last state: Data Bus—When the DSP is the bus master, D[0–23] are
Input:
active-high, bidirectional input/outputs that provide the
bidirectional data bus for external program and data memory
accesses. Otherwise, D[0–23] drivers are tri-stated. If the last
Ignored
Output:
Last value state is output, these lines maintain the last output state even if
all drivers are tri-stated, because they have internal weak
keeper circuits.
1-4
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External Memory Expansion Port (Port A)
1.5.3 External Bus Control
Table 1-7. External Bus Control Signals
State During
Reset, Stop, or
Wait
Signal
Name
Type
Signal Description
AA[0–3]
Output Tri-stated
Address Attribute—When defined as AA, these signals can be used as
chip selects or additional address lines. The default use defines a
priority scheme under which only one AA signal can be asserted at a
time. Setting the AA priority disable (APD) bit (Bit 14) of the Operating
Mode Register, the priority mechanism is disabled and the lines can be
used together as four external lines that can be decoded externally into
16 chip select signals.
RD
WR
TA
Output Tri-stated
Output Tri-stated
Read Enable—When the DSP is the bus master, RD is an active-low
output that is asserted to read external memory on the data bus
(D[0–23]). Otherwise, RD is tri-stated.
Write Enable—When the DSP is the bus master, WR is an active-low
output that is asserted to write external memory on the data bus
(D[0–23]). Otherwise, the signals are tri-stated.
Input
Ignored Input
Transfer Acknowledge—If the DSP56321T is the bus master and there
is no external bus activity, or the DSP56321T is not the bus master, the
TA input is ignored. The TA input is a data transfer acknowledge
(DTACK) function that can extend an external bus cycle indefinitely. Any
number of wait states (1, 2. . .infinity) can be added to the wait states
inserted by the bus control register (BCR) by keeping TA deasserted. In
typical operation, TA is deasserted at the start of a bus cycle, is asserted
to enable completion of the bus cycle, and is deasserted before the next
bus cycle. The current bus cycle completes one clock period after TA is
asserted synchronous to CLKOUT. The number of wait states is
determined by the TA input or by the BCR, whichever is longer. The
BCR can be used to set the minimum number of wait states in external
bus cycles.
To use the TA functionality, the BCR must be programmed to at least
one wait state. A zero wait state access cannot be extended by TA
deassertion; otherwise, improper operation may result. TA can operate
synchronously or asynchronously depending on the setting of the TAS
bit in the Operating Mode Register. TA functionality cannot be used
during DRAM type accesses; otherwise improper operation may result.
BR
Output Reset: Output
(deasserted)
Bus Request—Asserted when the DSP requests bus mastership. BR is
deasserted when the DSP no longer needs the bus. BR may be
asserted or deasserted independently of whether the DSP56321T is a
bus master or a bus slave. Bus “parking” allows BR to be deasserted
even though the DSP56321T is the bus master. (See the description of
bus “parking” in the BB signal description.) The bus request hold (BRH)
bit in the BCR allows BR to be asserted under software control even
though the DSP does not need the bus. BR is typically sent to an
State during
Stop/Wait depends
on BRH bit setting:
• BRH = 0: Output
(deasserted)
• BRH = 1: Maintains external bus arbitrator that controls the priority, parking, and tenure of
last state (that is, if
asserted, remains
asserted)
each master on the same external bus. BR is affected only by DSP
requests for the external bus, never for the internal bus. During
hardware reset, BR is deasserted and the arbitration is reset to the bus
slave state.
1-5
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External Memory Expansion Port (Port A)
Table 1-7. External Bus Control Signals (Continued)
State During
Reset, Stop, or
Wait
Signal
Name
Type
Signal Description
BG
Input
Ignored Input
Bus Grant—Asserted by an external bus arbitration circuit when the
DSP56321T becomes the next bus master. When BG is asserted, the
DSP56321T must wait until BB is deasserted before taking bus
mastership. When BG is deasserted, bus mastership is typically given
up at the end of the current bus cycle. This may occur in the middle of an
instruction that requires more than one external bus cycle for execution.
To ensure proper operation, the user must set the asynchronous bus
arbitration enable (ABE) bit (Bit 13) in the Operating Mode Register.
When this bit is set, BG and BB are synchronized internally. This adds a
required delay between the deassertion of an initial BG input and the
assertion of a subsequent BG input.
BB
Input/
Output
Ignored Input
Bus Busy—Indicates that the bus is active. Only after BB is deasserted
can the pending bus master become the bus master (and then assert
the signal again). The bus master may keep BB asserted after ceasing
bus activity regardless of whether BR is asserted or deasserted. Called
“bus parking,” this allows the current bus master to reuse the bus
without rearbitration until another device requires the bus. BB is
deasserted by an “active pull-up” method (that is, BB is driven high and
then released and held high by an external pull-up resistor).
Notes: 1. See BG for additional information.
2. BB requires an external pull-up resistor.
1-6
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Interrupt and Mode Control
1.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.
Table 1-8. Interrupt and Mode Control
State During
Signal Name
Type
Signal Description
Reset
MODA
Input
Schmitt-trigger
Input
Mode Select A—MODA, MODB, MODC, and MODD select one
of 16 initial chip operating modes, latched into the Operating
Mode Register when the RESET signal is deasserted.
IRQA
Input
External Interrupt Request A—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If the
processor is in the STOP or WAIT standby state and IRQA is
asserted, the processor exits the STOP or WAIT state.
MODB
IRQB
Input
Input
Schmitt-trigger
Input
Mode Select B—MODA, MODB, MODC, and MODD select one
of 16 initial chip operating modes, latched into the Operating
Mode Register when the RESET signal is deasserted.
External Interrupt Request B—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If the
processor is in the WAIT standby state and IRQB is asserted, the
processor exits the WAIT state.
MODC
IRQC
Input
Input
Schmitt-trigger
Input
Mode Select C—MODA, MODB, MODC, and MODD select one
of 16 initial chip operating modes, latched into the Operating
Mode Register when the RESET signal is deasserted.
External Interrupt Request C—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If the
processor is in the WAIT standby state and IRQC is asserted, the
processor exits the WAIT state.
MODD
IRQD
Input
Input
Schmitt-trigger
Input
Mode Select D—MODA, MODB, MODC, and MODD select one
of 16 initial chip operating modes, latched into the Operating
Mode Register when the RESET signal is deasserted.
External Interrupt Request D—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If the
processor is in the WAIT standby state and IRQD is asserted, the
processor exits the WAIT state.
RESET
Input
Schmitt-trigger
Input
Reset—Places the chip in the Reset state and resets the internal
phase generator. The Schmitt-trigger input allows a slowly rising
input (such as a capacitor charging) to reset the chip reliably.
When the RESET signal is deasserted, the initial chip operating
mode is latched from the MODA, MODB, MODC, and MODD
inputs. The RESET signal must be asserted after powerup.
PINIT
NMI
Input
Input
Input
PLL Initial—During assertion of RESET, the value of PINIT
determines whether the DPLL is enabled or disabled.
Nonmaskable Interrupt—After RESET deassertion and during
normal instruction processing, this Schmitt-trigger input is the
negative-edge-triggered NMI request.
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Host Interface (HI08)
1.7 Host Interface (HI08)
The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08 supports
a variety of standard buses and connects directly to a number of industry-standard microcomputers,
microprocessors, DSPs, and DMA hardware.
1.7.4 Host Port Usage Considerations
Careful synchronization is required when the system reads multiple-bit registers that are written by
another asynchronous system. This is a common problem when two asynchronous systems are connected
(as they are in the Host port). The considerations for proper operation are discussed in Table 1-9.
Table 1-9. Host Port Usage Considerations
Action
Description
Asynchronous read of receive
byte registers
When reading the receive byte registers, Receive register High (RXH), Receive
register Middle (RXM), or Receive register Low (RXL), the host interface
programmer should use interrupts or poll the Receive register Data Full (RXDF) flag
that indicates data is available. This assures that the data in the receive byte
registers is valid.
Asynchronous write to transmit The host interface programmer should not write to the transmit byte registers,
byte registers
Transmit register High (TXH), Transmit register Middle (TXM), or Transmit register
Low (TXL), unless the Transmit register Data Empty (TXDE) bit is set indicating that
the transmit byte registers are empty. This guarantees that the transmit byte
registers transfer valid data to the Host Receive (HRX) register.
Asynchronous write to host
vector
The host interface programmer must change the Host Vector (HV) register only
when the Host Command bit (HC) is clear. This practice guarantees that the DSP
interrupt control logic receives a stable vector.
1.7.5 Host Port Configuration
HI08 signal functions vary according to the programmed configuration of the interface as determined by
the 16 bits in the HI08 Port Control Register.
Table 1-10. Host Interface
StateDuring
Signal Name
Type
Signal Description
Reset1,2
H[0–7]
Input/Output
Ignored Input Host Data—When the HI08 is programmed to interface with a
non-multiplexed host bus and the HI function is selected, these
signals are lines 0–7 of the bidirectional Data bus.
HAD[0–7]
PB[0–7]
Input/Output
Host Address—When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, these signals
are lines 0–7 of the bidirectional multiplexed Address/Data bus.
Input or Output
Port B 0–7—When the HI08 is configured as GPIO through the
HI08 Port Control Register, these signals are individually
programmed as inputs or outputs through the HI08 Data Direction
Register.
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Host Interface (HI08)
Table 1-10. Host Interface (Continued)
StateDuring
Signal Name
Type
Signal Description
Reset1,2
HA0
Input
Ignored Input Host Address Input 0—When the HI08 is programmed to
interface with a nonmultiplexed host bus and the HI function is
selected, this signal is line 0 of the host address input bus.
HAS/HAS
Input
Host Address Strobe—When the HI08 is programmed to
interface with a multiplexed host bus and the HI function is
selected, this signal is the host address strobe (HAS)
Schmitt-trigger input. The polarity of the address strobe is
programmable but is configured active-low (HAS) following reset.
PB8
Input or Output
Port B 8—When the HI08 is configured as GPIO through the HI08
Port Control Register, this signal is individually programmed as an
input or output through the HI08 Data Direction Register.
HA1
Input
Ignored Input Host Address Input 1—When the HI08 is programmed to
interface with a nonmultiplexed host bus and the HI function is
selected, this signal is line 1 of the host address (HA1) input bus.
HA8
Input
Host Address 8—When the HI08 is programmed to interface with
a multiplexed host bus and the HI function is selected, this signal
is line 8 of the host address (HA8) input bus.
PB9
HA2
Input or Output
Input
Port B 9—When the HI08 is configured as GPIO through the HI08
Port Control Register, this signal is individually programmed as an
input or output through the HI08 Data Direction Register.
Ignored Input Host Address Input 2—When the HI08 is programmed to
interface with a nonmultiplexed host bus and the HI function is
selected, this signal is line 2 of the host address (HA2) input bus.
HA9
Input
Host Address 9—When the HI08 is programmed to interface with
a multiplexed host bus and the HI function is selected, this signal
is line 9 of the host address (HA9) input bus.
PB10
Input or Output
Input
Port B 10—When the HI08 is configured as GPIO through the
HI08 Port Control Register, this signal is individually programmed
as an input or output through the HI08 Data Direction Register.
HCS/HCS
Ignored Input Host Chip Select—When the HI08 is programmed to interface
with a nonmultiplexed host bus and the HI function is selected, this
signal is the host chip select (HCS) input. The polarity of the chip
select is programmable but is configured active-low (HCS) after
reset.
HA10
PB13
Input
Host Address 10—When the HI08 is programmed to interface
with a multiplexed host bus and the HI function is selected, this
signal is line 10 of the host address (HA10) input bus.
Input or Output
Port B 13—When the HI08 is configured as GPIO through the
HI08 Port Control Register, this signal is individually programmed
as an input or output through the HI08 Data Direction Register.
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Host Interface (HI08)
Table 1-10. Host Interface (Continued)
StateDuring
Signal Name
Type
Signal Description
Reset1,2
HRW
Input
Ignored Input Host Read/Write—When the HI08 is programmed to interface
with a single-data-strobe host bus and the HI function is selected,
this signal is the Host Read/Write (HRW) input.
HRD/HRD
Input
Host Read Data—When the HI08 is programmed to interface with
a double-data-strobe host bus and the HI function is selected, this
signal is the HRD strobe Schmitt-trigger input. The polarity of the
data strobe is programmable but is configured as active-low (HRD)
after reset.
PB11
Input or Output
Port B 11—When the HI08 is configured as GPIO through the
HI08 Port Control Register, this signal is individually programmed
as an input or output through the HI08 Data Direction Register.
HDS/HDS
Input
Ignored Input Host Data Strobe—When the HI08 is programmed to interface
with a single-data-strobe host bus and the HI function is selected,
this signal is the host data strobe (HDS) Schmitt-trigger input. The
polarity of the data strobe is programmable but is configured as
active-low (HDS) following reset.
HWR/HWR
Input
Host Write Data—When the HI08 is programmed to interface with
a double-data-strobe host bus and the HI function is selected, this
signal is the host write data strobe (HWR) Schmitt-trigger input.
The polarity of the data strobe is programmable but is configured
as active-low (HWR) following reset.
PB12
Input or Output
Output
Port B 12—When the HI08 is configured as GPIO through the
HI08 Port Control Register, this signal is individually programmed
as an input or output through the HI08 Data Direction Register.
HREQ/HREQ
Ignored Input Host Request—When the HI08 is programmed to interface with a
single host request host bus and the HI function is selected, this
signal is the host request (HREQ) output. The polarity of the host
request is programmable but is configured as active-low (HREQ)
following reset. The host request may be programmed as a driven
or open-drain output.
HTRQ/HTRQ
Output
Transmit Host Request—When the HI08 is programmed to
interface with a double host request host bus and the HI function is
selected, this signal is the transmit host request (HTRQ) output.
The polarity of the host request is programmable but is configured
as active-low (HTRQ) following reset. The host request may be
programmed as a driven or open-drain output.
PB14
Input or Output
Port B 14—When the HI08 is configured as GPIO through the
HI08 Port Control Register, this signal is individually programmed
as an input or output through the HI08 Data Direction Register.
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Host Interface (HI08)
Table 1-10. Host Interface (Continued)
StateDuring
Signal Name
Type
Signal Description
Reset1,2
HACK/HACK
Input
Ignored Input Host Acknowledge—When the HI08 is programmed to interface
with a single host request host bus and the HI function is selected,
this signal is the host acknowledge (HACK) Schmitt-trigger input.
The polarity of the host acknowledge is programmable but is
configured as active-low (HACK) after reset.
HRRQ/HRRQ
Output
Receive Host Request—When the HI08 is programmed to
interface with a double host request host bus and the HI function is
selected, this signal is the receive host request (HRRQ) output.
The polarity of the host request is programmable but is configured
as active-low (HRRQ) after reset. The host request may be
programmed as a driven or open-drain output.
PB15
Input or Output
Port B 15—When the HI08 is configured as GPIO through the
HI08 Port Control Register, this signal is individually programmed
as an input or output through the HI08 Data Direction Register.
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines maintain the last output state even if the drivers are tri-stated,
because they have internal weak keeper circuits.
2. The Wait processing state does not affect the signal state.
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Enhanced Synchronous Serial Interface 0 (ESSI0)
1.8 Enhanced Synchronous Serial Interface 0 (ESSI0)
Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial
communication with a variety of serial devices, including one or more industry-standard codecs, other
DSPs, microprocessors, and peripherals that implement the Motorola serial peripheral interface (SPI).
Table 1-11. Enhanced Synchronous Serial Interface 0
StateDuring
Signal Name
Type
Signal Description
Reset1,2
SC00
Input or Output Ignored Input Serial Control 0—For asynchronous mode, this signal is used for
the receive clock I/O (Schmitt-trigger input). For synchronous
mode, this signal is used either for transmitter 1 output or for serial
I/O flag 0.
PC0
Input or Output
Port C 0—The default configuration following reset is GPIO input
PC0. When configured as PC0, signal direction is controlled
through the Port C Direction Register. The signal can be
configured as ESSI signal SC00 through the Port C Control
Register.
SC01
PC1
Input/Output
Ignored Input Serial Control 1—For asynchronous mode, this signal is the
receiver frame sync I/O. For synchronous mode, this signal is
used either for transmitter 2 output or for serial I/O flag 1.
Input or Output
Port C 1—The default configuration following reset is GPIO input
PC1. When configured as PC1, signal direction is controlled
through the Port C Direction Register. The signal can be
configured as an ESSI signal SC01 through the Port C Control
Register.
SC02
Input/Output
Ignored Input Serial Control Signal 2—The frame sync for both the transmitter
and receiver in synchronous mode, and for the transmitter only in
asynchronous mode. When configured as an output, this signal is
the internally generated frame sync signal. When configured as an
input, this signal receives an external frame sync signal for the
transmitter (and the receiver in synchronous operation).
PC2
Input or Output
Input/Output
Port C 2—The default configuration following reset is GPIO input
PC2. When configured as PC2, signal direction is controlled
through the Port C Direction Register. The signal can be
configured as an ESSI signal SC02 through the Port C Control
Register.
SCK0
Ignored Input Serial Clock—Provides the serial bit rate clock for the ESSI. The
SCK0 is a clock input or output, used by both the transmitter and
receiver in synchronous modes or by the transmitter in
asynchronous modes.
Although an external serial clock can be independent of and
asynchronous to the DSP system clock, it must exceed the
minimum clock cycle time of 6T (that is, the system clock
frequency must be at least three times the external ESSI clock
frequency). The ESSI needs at least three DSP phases inside
each half of the serial clock.
PC3
Input or Output
Port C 3—The default configuration following reset is GPIO input
PC3. When configured as PC3, signal direction is controlled
through the Port C Direction Register. The signal can be
configured as an ESSI signal SCK0 through the Port C Control
Register.
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Enhanced Synchronous Serial Interface 1 (ESSI1)
Table 1-11. Enhanced Synchronous Serial Interface 0 (Continued)
StateDuring
Signal Name
Type
Signal Description
Reset1,2
SRD0
Input
Ignored Input Serial Receive Data—Receives serial data and transfers the data
to the ESSI Receive Shift Register. SRD0 is an input when data is
received.
PC4
Input or Output
Port C 4—The default configuration following reset is GPIO input
PC4. When configured as PC4, signal direction is controlled
through the Port C Direction Register. The signal can be
configured as an ESSI signal SRD0 through the Port C Control
Register.
STD0
PC5
Output
Ignored Input Serial Transmit Data—Transmits data from the Serial Transmit
Shift Register. STD0 is an output when data is transmitted.
Input or Output
Port C 5—The default configuration following reset is GPIO input
PC5. When configured as PC5, signal direction is controlled
through the Port C Direction Register. The signal can be
configured as an ESSI signal STD0 through the Port C Control
Register.
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines maintain the last output state even if the drivers are tri-stated,
because they have internal weak keeper circuits.
2. The Wait processing state does not affect the signal state.
1.9 Enhanced Synchronous Serial Interface 1 (ESSI1)
Table 1-12. Enhanced Serial Synchronous Interface 1
StateDuring
Signal Name
Type
Signal Description
Reset1,2
SC10
Input or Output Ignored Input Serial Control 0—For asynchronous mode, this signal is used for
the receive clock I/O (Schmitt-trigger input). For synchronous
mode, this signal is used either for transmitter 1 output or for serial
I/O flag 0.
PD0
Input or Output
Port D 0—The default configuration following reset is GPIO input
PD0. When configured as PD0, signal direction is controlled
through the Port D Direction Register. The signal can be
configured as an ESSI signal SC10 through the Port D Control
Register.
SC11
PD1
Input/Output
Ignored Input Serial Control 1—For asynchronous mode, this signal is the
receiver frame sync I/O. For synchronous mode, this signal is
used either for Transmitter 2 output or for Serial I/O Flag 1.
Input or Output
Port D 1—The default configuration following reset is GPIO input
PD1. When configured as PD1, signal direction is controlled
through the Port D Direction Register. The signal can be
configured as an ESSI signal SC11 through the Port D Control
Register.
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Enhanced Synchronous Serial Interface 1 (ESSI1)
Table 1-12. Enhanced Serial Synchronous Interface 1 (Continued)
StateDuring
Signal Name
Type
Signal Description
Reset1,2
SC12
Input/Output
Ignored Input Serial Control Signal 2—The frame sync for both the transmitter
and receiver in synchronous mode and for the transmitter only in
asynchronous mode. When configured as an output, this signal is
the internally generated frame sync signal. When configured as an
input, this signal receives an external frame sync signal for the
transmitter (and the receiver in synchronous operation).
PD2
Input or Output
Port D 2—The default configuration following reset is GPIO input
PD2. When configured as PD2, signal direction is controlled
through the Port D Direction Register. The signal can be
configured as an ESSI signal SC12 through the Port D Control
Register.
SCK1
Input/Output
Ignored Input Serial Clock—Provides the serial bit rate clock for the ESSI. The
SCK1 is a clock input or output used by both the transmitter and
receiver in synchronous modes or by the transmitter in
asynchronous modes.
Although an external serial clock can be independent of and
asynchronous to the DSP system clock, it must exceed the
minimum clock cycle time of 6T (that is, the system clock
frequency must be at least three times the external ESSI clock
frequency). The ESSI needs at least three DSP phases inside
each half of the serial clock.
PD3
Input or Output
Port D 3—The default configuration following reset is GPIO input
PD3. When configured as PD3, signal direction is controlled
through the Port D Direction Register. The signal can be
configured as an ESSI signal SCK1 through the Port D Control
Register.
SRD1
PD4
Input
Ignored Input Serial Receive Data—Receives serial data and transfers the data
to the ESSI Receive Shift Register. SRD1 is an input when data is
being received.
Input or Output
Port D 4—The default configuration following reset is GPIO input
PD4. When configured as PD4, signal direction is controlled
through the Port D Direction Register. The signal can be
configured as an ESSI signal SRD1 through the Port D Control
Register.
STD1
PD5
Output
Ignored Input Serial Transmit Data—Transmits data from the Serial Transmit
Shift Register. STD1 is an output when data is being transmitted.
Input or Output
Port D 5—The default configuration following reset is GPIO input
PD5. When configured as PD5, signal direction is controlled
through the Port D Direction Register. The signal can be
configured as an ESSI signal STD1 through the Port D Control
Register.
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines maintain the last output state even if the drivers are tri-stated,
because they have internal weak keeper circuits.
2. The Wait processing state does not affect the signal state.
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Serial Communication Interface (SCI)
1.10 Serial Communication Interface (SCI)
The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or
peripherals such as modems.
Table 1-13. Serial Communication Interface
StateDuring
Signal Name
Type
Signal Description
Reset1,2
RXD
Input
Ignored Input Serial Receive Data—Receives byte-oriented serial data and
transfers it to the SCI Receive Shift Register.
PE0
Input or Output
Port E 0—The default configuration following reset is GPIO input
PE0. When configured as PE0, signal direction is controlled
through the Port E Direction Register. The signal can be
configured as an SCI signal RXD through the Port E Control
Register.
TXD
PE1
Output
Ignored Input Serial Transmit Data—Transmits data from the SCI Transmit
Data Register.
Input or Output
Port E 1—The default configuration following reset is GPIO input
PE1. When configured as PE1, signal direction is controlled
through the Port E Direction Register. The signal can be
configured as an SCI signal TXD through the Port E Control
Register.
SCLK
PE2
Input/Output
Ignored Input Serial Clock—Provides the input or output clock used by the
transmitter and/or the receiver.
Input or Output
Port E 2—The default configuration following reset is GPIO input
PE2. When configured as PE2, signal direction is controlled
through the Port E Direction Register. The signal can be
configured as an SCI signal SCLK through the Port E Control
Register.
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines maintain the last output state even if the drivers are tri-stated,
because they have internal weak keeper circuits.
2. The Wait processing state does not affect the signal state.
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Timers
1.11 Timers
The DSP56321T has three identical and independent timers. Each timer can use internal or external
clocking and can either interrupt the DSP56321T after a specified number of events (clocks) or signal an
external device after counting a specific number of internal events.
Table 1-14. Triple Timer Signals
StateDuring
Reset1,2
Signal Name
Type
Signal Description
TIO0
Input or Output Ignored Input
Input or Output Ignored Input
Input or Output Ignored Input
Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions
as an external event counter or in measurement mode, TIO0 is
used as input. When Timer 0 functions in watchdog, timer, or pulse
modulation mode, TIO0 is used as output.
The default mode after reset is GPIO input. TIO0 can be changed
to output or configured as a timer I/O through the Timer 0
Control/Status Register (TCSR0).
TIO1
Timer 1 Schmitt-Trigger Input/Output— When Timer 1 functions
as an external event counter or in measurement mode, TIO1 is
used as input. When Timer 1 functions in watchdog, timer, or pulse
modulation mode, TIO1 is used as output.
The default mode after reset is GPIO input. TIO1 can be changed
to output or configured as a timer I/O through the Timer 1
Control/Status Register (TCSR1).
TIO2
Timer 2 Schmitt-Trigger Input/Output— When Timer 2 functions
as an external event counter or in measurement mode, TIO2 is
used as input. When Timer 2 functions in watchdog, timer, or pulse
modulation mode, TIO2 is used as output.
The default mode after reset is GPIO input. TIO2 can be changed
to output or configured as a timer I/O through the Timer 2
Control/Status Register (TCSR2).
Notes: 1. In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines maintain the last output state even if the drivers are tri-stated,
because they have internal weak keeper circuits.
2. The Wait processing state does not affect the signal state.
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JTAG and OnCE Interface
1.12 JTAG and OnCE Interface
The DSP56300 family and in particular the DSP56321T support circuit-board test strategies based on the
IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture, the industry standard
developed under the sponsorship of the Test Technology Committee of IEEE and the JTAG.
The OnCE module provides a means to interface nonintrusively with the DSP56300 core and its
peripherals so that you can examine registers, memory, or on-chip peripherals. Functions of the OnCE
module are provided through the JTAG TAP signals.
For programming models, see the chapter on debugging support in the DSP56300 Family Manual.
Table 1-15. JTAG/OnCE Interface
State
During
Reset
Signal
Name
Type
Signal Description
TCK
Input
Input
Test Clock—A test clock input signal to synchronize the JTAG
test logic.
TDI
Input
Input
Test Data Input—A test data serial input signal for test
instructions and data. TDI is sampled on the rising edge of TCK
and has an internal pull-up resistor.
TDO
Output
Tri-stated
Test Data Output—A test data serial output signal for test
instructions and data. TDO is actively driven in the shift-IR and
shift-DR controller states. TDO changes on the falling edge of
TCK.
TMS
TRST
DE
Input
Input
Input
Input
Input
Test Mode Select—Sequences the test controller’s state
machine. TMS is sampled on the rising edge of TCK and has an
internal pull-up resistor.
Test Reset—Initializes the test controller asynchronously. TRST
has an internal pull-up resistor. TRST must be asserted after
powerup.
Input/ Output
(open-drain)
Debug Event—As an input, initiates Debug mode from an
external command controller, and, as an open-drain output,
acknowledges that the chip has entered Debug mode. As an
input, DE causes the DSP56300 core to finish executing the
current instruction, save the instruction pipeline information,
enter Debug mode, and wait for commands to be entered from
the debug serial input line. This signal is asserted as an output
for three clock cycles when the chip enters Debug mode as a
result of a debug request or as a result of meeting a breakpoint
condition. The DE has an internal pull-up resistor.
This signal is not a standard part of the JTAG TAP controller.
The signal connects directly to the OnCE module to initiate
debug mode directly or to provide a direct external indication that
the chip has entered Debug mode. All other interface with the
OnCE module must occur through the JTAG port.
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JTAG and OnCE Interface
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Chapter 2
Specifications
2.1 Introduction
The DSP56321T is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL) compatible
inputs and outputs.
Note: The DSP56321T specifications are preliminary and are from design simulations, and may not be
fully tested or guaranteed. Finalized specifications will be published after full characterization
and device qualifications are complete.
2.2 Maximum Ratings
CAUTION
This device contains circuitry protecting
against damage due to high static voltage or
electrical fields; however, normal precautions
should be taken to avoid exceeding maximum
voltage ratings. Reliability is enhanced if
unused inputs are tied to an appropriate logic
voltage level (for example, either GND or
V
).
CCQH
Note: In the calculation of timing requirements, adding a maximum value of one specification to a
minimum value of another specification does not yield a reasonable sum. A maximum
specification is calculated using a worst case variation of process parameter values in one
direction. The minimum specification is calculated using the worst case for the same parameters
in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the
same device that has a “minimum” value for another specification; adding a maximum to a
minimum represents a condition that can never exist.
2-1
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Thermal Characteristics
Table 2-1. Absolute Maximum Ratings
Rating1
Symbol
Value1, 2
Unit
3
Supply Voltage
V
–0.1 to 2.25
–0.3 to 4.35
V
V
CCQL
3
4
Input/Output Supply Voltage
All input voltages
V
CCQH
V
GND – 0.3 to V
+ 0.3
V
IN
CCQH
Current drain per pin excluding V
and GND
, V
,
I
10
mA
CCQL
CCQH
5
Operating temperature range
T
0 to +85
°C
°C
J
Storage temperature
T
–55 to +150
STG
Notes: 1. GND = 0 V, V
= 1.6 V ± 0.1 V, V
= 3.3 V ± 0.3 V, T = 0°C to +85°C, CL = 50 pF
CCQL
CCQH J
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not
guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent
damage to the device.
3. Power-up sequence: During power-up, and throughout the DSP56321T operation, V
voltage
CCQH
must always be higher or equal to V
voltage.
CCQL
4.
V
provides input power for V
, V
, V
, V
, and V
. These power blocks are isolated
CCQH
CCA
CCD
CCC
CCH
CCS
internally, but must be connected together externally.
5. Typically, this value implies a maximum ambient temperature (T ) of +70°C.
A
2.3 Thermal Characteristics
Table 2-2. Thermal Characteristics
Thermal Resistance Characteristic Symbol
FC-PBGA
Value
Unit
1,2
1,3
Junction-to-ambient, natural convection, single-layer board (1s)
R
50
28
37
23
13
0.1
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJA
Junction-to-ambient, natural convection, four-layer board (2s2p)
Junction-to-ambient, @200 ft/min air flow, single-layer board (1s)
R
R
R
θJMA
θJMA
θJMA
1,3
1,3
Junction-to-ambient, @200 ft/min air flow, four-layer board (2s2p)
4
Junction-to-board
R
θJB
θJC
5
Junction-to-case thermal resistance
R
Notes: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the
board, and board thermal resistance. All values in this table are simulated; testing is not complete.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
5. Indicates the average thermal resistance between the die and the case top surface as measured by the
cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature.
2-2
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DC Electrical Characteristics
2.4 DC Electrical Characteristics
Table 2-3. DC Electrical Characteristics7
Characteristics
Symbol
Min
Typ
Max
Unit
1
Supply voltage :
•
•
Core (V
)
, V
1.5
3.0
1.6
3.3
1.7
3.6
V
V
CCQL
I/O (V
, V
, V
, V
, and V
)
CCQH
CCA
CCD
CCC
CCH
CCS
Input high voltage
•
•
D[0–23], BG, BB, TA
V
2.0
2.0
—
—
V
V
+ 0.3
V
V
IH
CCQH
+ 0.3
CCQH
2
MOD/IRQ RESET, PINIT/NMI and all
JTAG/ESSI/SCI/Timer/HI08 pins
V
IHP
9
•
EXTAL
V
0.8 × V
—
V
V
IHX
CCQH
CCQH
Input low voltage
3
3
•
•
•
D[0–23], BG, BB, TA, MOD /IRQ , RESET, PINIT
All JTAG/ESSI/SCI/Timer/HI08 pins
EXTAL
V
–0.3
–0.3
–0.3
—
—
—
0.8
0.8
V
V
V
IL
V
V
ILP
ILX
9
0.2 × V
CCQH
Input leakage current
I
–10
–10
—
—
10
10
µA
µA
IN
High impedance (off-state) input current
(@ 2.4 V / 0.4 V)
I
TSI
Output high voltage
V
OH
6,8
•
•
TTL (I = –0.4 mA)
2.4
– 0.01
CCQH
—
—
—
—
V
V
OH
6
CMOS (I = –10 µA)
V
OH
Output low voltage
V
OL
6,8
•
•
TTL (I = 3.0 mA, open-drain pins I = 6.7 mA)
—
—
—
—
0.4
0.01
V
V
OL
OL
6
CMOS (I = 10 µA)
OL
Internal supply current:
3
•
•
•
In Normal mode at:
—220 MHz
I
CCI
—
—
198
216
—
—
mA
mA
—240 MHz
4
In Wait mode at:
I
CCW
—220 MHz
—240 MHz
In Stop mode
—
—
—
TBD
TBD
TBD
—
—
—
mA
mA
µA
5
I
CCS
6
Input capacitance
C
—
—
10
pF
IN
Notes: 1. Power-up sequence: During power-up, and throughout the DSP56321T operation, V
voltage must
CCQH
always be higher or equal to V
voltage.
CCQL
2. Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins.
3. Section 4.3 provides a formula to compute the estimated current requirements in Normal mode. To
obtain these results, all inputs must be terminated (that is, not allowed to float). Measurements are
based on synthetic intensive DSP benchmarks (see Appendix A). The power consumption numbers in
this specification are 90 percent of the measured results of this benchmark. This reflects typical DSP
applications.
4. To obtain these results, all inputs must be terminated (that is, not allowed to float).
5. DC current in Stop mode is based on preliminary estimation, and is evaluated based on measurements.
To obtain these results, all inputs not disconnected at Stop mode must be terminated (that is, not
allowed to float), and the DPLL and on-chip crystal oscillator must be disabled.
6. Periodically sampled and not 100 percent tested.
7.
8. This characteristic does not apply to XTAL.
9. Driving EXTAL to the low V or the high V
V
= 3.3 V ± 0.3 V, V
= 1.6 V ± 0.1 V; T = 0°C to +85°C, C = 50 pF
CCQH
CCQL J L
value may cause additional power consumption (DC
ILX
IHX
current). To minimize power consumption, the minimum V
should be no lower than
IHX
0.9 × V
and the maximum V should be no higher than 0.1 × V
.
CCQH
ILX
CCQH
2-3
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AC Electrical Characteristics
2.5 AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum
of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels
shown in Note 6 of the previous table. AC timing specifications, which are referenced to a device input
signal, are measured in production with respect to the 50 percent point of the respective input signal’s
transition. DSP56321T output levels are measured with the production test machine VOL and VOH
reference levels set at 0.4 V and 2.4 V, respectively.
Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test
conditions are 15 MHz and rated speed.
2.5.1
Internal Clocks
Table 2-4. Internal Clocks
Expression
Typ
Characteristics
Symbol
Min
Max
Internal operating frequency
f
•
•
With DPLL disabled
With DPLL enabled
—
—
Ef/2
—
—
(Ef × MF)/(PDF × DF)
Internal clock cycle time
T
T
C
•
•
With DPLL disabled
With DPLL enabled
—
—
2 × ET
ET × PDF × DF/MF
—
—
C
C
Internal clock high period
H
•
•
With DPLL disabled
With DPLL enabled
—
0.49 × T
ET
—
—
0.51 × T
C
C
C
C
C
Internal clock low period
•
•
With DPLL disabled
With DPLL enabled
T
—
0.49 × T
ET
—
—
0.51 × T
L
C
Note:
Ef = External frequency; MF = Multiplication Factor = MFI + MFN/MFD; PDF = Predivision Factor;
DF = Division Factor; T = Internal clock cycle; ET = External clock cycle; T = Internal clock high;
C
C
H
T
= Internal clock low
L
2.5.2
External Clock Operation
The DSP56321T system clock is derived from the on-chip oscillator or is externally supplied. To use the
on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL;
an example is shown in Figure 2-1.
Suggested Component Values:
OSC
R = 1 MΩ ± 10%
C = 10 pF ± 10%
EXTAL
XTAL
f
= 16–32 MHz
R
Calculations are for a 16–32 MHz crystal with the following parameters:
•
•
•
shunt capacitance (C ) of 5.2–7.3 pF,
series resistance of 5–15 Ω, and
drive level of 2 mW.
C
0
C
XTAL1
Fundamental Frequency
Crystal Oscillator
Note: Make sure that in the PCTL Register:
XTLD (bit 2) = 0
•
Figure 2-1. Crystal Oscillator Circuits
2-4
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AC Electrical Characteristics
Table 2-5. External Clock Operation
220 MHz
240 MHz
No.
Characteristics
Symbol
Min
Max
Min
Max
1
1
Frequency of EXTAL (EXTAL Pin Frequency)
•
•
With DPLL disabled
With DPLL enabled
Ef
0 MHz
220 MHz
0 MHz
240 MHz
2
DEFR = PDF × PDFR 16 MHz 220 MHz 16 MHz 240 MHz
3
2
3
4
7
EXTAL input high
•
•
ET
H
4
With DPLL disabled (46.7%–53.3% duty cycle )
With DPLL enabled (42.5%–57.5% duty cycle )
2.13 ns
1.93 ns
∞
1.95 ns
1.77 ns
∞
4
35.9 ns
35.9 ns
4
EXTAL input low
•
•
ET
L
4
With DPLL disabled (46.7%–53.3% duty cycle )
With DPLL enabled (42.5%–57.5% duty cycle )
2.13 ns
1.93 ns
∞
1.95 ns
1.77 ns
∞
4
35.9 ns
35.9 ns
3
EXTAL cycle time
ET
C
•
•
With DPLL disabled
With DPLL enabled
4.55 ns
4.55 ns
∞
4.17 ns
4.17 ns
∞
62.5 ns
62.5 ns
Instruction cycle time = I
= ET
I
CYC
CYC
C
•
•
With DPLL disabled
With DPLL enabled
9.1 ns
4.55 ns
∞
1.6 µs
8.34 ns
4.17 ns
∞
1.6 µs
Notes: 1. The rise and fall time of this external clock should be 2 ns maximum.
2. Refer to Table 2-6 for a description of PDF and PDFR.
3. Measured at 50 percent of the input transition.
4. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock
high or low time required for correction operation, however, remains the same at lower operating frequencies;
therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as
long as the minimum high time and low time requirements are met.
Note: If an externally-supplied square wave voltage source is used, disable the internal oscillator
circuit during bootup by setting XTLD (PCTL Register bit 2 = 1—see the DSP56321T
Reference Manual). The external square wave source connects to EXTAL; XTAL is not
physically connected to the board or socket. Figure 2-2 shows the EXTAL input and the internal
clock signals.
VIHX
Midpoint
EXTAL
ET
ET
H
V
L
ILX
2
3
Note:
The midpoint is 0.5 (V
+ V ).
IHX ILX
4
ET
C
Figure 2-2. External Input Clock Timing
2-5
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AC Electrical Characteristics
2.5.3
Clock Generator (CLKGEN) and Digital Phase Lock Loop
(DPLL) Characteristics
Table 2-6. CLKGEN and DPLL Characteristics
220 MHz
240 MHz
Characteristics
Symbol
Unit
Min
Max
Min
Max
1
Predivision factor
PDF
1
16
5
16
32
1
16
5
16
32
—
MHz
—
Predivider output clock frequency range
PDFR
MF
2
Total multiplication factor
15
15
1
Multiplication factor integer part
MFI
5
15
5
15
—
3
Multiplication factor numerator
MFN
MFD
0
127
128
440
0
127
128
480
—
Multiplication factor denominator
Double clock frequency range
1
1
—
DDFR
DPLT
160
160
MHz
µs
4
5
6
5
6
Phase lock-in time
6.8
150
6.8
150
Notes: 1. Refer to the DSP56321 User’s Manual for a detailed description of register reset values.
2. The total multiplication factor (MF) includes both integer and fractional parts (that is, MF = MFI +
MFN/MFD).
3. The numerator (MFN) should be less than the denominator (MFD).
4. DPLL lock procedure duration is specified for the case when an external clock source is supplied to the
EXTAL pin. Parameters will be refined after silicon characterization.
5. Frequency-only Lock Mode or non-integer MF, after partial reset.
6. Frequency and Phase Lock Mode, integer MF, after full reset.
2-6
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AC Electrical Characteristics
2.5.4
Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6
220 MHz
240 MHz
No.
Characteristics
Expression
Unit
Min
Max
Min
Max
8
Delay from RESET assertion to all pins at
reset value
—
—
26
—
26
ns
3
4
9
Required RESET duration
Power on, external clock generator, DPLL
disabled
Power on, external clock generator, DPLL
enabled
50 × ET
227.5
4.55
—
—
208.5
4.17
—
—
ns
C
1000 × ET
µs
C
Power on, internal oscillator
During STOP, XTAL disabled
During STOP, XTAL enabled
During normal operation
75000 × ET
75000 × ET
0.341
0.341
11.38
11.38
—
—
—
—
0.313
0.313
10.43
10.43
—
—
—
—
ms
ms
ns
C
C
2.5 × T
2.5 × T
C
C
ns
10 Delay from asynchronous RESET
deassertion to first external address output
5
(internal reset deassertion)
Minimum
Maximum
3.25 × T + 2.0
16.79
—
—
102.14
15.55
—
—
94.44
ns
ns
C
20.25 T + 10
C
13 Mode select setup time
14 Mode select hold time
30.0
0.0
—
—
—
30.0
0.0
—
—
—
ns
ns
ns
15 Minimum edge-triggered interrupt request
assertion width
4.0
4.0
16 Minimum edge-triggered interrupt request
deassertion width
4.0
—
4.0
—
ns
17 Delay from IRQA, IRQB, IRQC, IRQD, NMI
assertion to external memory access address
out valid
Caused by first interrupt instruction fetch
Caused by first interrupt instruction execution
4.25 × T + 2.0
21.24
34.99
—
—
19.72
32.23
—
—
ns
ns
C
7.25 × T + 2.0
C
18 Delay from IRQA, IRQB, IRQC, IRQD, NMI
assertion to general-purpose transfer output
valid caused by first interrupt instruction
execution
10 × T + 5.0
50.5
—
46.17
—
ns
ns
ns
C
19 Delay from address output valid caused by
first interrupt instruction execute to interrupt
request deassertion for level sensitive fast
(WS + 3.75) × T – 10.94
—
Note 8
Note 8
—
Note 8
Note 8
C
1, 7, 8
interrupts
20 Delay from RD assertion to interrupt request
(WS + 3.25) × T – 10.94
—
—
C
1,
deassertion for level sensitive fast interrupts
7, 8
21 Delay from WR assertion to interrupt
request deassertion for level sensitive fast
1, 7, 8
interrupts
SRAM WS = 3
SRAM WS ≥ 4
(WS + 3) × T – 10.94
(WS + 2.5) × T – 10.94
C
—
—
Note 8
Note 8
—
—
Note 8
Note 8
ns
ns
C
24 Duration for IRQA assertion to recover from
Stop state
5.9
—
5.9
—
ns
2-7
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AC Electrical Characteristics
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued)
220 MHz
240 MHz
No.
Characteristics
Expression
Unit
Min
Max
Min
Max
25 Delay from IRQA assertion to fetch of first
2, 3
instruction (when exiting Stop)
DPLL is not active during Stop (PCTL Bit 1 =
0) and Stop delay is enabled (Operating Mode
Register Bit 6 = 0)
DPLL is not active during Stop (PCTL Bit 1 =
0) and Stop delay is not enabled (Operating
Mode Register Bit 6 = 1)
DPLT + (128K × T )
589.2
6.9
732.4
150.1
39.6
540.6
6.9
683.8
150.1
35.5
µs
µs
ns
C
DPLT + (23.75 ± 0.5) × T
C
DPLL is active during Stop (PCTL Bit 1 = 1;
Implies No Stop Delay)
(8.25 ± 0.5) × T
35.3
32.3
C
26 Duration of level sensitive IRQA assertion
to ensure interrupt service (when exiting
2, 3
Stop)
DPLL is not active during Stop (PCTL bit 1 =
0) and Stop delay is enabled (Operating Mode
Register Bit 6 = 0)
DPLL is not active during Stop (PCTL bit 1 =
0) and Stop delay is not enabled (Operating
Mode Register Bit 6 = 1)
DPLT + (128 K × T )
589.2
6.9
—
—
—
540.6
6.9
—
—
—
µs
µs
ns
C
DPLT + (20.5 ± 0.5) × T
C
DPLL is active during Stop ((PCTL bit 1 = 0;
implies no Stop delay)
5.5 × T
25.0
22.9
C
27 Interrupt Requests Rate
HI08, ESSI, SCI, Timer
DMA
12T
—
—
—
—
54.6
36.4
36.4
54.6
—
—
—
—
50.0
33.4
33.4
50.0
ns
ns
ns
ns
C
8T
8T
C
IRQ, NMI (edge trigger)
IRQ, NMI (level trigger)
C
12T
C
28 DMA Requests Rate
Data read from HI08, ESSI, SCI
Data write to HI08, ESSI, SCI
Timer
6T
7T
2T
3T
—
—
—
—
27.3
31.9
9.1
—
—
—
—
25.0
29.2
8.3
ns
ns
ns
ns
C
C
C
C
IRQ, NMI (edge trigger)
13.7
12.5
29 Delay from IRQA, IRQB, IRQC, IRQD, NMI
assertion to external memory (DMA source)
access address out valid
4.25 × T + 2.0
21.34
—
19.72
—
ns
C
Notes: 1. When fast interrupts are used and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19
through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted
Edge-triggered mode is recommended when fast interrupts are used. Long interrupts are recommended for
Level-sensitive mode.
2-8
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AC Electrical Characteristics
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued)
220 MHz 240 MHz
Min Max Min Max
No.
Characteristics
Expression
Unit
2. This timing depends on several settings:
For DPLL disable, using internal oscillator (DPLL Control Register (PCTL) Bit 2 = 0) and oscillator disabled during
Stop (PCTL Bit 1 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are
executed. Resetting the Stop delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While
Operating Mode Register Bit 6 = 1 can be set, it is not recommended, and these specifications do not guarantee
timings for that case.
For DPLL disable, using internal oscillator (PCTL Bit 2 = 0) and oscillator enabled during Stop (PCTL Bit 1 = 1), no
stabilization delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored).
For DPLL disable, using external clock (PCTL Bit 2 = 1), no stabilization delay is required and recovery time is
defined by the PCTL Bit 1 and Operating Mode Register Bit 6 settings.
For DPLL enable, if PCTL Bit 1 is 0, the DPLL is shut down during Stop. Recovering from Stop requires the DPLL
to lock. The DPLL lock procedure duration is defined in Table 2-6 and will be refined after silicon characterization.
This procedure is followed by the stop delay counter. Stop recovery ends when the stop delay counter completes
its count.
The DPLT value for DPLL disable is 0.
3. Periodically sampled and not 100 percent tested.
4. For an external clock generator, RESET duration is measured while RESET is asserted, V
is valid, and the
CCQL
EXTAL input is active and valid.
For an internal oscillator, RESET duration is measured while RESET is asserted and V
is valid. The specified
CCQL
timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the
specifications of the crystal and other components connected to the oscillator and reflects worst case conditions.
When the V
is valid, but the other “required RESET duration” conditions (as specified above) have not been
CCQL
yet met, the device circuitry is in an uninitialized state that can result in significant power consumption and
heat-up. Designs should minimize this state to the shortest possible duration.
5. If DPLL does not lose lock.
6.
V
= 3.3 V ± 0.3 V, V
= 1.6 V ± 0.1 V; T = 0°C to +85°C, C = 50 pF.
CCQH
CCQL J L
7. WS = number of wait states (measured in clock cycles, number of T ).
C
8. Use the expression to compute a maximum value.
V
IH
RESET
9
10
8
All Pins
Reset Value
First Fetch
A[0–17]
Figure 2-3. Reset Timing
2-9
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AC Electrical Characteristics
First Interrupt Instruction
A[0–17]
Execution/Fetch
RD
20
WR
21
17
19
IRQA, IRQB,
IRQC, IRQD,
NMI
a) First Interrupt Instruction Execution
General
Purpose
I/O
18
IRQA, IRQB,
IRQC, IRQD,
NMI
b) General-Purpose I/O
Figure 2-4. External Fast Interrupt Timing
IRQA, IRQB,
IRQC, IRQD, NMI
15
IRQA, IRQB,
IRQC, IRQD, NMI
16
Figure 2-5. External Interrupt Timing (Negative Edge-Triggered)
2-10
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AC Electrical Characteristics
V
IH
RESET
13
14
V
V
IH
IH
MODA, MODB,
MODC, MODD,
PINIT
IRQA, IRQB,
IRQC, IRQD, NMI
V
V
IL
IL
Figure 2-6. Operating Mode Select Timing
24
IRQA
25
First Instruction Fetch
A[0–17]
Figure 2-7. Recovery from Stop State Using IRQA
26
IRQA
25
First IRQA Interrupt
Instruction Fetch
A[0–17]
Figure 2-8. Recovery from Stop State Using IRQA Interrupt Service
DMA Source Address
A[0–17]
RD
WR
29
IRQA, IRQB,
IRQC, IRQD,
NMI
First Interrupt Instruction Execution
Figure 2-9. External Memory Access (DMA Source) Timing
2-11
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AC Electrical Characteristics
2.5.5
External Memory Expansion Port (Port A)
2.5.5.1 SRAM Timing
Table 2-8. SRAM Timing
220 MHz
240 MHz
No.
Characteristics
Symbol
Expression1
Unit
Min Max
Min Max
100 Address valid and AA assertion pulse
t
, t
(WS + 2) × T − 4.0
18.8
16.9
ns
ns
RC WC
C
2
width
[3 ≤ WS ≤ 7]
(WS + 3) × T − 4.0
46.0
—
41.9
—
C
[WS ≥ 8]
101 Address and AA valid to WR assertion
102 WR assertion pulse width
t
0.75 × T – 3.0
0.41
2.69
—
—
0.13
2.21
—
—
ns
ns
AS
C
[WS = 3]
1.25 × T – 3.0
C
[WS ≥ 4]
t
WS × T − 4.0
9.65
—
—
8.51
10.6
—
—
ns
ns
WP
C
[WS = 3]
(WS − 0.5) × T − 4.0
11.93
C
[WS ≥ 4]
103 WR deassertion to address not valid
t
1.25 × T − 4.0
[3 ≤ WS ≤ 7]
1.69
6.24
—
—
1.21
6.51
—
—
ns
ns
WR
C
2.25 × T − 4.0
C
[WS ≥ 8]
104 Address and AA valid to input data valid
105 RD assertion to input data valid
t
, t
(WS + 0.75) × T − 5.6
—
—
11.46
8.29
—
—
—
10.04
7.05
—
ns
ns
ns
ns
ns
AA AC
C
[WS ≥ 3]
t
(WS + 0.25) × T − 6.5
OE
C
[WS ≥ 3]
106 RD deassertion to data not valid (data hold
time)
t
0.0
0.0
OHZ
2
107 Address valid to WR deassertion
t
(WS + 0.75) × T − 4.0
13.06
7.11
—
11.64
6.07
—
AW
C
[WS ≥ 3]
108 Data valid to WR deassertion (data setup
time)
t
(t
)
(WS − 0.25) × T − 5.4
—
—
DS DW
C
[WS ≥ 3]
109 Data hold time from WR deassertion
t
1.25 × T − 4.0
[3 ≤ WS ≤ 7]
1.69
6.23
—
—
1.21
5.38
—
—
ns
ns
DH
C
2.25 × T − 4.0
C
[WS ≥ 8]
110 WR assertion to data active
—
—
—
—
0.25 × T − 4.0
C
[WS = 3]
–2.86
—
–2.96
—
ns
–0.25 × T − 4.0
C
[WS ≥ 4]
–5.14
5.69
—
—
–5.04
5.21
—
—
ns
ns
111 WR deassertion to data high impedance
1.25 × T
C
[3 ≤ WS ≤ 7]
2.25 × T
10.24
—
9.38
—
ns
C
[WS ≥ 8]
112 Previous RD deassertion to data active
(write)
2.25 × T − 4.0
6.23
—
—
5.38
9.54
—
—
ns
ns
C
[3 ≤ WS ≤ 7]
3.25 × T − 4.0
10.78
C
[WS ≥ 8]
113 RD deassertion time
1.75 × T − 3.0
4.96
9.51
—
—
4.30
8.47
—
—
ns
ns
C
[3 ≤ WS ≤ 7]
2.75 × T − 3.0
C
[WS ≥ 8]
2-12
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AC Electrical Characteristics
Table 2-8. SRAM Timing (Continued)
220 MHz
240 MHz
No.
Characteristics
Symbol
Expression1
Unit
Min Max
Min Max
4
114 WR deassertion time
—
2.0 × T − 3.0
[3 ≤ WS ≤ 7]
6.1
—
—
5.3
9.5
—
—
ns
ns
C
3.0 × T − 3.0
10.6
C
[WS ≥ 8]
115 Address valid to RD assertion
116 RD assertion pulse width
—
—
0.5 × T − 2.0
0.3
—
—
0.1
—
—
ns
ns
C
(WS + 0.25) × T − 3.0
11.79
10.55
C
[WS ≥ 3]
117 RD deassertion to address not valid
—
1.25 × T − 4.0
[3 ≤ WS ≤ 7]
1.69
6.24
—
—
1.21
5.38
—
—
ns
ns
C
2.25 × T − 4.0
C
[WS ≥ 8]
5
118 TA setup before RD or WR deassertion
119 TA hold after RD or WR deassertion
—
—
0.25 × T + 2.0
3.14
0
—
—
3.04
0
—
—
ns
ns
C
Notes: 1. WS is the number of wait states specified in the BCR. The value is given for the minimum for a given category. (For
example, for a category of [3 ≤ WS ≤ 7] timing is specified for 3 wait states.) Three wait states is the minimum value
otherwise.
2. Timings 100 and 107 are guaranteed by design, not tested.
3. All timings are measured from 0.5 × V
to 0.5 × V
.
CCQH
CCQH
4. The WS number applies to the access in which the deassertion of WR occurs and assumes the next access uses a
minimal number of wait states.
5. Timing 118 is relative to the deassertion edge of RD or WR even if TA remains asserted.
100
A[0–17]
AA[0–3]
117
106
113
116
RD
105
WR
104
118
119
TA
Data
In
D[0–23]
Note: Address lines A[0–17] hold their state after a
read or write operation. AA[0–3] do not hold their
state after a read or write operation.
Figure 2-10. SRAM Read Access
2-13
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AC Electrical Characteristics
100
A[0–17]
AA[0–3]
107
101
102
103
WR
RD
114
119
118
TA
108
109
Data
Out
D[0–23]
Note: Address lines A[0–17] hold their state after a
read or write operation. AA[0–3] do not hold their
state after a read or write operation.
Figure 2-11. SRAM Write Access
2.5.5.2 Asynchronous Bus Arbitration Timings
Table 2-9. Asynchronous Bus Timings
220 MHz
240 MHz
No.
Characteristics
Expression
Unit
Min Max
Min Max
250 BB assertion window from BG input deassertion.
2.5 × Tc + 5
2 × Tc + 5
—
16.4
—
—
15.4
—
ns
ns
251 Delay from BB assertion to BG assertion
14.1
13.3
Notes: 1. Bit 13 in the Operating Mode Register must be set to enable Asynchronous Arbitration mode.
2. At 150 MHz, Asynchronous Arbitration mode is recommended.
3. To guarantee timings 250 and 251, it is recommended that you assert non-overlapping BG inputs to different
DSP56300 devices (on the same bus), as shown in Figure 2-12, where BG1 is the BG signal for one DSP56300
device while BG2 is the BG signal for a second DSP56300 device.
2-14
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AC Electrical Characteristics
BG1
BB
250
BG2
251
250+251
Figure 2-12. Asynchronous Bus Arbitration Timing
The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs.
These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a
result of this delay, a DSP56300 part may assume mastership and assert BB, for some time after BG is
deasserted. This is the reason for timing 250.
Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is
exposed to other DSP56300 components that are potential masters on the same bus. If BG input is
asserted before that time, and BG is asserted and BB is deasserted, another DSP56300 component may
assume mastership at the same time. Therefore, some non-overlap period between one BG input active to
another BG input active is required. Timing 251 ensures that overlaps are avoided.
2-15
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AC Electrical Characteristics
2.5.6
Host Interface Timing
Table 2-10. Host Interface Timings1,2,12
220 MHz
240 MHz
No.
Characteristic10
Expression
Unit
Min Max
Min Max
5
317 Read data strobe assertion width
HACK assertion width
T
+ T
9.05
—
—
—
8.30
4.13
13.7
—
—
—
ns
ns
ns
C
318
5
318 Read data strobe deassertion width
HACK deassertion width
T
318
4.5
5
319 Read data strobe deassertion width after “Last Data Register”
2.5 × T + 3.3
14.7
C
8,11
reads
reads
, or between two consecutive CVR, ICR, or ISR
3
8,11
HACK deassertion width after “Last Data Register” reads
6
320 Write data strobe assertion width
6.0
—
5.5
—
ns
8
321 Write data strobe deassertion width
HACK write deassertion width
•
•
after ICR, CVR and “Last Data Register” writes
2.5 × T + 3.3
14.7
7.5
—
—
13.7
6.88
—
—
ns
ns
C
after IVR writes, or
after TXH:TXM:TXL writes (with HLEND= 0), or
after TXL:TXM:TXH writes (with HLEND = 1)
322 HAS assertion width
4.5
0.0
4.5
—
—
—
4.13
0.0
—
—
—
ns
ns
ns
4
323 HAS deassertion to data strobe assertion
324 Host data input setup time before write data strobe
4.13
6
deassertion
6
325 Host data input hold time after write data strobe deassertion
1.5
1.5
—
—
1.38
1.38
—
—
ns
ns
326 Read data strobe assertion to output data active from high
5
impedance
HACK assertion to output data active from high impedance
5
327 Read data strobe assertion to output data valid
—
—
13.45
4.5
—
—
12.32
4.13
—
ns
ns
ns
HACK assertion to output data valid
5
328 Read data strobe deassertion to output data high impedance
HACK deassertion to output data high impedance
5
329 Output data hold time after read data strobe deassertion
1.5
—
1.38
Output data hold time after HACK deassertion
5
330 HCS assertion to read data strobe deassertion
T
+ T
9.05
4.5
—
—
—
8.30
4.13
—
—
—
ns
ns
ns
ns
ns
C
318
6
331 HCS assertion to write data strobe deassertion
332 HCS assertion to output data valid
11.04
—
10.12
—
4
333 HCS hold time after data strobe deassertion
0.0
2.1
0.0
334 Address (HAD[0–7]) setup time before HAS deassertion
(HMUX=1)
—
1.93
—
335 Address (HAD[0–7]) hold time after HAS deassertion
(HMUX=1)
1.5
—
1.38
—
ns
336 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W setup time
4
before data strobe assertion
•
•
Read
Write
0
2.1
—
—
0
1.93
—
—
ns
ns
2-16
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AC Electrical Characteristics
Table 2-10. Host Interface Timings1,2,12 (Continued)
220 MHz
240 MHz
No.
Characteristic10
Expression
Unit
Min Max
Min Max
337 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W hold time
1.5
7.19
9.47
—
—
1.38
6.81
8.9
—
—
ns
ns
ns
ns
ns
4
after data strobe deassertion
338 Delay from read data strobe deassertion to host request
T + 2.64
C
—
—
5, 7, 8
assertion for “Last Data Register” read
339 Delay from write data strobe deassertion to host request
1.5 × T + 2.64
—
—
C
6, 7, 8
assertion for “Last Data Register” write
340 Delay from data strobe assertion to host request deassertion
11.04
300.0
10.12
300.0
4, 7, 8
for “Last Data Register” read or write (HROD=0)
341 Delay from data strobe assertion to host request deassertion
for “Last Data Register” read or write (HROD=1, open drain
—
—
4, 7, 8, 9
host request)
Notes: 1. See the Programmer’s Model section in the chapter on the HI08 in the DSP56321 User’s Manual.
2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3. This timing is applicable only if two consecutive reads from one of these registers are executed.
4. The data strobe is Host Read (HRD) or Host Write (HWR) in the Dual Data Strobe mode and Host Data Strobe
(HDS) in the Single Data Strobe mode.
5. The read data strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
6. The write data strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
7. The host request is HREQ in the Single Host Request mode and HRRQ and HTRQ in the Double Host Request
mode.
8. The “Last Data Register” is the register at address $7, which is the last location to be read or written in data
transfers. This is RXL/TXL in the Big Endian mode (HLEND = 0; HLEND is the Interface Control Register bit
7—ICR[7]), or RXH/TXH in the Little Endian mode (HLEND = 1).
9. In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the Open-drain mode.
10.
V
= 3.3 V ± 0.3 V, V
= 1.6 V ± 0.1 V; T = 0°C to +85°C, C = 50 pF
CCQH
CCQL J L
11. This timing is applicable only if a read from the “Last Data Register” is followed by a read from the RXL, RXM, or
RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ signal.
12. After the external host writes a new value to the ICR, the HI08 will be ready for operation after three DSP clock
cycles (3 × Tc).
317
318
HACK
328
327
329
326
H[0–7]
HREQ
Figure 2-13. Host Interrupt Vector Register (IVR) Read Timing Diagram
2-17
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AC Electrical Characteristics
HA[2–0]
336
337
333
337
330
HCS
HRW
HDS
336
317
318
328
332
327
319
329
326
341
H[7–0]
338
340
HREQ (single host request)
HRRQ (double host request)
Figure 2-14. Read Timing Diagram, Non-Multiplexed Bus, Single Data Strobe
HA[2–0]
336
337
333
330
HCS
317
HRD
318
328
332
327
319
329
326
341
H[7–0]
338
340
HREQ (single host request)
HRRQ (double host request)
Figure 2-15. Read Timing Diagram, Non-Multiplexed Bus, Double Data Strobe
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AC Electrical Characteristics
HA[2–0]
336
337
333
337
331
HCS
HRW
HDS
336
320
321
325
339
324
H[7–0]
340
341
HREQ (single host request)
HTRQ (double host request)
Figure 2-16. Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe
HA[2–0]
336
337
333
331
HCS
320
HWR
321
324
325
H[7–0]
339
340
341
HREQ (single host request)
HTRQ (double host request)
Figure 2-17. Write Timing Diagram, Non-Multiplexed Bus, Double Data Strobe
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AC Electrical Characteristics
,
HA[10–8]
336
337
322
HAS
323
336
337
HRW
317
HDS
334
318
319
335
327
328
329
HAD[7–0]
Address
Data
326
338
340
341
HREQ (single host request)
HRRQ (double host request)
Figure 2-18. Read Timing Diagram, Multiplexed Bus, Single Data Strobe
HA[10–8]
336
337
322
HAS
323
317
HRD
334
318
319
335
327
328
329
HAD[7–0]
Address
Data
326
338
340
341
HREQ (single host request)
HRRQ (double host request)
Figure 2-19. Read Timing Diagram, Multiplexed Bus, Double Data Strobe
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AC Electrical Characteristics
HA[10–8]
336
337
337
322
HAS
HRW
HDS
323
336
320
334
324
321
325
335
HAD[7–0]
Data
340
Address
339
341
HREQ (single host request)
HTRQ (double host request)
Figure 2-20. Write Timing Diagram, Multiplexed Bus, Single Data Strobe
,
HA[10–8]
336
337
322
HAS
323
320
HWR
334
324
321
325
335
HAD[7–0]
Data
340
Address
339
341
HREQ (single host request)
HTRQ (double host request)
Figure 2-21. Write Timing Diagram, Multiplexed Bus, Double Data Strobe
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AC Electrical Characteristics
2.5.7
SCI Timing
Table 2-11. SCI Timings
220 MHz
240 MHz
No.
Characteristics1
Symbol
Expression
Unit
Min
Max
Min
Max
2
400 Synchronous clock cycle
401 Clock low period
t
16 × T
72.8
26.4
26.4
3.5
—
—
—
—
66.7
23.4
23.4
1.76
—
—
—
—
ns
ns
ns
ns
SCC
C
t
t
/2 − 10.0
/2 − 10.0
SCC
SCC
402 Clock high period
403 Output data setup to clock falling edge
(internal clock)
t
/4 + 0.5 × T −17.0
SCC C
404 Output data hold after clock rising
edge (internal clock)
t
/4 − 0.5 × T
15.9
45.5
—
—
—
14.6
43.8
—
—
—
ns
ns
ns
ns
ns
ns
ns
SCC
C
405 Input data setup time before clock
rising edge (internal clock)
t
/4 + 0.5 × T + 25.0
SCC C
406 Input data not valid before clock rising
edge (internal clock)
t
/4 + 0.5 × T − 5.5
15.0
32.0
—
13.8
32.0
—
SCC
C
407 Clock falling edge to output data valid
(external clock)
—
—
408 Output data hold after clock rising
edge (external clock)
T
+ 8.0
12.6
0.0
9.0
12.2
0.0
9.0
C
409 Input data setup time before clock
rising edge (external clock)
—
—
410 Input data hold time after clock rising
edge (external clock)
—
—
3
411 Asynchronous clock cycle
412 Clock low period
t
64 × T
291.2
135.6
135.6
115.6
—
—
—
—
266.9
123.5
123.5
103.5
—
—
—
—
ns
ns
ns
ns
ACC
C
t
t
t
/2 − 10.0
/2 − 10.0
/2 − 30.0
ACC
ACC
ACC
413 Clock high period
414 Output data setup to clock rising edge
(internal clock)
415 Output data hold after clock rising
edge (internal clock)
t
/2 − 30.0
115.6
—
103.5
—
ns
ACC
Notes: 1.
2.
V
= 3.3 V ± 0.3 V, V
= synchronous clock cycle time (for internal clock, t
= 1.6 V ± 0.1 V; T = 0°C to +85°C, C = 50 pF.
CCQL J L
CCQH
t
is determined by the SCI clock control register and
SCC
SCC
T ).
C
3.
t
= asynchronous clock cycle time; value given for 1X Clock mode (for internal clock, t
is determined by the
ACC
ACC
SCI clock control register and T ).
C
4. In the timing diagrams below, the SCLK is drawn using the clock falling edge as a the first reference. Clock polarity
is programmable in the SCI Control Register (SCR). Refer to the DSP56321 Reference Manual for details.
2-22
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AC Electrical Characteristics
400
402
401
SCLK
(Output)
403
404
Data Valid
405
TXD
RXD
406
Data
Valid
a) Internal Clock
400
402
401
SCLK
(Input)
407
408
TXD
RXD
Data Valid
409
410
Data Valid
b) External Clock
Figure 2-22. SCI Synchronous Mode Timing
411
413
415
412
414
1X SCLK
(Output)
TXD
Data Valid
Figure 2-23. SCI Asynchronous Mode Timing
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AC Electrical Characteristics
2.5.8
ESSI0/ESSI1 Timing
Table 2-12. ESSI Timings
220 MHz 240 MHz
Min Max Min Max
Cond-
ition5
No.
Characteristics4, 6
Symbol Expression
Unit
1
430 Clock cycle
T
T
6 × T
8 × T
27.3
36.4
—
—
25.0
33.3
—
—
x ck
i ck
ns
ns
ECCX
C
C
ECCI
431 Clock high period
•
•
For external clock
For internal clock
T
T
/2 − 10.0 3.7
/2 − 10.0 8.2
—
—
2.5
6.7
—
—
x ck
i ck
ns
ns
ECCX
ECCI
432 Clock low period
•
•
For external clock
For internal clock
T
T
/2 − 10.0 3.7
/2 − 10.0 8.2
—
—
2.5
6.7
—
—
x ck
i ck
ns
ns
ECCX
ECCI
433 RXC rising edge to FSR out (bit-length) high
434 RXC rising edge to FSR out (bit-length) low
435 RXC rising edge to FSR out (word-length-relative)
0.25 × T
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck a
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ECCX
ECCI
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck a
ECCX
0.25 × T
ECCI
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck a
ECCX
2
high
0.25 × T
ECCI
436 RXC rising edge to FSR out (word-length-relative)
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck a
ECCX
2
low
0.25 × T
ECCI
437 RXC rising edge to FSR out (word-length) high
438 RXC rising edge to FSR out (word-length) low
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck a
ECCX
0.25 × T
ECCI
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck a
ECCX
0.25 × T
ECCI
439 Data in setup time before RXC (SCK in
Synchronous mode) falling edge
0.2 × T
5.5
7.3
—
—
5
6.7
—
—
x ck
i ck
ECCX
0.2 × T
ECCI
440 Data in hold time after RXC falling edge
0.15 × T
4.1
5.5
—
—
3.8
5.0
—
—
x ck
i ck
ECCX
0.15 × T
ECCI
2
441 FSR input (bl, wr) high before RXC falling edge
0.2 × T
5.5
7.3
—
—
5
6.7
—
—
x ck
i ck a
ECCX
0.2 × T
ECCI
442 FSR input (wl) high before RXC falling edge
443 FSR input hold time after RXC falling edge
444 Flags input setup before RXC falling edge
445 Flags input hold time after RXC falling edge
446 TXC rising edge to FST out (bit-length) high
447 TXC rising edge to FST out (bit-length) low
448 TXC rising edge to FST out (word-length-relative)
0.2 × T
5.5
7.3
—
—
5
6.7
—
—
x ck
i ck a
ECCX
0.2 × T
ECCI
0.15 × T
4.1
5.5
—
—
3.8
5.0
—
—
x ck
i ck a
ECCX
0.15 × T
ECCI
0.2 × T
5.5
7.3
—
—
5
6.7
—
—
x ck
i ck s
ECCX
0.2 × T
ECCI
0.15 × T
4.1
5.5
—
—
3.8
5.0
—
—
x ck
i ck s
ECCX
0.15 × T
ECCI
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck
ECCX
0.25 × T
ECCI
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck
ECCX
0.25 × T
ECCI
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck
ECCX
2
high
0.25 × T
ECCI
449 TXC rising edge to FST out (word-length-relative)
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck
ECCX
2
low
0.25 × T
ECCI
2-24
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AC Electrical Characteristics
Table 2-12. ESSI Timings (Continued)
220 MHz 240 MHz
Cond-
No.
Characteristics4, 6
Symbol Expression
Unit
ition5
Min Max Min Max
450 TXC rising edge to FST out (word-length) high
0.25 × T
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ECCX
ECCI
451 TXC rising edge to FST out (word-length) low
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck
ECCX
0.25 × T
ECCI
452 TXC rising edge to data out enable from high
impedance
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck
ECCX
0.25 × T
ECCI
453 TXC rising edge to Transmitter #0 drive enable
assertion
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck
ECCX
0.25 × T
ECCI
454 TXC rising edge to data out valid
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck
ECCX
0.25 × T
ECCI
3
455 TXC rising edge to data out high impedance
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck
ECCX
0.25 × T
ECCI
456 TXC rising edge to Transmitter #0 drive enable
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck
ECCX
3
deassertion
0.25 × T
ECCI
457 FST input (bl, wr) setup time before TXC falling
0.2 × T
5.5
7.3
—
—
5
6.7
—
—
x ck
i ck
ECCX
2
edge
0.2 × T
ECCI
458 FST input (wl) to data out enable from high
impedance
TBD
—
TBD
—
TBD
—
459 FST input (wl) to Transmitter #0 drive enable
assertion
TBD
—
TBD
—
TBD
—
460 FST input (wl) setup time before TXC falling edge
461 FST input hold time after TXC falling edge
462 Flag output valid after TXC rising edge
0.2 × T
5.5
7.3
—
—
5
6.7
—
—
x ck
i ck
ECCX
0.2 × T
ECCI
0.15 × T
4.1
5.5
—
—
3.8
5.0
—
—
x ck
i ck
ECCX
0.15 × T
ECCI
0.25 × T
—
—
6.8
9.1
—
—
6.3
8.3
x ck
i ck
ECCX
0.25 × T
ECCI
Notes: 1. For the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in Table 2-5 on page
2-5) and the ESSI control register. T must be ≥ T × 3, in accordance with the note below Table 7-1 in the
ECCX
C
DSP56321 Reference Manual. T
must be ≥ T × 4, in accordance with the explanation of CRA[PSR] and the
ECCI
C
ESSI Clock Generator Functional Block Diagram shown in Figure 7-3 of the DSP56321 Reference Manual.
2. The word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal
waveform, but spreads from one serial clock before the first bit clock (same as the Bit Length Frame Sync signal)
until the one before last bit clock of the first word in the frame.
3. Periodically sampled and not 100 percent tested
4.
V
= 3.3 V ± 0.3 V, V
= 1.6 V ± 0.1 V; T = 0°C to +85°C, C = 50 pF
CCQH
CCQL J L
5. TXC (SCK Pin) = Transmit Clock
RXC (SC0 or SCK Pin) = Receive Clock
FST (SC2 Pin) = Transmit Frame Sync
FSR (SC1 or SC2 Pin) Receive Frame Sync
6. i ck = Internal Clock; x ck = External Clock
i ck a = Internal Clock, Asynchronous Mode (asynchronous implies that TXC and RXC are two different clocks)
i ck s = Internal Clock, Synchronous Mode (synchronous implies that TXC and RXC are the same clock)
7. In the timing diagrams below, the clocks and frame sync signals are drawn using the clock falling edge as a the first
reference. Clock and frame sync polarities are programmable in Control Register B (CRB). Refer to the DSP56321
Reference Manual for details.
2-25
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AC Electrical Characteristics
430
431
432
TXC
(Input/
Output)
446
447
FST (Bit)
Out
450
451
FST (Word)
Out
454
452
454
455
First Bit
Last Bit
Data Out
459
Transmitter
#0 Drive
Enable
457
453
456
461
FST (Bit) In
458
461
460
FST (Word)
In
462
See Note
Flags Out
Note:
In Network mode, output flag transitions can occur at the start of each time slot within the frame. In
Normal mode, the output flag state is asserted for the entire frame period.
Figure 2-24. ESSI Transmitter Timing
2-26
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AC Electrical Characteristics
430
431
RXC
432
(Input/
Output)
433
434
FSR (Bit)
Out
437
438
FSR
(Word)
Out
440
439
Last Bit
First Bit
Data In
443
441
FSR (Bit)
In
443
445
442
FSR
(Word)
In
444
Flags In
Figure 2-25. ESSI Receiver Timing
2-27
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AC Electrical Characteristics
2.5.9
Timer Timing
Table 2-13. Timer Timings
220 MHz
240 MHz
No.
Characteristics
Expression
Unit
Min
Max
Min
Max
480
481
486
2 × T + 2.0
11.1
11.0
—
—
—
10.3
10.3
—
—
—
ns
ns
ns
TIO Low
C
TIO High
2 × T + 2.0
C
Synchronous delay time from Timer input
rising edge to the external memory address
out valid caused by the first interrupt
instruction execution
10.25 × T + 10.0
56.64
52.74
C
Notes: 1.
V
= 3.3 V ± 0.3 V, V
= 1.6 V ± 0.1 V; T = 0°C to +85°C, C = 50 pF
CCQL J L
CCQH
2. The maximum frequency of pulses generated by a timer will be defined after device characterization is
completed.
3. In the timing diagrams below, TIO is drawn using the rising edge as the reference. TIO polarity is programmable
in the Timer Control/Status Register (TCSR). Refer to the DSP56321 Reference Manual for details.
TIO
480
481
Figure 2-26. TIO Timer Event Input Restrictions
TIO (Input)
Address
486
First Interrupt Instruction Execution
Figure 2-27. Timer Interrupt Generation
2-28
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AC Electrical Characteristics
2.5.10 CONSIDERATIONS FOR GPIO USE
The following considerations can be helpful when GPIO is used.
2.5.10.1 GPIO as Output
• The time from fetch of the instruction that changes the GPIO pin to the actual change is seven core
clock cycles, if the instruction is a one-cycle instruction and there are no pipeline stalls or any other
pipeline delays.
• The maximum rise or fall time of a GPIO pin is 13 ns (TTL levels, assuming that the maximum of 50
pF load limit is met).
2.5.10.2 GPIO as Input
GPIO inputs are not synchronized with the core clock. When only one GPIO bit is polled, this lack of
synchronization presents no problem, since the read value can be either the previous value or the new
value of the corresponding GPIO pin. However, there is the risk of reading an intermediate state if:
• Two or more GPIO bits are treated as a coupled group (for example, four possible status states encoded
in two bits).
• The read operation occurs during a simultaneous change of GPIO pins (for example, the change of 00
to 11 may happen through an intermediate state of 01 or 10).
Therefore, when GPIO bits are read, the recommended practice is to poll continuously until two
consecutive read operations have identical results.
2-29
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AC Electrical Characteristics
2.5.11 JTAG Timing
Table 2-14. JTAG Timing
All frequencies
No.
Characteristics
Unit
Min
Max
500
501
502
503
504
505
506
507
508
509
510
511
512
513
TCK frequency of operation
TCK cycle time in Crystal mode
TCK clock pulse width measured at 1.6 V
TCK rise and fall times
0.0
45.0
20.0
0.0
22.0
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
3.0
—
Boundary scan input data setup time
Boundary scan input data hold time
TCK low to output data valid
TCK low to output high impedance
TMS, TDI data setup time
5.0
24.0
0.0
—
40.0
40.0
—
0.0
5.0
TMS, TDI data hold time
25.0
0.0
—
TCK low to TDO data valid
44.0
44.0
—
TCK low to TDO high impedance
TRST assert time
0.0
100.0
40.0
TRST setup time to TCK low
—
Notes: 1.
V
= 3.3 V ± 0.3 V, V
= 1.6 V ± 0.1 V; T = 0°C to +85°C, C = 50 pF
CCQL J L
CCQH
2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
501
502
502
V
M
V
V
M
TCK
(Input)
IH
V
IL
503
503
Figure 2-28. Test Clock Input Timing Diagram
2-30
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AC Electrical Characteristics
V
TCK
(Input)
IH
V
IL
504
505
Data
Inputs
Input Data Valid
506
507
506
Data
Outputs
Output Data Valid
Data
Outputs
Data
Outputs
Output Data Valid
Figure 2-29. Boundary Scan (JTAG) Timing Diagram
V
IH
TCK
(Input)
V
IL
509
508
Input Data Valid
TDI
TMS
(Input)
510
TDO
(Output)
Output Data Valid
511
TDO
(Output)
510
TDO
(Output)
Output Data Valid
Figure 2-30. Test Access Port Timing Diagram
TCK
(Input)
513
TRST
(Input)
512
Figure 2-31. TRST Timing Diagram
2-31
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AC Electrical Characteristics
2.5.12 OnCE Module TimIng
Table 2-15. OnCE Module Timing
All
Frequencies
No.
Characteristics
Expression
Unit
Min
Max
500 TCK frequency of operation
Max 22.0 MHz
1.5 × T + 10.0
0.0
20.0
—
22.0
—
MHz
ns
514 DE assertion time in order to enter Debug mode
C
515 Response time when DSP56321T is executing NOP
instructions from internal memory
5.5 × T + 30.0
67.0
ns
C
516 Debug acknowledge assertion time
3 × T + 5.0
25.0
—
ns
C
Note:
V
= 3.3 V ± 0.3 V, V
= 1.6 V ± 0.1 V; T = 0°C to +85°C, C = 50 pF
CCQH
CCQL J L
DE
514
515
516
Figure 2-32. OnCE—Debug Request
2-32
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Chapter 3
Packaging
3.1 Pin-Out and Package Information
This section includes diagrams of the DSP56321T package pin-outs and tables showing how the
signals described in Chapter 1 are allocated for the package. The DSP56321T is available in a
196-pin Flip Chip-Plastic Ball Grid Array (FC-PBGA) package.
3-1
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FC-PBGA Package Description
3.2 FC-PBGA Package Description
Top and bottom views of the FC-PBGA package are shown in Figure 3-1 and Figure 3-2 with their
pin-outs.
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
NC
SC11
SC12
STD1
SC01
TMS
TDO
IRQB
D23
V
D19
D17
D16
D14
D11
D9
D7
NC
CCD
SRD1
SC02
PINIT
STD0
RXD
TDI
TCK
DE
TRST IRQD
IRQA IRQC
D21
D22
D20
D15
D13
D12
D10
D8
D6
D5
D3
NC
V
D18
V
V
D4
C
CCQL
CCD
CCD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
EXTAL
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
GND
D1
D2
V
D
E
F
CCD
D0
V
SRD0
SC00
TXD
SCK0
HDS
TIO2
TIO0
HA0
H4
GND
GND
GND
GND
GND
GND
GND
Res’d
GND
GND
GND
GND
GND
GND
GND
WR
BR
A17
A16
A14
CCS
SC10
V
A15
A12
A11
A9
CCQH
A13
G
SCK1
SCLK
V
CCQL
A10
V
V
V
H
J
CCQH
CCQL
CCA
HACK
HRW
A8
A7
A5
K
V
HREQ
TIO1
HA2
H7
V
A6
CCS
CCA
HCS
HA1
H6
V
A3
A4
L
CCA
M
V
V
V
RD
A1
A2
CCH
H2
CCQL
CCQH
N
P
RESET GND
AA3
V
Res’d
TA
V
AA0
BG
A0
CCQL
CCC
NC
H5
H3
H1
NC
GND
AA2
XTAL
V
BB
AA1
NC
CCC
Figure 3-1. DSP56321T FC-PBGA Package, Top View
3-2
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FC-PBGA Package Description
Bottom View
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
NC
D7
D9
D11
D14
D16
D19
V
D23
IRQB
TDO
TMS
SC11
NC
CCD
NC
D4
D5
D3
D8
D6
D10
D13
D12
D15
D17
D18
D20
D21
D22
IRQD TRST
IRQC IRQA
TDI
TCK
DE
SC12
STD1
SC01
SRD1
SC02
PINIT
STD0
RXD
V
V
V
CCQL
C
CCD
CCD
V
D2
D1
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
EXTAL
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H0
GND
GND
GND
GND
GND
GND
GND
GND
D
E
F
CCD
D0
A16
A14
A17
GND
GND
GND
GND
GND
GND
GND
WR
BR
GND
GND
GND
GND
GND
GND
GND
Res’d
SRD0
SC00
TXD
SCK0
HDS
TIO2
TIO0
HA0
H4
V
CCS
A15
A12
A11
A9
V
SC10
SCLK
CCQH
G
V
A13
SCK1
CCQL
A10
V
V
V
CCQH
H
J
CCA
A8
CCQL
A7
A5
HRW
HACK
K
A6
V
HREQ
TIO1
HA2
H7
V
CCS
CCA
CCA
A4
A3
V
HCS
HA1
H6
L
M
A2
A1
RD
V
V
V
CCQH
CCQL
CCH
H2
N
P
A0
AA0
BG
V
V
AA3
GND
RESET
NC
Res’d
TA
CCC
CCQL
NC
AA1
BB
V
XTAL
AA2
GND
H1
H3
H5
NC
CCC
Figure 3-2. DSP56321T FC-PBGA Package, Bottom View
3-3
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FC-PBGA Package Description
Table 3-1. Signal List by Ball Number
Ball
No.
Ball
No.
Ball
No.
Signal Name
Signal Name
Signal Name
A1
Not Connected (NC),
reserved
B12 D8
D9
GND
A2
A3
A4
A5
A6
A7
A8
A9
SC11 or PD1
TMS
B13 D5
B14 NC
D10 GND
D11 GND
D12 D1
TDO
C1
C2
C3
C4
C5
C6
C7
C8
C9
SC02 or PC2
STD1 or PD5
MODB/IRQB
D23
D13 D2
TCK
D14
E1
E2
E3
E4
E5
E6
E7
E8
E9
V
CCD
V
MODA/IRQA
MODC/IRQC
D22
STD0 or PC5
CCD
D19
D16
V
CCS
SRD0 or PC4
GND
A10 D14
A11 D11
A12 D9
A13 D7
A14 NC
V
CCQL
D18
GND
V
GND
CCD
C10 D12
C11
GND
V
GND
CCD
B1
B2
B3
B4
B5
B6
B7
B8
B9
SRD1 or PD4
C12 D6
C13 D3
C14 D4
GND
SC12 or PD2
TDI
E10 GND
E11 GND
E12 A17
E13 A16
E14 D0
TRST
D1
D2
D3
D4
D5
D6
D7
D8
PINIT/NMI
MODD/IRQD
D21
SC01 or PC1
DE
D20
GND
F1
F2
F3
F4
F5
RXD or PE0
D17
GND
SC10 or PD0
SC00 or PC0
GND
D15
GND
B10 D13
B11 D10
GND
GND
GND
3-4
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FC-PBGA Package Description
Table 3-1. Signal List by Ball Number (Continued)
Ball
No.
Ball
No.
Ball
No.
Signal Name
Signal Name
Signal Name
F6
F7
F8
GND
GND
GND
H3
H4
H5
SCK0 or PC3
J14
K1
A9
GND
GND
V
CCS
K2
HREQ/HREQ,
HTRQ/HTRQ, or PB14
F9
GND
H6
H7
H8
H9
GND
GND
GND
GND
K3
K4
K5
K6
K7
K8
K9
TIO2
GND
GND
GND
GND
GND
GND
F10 GND
F11 GND
F12
V
CCQH
F13 A14
F14 A15
H10 GND
H11 GND
G1
G2
G3
G4
SCK1 or PD3
SCLK or PE2
H12
V
CCA
H13 A10
H14 A11
K10 GND
K11 GND
TXD or PE1
GND
J1
HACK/HACK,
K12
V
CCA
HRRQ/HRRQ, or PB15
G5
G6
GND
GND
J2
J3
HRW, HRD/HRD, or PB11
K13 A5
K14 A6
HDS/HDS, HWR/HWR, or
PB12
G7
G8
G9
GND
GND
GND
J4
J5
GND
GND
GND
GND
GND
GND
GND
GND
A8
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
HCS/HCS, HA10, or PB13
TIO1
TIO0
GND
GND
GND
GND
GND
GND
GND
J6
G10 GND
G11 GND
G12 A13
J7
J8
J9
G13
V
J10
J11
J12
J13
CCQL
G14 A12
H1
H2
V
V
CCQH
A7
CCQL
3-5
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FC-PBGA Package Description
Table 3-1. Signal List by Ball Number (Continued)
Ball
No.
Ball
No.
Ball
No.
Signal Name
Signal Name
Signal Name
L11
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
GND
M13 A1
M14 A2
P1
P2
P3
P4
P5
P6
P7
P8
P9
NC
V
H5, HAD5, or PB5
CCA
A3
A4
N1
N2
N3
N4
N5
N6
N7
N8
N9
H6, HAD6, or PB6
H7, HAD7, or PB7
H3, HAD3, or PB3
H1, HAD1, or PB1
HA1, HA8, or PB9
H4, HAD4, or PB4
NC
HA2, HA9, or PB10
HA0, HAS/HAS, or PB8
H2, HAD2, or PB2
GND
AA2
XTAL
RESET
GND
AA3
V
CCH
H0, HAD0, or PB0
V
CCC
V
V
NC
P10 TA
P11 BB
P12 AA1
P13 BG
P14 NC
CCQL
CCQH
V
CCQL
EXTAL
N10 Reserved
N11 BR
Reserved
M10 NC
M11 WR
M12 RD
N12
V
CCC
N13 AA0
N14 A0
Note:
Signal names are based on configured functionality. Most connections supply a single signal. Some
connections provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating
mode after RESET is deasserted but act as interrupt lines during operation. Some signals have
configurable polarity; these names are shown with and without overbars, such as HAS/HAS. Some
connections have two or more configurable functions; names assigned to these connections indicate the
function for a specific configuration. For example, connection N2 is data line H7 in non-multiplexed bus
mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is
enabled for this pin. Unlike the TQFP package, most of the GND pins are connected internally in the center
of the connection array and act as heat sink for the chip. Therefore, except for GND and GND that
P
P1
support the PLL, other GND signals do not support individual subsystems in the chip.
3-6
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FC-PBGA Package Description
Table 3-2. Signal List by Signal Name
Ball
No.
Ball
No.
Ball
No.
Signal Name
Signal Name
Signal Name
A0
A1
N14
M13
H13
H14
G14
G12
F13
F14
E13
E12
M14
L13
L14
K13
K14
J13
J12
J14
N13
P12
P7
BR
D0
N10
E14
D12
B11
A11
C10
B10
A10
B9
D9
DE
A12
D3
M8
D4
D5
D6
D7
D8
D9
D10
D11
E4
A10
A11
A12
A13
A14
A15
A16
A17
A2
D1
EXTAL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D2
A9
B8
A3
C8
A4
A8
E5
A5
D13
B7
E6
A6
D20
D21
D22
D23
D3
E7
A7
B6
E8
A8
C6
E9
A9
A6
E10
E11
F4
AA0
AA1
AA2
AA3
BB
C13
C14
B13
C12
A13
B12
D4
D5
F5
N7
D6
F6
P11
P13
D7
F7
BG
D8
F8
3-7
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FC-PBGA Package Description
Table 3-2. Signal List by Signal Name (Continued)
Ball
No.
Ball
No.
Ball
No.
Signal Name
Signal Name
Signal Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
F9
F10
F11
G4
G5
G6
G7
G8
G9
G10
G11
H4
H5
H6
H7
H8
H9
H10
H11
J4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H0
K4
K5
K6
K7
K8
K9
K10
K11
L4
HA1
HA10
M1
L1
HA2
M2
M1
M2
J1
HA8
HA9
HACK/HACK
HAD0
M5
P4
N4
P3
N3
P2
N1
N2
M3
L1
HAD1
HAD2
L5
HAD3
L6
HAD4
L7
HAD5
L8
HAD6
L9
HAD7
L10
L11
N6
P6
M5
P4
N4
P3
N3
P2
N2
N2
M3
HAS/HAS
HCS/HCS
HDS/HDS
HRD/HRD
HREQ/HREQ
HRRQ/HRRQ
HRW
J3
J2
K2
J1
H1
J5
H2
J2
J6
H3
HTRQ/HTRQ
HWR/HWR
IRQA
K2
J3
J7
H4
J8
H5
C4
A5
C5
B5
J9
H6
IRQB
J10
J11
H7
IRQC
HA0
IRQD
3-8
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FC-PBGA Package Description
Table 3-2. Signal List by Signal Name (Continued)
Ball
No.
Ball
No.
Ball
No.
Signal Name
Signal Name
Signal Name
MODA
MODB
MODC
MODD
NC
C4
A5
C5
B5
A1
A14
B14
M10
N8
P1
P5
P14
D1
M5
P4
M2
J2
PC3
PC4
H3
E3
E1
P5
F2
TA
P10
C3
TCK
TDI
PC5
B3
PCAP
PD0
TDO
TIO0
TIO1
TIO2
TMS
TRST
TXD
A4
L3
NC
PD1
A2
B2
G1
B1
C2
F1
L2
NC
PD2
K3
NC
PD3
A3
NC
PD4
B4
NC
PD5
G3
H12
K12
L12
N12
P9
NC
PE0
V
V
V
V
V
V
V
V
V
V
CCA
CCA
CCA
CCC
CCC
CCD
CCD
CCD
CCD
CCH
NC
PE1
G3
G2
D1
M12
M9
N10
N5
F1
NMI
PE2
PB0
PB1
PB10
PB11
PB12
PB13
PB14
PB15
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PC0
PC1
PC2
PINIT
RD
Reserved
Reserved
RESET
RXD
A7
C9
J3
C11
D14
M4
F12
H1
L1
K2
J1
SC00
SC01
SC02
SC10
SC11
SC12
SCK0
SCK1
SCLK
SRD0
SRD1
STD0
STD1
F3
D2
C1
F2
V
V
V
CCQH
CCQH
CCQH
N4
P3
N3
P2
N1
N2
M3
M1
F3
M7
C7
A2
B2
H3
G1
G2
E3
B1
E1
C2
V
V
V
V
V
CCQL
CCQL
CCQL
CCQL
CCQL
G13
H2
M6
N9
V
E2
CCS
CCS
V
K1
D2
C1
WR
M11
P8
XTAL
3-9
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FC-PBGA Package Mechanical Drawing
3.3 FC-PBGA Package Mechanical Drawing
NOTES:
Millimeters
1. DIMENSIONS IN MILLIMETERS.
MIN
MAX
DIM
A
A1
A2
—
0.27
0.74
2.43
0.47
1.04
0.92
0.55
2. DIMENSIONS AND TOLERANCING PER ASME
Y14.5, 1994.
A3 0.80
3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.
b
D
D1
D2
e
E
E1
E2
0.45
15 BSC
13 REF
9.3
4. DATUM A THE SEATING PLANE IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
—
1 BSC
15 BSC
13 REF
CASE 1128F-01
ISSUE A
5. D2 AND E2 DEFINE THE AREA OCCUPIED BY THE
DIE.
5
—
DATE: 06/08/01
Figure 3-3. DSP56321T Mechanical Information, 196-pin FC-PBGA Package
3-10
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Chapter 4
Design
Considerations
4.1 Thermal Design Considerations
An estimate of the chip junction temperature, TJ, in °C can be obtained from
this equation:
Equation 1: TJ = TA + (PD × RθJA
)
Where:
TA
=
=
=
ambient temperature °C
RθJA
PD
package junction-to-ambient thermal resistance °C/W
power dissipation in package
Historically, thermal resistance has been expressed as the sum of a
junction-to-case thermal resistance and a case-to-ambient thermal resistance,
as in this equation:
Equation 2: RθJA = RθJC + RθCA
Where:
RθJA
RθJC
RθCA
=
=
=
package junction-to-ambient thermal resistance °C/W
package junction-to-case thermal resistance °C/W
package case-to-ambient thermal resistance °C/W
R
θJC is device-related and cannot be influenced by the user. The user controls
the thermal environment to change the case-to-ambient thermal resistance,
θCA. For example, the user can change the air flow around the device, add a
R
heat sink, change the mounting arrangement on the printed circuit board
(PCB) or otherwise change the thermal dissipation capability of the area
surrounding the device on a PCB. This model is most useful for ceramic
packages with heat sinks; some 90 percent of the heat flow is dissipated
through the case to the heat sink and out to the ambient environment. For
ceramic packages, in situations where the heat flow is split between a path to
the case and an alternate path through the PCB, analysis of the device thermal
performance may need the additional modeling capability of a system-level
thermal simulation tool.
The thermal performance of plastic packages is more dependent on the
temperature of the PCB to which the package is mounted. Again, if the
estimates obtained from RθJA do not satisfactorily answer whether the thermal
performance is adequate, a system-level model may be appropriate.
4-1
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Electrical Design Considerations
A complicating factor is the existence of three common ways to determine the junction-to-case thermal
resistance in plastic packages.
• To minimize temperature variation across the surface, the thermal resistance is measured from the
junction to the outside surface of the package (case) closest to the chip mounting area when that surface
has a proper heat sink.
• To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance
is measured from the junction to the point at which the leads attach to the case.
• If the temperature of the package case (TT) is determined by a thermocouple, thermal resistance is
computed from the value obtained by the equation (TJ – TT)/PD.
As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using
the first definition. From a practical standpoint, that value is also suitable to determine the junction
temperature from a case thermocouple reading in forced convection environments. In natural convection,
the use of the junction-to-case thermal resistance to estimate junction temperature from a thermocouple
reading on the case of the package will yield an estimate of a junction temperature slightly higher than
actual temperature. Hence, the new thermal metric, thermal characterization parameter or ΨJT, has been
defined to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature in natural
convection when the surface temperature of the package is used. Remember that surface temperature
readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the
surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a
40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
4.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to
guard against damage due to high static
voltage or electrical fields. However, normal
precautions are advised to avoid application
of any voltages higher than maximum rated
voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage
level (for example, either GND or V ).
CC
Use the following list of recommendations to ensure correct DSP operation.
• Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the
board ground to each GND pin.
• Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of the
package to connect the VCC power source to GND.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND
pins are less than 0.5 inch per capacitor lead.
• Use at least a four-layer PCB with two inner layers for VCC and GND.
4-2
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Power Consumption Considerations
• Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.
This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB,
IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order of 6 inches are recommended.
• Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate
capacitance. This is especially critical in systems with higher capacitive loads that could create higher
transient currents in the VCC and GND circuits.
• All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins
with internal pull-up resistors (TRST, TMS, DE).
• Take special care to minimize noise levels on the VCCP, GNDP, and GNDP1 pins.
• The following pins must be asserted during power-up: RESET and TRST. A stable EXTAL signal
should be supplied before deassertion of RESET. If the VCC reaches the required level before EXTAL
is stable or other “required RESET duration” conditions are met (see Table 2-7), the device circuitry
can be in an uninitialized state that may result in significant power consumption and heat-up. Designs
should minimize this condition to the shortest possible duration.
• Ensure that during power-up, and throughout the DSP56321 operation, VCCQH is always higher or
equal to the VCC voltage level.
• If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies
due to synchronous operation of the devices.
• The Port A data bus (D[0–23]), HI08, ESSI0, ESSI1, SCI, and timers all use internal keepers to
maintain the last output value even when the internal signal is tri-stated. Typically, no pull-up or
pull-down resistors should be used with these signal lines. However, if the DSP is connected to a
device that requires pull-up resistors (such as an MPC8260), the recommended resistor value is 10 KΩ
or less. If more than one DSP must be connected in parallel to the other device, the pull-up resistor
value requirement changes as follows:
— 2 DSPs = 5 KΩ (mask sets 0K91M and 1K91M)/7 KΩ (mask set 0K93M) or less
— 3 DSPs = 3 KΩ (mask sets 0K91M and 1K91M)/4 KΩ (mask set 0K93M) or less
— 4 DSPs = 2 KΩ (mask sets 0K91M and 1K91M)/3 KΩ (mask set 0K93M) or less
— 5 DSPs = 1.5 KΩ (mask sets 0K91M and 1K91M)/2 KΩ (mask set 0K93M) or less
— 6 DSPs = 1 KΩ (mask sets 0K91M and 1K91M)/1.5 KΩ (mask set 0K93M) or less
4.3 Power Consumption Considerations
Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current
consumption are described in this section. Most of the current consumed by CMOS devices is alternating
current (ac), which is charging and discharging the capacitances of the pins and internal nodes.
Current consumption is described by this formula:
Equation 3: I = C × V × f
Where:
C
V
f
=
=
=
node/pin capacitance
voltage swing
frequency of node/pin toggle
Example 4-1. Current Consumption
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its
maximum possible rate (33 MHz), the current consumption is expressed in Equation 4.
Equation 4: I = 50 × 10–12 × 3.3 × 33 × 106 = 5.48 mA
4-3
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Input (EXTAL) Jitter Requirements
The maximum internal current (ICCImax) value reflects the typical possible switching of the internal
buses on best-case operation conditions—not necessarily a real application case. The typical internal
current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions.
Perform the following steps for applications that require very low current consumption:
1.
2.
3.
4.
5.
6.
7.
Set the EBD bit when you are not accessing external memory.
Minimize external memory accesses, and use internal memory accesses.
Minimize the number of pins that are switching.
Minimize the capacitive load on the pins.
Connect the unused inputs to pull-up or pull-down resistors.
Disable unused peripherals.
Disable unused pin activity (for example, CLKOUT, XTAL).
One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to
minimize specific board effects (that is, to compensate for measured board current not caused by the
DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm,
specific test current measurements, and the following equation to derive the current-per-MIPS value.
Equation 5: I ⁄ MIPS = I ⁄ MHz = (ItypF2 – ItypF1) ⁄ (F2 – F1)
Where:
ItypF2
ItypF1
=
=
current at F2
current at F1
F2
F1
=
=
high frequency (any specified operating frequency)
low frequency (any specified operating frequency lower than F2)
Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33
MHz. The degree of difference between F1 and F2 determines the amount of precision with
which the current rating can be determined for an application.
4.4 Input (EXTAL) Jitter Requirements
The allowed jitter on the frequency of EXTAL is 0.5 percent. If the rate of change of the frequency of
EXTAL is slow (that is, it does not jump between the minimum and maximum values in one cycle) or the
frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the allowed
jitter can be 2 percent. The phase and frequency jitter performance results are valid only if the input jitter
is less than the prescribed values.
4-4
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Appendix A
Power
Consumption
Benchmark
The following benchmark program evaluates DSP56321T power use in a test situation. It enables the
PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of
synthetic DSP application data to emulate intensive sustained DSP operation.
;**************************************************************************
;**************************************************************************
;*
*
*
*
;* CHECKS
;*
Typical Power Consumption
;**************************************************************************
page
nolist
200,55,0,0,0
I_VEC EQU $000000; Interrupt vectors for program debug only
START EQU $8000; MAIN (external) program starting address
INT_PROG EQU $100 ; INTERNAL program memory starting address
INT_XDAT EQU $0; INTERNAL X-data memory starting address
INT_YDAT EQU $0; INTERNAL Y-data memory starting address
INCLUDE "ioequ.asm"
INCLUDE "intequ.asm"
list
org
P:START
;
movep #$0243FF,x:M_BCR ;; BCR: Area 3 = 2 w.s (SRAM)
; Default: 2w.s (SRAM)
;
movep
#$0d0000,x:M_PCTL
; XTAL disable
; PLL enable
; CLKOUT disable
;
; Load the program
;
move
move
do
move
move
nop
#INT_PROG,r0
#PROG_START,r1
#(PROG_END-PROG_START),PLOAD_LOOP
p:(r1)+,x0
x0,p:(r0)+
PLOAD_LOOP
;
; Load the X-data
;
move
move
do
move
move
#INT_XDAT,r0
#XDAT_START,r1
#(XDAT_END-XDAT_START),XLOAD_LOOP
p:(r1)+,x0
x0,x:(r0)+
XLOAD_LOOP
;
; Load the Y-data
;
move
move
do
move
move
#INT_YDAT,r0
#YDAT_START,r1
#(YDAT_END-YDAT_START),YLOAD_LOOP
p:(r1)+,x0
x0,y:(r0)+
YLOAD_LOOP
;
jmp
PROG_START
INT_PROG
move
#$0,r0
#$0,r4
#$3f,m0
#$3f,m4
move
move
move
;
clr
a
A-1
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Power Consumption Benchmark
clr
b
move
move
move
move
bset
#$0,x0
#$0,x1
#$0,y0
#$0,y1
#4,omr
; ebd
;
sbr
dor
mac
mac
add
mac
mac
move
#60,_end
x0,y0,ax:(r0)+,x1
x1,y1,ax:(r0)+,x0
a,b
x0,y0,ax:(r0)+,x1
x1,y1,a
y:(r4)+,y1
y:(r4)+,y0
y:(r4)+,y0
b1,x:$ff
_end
bra
nop
nop
nop
nop
sbr
PROG_END
nop
nop
XDAT_START
;
org
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
x:0
$262EB9
$86F2FE
$E56A5F
$616CAC
$8FFD75
$9210A
$A06D7B
$CEA798
$8DFBF1
$A063D6
$6C6657
$C2A544
$A3662D
$A4E762
$84F0F3
$E6F1B0
$B3829
$8BF7AE
$63A94F
$EF78DC
$242DE5
$A3E0BA
$EBAB6B
$8726C8
$CA361
$2F6E86
$A57347
$4BE774
$8F349D
$A1ED12
$4BFCE3
$EA26E0
$CD7D99
$4BA85E
$27A43F
$A8B10C
$D3A55
$25EC6A
$2A255B
$A5F1F8
$2426D1
$AE6536
$CBBC37
$6235A4
$37F0D
$63BEC2
$A5E4D3
$8CE810
$3FF09
$60E50E
$CFFB2F
$40753C
$8262C5
$CA641A
A-2
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Power Consumption Benchmark
dc
$EB3B4B
$2DA928
$AB6641
$28A7E6
$4E2127
$482FD4
$7257D
dc
dc
dc
dc
dc
dc
dc
dc
dc
$E53C72
$1A8C3
$E27540
XDAT_END
YDAT_START
;
org
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
y:0
$5B6DA
$C3F70B
$6A39E8
$81E801
$C666A6
$46F8E7
$AAEC94
$24233D
$802732
$2E3C83
$A43E00
$C2B639
$85A47E
$ABFDDF
$F3A2C
$2D7CF5
$E16A8A
$ECB8FB
$4BED18
$43F371
$83A556
$E1E9D7
$ACA2C4
$8135AD
$2CE0E2
$8F2C73
$432730
$A87FA9
$4A292E
$A63CCF
$6BA65C
$E06D65
$1AA3A
$A1B6EB
$48AC48
$EF7AE1
$6E3006
$62F6C7
$6064F4
$87E41D
$CB2692
$2C3863
$C6BC60
$43A519
$6139DE
$ADF7BF
$4B3E8C
$6079D5
$E0F5EA
$8230DB
$A3B778
$2BFE51
$E0A6B6
$68FFB7
$28F324
$8F2E8D
$667842
$83E053
$A1FD90
$6B2689
$85B68E
$622EAF
$6162BC
$E4A245
YDAT_END
;**************************************************************************
A-3
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Go to: www.freescale.com
Freescale Semiconductor, Inc.
Power Consumption Benchmark
;
;
;
;
;
EQUATES for DSP56321 I/O registers and ports
Last update: June 11 1995
;**************************************************************************
page
opt
132,55,0,0,0
mex
ioequ
ident
1,0
;------------------------------------------------------------------------
;
;
;
EQUATES for I/O Port Programming
;------------------------------------------------------------------------
;
Register Addresses
M_HDR EQU $FFFFC9
M_HDDR EQU $FFFFC8
M_PCRC EQU $FFFFBF
M_PRRC EQU $FFFFBE
M_PDRC EQU $FFFFBD
M_PCRD EQU $FFFFAF
M_PRRD EQU $FFFFAE
M_PDRD EQU $FFFFAD
M_PCRE EQU $FFFF9F
M_PRRE EQU $FFFF9E
M_PDRE EQU $FFFF9D
M_OGDB EQU $FFFFFC
; Host port GPIO data Register
; Host port GPIO direction Register
; Port C Control Register
; Port C Direction Register
; Port C GPIO Data Register
; Port D Control register
; Port D Direction Data Register
; Port D GPIO Data Register
; Port E Control register
; Port E Direction Register
; Port E Data Register
; OnCE GDB Register
;------------------------------------------------------------------------
;
;
;
EQUATES for Host Interface
;------------------------------------------------------------------------
;
Register Addresses
M_HCR EQU $FFFFC2
M_HSR EQU $FFFFC3
M_HPCR EQU $FFFFC4
M_HBAR EQU $FFFFC5
M_HRX EQU $FFFFC6
M_HTX EQU $FFFFC7
; Host Control Register
; Host Status Register
; Host Polarity Control Register
; Host Base Address Register
; Host Receive Register
; Host Transmit Register
;
HCR bits definition
M_HRIE EQU $0
M_HTIE EQU $1
M_HCIE EQU $2
M_HF2 EQU $3
M_HF3 EQU $4
; Host Receive interrupts Enable
; Host Transmit Interrupt Enable
; Host Command Interrupt Enable
; Host Flag 2
; Host Flag 3
;
HSR bits definition
M_HRDF EQU $0
M_HTDE EQU $1
M_HCP EQU $2
M_HF0 EQU $3
M_HF1 EQU $4
; Host Receive Data Full
; Host Receive Data Empty
; Host Command Pending
; Host Flag 0
; Host Flag 1
;
HPCR bits definition
M_HGEN EQU $0
M_HA8EN EQU $1
M_HA9EN EQU $2
M_HCSEN EQU $3
M_HREN EQU $4
M_HAEN EQU $5
M_HEN EQU $6
M_HOD EQU $8
M_HDSP EQU $9
M_HASP EQU $A
M_HMUX EQU $B
M_HD_HS EQU $C
M_HCSP EQU $D
M_HRP EQU $E
M_HAP EQU $F
; Host Port GPIO Enable
; Host Address 8 Enable
; Host Address 9 Enable
; Host Chip Select Enable
; Host Request Enable
; Host Acknowledge Enable
; Host Enable
; Host Request Open Drain mode
; Host Data Strobe Polarity
; Host Address Strobe Polarity
; Host Multiplexed bus select
; Host Double/Single Strobe select
; Host Chip Select Polarity
; Host Request Polarity
; Host Acknowledge Polarity
A-4
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Power Consumption Benchmark
;------------------------------------------------------------------------
;
;
;
EQUATES for Serial Communications Interface (SCI)
;------------------------------------------------------------------------
;
Register Addresses
M_STXH EQU $FFFF97
M_STXM EQU $FFFF96
M_STXL EQU $FFFF95
M_SRXH EQU $FFFF9A
M_SRXM EQU $FFFF99
M_SRXL EQU $FFFF98
M_STXA EQU $FFFF94
M_SCR EQU $FFFF9C
M_SSR EQU $FFFF93
M_SCCR EQU $FFFF9B
; SCI Transmit Data Register (high)
; SCI Transmit Data Register (middle)
; SCI Transmit Data Register (low)
; SCI Receive Data Register (high)
; SCI Receive Data Register (middle)
; SCI Receive Data Register (low)
; SCI Transmit Address Register
; SCI Control Register
; SCI Status Register
; SCI Clock Control Register
;
SCI Control Register Bit Flags
M_WDS EQU $7
M_WDS0 EQU 0
M_WDS1 EQU 1
M_WDS2 EQU 2
M_SSFTD EQU 3
M_SBK EQU 4
; Word Select Mask (WDS0-WDS3)
; Word Select 0
; Word Select 1
; Word Select 2
; SCI Shift Direction
; Send Break
M_WAKE EQU 5
M_RWU EQU 6
; Wakeup Mode Select
; Receiver Wakeup Enable
; Wired-OR Mode Select
; SCI Receiver Enable
; SCI Transmitter Enable
; Idle Line Interrupt Enable
; SCI Receive Interrupt Enable
; SCI Transmit Interrupt Enable
; Timer Interrupt Enable
; Timer Interrupt Rate
; SCI Clock Polarity
M_WOMS EQU 7
M_SCRE EQU 8
M_SCTE EQU 9
M_ILIE EQU 10
M_SCRIE EQU 11
M_SCTIE EQU 12
M_TMIE EQU 13
M_TIR EQU 14
M_SCKP EQU 15
M_REIE EQU 16
; SCI Error Interrupt Enable (REIE)
;
SCI Status Register Bit Flags
M_TRNE EQU 0
M_TDRE EQU 1
M_RDRF EQU 2
M_IDLE EQU 3
M_OR EQU 4
; Transmitter Empty
; Transmit Data Register Empty
; Receive Data Register Full
; Idle Line Flag
; Overrun Error Flag
M_PE EQU 5
; Parity Error
M_FE EQU 6
M_R8 EQU 7
; Framing Error Flag
; Received Bit 8 (R8) Address
;
SCI Clock Control Register
M_CD EQU $FFF
M_COD EQU 12
M_SCP EQU 13
M_RCM EQU 14
M_TCM EQU 15
; Clock Divider Mask (CD0-CD11)
; Clock Out Divider
; Clock Prescaler
; Receive Clock Mode Source Bit
; Transmit Clock Source Bit
;------------------------------------------------------------------------
;
;
;
EQUATES for Synchronous Serial Interface (SSI)
;------------------------------------------------------------------------
;
;
Register Addresses Of SSI0
M_TX00 EQU $FFFFBC
M_TX01 EQU $FFFFBB
M_TX02 EQU $FFFFBA
M_TSR0 EQU $FFFFB9
M_RX0 EQU $FFFFB8
M_SSISR0 EQU $FFFFB7
M_CRB0 EQU $FFFFB6
M_CRA0 EQU $FFFFB5
M_TSMA0 EQU $FFFFB4
M_TSMB0 EQU $FFFFB3
M_RSMA0 EQU $FFFFB2
M_RSMB0 EQU $FFFFB1
; SSI0 Transmit Data Register 0
; SSIO Transmit Data Register 1
; SSIO Transmit Data Register 2
; SSI0 Time Slot Register
; SSI0 Receive Data Register
; SSI0 Status Register
; SSI0 Control Register B
; SSI0 Control Register A
; SSI0 Transmit Slot Mask Register A
; SSI0 Transmit Slot Mask Register B
; SSI0 Receive Slot Mask Register A
; SSI0 Receive Slot Mask Register B
A-5
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Power Consumption Benchmark
;
Register Addresses Of SSI1
M_TX10 EQU $FFFFAC
M_TX11 EQU $FFFFAB
M_TX12 EQU $FFFFAA
M_TSR1 EQU $FFFFA9
M_RX1 EQU $FFFFA8
M_SSISR1 EQU $FFFFA7
M_CRB1 EQU $FFFFA6
M_CRA1 EQU $FFFFA5
M_TSMA1 EQU $FFFFA4
M_TSMB1 EQU $FFFFA3
M_RSMA1 EQU $FFFFA2
M_RSMB1 EQU $FFFFA1
; SSI1 Transmit Data Register 0
; SSI1 Transmit Data Register 1
; SSI1 Transmit Data Register 2
; SSI1 Time Slot Register
; SSI1 Receive Data Register
; SSI1 Status Register
; SSI1 Control Register B
; SSI1 Control Register A
; SSI1 Transmit Slot Mask Register A
; SSI1 Transmit Slot Mask Register B
; SSI1 Receive Slot Mask Register A
; SSI1 Receive Slot Mask Register B
;
SSI Control Register A Bit Flags
M_PM EQU $FF
; Prescale Modulus Select Mask (PM0-PM7)
; Prescaler Range
M_PSR EQU 11
M_DC EQU $1F000
M_ALC EQU 18
M_WL EQU $380000
M_SSC1 EQU 22
; Frame Rate Divider Control Mask (DC0-DC7)
; Alignment Control (ALC)
; Word Length Control Mask (WL0-WL7)
; Select SC1 as TR #0 drive enable (SSC1)
;
SSI Control Register B Bit Flags
M_OF EQU $3
; Serial Output Flag Mask
; Serial Output Flag 0
; Serial Output Flag 1
M_OF0 EQU 0
M_OF1 EQU 1
M_SCD EQU $1C
M_SCD0 EQU 2
M_SCD1 EQU 3
M_SCD2 EQU 4
M_SCKD EQU 5
M_SHFD EQU 6
M_FSL EQU $180
M_FSL0 EQU 7
M_FSL1 EQU 8
M_FSR EQU 9
M_FSP EQU 10
M_CKP EQU 11
M_SYN EQU 12
M_MOD EQU 13
M_SSTE EQU $1C000
M_SSTE2 EQU 14
M_SSTE1 EQU 15
M_SSTE0 EQU 16
M_SSRE EQU 17
M_SSTIE EQU 18
M_SSRIE EQU 19
M_STLIE EQU 20
M_SRLIE EQU 21
M_STEIE EQU 22
M_SREIE EQU 23
; Serial Control Direction Mask
; Serial Control 0 Direction
; Serial Control 1 Direction
; Serial Control 2 Direction
; Clock Source Direction
; Shift Direction
; Frame Sync Length Mask (FSL0-FSL1)
; Frame Sync Length 0
; Frame Sync Length 1
; Frame Sync Relative Timing
; Frame Sync Polarity
; Clock Polarity
; Sync/Async Control
; SSI Mode Select
; SSI Transmit enable Mask
; SSI Transmit #2 Enable
; SSI Transmit #1 Enable
; SSI Transmit #0 Enable
; SSI Receive Enable
; SSI Transmit Interrupt Enable
; SSI Receive Interrupt Enable
; SSI Transmit Last Slot Interrupt Enable
; SSI Receive Last Slot Interrupt Enable
; SSI Transmit Error Interrupt Enable
; SI Receive Error Interrupt Enable
;
SSI Status Register Bit Flags
M_IF EQU $3
M_IF0 EQU 0
M_IF1 EQU 1
M_TFS EQU 2
M_RFS EQU 3
M_TUE EQU 4
M_ROE EQU 5
M_TDE EQU 6
M_RDF EQU 7
; Serial Input Flag Mask
; Serial Input Flag 0
; Serial Input Flag 1
; Transmit Frame Sync Flag
; Receive Frame Sync Flag
; Transmitter Underrun Error FLag
; Receiver Overrun Error Flag
; Transmit Data Register Empty
; Receive Data Register Full
;
SSI Transmit Slot Mask Register A
M_SSTSA EQU $FFFF
; SSI Transmit Slot Bits Mask A (TS0-TS15)
; SSI Transmit Slot Bits Mask B (TS16-TS31)
; SSI Receive Slot Bits Mask A (RS0-RS15)
; SSI Receive Slot Bits Mask B (RS16-RS31)
;
SSI Transmit Slot Mask Register B
M_SSTSB EQU $FFFF
;
SSI Receive Slot Mask Register A
M_SSRSA EQU $FFFF
;
SSI Receive Slot Mask Register B
M_SSRSB EQU $FFFF
A-6
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Power Consumption Benchmark
;------------------------------------------------------------------------
;
;
;
EQUATES for Exception Processing
;------------------------------------------------------------------------
;
Register Addresses
M_IPRC EQU $FFFFFF
M_IPRP EQU $FFFFFE
; Interrupt Priority Register Core
; Interrupt Priority Register Peripheral
;
Interrupt Priority Register Core (IPRC)
M_IAL EQU $7
; IRQA Mode Mask
M_IAL0 EQU 0
; IRQA Mode Interrupt Priority Level (low)
; IRQA Mode Interrupt Priority Level (high)
; IRQA Mode Trigger Mode
M_IAL1 EQU 1
M_IAL2 EQU 2
M_IBL EQU $38
M_IBL0 EQU 3
; IRQB Mode Mask
; IRQB Mode Interrupt Priority Level (low)
; IRQB Mode Interrupt Priority Level (high)
; IRQB Mode Trigger Mode
M_IBL1 EQU 4
M_IBL2 EQU 5
M_ICL EQU $1C0
M_ICL0 EQU 6
; IRQC Mode Mask
; IRQC Mode Interrupt Priority Level (low)
; IRQC Mode Interrupt Priority Level (high)
; IRQC Mode Trigger Mode
M_ICL1 EQU 7
M_ICL2 EQU 8
M_IDL EQU $E00
M_IDL0 EQU 9
; IRQD Mode Mask
; IRQD Mode Interrupt Priority Level (low)
; IRQD Mode Interrupt Priority Level (high)
; IRQD Mode Trigger Mode
M_IDL1 EQU 10
M_IDL2 EQU 11
M_D0L EQU $3000
M_D0L0 EQU 12
M_D0L1 EQU 13
M_D1L EQU $C000
M_D1L0 EQU 14
M_D1L1 EQU 15
M_D2L EQU $30000
M_D2L0 EQU 16
M_D2L1 EQU 17
M_D3L EQU $C0000
M_D3L0 EQU 18
M_D3L1 EQU 19
M_D4L EQU $300000
M_D4L0 EQU 20
M_D4L1 EQU 21
M_D5L EQU $C00000
M_D5L0 EQU 22
M_D5L1 EQU 23
; DMA0 Interrupt priority Level Mask
; DMA0 Interrupt Priority Level (low)
; DMA0 Interrupt Priority Level (high)
; DMA1 Interrupt Priority Level Mask
; DMA1 Interrupt Priority Level (low)
; DMA1 Interrupt Priority Level (high)
; DMA2 Interrupt priority Level Mask
; DMA2 Interrupt Priority Level (low)
; DMA2 Interrupt Priority Level (high)
; DMA3 Interrupt Priority Level Mask
; DMA3 Interrupt Priority Level (low)
; DMA3 Interrupt Priority Level (high)
; DMA4 Interrupt priority Level Mask
; DMA4 Interrupt Priority Level (low)
; DMA4 Interrupt Priority Level (high)
; DMA5 Interrupt priority Level Mask
; DMA5 Interrupt Priority Level (low)
; DMA5 Interrupt Priority Level (high)
;
Interrupt Priority Register Peripheral (IPRP)
M_HPL EQU $3
M_HPL0 EQU 0
M_HPL1 EQU 1
M_S0L EQU $C
M_S0L0 EQU 2
M_S0L1 EQU 3
M_S1L EQU $30
M_S1L0 EQU 4
M_S1L1 EQU 5
M_SCL EQU $C0
M_SCL0 EQU 6
M_SCL1 EQU 7
M_T0L EQU $300
M_T0L0 EQU 8
M_T0L1 EQU 9
; Host Interrupt Priority Level Mask
; Host Interrupt Priority Level (low)
; Host Interrupt Priority Level (high)
; SSI0 Interrupt Priority Level Mask
; SSI0 Interrupt Priority Level (low)
; SSI0 Interrupt Priority Level (high)
; SSI1 Interrupt Priority Level Mask
; SSI1 Interrupt Priority Level (low)
; SSI1 Interrupt Priority Level (high)
; SCI Interrupt Priority Level Mask
; SCI Interrupt Priority Level (low)
; SCI Interrupt Priority Level (high)
; TIMER Interrupt Priority Level Mask
; TIMER Interrupt Priority Level (low)
; TIMER Interrupt Priority Level (high)
;------------------------------------------------------------------------
;
;
;
EQUATES for TIMER
;------------------------------------------------------------------------
;
Register Addresses Of TIMER0
M_TCSR0 EQU $FFFF8F ; Timer 0 Control/Status Register
A-7
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Power Consumption Benchmark
M_TLR0 EQU $FFFF8E
M_TCPR0 EQU $FFFF8D
M_TCR0 EQU $FFFF8C
; TIMER0 Load Reg
; TIMER0 Compare Register
; TIMER0 Count Register
;
Register Addresses Of TIMER1
M_TCSR1 EQU $FFFF8B
M_TLR1 EQU $FFFF8A
M_TCPR1 EQU $FFFF89
M_TCR1 EQU $FFFF88
; TIMER1 Control/Status Register
; TIMER1 Load Reg
; TIMER1 Compare Register
; TIMER1 Count Register
;
Register Addresses Of TIMER2
M_TCSR2 EQU $FFFF87
M_TLR2 EQU $FFFF86
M_TCPR2 EQU $FFFF85
M_TCR2 EQU $FFFF84
M_TPLR EQU $FFFF83
M_TPCR EQU $FFFF82
; TIMER2 Control/Status Register
; TIMER2 Load Reg
; TIMER2 Compare Register
; TIMER2 Count Register
; TIMER Prescaler Load Register
; TIMER Prescalar Count Register
;
Timer Control/Status Register Bit Flags
M_TE EQU 0
; Timer Enable
M_TOIE EQU 1
M_TCIE EQU 2
M_TC EQU $F0
M_INV EQU 8
M_TRM EQU 9
M_DIR EQU 11
M_DI EQU 12
M_DO EQU 13
M_PCE EQU 15
M_TOF EQU 20
M_TCF EQU 21
; Timer Overflow Interrupt Enable
; Timer Compare Interrupt Enable
; Timer Control Mask (TC0-TC3)
; Inverter Bit
; Timer Restart Mode
; Direction Bit
; Data Input
; Data Output
; Prescaled Clock Enable
; Timer Overflow Flag
; Timer Compare Flag
;
Timer Prescaler Register Bit Flags
M_PS EQU $600000
M_PS0 EQU 21
M_PS1 EQU 22
; Prescaler Source Mask
;
Timer Control Bits
M_TC0 EQU 4
M_TC1 EQU 5
M_TC2 EQU 6
M_TC3 EQU 7
; Timer Control 0
; Timer Control 1
; Timer Control 2
; Timer Control 3
;------------------------------------------------------------------------
;
;
;
EQUATES for Direct Memory Access (DMA)
;------------------------------------------------------------------------
;
Register Addresses Of DMA
M_DSTR EQU FFFFF4 ; DMA Status Register
M_DOR0 EQU $FFFFF3 ; DMA Offset Register 0
M_DOR1 EQU $FFFFF2 ; DMA Offset Register 1
M_DOR2 EQU $FFFFF1 ; DMA Offset Register 2
M_DOR3 EQU $FFFFF0 ; DMA Offset Register 3
;
Register Addresses Of DMA0
M_DSR0 EQU $FFFFEF ; DMA0 Source Address Register
M_DDR0 EQU $FFFFEE ; DMA0 Destination Address Register
M_DCO0 EQU $FFFFED ; DMA0 Counter
M_DCR0 EQU $FFFFEC ; DMA0 Control Register
;
Register Addresses Of DMA1
M_DSR1 EQU $FFFFEB ; DMA1 Source Address Register
M_DDR1 EQU $FFFFEA ; DMA1 Destination Address Register
M_DCO1 EQU $FFFFE9 ; DMA1 Counter
M_DCR1 EQU $FFFFE8 ; DMA1 Control Register
;
Register Addresses Of DMA2
M_DSR2 EQU $FFFFE7 ; DMA2 Source Address Register
A-8
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Power Consumption Benchmark
M_DDR2 EQU $FFFFE6 ; DMA2 Destination Address Register
M_DCO2 EQU $FFFFE5 ; DMA2 Counter
M_DCR2 EQU $FFFFE4 ; DMA2 Control Register
;
Register Addresses Of DMA4
M_DSR3 EQU $FFFFE3 ; DMA3 Source Address Register
M_DDR3 EQU $FFFFE2 ; DMA3 Destination Address Register
M_DCO3 EQU $FFFFE1 ; DMA3 Counter
M_DCR3 EQU $FFFFE0 ; DMA3 Control Register
;
Register Addresses Of DMA4
M_DSR4 EQU $FFFFDF ; DMA4 Source Address Register
M_DDR4 EQU $FFFFDE ; DMA4 Destination Address Register
M_DCO4 EQU $FFFFDD ; DMA4 Counter
M_DCR4 EQU $FFFFDC ; DMA4 Control Register
;
Register Addresses Of DMA5
M_DSR5 EQU $FFFFDB ; DMA5 Source Address Register
M_DDR5 EQU $FFFFDA ; DMA5 Destination Address Register
M_DCO5 EQU $FFFFD9 ; DMA5 Counter
M_DCR5 EQU $FFFFD8 ; DMA5 Control Register
;
DMA Control Register
M_DSS EQU $3
M_DSS0 EQU 0
M_DSS1 EQU 1
M_DDS EQU $C
M_DDS0 EQU 2
M_DDS1 EQU 3
; DMA Source Space Mask (DSS0-Dss1)
; DMA Source Memory space 0
; DMA Source Memory space 1
; DMA Destination Space Mask (DDS-DDS1)
; DMA Destination Memory Space 0
; DMA Destination Memory Space 1
M_DAM EQU $3f0 ; DMA Address Mode Mask (DAM5-DAM0)
M_DAM0 EQU 4 ; DMA Address Mode 0
M_DAM1 EQU 5 ; DMA Address Mode 1
M_DAM2 EQU 6 ; DMA Address Mode 2
M_DAM3 EQU 7 ; DMA Address Mode 3
M_DAM4 EQU 8 ; DMA Address Mode 4
M_DAM5 EQU 9 ; DMA Address Mode 5
M_D3D EQU 10
; DMA Three Dimensional Mode
M_DRS EQU $F800; DMA Request Source Mask (DRS0-DRS4)
M_DCON EQU 16 ; DMA Continuous Mode
M_DPR EQU $60000; DMA Channel Priority
M_DPR0 EQU 17 ; DMA Channel Priority Level (low)
M_DPR1 EQU 18 ; DMA Channel Priority Level (high)
M_DTM EQU $380000; DMA Transfer Mode Mask (DTM2-DTM0)
M_DTM0 EQU 19 ; DMA Transfer Mode 0
M_DTM1 EQU 20 ; DMA Transfer Mode 1
M_DTM2 EQU 21 ; DMA Transfer Mode 2
M_DIE EQU 22
M_DE EQU 23
; DMA Interrupt Enable bit
; DMA Channel Enable bit
;
DMA Status Register
M_DTD EQU $3F ; Channel Transfer Done Status MASK (DTD0-DTD5)
M_DTD0 EQU 0
M_DTD1 EQU 1
M_DTD2 EQU 2
M_DTD3 EQU 3
M_DTD4 EQU 4
M_DTD5 EQU 5
M_DACT EQU
; DMA Channel Transfer Done Status 0
; DMA Channel Transfer Done Status 1
; DMA Channel Transfer Done Status 2
; DMA Channel Transfer Done Status 3
; DMA Channel Transfer Done Status 4
; DMA Channel Transfer Done Status 5
; DMA Active State
8
M_DCH EQU $E00; DMA Active Channel Mask (DCH0-DCH2)
M_DCH0 EQU
M_DCH1 EQU 10 ; DMA Active Channel 1
M_DCH2 EQU 11 ; DMA Active Channel 2
9
; DMA Active Channel 0
;------------------------------------------------------------------------
;
;
;
EQUATES for Enhanced Filter Co-Processor (EFCOP)
;------------------------------------------------------------------------
M_FDIR
M_FDOR
M_FKIR
M_FCNT
M_FCSR
M_FACR
EQU
EQU
EQU
EQU
EQU
EQU
$FFFFB0
$FFFFB1
$FFFFB2
$FFFFB3
$FFFFB4
$FFFFB5
; EFCOP Data Input Register
; EFCOP Data Output Register
; EFCOP K-Constant Register
; EFCOP Filter Counter
; EFCOP Control Status Register
; EFCOP ALU Control Register
A-9
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Power Consumption Benchmark
M_FDBA
M_FCBA
M_FDCH
EQU
EQU
EQU
$FFFFB6
$FFFFB7
$FFFFB8
; EFCOP Data Base Address
; EFCOP Coefficient Base Address
; EFCOP Decimation/Channel Register
;------------------------------------------------------------------------
;
;
;
EQUATES for Phase Locked Loop (PLL)
;------------------------------------------------------------------------
;
Register Addresses Of PLL
M_PCTL EQU $FFFFFD ; PLL Control Register
PLL Control Register
;
M_MF EQU $FFF : Multiplication Factor Bits Mask (MF0-MF11)
M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2)
M_XTLR EQU 15 ; XTAL Range select bit
M_XTLD EQU 16 ; XTAL Disable Bit
M_PSTP EQU 17 ; STOP Processing State Bit
M_PEN EQU 18
; PLL Enable Bit
M_PCOD EQU 19 ; PLL Clock Output Disable Bit
M_PD EQU $F00000; PreDivider Factor Bits Mask (PD0-PD3)
;------------------------------------------------------------------------
;
;
;
EQUATES for BIU
;------------------------------------------------------------------------
;
Register Addresses Of BIU
M_BCR EQU $FFFFFB; Bus Control Register
M_DCR EQU $FFFFFA; DRAM Control Register
M_AAR0 EQU $FFFFF9; Address Attribute Register 0
M_AAR1 EQU $FFFFF8; Address Attribute Register 1
M_AAR2 EQU $FFFFF7; Address Attribute Register 2
M_AAR3 EQU $FFFFF6; Address Attribute Register 3
M_IDR EQU $FFFFF5 ; ID Register
;
Bus Control Register
M_BA0W EQU $1F ; Area 0 Wait Control Mask (BA0W0-BA0W4)
M_BA1W EQU $3E0; Area 1 Wait Control Mask (BA1W0-BA14)
M_BA2W EQU $1C00; Area 2 Wait Control Mask (BA2W0-BA2W2)
M_BA3W EQU $E000; Area 3 Wait Control Mask (BA3W0-BA3W3)
M_BDFW EQU $1F0000 ; Default Area Wait Control Mask (BDFW0-BDFW4)
M_BBS EQU 21
M_BLH EQU 22
M_BRH EQU 23
; Bus State
; Bus Lock Hold
; Bus Request Hold
;
DRAM Control Register
M_BCW EQU $3
M_BRW EQU $C
; In Page Wait States Bits Mask (BCW0-BCW1)
; Out Of Page Wait States Bits Mask (BRW0-BRW1)
M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1)
M_BPLE EQU 11 ; Page Logic Enable
M_BME EQU 12
M_BRE EQU 13
; Mastership Enable
; Refresh Enable
M_BSTR EQU 14 ; Software Triggered Refresh
M_BRF EQU $7F8000; Refresh Rate Bits Mask (BRF0-BRF7)
M_BRP EQU 23
; Refresh prescaler
;
Address Attribute Registers
M_BAT EQU $3
M_BAAP EQU 2
M_BPEN EQU 3
M_BXEN EQU 4
M_BYEN EQU 5
M_BAM EQU 6
M_BPAC EQU 7
; Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1)
; Address Attribute Pin Polarity
; Program Space Enable
; X Data Space Enable
; Y Data Space Enable
; Address Muxing
; Packing Enable
M_BNC EQU $F00 ; Number of Address Bits to Compare Mask (BNC0-BNC3)
M_BAC EQU $FFF000; Address to Compare Bits Mask (BAC0-BAC11)
A-10
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Power Consumption Benchmark
;
control and status bits in SR
M_CP EQU $c00000; mask for CORE-DMA priority bits in SR
M_CA EQU 0
M_V EQU 1
; Carry
; Overflow
M_Z EQU 2
; Zero
M_N EQU 3
; Negative
M_U EQU 4
; Unnormalized
M_E EQU 5
; Extension
M_L EQU 6
; Limit
M_S EQU 7
; Scaling Bit
M_I0 EQU 8
M_I1 EQU 9
M_S0 EQU 10
M_S1 EQU 11
M_SC EQU 13
M_DM EQU 14
M_LF EQU 15
M_FV EQU 16
M_SA EQU 17
M_CE EQU 19
M_SM EQU 20
M_RM EQU 21
M_CP0 EQU 22
M_CP1 EQU 23
; Interupt Mask Bit 0
; Interupt Mask Bit 1
; Scaling Mode Bit 0
; Scaling Mode Bit 1
; Sixteen_Bit Compatibility
; Double Precision Multiply
; DO-Loop Flag
; DO-Forever Flag
; Sixteen-Bit Arithmetic
; Instruction Cache Enable
; Arithmetic Saturation
; Rounding Mode
; bit 0 of priority bits in SR
; bit 1 of priority bits in SR
;
control and status bits in OMR
M_CDP EQU $300 ; mask for CORE-DMA priority bits in OMR
M_MA
M_MB
M_MC
M_MD
equ0
; Operating Mode A
equ1
; Operating Mode B
equ2
equ3
; Operating Mode C
; Operating Mode D
M_EBD EQU 4
M_SD EQU 6
; External Bus Disable bit in OMR
; Stop Delay
M_MS EQU 7
; Memory Switch bit in OMR
; bit 0 of priority bits in OMR
; bit 1 of priority bits in OMR
M_CDP0 EQU 8
M_CDP1 EQU 9
M_BEN
EQU 10 ; Burst Enable
M_TAS EQU 11 ; TA Synchronize Select
M_BRT EQU 12 ; Bus Release Timing
M_ATE EQU 15
M_XYS EQU 16
M_EUN EQU 17
M_EOV EQU 18
M_WRP EQU 19
M_SEN EQU 20
; Address Tracing Enable bit in OMR.
; Stack Extension space select bit in OMR.
; Extensed stack UNderflow flag in OMR.
; Extended stack OVerflow flag in OMR.
; Extended WRaP flag in OMR.
; Stack Extension Enable bit in OMR.
;*************************************************************************
;
;
;
;
;
EQUATES for DSP56321 interrupts
Last update: June 11 1995
;*************************************************************************
page
opt
132,55,0,0,0
mex
intequ ident
if
1,0
@DEF(I_VEC)
;leave user definition as is.
else
I_VEC EQU $0
endif
;------------------------------------------------------------------------
; Non-Maskable interrupts
;------------------------------------------------------------------------
I_RESET EQU I_VEC+$00 ; Hardware RESET
I_STACK EQU I_VEC+$02 ; Stack Error
I_ILL EQU I_VEC+$04
I_DBG EQU I_VEC+$06
; Illegal Instruction
; Debug Request
A-11
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Power Consumption Benchmark
I_TRAP EQU I_VEC+$08
I_NMI EQU I_VEC+$0A
; Trap
; Non Maskable Interrupt
;------------------------------------------------------------------------
; Interrupt Request Pins
;------------------------------------------------------------------------
I_IRQA EQU I_VEC+$10
I_IRQB EQU I_VEC+$12
I_IRQC EQU I_VEC+$14
I_IRQD EQU I_VEC+$16
; IRQA
; IRQB
; IRQC
; IRQD
;------------------------------------------------------------------------
; DMA Interrupts
;------------------------------------------------------------------------
I_DMA0 EQU I_VEC+$18
I_DMA1 EQU I_VEC+$1A
I_DMA2 EQU I_VEC+$1C
I_DMA3 EQU I_VEC+$1E
I_DMA4 EQU I_VEC+$20
I_DMA5 EQU I_VEC+$22
; DMA Channel 0
; DMA Channel 1
; DMA Channel 2
; DMA Channel 3
; DMA Channel 4
; DMA Channel 5
;------------------------------------------------------------------------
; Timer Interrupts
;------------------------------------------------------------------------
I_TIM0C EQU I_VEC+$24 ; TIMER 0 compare
I_TIM0OF EQU I_VEC+$26; TIMER 0 overflow
I_TIM1C EQU I_VEC+$28 ; TIMER 1 compare
I_TIM1OF EQU I_VEC+$2A; TIMER 1 overflow
I_TIM2C EQU I_VEC+$2C ; TIMER 2 compare
I_TIM2OF EQU I_VEC+$2E; TIMER 2 overflow
;------------------------------------------------------------------------
; ESSI Interrupts
;------------------------------------------------------------------------
I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive Data
I_SI0RDE EQU I_VEC+$32; ESSI0 Receive Data w/ exception Status
I_SI0RLS EQU I_VEC+$34; ESSI0 Receive last slot
I_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit data
I_SI0TDE EQU I_VEC+$38; ESSI0 Transmit Data w/ exception Status
I_SI0TLS EQU I_VEC+$3A; ESSI0 Transmit last slot
I_SI1RD EQU I_VEC+$40 ; ESSI1 Receive Data
I_SI1RDE EQU I_VEC+$42; ESSI1 Receive Data w/ exception Status
I_SI1RLS EQU I_VEC+$44
I_SI1TD EQU I_VEC+$46
; ESSI1 Receive last slot
; ESSI1 Transmit data
I_SI1TDE EQU I_VEC+$48; ESSI1 Transmit Data w/ exception Status
I_SI1TLS EQU I_VEC+$4A; ESSI1 Transmit last slot
;------------------------------------------------------------------------
; SCI Interrupts
;------------------------------------------------------------------------
I_SCIRD EQU I_VEC+$50
I_SCIRDE EQU I_VEC+$52
I_SCITD EQU I_VEC+$54
I_SCIIL EQU I_VEC+$56
I_SCITM EQU I_VEC+$58
; SCI Receive Data
; SCI Receive Data With Exception Status
; SCI Transmit Data
; SCI Idle Line
; SCI Timer
;------------------------------------------------------------------------
; HOST Interrupts
;------------------------------------------------------------------------
I_HRDF EQU I_VEC+$60
I_HTDE EQU I_VEC+$62
I_HC EQU I_VEC+$64
; Host Receive Data Full
; Host Transmit Data Empty
; Default Host Command
;-----------------------------------------------------------------------
; EFCOP Filter Interrupts
;-----------------------------------------------------------------------
I_FDIIE EQU
I_FDOIE EQU
I_VEC+$68 ; EFilter input buffer empty
I_VEC+$6A ; EFilter output buffer full
;------------------------------------------------------------------------
; INTERRUPT ENDING ADDRESS
;------------------------------------------------------------------------
I_INTEND EQU I_VEC+$FF
; last address of interrupt vector space
A-12
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Index
Technical Data v
User’s Manual v
A
ac electrical characteristics 2-4
address bus 1-1
applications iv
E
EFCOP
interrupts A-12
electrical
design considerations 4-2, 4-3
B
benchmark test algorithm A-1
block diagram i
bootstrap ROM iii
Boundary Scan (JTAG Port) timing diagram 2-31
bus
Enhanced Synchronous Serial Interface (ESSI) iii,
1-1, 1-2, 1-12, 1-13
receiver timing 2-27
transmitter timing 2-26
external address bus 1-4
address 1-2
external bus control 1-4, 1-5, 1-6
external clock operation 2-4
external data bus 1-4
external interrupt timing (negative
edge-triggered) 2-10
control 1-1
data 1-2
external address 1-4
external data 1-4
multiplexed 1-2
external level-sensitive fast interrupt timing 2-10
external memory access (DMA Source)
timing 2-11
External Memory Expansion Port 2-12
external memory expansion port 1-4
non-multiplexed 1-2
C
clock 1-1, 1-3
external 2-4
operation 2-5
clocks
F
functional groups 1-2
internal 2-4
functional signal groups 1-1
crystal oscillator circuits 2-4
G
D
General-Purpose Input/Output (GPIO) iii, 1-2
ground 1-1, 1-3
data bus 1-1
data memory expansion iv
Data Strobe (DS) 1-2
dc electrical characteristics 2-3
DE signal 1-17
Debug Event signal (DE signal) 1-17
Debug mode
entering 1-17
external indication 1-17
Debug support iii
design considerations
electrical 4-2, 4-3
PLL 4-4
power consumption 4-3
thermal 4-1
Digital Phase Lock Loop (DPLL) 2-6
documentation list v
Double Data Strobe 1-2
DSP56300
H
Host Interface (HI08) iii, 1-1, 1-2, 1-8, 1-9, 1-10,
1-11
Host Port Control Register (HPCR) 1-9, 1-11
host port
configuration 1-8
usage considerations 1-8
Host Port Control Register (HPCR) 1-9, 1-11
Host Request
Double 1-2
Single 1-2
Host Request (HR) 1-2
I
information sources v
instruction cache iii
internal clocks 2-4
Family Manual v
DSP56321
block diagram i
Index-1
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Index
interrupt and mode control 1-1, 1-7
interrupt control 1-7
interrupt timing 2-7
on-chip memory iii
operating mode select timing 2-11
ordering information Back Cover
external level-sensitive fast 2-10
external negative edge-triggered 2-10
interrupts
P
package
EFCOP A-12
MAP-BGA description 3-2, 3-3, 3-10
Phase-Lock Loop (PLL) 1-1
design considerations 4-4
performance issues 4-4
PLL 1-3
J
Joint Test Action Group (JTAG)
interface 1-17
JTAG iii
JTAG Port
Port A 1-1, 1-4, 2-12
Port B 1-1, 1-2, 1-10
Port C 1-1, 1-2, 1-12
Port D 1-1, 1-2, 1-13
Port E 1-1
reset timing diagram 2-31
timing 2-31
JTAG/OnCE Interface signals
Debug Event signal (DE signal) 1-17
JTAG/OnCE port 1-1, 1-2
power 1-1, 1-2, 1-3
power consumption
design considerations 4-3
power consumption benchmark test A-1
power management iv
program memory expansion iv
program RAM iii
K
keeper circuit
design considerations 4-3
M
R
MAP-BGA
recovery from Stop state using IRQA 2-11
reset
ball grid drawing (bottom) 3-3
ball grid drawing (top) 3-2
mechanical drawing 3-10
maximum ratings 2-1, 2-2
memory expansion port iii
mode control 1-7
Mode select timing 2-7
multiplexed bus 1-2
multiplexed bus timings
read 2-20
clock signals 1-3
interrupt signals 1-7
JTAG signals 1-17
mode control 1-7
OnCE signals 1-17
Reset timing 2-7, 2-9
ROM, bootstrap iii
S
write 2-21
Serial Communication Interface (SCI) iii, 1-1,
1-2, 1-15
N
Asynchronous mode timing 2-23
Synchronous mode timing 2-23
signal groupings 1-1
signals 1-1
functional grouping 1-2
Single Data Strobe 1-2
SRAM
non-multiplexed bus 1-2
non-multiplexed bus timings
read 2-18
write 2-19
O
read access 2-13
support iv
write access 2-14
off-chip memory iii
OnCE module iii
Debug request 2-32
On-Chip Emulation (OnCE) module
interface 1-17
Stop mode iv
Stop state
recovery from 2-11
On-Chip Emulation module iii
Index-2
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Index
Stop timing 2-7
supply voltage 2-2
Switch mode iii
T
target applications iv
Test Access Port (TAP) iii
timing diagram 2-31
Test Clock (TCLK) input timing diagram 2-30
thermal
design considerations 4-1
Timer
event input restrictions 2-28
Timers 1-1, 1-2, 1-16
interrupt generation 2-28
timing
interrupt 2-7
mode select 2-7
Reset 2-7
Stop 2-7
W
Wait mode iv
World Wide Web v
X
X-data RAM iii
Y
Y-data RAM iii
Index-3
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Index
Index-4
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Ordering Information
Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and place an order.
Core
Supply
Voltage
Part
Package Type
Pin Count Frequency
(MHz)
Order Number
DSP56321T 1.6 V core Flip-Chip Plastic Ball Grid Array (FC-PBGA)
3.3 V I/O
196
220
240
DSP56321TFC220
DSP56321TFC240
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