FBL22041 [NXP]
3.3V BTL 7-bit Futurebus transceiver standard A-port; 3.3V的BTL 7位FUTUREBUS收发器标准的A口
| 型号： | FBL22041 |
| 厂家： | 
NXP |
| 描述： | 3.3V BTL 7-bit Futurebus transceiver standard A-port |
| 文件： | 总14页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
FBL22041
3.3V BTL 7-bit Futurebus + transceiver
(standard A-port)
Product specification
1998 Aug 12
Supersedes data of 1998 Feb 02
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
FBL22041
FEATURES
• 7-bit BTL transceiver
• Tight output skew
• Supports live insertion
• Separate I/O on TTL A-port
• Pins for the optional JTAG boundary scan function are provided
• High density packaging in plastic Quad Flatpack
• 5V compatible I/O on A-port
• Inverting
• Three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement
• The A port includes a series resistor of 30Ω making external
• Drives heavily loaded backplanes with equivalent load
impedances down to 10Ω.
terminating resistors unnecessary
• High drive 100mA BTL open collector drivers on B-port
DESCRIPTION
• Allows incident wave switching in heavily loaded backplane buses
The FBL22041 is a 7-bit bidirectional BTL transceiver and is
intended to provide the electrical interface to a high performance
wired-OR bus. The FBL22041 is an inverting transceiver.
• Reduced BTL voltage swing produces less noise and reduces
power consumption
• Built-in precision band-gap reference provides accurate receiver
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
thresholds and improved noise immunity
• Compatible with IEEE Futurebus+ or proprietary BTL backplanes
• Controlled output ramp and multiple GND pins minimize ground
The FBL22041 is designed with a 30Ω series resistance in both the
HIGH and LOW states of the output.
bounce
• Each BTL driver has a dedicated Bus GND for a signal return
• Glitch-free power up/power down operation
The FBL22041 is pin and function compatible with FB2041 but
operates at a 3.3V supply voltage, greatly reducing power
consumption.
• Low I current
CC
QUICK REFERENCE DATA
SYMBOL
PARAMETER
Propagation delay
TYPICAL
4.1
UNIT
t
t
t
t
PLH
PHL
PLH
PHL
ns
AIn to Bn
3.6
Propagation delay
5.2
ns
Bn to AOn
5.1
C
Output capacitance (B0 - B6 only)
Output current (B0 - B6 only)
6
pF
OB
I
OL
100
6.0
mA
Standby
AIn to Bn (outputs Low or High)
Bn to AOn (outputs Low)
Bn to AOn (outputs High)
5.1
I
Supply Current
mA
CC
13.4
10.6
ORDERING INFORMATION
PACKAGE
COMMERCIAL RANGE
DWG
No.
V
CC
= 3.3V±10%; T
= 0 to +70°C
amb
52-pin Plastic Quad Flatpack
FBL22041BB
SOT379-1
2
1998 Aug 12
853-2039 19863
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
FBL22041
52 51 50 49 48 47 46 45 44 43 42 41 40
LOGIC GND
AI1
BUS GND
1
2
3
4
5
6
7
39
38 B1
AI2
37 BUS GND
36 B2
AO2
7-Bit Transceiver
35
34
33
LOGIC GND
BUS GND
AO3
B3
LOGIC GND
BUS GND
AI3
AI4
B4
8
32
31
30
29
28
52-lead PQFP
9
BUS GND
B5
10
11
12
AO4
LOGIC GND
AO5
BUS GND
B6
LOGIC GND 13
27 N/C
14 15 16 17 18 19 20 21 22 23 24 25 26
SG00084
The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced
capacitive loading by placing an internal series diode on the drivers.
BTL also provides incident wave switching, a necessity for high
performance backplanes.
The A-port operates at TTL levels with separate I/O. The 3-state
A-port drivers are enabled when OEAn goes High after an extra 6ns
delay which is built in to provide a break-before-make function.
When OEAn goes Low, A-port drivers become High impedance
without any extra delay. During power on/off cycles, the A-port
drivers are held in a High impedance state when V is below 1.3V.
CC
There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement. The TTL/BTL output drivers for bit 0 are enabled with
OEA1/OEB1, output drivers for bits 1–2–3 are enabled with
OEA2/OEB2 and output drivers for bits 4–5–6 are enabled with
OEA3/OEB3.
The B-port has an output enable, OEB0, which affects all seven
drivers. When OEB0 is High and OEBn is Low the output driver will
be enabled. When OEB0 is Low or if OEBn is High, the B-port
drivers will be inactive and at the level of the backplane signal.
3
1998 Aug 12
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
FBL22041
PIN DESCRIPTION
SYMBOL
ai0 – ai6
aO0 – aO6
b0 – b6
OEB0
PIN NUMBER
TYPE
Input
Output
i/o
NAME AND FUNCTION
Data inputs (TTL)
51, 2, 3, 8, 9, 14, 18
50, 52, 4, 6, 10, 12, 16
3-state outputs (TTL)
40, 38, 36, 34, 32, 30, 28
Data inputs/Open Collector outputs, High current drive (BTL)
Enables the Bn outputs when High
Enables the B0 output when Low
Enables the B1 – B3 outputs when Low
Enables the B4 – B6 outputs when Low
Enables the A0 outputs when High
Enables the A1 – A3 outputs when High
Enables the A4 – A6 outputs when High
Bus ground (0V)
46
Input
Input
Input
Input
Input
Input
Input
GND
GND
Power
Power
Power
Input
Input
Input
Output
GND
OEB1
45
OEB2
25
OEB3
26
OEA1
47
OEA2
20
OEA3
24
bus gnd
LOGIC gnd
41, 39, 37, 35, 33, 31, 29
1, 5, 7, 11, 13, 15
Logic ground (0V)
LOGIC/bus V
23, 43, 49
Positive supply voltage
CC
BG V
17
48
42
44
22
21
19
Positive supply voltage BAND GAP
Positive supply voltage
CC
BIAS V
TMS
Test Mode Select (no-connect)
Test Clock (no-connect)
Tck
Tdi
Test Data In (shorted to TDO)
Test Data Out (TDI)
Tdo
BG GND
BAND GAP GROUND (0V)
4
1998 Aug 12
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
FBL22041
FUNCTION TABLE
INPUTS
OEB0 OEB1 OEB2 OEB3 OEA1 OEA2 OEA3
OUTPUTS
MODE
AIn
L
Bn*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
AOn
Z
Z
L
Bn*
H**
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
AIn to Bn
H
L
L
L
L
H
H
L
H
H
L
H
H
L
H**
L
H
L
L
L
L
H
Z
Z
L
L
X
X
X
X
L
X
X
X
X
X
X
X
X
L
H**
L
AI0 to B0
H
L
L
L
L
L
L
H
H
L
H
H
L
H
H
L
H**
L
H
L
L
H
Z
Z
L
X
X
X
X
X
X
X
X
X
H
H
X
X
X
X
H
H
X
X
H
H
X
X
H
H
X
X
H
H
X
X
X
X
H**
L
AI1 – AI3 to B1 – B3
H
L
L
L
L
L
L
H
H
L
H
H
L
H
H
L
H**
L
H
L
L
H
Z
Z
L
X
X
X
X
X
H
X
H
X
X
X
H
H
X
X
H
H
X
X
H
H
X
X
H
H
X
X
X
X
H**
L
AI4 – AI6 to B4 – B6
Disable Bn outputs
H
L
L
L
L
L
L
H
H
X
X
X
X
X
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
H
H
X
X
X
X
X
H
H
H
H
X
X
X
X
H
H
H
H
X
X
X
X
L
H
H
X
X
X
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
H
H
H
L
H**
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
H
L
X
H
X
X
H
X
X
H
H
X
X
H
H
X
X
H
H
X
X
H
H
X
X
X
X
H**
H**
H**
H**
H**
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
X
X
X
H
H
H
L
Disable B0 outputs
X
Disable B1 – B3 outputs
Disable B4 – B6 outputs
X
X
L
Bn to AOn
H
L
L
X
X
L
H
L
H
L
H
L
B0 to AO0
H
L
L
X
X
L
H
L
H
L
H
L
B1 – B3 to AO1 – AO3
B4 – B6 to AO4 – AO6
H
L
L
X
X
L
H
L
H
L
H
L
H
L
L
X
X
X
X
X
X
H
L
H
Disable AOn outputs
X
Z
Z
Z
Z
Disable AO0 outputs
X
L
X
L
X
X
L
X
Disable AO1 – AO3 outputs
Disable AO4 – AO6 outputs
X
X
X
X
X
X
X
NOTES:
H
L
X
Z
—
=
=
=
=
=
High voltage level
Low voltage level
Don’t care
High-impedance (OFF) state
Input not externally driven
Z
—
=
=
High-impedance (OFF) state
Input not externally driven
H** = Goes to level of pull-up voltage
B*
=
Precaution should be taken to ensure B inputs do not float.
If they do, they are equal to Low state.
H** = Goes to level of pull-up voltage
B*
=
Precaution should be taken to ensure B inputs do not float.
If they do, they are equal to Low state.
5
1998 Aug 12
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
FBL22041
LOGIC DIAGRAM
46
OEB0
45
OEB1
47
OEA1
40
B0
51
AI0
50
AO0
25
OEB2
20
OEA2
38
B1
2
AI1
52
AO1
36
34
B2
B3
3
AI2
4
AO2
TTL
Levels
BTL
Levels
8
AI3
6
AO3
26
OEB3
24
OEA3
32
B4
9
AI4
10
AO4
30
28
B5
B6
14
AI5
12
AO5
18
AI6
16
AO6
42
TMS
44
TCK
TDI
TDO
(Future JTAG Boundary Scan option)
22
21
LOGIC V
=
=
=
=
=
17, 49
1, 5, 7, 11, 13, 15, 19
23, 43
27, 29, 31, 33, 35, 37, 39, 41
48
CC
LOGIC GND
BUS V
CC
BUS GND
BIAS V
SG00071
6
1998 Aug 12
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
FBL22041
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.
SYMBOL
PARAMETER
RATING
UNIT
V
Supply voltage
Input voltage
-0.5 to +4.6
-0.5 to +7.0
-0.5 to +3.5
-50
V
V
CC
AI0 – AI6, OEB0, OEBn, OEAn
B0 – B6
V
IN
I
IN
Input current
V
IN
t 0
V
OUT
Voltage applied to output in High output state
Current applied to output in
Low output state/High output state
Storage temperature
-0.5 to +7.0
48, –24
V
AO0 – AO6
B0 – B6
mA
I
OUT
200
T
STG
-65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
COMMERCIAL LIMITS
= 3.3V±10%;
V
PARAMETER
SYMBOL
CC
UNIT
T
amb
= 0 to +70°C
MIN
3.0
TYP
MAX
V
Supply voltage
3.3
3.6
V
V
CC
Except B0–B6
2.0
V
High-level input voltage
IH
B0 – B6
1.62
1.55
Except B0–B6
B0 – B6
0.8
1.47
-18
-12
12
V
V
Low-level input voltage
IL
I
IK
Input clamp current
mA
mA
mA
I
High-level output current
AO0 – AO6
AO0 – AO6
B0 – B6
OH
I
OL
Low-level output current
100
7
C
Output capacitance on B port
6
pF
OB
T
amb
Operating free-air temperature range
0
+70
°C
7
1998 Aug 12
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
FBL22041
LIVE INSERTION SPECIFICATIONS
LIMITS
TYP
SYMBOL
PARAMETER
UNIT
MAX
MIN
Voltage difference between the Bias voltage
V
Bias pin voltage
Bias pin (I ) input
–
–
0.5
V
BIASV
and V after the PCB is plugged in.
CC
V
CC
V
CC
= 0 V, Bias V = 3.6V
= 3.3V, Bias V = 3.6V
1.2
10
2.1
1
mA
µA
V
BIASV
I
BIASV
DC current
V
Bn
Bus voltage during prebias
Fall current during prebias
Rise current during prebias
B0 – B8 = 0V, Bias V = 3.3V
1.62
-1
I
B0 – B8 = 2V, Bias V = 1.3 to 2.5V
B0 – B8 = 1V, Bias V = 3 to 3.6V
µA
µA
LM
I
HM
Peak bus current during
insertion
V
= 0 to 3.3V, B0 – B8 = 0 to 2.0V,
CC
I
Bn
PEAK
10
mA
Bias V = 2.7 to 3.6V, OEB0 = 0.8V, t = 2ns
r
V
CC
V
CC
V
CC
= 0 to 3.3V, OEB0 = 0.8V
= 0 to 1.2V, OEB0 = 0 to 5V
= 3.3V
100
100
I
OFF
Power up current
µA
OL
t
Input glitch rejection
1.0
1.35
ns
GR
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
TYP
MAX
100
I
High level output current B0 – B6
Power-off output current B0 – B6
V
V
= MAX, V = MAX, V = 1.9V
µA
µA
OH
CC
IL
OH
I
= 0V, V = MAX, V = 1.9V
100
OFF
CC
IL
OH
V
–0.2
CC
V
CC
= MIN to MAX; I = -100µA
V
OH
High-level output
voltage
3
3
V
AO0 – AO6
OH
V
V
V
V
V
V
V
V
= MIN; I = -4mA
2.4
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
OH
= MIN; I = -12mA
2.0
OH
= MIN; I = 4mA
0.4
0.8
OL
AO0 – AO6
B0 – B6
V
Low-level output voltage
= MIN; I = 12mA
OL
OL
= MIN, I = 4mA
0.5
OL
V
V
= MIN, I = 100mA
0.75
1.0
1.20
-1.2
±1.0
OL
V
Input clamp voltage
Input leakage current
= MIN, I = I = –18mA
–0.85
IK
I
IK
Control pins
= 3.6V; V = V or GND
I CC
Control/
AI0 – AI6
V
CC
= 0V or 3.6V; V = 5.5V
10
I
I
I
µA
AI0 – AI6
Note 4
V
V
V
V
V
V
V
V
V
V
V
V
= 3.6V; V = V
CC
1
CC
CC
CC
CC
CC
I
= 3.6V; V = 0V
–5
I
= MAX, V = 1.9V
100
µA
mA
mA
µA
µA
µA
I
I
High-level input current
B0 – B6
= MAX, V = 3.5V, note 5
100
100
IH
I
= MAX, V = 3.75V @ –40°C
I
I
Low-level input current
Off-state output current
Off-state output current
B0 – B6
= MAX, V = 0.75V
-100
5
IL
CC
CC
CC
CC
CC
CC
CC
I
I
AO0 – AO6
AO0 – AO6
= MAX, V =3V
O
OZH
I
= MAX, V = 0.5V
-5
OZL
O
I
I
I
I
(standby)
AIn to Bn
Bn to AOn
Bn to AOn
= MAX
6.0
5.1
13.0
10.0
19.5
16.0
CCZ
= MAX, outputs Low or High
= MAX, outputs Low
= MAX, outputs High
CCB,
CCA,
CCA,
I
Supply current (total)
mA
CC
13.4
10.6
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at V = 3.3V, T = 25°C.
CC
A
3. Due to test equipment limitations, actual test conditions are V = 1.8V and V = 1.3V for the B side.
IH
IL
4. Unused pins are at V or GND.
CC
5. For B port input voltage between 3 and 5 volt; I will be greater than 100mA but the part will continue to function normally (clamping circuit
IH
is active).
8
1998 Aug 12
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
FBL22041
AC ELECTRICAL CHARACTERISTICS (Commercial)
A PORT LIMITS
T
V
= 0 to 70°C,
= 3.3V±10%,
amb
CC
TEST
CONDITION
T
= +25°C, V = 3.3V,
SYMBOL
PARAMETER
UNIT
amb
L
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay,
Bn to AOn
4.2
4.1
5.2
5.1
6.2
6.1
3.9
3.9
7.0
6.8
PLH
PHL
Waveform 1, 2
Waveform 4, 5
Waveform 4, 5
ns
ns
ns
ns
ns
t
Output enable time,
OEA to AOn
5.8
2.7
7.1
4.5
8.5
8.0
5.4
2.5
9.4
8.5
PZH
t
PZL
t
Output disable time,
OEA to AOn
3.9
3.7
5.2
4.8
6.5
6.0
3.6
3.3
7.0
7.3
PHZ
t
PLZ
t
t
Transition time, AOn Port
(10% to 90% or 90% to 10%)
Test Circuit and
Waveforms
0.8
0.6
1.6
1.1
2.8
1.7
0.7
0.5
3.0
2.0
TLH
THL
Output skew between receivers
t
(o)
Waveform 3
0.4
1.5
1.5
SK
1
in same package
B PORT LIMITS
T
V
= 0 to 70°C,
= 3.3V±10%,
amb
CC
SYMBOL
T
= +25°C, V = 3.3V,
CC
amb
C
PARAMETER
TEST CONDITION
UNIT
= 30pF, R = 9Ω
D
U
C
= 30pF, R = 9Ω
D
U
t
t
Propagation delay,
AIn to Bn
3.2
2.9
4.1
3.6
5.0
4.4
2.9
2.7
5.8
4.9
PLH
PHL
Waveform 1, 2
Waveform 2
Waveform 1
ns
ns
ns
ns
t
t
Enable/disable time,
OEB0 to Bn
3.9
3.5
4.7
4.4
5.5
5.4
3.5
3.2
6.4
5.9
PLH
PHL
t
t
Enable/disable time,
OEB1 to Bn
4.1
3.0
5.0
3.9
5.9
4.8
3.8
2.6
6.6
5.5
PLH
PHL
t
t
Transition time, Bn Port
(1.3V to 1.8V)
Test Circuit and
Waveforms
1.3
0.4
1.9
0.8
2.8
1.4
1.2
0.4
3.0
1.5
TLH
THL
Output skew between drivers in
same package
t
(o)
Waveform 3
TEST CONDITION
Waveform 1, 2
0.3
1.4
1.4
ns
UNIT
ns
SK
1
SYMBOL
PARAMETER
R
= 16.5Ω
R = 16.5Ω
U
U
t
t
Propagation delay,
AIn to Bn
3.2
2.9
4.1
3.6
5.0
4.9
2.9
2.6
5.8
4.9
PLH
PHL
t
t
Enable/disable time,
OEB0 to Bn
3.9
3.5
4.7
4.4
5.5
5.4
3.5
3.2
6.4
5.9
PLH
PHL
Waveform 2
Waveform 1
ns
ns
ns
ns
t
t
Enable/disable time,
OEB1 to Bn
4.1
3.0
5.0
3.9
5.9
4.8
3.8
2.6
6.6
5.5
PLH
PHL
t
t
Transition time, Bn Port
(1.3V to 1.8V)
Test Circuit and
Waveforms
1.3
0.4
1.9
0.8
2.8
1.4
1.2
0.4
3.0
1.5
TLH
THL
Output skew between drivers in
t
(o)
Waveform 3
0.3
1.4
1.4
SK
1
same package
NOTES:
1.
t
actual – t actual for any data input to output path compared to any other data input to output path where N and M are either LH or
PN PM
HL. Skew times are valid only under same test conditions (temperature, V , loading, etc.).
CC
9
1998 Aug 12
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
FBL22041
AC WAVEFORMS
AIn, Bn
OEB0
V
t
V
V
V
M
AIn, Bn or Bn
OEBn
M
M
M
t
t
PHL
PLH
PHL
t
PLH
V
V
M
AOn, Bn
V
V
M
M
M
AOn or Bn
Waveform 1. Propagation Delay for Data
or Output Enable to Output
Waveform 2. Propagation Delay for Data
or Output Enable to Output
V
t
AIn, Bn
M
(o)
SK
AOn, Bn
V
M
V
t
V
M
Waveform 3. Output Skews
M
OEA
AOn
V
V
OEA
AOn
M
M
PZL
t
t
t
PLZ
PZH
PHZ
V
-0.3V
OV
OH
V
M
V
V
+0.3V
M
OL
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
NOTE:
V
= 1.55V for Bn, V = 1.5V for all others.
M M
SG00086
10
1998 Aug 12
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus+ transceiver (standard A-port)
FBL22041
TEST CIRCUIT AND WAVEFORMS
V
CC
BIAS
V
6.0V
t
W
V
IN
90%
90%
NEGATIVE
PULSE
R
R
L
L
V
V
M
M
V
V
OUT
IN
PULSE
GENERATOR
10%
10%
D.U.T.
LOW V
t
t
(t )
r
t
(t )
f
TLH
THL
R
T
C
L
(t )
t
90%
M
(t )
r
THL
f
TLH
V
IN
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs on A Port
SWITCH POSITION FOR ALL A-PORTS
10%
10%
LOW V
t
W
V
= 1.55V for Bn, V = 1.5V for all others.
M
M
TEST
SWITCH
OPEN
Input Pulse Definitions
t
t
t
PLH, PHL
t
CLOSED
PLZ, PZL
INPUT PULSE REQUIREMENTS
Family
FB+
t
t
GND
PHZ, PZH
Amplitude Low V
Rep. Rate
t
t
t
THL
W
TLH
2.0V (for R = 9 Ω)
U
500ns 2.5ns 2.5ns
500ns 2.5ns 2.5ns
A Port
B Port
3.0V
2.0V
0.0V
1.0V
1MHz
1MHz
V
CC
2.1V (for R = 16.5 Ω)
BIAS
V
U
R
U
V
V
OUT
IN
DEFINITIONS:
PULSE
GENERATOR
D.U.T.
R
C
=
=
Load Resistor; see AC CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
L
L
R
T
C
D
R
C
=
=
Termination resistance should be equal to Z
Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
of pulse generators.
T
D
OUT
R
=
Pull up resistor; see AC CHARACTERISTICS for value.
U
Test Circuit for Outputs on B Port
SG00090
11
1998 Aug 12
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus + transceiver (standard A-port)
FBL22041
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
SOT379-1
12
1998 Aug 12
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus + transceiver (standard A-port)
FBL22041
NOTES
13
1998 Aug 12
Philips Semiconductors
Product specification
3.3V BTL 7-bit Futurebus + transceiver (standard A–Port)
74FBL22041
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-04279
Document order number:
Philips
Semiconductors
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