GTL2002DP [NXP]
2-bit bi-directional low voltage translator; 2位双向低电压转换
| 型号： | GTL2002DP |
| 厂家： | 
NXP |
| 描述： | 2-bit bi-directional low voltage translator |
| 文件： | 总14页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
GTL2002
2-bit bi-directional low voltage translator
Product data sheet
2004 Sep 29
Supersedes data of 2003 Apr 01
Philips
Semiconductors
Philips Semiconductors
Product data sheet
2-bit bi-directional low voltage translator
GTL2002
FEATURES
DESCRIPTION
The Gunning Transceiver Logic — Transceiver Voltage Clamps
• 2-bit bi-directional low voltage translator
(GTL–TVC) provide high-speed voltage translation with low
ON-state resistance and minimal propagation delay. The GTL2002
provides 2 NMOS pass transistors (Sn and Dn) with a common gate
• Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V, 3.3 V, and 5 V buses which allows direct interface with GTL,
GTL+, LVTTL/TTL and 5 V CMOS levels
(G
) and a reference transistor (S
REF
and D ). The device
REF
REF
allows bi-directional voltage translations between 1.0 V and 5.0 V
without use of a direction pin.
• Provides bi-directional voltage translation with no direction pin
• Low 6.5 Ω RDS resistance between input and output pins
ON
When the Sn or Dn port is LOW the clamp is in the ON-state and a
low resistance connection exists between the Sn and Dn ports.
Assuming the higher voltage is on the Dn port, when the Dn port is
high, the voltage on the Sn port is limited to the voltage set by the
(Sn/Dn)
• Supports hot insertion
• No power supply required - Will not latch up
• 5 V tolerant inputs
reference transistor (S
). When the Sn port is high, the Dn port is
REF
pulled to V by the pull up resistors. This functionality allows a
CC
seamless translation between higher and lower voltages selected by
the user, without the need for directional control.
• Low stand-by current
All transistors have the same electrical characteristics and there is
minimal deviation from one output to another in voltage or
propagation delay. This is a benefit over discrete transistor voltage
translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical,
• Flow-through pinout for ease of printed circuit board trace routing
• ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V per JESD22-C101
• Packages offered: SO8, TSSOP8 (MSOP8), VSSOP8
S
REF
and D
can be located on any of the other two matched
REF
Sn/Dn transistors, allowing for easier board layout. The translator’s
transistors provides excellent ESD protection to lower voltage
devices and at the same time protect less ESD resistant devices.
APPLICATIONS
• Any application that requires bi-directional or unidirectional
voltage level translation from any voltage between 1.0 V and 5.0 V
to any voltage between 1.0 V and 5.0 V
• The open drain construction with no direction pin is ideal for
bi-directional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V)
processor I C port translation to the normal 3.3 V or 5.0 V I C-bus
signal levels or GTL/GTL+ translation to LVTTL/TTL signal levels.
2
2
ORDERING INFORMATION
PACKAGES
8-Pin Plastic SO
TEMPERATURE RANGE
–40 °C to +85 °C
ORDER CODE
GTL2002D
TOPSIDE MARK
GTL2002
2002
DWG NUMBER
SOT96–1
8-Pin Plastic TSSOP (MSOP)
8-Pin Plastic VSSOP
–40 °C to +85 °C
GTL2002DP
GTL2002DC
SOT505–1
SOT765–1
–40 °C to +85 °C
2002
Standard packing quantities and other packaging data is available at www.standardproducts.philips.com/packaging.
2
2004 Sep 29
Philips Semiconductors
Product data sheet
2-bit bi-directional low voltage translator
GTL2002
PIN CONFIGURATION
FUNCTION TABLE
LOW-to-HIGH translation assuming Dn is at the higher voltage level
G
D
S
REF
In-Sn
Out-Dn
Transistor
Off
REF
REF
1
2
3
8
7
GND
G
REF
H
H
0 V
X
X
S
D
REF
REF
1
H
H
L
H
H
L
V
V
TT
H
nearly off
On
TT
TT
S
6
5
D
1
1
2
2
V
L
L
S
D
2
4
0 – V
X
X
Off
TT
SA00640
H
L
X
=
=
=
HIGH voltage level
LOW voltage level
Don’t Care
Figure 1. SO8 and TSSOP8 pinning
NOTES:
1. Dn is pulled up to V through an external resistor.
CC
2. Dn follows the Sn input LOW.
3. G
should be at least 1.5 V higher than S
for best
REF
REF
1
2
3
8
7
S
G
D
REF
REF
translator operation.
S
1
4. V is equal to the S
voltage.
REF
TT
REF
S
2
6
5
D
1
GND
D
2
4
CLAMP SCHEMATIC
SA00658
D
G
REF
D1
D2
REF
Figure 2. VSSOP8 pinning
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
SO8 and
TSSOP8
VSSOP8
1
2
4
1
GND
Ground (0 V)
S
REF
Source of reference transistor
S
S1
S2
REF
3, 4
5, 6
7
2, 3
5, 6
7
S
Port S and Port S
1 2
n
D
Port D and Port D
1 2
SA00645
n
D
Drain of reference transistor
Gate of reference transistor
REF
REF
Figure 3. Clamp schematic
8
8
G
FUNCTION TABLE
HIGH-to-LOW translation assuming Dn is at the higher voltage level
G
D
S
REF
In-Dn
Out-Sn
Transistor
REF
REF
H
H
0 V
X
H
L
X
Off
On
On
Off
1
H
H
L
H
H
L
V
TT
V
TT
V
TT
2
L
0 – V
X
X
TT
H
L
X
=
=
=
HIGH voltage level
LOW voltage level
Don’t Care
NOTES:
1. Sn is not pulled up or pulled down.
2. Sn follows the Dn input LOW.
3. G
should be at least 1.5 V higher than S
for best
REF
REF
translator operation.
4. V is equal to the S
voltage.
TT
REF
3
2004 Sep 29
Philips Semiconductors
Product data sheet
2-bit bi-directional low voltage translator
GTL2002
APPLICATIONS
Bi-directional translation
For the bi-directional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the G
input must be
REF
connected to D
and both pins pulled to HIGH side V through a pull-up resistor (typically 200 kΩ). A filter capacitor on D
is
REF
REF
CC
recommended. The processor output can be totem pole or open drain (pull-up resistors may be required) and the chipset output can be totem
pole or open drain (pull-up resistors are required to pull the Dn outputs to V ). However, if either output is totem pole, data must be
CC
uni-directional or the outputs must be 3-statable and the outputs must be controlled by some direction control mechanism to prevent
HIGH-to-LOW contentions in either direction. If both outputs are open drain, no direction control is needed. The opposite side of the reference
transistor (S
) is connected to the processor core power supply voltage. When D
is connected through a 200 kΩ resistor to a 3.3 V to
REF
REF
5.5 V V supply and S
is set between 1.0 V to V – 1.5 V, the output of each Sn has a maximum output voltage equal to S
and the
REF
CC
REF
CC
output of each Dn has a maximum output voltage equal to V
.
CC
TYPICAL BI-DIRECTIONAL VOLTAGE TRANSLATION
1.8 V
1.5 V
5 V
200 kΩ
1.2 V
1.0 V
GTL2002
TOTEM POLE OR
OPEN DRAIN I/O
GND
G
D
REF
S
V
REF
CORE
V
REF
D1
CC
S1
S2
CPU I/O
CHIPSET I/O
D2
3.3 V
INCREASE BIT
SIZE BY USING
10 BIT GTL2010 OR
22 BIT GTL2000
V
CC
S3
D3
D4
CHIPSET I/O
S4
S5
D5
Dn
Sn
SA00642
2
Figure 4. Bi-directional translation to multiple higher voltage levels such as an I C-bus application
4
2004 Sep 29
Philips Semiconductors
Product data sheet
2-bit bi-directional low voltage translator
GTL2002
Uni-directional down translation
For uni-directional clamping, higher voltage to lower voltage, the G
input must be connected to D
and both pins pulled to the higher side
REF
REF
V
CC
through a pull-up resistor (typically 200 kΩ). A filter capacitor on D
is recommended. Pull-up resistors are required if the chipset I/O are
REF
open drain. The opposite side of the reference transistor (S
) is connected to the processor core supply voltage. When D
is connected
REF
REF
through a 200 kΩ resistor to a 3.3 V to 5.5 V V supply and S
is set between 1.0 V to V – 1.5 V, the output of each Sn has a maximum
CC
CC
REF
output voltage equal to S
.
REF
TYPICAL UNI-DIRECTIONAL – HIGH TO LOW VOLTAGE TRANSLATION
1.8 V
1.5 V
5 V
200 kΩ
1.2 V
1.0 V
GTL2002
GND
G
D
REF
EASY MIGRATION TO
LOWER VOLTAGE AS PRO-
CESSOR GEOMETRY
SHRINKS.
S
V
REF
REF
V
CORE
CC
S1
S2
D1
D2
CPU I/O
CHIPSET I/O
TOTEM POLE I/O
SA00643
Figure 5. Uni-directional down translation, to protect low voltage processor pins
Uni-directional up translation
For uni-directional up translation, lower voltage to higher voltage, the reference transistor is connected the same as for a down translation.
A pull-up resistor is required on the higher voltage side (Dn or Sn) to get the full HIGH level, since the GTL–TVC device will only pass the
reference source (S
open drain.
) voltage as a HIGH when doing an up translation. The driver on the lower voltage side only needs pull-up resistors if it is
REF
TYPICAL UNI-DIRECTIONAL – LOW TO HIGH VOLTAGE TRANSLATION
1.8 V
5 V
1.5 V
200 kΩ
1.2 V
GTL2002
1.0 V
GND
G
D
REF
EASY MIGRATION TO
LOWER VOLTAGE AS PRO-
CESSOR GEOMETRY
SHRINKS.
S
V
REF
REF
V
CORE
CC
S1
S2
D1
D2
CPU I/O
CHIPSET I/O
TOTEM POLE I/O
OR OPEN DRAIN
SA00644
Figure 6. Uni-directional up translation, to higher voltage chip sets
5
2004 Sep 29
Philips Semiconductors
Product data sheet
2-bit bi-directional low voltage translator
GTL2002
Sizing pull-up resistor
The pull-up resistor value needs to limit the current through the pass transistor when it is in the “on” state to about 15 mA. This will guarantee a
pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage will also be higher in the
“on” state. To set the current through each pass transistor at 15 mA, the pull-up resistor value is calculated as follows:
Pull–up voltage (V)*0.35 V
Resistor value (W) +
0.015 A
The table below summarizes resistor values for various reference voltages and currents at 15 mA and also at 10 mA and 3 mA. The resistor
value shown in the +10 % column or a larger value should be used to ensure that the pass voltage of the transistor would be 350 mV or less.
The external driver must be able to sink the total current from the resistors on both sides of the GTL–TVC device at 0.175 V, although the 15 mA
only applies to current flowing through the GTL–TVC device. See Application Note AN10145-01 Bi-Directional Voltage Translators for more
information.
PULL-UP RESISTOR VALUES
PULL-UP RESISTOR VALUE (Ω)
15 mA
10 mA
3 mA
VOLTAGE
NOMINAL
310
+ 10 %
341
217
158
106
85
NOMINAL
465
+ 10 %
512
325
237
160
127
94
NOMINAL
1550
983
+ 10 %
1705
1082
788
5.0 V
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
197
295
143
215
717
97
145
483
532
77
115
383
422
57
63
85
283
312
NOTES:
1. Calculated for V = 0.35 V
OL
2. Assumes output driver V = 0.175 V at stated current
OL
3. +10 % to compensate for V range and resistor tolerance.
DD
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC source reference voltage
DC drain reference voltage
DC gate reference voltage
CONDITIONS
RATING
UNIT
V
V
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +7.0
–50
V
V
SREF
DREF
GREF
V
V
V
DC voltage Port S
V
Sn
Dn
n
V
DC voltage Port D
V
n
I
DC diode current on reference pins
DC diode current Port S
V < 0 V
I
mA
mA
mA
mA
°C
REFK
I
V < 0 V
I
–50
SK
DK
n
I
DC diode current Port D
V < 0 V
I
–50
n
I
DC clamp current per channel
Storage temperature range
Channel in ON-state
±128
MAX
T
stg
–65 to +150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
6
2004 Sep 29
Philips Semiconductors
Product data sheet
2-bit bi-directional low voltage translator
GTL2002
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
Min
0
Max
5.5
5.5
5.5
5.5
64
V
I/O
Input/output voltage (Sn, Dn)
V
V
1
V
DC source reference voltage
DC drain reference voltage
0
SREF
DREF
GREF
PASS
V
V
0
V
DC gate reference voltage
0
V
I
Pass transistor current
—
–40
mA
°C
T
amb
Operating ambient temperature range In free air
+85
NOTE:
1. V
≤ V
– 1.5 V for best results in level shifting applications.
SREF
DREF
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
= 1.365 V; V or V = 0.175 V;
UNIT
MAX
1
MIN
TYP
V
= 3.0 V; V
SREF
= 15.2 mA
DD
Sn
Dn
V
OL
LOW-level output voltage
—
260
350
mV
I
clamp
V
Input clamp voltage
Gate input leakage
Gate capacitance
Off capacitance
I = –18 mA
V
V
= 0 V
= 0 V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–1.2
5
V
IK
I
GREF
I
IH
V = 5 V
I
µA
pF
pF
pF
GREF
C
C
V = 3 V or 0 V
I
19.4
7.4
18.6
3.5
4.4
5.5
67
—
—
—
5
I(GREF)
IO(OFF)
V
O
V
O
= 3 V or 0 V
= 3 V or 0 V
V
GREF
V
GREF
V
GREF
V
GREF
V
GREF
V
GREF
V
GREF
V
GREF
V
GREF
V
GREF
= 0 V
= 3 V
C
On capacitance
IO(ON)
= 4.5 V
= 3 V
7
I
= 64 mA
Ω
O
= 2.3 V
= 1.5 V
= 1.5 V
= 4.5 V
= 3 V
9
V = 0 V
I
105
15
10
80
70
2
r
On-resistance
on
I
I
= 30 mA
= 15 mA
9
Ω
Ω
O
7
V = 2.4 V
I
58
O
V = 1.7 V
I
= 2.3 V
50
NOTES:
1. All typical values are measured at T
= 25 °C
amb
2. Measured by the voltage drop between the Sn and the Dn terminals at the indicated current through the switch.
On-state resistance is determined by the lowest voltage of the two (Sn or Dn) terminals.
7
2004 Sep 29
Philips Semiconductors
Product data sheet
2-bit bi-directional low voltage translator
GTL2002
AC CHARACTERISTICS FOR TRANSLATOR TYPE APPLICATIONS
V
REF
= 1.365 V to 1.635 V; V
= 3.0 V to 3.6 V; V
= 2.36 V to 2.64 V; GND = 0 V; t = t ≤ 3.0 ns. Refer to the Test Circuit diagram.
DD1
DD2
r
f
LIMITS
T
amb
= –40 °C to +85 °C
SYMBOL
PARAMETER
WAVEFORM
UNIT
1
MIN
TYP
MAX
5.5
Propagation delay
Sn to Dn; Dn to Sn
2
t
0.5
1.5
ns
PLH
NOTES:
1. All typical values are measured at V
= 3.3 V, V
= 2.5 V, V
= 1.5 V and T = 25 °C.
amb
DD1
DD2
REF
2. Propagation delay guaranteed by characterization.
3. C of 30 pF and a C of 15 pF is guaranteed by design.
ON(max)
OFF(max)
AC WAVEFORMS
TEST CIRCUIT
V
= 1.5 V; V = GND to 3.0 V
M
IN
V
V
V
V
DD2
DD1
DD2
DD2
200 kΩ
150 Ω
150 Ω
150 Ω
V
I
INPUT
GND
V
V
M
M
DUT
t
t
PLH
PHL
0
0
V
DD2
D
G
REF
D
D
2
REF
1
TEST JIG OUTPUT
HIGH-to-LOW
V
t
M
V
t
M
LOW-to-HIGH
V
OL
PHL
PLH
t
PHL
t
PLH
1
1
V
DD2
S
REF
DUT OUTPUT
HIGH-to-LOW
LOW-to-HIGH
S
S
2
1
V
M
V
M
V
OL
V
REF
TEST
JIG
SA00659
Waveform 1. The Input (S ) to Output (D ) propagation delays
n
n
PULSE
GENERATOR
SA00646
Waveform 2. Load circuit
8
2004 Sep 29
Philips Semiconductors
Product data sheet
2-bit bi-directional low voltage translator
GTL2002
AC CHARACTERISTICS FOR CBT TYPE APPLICATION
GND = 0 V; t C = 50 pF
R;
L
LIMITS
= –40 °C to +85 °C
T
amb
SYMBOL
PARAMETER DESCRIPTION
UNITS
G
= 5 V ± 0.5 V
REF
Min
Mean
Max
1
t
pd
Propagation delay
—
—
250
ps
NOTES:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
AC WAVEFORMS
TEST CIRCUIT AND WAVEFORMS
V
= 1.5 V; V = GND to 3.0 V
M
IN
7 V
500 Ω
S1
3 V
0 V
From Output
Under Test
Open
GND
1.5 V
1.5 V
500 Ω
C
= 50 pF
L
INPUT
t
t
PHL
PLH
Load Circuit
V
OH
1.5 V
1.5 V
TEST
S1
OUTPUT
t
open
7 V
pd
V
OL
t
/t
PLZ PZL
SA00639
t
/t
open
PHZ PZH
Waveform 3. Input (Sn) to Output (Dn) Propagation Delays
DEFINITIONS
C
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
L
SA00012
Waveform 4. Load circuit
9
2004 Sep 29
Philips Semiconductors
Product data sheet
2-bit bi-directional low voltage translator
GTL2002
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
10
2004 Sep 29
Philips Semiconductors
Product data sheet
2-bit bi-directional low voltage translator
GTL2002
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
11
2004 Sep 29
Philips Semiconductors
Product data sheet
2-bit bi-directional low voltage translator
GTL2002
VSSOP8: plastic very thin shrink small outline package; body width 2.3 mm
SOT765-1
12
2004 Sep 29
Philips Semiconductors
Product data sheet
2-bit bi-directional low voltage translator
GTL2002
REVISION HISTORY
Rev
Date
Description
_3
20040929
Product data (9397 750 13058). Supersedes data of 2003 Apr 01 (9397 750 11349).
Modifications:
• “Features” section on page 2, last bullet: add “(MSOP8)”
• “Ordering information” table on page 2: add “(MSOP)” to cell 8-Pin Plastic TSSOP in Packages column.
• Add VSSOP8 package offering.
_2
_1
20030401
20000816
Product data (9397 750 11349); ECN 853-2214 29603 Dated 28 February 2003.
Supersedes data dated 2000 Aug 16 (9397 750 07417).
Product data (9397 750 07417); ECN 853-2214 24367 dated 2000 Aug 16.
13
2004 Sep 29
Philips Semiconductors
Product data sheet
2-bit bi-directional low voltage translator
GTL2002
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data sheet
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data sheet
Product data sheet
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2004
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 09-04
9397 750 13058
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
相关型号：
GTL2002DP/S440,118
IC SPECIALTY INTERFACE CIRCUIT, PDSO8, 3 MM WIDTH, PLASTIC, SOT505-1, TSSOP-8, Interface IC:Other
NXP
©2020 ICPDF网 联系我们和版权申明