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GTL2018PW,112 [NXP]

GTL2018 - 8-bit LVTTL to GTL transceiver TSSOP2 24-Pin;
GTL2018PW,112
型号： GTL2018PW,112
厂家： NXP    NXP
描述：

GTL2018 - 8-bit LVTTL to GTL transceiver TSSOP2 24-Pin

光电二极管 接口集成电路
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GTL2018  
8-bit LVTTL to GTL transceiver  
Rev. 2 — 29 August 2011  
Product data sheet  
1. General description  
The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system  
interface with a GTL/GTL/GTL+ bus.  
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling  
receiver or as an LVTTL-to-GTL interface.  
The GTL2018 LVTTL inputs (only) are tolerant up to 5.5 V, allowing direct access to TTL  
or 5 V CMOS inputs.  
2. Features and benefits  
Operates as an octal GTL/GTL/GTL+ sampling receiver or as an LVTTL to  
GTL/GTL/GTL+ driver  
3.0 V to 3.6 V operation with 5 V tolerant LVTTL input  
GTL input and output 3.6 V tolerant  
Vref adjustable from 0.5 V to 0.5VCC  
Partial power-down permitted  
Latch-up protection exceeds 100 mA per JESD78  
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per  
JESD22-CC101  
AEC-Q100 compliance available  
Package offered: TSSOP24  
3. Quick reference data  
Table 1.  
Symbol  
Ci  
Quick reference data  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
input capacitance  
control inputs;  
-
2
2.5  
pF  
VI = 3.0 V or 0 V  
Cio  
input/output capacitance  
A port; VO = 3.0 V or 0 V  
B port; VO = VTT or 0 V  
-
-
4.6  
3.4  
6
pF  
pF  
4.3  
GTL; Vref = 0.8 V; VTT = 1.2 V  
tPLH  
tPHL  
tPLH  
tPHL  
LOW to HIGH propagation delay  
An to Bn; see Figure 3  
An to Bn; see Figure 3  
Bn to An; see Figure 4  
Bn to An; see Figure 4  
-
-
-
-
2.8  
3.4  
5.2  
4.9  
5
7
8
7
ns  
ns  
ns  
ns  
HIGH to LOW propagation delay  
LOW to HIGH propagation delay  
HIGH to LOW propagation delay  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
4. Ordering information  
Table 2.  
Ordering information  
Tamb = 40 C to +85 C.  
Type number  
Topside mark  
Package  
Name  
Description  
Version  
GTL2018PW  
GTL2018PW/Q900[1]  
GTL2018PW  
TSSOP24  
plastic thin shrink small outline package; 24 leads;  
body width 4.4 mm  
SOT355-1  
[1] GTL2018PW/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP.  
5. Functional diagram  
GTL2018  
&
B0  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
&
B1  
&
B2  
&
B3  
&
B4  
&
B5  
&
B6  
&
B7  
002aab603  
VREF  
DIR  
Fig 1. Logic diagram of GTL2018  
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
2 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
6. Pinning information  
6.1 Pinning  
1
2
24  
V
GND  
B0  
CC  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
A0  
A1  
A2  
A3  
GND  
A4  
A5  
A6  
A7  
3
B1  
4
B2  
5
B3  
6
VREF  
GND  
B4  
GTL2018PW  
GTL2018PW/Q900  
7
8
9
B5  
10  
11  
12  
B6  
B7  
V
CC  
GND  
DIR  
002aab604  
Fig 2. Pin configuration for TSSOP24  
6.2 Pin description  
Table 3.  
Pin description  
Symbol  
GND  
B0  
Pin  
Description  
1, 7, 12, 19  
ground (0 V)  
2
data inputs/outputs (B side, GTL)  
B1  
3
B2  
4
B3  
5
B4  
8
B5  
9
B6  
10  
11  
6
B7  
VREF  
DIR  
VCC  
A7  
GTL reference voltage  
13  
14, 24  
15  
16  
17  
18  
20  
21  
22  
23  
direction control input (LVTTL)  
positive supply voltage  
data inputs/outputs (A side, LVTTL)  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
3 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
7. Functional description  
Refer to Figure 1 “Logic diagram of GTL2018”.  
7.1 Function table  
Table 4.  
Function table  
H = HIGH voltage level; L = LOW voltage level.  
Input  
DIR  
H
Input/output  
An (LVTTL)  
input  
Bn (GTL)  
Bn = An  
input  
L
An = Bn  
8. Limiting values  
Table 5.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC  
IIK  
Parameter  
Conditions  
Min  
0.5  
-
0.5[1]  
0.5[1]  
-
Max  
4.6  
Unit  
V
supply voltage  
input clamping current  
input voltage  
VI < 0 V  
A port  
50  
7.0  
mA  
V
VI  
B port  
4.6  
V
IOK  
VO  
output clamping current  
output voltage  
VO < 0 V  
50  
7.0  
mA  
V
output in OFF or  
0.5[1]  
HIGH state; A port  
output in OFF or  
0.5[1]  
4.6  
V
HIGH state; B port  
[2]  
[2]  
[3]  
[4]  
IOL  
LOW-level output current  
A port  
B port  
A port  
-
32  
mA  
mA  
mA  
C  
-
80  
IOH  
HIGH-level output current  
storage temperature  
-
32  
+150  
Tstg  
60  
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current  
ratings are observed.  
[2] Current into any output in the LOW state.  
[3] Current into any output in the HIGH state.  
[4] The performance capability of a high-performance integrated circuit in conjunction with its thermal  
environment can create junction temperatures which are detrimental to reliability. The maximum junction  
temperature of this integrated circuit should not exceed 150 C.  
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
4 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
9. Recommended operating conditions  
Table 6.  
Recommended operating conditions[1]  
Symbol Parameter  
Conditions  
Min  
Typ  
-
Max  
3.6  
Unit  
V
VCC  
VTT  
supply voltage  
termination voltage[2] GTL  
3.0  
0.85  
0.9  
1.2  
1.5  
0.95  
1.26  
1.65  
V
GTL  
1.14  
V
GTL+  
1.35  
V
Vref  
reference voltage  
overall  
0.5  
2⁄3VTT 0.5VCC  
V
GTL  
0.5  
0.6  
0.8  
1.0  
VTT  
3.3  
-
0.63  
V
GTL  
0.76  
0.84  
V
GTL+  
0.87  
1.10  
V
VI  
input voltage  
B port  
0
3.6  
V
[3]  
except B port  
B port  
0
5.5  
V
VIH  
VIL  
HIGH-level input  
voltage  
Vref + 0.050  
-
V
except B port  
B port  
2
-
-
-
V
LOW-level input  
voltage  
-
Vref 0.050  
0.8  
V
except B port  
A port  
-
-
V
IOH  
IOL  
HIGH-level output  
current  
-
-
16  
mA  
LOW-level output  
current  
B port  
A port  
-
-
-
-
40  
mA  
mA  
C  
-
16  
Tamb  
ambient temperature  
operating in  
free air  
40  
+85  
[1] Unused inputs must be held HIGH or LOW to prevent them from floating.  
[2] TT maximum of 3.6 V with resistor sized to so IOL maximum is not exceeded.  
V
[3] A0 to A7 VI(max) is 3.6 V if configured as outputs (DIR = LOW).  
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
5 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
10. Static characteristics  
Table 7.  
Static characteristics  
Recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 40 C to +85 C.  
Symbol Parameter  
VOH HIGH-level output  
Conditions  
Min  
Typ[1]  
-
Max  
-
Unit  
V
[2]  
[2]  
[2]  
[2]  
[2]  
[2]  
A port; VCC = 3.0 V to 3.6 V; IOH = 100 A  
A port; VCC = 3.0 V; IOH = 16 mA  
B port; VCC = 3.0 V; IOL = 40 mA  
A port; VCC = 3.0 V; IOL = 8 mA  
A port; VCC = 3.0 V; IOL = 12 mA  
A port; VCC = 3.0 V; IOL = 16 mA  
VCC 0.2  
voltage  
2.0  
-
-
V
VOL  
LOW-level output  
voltage  
-
-
-
-
-
0.23  
0.28  
0.40  
0.55  
-
0.4  
0.4  
0.55  
0.8  
1  
V
V
V
V
II  
input current  
control inputs; VCC = 3.6 V;  
VI = VCC or GND  
A  
B port; VCC = 3.6 V; VI = VTT or GND  
A port; VCC = 0 V or 3.6 V; VI = 5.5 V  
A port; VCC = 3.6 V; VI = VCC  
-
-
-
-
-
-
-
-
-
-
1  
A  
A  
A  
A  
A  
10  
1  
A port; VCC = 3.6 V; VI = 0 V  
5  
IOZ  
ICC  
off-state output  
current  
A port; VCC = 0 V; VI or VO = 0 V to 3.6 V  
100  
supply current  
A port; VCC = 3.6 V; VI = VCC or GND;  
IO = 0 mA  
-
-
-
8
8
-
12  
mA  
mA  
A  
B port; VCC = 3.6 V; VI = VTT or GND;  
IO = 0 mA  
12  
[3]  
ICC  
additional supply  
current  
per input; A port or control inputs;  
VCC = 3.6 V; VI = VCC 0.6 V  
500  
Ci  
input capacitance  
control inputs; VI = 3.0 V or 0 V  
A port; VO = 3.0 V or 0 V  
B port; VO = VTT or 0 V  
-
-
-
2
2.5  
6
pF  
pF  
pF  
Cio  
input/output  
capacitance  
4.6  
3.4  
4.3  
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 C.  
[2] The input and output voltage ratings my be exceeded if the input and output current ratings are observed.  
[3] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.  
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
6 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
11. Dynamic characteristics  
Table 8.  
Dynamic characteristics  
VCC = 3.3 V 0.3 V.  
Symbol Parameter  
GTL; Vref = 0.6 V; VTT = 0.9 V  
Conditions  
Min  
Typ[1]  
Max  
Unit  
tPLH  
tPHL  
tPLH  
tPHL  
LOW to HIGH propagation delay  
An to Bn; see Figure 3  
An to Bn; see Figure 3  
Bn to An; see Figure 4  
Bn to An; see Figure 4  
-
-
-
-
2.8  
3.3  
5.3  
5.2  
5
7
8
8
ns  
ns  
ns  
ns  
HIGH to LOW propagation delay  
LOW to HIGH propagation delay  
HIGH to LOW propagation delay  
GTL; Vref = 0.8 V; VTT = 1.2 V  
tPLH  
tPHL  
tPLH  
tPHL  
LOW to HIGH propagation delay  
An to Bn; see Figure 3  
An to Bn; see Figure 3  
Bn to An; see Figure 4  
Bn to An; see Figure 4  
-
-
-
-
2.8  
3.4  
5.2  
4.9  
5
7
8
7
ns  
ns  
ns  
ns  
HIGH to LOW propagation delay  
LOW to HIGH propagation delay  
HIGH to LOW propagation delay  
GTL+; Vref = 1.0 V; VTT = 1.5 V  
tPLH  
tPHL  
tPLH  
tPHL  
LOW to HIGH propagation delay  
An to Bn; see Figure 3  
An to Bn; see Figure 3  
Bn to An; see Figure 4  
Bn to An; see Figure 4  
-
-
-
-
2.8  
3.4  
5.1  
4.7  
5
7
8
7
ns  
ns  
ns  
ns  
HIGH to LOW propagation delay  
LOW to HIGH propagation delay  
HIGH to LOW propagation delay  
[1] All typical values are at VCC = 3.3 V and Tamb = 25 C.  
11.1 Waveforms  
VM = 1.5 V at VCC 3.0 V; VM = 0.5VCC at VCC 2.7 V for A ports and control pins;  
VM = Vref for B ports.  
3.0 V  
input  
1.5 V  
1.5 V  
0 V  
V
t
t
PHL  
PLH  
t
p
3.0 V  
0 V  
OH  
output  
V
V
ref  
ref  
V
M
V
M
V
OL  
002aab141  
002aab140  
VM = 1.5 V for A port and Vref for B port  
a. Pulse duration  
A port to B port  
b. Propagation delay times  
Fig 3. Voltage waveforms  
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
7 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
V
1
TT  
input  
V
ref  
V
ref  
/ V  
3
TT  
t
t
PHL  
PLH  
V
OH  
OL  
output  
1.5 V  
1.5 V  
V
002aab142  
PRR 10 MHz; Zo = 50 ; tr 2.5 ns; tf 2.5 ns  
Fig 4. Propagation delay, Bn to An  
12. Test information  
V
CC  
V
V
I
O
PULSE  
GENERATOR  
DUT  
R
500 Ω  
C
L
50 pF  
L
R
T
002aab006  
Fig 5. Load circuitry for switching times  
V
TT  
V
CC  
25 Ω  
V
V
O
I
PULSE  
GENERATOR  
DUT  
C
30 pF  
L
R
T
002aab143  
RL = load resistor.  
CL = load capacitance; includes jib and probe capacitance.  
RT = termination resistance; should be equal to Zo of pulse generators.  
Fig 6. Load circuit for B outputs  
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
8 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
13. Package outline  
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm  
SOT355-1  
D
E
A
X
c
H
v
M
A
y
E
Z
13  
24  
Q
A
2
(A )  
3
A
A
1
pin 1 index  
θ
L
p
L
1
12  
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
8o  
0o  
0.15  
0.05  
0.95  
0.80  
0.30  
0.19  
0.2  
0.1  
7.9  
7.7  
4.5  
4.3  
6.6  
6.2  
0.75  
0.50  
0.4  
0.3  
0.5  
0.2  
mm  
1.1  
0.65  
0.25  
1
0.2  
0.13  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT355-1  
MO-153  
Fig 7. Package outline SOT355-1 (TSSOP24)  
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
9 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
14. Soldering of SMD packages  
This text provides a very brief insight into a complex technology. A more in-depth account  
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow  
soldering description”.  
14.1 Introduction to soldering  
Soldering is one of the most common methods through which packages are attached to  
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both  
the mechanical and the electrical connection. There is no single soldering method that is  
ideal for all IC packages. Wave soldering is often preferred when through-hole and  
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not  
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high  
densities that come with increased miniaturization.  
14.2 Wave and reflow soldering  
Wave soldering is a joining technology in which the joints are made by solder coming from  
a standing wave of liquid solder. The wave soldering process is suitable for the following:  
• Through-hole components  
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board  
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless  
packages which have solder lands underneath the body, cannot be wave soldered. Also,  
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,  
due to an increased probability of bridging.  
The reflow soldering process involves applying solder paste to a board, followed by  
component placement and exposure to a temperature profile. Leaded packages,  
packages with solder balls, and leadless packages are all reflow solderable.  
Key characteristics in both wave and reflow soldering are:  
• Board specifications, including the board finish, solder masks and vias  
• Package footprints, including solder thieves and orientation  
• The moisture sensitivity level of the packages  
• Package placement  
• Inspection and repair  
• Lead-free soldering versus SnPb soldering  
14.3 Wave soldering  
Key characteristics in wave soldering are:  
• Process issues, such as application of adhesive and flux, clinching of leads, board  
transport, the solder wave parameters, and the time during which components are  
exposed to the wave  
• Solder bath specifications, including temperature and impurities  
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
10 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
14.4 Reflow soldering  
Key characteristics in reflow soldering are:  
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to  
higher minimum peak temperatures (see Figure 8) than a SnPb process, thus  
reducing the process window  
• Solder paste printing issues including smearing, release, and adjusting the process  
window for a mix of large and small components on one board  
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is  
heated to the peak temperature) and cooling down. It is imperative that the peak  
temperature is high enough for the solder to make reliable solder joints (a solder paste  
characteristic). In addition, the peak temperature must be low enough that the  
packages and/or boards are not damaged. The peak temperature of the package  
depends on package thickness and volume and is classified in accordance with  
Table 9 and 10  
Table 9.  
SnPb eutectic process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (C)  
Volume (mm3)  
< 350  
350  
220  
< 2.5  
235  
220  
2.5  
220  
Table 10. Lead-free process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (C)  
Volume (mm3)  
< 350  
260  
350 to 2000  
> 2000  
260  
< 1.6  
260  
250  
245  
1.6 to 2.5  
> 2.5  
260  
245  
250  
245  
Moisture sensitivity precautions, as indicated on the packing, must be respected at all  
times.  
Studies have shown that small packages reach higher temperatures during reflow  
soldering, see Figure 8.  
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
11 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
maximum peak temperature  
= MSL limit, damage level  
temperature  
minimum peak temperature  
= minimum soldering temperature  
peak  
temperature  
time  
001aac844  
MSL: Moisture Sensitivity Level  
Fig 8. Temperature profiles for large and small components  
For further information on temperature profiles, refer to Application Note AN10365  
“Surface mount reflow soldering description”.  
15. Abbreviations  
Table 11. Abbreviations  
Acronym  
CDM  
CMOS  
DUT  
Description  
Charged-Device Model  
Complementary Metal-Oxide Semiconductor  
Device Under Test  
ESD  
ElectroStatic Discharge  
GTL  
Gunning Transceiver Logic  
Human Body Model  
HBM  
LVTTL  
PRR  
Low Voltage Transistor-Transistor Logic  
Pulse Repetition Rate  
TTL  
Transistor-Transistor Logic  
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
12 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
16. Revision history  
Table 12. Revision history  
Document ID  
GTL2018 v.2  
Modifications:  
Release date  
Data sheet status  
Change notice  
Supersedes  
20110829  
Product data sheet  
-
GTL2018 v.1  
• Section 2 “Features and benefits”:  
–
6th bullet item corrected from “...exceeds 500 mA per JESD78” to “...exceeds 100 mA per  
JESD78”  
–
–
7th bullet item: removed phrase “200 V MM per JESD22-A115”  
added (new) 8th bullet item “AEC-Q100 compliance available”  
• Table 2 “Ordering information”:  
–
added type number GTL2018PW/Q900  
–
added Table note [1]  
• Figure 2 “Pin configuration for TSSOP24” modified: added type number GTL2018PW/Q900  
20070215 Product data sheet  
GTL2018 v.1  
-
-
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
13 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
17. Legal information  
17.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of an NXP Semiconductors product can reasonably be expected  
17.2 Definitions  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
17.3 Disclaimers  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
14 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
non-automotive qualified products in automotive equipment or applications.  
17.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
18. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
GTL2018  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 2 — 29 August 2011  
15 of 16  
GTL2018  
NXP Semiconductors  
8-bit LVTTL to GTL transceiver  
19. Contents  
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
7
7.1  
8
Functional description . . . . . . . . . . . . . . . . . . . 4  
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Recommended operating conditions. . . . . . . . 5  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Test information. . . . . . . . . . . . . . . . . . . . . . . . . 8  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9  
9
10  
11  
11.1  
12  
13  
14  
Soldering of SMD packages . . . . . . . . . . . . . . 10  
Introduction to soldering . . . . . . . . . . . . . . . . . 10  
Wave and reflow soldering . . . . . . . . . . . . . . . 10  
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 10  
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 11  
14.1  
14.2  
14.3  
14.4  
15  
16  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13  
17  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
17.1  
17.2  
17.3  
17.4  
18  
19  
Contact information. . . . . . . . . . . . . . . . . . . . . 15  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2011.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 29 August 2011  
Document identifier: GTL2018  

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