HEC4015BDB [NXP]
暂无描述;
| 型号： | HEC4015BDB |
| 厂家： | 
NXP |
| 描述： | 暂无描述 移位寄存器 |
| 文件： | 总5页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4015B
MSI
Dual 4-bit static shift register
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4015B
MSI
Dual 4-bit static shift register
present on D is shifted to the first register position, and all
the data in the register is shifted one position to the right
on the LOW-to-HIGH transition of CP. A HIGH on MR
clears the register and forces O0 to O3 to LOW,
independent of CP and D. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
DESCRIPTION
The HEF4015B is a dual edge-triggered 4-bit static shift
register (serial-to-parallel converter). Each shift register
has a serial data input (D), a clock input (CP), four fully
buffered parallel outputs (O0 to O3) and an overriding
asynchronous master reset input (MR). Information
Fig.2 Pinning diagram.
HEF4015BP(N):
HEF4015BD(F):
HEF4015BT(D):
16-lead DIL; plastic
(SOT38-1)
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic
(SOT109-1)
Fig.1 Functional diagram.
( ): Package Designator North America
PINNING
FAMILY DATA, IDD LIMITS category MSI
DA, DB
serial data input
See Family Specifications
MRA, MRB
CPA, CPB
master reset input (active HIGH)
clock input (LOW-to-HIGH
edge-triggered)
O0A, O1A, O2A, O3A parallel outputs
O0B, O1B, O2B, O3B parallel outputs
APPLICATION INFORMATION
Some examples of applications for the HEF4015B are:
• Serial-to-parallel converter
• Buffer stores
• General purpose register
January 1995
2
Philips Semiconductors
Product specification
HEF4015B
MSI
Dual 4-bit static shift register
LOGIC DIAGRAM (one register)
Fig.3 Logic diagram.
Note
FUNCTION TABLE
1. H = HIGH state (the more positive voltage)
INPUTS
D
OUTPUTS
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
n
CP
MR
O0
O1
O2
O3
1
D1
D2
D3
D4
L
D1
X
X
X
4.
5.
= positive-going transition
= negative-going transition
2
3
4
L
L
L
D2
D3
D4
D1
D2
D3
X
X
X
6. Dn = either HIGH or LOW
D1
D2
7. n = number of clock pulse transitions
D1
X
X
L
no change
X
H
L
L
L
L
January 1995
3
Philips Semiconductors
Product specification
HEF4015B
MSI
Dual 4-bit static shift register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
MIN.
TYP.
MAX.
Propagation delays
CP → On
HIGH to LOW
5
130
55
40
120
55
40
105
45
35
60
30
20
60
30
20
−15
−10
−5
20
10
8
260
110
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
103 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
93 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
78 ns + (0,55 ns/pF) CL
34 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
10
15
5
tPHL
240
110
80
LOW to HIGH
10
15
5
tPLH
tPHL
tTHL
tTLH
tsu
MR → On
210
90
HIGH to LOW
10
15
5
70
Output transition times
HIGH to LOW
120
60
10 ns + (1,0 ns/pF) CL
10
15
5
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
40
120
60
LOW to HIGH
10
15
5
40
Set-up time
25
25
20
40
20
15
60
30
20
80
30
24
50
30
20
7
D → CP
10
15
5
Hold time
D → CP
10
15
5
thold
tWCPL
tWMRH
tRMR
fmax
Minimum clock
30
15
10
40
15
12
20
10
5
see waveforms Figs 4 and 5
pulse width; LOW
10
15
5
Minimum MR
pulse width; HIGH
10
15
5
Recovery time
for MR
10
15
5
Maximum clock
pulse frequency
15
30
44
10
15
15
22
January 1995
4
Philips Semiconductors
Product specification
HEF4015B
MSI
Dual 4-bit static shift register
VDD
V
TYPICAL FORMULA FOR P (µW)
2
2
2
Dynamic power
dissipation per
package (P)
5
1 500 fi + ∑ (foCL) × VDD
6 300 fi + ∑ (foCL) × VDD
17 000 fi + ∑ (foCL) × VDD
where
10
15
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
Fig.4 Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are
shown as positive values but may be specified as negative values.
Fig.5 Waveforms showing recovery time for MR and minimum MR pulse width.
January 1995
5
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