HEF4015BT-T [NXP]
IC 4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT-109-1, SO-16, Shift Register;型号: | HEF4015BT-T |
厂家: | NXP |
描述: | IC 4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT-109-1, SO-16, Shift Register 光电二极管 输出元件 逻辑集成电路 触发器 |
文件: | 总15页 (文件大小:144K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HEF4015B
Dual 4-bit static shift register
Rev. 7 — 14 September 2011
Product data sheet
1. General description
The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel
converter). Each shift register has a serial data input (D), a clock input (CP), four fully
buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input
(MR). Information present on D is shifted to the first register position, and all the data in
the register is shifted one position to the right on the LOW-to-HIGH transition of CP. A
HIGH on MR clears the register and forces Q0 to Q3 to LOW, independent of CP and D.
The clock input’s Schmitt trigger action makes the input highly tolerant of slower clock rise
and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is
also suitable for use over the full industrial (40 C to +85 C) temperature range.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the automotive temperature range 40 C to +85 C.
Complies with JEDEC standard JESD 13-B
3. Applications
Serial-to-parallel converter
Buffer stores
General purpose register
4. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C.
Type number
Package
Name
Description
Version
HEF4015BP
HEF4015BT
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
SOT38-4
SOT109-1
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
5. Functional diagram
1Q0
1Q1
1Q2
5
4
3
7
1D
SHIFT
REGISTER
4 BITS
9
6
1CP
1MR
1Q3 10
2Q0 13
2Q1 12
2Q2 11
15 2D
SHIFT
REGISTER
4 BITS
1
2CP
2Q3
2
14 2MR
001aae560
Fig 1. Functional diagram
Q0
Q1
Q2
Q3
D
D
Q
D
Q
D
Q
D
Q
FF 1
CP
CD
FF 2
CP
CD
FF 3
FF 4
CP
CD
CP
CD
CP
MR
001aae562
Fig 2. Logic diagram for one register
HEF4015B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
2 of 15
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
6. Pinning information
6.1 Pinning
HEF4015B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2CP
2Q3
1Q2
1Q1
1Q0
1MR
1D
V
DD
2D
2MR
2Q0
2Q1
2Q2
1Q3
1CP
V
SS
001aae561
Fig 3. Pin configuration
6.2 Pin description
Table 2.
Symbol
1Q0 to 1Q3
2Q0 to 2Q3;
1MR, 2MR
1D, 2D
Pin description
Pin
Description
5, 4, 3, 10
parallel output
parallel output
13, 12, 11, 2
6, 14
7, 15
8
master reset input (active HIGH)
serial data input
VSS
ground supply voltage
1CP, 2CP
VDD
9, 1
16
clock input (LOW-to-HIGH edge-triggered)
supply voltage
7. Functional description
Table 3.
Function table [1]
number of clock
pulse transitions
Input
Output
CP
D
MR
L
Q0
Q1
Q2
Q3
1
2
3
4
D1
D2
D3
D4
X
D1
X
X
X
L
D2
D1
X
X
L
D3
D2
D1
X
L
D4
D3
D2
D1
L
no change
L
no change
L
no change
L
no change
L
X
X
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Dn = either HIGH or LOW;
= positive-going transition; = negative-going transition.
HEF4015B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
3 of 15
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
0.5
-
Max
+18
Unit
V
supply voltage
input clamping current
input voltage
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
10
mA
V
VI
0.5
-
VDD + 0.5
10
IOK
output clamping current
input/output current
supply current
mA
mA
mA
C
II/O
-
10
IDD
-
50
Tstg
Tamb
Ptot
storage temperature
ambient temperature
total power dissipation
65
40
+150
+85
C
Tamb = 40 C to +85 C
DIP16 package
SO16 package
per output
[1]
[2]
-
-
-
750
500
100
mW
mW
mW
P
power dissipation
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
15
Unit
supply voltage
3
-
-
-
-
-
-
V
VI
input voltage
0
VDD
+85
3.75
0.5
V
Tamb
ambient temperature
input transition rise and fall rate
in free air
40
C
t/V
VDD = 5 V
VDD = 10 V
VDD = 15 V
-
-
-
s/V
s/V
s/V
0.08
HEF4015B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
4 of 15
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = 40 C Tamb = 25 C
Tamb = 85 C Unit
Min
Max
-
Min
Max
-
Min
Max
VIH
HIGH-level input voltage
LOW-level input voltage
IO < 1 A
5 V
10 V
15 V
5 V
3.5
3.5
3.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
7.0
-
7.0
-
7.0
11.0
-
11.0
-
11.0
-
VIL
IO < 1 A
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
10 V
15 V
5 V
-
-
-
-
-
-
VOH
VOL
IOH
HIGH-level output voltage IO < 1 A
LOW-level output voltage IO < 1 A
4.95
4.95
4.95
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
14.95
-
14.95
-
14.95
-
-
0.05
0.05
0.05
1.7
0.52
1.3
3.6
-
-
0.05
0.05
0.05
1.4
0.44
1.1
3.0
-
-
0.05
0.05
0.05
10 V
15 V
5 V
-
-
-
-
-
-
HIGH-level output current VO = 2.5 V
-
-
-
1.1 mA
0.36 mA
0.9 mA
2.4 mA
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
5 V
-
-
-
10 V
15 V
5 V
-
-
-
-
-
-
IOL
LOW-level output current
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
0.52
0.44
0.36
-
-
-
mA
mA
mA
10 V
15 V
15 V
5 V
1.3
-
1.1
-
0.9
3.6
-
3.0
-
2.4
II
input leakage current
supply current
-
-
-
-
-
0.3
20
40
80
-
-
-
-
-
-
0.3
20
40
80
7.5
-
-
-
-
-
1.0 A
150 A
300 A
600 A
IDD
IO = 0 A
10 V
15 V
-
CI
input capacitance
-
pF
HEF4015B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
5 of 15
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
11. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; CL = 50 pF; Tamb = 25 C.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula[1] Min
Typ
130
55
40
105
45
35
120
55
40
60
30
20
15
10
5
20
10
8
Max
Unit
ns
tPHL
HIGH to LOW
nCP to Qn;
see Figure 4
103 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
78 ns + (0.55 ns/pF)CL
34 ns + (0.23 ns/pF)CL
27 ns + (0.16 ns/pF)CL
93 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
-
260
propagation delay
10 V
15 V
5 V
-
110
ns
-
80
ns
nMR to Qn;
see Figure 6
-
210
ns
10 V
15 V
5 V
-
90
ns
-
70
ns
tPLH
LOW to HIGH
nCP to Qn
see Figure 4
-
240
ns
propagation delay
10 V
15 V
5 V
-
110
ns
-
80
ns
tt
transition time
set-up time
hold time
see Figure 4
-
120
ns
10 V
15 V
5 V
-
60
40
-
ns
-
ns
tsu
nD to nCP;
see Figure 5
+25
+25
+20
40
20
15
60
30
20
80
30
24
50
30
20
7
ns
10 V
15 V
5 V
-
ns
-
ns
th
nD to nCP;
see Figure 5
-
ns
10 V
15 V
5 V
-
ns
-
ns
tW
pulse width
nCP LOW;
minimum width;
see Figure 5
30
15
10
40
15
12
20
10
5
-
ns
10 V
15 V
5 V
-
ns
-
ns
nMR HIGH;
minimum width;
see Figure 6
-
ns
10 V
15 V
5 V
-
ns
-
ns
trec
recovery time
pin nMR;
see Figure 6
-
ns
10 V
15 V
5 V
-
ns
-
ns
fmax
maximum frequency see Figure 5
15
30
44
-
MHz
MHz
MHz
10 V
15 V
15
22
-
-
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
HEF4015B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
6 of 15
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (W)
PD = 1500 fi + (fo CL) VDD
PD = 6300 fi + (fo CL) VDD
where:
2
2
PD
dynamic power
dissipation
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
10 V
15 V
2
PD = 17000 fi + (fo CL) VDD
VDD = supply voltage in V;
(CL fo) = sum of the outputs.
12. Waveforms
V
I
V
nCP input
M
V
SS
t
t
PLH
PHL
V
OH
90 %
V
nQn output
M
10 %
V
OL
t
t
t
t
001aaj464
Measurement points are given in Table 9.
Fig 4. Waveforms showing nCP propagation delays and nQn transition times
t
W
V
I
nCP input
V
V
V
M
M
M
V
SS
1/f
max
t
t
h
h
V
I
nD input
V
V
V
V
M
M
M
M
V
SS
t
t
su
su
001aae563
The shaded area indicates where the input is permitted to change for predictable output performance.
Set-up and hold times are shown as positive values but may be specified as negative values;
Measurement points are given in Table 9.
Fig 5. Waveforms showing set-up times, hold times, and minimum clock pulse width
HEF4015B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
7 of 15
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
V
I
nMR input
nCP input
V
M
V
M
V
V
SS
t
W
t
rec
V
I
V
M
SS
t
PHL
V
OH
nQn output
V
M
V
OL
001aae564
Measurement points are given in Table 9.
Fig 6. Waveforms showing MR recovery time, propagation delay and minimum pulse width
Table 9. Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
HEF4015B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
8 of 15
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
t
W
V
I
90 %
90 %
negative
pulse
V
V
V
M
M
10 %
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
90 %
positive
pulse
V
M
M
10 %
10 %
0 V
t
W
001aaj781
a. Input waveforms
V
DD
V
V
O
I
G
DUT
C
L
R
T
001aag182
b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test;
CL = load capacitance including jig and probe capacitance;
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 7. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VDD
Input
Load
CL
VI
tr, tf
5 V to 15 V
VSS or VDD
20 ns
50 pF
HEF4015B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
9 of 15
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 8. Package outline SOT38-4 (DIP16)
HEF4015B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
10 of 15
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 9. Package outline SOT109-1 (SO16)
HEF4015B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
11 of 15
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
14. Revision history
Table 11. Revision history
Document ID
Release date
20110914
Data sheet status
Change notice
Supersedes
HEF4015B v.7
Modifications:
Product data sheet
-
HEF4015B v.6
• Table 6: IOH minimum values changed to maximum
HEF4015B v.6
HEF4015B v.5
HEF4015B v.4
HEF4015B_CNV v.3
HEF4015B_CNV v.2
20091103
20090624
20090127
19950101
19950101
Product data sheet
Product data sheet
Product data sheet
Product specification
Product specification
-
-
-
-
-
HEF4015B v.5
HEF4015B v.4
HEF4015B_CNV v.3
HEF4015B_CNV v.2
-
HEF4015B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
12 of 15
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
authorized or warranted to be suitable for use in life support, life-critical or
15.2 Definitions
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer's own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
HEF4015B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
13 of 15
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4015B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
14 of 15
HEF4015B
NXP Semiconductors
Dual 4-bit static shift register
17. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 September 2011
Document identifier: HEF4015B
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