HEF40161B [NXP]
4-bit synchronous binary counter with asynchronous reset; 与异步复位4位同步二进制计数器
| 型号： | HEF40161B |
| 厂家： | 
NXP |
| 描述： | 4-bit synchronous binary counter with asynchronous reset |
| 文件： | 总10页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40161B
MSI
4-bit synchronous binary counter
with asynchronous reset
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
4-bit synchronous binary counter with
asynchronous reset
HEF40161B
MSI
When PE is HIGH, the next LOW to HIGH transition of CP
advances the counter to its next state only if both CEP and
CET are HIGH; otherwise, no change occurs in the state
of the counter. TC is HIGH when the state of the counter is
15 (O1 to O3 = HIGH) and when CET is HIGH. A LOW on
MR sets all outputs (O0 to O3 and TC) LOW, independent
of the state of all other inputs. Multistage synchronous
counting is possible without additional components by
using a carry look-ahead counting technique; in this case,
TC is used to enable successive cascaded stages. CEP,
CET and PE must be stable only during the set-up time
before the LOW to HIGH transition of CP.
DESCRIPTION
The HEF40161B is a fully synchronous edge-triggered
4-bit binary counter with a clock input (CP), an overriding
asynchronous master reset (MR), four parallel data inputs
(P0 to P3), three synchronous mode control inputs (parallel
enable (PE), count enable parallel (CEP) and count enable
trickle (CET)), buffered outputs from all four bit positions
(O0 to O3) and a terminal count output (TC).
Operation is fully synchronous (except for the MR input)
and occurs on the LOW to HIGH transition of CP. When
PE is LOW, the next LOW to HIGH transition of CP loads
data into the counter from P0 to P3 regardless of the levels
of CEP and CET inputs.
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
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Fig.2 Logic diagram.
Philips Semiconductors
Product specification
4-bit synchronous binary counter with
asynchronous reset
HEF40161B
MSI
PINNING
PE
parallel enable input
parallel data inputs
P0 to P3
CEP
CET
CP
count enable parallel input
count enable trickle input
clock input (LOW to HIGH, edge-triggered)
master reset input (active LOW)
MR
O0 to O3 parallel outputs
TC
terminal count output
Fig.3 Pinning diagram.
HEF40161BP(N): 16-lead DIL; plastic (SOT38-1)
HEF40161BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF40161BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
SYNCHRONOUS MODE SELECTION
TERMINAL COUNT GENERATION
PE
CEP
CET
MODE
CET
(O0 O1 O2 O3)
TC
L
H
H
H
X
L
X
X
L
preset
L
L
L
H
L
L
L
no change
no change
count
X
H
H
H
L
H
H
H
Notes
Note
1. TC = CET . O0 . O1 . O2 . O3
1. MR = HIGH
2. H = HIGH state (the more positive voltage)
3. L = LOW state (the less positive voltage)
4. X = state is immaterial
Fig.4 State diagram.
January 1995
4
Philips Semiconductors
Product specification
4-bit synchronous binary counter with
asynchronous reset
HEF40161B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
2
2
Dynamic power
5
10
15
1 200 fi + ∑ (foCL) × VDD
5 600 fi + ∑ (foCL) × VDD
16 000 fi + ∑ (foCL) × VDD
where
dissipation per
package (P)
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
Propagation delays
CP → On
5
110
45
220
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
83 ns + (0,55 ns/pF) CL
34 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
88 ns + (0,55 ns/pF) CL
34 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
103 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
113 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
78 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
63 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
93 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
118 ns + (0,55 ns/pF) CL
49 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
HIGH to LOW
10
15
5
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
30
60
115
45
230
95
LOW to HIGH
10
15
5
35
65
CP → TC
130
55
260
105
75
HIGH to LOW
10
15
5
35
140
55
280
115
80
LOW to HIGH
10
15
5
40
CET → TC
105
50
210
100
75
HIGH to LOW
10
15
5
35
90
185
70
LOW to HIGH
10
15
5
35
25
50
MR → On
120
50
245
100
70
HIGH to LOW
10
15
5
35
MR → TC
145
60
295
120
85
HIGH to LOW
10
15
45
January 1995
5
Philips Semiconductors
Product specification
4-bit synchronous binary counter with
asynchronous reset
HEF40161B
MSI
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
Output transition times
HIGH to LOW
5
60
30
20
60
30
20
120
60
ns
ns
ns
ns
ns
ns
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10
15
5
tTHL
40
120
60
LOW to HIGH
10
15
tTLH
40
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL MIN. TYP. MAX.
Minimum clock
5
10
15
5
100
40
30
100
40
30
25
15
10
110
40
30
120
40
25
260
100
70
20
10
5
50
20
ns
pulse width; LOW
tWCPL
tWMRL
tRMR
tsu
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
Minimum MR
50
pulse width; LOW
10
15
5
20
15
Recovery time
for MR
0
10
15
5
0
0
Set-up times
55
Pn → CP
10
15
5
20
15
60
see also waveforms
Figs 5, 6, 7 and 8
PE → CP
10
15
5
tsu
20
10
130
50
CEP, CET → CP
10
15
5
tsu
35
Hold times
−35
−10
−10
−45
−15
−10
−105
−35
−25
Pn → CP
10
15
5
thold
thold
thold
15
5
PE → CP
10
15
5
5
25
15
10
CEP, CET → CP
10
15
January 1995
6
Philips Semiconductors
Product specification
4-bit synchronous binary counter with
asynchronous reset
HEF40161B
MSI
VDD
V
SYMBOL MIN. TYP. MAX.
Maximum clock
pulse frequency
5
10
15
2,5
7
5
14
18
MHz
MHz
MHz
fmax
9
Conditions
PE = LOW
P0 to P3 = HIGH
Fig.5 Waveforms showing
minimum CP and MR pulse
widths and MR to CP
recovery time.
Condition: PE = MR = HIGH.
Fig.6 Waveforms
showing
set-up times
and hold
times for CEP
and CET
inputs.
January 1995
7
Philips Semiconductors
Product specification
4-bit synchronous binary counter with
asynchronous reset
HEF40161B
MSI
Conditions
PE = LOW
MR = HIGH
Fig.7 Waveforms showing set-up times and hold times for Pn inputs.
Condition
MR = HIGH
Fig.8 Waveforms showing set-up times and hold times for PE input.
Note
Set-up and hold times are shown as positive values but may be specified as negative values.
January 1995
8
Philips Semiconductors
Product specification
4-bit synchronous binary counter with
asynchronous reset
HEF40161B
MSI
Fig.9 Timing diagram.
APPLICATION INFORMATION
An example of an application for the HEF40161B is:
• Programmable binary counter.
January 1995
9
Philips Semiconductors
Product specification
4-bit synchronous binary counter with
asynchronous reset
HEF40161B
MSI
NOTE
On the TC outputs, glitches can
occur during counting. In totally
synchronous mode they will not
have any adverse affect.
However the TC output in
asynchronous mode can cause
problems.
Fig.10 Synchronous multi-stage counting scheme.
January 1995
10
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