HEF40194BDB [NXP]
IC 4000/14000/40000 SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, Shift Register;
| 型号： | HEF40194BDB |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, Shift Register 移位寄存器 |
| 文件： | 总8页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40194B
MSI
4-bit bidirectional universal shift
register
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF40194B
MSI
4-bit bidirectional universal shift register
Serial and parallel operation are edge-triggered on the
LOW to HIGH transition of CP. The inputs at which the
data are to be entered and S0, S1 must be stable for a
set-up time before the LOW to HIGH transition of CP.
DESCRIPTION
The HEF40194B is a 4-bit bidirectional shift register with
two mode control inputs (S0 and S1), a clock input (CP), a
serial data shift left input (DSL), a serial data shift right input
(DSR), four parallel data inputs (P0 to P3), an overriding
asynchronous master reset input (MR), and four buffered
parallel outputs (O0 to O3). When LOW, MR resets all
stages and forces O0 to O3 LOW, overriding all other input
conditions. When MR is HIGH, the operation mode is
controlled by S0 and S1 as shown in the function table.
Fig.2 Pinning diagram.
HEF40194BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF40194BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40194BT(D): 16-lead SO; plastic
(SOT109-1)
Fig.1 Functional diagram.
( ): Package Designator North America
PINNING
FAMILY DATA, IDD LIMITS category MSI
S0, S1
P0 to P3
DSR
mode control inputs
See Family Specifications
parallel data inputs
serial data shift right input
serial data shift left input
clock input (LOW to HIGH edge-triggered)
master reset input (active LOW)
buffered parallel outputs
DSL
CP
MR
O0 to O3
January 1995
2
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Fig.3 Logic diagram.
Philips Semiconductors
Product specification
HEF40194B
MSI
4-bit bidirectional universal shift register
FUNCTION TABLE
INPUTS (MR = HIGH)
OUTPUTS AT Tn + 1
OPERATING MODE
S1
S0
DSR
DSL
P0 TO P3
O0
O1
O2
O3
hold
L
H
H
L
L
L
X
X
X
L
X
L
X
X
X
X
X
L
O0
O1
O1
L
O1
O2
O2
O0
O0
L
O2
O3
O3
O1
O1
L
O3
L
shift left
L
H
X
X
X
X
H
H
H
H
H
O2
O2
L
shift right
L
H
X
X
H
H
H
L
parallel load
H
H
H
H
H
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
4. tn + 1 = state after next LOW to HIGH transition of CP
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
1 500 fi + ∑ (foCL) × VDD
where
2
6 900 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
18 900 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
HEF40194B
MSI
4-bit bidirectional universal shift register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
TYPICALEXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
V
Propagation delays
CP → On
5
10
15
5
100
40
30
80
35
25
85
40
30
60
30
20
60
30
20
205
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
73 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
53 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
58 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
HIGH to LOW
tPHL
tPLH
tPHL
tTHL
tTLH
60
165
70
LOW to HIGH
10
15
5
55
MR → On
175
80
HIGH to LOW
10
15
5
60
Output transition times
HIGH to LOW
120
60
10
15
5
40
120
60
LOW to HIGH
10
15
40
January 1995
5
Philips Semiconductors
Product specification
HEF40194B
MSI
4-bit bidirectional universal shift register
VDD
V
TYPICALEXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
Set-up times
5
80
30
20
140
60
40
10
5
40
15
10
70
30
20
−30
−10
−5
−45
−15
−10
25
10
10
40
20
15
10
5
ns
Pn, DSR, DSL → CP
10
15
5
tsu
ns
ns
ns
Sn → CP
10
15
5
tsu
ns
ns
Hold times
ns
Pn, DSR, DSL → CP
10
15
5
thold
thold
tWCPL
tWMRL
tRMR
fmax
ns
5
ns
25
15
10
50
20
20
80
40
30
30
15
15
6
ns
Sn → CP
10
15
5
ns
ns
see also waveforms
Figs 4 and 5
Minimum clock
ns
pulse width; LOW
10
15
5
ns
ns
Minimum MR
ns
pulse width; LOW
10
15
5
ns
ns
Recovery time
for MR
ns
10
15
5
ns
5
ns
Maximum clock
pulse frequency
12
30
40
MHz
MHz
MHz
10
15
15
20
January 1995
6
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Fig.4 Waveforms showing set-up times, hold times for DSR, DSL and Pn inputs; minimum MR pulse width, MR to output delays and MR to CP
recovery time; minimum CP pulse width and CP to output delays. Set-up and hold times are shown as positive values but may be
specified as negative values.
Philips Semiconductors
Product specification
HEF40194B
MSI
4-bit bidirectional universal shift register
Fig.5 Waveforms showing set-up times and hold times for S0 and S1 inputs. Set-up and hold times are shown
as positive values but may be specified as negative values.
APPLICATION INFORMATION
Some examples of applications for the HEF40194B are:
• Arithmetic unit register
• Serial/parallel converter.
January 1995
8
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